From efe2103f9b28458a1615ff096054479743ade236 Mon Sep 17 00:00:00 2001 From: graham sanderson Date: Thu, 8 Aug 2024 06:02:04 -0500 Subject: [PATCH] SDK 2.0.0 release --- .bazelignore | 4 + .bazelrc | 4 + .bazelversion | 2 +- .gitignore | 2 + CMakeLists.txt | 8 + MODULE.bazel | 101 +- README.md | 47 +- WORKSPACE | 0 bazel/BUILD.bazel | 6 + bazel/README.md | 45 +- bazel/config/BUILD.bazel | 130 +- bazel/constraint/BUILD.bazel | 113 +- bazel/generate_version_header.py | 2 +- bazel/platform/BUILD.bazel | 10 +- bazel/toolchain/BUILD.bazel | 140 +- bazel/toolchain/clang.BUILD | 170 + bazel/util/transition.bzl | 20 + {src/boards => cmake}/generic_board.cmake | 21 +- cmake/pico_pre_load_platform.cmake | 138 +- cmake/pico_pre_load_toolchain.cmake | 69 +- cmake/preload/platforms/combined-docs.cmake | 3 + cmake/preload/platforms/pico/pico.cmake | 7 - cmake/preload/platforms/rp2040.cmake | 3 +- cmake/preload/platforms/rp2350-arm-s.cmake | 3 + cmake/preload/platforms/rp2350-riscv.cmake | 3 + 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tools/pioasm/ada_output.cpp | 2 +- tools/pioasm/c_sdk_output.cpp | 44 +- tools/pioasm/cmake/pioasmConfig.cmake | 3 + tools/pioasm/gen/lexer.cpp | 905 +- tools/pioasm/gen/location.h | 8 +- tools/pioasm/gen/parser.cpp | 973 +- tools/pioasm/gen/parser.hpp | 970 +- tools/pioasm/lexer.ll | 42 +- tools/pioasm/main.cpp | 13 + tools/pioasm/output_format.h | 19 + tools/pioasm/parser.yy | 115 +- tools/pioasm/pio_assembler.cpp | 193 +- tools/pioasm/pio_assembler.h | 31 +- tools/pioasm/pio_disassembler.cpp | 57 +- tools/pioasm/pio_disassembler.h | 5 +- tools/pioasm/pio_enums.h | 21 + tools/pioasm/pio_types.h | 191 +- tools/pioasm/python_output.cpp | 14 +- tools/pioasm/test/amethyst.pio | 46 + tools/run_all_bazel_checks.py | 55 + tools/uf2_aspect.bzl | 12 +- 933 files changed, 349994 insertions(+), 66341 deletions(-) create mode 100644 .bazelignore create mode 100644 WORKSPACE create mode 100644 bazel/toolchain/clang.BUILD rename {src/boards => cmake}/generic_board.cmake (51%) create mode 100644 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src/rp2_common/pico_platform_sections/include/pico/platform/sections.h rename src/rp2_common/{pico_stdio => pico_printf}/LICENSE (100%) create mode 100644 src/rp2_common/pico_runtime_init/BUILD.bazel create mode 100644 src/rp2_common/pico_runtime_init/CMakeLists.txt create mode 100644 src/rp2_common/pico_runtime_init/include/pico/runtime_init.h create mode 100644 src/rp2_common/pico_runtime_init/runtime_init.c create mode 100644 src/rp2_common/pico_runtime_init/runtime_init_clocks.c create mode 100644 src/rp2_common/pico_runtime_init/runtime_init_stack_guard.c create mode 100644 src/rp2_common/pico_sha256/BUILD.bazel create mode 100644 src/rp2_common/pico_sha256/CMakeLists.txt create mode 100644 src/rp2_common/pico_sha256/include/pico/sha256.h create mode 100644 src/rp2_common/pico_sha256/sha256.c create mode 100644 src/rp2_common/pico_standard_binary_info/BUILD.bazel create mode 100644 src/rp2_common/pico_standard_binary_info/CMakeLists.txt create mode 100644 src/rp2_common/pico_standard_binary_info/doc.h rename src/rp2_common/{pico_standard_link/binary_info.c => pico_standard_binary_info/standard_binary_info.c} (74%) create mode 100644 src/rp2_common/pico_standard_link/pico_flash_region.bzl create mode 100644 src/rp2_common/pico_standard_link/pico_flash_region.template.ld create mode 100644 src/rp2_common/pico_stdio_rtt/BUILD.bazel create mode 100644 src/rp2_common/pico_time_adapter/BUILD.bazel create mode 100644 src/rp2_common/pico_time_adapter/CMakeLists.txt create mode 100644 src/rp2_common/pico_time_adapter/include/pico/time_adapter.h create mode 100644 src/rp2_common/tinyusb/include/bsp/board.h create mode 100644 test/hardware_sync_spin_lock_test/BUILD.bazel create mode 100644 test/hardware_sync_spin_lock_test/CMakeLists.txt create mode 100644 test/hardware_sync_spin_lock_test/hardware_sync_spin_lock_test.c create mode 100644 test/pico_float_test/m33.c create mode 100644 test/pico_sha256_test/BUILD.bazel create mode 100644 test/pico_sha256_test/CMakeLists.txt create mode 100644 test/pico_sha256_test/pico_sha256_test.c create mode 100644 test/pico_test/include/pico/test/xrand.h delete mode 100644 tools/FindELF2UF2.cmake delete mode 100644 tools/FindPioasm.cmake create mode 100644 tools/Findpicotool.cmake create mode 100644 tools/Findpioasm.cmake create mode 100755 tools/bazel_build.py create mode 100644 tools/bazel_common.py create mode 100755 tools/check_source_files_in_bazel_build.py mode change 100644 => 100755 tools/compare_build_systems.py create mode 100644 tools/copro_dis.py delete mode 100644 tools/elf2uf2/BUILD.bazel delete mode 100644 tools/elf2uf2/CMakeLists.txt delete mode 100644 tools/elf2uf2/elf.h delete mode 100644 tools/elf2uf2/main.cpp create mode 100644 tools/pioasm/cmake/pioasmConfig.cmake create mode 100644 tools/pioasm/pio_enums.h create mode 100644 tools/pioasm/test/amethyst.pio create mode 100755 tools/run_all_bazel_checks.py diff --git a/.bazelignore b/.bazelignore new file mode 100644 index 000000000..a086fff4b --- /dev/null +++ b/.bazelignore @@ -0,0 +1,4 @@ +# Don't accidentally pick up external CMake deps with Bazel build files. +build +# Don't treat submodules as part of this project. +lib diff --git a/.bazelrc b/.bazelrc index b5ebd97a9..a94ccd3de 100644 --- a/.bazelrc +++ b/.bazelrc @@ -2,5 +2,9 @@ build --incompatible_enable_cc_toolchain_resolution build --@rules_cc//cc/toolchains:experimental_enable_rule_based_toolchains +# Silence all C/C++ warnings in external code. +common --per_file_copt=external/.*@-w +common --host_per_file_copt=external/.*@-w + # Produce useful output when the build fails. common --verbose_failures diff --git a/.bazelversion b/.bazelversion index a8907c025..b26a34e47 100644 --- a/.bazelversion +++ b/.bazelversion @@ -1 +1 @@ -7.0.2 +7.2.1 diff --git a/.gitignore b/.gitignore index c01419576..a893fc633 100644 --- a/.gitignore +++ b/.gitignore @@ -3,8 +3,10 @@ cmake-* .DS_Store build +build-* bazel-* # Ignore until https://github.com/bazelbuild/bazel/issues/20369 is fixed. MODULE.bazel.lock +__pycache__/ diff --git a/CMakeLists.txt b/CMakeLists.txt index a622f05e7..2ecb515e5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -15,6 +15,11 @@ if (NOT TARGET _pico_sdk_inclusion_marker) pico_register_common_scope_var(PICO_C_COMPILER_IS_CLANG) pico_register_common_scope_var(PICO_C_COMPILER_IS_GNU) pico_register_common_scope_var(PICO_C_COMPILER_IS_IAR) + pico_register_common_scope_var(PICO_SDK_VERSION_MAJOR) + pico_register_common_scope_var(PICO_SDK_VERSION_MINOR) + pico_register_common_scope_var(PICO_SDK_VERSION_REVISION) + pico_register_common_scope_var(PICO_SDK_VERSION_PRE_RELEASE_ID) + pico_register_common_scope_var(PICO_SDK_VERSION_STRING) message("Build type is ${CMAKE_BUILD_TYPE}") if ("${CMAKE_BUILD_TYPE}" STREQUAL "Debug") @@ -38,6 +43,9 @@ if (NOT TARGET _pico_sdk_inclusion_marker) add_sub_list_dirs(PICO_SDK_PRE_LIST_DIRS) add_sub_list_files(PICO_SDK_PRE_LIST_FILES) + # needed by certain functions + set(PICO_TOOLS_DIR "${CMAKE_CURRENT_LIST_DIR}/tools" CACHE INTERNAL "") + add_subdirectory(tools) add_subdirectory(src) diff --git a/MODULE.bazel b/MODULE.bazel index 883fad7dc..2094c3b8e 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -1,8 +1,12 @@ -module(name = "pico-sdk", version = "1.6.0-rc1") - -bazel_dep(name = "platforms", version = "0.0.8") +module( + name = "pico-sdk", + version = "2.0.0", +) +bazel_dep(name = "platforms", version = "0.0.9") bazel_dep(name = "bazel_skylib", version = "1.6.1") +bazel_dep(name = "rules_python", version = "0.22.1") +bazel_dep(name = "picotool", version = "2.0.0") # Note: rules_cc is special-cased repository; a dependency on rules_cc in a # module will not ensure that the root Bazel module has that same version of @@ -15,84 +19,123 @@ bazel_dep(name = "rules_cc", version = "0.0.9") # project's MODULE.bazel too. archive_override( module_name = "rules_cc", - urls = "https://github.com/bazelbuild/rules_cc/archive/1acf5213b6170f1f0133e273cb85ede0e732048f.zip", + integrity = "sha256-zdQo/pQWKdIAPKSflBxOSWZNwCbc86T7SechKZo/3Xw=", strip_prefix = "rules_cc-1acf5213b6170f1f0133e273cb85ede0e732048f", - integrity = "sha256-NddP6xi6LzsIHT8bMSVJ2NtoURbN+l3xpjvmIgB6aSg=", + urls = "https://github.com/bazelbuild/rules_cc/archive/1acf5213b6170f1f0133e273cb85ede0e732048f.tar.gz", ) http_archive = use_repo_rule("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") http_archive( name = "arm_gcc_linux-x86_64", - url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-x86_64-arm-none-eabi.tar.xz", - strip_prefix = "arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi", build_file = "//bazel/toolchain:gcc_arm_none_eabi.BUILD", sha256 = "6cd1bbc1d9ae57312bcd169ae283153a9572bd6a8e4eeae2fedfbc33b115fdbb", + strip_prefix = "arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi", + url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-x86_64-arm-none-eabi.tar.xz", ) http_archive( name = "arm_gcc_win-x86_64", - url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-mingw-w64-i686-arm-none-eabi.zip", - strip_prefix = "arm-gnu-toolchain-13.2.Rel1-mingw-w64-i686-arm-none-eabi", build_file = "//bazel/toolchain:gcc_arm_none_eabi.BUILD", sha256 = "51d933f00578aa28016c5e3c84f94403274ea7915539f8e56c13e2196437d18f", + strip_prefix = "arm-gnu-toolchain-13.2.Rel1-mingw-w64-i686-arm-none-eabi", + url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-mingw-w64-i686-arm-none-eabi.zip", ) http_archive( name = "arm_gcc_mac-x86_64", - url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-darwin-x86_64-arm-none-eabi.tar.xz", - strip_prefix = "arm-gnu-toolchain-13.2.Rel1-darwin-x86_64-arm-none-eabi", build_file = "//bazel/toolchain:gcc_arm_none_eabi.BUILD", sha256 = "075faa4f3e8eb45e59144858202351a28706f54a6ec17eedd88c9fb9412372cc", + strip_prefix = "arm-gnu-toolchain-13.2.Rel1-darwin-x86_64-arm-none-eabi", + url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-darwin-x86_64-arm-none-eabi.tar.xz", ) http_archive( name = "arm_gcc_mac-aarch64", - url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-darwin-arm64-arm-none-eabi.tar.xz", - strip_prefix = "arm-gnu-toolchain-13.2.Rel1-darwin-arm64-arm-none-eabi", build_file = "//bazel/toolchain:gcc_arm_none_eabi.BUILD", sha256 = "39c44f8af42695b7b871df42e346c09fee670ea8dfc11f17083e296ea2b0d279", + strip_prefix = "arm-gnu-toolchain-13.2.Rel1-darwin-arm64-arm-none-eabi", + url = "https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-darwin-arm64-arm-none-eabi.tar.xz", +) + +http_archive( + name = "clang_linux-x86_64", + build_file = "//bazel/toolchain:clang.BUILD", + sha256 = "e12ee0db9226f5b4a4400c5eb2c0f757d7056181b651622b5453acb00105fd87", + type = "zip", + url = "https://chrome-infra-packages.appspot.com/dl/fuchsia/third_party/clang/linux-amd64/+/git_revision:248c53429427034f45705af60d47f3b1090c4799", +) + +http_archive( + name = "clang_win-x86_64", + build_file = "//bazel/toolchain:clang.BUILD", + sha256 = "8c41e8b507f4dfede80842f98a716cac209f552064088fa1b7f4c64a1e547534", + type = "zip", + # Windows doesn't like `:` in the produced filename, so replace it with `%3A`. + url = "https://chrome-infra-packages.appspot.com/dl/fuchsia/third_party/clang/windows-amd64/+/git_revision:248c53429427034f45705af60d47f3b1090c4799".replace("git_revision:", "git_revision%3A"), +) + +http_archive( + name = "clang_mac-x86_64", + build_file = "//bazel/toolchain:clang.BUILD", + sha256 = "1d92f52609d3c1e958fd56f5e9a68ab99b2042ddcc6e90a5eb5009cf7ac4897d", + type = "zip", + url = "https://chrome-infra-packages.appspot.com/dl/fuchsia/third_party/clang/mac-amd64/+/git_revision:248c53429427034f45705af60d47f3b1090c4799", +) + +http_archive( + name = "clang_mac-aarch64", + build_file = "//bazel/toolchain:clang.BUILD", + sha256 = "53184680db7e0043a8fba1556c7644b8f5e6c8cdffa4436a92a8e8adb0f45b8d", + type = "zip", + url = "https://chrome-infra-packages.appspot.com/dl/fuchsia/third_party/clang/mac-arm64/+/git_revision:248c53429427034f45705af60d47f3b1090c4799", ) # TODO: Provide tinyusb as a proper Bazel module. http_archive( name = "tinyusb", - url = "https://github.com/hathach/tinyusb/archive/86c416d4c0fb38432460b3e11b08b9de76941bf5.zip", - strip_prefix = "tinyusb-86c416d4c0fb38432460b3e11b08b9de76941bf5", build_file = "//src/rp2_common/tinyusb:tinyusb.BUILD", - sha256 = "ac57109bba00d26ffa33312d5f334990ec9a9a4d82bf890ed8b825b4610d1da2", + sha256 = "d64728aef58b80d5ce3747cad133f520da46e2b7ea3aadfda0e981aba6b658b3", + strip_prefix = "tinyusb-4232642899362fa5e9cf0dc59bad6f1f6d32c563", + url = "https://github.com/hathach/tinyusb/archive/4232642899362fa5e9cf0dc59bad6f1f6d32c563.tar.gz", ) # TODO: Provide btstack as a proper Bazel module. http_archive( name = "btstack", - url = "https://github.com/bluekitchen/btstack/archive/72ef1732c954d938091467961e41f4aa9b976b34.zip", - strip_prefix = "btstack-72ef1732c954d938091467961e41f4aa9b976b34", build_file = "//src/rp2_common/pico_btstack:btstack.BUILD", - sha256 = "f45d72b5d404dd2f8e311287de6f2ba3561fc8ae956737eeb611b277aadc2391", + sha256 = "64e86d9cf82b346e743fe1d4818b9380712b17abdb3f2c3524e92464b5ef3d19", + strip_prefix = "btstack-2b49e57bd1fae85ac32ac1f41cdb7c794de335f6", + url = "https://github.com/bluekitchen/btstack/archive/2b49e57bd1fae85ac32ac1f41cdb7c794de335f6.tar.gz", ) # TODO: Provide btstack as a proper Bazel module. http_archive( name = "cyw43-driver", - url = "https://github.com/georgerobotics/cyw43-driver/archive/8ef38a6d32c54f850bff8f189bdca19ded33792a.zip", - strip_prefix = "cyw43-driver-8ef38a6d32c54f850bff8f189bdca19ded33792a", build_file = "//src/rp2_common/pico_cyw43_driver:cyw43-driver.BUILD", - sha256 = "0b44a19ea58537ee954357606cde5ed20c3a42be77adfebb07b7c0e4740f6228", + sha256 = "0fcc7707fef95dd562d5572604713266613a27caeeae2f10afeccee9592a53ce", + strip_prefix = "cyw43-driver-faf36381bad1f668a30172b6336c9a970966ef4c", + url = "https://github.com/georgerobotics/cyw43-driver/archive/faf36381bad1f668a30172b6336c9a970966ef4c.tar.gz", ) # TODO: Provide lwip as a proper Bazel module. http_archive( name = "lwip", - url = "https://github.com/lwip-tcpip/lwip/archive/239918ccc173cb2c2a62f41a40fd893f57faf1d6.zip", - strip_prefix = "lwip-239918ccc173cb2c2a62f41a40fd893f57faf1d6", build_file = "//src/rp2_common/pico_lwip:lwip.BUILD", - sha256 = "7ee9e02f2719c0422377e1fcce5a21716ca2e2e855cca56695f9ef7cb020e5dd", + sha256 = "72856d557f72911cf6826ef745c23c54822df83a474557823241164a1d1361aa", + strip_prefix = "lwip-0a0452b2c39bdd91e252aef045c115f88f6ca773", + url = "https://github.com/lwip-tcpip/lwip/archive/0a0452b2c39bdd91e252aef045c115f88f6ca773.tar.gz", ) register_toolchains( - "//bazel/toolchain:arm_gcc_linux-x86_64", - "//bazel/toolchain:arm_gcc_win-x86_64", - "//bazel/toolchain:arm_gcc_mac-x86_64", - "//bazel/toolchain:arm_gcc_mac-aarch64", + "//bazel/toolchain:linux-x86_64-rp2040", + "//bazel/toolchain:linux-x86_64-rp2350", + "//bazel/toolchain:win-x86_64-rp2040", + "//bazel/toolchain:win-x86_64-rp2350", + "//bazel/toolchain:mac-x86_64-rp2040", + "//bazel/toolchain:mac-x86_64-rp2350", + "//bazel/toolchain:mac-aarch64-rp2040", + "//bazel/toolchain:mac-aarch64-rp2350", + # Require users to opt-in to the Pico SDK's toolchains. + dev_dependency = True, ) diff --git a/README.md b/README.md index 6388cf7f9..6129a007f 100644 --- a/README.md +++ b/README.md @@ -1,31 +1,31 @@ # Raspberry Pi Pico SDK The Raspberry Pi Pico SDK (henceforth the SDK) provides the headers, libraries and build system -necessary to write programs for the RP2040-based devices such as the Raspberry Pi Pico +necessary to write programs for the RP-series microcontroller-based devices such as the Raspberry Pi Pico or Raspberry Pi Pico 2 in C, C++ or assembly language. The SDK is designed to provide an API and programming environment that is familiar both to non-embedded C developers and embedded C developers alike. A single program runs on the device at a time and starts with a conventional `main()` method. Standard C/C++ libraries are supported along with -C level libraries/APIs for accessing all of the RP2040's hardware include PIO (Programmable IO). +C-level libraries/APIs for accessing all of the RP-series microcontroller's hardware including PIO (Programmable IO). -Additionally the SDK provides higher level libraries for dealing with timers, synchronization, USB (TinyUSB) and multi-core programming -along with various utilities. +Additionally, the SDK provides higher level libraries for dealing with timers, synchronization, Wi-Fi and Bluetooth networking, USB and multicore programming. These libraries should be comprehensive enough that your application code rarely, if at all, needs to access hardware registers directly. However, if you do need or prefer to access the raw hardware registers, you will also find complete and fully-commented register definition headers in the SDK. There's no need to look up addresses in the datasheet. -The SDK can be used to build anything from simple applications, to fully fledged runtime environments such as MicroPython, to low level software -such as RP2040's on-chip bootrom itself. +The SDK can be used to build anything from simple applications, fully-fledged runtime environments such as MicroPython, to low level software +such as the RP-series microcontroller's on-chip bootrom itself. + +The design goal for entire SDK is to be simple but powerful. Additional libraries/APIs that are not yet ready for inclusion in the SDK can be found in [pico-extras](https://github.com/raspberrypi/pico-extras). # Documentation -See [Getting Started with the Raspberry Pi Pico](https://rptl.io/pico-get-started) for information on how to setup your -hardware, IDE/environment and for how to build and debug software for the Raspberry Pi Pico -and other RP2040-based devices. +See [Getting Started with the Raspberry Pi Pico-Series](https://rptl.io/pico-get-started) for information on how to setup your +hardware, IDE/environment and how to build and debug software for the Raspberry Pi Pico and other RP-series microcontroller based devices. See [Connecting to the Internet with Raspberry Pi Pico W](https://rptl.io/picow-connect) to learn more about writing applications for your Raspberry Pi Pico W that connect to the internet. -See [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk) to learn more about programming using the +See [Raspberry Pi Pico-Series C/C++ SDK](https://rptl.io/pico-c-sdk) to learn more about programming using the SDK, to explore more advanced features, and for complete PDF-based API documentation. See [Online Raspberry Pi Pico SDK API docs](https://rptl.io/pico-doxygen) for HTML-based API documentation. @@ -42,10 +42,16 @@ _latest stable release_ of the SDK. If you need or want to test upcoming feature # Quick-start your own project +## Using Visual Studio Code + +You can install the [Raspberry Pi Pico Visual Studio Code extension](https://marketplace.visualstudio.com/items?itemName=raspberry-pi.raspberry-pi-pico) in VS Code. + +## Unix command line + These instructions are extremely terse, and Linux-based only. For detailed steps, -instructions for other platforms, and just in general, we recommend you see [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk) +instructions for other platforms, and just in general, we recommend you see [Raspberry Pi Pico-Series C/C++ SDK](https://rptl.io/pico-c-sdk) -1. Install CMake (at least version 3.13), and GCC cross compiler +1. Install CMake (at least version 3.13), and a GCC cross compiler ``` sudo apt install cmake gcc-arm-none-eabi libnewlib-arm-none-eabi libstdc++-arm-none-eabi-newlib ``` @@ -137,7 +143,7 @@ instructions for other platforms, and just in general, we recommend you see [Ras # rest of your project ``` -1. Write your code (see [pico-examples](https://github.com/raspberrypi/pico-examples) or the [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk) documentation for more information) +1. Write your code (see [pico-examples](https://github.com/raspberrypi/pico-examples) or the [Raspberry Pi Pico-Series C/C++ SDK](https://rptl.io/pico-c-sdk) documentation for more information) About the simplest you can do is a single source file (e.g. hello_world.c) @@ -146,7 +152,7 @@ instructions for other platforms, and just in general, we recommend you see [Ras #include "pico/stdlib.h" int main() { - setup_default_uart(); + stdio_init_all(); printf("Hello, world!\n"); return 0; } @@ -176,12 +182,11 @@ instructions for other platforms, and just in general, we recommend you see [Ras $ cmake .. ``` - When building for a board other than the Raspberry Pi Pico, you should pass `-DPICO_BOARD=board_name` to the `cmake` command above, e.g. `cmake -DPICO_BOARD=pico_w ..` - to configure the SDK and build options accordingly for that particular board. + When building for a board other than the Raspberry Pi Pico, you should pass `-DPICO_BOARD=board_name` to the `cmake` command above, e.g. `cmake -DPICO_BOARD=pico2 ..` or `cmake -DPICO_BOARD=pico_w ..` to configure the SDK and build options accordingly for that particular board. - Doing so sets up various compiler defines (e.g. default pin numbers for UART and other hardware) and in certain + Specifying `PICO_BOARD=` sets up various compiler defines (e.g. default pin numbers for UART and other hardware) and in certain cases also enables the use of additional libraries (e.g. wireless support when building for `PICO_BOARD=pico_w`) which cannot - be built without a board which provides the requisite functionality. + be built without a board which provides the requisite hardware functionality. For a list of boards defined in the SDK itself, look in [this directory](src/boards/include/boards) which has a header for each named board. @@ -191,4 +196,8 @@ instructions for other platforms, and just in general, we recommend you see [Ras $ make hello_world ``` -1. You now have `hello_world.elf` to load via a debugger, or `hello_world.uf2` that can be installed and run on your Raspberry Pi Pico via drag and drop. +1. You now have `hello_world.elf` to load via a debugger, or `hello_world.uf2` that can be installed and run on your Raspberry Pi Pico-series device via drag and drop. + +# RISC-V support on RP2350 + +See [Raspberry Pi Pico-series C/C++ SDK](https://rptl.io/pico-c-sdk) for information on setting up a build environment for RISC-V on RP2350. \ No newline at end of file diff --git a/WORKSPACE b/WORKSPACE new file mode 100644 index 000000000..e69de29bb diff --git a/bazel/BUILD.bazel b/bazel/BUILD.bazel index e4ab8f31d..ff093d402 100644 --- a/bazel/BUILD.bazel +++ b/bazel/BUILD.bazel @@ -55,3 +55,9 @@ cc_library( cc_library( name = "empty_cc_lib", ) + +# A library incompatible with everything. Use to mark an invalid configuration. +cc_library( + name = "incompatible_cc_lib", + target_compatible_with = ["@platforms//:incompatible"], +) diff --git a/bazel/README.md b/bazel/README.md index 1db0c930e..6520e7a0f 100644 --- a/bazel/README.md +++ b/bazel/README.md @@ -7,9 +7,10 @@ First, in your `MODULE.bazel` file, add a dependency on the Pico SDK: ```python bazel_dep( name = "pico-sdk", - version = "1.6.0-rc1", + version = "2.0.0", ) ``` + Second, in the same file you'll need to add an explicit dependency on `rules_cc`, as it's a special-cased Bazel module: ```python @@ -35,10 +36,14 @@ These toolchains tell Bazel how to compile for ARM cores. Add the following to the `MODULE.bazel` for your project: ```python register_toolchains( - "@pico-sdk//bazel/toolchain:arm_gcc_linux-x86_64", - "@pico-sdk//bazel/toolchain:arm_gcc_win-x86_64", - "@pico-sdk//bazel/toolchain:arm_gcc_mac-x86_64", - "@pico-sdk//bazel/toolchain:arm_gcc_mac-aarch64", + "@pico-sdk//bazel/toolchain:linux-x86_64-rp2040", + "@pico-sdk//bazel/toolchain:linux-x86_64-rp2350", + "@pico-sdk//bazel/toolchain:win-x86_64-rp2040", + "@pico-sdk//bazel/toolchain:win-x86_64-rp2350", + "@pico-sdk//bazel/toolchain:mac-x86_64-rp2040", + "@pico-sdk//bazel/toolchain:mac-x86_64-rp2350", + "@pico-sdk//bazel/toolchain:mac-aarch64-rp2040", + "@pico-sdk//bazel/toolchain:mac-aarch64-rp2350", ) ``` @@ -82,7 +87,7 @@ rule basis, or through an aspect. Running a wildcard build with the firmware image. ```console -$ bazel build --platforms=@pico-sdk//bazel/platform:rp2040 \ +$ bazelisk build --platforms=@pico-sdk//bazel/platform:rp2040 \ --aspects @pico-sdk//tools:uf2_aspect.bzl%pico_uf2_aspect \ --output_groups=+pico_uf2_files \ //... @@ -97,6 +102,13 @@ launcher) to build the Pico SDK. We strongly recommend you set up [Bazelisk](https://bazel.build/install/bazelisk). +You will also need a working compiler configured if you wish to build Picotool +or pioasm. + +* Linux: `sudo apt-get install build-essential` or similar. +* macOS: `xcode-select --install` +* Windows: [Install MSVC](https://visualstudio.microsoft.com/vs/features/cplusplus/) + ### Building To build all of the Pico SDK, run the following command: ```console @@ -111,6 +123,23 @@ you encounter along the way. Currently, the following features are not supported: -* "None" variants of pico_double, pico_float, and pico_printf are not yet - supported. * The pioasm parser cannot be built from source via Bazel. +* Windows MSVC wildcard build (`bazel build //...`) does not work when targeting + host. +* Bazel does not yet provide RISC-V support for Pico 2/RP2350. +* Pico W wireless libraries have link issues. + +## Contributing +When making changes to the Bazel build, please run the Bazel validation script +to ensure all supported configurations build properly: + +```console +$ ./tools/run_all_bazel_checks.py +``` + +If you need to check against a local version of Picotool, you can run the script +with `--picotool-dir`: + +```console +$ ./tools/run_all_bazel_checks.py --picotool-dir=/path/to/picotool +``` diff --git a/bazel/config/BUILD.bazel b/bazel/config/BUILD.bazel index 50530ecfd..4ab2ccc9b 100644 --- a/bazel/config/BUILD.bazel +++ b/bazel/config/BUILD.bazel @@ -2,7 +2,17 @@ load("@bazel_skylib//rules:common_settings.bzl", "bool_flag", "int_flag", "strin package(default_visibility = ["//visibility:public"]) -# PICO_BAZEL_CONFIG: PICO_BOARD, The board name being built for, type=string, default=pico, group=build +# PICO_BAZEL_CONFIG: PICO_TOOLCHAIN, The toolchain to use, type=string, default=gcc, group=build +string_flag( + name = "PICO_TOOLCHAIN", + build_setting_default = "gcc", + values = [ + "gcc", + "clang", + ], +) + +# PICO_BAZEL_CONFIG: PICO_BOARD, Board name being built for, type=string, default=pico or pico2, group=build, docref=cmake-platform-board-config string_flag( name = "PICO_BOARD", build_setting_default = "pico", @@ -14,7 +24,7 @@ bool_flag( build_setting_default = False, ) -# PICO_BAZEL_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link +# PICO_BAZEL_CONFIG: PICO_NO_GC_SECTIONS, Disable `-ffunction-sections` `-fdata-sections` and `--gc-sections`, type=bool, default=0, advanced=true, group=pico_standard_link bool_flag( name = "PICO_NO_GC_SECTIONS", build_setting_default = False, @@ -23,57 +33,124 @@ bool_flag( # PICO_BAZEL_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Boot stage 2 file to use; this should point to a filegroup with the .S file to use, type=string, group=build label_flag( name = "PICO_DEFAULT_BOOT_STAGE2_FILE", - build_setting_default = "//src/rp2_common/boot_stage2:build_selected_boot2", + build_setting_default = "//src/rp2_common:build_selected_boot2", ) -# PICO_BAZEL_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the file is src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, type=string, default=compile_time_choice, group=build +# PICO_BAZEL_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the latter is set to src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, type=string, default=compile_time_choice, group=build string_flag( name = "PICO_DEFAULT_BOOT_STAGE2", build_setting_default = "compile_time_choice", ) -# PICO_BAZEL_CONFIG: PICO_BOOT_STAGE2_LINK_IMAGE, [Bazel only] The final boot_stage2 image target to link in. Use this to fully override/replace boot_stage2, default=@pico-sdk//src/rp2_common/boot_stage2:boot_stage2, group=build +# PICO_BAZEL_CONFIG: PICO_BOOT_STAGE2_LINK_IMAGE, [Bazel only] The final boot_stage2 image target to link in. Use this to fully override/replace boot_stage2, default=@pico-sdk//src/rp2_common:boot_stage2, group=build label_flag( name = "PICO_BOOT_STAGE2_LINK_IMAGE", - build_setting_default = "//src/rp2_common/boot_stage2:boot_stage2", + build_setting_default = "//src/rp2_common:boot_stage2", ) -# PICO_BAZEL_CONFIG: PICO_CXX_ENABLE_EXCEPTIONS, Enabled CXX exception handling, type=bool, default=0, group=pico_cxx_options +# PICO_BAZEL_CONFIG: PICO_CXX_ENABLE_EXCEPTIONS, Enable CXX exception handling, type=bool, default=0, group=pico_cxx_options bool_flag( name = "PICO_CXX_ENABLE_EXCEPTIONS", build_setting_default = False, ) -# PICO_BAZEL_CONFIG: PICO_CXX_ENABLE_RTTI, Enabled CXX rtti, type=bool, default=0, group=pico_cxx_options +# PICO_BAZEL_CONFIG: PICO_CXX_ENABLE_RTTI, Enable CXX rtti, type=bool, default=0, group=pico_cxx_options bool_flag( name = "PICO_CXX_ENABLE_RTTI", build_setting_default = False, ) -# PICO_BAZEL_CONFIG: PICO_CXX_ENABLE_CXA_ATEXIT, Enabled cxa-atexit, type=bool, default=0, group=pico_cxx_options +# PICO_BAZEL_CONFIG: PICO_CXX_ENABLE_CXA_ATEXIT, Enable cxa-atexit, type=bool, default=0, group=pico_cxx_options bool_flag( name = "PICO_CXX_ENABLE_CXA_ATEXIT", build_setting_default = False, ) -# PICO_BAZEL_CONFIG: PICO_STDIO_UART, OPTION: Globally enable stdio UART, type=bool, default=1, group=pico_stdlib +# PICO_BAZEL_CONFIG: PICO_STDIO_UART, Option to globally enable stdio UART for all targets by default, type=bool, default=1, group=pico_stdlib bool_flag( name = "PICO_STDIO_UART", build_setting_default = True, ) -# PICO_BAZEL_CONFIG: PICO_STDIO_USB, OPTION: Globally enable stdio USB, type=bool, default=0, group=pico_stdlib +# PICO_BAZEL_CONFIG: PICO_STDIO_USB, Option to globally enable stdio USB for all targets by default, type=bool, default=0, group=pico_stdlib bool_flag( name = "PICO_STDIO_USB", build_setting_default = False, ) -# PICO_BAZEL_CONFIG: PICO_STDIO_SEMIHOSTING, OPTION: Globally enable stdio semihosting, type=bool, default=0, group=pico_stdlib +# PICO_BAZEL_CONFIG: PICO_STDIO_SEMIHOSTING, Option to globally enable stdio semi-hosting for all targets by default, type=bool, default=0, group=pico_stdlib bool_flag( name = "PICO_STDIO_SEMIHOSTING", build_setting_default = False, ) +# PICO_BAZEL_CONFIG: PICO_STDIO_RTT, Option to globally enable stdio RTT for all targets by default, type=bool, default=0, group=pico_stdlib +bool_flag( + name = "PICO_STDIO_RTT", + build_setting_default = False, +) + +# PICO_BAZEL_CONFIG: PICO_MULTICORE_ENABLED, OPTION: Enable multicore handling, type=bool, default=1, group=pico_stdlib +bool_flag( + name = "PICO_MULTICORE_ENABLED", + build_setting_default = True, +) + +# PICO_BAZEL_CONFIG: PICO_DEFAULT_DOUBLE_IMPL, The default implementation for pico_double to link. auto selects an appropriate default for the current platform. rp2040 is only supported on the rp2040. dcp is only supported on rp2350, type=string, default=auto, group=build +string_flag( + name = "PICO_DEFAULT_DOUBLE_IMPL", + build_setting_default = "auto", + values = [ + "auto", + "compiler", + "dcp", + "rp2040", + "none", + ], +) + +# PICO_BAZEL_CONFIG: PICO_DEFAULT_FLOAT_IMPL, The default implementation for pico_float to link. auto selects an appropriate default for the current platform. rp2040 is only supported on the rp2040. vfp and dcp are only supported on rp2350, type=string, default=auto, group=build +string_flag( + name = "PICO_DEFAULT_FLOAT_IMPL", + build_setting_default = "auto", + values = [ + "auto", + "compiler", + "dcp", + "rp2040", + "vfp", + "none", + ], +) + +# PICO_BAZEL_CONFIG: PICO_DEFAULT_DIVIDER_IMPL, The default implementation for pico_divider to link. hardware uses accelerated divide instructions while compiler allows the compiler to decide how to handle divide instructions. auto uses the platform default (hardware on RP2040 and compiler on RP2350), type=string, default=auto, group=build +string_flag( + name = "PICO_DEFAULT_DIVIDER_IMPL", + build_setting_default = "auto", + values = [ + "auto", + "hardware", + "compiler", + ], +) + +# PICO_BAZEL_CONFIG: PICO_DEFAULT_PRINTF_IMPL, The default implementation for pico_printf to link. compiler lets the compiler control printf behavior while pico provides a pico-specific implementation, type=string, default=double, group=build +string_flag( + name = "PICO_DEFAULT_PRINTF_IMPL", + build_setting_default = "pico", + values = [ + "pico", + "compiler", + "none", + ], +) + +# PICO_BAZEL_CONFIG: PICO_BINARY_INFO_ENABLED, Whether to include binary info in final firmware, type=bool, default=1, group=pico_stdlib +bool_flag( + name = "PICO_BINARY_INFO_ENABLED", + build_setting_default = True, +) + # PICO_BAZEL_CONFIG: PICO_CMSIS_PATH, Label of a cc_ibrary providing CMSIS core, default="included stub CORE only impl", group=build label_flag( name = "PICO_CMSIS_PATH", @@ -98,10 +175,17 @@ label_flag( build_setting_default = "@tinyusb//:tinyusb", ) -# PICO_BAZEL_CONFIG: PICO_DEFAULT_BINARY_INFO, [Bazel only] The library that provides custom_pico_binary_info to link into all binaries, default=//src/rp2_common/pico_standard_link:default_binary_info, group=pico_standard_link +# TODO: Bazel build for mbedtls at @mbedtls//:mbedtls. +# PICO_BAZEL_CONFIG: PICO_MBEDTLS_LIB, [Bazel only] The library that provides mbedtls, default=@mbedtls//:mbedtls, group=build +label_flag( + name = "PICO_MBEDTLS_LIB", + build_setting_default = "//bazel:incompatible_cc_lib", +) + +# PICO_BAZEL_CONFIG: PICO_DEFAULT_BINARY_INFO, [Bazel only] The library that provides custom_pico_binary_info to link into all binaries, default=//src/rp2_common/pico_standard_binary_info:default_binary_info, group=pico_standard_link label_flag( name = "PICO_DEFAULT_BINARY_INFO", - build_setting_default = "//src/rp2_common/pico_standard_link:default_binary_info", + build_setting_default = "//src/rp2_common/pico_standard_binary_info:default_binary_info", ) # PICO_BAZEL_CONFIG: PICO_BAZEL_BUILD_TYPE, The type of build (e.g. Debug or Release) to embed in binary info, type=string, default=pico, group=build @@ -110,10 +194,10 @@ string_flag( build_setting_default = "Debug", ) -# PICO_BAZEL_CONFIG: PICO_DEFAULT_LINKER_SCRIPT, [Bazel only] The library that provides a linker script to link into all binaries, default=//src/rp2_common/pico_standard_link:default_linker_script, group=pico_standard_link +# PICO_BAZEL_CONFIG: PICO_DEFAULT_LINKER_SCRIPT, [Bazel only] The library that provides a linker script to link into all binaries, default=//src/rp2_common/pico_crt0:default_linker_script, group=pico_standard_link label_flag( name = "PICO_DEFAULT_LINKER_SCRIPT", - build_setting_default = "//src/rp2_common/pico_standard_link:default_linker_script", + build_setting_default = "//src/rp2_common/pico_crt0:default_linker_script", ) # PICO_BAZEL_CONFIG: PICO_NO_TARGET_NAME, Don't define PICO_TARGET_NAME, type=bool, default=0, group=build @@ -128,7 +212,7 @@ label_flag( build_setting_default = "//bazel:no_extra_headers", ) -# PICO_BAZEL_CONFIG: PICO_CONFIG_PLATFORM_HEADER, [Bazel only] The cc_library that provides "pico_config_platform_headers.h" and defines PICO_BOARD, default=//src/common/pico_base:default_platform_headers, group=pico_base +# PICO_BAZEL_CONFIG: PICO_CONFIG_PLATFORM_HEADER, [Bazel only] The cc_library that provides "pico_config_platform_headers.h" and defines PICO_BOARD, default=//src/common/pico_base_headers:default_platform_headers, group=pico_base label_flag( name = "PICO_CONFIG_PLATFORM_HEADER", build_setting_default = "//src/boards:default", @@ -140,6 +224,18 @@ label_flag( build_setting_default = "//bazel:generate_config_header", ) +# PICO_BAZEL_CONFIG: PICO_CLIB, [Bazel only] The flavor of libc porting layer to use. auto infers the correct value to use from PICO_TOOLCHAIN, group=pico_standard_link +string_flag( + name = "PICO_CLIB", + build_setting_default = "auto", + values = [ + "auto", + "llvm_libc", + "newlib", + "picolibc", + ], +) + # PICO_BAZEL_CONFIG: PICO_BTSTACK_CONFIG, [Bazel only] The cc_library that provides btstack_config.h, default=//bazel:empty_cc_lib, group=wireless label_flag( name = "PICO_BTSTACK_CONFIG", diff --git a/bazel/constraint/BUILD.bazel b/bazel/constraint/BUILD.bazel index e11d44286..05cccb92b 100644 --- a/bazel/constraint/BUILD.bazel +++ b/bazel/constraint/BUILD.bazel @@ -21,6 +21,13 @@ constraint_value( constraint_setting = ":sdk_target", ) +# This constraint value is used to guide parts of the build that are specific +# to the rp2350. +constraint_value( + name = "rp2350", + constraint_setting = ":sdk_target", +) + constraint_setting( name = "wireless_support", default_constraint_value = "no_wireless", @@ -41,6 +48,16 @@ config_setting( flag_values = {"//bazel/config:PICO_BOARD": "pico_w"}, ) +config_setting( + name = "pico_toolchain_clang_enabled", + flag_values = {"//bazel/config:PICO_TOOLCHAIN": "clang"}, +) + +config_setting( + name = "pico_toolchain_gcc_enabled", + flag_values = {"//bazel/config:PICO_TOOLCHAIN": "gcc"}, +) + config_setting( name = "pico_baremetal_enabled", flag_values = {"//bazel/config:PICO_BARE_METAL": "True"}, @@ -81,6 +98,81 @@ config_setting( flag_values = {"//bazel/config:PICO_STDIO_SEMIHOSTING": "True"}, ) +config_setting( + name = "pico_stdio_rtt_enabled", + flag_values = {"//bazel/config:PICO_STDIO_RTT": "True"}, +) + +config_setting( + name = "pico_multicore_enabled", + flag_values = {"//bazel/config:PICO_MULTICORE_ENABLED": "True"}, +) + +config_setting( + name = "pico_float_auto_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_FLOAT_IMPL": "auto"}, +) + +config_setting( + name = "pico_float_compiler_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_FLOAT_IMPL": "compiler"}, +) + +config_setting( + name = "pico_float_dcp_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_FLOAT_IMPL": "dcp"}, +) + +config_setting( + name = "pico_float_rp2040_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_FLOAT_IMPL": "rp2040"}, +) + +config_setting( + name = "pico_float_vfp_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_FLOAT_IMPL": "vfp"}, +) + +config_setting( + name = "pico_double_auto_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_DOUBLE_IMPL": "auto"}, +) + +config_setting( + name = "pico_double_compiler_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_DOUBLE_IMPL": "compiler"}, +) + +config_setting( + name = "pico_double_dcp_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_DOUBLE_IMPL": "dcp"}, +) + +config_setting( + name = "pico_double_rp2040_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_DOUBLE_IMPL": "rp2040"}, +) + +config_setting( + name = "pico_divider_hardware_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_DIVIDER_IMPL": "hardware"}, +) + +config_setting( + name = "pico_divider_auto_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_DIVIDER_IMPL": "auto"}, +) + +config_setting( + name = "pico_printf_pico_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_PRINTF_IMPL": "pico"}, +) + +config_setting( + name = "pico_printf_compiler_enabled", + flag_values = {"//bazel/config:PICO_DEFAULT_PRINTF_IMPL": "compiler"}, +) + config_setting( name = "pico_use_default_max_page_size_enabled", flag_values = {"//bazel/config:PICO_USE_DEFAULT_MAX_PAGE_SIZE": "True"}, @@ -91,17 +183,32 @@ config_setting( flag_values = {"//bazel/config:PICO_NO_TARGET_NAME": "True"}, ) +config_setting( + name = "pico_clib_llvm_libc_enabled", + flag_values = {"//bazel/config:PICO_CLIB": "llvm_libc"}, +) + +config_setting( + name = "pico_clib_newlib_enabled", + flag_values = {"//bazel/config:PICO_CLIB": "newlib"}, +) + +config_setting( + name = "pico_clib_picolibc_enabled", + flag_values = {"//bazel/config:PICO_CLIB": "picolibc"}, +) + config_setting( name = "pico_btstack_config_unset", - flag_values = {"//bazel/config:PICO_BTSTACK_CONFIG": "@pico-sdk//bazel:empty_cc_lib"}, + flag_values = {"//bazel/config:PICO_BTSTACK_CONFIG": "//bazel:empty_cc_lib"}, ) config_setting( name = "pico_lwip_config_unset", - flag_values = {"//bazel/config:PICO_LWIP_CONFIG": "@pico-sdk//bazel:empty_cc_lib"}, + flag_values = {"//bazel/config:PICO_LWIP_CONFIG": "//bazel:empty_cc_lib"}, ) config_setting( name = "pico_freertos_unset", - flag_values = {"//bazel/config:PICO_FREERTOS_LIB": "@pico-sdk//bazel:empty_cc_lib"}, + flag_values = {"//bazel/config:PICO_FREERTOS_LIB": "//bazel:empty_cc_lib"}, ) diff --git a/bazel/generate_version_header.py b/bazel/generate_version_header.py index bd47b7c4f..79be833c2 100644 --- a/bazel/generate_version_header.py +++ b/bazel/generate_version_header.py @@ -35,7 +35,7 @@ def _parse_args(): return parser.parse_args() -_EXPANSION_REGEX = re.compile("(?:\$\{)([a-zA-Z]\w*)(?:\})") +_EXPANSION_REGEX = re.compile(r"(?:\$\{)([a-zA-Z]\w*)(?:\})") def generate_version_header(version_string, template, output): diff --git a/bazel/platform/BUILD.bazel b/bazel/platform/BUILD.bazel index 467c0b1d6..39187b259 100644 --- a/bazel/platform/BUILD.bazel +++ b/bazel/platform/BUILD.bazel @@ -4,6 +4,14 @@ platform( name = "rp2040", constraint_values = [ "@pico-sdk//bazel/constraint:rp2040", - "@platforms//cpu:armv6-m", # This is just FYI. + "@platforms//cpu:armv6-m", + ], +) + +platform( + name = "rp2350", + constraint_values = [ + "@pico-sdk//bazel/constraint:rp2350", + "@platforms//cpu:armv8-m", ], ) diff --git a/bazel/toolchain/BUILD.bazel b/bazel/toolchain/BUILD.bazel index 775ee1896..9e0f7719f 100644 --- a/bazel/toolchain/BUILD.bazel +++ b/bazel/toolchain/BUILD.bazel @@ -6,6 +6,24 @@ load("configurable_feature.bzl", "configurable_toolchain_feature") package(default_visibility = ["//visibility:public"]) +cc_args( + name = "armv6m-none-eabi", + actions = [ + "@rules_cc//cc/toolchains/actions:compile_actions", + "@rules_cc//cc/toolchains/actions:link_actions", + ], + args = ["--target=armv6m-none-eabi"], +) + +cc_args( + name = "armv8m.main-none-eabi", + actions = [ + "@rules_cc//cc/toolchains/actions:compile_actions", + "@rules_cc//cc/toolchains/actions:link_actions", + ], + args = ["--target=armv8m.main-none-eabi"], +) + cc_args( name = "cortex-m0", actions = [ @@ -19,20 +37,50 @@ cc_args( ) cc_args( - name = "bazel_no_absolute_paths", - actions = ["@rules_cc//cc/toolchains/actions:compile_actions"], + name = "cortex-m33", + actions = [ + "@rules_cc//cc/toolchains/actions:compile_actions", + "@rules_cc//cc/toolchains/actions:link_actions", + ], args = [ - "-fno-canonical-system-headers", - "-no-canonical-prefixes", + "-mcpu=cortex-m33", + "-march=armv8-m.main+fp+dsp", + "-mfloat-abi=softfp", + "-mthumb", + "-mcmse", ], ) +cc_args( + name = "no-canonical-system-headers", + actions = ["@rules_cc//cc/toolchains/actions:compile_actions"], + args = ["-fno-canonical-system-headers"], +) + +cc_args( + name = "no-canonical-prefixes", + actions = ["@rules_cc//cc/toolchains/actions:compile_actions"], + args = ["-no-canonical-prefixes"], +) + +cc_args( + name = "nostdlibxx", + actions = ["@rules_cc//cc/toolchains/actions:link_actions"], + args = ["-nostdlib++"], +) + +cc_args( + name = "nostartfiles", + actions = ["@rules_cc//cc/toolchains/actions:link_actions"], + args = ["-nostartfiles"], +) + cc_args_list( - name = "all_unconditional_args", - args = [ - ":cortex-m0", - ":bazel_no_absolute_paths", - ], + name = "bazel_no_absolute_paths", + args = select({ + "//bazel/constraint:pico_toolchain_clang_enabled": [], + "//conditions:default": [":no-canonical-system-headers"], + }) + [":no-canonical-prefixes"], ) cc_args( @@ -151,7 +199,13 @@ _HOST_CPU_CONSTRAINTS = { "@arm_gcc_{}-{}//:arm-none-eabi-objcopy".format(host_os, host_cpu), "@arm_gcc_{}-{}//:arm-none-eabi-strip".format(host_os, host_cpu), ], - args = ["@pico-sdk//bazel/toolchain:all_unconditional_args"], + args = select({ + "//bazel/constraint:rp2040": [":cortex-m0"], + "//bazel/constraint:rp2350": [":cortex-m33"], + "//conditions:default": [], + }) + [ + ":bazel_no_absolute_paths", + ], compiler = "gcc", # Useful for distinguishing gcc vs clang. cxx_builtin_include_directories = [ "%sysroot%/arm-none-eabi/include/newlib-nano", @@ -168,9 +222,48 @@ _HOST_CPU_CONSTRAINTS = { ], sysroot = "external/arm_gcc_{}-{}".format(host_os, host_cpu), tags = ["manual"], # Don't try to build this in wildcard builds. - target_compatible_with = [ - "@pico-sdk//bazel/constraint:rp2040", + toolchain_features = [ + "@pico-sdk//bazel/toolchain:legacy_features", + "@pico-sdk//bazel/toolchain:override_debug", + "@pico-sdk//bazel/toolchain:gc_sections", + "@pico-sdk//bazel/toolchain:cxx_no_exceptions", + "@pico-sdk//bazel/toolchain:cxx_no_rtti", + "@pico-sdk//bazel/toolchain:cxx_no_cxa_atexit", + "@pico-sdk//bazel/toolchain:override_max_page_size", + ], +) for host_os, host_cpu in HOSTS] + +[cc_toolchain( + name = "clang_{}-{}_toolchain_cortex-m".format(host_os, host_cpu), + action_type_configs = [ + "@clang_{}-{}//:llvm-ar".format(host_os, host_cpu), + "@clang_{}-{}//:clang".format(host_os, host_cpu), + "@clang_{}-{}//:clang++".format(host_os, host_cpu), + "@clang_{}-{}//:lld".format(host_os, host_cpu), + "@clang_{}-{}//:llvm-objcopy".format(host_os, host_cpu), + "@clang_{}-{}//:llvm-strip".format(host_os, host_cpu), + ], + args = select({ + "//bazel/constraint:rp2040": [ + ":armv6m-none-eabi", + ":cortex-m0", + ], + "//bazel/constraint:rp2350": [ + ":armv8m.main-none-eabi", + ":cortex-m33", + ], + "//conditions:default": [], + }) + [ + ":bazel_no_absolute_paths", + ":nostdlibxx", + ":nostartfiles", ], + compiler = "clang", # Useful for distinguishing gcc vs clang. + exec_compatible_with = [ + _HOST_CPU_CONSTRAINTS[host_cpu], + _HOST_OS_CONSTRAINTS[host_os], + ], + tags = ["manual"], # Don't try to build this in wildcard builds. toolchain_features = [ "@pico-sdk//bazel/toolchain:legacy_features", "@pico-sdk//bazel/toolchain:override_debug", @@ -183,7 +276,7 @@ _HOST_CPU_CONSTRAINTS = { ) for host_os, host_cpu in HOSTS] [toolchain( - name = "arm_gcc_{}-{}".format(host_os, host_cpu), + name = "{}-{}-rp2040".format(host_os, host_cpu), exec_compatible_with = [ _HOST_CPU_CONSTRAINTS[host_cpu], _HOST_OS_CONSTRAINTS[host_os], @@ -191,6 +284,25 @@ _HOST_CPU_CONSTRAINTS = { target_compatible_with = [ "@pico-sdk//bazel/constraint:rp2040", ], - toolchain = ":arm_gcc_{}-{}_toolchain_cortex-m".format(host_os, host_cpu), + toolchain = select({ + "//bazel/constraint:pico_toolchain_clang_enabled": "clang_{}-{}_toolchain_cortex-m".format(host_os, host_cpu), + "//conditions:default": ":arm_gcc_{}-{}_toolchain_cortex-m".format(host_os, host_cpu), + }), + toolchain_type = "@bazel_tools//tools/cpp:toolchain_type", +) for host_os, host_cpu in HOSTS] + +[toolchain( + name = "{}-{}-rp2350".format(host_os, host_cpu), + exec_compatible_with = [ + _HOST_CPU_CONSTRAINTS[host_cpu], + _HOST_OS_CONSTRAINTS[host_os], + ], + target_compatible_with = [ + "@pico-sdk//bazel/constraint:rp2350", + ], + toolchain = select({ + "//bazel/constraint:pico_toolchain_clang_enabled": "clang_{}-{}_toolchain_cortex-m".format(host_os, host_cpu), + "//conditions:default": ":arm_gcc_{}-{}_toolchain_cortex-m".format(host_os, host_cpu), + }), toolchain_type = "@bazel_tools//tools/cpp:toolchain_type", ) for host_os, host_cpu in HOSTS] diff --git a/bazel/toolchain/clang.BUILD b/bazel/toolchain/clang.BUILD new file mode 100644 index 000000000..426fc3339 --- /dev/null +++ b/bazel/toolchain/clang.BUILD @@ -0,0 +1,170 @@ +load("@rules_cc//cc/toolchains:action_type_config.bzl", "cc_action_type_config") +load("@rules_cc//cc/toolchains:tool.bzl", "cc_tool") + +package(default_visibility = ["//visibility:public"]) + +cc_tool( + name = "llvm-ar_tool", + src = select({ + "@platforms//os:windows": "//:bin/llvm-ar.exe", + "//conditions:default": "//:bin/llvm-ar", + }), + data = select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +cc_action_type_config( + name = "llvm-ar", + action_types = ["@rules_cc//cc/toolchains/actions:ar_actions"], + tools = [":llvm-ar_tool"], +) + +cc_tool( + name = "clang_tool", + src = select({ + "@platforms//os:windows": "//:bin/clang.exe", + "//conditions:default": "//:bin/clang", + }), + data = glob([ + "include/armv*-unknown-none-eabi/**", + "lib/clang/*/include/**", + ]) + select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +cc_action_type_config( + name = "clang", + action_types = [ + "@rules_cc//cc/toolchains/actions:assembly_actions", + "@rules_cc//cc/toolchains/actions:c_compile", + ], + tools = [":clang_tool"], +) + +cc_tool( + name = "clang++_tool", + src = select({ + "@platforms//os:windows": "//:bin/clang++.exe", + "//conditions:default": "//:bin/clang++", + }), + data = glob([ + "include/armv*-unknown-none-eabi/**", + "include/c++/**", + "lib/clang/*/include/**", + ]) + select({ + # Windows doesn't have llvm.exe. + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +cc_action_type_config( + name = "clang++", + action_types = ["@rules_cc//cc/toolchains/actions:cpp_compile_actions"], + tools = [":clang++_tool"], +) + +# This tool is actually just clang++ under the hood, but this specifies a +# different set of data files to pull into the sandbox at runtime. +cc_tool( + name = "lld_tool", + src = select({ + "@platforms//os:windows": "//:bin/clang++.exe", + "//conditions:default": "//:bin/clang++", + }), + data = glob([ + "lib/armv*-unknown-none-eabi/**", + "lib/clang/*/lib/armv*-unknown-none-eabi/**", + ]) + select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +cc_action_type_config( + name = "lld", + action_types = ["@rules_cc//cc/toolchains/actions:link_actions"], + tools = [":lld_tool"], +) + +cc_tool( + name = "llvm-objcopy_tool", + src = select({ + "@platforms//os:windows": "//:bin/llvm-objcopy.exe", + "//conditions:default": "//:bin/llvm-objcopy", + }), + data = select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +cc_action_type_config( + name = "llvm-objcopy", + action_types = ["@rules_cc//cc/toolchains/actions:objcopy_embed_data"], + tools = [":llvm-objcopy_tool"], +) + +cc_tool( + name = "llvm-strip_tool", + src = select({ + "@platforms//os:windows": "//:bin/llvm-strip.exe", + "//conditions:default": "//:bin/llvm-strip", + }), + data = select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +cc_action_type_config( + name = "llvm-strip", + action_types = ["@rules_cc//cc/toolchains/actions:strip"], + tools = [":llvm-strip_tool"], +) + +cc_tool( + name = "llvm-objdump_tool", + src = select({ + "@platforms//os:windows": "//:bin/llvm-objdump.exe", + "//conditions:default": "//:bin/llvm-objdump", + }), + data = select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +# There is not yet a well-known action type for llvm-objdump. + +cc_tool( + name = "llvm-profdata_tool", + src = select({ + "@platforms//os:windows": "//:bin/llvm-profdata.exe", + "//conditions:default": "//:bin/llvm-profdata", + }), + data = select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +# There is not yet a well-known action type for llvm-profdata. + +cc_tool( + name = "llvm-cov_tool", + src = select({ + "@platforms//os:windows": "//:bin/llvm-cov.exe", + "//conditions:default": "//:bin/llvm-cov", + }), + data = select({ + "@platforms//os:windows": [], + "//conditions:default": ["//:bin/llvm"], + }), +) + +# There is not yet a well-known action type for llvm-cov. diff --git a/bazel/util/transition.bzl b/bazel/util/transition.bzl index d0baf0d6e..5346c2583 100644 --- a/bazel/util/transition.bzl +++ b/bazel/util/transition.bzl @@ -113,6 +113,26 @@ kitchen_sink_test_binary = declare_transtion( }, ) +# This transition sets SDK configuration options required to build test binaries +# for the pico_float_test suite of tests. +pico_float_test_binary = declare_transtion( + attrs = { + "pico_printf_impl": attr.string(), + "extra_copts": attr.string_list(), + # This could be shared, but we don't in order to make it clearer that + # a transition is in use. + "_allowlist_function_transition": attr.label( + default = "@bazel_tools//tools/allowlists/function_transition_allowlist", + ), + }, + flag_overrides = { + "@pico-sdk//bazel/config:PICO_DEFAULT_PRINTF_IMPL": "pico_printf_impl", + }, + append_to_flags = { + "//command_line_option:copt": "extra_copts", + }, +) + # This is a general purpose transition that applies the listed copt flags to # all transitive dependencies. extra_copts_for_all_deps = declare_transtion( diff --git a/src/boards/generic_board.cmake b/cmake/generic_board.cmake similarity index 51% rename from src/boards/generic_board.cmake rename to cmake/generic_board.cmake index 3307e78c1..5238f205b 100644 --- a/src/boards/generic_board.cmake +++ b/cmake/generic_board.cmake @@ -1,18 +1,33 @@ -# For boards without their own cmake file, simply include a header +# For boards without their own cmake file, we look for a header file -# PICO_CMAKE_CONFIG: PICO_BOARD_HEADER_DIRS, Directories to look for .h in. This is overridable from the user environment, type=list, group=build +# PICO_CMAKE_CONFIG: PICO_BOARD_HEADER_DIRS, List of directories to look for .h in. This may be specified the user environment, type=list, group=build if (DEFINED ENV{PICO_BOARD_HEADER_DIRS}) set(PICO_BOARD_HEADER_DIRS $ENV{PICO_BOARD_HEADER_DIRS}) message("Using PICO_BOARD_HEADER_DIRS from environment ('${PICO_BOARD_HEADER_DIRS}')") endif() set(PICO_BOARD_HEADER_DIRS ${PICO_BOARD_HEADER_DIRS} CACHE STRING "PICO board header directories" FORCE) -list(APPEND PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}/include/boards) +list(APPEND PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}/../src/boards/include/boards) pico_find_in_paths(PICO_BOARD_HEADER_FILE PICO_BOARD_HEADER_DIRS ${PICO_BOARD}.h) if (EXISTS ${PICO_BOARD_HEADER_FILE}) message("Using board configuration from ${PICO_BOARD_HEADER_FILE}") list(APPEND PICO_CONFIG_HEADER_FILES ${PICO_BOARD_HEADER_FILE}) + + # we parse the header file to configure the defaults + file(STRINGS ${PICO_BOARD_HEADER_FILE} HEADER_FILE_CONTENTS) + + while(HEADER_FILE_CONTENTS) + list(POP_FRONT HEADER_FILE_CONTENTS LINE) + if (LINE MATCHES "^[ \t\]*//[ \t\]*pico_cmake_set[ \t\]*([a-zA-Z_][a-zA-Z0-9_]*)[ \t\]*=[ \t\]*(.*)") + set("${CMAKE_MATCH_1}" "${CMAKE_MATCH_2}") + endif() + if (LINE MATCHES "^[ \t\]*//[ \t\]*pico_cmake_set_default[ \t\]*([a-zA-Z_][a-zA-Z0-9_]*)[ \t\]*=[ \t\]*(.*)") + if (NOT DEFINED "${CMAKE_MATCH_1}") + set("${CMAKE_MATCH_1}" "${CMAKE_MATCH_2}") + endif() + endif() + endwhile() else() set(msg "Unable to find definition of board '${PICO_BOARD}' (specified by PICO_BOARD):\n") list(JOIN PICO_BOARD_HEADER_DIRS ", " DIRS) diff --git a/cmake/pico_pre_load_platform.cmake b/cmake/pico_pre_load_platform.cmake index 3bce8e6b4..7a2c2ab2d 100644 --- a/cmake/pico_pre_load_platform.cmake +++ b/cmake/pico_pre_load_platform.cmake @@ -1,21 +1,135 @@ -# PICO_CMAKE_CONFIG: PICO_PLATFORM, platform to build for e.g. rp2040/host, type=string, default=rp2040 or environment value, group=build -if (DEFINED ENV{PICO_PLATFORM} AND (NOT PICO_PLATFORM)) +# PICO_BOARD is the root of config as it can define PICO_PLATFORM and other build vars + +# PICO_CMAKE_CONFIG: PICO_BOARD, Board name being built for. This may be specified in the user environment, type=string, default=pico or pico2, group=build, docref=cmake-platform-board-config +if (DEFINED ENV{PICO_BOARD} AND NOT PICO_BOARD) + set(PICO_BOARD $ENV{PICO_BOARD}) + message("Initializing PICO_BOARD from environment ('${PICO_BOARD}')") +endif() + +# PICO_CMAKE_CONFIG: PICO_PLATFORM, Platform to build for e.g. rp2040/rp2350/rp2350-arm-s/rp2350-riscv/host. This may be specified in the user environment, type=string, default=based on PICO_BOARD or environment value, group=build, docref=cmake-platform-board-config +if (DEFINED ENV{PICO_PLATFORM} AND NOT PICO_PLATFORM) set(PICO_PLATFORM $ENV{PICO_PLATFORM}) - message("Using PICO_PLATFORM from environment ('${PICO_PLATFORM}')") -else() + message("Initializing PICO_PLATFORM from environment ('${PICO_PLATFORM}')") +endif() +set(PICO_SAVED_PLATFORM "${PICO_PLATFORM}") + +# If PICO_PLATFORM is specified byt not PICO_BOARD, we'll make a stab at defaulting +if (NOT PICO_DEFAULT_BOARD_rp2040) + set(PICO_DEFAULT_BOARD_rp2040 "pico") +endif() +if (NOT PICO_DEFAULT_BOARD_rp2350) + set(PICO_DEFAULT_BOARD_rp2350 "pico2") +endif() +if (NOT PICO_DEFAULT_BOARD_rp2350-arm-s) + set(PICO_DEFAULT_BOARD_rp2350-arm-s "pico2") +endif() +if (NOT PICO_DEFAULT_BOARD_rp2350-riscv) + set(PICO_DEFAULT_BOARD_rp2350-riscv "pico2") +endif() +if (NOT PICO_DEFAULT_BOARD_host) + set(PICO_DEFAULT_BOARD_host "none") +endif() + +if (NOT PICO_DEFAULT_PLATFORM) + set(PICO_DEFAULT_PLATFORM "rp2040") +endif() + +if (NOT PICO_BOARD) if (NOT PICO_PLATFORM) - set(PICO_PLATFORM "rp2040") - pico_message("Defaulting PICO_PLATFORM to ${PICO_PLATFORM} since not specified.") + # if we have neither BOARD nor PLATFORM default PLATFORM silently, so we don't end up with a board of "none" + # on platform that does have a default board (we want default PLATFORM and BOARD in that case) + set(PICO_PLATFORM ${PICO_DEFAULT_PLATFORM}) + # set PICO_SAVED_PLATFORM so we don't print "Defaulting" again below + set(PICO_SAVED_PLATFORM ${PICO_DEFAULT_PLATFORM}) + pico_message("Defaulting platform (PICO_PLATFORM) to '${PICO_PLATFORM}' since not specified.") + endif() + if (PICO_DEFAULT_BOARD_${PICO_PLATFORM}) + set(PICO_BOARD ${PICO_DEFAULT_BOARD_${PICO_PLATFORM}}) else() - message("PICO platform is ${PICO_PLATFORM}.") + set(PICO_BOARD "none") endif() -endif () + pico_message("Defaulting target board (PICO_BOARD) to '${PICO_BOARD}' since not specified.") +else() + message("Target board (PICO_BOARD) is '${PICO_BOARD}'.") +endif() +set(PICO_BOARD ${PICO_BOARD} CACHE STRING "PICO target board (e.g. pico, pico2)" FORCE) + +# PICO_CMAKE_CONFIG: PICO_BOARD_CMAKE_DIRS, List of directories to look for .cmake in. This may be specified in the user environment, type=list, group=build +if (DEFINED ENV{PICO_BOARD_CMAKE_DIRS}) + set(PICO_BOARD_CMAKE_DIRS $ENV{PICO_BOARD_CMAKE_DIRS}) + message("Using PICO_BOARD_CMAKE_DIRS from environment ('${PICO_BOARD_CMAKE_DIRS}')") +endif() + +list(APPEND PICO_BOARD_CMAKE_DIRS ${CMAKE_CURRENT_LIST_DIR}/../src/boards) + +pico_find_in_paths(PICO_BOARD_CMAKE_FILE PICO_BOARD_CMAKE_DIRS ${PICO_BOARD}.cmake) +if (EXISTS "${PICO_BOARD_CMAKE_FILE}") + message("Using CMake board configuration from ${PICO_BOARD_CMAKE_FILE}") + include(${PICO_BOARD_CMAKE_FILE} board_config) +else() + include(generic_board) +endif() + +list(APPEND PICO_INCLUDE_DIRS ${PICO_SDK_PATH}/src/boards/include) # so boards/foo.h can be explicitly included + +# PICO_CMAKE_CONFIG: PICO_DEFAULT_RP2350_PLATFORM, Default actual platform to build for if rp2350 is specified for PICO_PLATFORM e.g. rp2350-arm-s/rp2350-riscv, type=string, default=rp2350-arm-s, group=build +if (DEFINED ENV{PICO_DEFAULT_RP2350_PLATFORM} AND NOT PICO_DEFAULT_RP2350_PLATFORM) + set(PICO_DEFAULT_RP2350_PLATFORM $ENV{PICO_DEFAULT_RP2350_PLATFORM}) +endif() +if (NOT PICO_DEFAULT_RP2350_PLATFORM) + set(PICO_DEFAULT_RP2350_PLATFORM "rp2350-arm-s") +endif() + +if (NOT COMMAND pico_expand_pico_platform) + function(pico_expand_pico_platform FUNC DO_MESSAGE) + if (${FUNC} STREQUAL "rp2350") + if (DO_MESSAGE) + message("Auto-converting non-specific PICO_PLATFORM='rp2350' to 'rp2350-arm-s'") + endif() + set(${FUNC} "${PICO_DEFAULT_RP2350_PLATFORM}" PARENT_SCOPE) + endif() + endfunction() +endif() + +if (NOT PICO_PLATFORM) + set(PICO_PLATFORM ${PICO_DEFAULT_PLATFORM}) + pico_message("Defaulting platform (PICO_PLATFORM) to '${PICO_PLATFORM}' since not specified.") +else() + if (NOT PICO_SAVED_PLATFORM) + pico_expand_pico_platform(PICO_PLATFORM 1) + pico_message("Defaulting platform (PICO_PLATFORM) to '${PICO_PLATFORM}' based on PICO_BOARD setting.") + else() + string(REGEX REPLACE "-.*" "" PICO_PLATFORM_PREFIX ${PICO_PLATFORM}) + string(REGEX REPLACE "-.*" "" PICO_SAVED_PLATFORM_PREFIX ${PICO_SAVED_PLATFORM}) + if (PICO_PLATFORM_PREFIX STREQUAL PICO_SAVED_PLATFORM_PREFIX) + # the PICO_PLATFORM specified based on the board is compatible based on the one we were + # already using, so use that + pico_expand_pico_platform(PICO_SAVED_PLATFORM 0) + set(PICO_PLATFORM ${PICO_SAVED_PLATFORM}) + message("Pico Platform (PICO_PLATFORM) is '${PICO_PLATFORM}'.") + else() + message(FATAL_ERROR "PICO_PLATFORM is specified to be '${PICO_SAVED_PLATFORM}', but PICO_BOARD='${PICO_BOARD}' uses \ + '${PICO_PLATFORM}' which is incompatible. You need to delete the CMake cache or build directory and reconfigure to proceed. \ + The best practice is to use separate build directories for different platforms.") + endif() + endif() +endif() +unset(PICO_SAVED_PLATFORM) -set(PICO_PLATFORM ${PICO_PLATFORM} CACHE STRING "PICO Build platform (e.g. rp2040, host)") +if (PICO_PREVIOUS_PLATFORM AND NOT PICO_PREVIOUS_PLATFORM STREQUAL PICO_PLATFORM) + message(FATAL_ERROR "PICO_PLATFORM has been modified from '${PICO_SAVED_PLATFORM}' to '${PICO_PLATFORM}.\ + You need to delete the CMake cache or build directory and reconfigure to proceed.\ + The best practice is to use separate build directories for different platforms.") +endif() +set(PICO_PLATFORM ${PICO_PLATFORM} CACHE STRING "PICO Build platform (e.g. rp2040, rp2350, rp2350-riscv, host)" FORCE) +set(PICO_PREVIOUS_PLATFORM ${PICO_PLATFORM} CACHE STRING "Saved PICO Build platform (e.g. rp2040, rp2350, rp2350-riscv, host)" INTERNAL) -# PICO_CMAKE_CONFIG: PICO_CMAKE_PRELOAD_PLATFORM_FILE, custom CMake file to use to set up the platform environment, type=string, group=build -set(PICO_CMAKE_PRELOAD_PLATFORM_FILE "" CACHE INTERNAL "") -set(PICO_CMAKE_PRELOAD_PLATFORM_DIR "${CMAKE_CURRENT_LIST_DIR}/preload/platforms" CACHE INTERNAL "") +# PICO_CMAKE_CONFIG: PICO_CMAKE_PRELOAD_PLATFORM_FILE, Custom CMake file to use to set up the platform environment, type=string, group=build +set(PICO_CMAKE_PRELOAD_PLATFORM_FILE ${PICO_CMAKE_PRELOAD_PLATFORM_FILE} CACHE INTERNAL "") +if (NOT PICO_CMAKE_PRELOAD_PLATFORM_DIR) + set(PICO_CMAKE_PRELOAD_PLATFORM_DIR "${CMAKE_CURRENT_LIST_DIR}/preload/platforms") +endif() +set(PICO_CMAKE_PRELOAD_PLATFORM_DIR "${PICO_CMAKE_PRELOAD_PLATFORM_DIR}" CACHE INTERNAL "") if (NOT PICO_CMAKE_PRELOAD_PLATFORM_FILE) set(PICO_CMAKE_PRELOAD_PLATFORM_FILE ${PICO_CMAKE_PRELOAD_PLATFORM_DIR}/${PICO_PLATFORM}.cmake CACHE INTERNAL "") diff --git a/cmake/pico_pre_load_toolchain.cmake b/cmake/pico_pre_load_toolchain.cmake index a8fbbdbeb..b41b386cf 100644 --- a/cmake/pico_pre_load_toolchain.cmake +++ b/cmake/pico_pre_load_toolchain.cmake @@ -1,9 +1,11 @@ -# PICO_CMAKE_CONFIG: PICO_TOOLCHAIN_PATH, Path to search for compiler, type=string, default=none (i.e. search system paths), group=build +# PICO_CMAKE_CONFIG: PICO_TOOLCHAIN_PATH, Path to search for compiler, type=string, default=none (i.e. search system paths), group=build, docref=cmake-toolchain-config set(PICO_TOOLCHAIN_PATH "${PICO_TOOLCHAIN_PATH}" CACHE INTERNAL "") # Set a default build type if none was specified set(default_build_type "Release") +list(APPEND CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_PREFIX_PATH) + if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES) message(STATUS "Defaulting build type to '${default_build_type}' since not specified.") set(CMAKE_BUILD_TYPE "${default_build_type}" CACHE STRING "Choose the type of build, options are: 'Debug', 'Release', 'MinSizeRel', 'RelWithDebInfo'." FORCE) @@ -16,28 +18,59 @@ if (CMAKE_BUILD_TYPE STREQUAL "Default") error("Default build type is NOT supported") endif() -# PICO_CMAKE_CONFIG: PICO_COMPILER, Optionally specifies a different compiler (other than pico_arm_gcc.cmake) - this is not yet fully supported, type=string, group=build +if (NOT (DEFINED PICO_COMPILER OR DEFINED CMAKE_TOOLCHAIN_FILE)) + if (DEFINED PICO_DEFAULT_COMPILER) + pico_message("Defaulting compiler (PICO_COMPILER) to '${PICO_DEFAULT_COMPILER}' since not specified.") + set(PICO_COMPILER ${PICO_DEFAULT_COMPILER}) + endif() +endif () + +# PICO_CMAKE_CONFIG: PICO_COMPILER, Specifies the compiler family to use, type=string, group=build, default=PICO_DEFAULT_COMPILER which is set based on PICO_PLATFORM, docref=cmake-toolchain-config # If PICO_COMPILER is specified, set toolchain file to ${PICO_COMPILER}.cmake. if (DEFINED PICO_COMPILER) - if (DEFINED CMAKE_TOOLCHAIN_FILE) - get_filename_component(toolchain "${CMAKE_TOOLCHAIN_FILE}" NAME_WE) - if (NOT "${PICO_COMPILER}" STREQUAL "${toolchain}") - message(WARNING "CMAKE_TOOLCHAIN_FILE is already defined to ${toolchain}.cmake, you\ - need to delete cache and reconfigure if you want to switch compiler.") - endif () + # maintain backwards compatibility with RP2040 SDK compilers + set(ORIG_PICO_COMPILER "${PICO_COMPILER}") + if (PICO_COMPILER STREQUAL "pico_arm_gcc") + if (PICO_PLATFORM STREQUAL "rp2040") + set(PICO_COMPILER "pico_arm_cortex_m0plus_gcc") + elseif(PICO_PLATFORM STREQUAL "rp2350") + set(PICO_COMPILER "pico_arm_cortex_m33_gcc") + endif() + elseif(PICO_COMPILER STREQUAL "pico_arm_clang") + if (PICO_PLATFORM STREQUAL "rp2040") + set(PICO_COMPILER "pico_arm_cortex_m0plus_clang") + elseif(PICO_PLATFORM STREQUAL "rp2350-arm-s") + set(PICO_COMPILER "pico_arm_cortex_m33_clang") + elseif(PICO_PLATFORM STREQUAL "rp2350-arm-ns") + set(PICO_COMPILER "pico_arm_cortex_m33_clang") + endif() + endif() + if (NOT PICO_COMPILER STREQUAL ORIG_PICO_COMPILER) + message("Accepting PICO_COMPILER value '${ORIG_PICO_COMPILER}' for compatibility, but using '${PICO_COMPILER}' instead") + endif() + if (NOT DEFINED PICO_TOOLCHAIN_DIR) + set(PICO_TOOLCHAIN_DIR "${CMAKE_CURRENT_LIST_DIR}/preload/toolchains") + endif() + set(toolchain_file "${PICO_TOOLCHAIN_DIR}/${PICO_COMPILER}.cmake") + if (EXISTS "${toolchain_file}") + set(CMAKE_TOOLCHAIN_FILE "${toolchain_file}") else () - set(toolchain_dir "${CMAKE_CURRENT_LIST_DIR}/preload/toolchains") - set(toolchain_file "${toolchain_dir}/${PICO_COMPILER}.cmake") - if (EXISTS "${toolchain_file}") - set(CMAKE_TOOLCHAIN_FILE "${toolchain_file}" CACHE INTERNAL "") - else () - # todo improve message - message(FATAL_ERROR "Toolchain file \"${PICO_COMPILER}.cmake\" does not exist, please\ - select one from \"cmake/toolchains\" folder.") - endif () + # todo improve message + message(FATAL_ERROR "Toolchain file \"${PICO_COMPILER}.cmake\" does not exist, please\ + select one from \"cmake/toolchains\" folder.") + endif () + message("Configuring toolchain based on PICO_COMPILER '${PICO_COMPILER}'") +endif () + +if (PICO_PREVIOUS_CMAKE_TOOLCHAIN_FILE) + if (NOT "${PICO_PREVIOUS_CMAKE_TOOLCHAIN_FILE}" STREQUAL "${CMAKE_TOOLCHAIN_FILE}") + message(FATAL_ERROR "CMAKE_TOOLCHAIN_FILE was previously defined to ${PICO_PREVIOUS_CMAKE_TOOLCHAIN_FILE}, and now\ + is being changed to ${CMAKE_TOOLCHAIN_FILE}. You\ + need to delete the CMake cache and reconfigure if you want to switch compiler.\ + The best practice is to use separate build directories for different platforms or compilers.") endif () - message("PICO compiler is ${PICO_COMPILER}") endif () +set(PICO_PREVIOUS_CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_FILE} CACHE INTERNAL "Saved CMAKE_TOOLCHAIN_FILE" FORCE) unset(PICO_COMPILER CACHE) diff --git a/cmake/preload/platforms/combined-docs.cmake b/cmake/preload/platforms/combined-docs.cmake new file mode 100644 index 000000000..5683d77a5 --- /dev/null +++ b/cmake/preload/platforms/combined-docs.cmake @@ -0,0 +1,3 @@ +set(PICO_DEFAULT_COMPILER "pico_arm_cortex_m33_gcc") +set(PICO_CHIP rp2350) + diff --git a/cmake/preload/platforms/pico/pico.cmake b/cmake/preload/platforms/pico/pico.cmake deleted file mode 100644 index 6e49411ab..000000000 --- a/cmake/preload/platforms/pico/pico.cmake +++ /dev/null @@ -1,7 +0,0 @@ -if (NOT (DEFINED PICO_COMPILER OR DEFINED CMAKE_TOOLCHAIN_FILE)) - pico_message("Defaulting PICO platform compiler to pico_arm_gcc since not specified.") - set(PICO_COMPILER "pico_arm_gcc") -endif () - - - diff --git a/cmake/preload/platforms/rp2040.cmake b/cmake/preload/platforms/rp2040.cmake index 3406bfcfd..e8151dc0b 100644 --- a/cmake/preload/platforms/rp2040.cmake +++ b/cmake/preload/platforms/rp2040.cmake @@ -1 +1,2 @@ -include(${CMAKE_CURRENT_LIST_DIR}/pico/pico.cmake) \ No newline at end of file +set(PICO_DEFAULT_COMPILER "pico_arm_cortex_m0plus_gcc") +set(PICO_CHIP rp2040) diff --git a/cmake/preload/platforms/rp2350-arm-s.cmake b/cmake/preload/platforms/rp2350-arm-s.cmake new file mode 100644 index 000000000..5683d77a5 --- /dev/null +++ b/cmake/preload/platforms/rp2350-arm-s.cmake @@ -0,0 +1,3 @@ +set(PICO_DEFAULT_COMPILER "pico_arm_cortex_m33_gcc") +set(PICO_CHIP rp2350) + diff --git a/cmake/preload/platforms/rp2350-riscv.cmake b/cmake/preload/platforms/rp2350-riscv.cmake new file mode 100644 index 000000000..2d15db4c7 --- /dev/null +++ b/cmake/preload/platforms/rp2350-riscv.cmake @@ -0,0 +1,3 @@ +set(PICO_DEFAULT_COMPILER "pico_riscv_gcc") +set(PICO_CHIP rp2350) + diff --git a/cmake/preload/toolchains/pico_arm_clang.cmake b/cmake/preload/toolchains/pico_arm_clang.cmake deleted file mode 100644 index 2e600c878..000000000 --- a/cmake/preload/toolchains/pico_arm_clang.cmake +++ /dev/null @@ -1,47 +0,0 @@ -# NOTE: THIS IS A WIP ONLY PICO_ARM_GCC IS CURRENTLY SUPPORTED, however should work with LLVM Embedded Toolchain for ARM -# version 14.0.0 https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-14.0.0 -# todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform -# i.e. CMakeInformation and whatnot -include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake) - -# include our Platform/pico.cmake -set(CMAKE_SYSTEM_NAME PICO) -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus) - -# Find CLANG -pico_find_compiler(PICO_COMPILER_CC clang) -pico_find_compiler(PICO_COMPILER_CXX clang) -#pico_find_compiler(PICO_COMPILER_ASM armasm) -set(PICO_COMPILER_ASM "${PICO_COMPILER_CC}" CACHE INTERNAL "") -pico_find_compiler(PICO_OBJCOPY llvm-objcopy) -pico_find_compiler(PICO_OBJDUMP llvm-objdump) - -# Specify the cross compiler. -set(CMAKE_C_COMPILER ${PICO_COMPILER_CC} CACHE FILEPATH "C compiler") -set(CMAKE_CXX_COMPILER ${PICO_COMPILER_CXX} CACHE FILEPATH "C++ compiler") -set(CMAKE_C_OUTPUT_EXTENSION .o) - -# todo should we be including CMakeASMInformation anyway - i guess that is host side -set(CMAKE_ASM_COMPILER ${PICO_COMPILER_ASM} CACHE FILEPATH "ASM compiler") -set(CMAKE_ASM_COMPILE_OBJECT " -o -c ") -set(CMAKE_INCLUDE_FLAG_ASM "-I") -set(CMAKE_OBJCOPY ${PICO_OBJCOPY} CACHE FILEPATH "") -set(CMAKE_OBJDUMP ${PICO_OBJDUMP} CACHE FILEPATH "") - -# Add target system root to cmake find path. -get_filename_component(PICO_COMPILER_DIR "${PICO_COMPILER_CC}" DIRECTORY) -get_filename_component(CMAKE_FIND_ROOT_PATH "${PICO_COMPILER_DIR}" DIRECTORY) - -# Look for includes and libraries only in the target system prefix. -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) - -option(PICO_DEOPTIMIZED_DEBUG "Build debug builds with -O0" 0) - -# Oz is preferred for Clang (verses CMake default -Os) see also https://gitlab.kitware.com/cmake/cmake/-/issues/22458 -set(CMAKE_C_FLAGS_MINSIZEREL "-Oz -DNDEBUG") - -set(ARM_TOOLCHAIN_COMMON_FLAGS "--target=armv6m-none-eabi -mfloat-abi=soft -march=armv6m --sysroot ${PICO_COMPILER_DIR}/../lib/clang-runtimes/armv6m_soft_nofp") -include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) diff --git a/cmake/preload/toolchains/pico_arm_clang_arm.cmake b/cmake/preload/toolchains/pico_arm_clang_arm.cmake index b943f1bfb..bf06d3410 100644 --- a/cmake/preload/toolchains/pico_arm_clang_arm.cmake +++ b/cmake/preload/toolchains/pico_arm_clang_arm.cmake @@ -1,7 +1,7 @@ # NOTE: THIS IS A WIP ONLY PICO_ARM_GCC IS CURRENTLY SUPPORTED # todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform # i.e. CMakeInformation and whatnot -include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake) +include(${CMAKE_CURRENT_LIST_DIR}/util/find_compiler.cmake) # include our Platform/PICO.cmake set(CMAKE_SYSTEM_NAME PICO) @@ -37,7 +37,5 @@ set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -option(PICO_DEOPTIMIZED_DEBUG "Build debug builds with -O0" 0) - set(ARM_TOOLCHAIN_COMMON_FLAGS " --cpu=Cortex-M0plus") -include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) +include(${CMAKE_CURRENT_LIST_DIR}/util/set_flags.cmake) diff --git a/cmake/preload/toolchains/pico_arm_cortex_m0plus_clang.cmake b/cmake/preload/toolchains/pico_arm_cortex_m0plus_clang.cmake new file mode 100644 index 000000000..5ebde3e00 --- /dev/null +++ b/cmake/preload/toolchains/pico_arm_cortex_m0plus_clang.cmake @@ -0,0 +1,8 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus) + +# these are all the directories under LLVM embedded toolchain for ARM (newlib or pibolibc) and under llvm_libc +set(PICO_CLANG_RUNTIMES armv6m_soft_nofp armv6m-unknown-none-eabi) + +set(PICO_COMMON_LANG_FLAGS "--target=armv6m-none-eabi -mfloat-abi=soft -march=armv6m") + +include(${CMAKE_CURRENT_LIST_DIR}/util/pico_arm_clang_common.cmake) diff --git a/cmake/preload/toolchains/pico_arm_cortex_m0plus_gcc.cmake b/cmake/preload/toolchains/pico_arm_cortex_m0plus_gcc.cmake new file mode 100644 index 000000000..55bfffe2f --- /dev/null +++ b/cmake/preload/toolchains/pico_arm_cortex_m0plus_gcc.cmake @@ -0,0 +1,7 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus) + +set(PICO_DEFAULT_GCC_TRIPLE arm-none-eabi) +# on ARM -mcpu should not be mixed with -march +set(PICO_COMMON_LANG_FLAGS " -mcpu=cortex-m0plus -mthumb") + +include(${CMAKE_CURRENT_LIST_DIR}/util/pico_arm_gcc_common.cmake) \ No newline at end of file diff --git a/cmake/preload/toolchains/pico_arm_cortex_m23_gcc.cmake b/cmake/preload/toolchains/pico_arm_cortex_m23_gcc.cmake new file mode 100644 index 000000000..4bd6b2409 --- /dev/null +++ b/cmake/preload/toolchains/pico_arm_cortex_m23_gcc.cmake @@ -0,0 +1,15 @@ +# todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform +# i.e. CMakeInformation and whatnot + +set(CMAKE_SYSTEM_PROCESSOR cortex-m23) +set(PICO_DEFAULT_GCC_TRIPLE arm-none-eabi) + +# todo amy should this be -mfloat-abi=hard? +set(PICO_COMMON_LANG_FLAGS " -mcpu=cortex-m23 -mthumb -march=armv8-m.base") +# todo probably need a setting here, also do we want `softfp`? +set(PICO_COMMON_LANG_FLAGS "${PICO_COMMON_LANG_FLAGS} -mfloat-abi=softfp") +if (NOT PICO_NO_CMSE) + set(PICO_COMMON_LANG_FLAGS "${PICO_COMMON_LANG_FLAGS} -mcmse") +endif() + +include(${CMAKE_CURRENT_LIST_DIR}/util/pico_arm_gcc_common.cmake) \ No newline at end of file diff --git a/cmake/preload/toolchains/pico_arm_cortex_m33_clang.cmake b/cmake/preload/toolchains/pico_arm_cortex_m33_clang.cmake new file mode 100644 index 000000000..d35bdbc19 --- /dev/null +++ b/cmake/preload/toolchains/pico_arm_cortex_m33_clang.cmake @@ -0,0 +1,8 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m33) + +# these are all the directories under LLVM embedded toolchain for ARM (newlib or pibolibc) and under llvm_libc +set(PICO_CLANG_RUNTIMES armv8m.main_soft_nofp armv8m.main-unknown-none-eabi) + +set(PICO_COMMON_LANG_FLAGS "-mcpu=cortex-m33 --target=armv8m.main-none-eabi -mfloat-abi=softfp -march=armv8m.main+fp+dsp") + +include(${CMAKE_CURRENT_LIST_DIR}/util/pico_arm_clang_common.cmake) diff --git a/cmake/preload/toolchains/pico_arm_cortex_m33_gcc.cmake b/cmake/preload/toolchains/pico_arm_cortex_m33_gcc.cmake new file mode 100644 index 000000000..0ba3351f4 --- /dev/null +++ b/cmake/preload/toolchains/pico_arm_cortex_m33_gcc.cmake @@ -0,0 +1,10 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m33) +set(PICO_DEFAULT_GCC_TRIPLE arm-none-eabi) + +set(PICO_COMMON_LANG_FLAGS " -mcpu=cortex-m33 -mthumb -march=armv8-m.main+fp+dsp") +set(PICO_COMMON_LANG_FLAGS "${PICO_COMMON_LANG_FLAGS} -mfloat-abi=softfp") +if (NOT PICO_NO_CMSE) + set(PICO_COMMON_LANG_FLAGS "${PICO_COMMON_LANG_FLAGS} -mcmse") +endif() + +include(${CMAKE_CURRENT_LIST_DIR}/util/pico_arm_gcc_common.cmake) \ No newline at end of file diff --git a/cmake/preload/toolchains/pico_arm_gcc.cmake b/cmake/preload/toolchains/pico_arm_gcc.cmake deleted file mode 100644 index ad5d33f38..000000000 --- a/cmake/preload/toolchains/pico_arm_gcc.cmake +++ /dev/null @@ -1,52 +0,0 @@ -# todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform -# i.e. CMakeInformation and whatnot -include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake) - -# include our Platform/PICO.cmake -set(CMAKE_SYSTEM_NAME PICO) -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus) - -if (NOT PICO_GCC_TRIPLE) - if (DEFINED ENV{PICO_GCC_TRIPLE}) - set(PICO_GCC_TRIPLE $ENV{PICO_GCC_TRIPLE}) - message("PICO_GCC_TRIPLE set from environment: $ENV{PICO_GCC_TRIPLE}") - else() - set(PICO_GCC_TRIPLE arm-none-eabi) - #pico_message_debug("PICO_GCC_TRIPLE defaulted to arm-none-eabi") - endif() -endif() - -# Find GCC for ARM. -pico_find_compiler(PICO_COMPILER_CC ${PICO_GCC_TRIPLE}-gcc) -pico_find_compiler(PICO_COMPILER_CXX ${PICO_GCC_TRIPLE}-g++) -set(PICO_COMPILER_ASM "${PICO_COMPILER_CC}" CACHE INTERNAL "") -pico_find_compiler(PICO_OBJCOPY ${PICO_GCC_TRIPLE}-objcopy) -pico_find_compiler(PICO_OBJDUMP ${PICO_GCC_TRIPLE}-objdump) - -# Specify the cross compiler. -set(CMAKE_C_COMPILER ${PICO_COMPILER_CC} CACHE FILEPATH "C compiler") -set(CMAKE_CXX_COMPILER ${PICO_COMPILER_CXX} CACHE FILEPATH "C++ compiler") -set(CMAKE_C_OUTPUT_EXTENSION .o) - -# todo should we be including CMakeASMInformation anyway - i guess that is host side -set(CMAKE_ASM_COMPILER ${PICO_COMPILER_ASM} CACHE FILEPATH "ASM compiler") -set(CMAKE_ASM_COMPILE_OBJECT " -o -c ") -set(CMAKE_INCLUDE_FLAG_ASM "-I") -set(CMAKE_OBJCOPY ${PICO_OBJCOPY} CACHE FILEPATH "") -set(CMAKE_OBJDUMP ${PICO_OBJDUMP} CACHE FILEPATH "") - -# Add target system root to cmake find path. -get_filename_component(PICO_COMPILER_DIR "${PICO_COMPILER_CC}" DIRECTORY) -get_filename_component(CMAKE_FIND_ROOT_PATH "${PICO_COMPILER_DIR}" DIRECTORY) - -# Look for includes and libraries only in the target system prefix. -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) - -option(PICO_DEOPTIMIZED_DEBUG "Build debug builds with -O0" 0) - -# on ARM -mcpu should not be mixed with -march -set(ARM_TOOLCHAIN_COMMON_FLAGS " -mcpu=cortex-m0plus -mthumb") -include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) diff --git a/cmake/preload/toolchains/pico_riscv_gcc.cmake b/cmake/preload/toolchains/pico_riscv_gcc.cmake new file mode 100644 index 000000000..d8a45486f --- /dev/null +++ b/cmake/preload/toolchains/pico_riscv_gcc.cmake @@ -0,0 +1,7 @@ +set(CMAKE_SYSTEM_PROCESSOR hazard3) + +set(PICO_DEFAULT_GCC_TRIPLE riscv32-unknown-elf riscv32-corev-elf) + +set(PICO_COMMON_LANG_FLAGS " -march=rv32imac_zicsr_zifencei_zba_zbb_zbs_zbkb -mabi=ilp32") + +include(${CMAKE_CURRENT_LIST_DIR}/util/pico_arm_gcc_common.cmake) diff --git a/cmake/preload/toolchains/pico_riscv_gcc_zcb_zcmp.cmake b/cmake/preload/toolchains/pico_riscv_gcc_zcb_zcmp.cmake new file mode 100644 index 000000000..ffb067da4 --- /dev/null +++ b/cmake/preload/toolchains/pico_riscv_gcc_zcb_zcmp.cmake @@ -0,0 +1,10 @@ +# todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform +# i.e. CMakeInformation and whatnot + +set(CMAKE_SYSTEM_PROCESSOR hazard3) + +set(PICO_DEFAULT_GCC_TRIPLE riscv32-unknown-elf riscv32-corev-elf) + +set(PICO_COMMON_LANG_FLAGS " -march=rv32ima_zicsr_zifencei_zba_zbb_zbs_zbkb_zca_zcb_zcmp -mabi=ilp32") + +include(${CMAKE_CURRENT_LIST_DIR}/util/pico_arm_gcc_common.cmake) diff --git a/cmake/preload/toolchains/find_compiler.cmake b/cmake/preload/toolchains/util/find_compiler.cmake similarity index 59% rename from cmake/preload/toolchains/find_compiler.cmake rename to cmake/preload/toolchains/util/find_compiler.cmake index 6052369fd..62519bdfc 100644 --- a/cmake/preload/toolchains/find_compiler.cmake +++ b/cmake/preload/toolchains/util/find_compiler.cmake @@ -7,10 +7,10 @@ endif () # Find the compiler executable and store its path in a cache entry ${compiler_path}. # If not found, issue a fatal message and stop processing. PICO_TOOLCHAIN_PATH can be provided from # commandline as additional search path. -function(pico_find_compiler compiler_path compiler_exe) +function(pico_find_compiler compiler_path compiler_exes) # Search user provided path first. find_program( - ${compiler_path} ${compiler_exe} + ${compiler_path} NAMES ${compiler_exes} PATHS ENV PICO_TOOLCHAIN_PATH PATH_SUFFIXES bin NO_DEFAULT_PATH @@ -21,11 +21,21 @@ function(pico_find_compiler compiler_path compiler_exe) if (DEFINED ENV{PICO_TOOLCHAIN_PATH}) message(WARNING "PICO_TOOLCHAIN_PATH specified ($ENV{PICO_TOOLCHAIN_PATH}), but ${compiler_exe} not found there") endif() - find_program(${compiler_path} ${compiler_exe}) + find_program(${compiler_path} NAMES ${compiler_exes}) endif () if ("${${compiler_path}}" STREQUAL "${compiler_path}-NOTFOUND") set(PICO_TOOLCHAIN_PATH "" CACHE PATH "Path to search for compiler.") - message(FATAL_ERROR "Compiler '${compiler_exe}' not found, you can specify search path with\ + list(JOIN compiler_exes " / " compiler_exes) + message(FATAL_ERROR "Compiler '${compiler_exes}' not found, you can specify search path with\ \"PICO_TOOLCHAIN_PATH\".") endif () endfunction() + +# Find the compiler executable and store its path in a cache entry ${compiler_path}. +# If not found, issue a fatal message and stop processing. PICO_TOOLCHAIN_PATH can be provided from +# commandline as additional search path. +function(pico_find_compiler_with_triples compiler_path triples compiler_suffix) + list(TRANSFORM triples APPEND "-${compiler_suffix}") + pico_find_compiler(${compiler_path} "${triples}") + set(${compiler_path} ${${compiler_path}} PARENT_SCOPE) +endfunction() diff --git a/cmake/preload/toolchains/util/pico_arm_clang_common.cmake b/cmake/preload/toolchains/util/pico_arm_clang_common.cmake new file mode 100644 index 000000000..5cb4e2df5 --- /dev/null +++ b/cmake/preload/toolchains/util/pico_arm_clang_common.cmake @@ -0,0 +1,97 @@ +include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake) + +# include our Platform/PICO.cmake +set(CMAKE_SYSTEM_NAME PICO) + +# Find Clang +pico_find_compiler(PICO_COMPILER_CC clang) +pico_find_compiler(PICO_COMPILER_CXX clang++) +set(PICO_COMPILER_ASM "${PICO_COMPILER_CC}" CACHE INTERNAL "") +pico_find_compiler(PICO_OBJCOPY llvm-objcopy) +pico_find_compiler(PICO_OBJDUMP llvm-objdump) + +# Specify the cross compiler. +set(CMAKE_C_COMPILER ${PICO_COMPILER_CC} CACHE FILEPATH "C compiler") +set(CMAKE_CXX_COMPILER ${PICO_COMPILER_CXX} CACHE FILEPATH "C++ compiler") +set(CMAKE_ASM_COMPILER ${PICO_COMPILER_ASM} CACHE FILEPATH "ASM compiler") + +# workaround for projects that don't enable ASM +set(CMAKE_ASM_COMPILE_OBJECT " -o -c ") +set(CMAKE_INCLUDE_FLAG_ASM "-I") + +set(CMAKE_OBJCOPY ${PICO_OBJCOPY} CACHE FILEPATH "") +set(CMAKE_OBJDUMP ${PICO_OBJDUMP} CACHE FILEPATH "") + +foreach(LANG IN ITEMS C CXX ASM) + set(CMAKE_${LANG}_OUTPUT_EXTENSION .o) +endforeach() + +# Add target system root to cmake find path. +get_filename_component(PICO_COMPILER_DIR "${PICO_COMPILER_CC}" DIRECTORY) +get_filename_component(CMAKE_FIND_ROOT_PATH "${PICO_COMPILER_DIR}" DIRECTORY) + +# Look for includes and libraries only in the target system prefix. +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) + +# Oz is preferred for Clang (verses CMake default -Os) see also https://gitlab.kitware.com/cmake/cmake/-/issues/22458 +foreach(LANG IN ITEMS C CXX ASM) + set(CMAKE_${LANG}_FLAGS_MINSIZEREL_INIT "-Oz -DNDEBUG") +endforeach() + +list(APPEND CMAKE_TRY_COMPILE_PLATFORM_VARIABLES PICO_CLIB) + +foreach(PICO_CLANG_RUNTIME IN LISTS PICO_CLANG_RUNTIMES) + # LLVM embedded-toolchain for ARM style + find_path(PICO_COMPILER_SYSROOT NAMES include/stdio.h + HINTS + ${PICO_COMPILER_DIR}/../lib/clang-runtimes/arm-none-eabi/${PICO_CLANG_RUNTIME} + ${PICO_COMPILER_DIR}/../lib/clang-runtimes/${PICO_CLANG_RUNTIME} + ) + + if (PICO_COMPILER_SYSROOT) + if (NOT PICO_CLIB) + # this is a bit of a hack; to try to autodetect the C library used: + # `picolibc.h` seems to exist on the newer versions of LLVM embedded toolchain for ARM using picolibc whereas + # `newlib.h` appears in all versions, so isn't very useful + if (EXISTS "${PICO_COMPILER_SYSROOT}/include/picolibc.h") + message("Setting default C library to picolibc as LLVM appears to be using it") + set(PICO_CLIB "picolibc" CACHE INTERNAL "") + endif() + endif() + break() + endif() + # llvm_libc style + find_path(PICO_COMPILER_SYSROOT NAMES stdio.h + HINTS + ${PICO_COMPILER_DIR}/../include/${PICO_CLANG_RUNTIME} + ) + if (PICO_COMPILER_SYSROOT) + if (NOT PICO_CLIB) + message("Setting default C library to llvm_libc as LLVM appears to be using it") + set(PICO_CLIB "llvm_libc" CACHE INTERNAL "") + endif() + break() + endif() +endforeach() + +# moving this here as a reminder from pico_standard_link; it was commented out theee, but if ever needed, +# it belongs here as part of LINKER_FLAGS_INIT +#target_link_options(pico_standard_link INTERFACE "LINKER:-fuse-ld=lld") + +if (PICO_CLIB STREQUAL "llvm_libc") + # TODO: Remove -nostdlib++ once we include libc++ in the toolchain. + # TODO: Move -nostartfiles to the appropriate library. + foreach(TYPE IN ITEMS EXE SHARED MODULE) + set(CMAKE_${TYPE}_LINKER_FLAGS_INIT "-nostdlib++ -nostartfiles") + endforeach() +else() + if (NOT PICO_COMPILER_SYSROOT) + message(FATAL_ERROR "Could not find an llvm runtime for '${PICO_CLANG_RUNTIME}'") + endif() + + set(PICO_COMMON_LANG_FLAGS "${PICO_COMMON_LANG_FLAGS} --sysroot ${PICO_COMPILER_SYSROOT}") +endif() +include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) diff --git a/cmake/preload/toolchains/util/pico_arm_gcc_common.cmake b/cmake/preload/toolchains/util/pico_arm_gcc_common.cmake new file mode 100644 index 000000000..053e1b165 --- /dev/null +++ b/cmake/preload/toolchains/util/pico_arm_gcc_common.cmake @@ -0,0 +1,57 @@ +include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake) + +# include our Platform/PICO.cmake +set(CMAKE_SYSTEM_NAME PICO) + +# PICO_CMAKE_CONFIG: PICO_GCC_TRIPLE, List of GCC_TRIPLES -- usually only one -- to try when searching for a compiler. This may be specified the user environment, type=int, default=PICO_DEFAULT_GCC_TRIPLE which is set based on PICO_COMPILER, group=pico_base, doxref=cmake-toolchain-config +if (NOT PICO_GCC_TRIPLE) + if (DEFINED ENV{_SAVED_PICO_GCC_TRIPLE}) + # saved within the same cmake invocation + set(PICO_GCC_TRIPLE $ENV{_SAVED_PICO_GCC_TRIPLE}) + elseif (DEFINED ENV{PICO_GCC_TRIPLE}) + set(PICO_GCC_TRIPLE $ENV{PICO_GCC_TRIPLE}) + message("Initializing PICO_GCC_TRIPLE from environment ('${PICO_GCC_TRIPLE}')") + elseif(DEFINED PICO_DEFAULT_GCC_TRIPLE) + message("Defaulting PICO_GCC_TRIPLE to '${PICO_DEFAULT_GCC_TRIPLE}'") + set(PICO_GCC_TRIPLE ${PICO_DEFAULT_GCC_TRIPLE}) + else() + message(FATAL_ERROR "PICO_DEFAULT_GCC_TRIPLE is not defined") + endif() +endif() +set(PICO_GCC_TRIPLE "${PICO_GCC_TRIPLE}" CACHE INTERNAL "") +set(ENV{_SAVED_PICO_GCC_TRIPLE} "${PICO_GCC_TRIPLE}") + +# Find GCC +pico_find_compiler_with_triples(PICO_COMPILER_CC "${PICO_GCC_TRIPLE}" gcc) +pico_find_compiler_with_triples(PICO_COMPILER_CXX "${PICO_GCC_TRIPLE}" g++) +set(PICO_COMPILER_ASM "${PICO_COMPILER_CC}" CACHE INTERNAL "") +pico_find_compiler_with_triples(PICO_OBJCOPY "${PICO_GCC_TRIPLE}" objcopy) +pico_find_compiler_with_triples(PICO_OBJDUMP "${PICO_GCC_TRIPLE}" objdump) + +# Specify the cross compiler. +set(CMAKE_C_COMPILER ${PICO_COMPILER_CC} CACHE FILEPATH "C compiler") +set(CMAKE_CXX_COMPILER ${PICO_COMPILER_CXX} CACHE FILEPATH "C++ compiler") +set(CMAKE_ASM_COMPILER ${PICO_COMPILER_ASM} CACHE FILEPATH "ASM compiler") + +# workaround for projects that don't enable ASM +set(CMAKE_ASM_COMPILE_OBJECT " -o -c ") +set(CMAKE_INCLUDE_FLAG_ASM "-I") + +set(CMAKE_OBJCOPY ${PICO_OBJCOPY} CACHE FILEPATH "") +set(CMAKE_OBJDUMP ${PICO_OBJDUMP} CACHE FILEPATH "") + +foreach(LANG IN ITEMS C CXX ASM) + set(CMAKE_${LANG}_OUTPUT_EXTENSION .o) +endforeach() + +# Add target system root to cmake find path. +get_filename_component(PICO_COMPILER_DIR "${PICO_COMPILER_CC}" DIRECTORY) +get_filename_component(CMAKE_FIND_ROOT_PATH "${PICO_COMPILER_DIR}" DIRECTORY) + +# Look for includes and libraries only in the target system prefix. +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) + +include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake) diff --git a/cmake/preload/toolchains/set_flags.cmake b/cmake/preload/toolchains/util/set_flags.cmake similarity index 67% rename from cmake/preload/toolchains/set_flags.cmake rename to cmake/preload/toolchains/util/set_flags.cmake index 7f208db3b..5a7067012 100644 --- a/cmake/preload/toolchains/set_flags.cmake +++ b/cmake/preload/toolchains/util/set_flags.cmake @@ -1,13 +1,19 @@ +option(PICO_DEOPTIMIZED_DEBUG "Build debug builds with -O0" 0) +option(PICO_DEBUG_INFO_IN_RELEASE "Include debug info in release builds" 1) get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) foreach(LANG IN ITEMS C CXX ASM) - set(CMAKE_${LANG}_FLAGS_INIT "${ARM_TOOLCHAIN_COMMON_FLAGS}") + set(CMAKE_${LANG}_FLAGS_INIT "${PICO_COMMON_LANG_FLAGS}") unset(CMAKE_${LANG}_FLAGS_DEBUG CACHE) if (PICO_DEOPTIMIZED_DEBUG) set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0") else() set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og") endif() + if (PICO_DEBUG_INFO_IN_RELEASE) + set(CMAKE_${LANG}_FLAGS_RELEASE_INIT "-g") + set(CMAKE_${LANG}_FLAGS_MINSIZEREL_INIT "-g") + endif() set(CMAKE_${LANG}_LINK_FLAGS "-Wl,--build-id=none") # try_compile is where the feature testing is done, and at that point, diff --git a/docs/CMakeLists.txt b/docs/CMakeLists.txt index 45fd1d609..3171c5d3b 100644 --- a/docs/CMakeLists.txt +++ b/docs/CMakeLists.txt @@ -40,13 +40,26 @@ if(PICO_BUILD_DOCS) endif() set(DOXY_OUTPUT_DIR "${CMAKE_CURRENT_BINARY_DIR}/doxygen") - set(DOXY_INPUT_DIRS "${PICO_DOXYGEN_PATHS}") - set(DOXY_EXCLUDE_DIRS "${PICO_DOXYGEN_EXCLUDE_PATHS}") + string(REPLACE ";" " " DOXY_INPUT_DIRS "${PICO_DOXYGEN_PATHS}") + string(REPLACE ";" " " DOXY_EXCLUDE_DIRS "${PICO_DOXYGEN_EXCLUDE_PATHS}") + string(REPLACE ";" " " DOXY_PREDEFINED "${PICO_DOXYGEN_PRE_DEFINES}") + string(REPLACE ";" " " DOXY_ENABLED_SECTIONS "${PICO_DOXYGEN_ENABLED_SECTIONS}") set(DOXY_EXAMPLE_DIR "${PICO_EXAMPLES_PATH}") - + # auto genereate additional section enables from library paths + foreach (DIR IN LISTS PICO_DOXYGEN_PATHS) + get_filename_component(NAME "${DIR}" NAME) + if (NOT DIR STREQUAL "src") + set(DOXY_ENABLED_SECTIONS "${DOXY_ENABLED_SECTIONS} ${NAME}") + endif() + endforeach () set(doxyfile_in ${CMAKE_CURRENT_SOURCE_DIR}/Doxyfile.in) set(doxyfile ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile) + if (PICO_PLATFORM STREQUAL "rp2040") + set(PICO_DOXYGEN_TAG "(RP2040)") + elseif (PICO_PLATFORM STREQUAL "rp2350-arm-s" OR PICO_PLATFORM STREQUAL "rp2350-riscv") + set(PICO_DOXYGEN_TAG "(RP2350)") + endif() configure_file(${doxyfile_in} ${doxyfile} @ONLY) add_custom_target(docs diff --git a/docs/Doxyfile.in b/docs/Doxyfile.in index 5dc4be72f..916877b32 100644 --- a/docs/Doxyfile.in +++ b/docs/Doxyfile.in @@ -1,6 +1,6 @@ PROJECT_NAME = "Raspberry Pi Pico SDK" PROJECT_BRIEF = "Raspberry Pi Pico SDK documentation" -PROJECT_NUMBER = @PICO_SDK_VERSION_STRING@ +PROJECT_NUMBER = @PICO_SDK_VERSION_STRING@ @PICO_DOXYGEN_TAG@ #STRIP_FROM_PATH = @PROJECT_SOURCE_DIR@ STRIP_FROM_PATH = @DOXY_INPUT_DIRS@ @@ -50,15 +50,19 @@ EXTRACT_STATIC = YES EXTRACT_ALL = NO ALWAYS_DETAILED_SEC = NO -#REPEAT_BRIEF = NO +#REPEAT_BRIEF = NO +ENABLE_PREPROCESSING = YES # Need these next options to ensure that functions with modifiers do not confuse the Doxygen parser. # And any further function modifiers here. MACRO_EXPANSION = YES -PREDEFINED = __not_in_flash_func(x) \ - __time_critical_func(x) \ +PREDEFINED = __not_in_flash_func(x)= \ + __time_critical_func(x)= \ __not_in_flash(x)= \ __no_inline_not_in_flash(x)= \ __attribute__(x)= \ - DOXYGEN_GENERATION= + DOXYGEN_GENERATION= \ + @DOXY_PREDEFINED@ + +ENABLED_SECTIONS = @DOXY_ENABLED_SECTIONS@ \ No newline at end of file diff --git a/docs/index.h b/docs/index.h index d6edc0040..ded921d75 100644 --- a/docs/index.h +++ b/docs/index.h @@ -6,67 +6,88 @@ // Here to organize documentation order +// for some reason cond/endcond work better here than if/endif + /** * \defgroup hardware Hardware APIs - * This group of libraries provides a thin and efficient C API / abstractions to access the RP2040 hardware without having to read and write + * This group of libraries provides a thin and efficient C API / abstractions to access the RP-series microcontroller hardware without having to read and write * hardware registers directly. * @{ - * \defgroup hardware_adc hardware_adc - * \defgroup hardware_base hardware_base - * \defgroup hardware_claim hardware_claim - * \defgroup hardware_clocks hardware_clocks - * \defgroup hardware_divider hardware_divider - * \defgroup hardware_dma hardware_dma - * \defgroup hardware_exception hardware_exception - * \defgroup hardware_flash hardware_flash - * \defgroup hardware_gpio hardware_gpio - * \defgroup hardware_i2c hardware_i2c - * \defgroup hardware_interp hardware_interp - * \defgroup hardware_irq hardware_irq - * \defgroup hardware_pio hardware_pio - * \defgroup hardware_pll hardware_pll - * \defgroup hardware_pwm hardware_pwm - * \defgroup hardware_resets hardware_resets - * \defgroup hardware_rtc hardware_rtc - * \defgroup hardware_spi hardware_spi - * \defgroup hardware_sync hardware_sync - * \defgroup hardware_timer hardware_timer - * \defgroup hardware_uart hardware_uart - * \defgroup hardware_vreg hardware_vreg - * \defgroup hardware_watchdog hardware_watchdog - * \defgroup hardware_xosc hardware_xosc + * \cond hardware_adc \defgroup hardware_adc hardware_adc \endcond + * \cond hardware_base \defgroup hardware_base hardware_base \endcond + * \cond hardware_bootlock \defgroup hardware_bootlock hardware_bootlock \endcond + * \cond hardware_claim \defgroup hardware_claim hardware_claim \endcond + * \cond hardware_clocks \defgroup hardware_clocks hardware_clocks \endcond + * \cond hardware_divider \defgroup hardware_divider hardware_divider \endcond + * \cond hardware_dcp \defgroup hardware_dcp hardware_dcp \endcond + * \cond hardware_dma \defgroup hardware_dma hardware_dma \endcond + * \cond hardware_exception \defgroup hardware_exception hardware_exception \endcond + * \cond hardware_flash \defgroup hardware_flash hardware_flash \endcond + * \cond hardware_gpio \defgroup hardware_gpio hardware_gpio \endcond + * \cond hardware_hazard3 \defgroup hardware_hazard3 hardware_hazard3 \endcond + * \cond hardware_i2c \defgroup hardware_i2c hardware_i2c \endcond + * \cond hardware_interp \defgroup hardware_interp hardware_interp \endcond + * \cond hardware_irq \defgroup hardware_irq hardware_irq \endcond + * \cond hardware_pio \defgroup hardware_pio hardware_pio \endcond + * \cond hardware_pll \defgroup hardware_pll hardware_pll \endcond + * \cond hardware_powman \defgroup hardware_powman hardware_powman \endcond + * \cond hardware_pwm \defgroup hardware_pwm hardware_pwm \endcond + * \cond hardware_pwm \defgroup hardware_pwm hardware_pwm \endcond + * \cond hardware_resets \defgroup hardware_resets hardware_resets \endcond + * \cond hardware_riscv \defgroup hardware_riscv hardware_riscv \endcond + * \cond hardware_riscv_platform_timer \defgroup hardware_riscv_platform_timer hardware_riscv_platform_timer \endcond + * \cond hardware_rtc \defgroup hardware_rtc hardware_rtc \endcond + * \cond hardware_rcp \defgroup hardware_rcp hardware_rcp \endcond + * \cond hardware_spi \defgroup hardware_spi hardware_spi \endcond + * \cond hardware_sha256 \defgroup hardware_sha256 hardware_sha256 \endcond + * \cond hardware_sync \defgroup hardware_sync hardware_sync \endcond + * \cond hardware_ticks \defgroup hardware_ticks hardware_ticks \endcond + * \cond hardware_timer \defgroup hardware_timer hardware_timer \endcond + * \cond hardware_uart \defgroup hardware_uart hardware_uart \endcond + * \cond hardware_vreg \defgroup hardware_vreg hardware_vreg \endcond + * \cond hardware_watchdog \defgroup hardware_watchdog hardware_watchdog \endcond + * \cond hardware_xosc \defgroup hardware_xosc hardware_xosc \endcond + * \cond hardware_powman hardware_powman + * \cond hardware_hazard3 hardware_hazard3 + * \cond hardware_riscv hardware_riscv + * @} * * \defgroup high_level High Level APIs * This group of libraries provide higher level functionality that isn't hardware related or provides a richer * set of functionality above the basic hardware interfaces * @{ - * \defgroup pico_async_context pico_async_context - * \defgroup pico_flash pico_flash - * \defgroup pico_i2c_slave pico_i2c_slave - * \defgroup pico_multicore pico_multicore - * \defgroup pico_rand pico_rand - * \defgroup pico_stdlib pico_stdlib - * \defgroup pico_sync pico_sync - * \defgroup pico_time pico_time - * \defgroup pico_unique_id pico_unique_id - * \defgroup pico_util pico_util + * \cond pico_aon_timer \defgroup pico_aon_timer pico_aon_timer \endcond + * \cond pico_async_context \defgroup pico_async_context pico_async_context \endcond + * \cond pico_bootsel_via_double_reset \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset \endcond + * \cond pico_flash \defgroup pico_flash pico_flash \endcond + * \cond pico_i2c_slave \defgroup pico_i2c_slave pico_i2c_slave \endcond + * \cond pico_multicore \defgroup pico_multicore pico_multicore \endcond + * \cond pico_rand \defgroup pico_rand pico_rand \endcond + * \cond pico_sha256 \defgroup pico_sha256 pico_sha256 \endcond + * \cond pico_stdlib \defgroup pico_stdlib pico_stdlib \endcond + * \cond pico_sync \defgroup pico_sync pico_sync \endcond + * \cond pico_time \defgroup pico_time pico_time \endcond + * \cond pico_unique_id \defgroup pico_unique_id pico_unique_id \endcond + * \cond pico_util \defgroup pico_util pico_util \endcond * @} * * \defgroup third_party Third-party Libraries * Third party libraries for implementing high level functionality. * @{ + * \cond tinyusb * \defgroup tinyusb_device tinyusb_device * \defgroup tinyusb_host tinyusb_host + * \endcond * @} * * \defgroup networking Networking Libraries * Functions for implementing networking * @{ - * \defgroup pico_btstack pico_btstack - * \defgroup pico_lwip pico_lwip - * \defgroup pico_cyw43_driver pico_cyw43_driver - * \defgroup pico_cyw43_arch pico_cyw43_arch + * \cond pico_btstack \defgroup pico_btstack pico_btstack \endcond + * \cond pico_lwip \defgroup pico_lwip pico_lwip \endcond + * \cond pico_cyw43_driver \defgroup pico_cyw43_driver pico_cyw43_driver \endcond + * \cond pico_cyw43_arch \defgroup pico_cyw43_arch pico_cyw43_arch \endcond * @} * * \defgroup runtime Runtime Infrastructure @@ -74,30 +95,36 @@ * language level and C library functions, as well as CMake INTERFACE libraries * abstracting the compilation and link steps in the SDK * @{ - * \defgroup boot_stage2 boot_stage2 - * \defgroup pico_base pico_base - * \defgroup pico_binary_info pico_binary_info - * \defgroup pico_bit_ops pico_bit_ops - * \defgroup pico_bootrom pico_bootrom - * \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset - * \defgroup pico_cxx_options pico_cxx_options - * \defgroup pico_divider pico_divider - * \defgroup pico_double pico_double - * \defgroup pico_float pico_float - * \defgroup pico_int64_ops pico_int64_ops - * \defgroup pico_malloc pico_malloc - * \defgroup pico_mem_ops pico_mem_ops - * \defgroup pico_platform pico_platform - * \defgroup pico_printf pico_printf - * \defgroup pico_runtime pico_runtime - * \defgroup pico_stdio pico_stdio - * \defgroup pico_standard_link pico_standard_link + * \cond boot_stage2 \defgroup boot_stage2 boot_stage2 \endcond + * \cond pico_atomic \defgroup pico_atomic pico_atomic \endcond + * \cond pico_base_headers \defgroup pico_base pico_base \endcond + * \cond pico_binary_info \defgroup pico_binary_info pico_binary_info \endcond + * \cond pico_bootrom \defgroup pico_bootrom pico_bootrom \endcond + * \cond pico_bit_ops \defgroup pico_bit_ops pico_bit_ops \endcond + * \cond pico_cxx_options \defgroup pico_cxx_options pico_cxx_options \endcond + * \cond pico_clib_interface \defgroup pico_clib_interface pico_clib_interface \endcond + * \cond pico_crt0 \defgroup pico_crt0 pico_crt0 \endcond + * \cond pico_divider \defgroup pico_divider pico_divider \endcond + * \cond pico_double \defgroup pico_double pico_double \endcond + * \cond pico_float \defgroup pico_float pico_float \endcond + * \cond pico_int64_ops \defgroup pico_int64_ops pico_int64_ops \endcond + * \cond pico_malloc \defgroup pico_malloc pico_malloc \endcond + * \cond pico_mem_ops \defgroup pico_mem_ops pico_mem_ops \endcond + * \cond pico_platform \defgroup pico_platform pico_platform \endcond + * \cond pico_printf \defgroup pico_printf pico_printf \endcond + * \cond pico_runtime \defgroup pico_runtime pico_runtime \endcond + * \cond pico_runtime_init \defgroup pico_runtime_init pico_runtime_init \endcond + * \cond pico_stdio \defgroup pico_stdio pico_stdio \endcond + * \cond pico_standard_binary_info \defgroup pico_standard_binary_info pico_standard_binary_info \endcond + * \cond pico_standard_link \defgroup pico_standard_link pico_standard_link \endcond * @} * * \defgroup misc External API Headers * Headers for interfaces that are shared with code outside of the SDK * @{ - * \defgroup boot_picoboot boot_picoboot - * \defgroup boot_uf2 boot_uf2 + * \cond boot_picobin_headers \defgroup boot_picobin_headers boot_picobin_headers \endcond + * \cond boot_picoboot_headers \defgroup boot_picoboot_headers boot_picoboot_headers \endcond + * \cond boot_uf2_headers \defgroup boot_uf2_headers boot_uf2_headers \endcond + * \cond pico_usb_reset_interface_headers \defgroup pico_usb_reset_interface_headers pico_usb_reset_interface_headers \endcond * @} */ diff --git a/docs/mainpage.md b/docs/mainpage.md index 01e541165..307fbb372 100644 --- a/docs/mainpage.md +++ b/docs/mainpage.md @@ -1,16 +1,16 @@ # Raspberry Pi Pico SDK -The Raspberry Pi Pico SDK (Software Development Kit), henceforth SDK, provides the headers, libraries and build system necessary to write programs for RP2040-based devices such as the Raspberry Pi Pico in C, C++ or assembly language. The SDK is designed to provide an API (Application Programming Interface) and programming environment that is familiar both to non-embedded C developers and embedded C developers alike. +The Raspberry Pi Pico SDK (Software Development Kit), henceforth SDK, provides the headers, libraries and build system necessary to write programs for RP-series microcontroller devices such as the Raspberry Pi Pico in C, C++ or assembly language. The SDK is designed to provide an API (Application Programming Interface) and programming environment that is familiar both to non-embedded C developers and embedded C developers alike. -A single program runs on the device at a time with a conventional `main()` method. Standard C/C++ libraries are supported along with APIs for accessing the RP2040’s hardware, including DMA, IRQs, and the wide variety of fixed-function peripherals and PIO (Programmable IO). +A single program runs on the device at a time with a conventional `main()` method. Standard C/C++ libraries are supported along with APIs for accessing the microcontroller's hardware, including DMA, IRQs, and the wide variety of fixed-function peripherals and PIO (Programmable IO). -Additionally the SDK provides higher-level libraries for dealing with timers, USB, synchronization and multi-core programming, along with additional high-level functionality built using PIO, such as audio. The SDK can be used to build anything from simple applications, or full-fledged runtime environments such as MicroPython, to low-level software such as the RP2040’s on-chip bootrom itself. +Additionally the SDK provides higher-level libraries for dealing with timers, USB, synchronization and multi-core programming, along with additional high-level functionality built using PIO, such as audio. The SDK can be used to build anything from simple applications, or full-fledged runtime environments such as MicroPython, to low-level software such as the microcontroller's on-chip bootrom itself. This documentation is generated from the SDK source tree using Doxygen. It provides basic information on the APIs used for each library, but does not provide usage information. Please refer to the Databooks for usage and more technical information. ## SDK Design -The RP2040 is a powerful chip, however it is an embedded environment, so both RAM and program space are at premium. Additionally the trade-offs between performance and other factors (e.g. edge-case error handling, runtime vs compile-time configuration) are necessarily much more visible to the developer than they might be on other higher-level platforms. +The RP-series microcontroller range are powerful chips, however they are used in an embedded environment, so both RAM and program space are at premium. Additionally the trade-offs between performance and other factors (e.g. edge-case error handling, runtime vs compile-time configuration) are necessarily much more visible to the developer than they might be on other higher-level platforms. The intention within the SDK has been for features to just work out of the box, with sensible defaults, but also to give the developer as much control and power as possible (if they want it) to fine-tune every aspect of the application they are building and the libraries used. @@ -20,7 +20,7 @@ The SDK uses CMake to manage the build. CMake is widely supported by IDEs (Integ Apart from being a widely-used build system for C/C++ development, CMake is fundamental to the way the SDK is structured, and how applications are configured and built. -The SDK builds an executable which is bare-metal, i.e. it includes the entirety of the code needed to run on the device (other than floating-point and other optimized code contained in the bootrom within the RP2040). +The SDK builds an executable which is bare-metal, i.e. it includes the entirety of the code needed to run on the device (other than device specific floating-point and other optimized code contained in the bootrom within the microcontroller). ## Examples diff --git a/docs/weblinks_page.md b/docs/weblinks_page.md index 7b84fc99d..4f96db752 100644 --- a/docs/weblinks_page.md +++ b/docs/weblinks_page.md @@ -4,6 +4,8 @@ The full documentation for the RP2040 and Raspberry Pi Pico board can be found a - [RP2040 Datasheet](https://rptl.io/rp2040-datasheet) - [Raspberry Pi Pico Datasheet](https://rptl.io/pico-datasheet) + - [RP235x Datasheet](https://rptl.io/rp2040-datasheet) + - [Raspberry Pi Pico2 Datasheet](https://rptl.io/pico-datasheet) - [Raspberry Pi Pico W Datasheet](https://rptl.io/picow-datasheet) - [Hardware design with RP2040](https://rptl.io/rp2040-design) - [Raspberry Pi Pico C/C++ SDK](https://rptl.io/pico-c-sdk) diff --git a/lib/cyw43-driver b/lib/cyw43-driver index 7ee0b7bd4..faf36381b 160000 --- a/lib/cyw43-driver +++ b/lib/cyw43-driver @@ -1 +1 @@ -Subproject commit 7ee0b7bd4a4fd13b5e03a0bab7f80491ae37e9ab +Subproject commit faf36381bad1f668a30172b6336c9a970966ef4c diff --git a/lib/mbedtls b/lib/mbedtls index a77287f8f..5a764e555 160000 --- a/lib/mbedtls +++ b/lib/mbedtls @@ -1 +1 @@ -Subproject commit a77287f8fa6b76f74984121fdafc8563147435c8 +Subproject commit 5a764e5555c64337ed17444410269ff21cb617b1 diff --git a/lib/tinyusb b/lib/tinyusb index 86c416d4c..423264289 160000 --- a/lib/tinyusb +++ b/lib/tinyusb @@ -1 +1 @@ -Subproject commit 86c416d4c0fb38432460b3e11b08b9de76941bf5 +Subproject commit 4232642899362fa5e9cf0dc59bad6f1f6d32c563 diff --git a/pico_sdk_init.cmake b/pico_sdk_init.cmake index 5153e2b01..48b44db38 100644 --- a/pico_sdk_init.cmake +++ b/pico_sdk_init.cmake @@ -41,13 +41,6 @@ if (NOT TARGET _pico_sdk_pre_init_marker) include(pico_utils) message("PICO_SDK_PATH is ${CMAKE_CURRENT_LIST_DIR}") - - include(pico_pre_load_platform) - - # We want to configure correct toolchain prior to project load - # todo perhaps this should be included by the platform instead? - include(pico_pre_load_toolchain) - macro(pico_sdk_init) if (NOT CMAKE_PROJECT_NAME) message(WARNING "pico_sdk_init() should be called after the project is created (and languages added)") @@ -90,4 +83,10 @@ if (NOT TARGET _pico_sdk_pre_init_marker) SET(${VAR} ${${VAR}} PARENT_SCOPE) endforeach() endmacro() + + include(pico_pre_load_platform) + + # We want to configure correct toolchain prior to project load + # todo perhaps this should be included by the platform instead? + include(pico_pre_load_toolchain) endif() diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake index bb7b050cc..37145ce85 100644 --- a/pico_sdk_version.cmake +++ b/pico_sdk_version.cmake @@ -1,18 +1,18 @@ -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, group=pico_base -# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, group=pico_base -set(PICO_SDK_VERSION_MAJOR 1) -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base -# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base -set(PICO_SDK_VERSION_MINOR 5) -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base -# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base -set(PICO_SDK_VERSION_REVISION 2) -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base -# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base -set(PICO_SDK_VERSION_PRE_RELEASE_ID develop) +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, default=Current SDK major version, group=pico_base +# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, default=Current SDK major version, group=pico_base +set(PICO_SDK_VERSION_MAJOR 2) +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, default=Current SDK minor version, group=pico_base +# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, default=Current SDK minor version, group=pico_base +set(PICO_SDK_VERSION_MINOR 0) +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, default=Current SDK revision, group=pico_base +# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, default=Current SDK revision, group=pico_base +set(PICO_SDK_VERSION_REVISION 0) +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, Optional SDK pre-release version identifier, default=Current SDK pre-release identifier, type=string, group=pico_base +# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, Optional SDK pre-release version identifier, default=Current SDK pre-release identifier, type=string, group=pico_base +#set(PICO_SDK_VERSION_PRE_RELEASE_ID develop) -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base -# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version string, type=string, default=Current SDK version string, group=pico_base +# PICO_CMAKE_CONFIG: PICO_SDK_VERSION_STRING, SDK version string, type=string, default=Current SDK version string, group=pico_base set(PICO_SDK_VERSION_STRING "${PICO_SDK_VERSION_MAJOR}.${PICO_SDK_VERSION_MINOR}.${PICO_SDK_VERSION_REVISION}") if (PICO_SDK_VERSION_PRE_RELEASE_ID) diff --git a/src/BUILD.bazel b/src/BUILD.bazel new file mode 100644 index 000000000..6f121f859 --- /dev/null +++ b/src/BUILD.bazel @@ -0,0 +1,26 @@ +package(default_visibility = ["//visibility:public"]) + +# This shim exists as a way to break internal header dependency cycles +# that occur within the dependency chain of the pico_platform target below. +alias( + name = "pico_platform_internal", + actual = select({ + "//bazel/constraint:host": "//src/host/pico_platform:pico_platform_internal", + "//conditions:default": "//src/rp2_common:pico_platform_internal", + }), + visibility = [ + "//src/common/boot_picobin_headers:__pkg__", + "//src/common/boot_picoboot_headers:__pkg__", + "//src/common/hardware_claim:__pkg__", + "//src/common/pico_base_headers:__pkg__", + "//src/common/pico_binary_info:__pkg__", + ], +) + +alias( + name = "pico_platform", + actual = select({ + "//bazel/constraint:host": "//src/host/pico_platform", + "//conditions:default": "//src/rp2_common:pico_platform", + }), +) diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 1316c56ab..f21db2d80 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -1,9 +1,15 @@ cmake_policy(SET CMP0079 NEW) # allow inserting of dependencies into our INTERFACE libraries -set(PICO_PLATFORM_CMAKE_FILE "" CACHE INTERNAL "") +set(PICO_PLATFORM_CMAKE_FILE "${PICO_PLATFORM_CMAKE_FILE}" CACHE INTERNAL "") set(PICO_DOXYGEN_PATHS "" CACHE INTERNAL "") # generated each time +set(PICO_DOXYGEN_EXCLUDE_PATHS "" CACHE INTERNAL "") # generated each time +set(PICO_DOXYGEN_PRE_DEFINES "" CACHE INTERNAL "") # generated each time +set(PICO_DOXYGEN_ENABLED_SECTIONS "" CACHE INTERNAL "") # generated each time +if (NOT PICO_PLATFORM_CMAKE_DIR) + set(PICO_PLATFORM_CMAKE_DIR ${CMAKE_CURRENT_LIST_DIR}) +endif() if (NOT PICO_PLATFORM_CMAKE_FILE) - set(PICO_PLATFORM_CMAKE_FILE ${CMAKE_CURRENT_LIST_DIR}/${PICO_PLATFORM}.cmake CACHE INTERNAL "") + set(PICO_PLATFORM_CMAKE_FILE ${PICO_PLATFORM_CMAKE_DIR}/${PICO_PLATFORM}.cmake CACHE INTERNAL "") endif () if (NOT EXISTS "${PICO_PLATFORM_CMAKE_FILE}") @@ -11,17 +17,28 @@ if (NOT EXISTS "${PICO_PLATFORM_CMAKE_FILE}") Either specify a valid PICO_PLATFORM (or PICO_PLATFORM_CMAKE_FILE).") endif () -# Initialize board related build/compile settings -include(${CMAKE_CURRENT_LIST_DIR}/board_setup.cmake) - # call add_subdirectory(subdir) unless SKIP_SUBDIR evaluates to true +# second argument is optional path function(pico_add_subdirectory subdir) # todo add option to disable skip flag string(TOUPPER ${subdir} subdir_upper) + # we do not include any path part of the subdir + get_filename_component(subdir_upper ${subdir_upper} NAME) set(replace_flag SKIP_${subdir_upper}) if (NOT ${replace_flag}) - add_subdirectory(${subdir}) - else () + string(TOUPPER ${subdir} subdir_upper) + set(replace_flag SKIP_${subdir_upper}) + if (${ARGC} GREATER 1) + # argv1 is the root where the subdir is relative to + add_subdirectory(${ARGV1}/${subdir} ${subdir}) + # todo make this optional? + pico_add_doxygen(${ARGV1}/${subdir}) + else() + add_subdirectory(${subdir}) + # todo make this optional? + pico_add_doxygen(${subdir}) + endif() + else() message("Not including ${subdir} because ${replace_flag} defined.") endif () pico_promote_common_scope_vars() @@ -57,11 +74,12 @@ endfunction() # add map file generation for the given target function(pico_add_map_output TARGET) + pico_get_runtime_output_directory(${TARGET} output_path) get_target_property(target_type ${TARGET} TYPE) if ("EXECUTABLE" STREQUAL "${target_type}") - target_link_options(${TARGET} PRIVATE "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map") + target_link_options(${TARGET} PRIVATE "LINKER:-Map=${output_path}$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map") else () - target_link_options(${TARGET} INTERFACE "LINKER:-Map=$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map") + target_link_options(${TARGET} INTERFACE "LINKER:-Map=${output_path}$>,$,$>${CMAKE_EXECUTABLE_SUFFIX}.map") endif () endfunction() @@ -102,7 +120,7 @@ macro(pico_simple_hardware_headers_target NAME) if (NOT TARGET hardware_${NAME}_headers) add_library(hardware_${NAME}_headers INTERFACE) - target_include_directories(hardware_${NAME}_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(hardware_${NAME}_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(hardware_${NAME}_headers INTERFACE pico_base_headers) if (NOT PICO_NO_HARDWARE) target_link_libraries(hardware_${NAME}_headers INTERFACE hardware_structs hardware_claim_headers) @@ -122,7 +140,7 @@ macro(pico_simple_hardware_headers_only_target NAME) add_library(hardware_${NAME}_headers INTERFACE) # a headers only target should still have an explicit _headers library for consistency - target_include_directories(hardware_${NAME}_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(hardware_${NAME}_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(hardware_${NAME}_headers INTERFACE pico_base_headers) if (NOT PICO_NO_HARDWARE) target_link_libraries(hardware_${NAME}_headers INTERFACE hardware_structs) @@ -154,12 +172,30 @@ macro(pico_simple_hardware_impl_target NAME) endif() endmacro() +function(pico_add_doxygen_pre_define PRE_DEFINE) + list(APPEND PICO_DOXYGEN_PRE_DEFINES "${PRE_DEFINE}") + set(PICO_DOXYGEN_PRE_DEFINES "${PICO_DOXYGEN_PRE_DEFINES}" CACHE INTERNAL "") +endfunction() + +function(pico_add_doxygen_enabled_section ENABLED_SECTION) + list(APPEND PICO_DOXYGEN_ENABLED_SECTIONS "${ENABLED_SECTION}") + set(PICO_DOXYGEN_ENABLED_SECTIONS "${PICO_DOXYGEN_ENABLED_SECTIONS}" CACHE INTERNAL "") +endfunction() + function(pico_add_doxygen SOURCE_DIR) - set(PICO_DOXYGEN_PATHS "${PICO_DOXYGEN_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "") + if (NOT IS_ABSOLUTE "${SOURCE_DIR}") + get_filename_component(SOURCE_DIR "${SOURCE_DIR}" ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + endif() + list(APPEND PICO_DOXYGEN_PATHS "${SOURCE_DIR}") + set(PICO_DOXYGEN_PATHS "${PICO_DOXYGEN_PATHS}" CACHE INTERNAL "") endfunction() function(pico_add_doxygen_exclude SOURCE_DIR) - set(PICO_DOXYGEN_EXCLUDE_PATHS "${PICO_DOXYGEN_EXCLUDE_PATHS} ${SOURCE_DIR}" CACHE INTERNAL "") + if (NOT IS_ABSOLUTE "${SOURCE_DIR}") + get_filename_component(SOURCE_DIR "${SOURCE_DIR}" ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + endif() + list(APPEND PICO_DOXYGEN_EXCLUDE_PATHS "${SOURCE_DIR}") + set(PICO_DOXYGEN_EXCLUDE_PATHS "${PICO_DOXYGEN_EXCLUDE_PATHS}" CACHE INTERNAL "") endfunction() include(${PICO_PLATFORM_CMAKE_FILE}) diff --git a/src/board_setup.cmake b/src/board_setup.cmake deleted file mode 100644 index 48839f737..000000000 --- a/src/board_setup.cmake +++ /dev/null @@ -1,31 +0,0 @@ -# PICO_CMAKE_CONFIG: PICO_BOARD, The board name being built for. This is overridable from the user environment, type=string, default=pico, group=build -if (DEFINED ENV{PICO_BOARD}) - set(PICO_BOARD $ENV{PICO_BOARD}) - message("Using PICO_BOARD from environment ('${PICO_BOARD}')") -else() - if (NOT PICO_BOARD) - set(PICO_BOARD "pico") - pico_message("Defaulting PICO target board to ${PICO_BOARD} since not specified.") - else() - message("PICO target board is ${PICO_BOARD}.") - endif() -endif() -set(PICO_BOARD ${PICO_BOARD} CACHE STRING "PICO target board (e.g. pico)" FORCE) - -# PICO_CMAKE_CONFIG: PICO_BOARD_CMAKE_DIRS, Directories to look for .cmake in. This is overridable from the user environment, type=list, group=build -if (DEFINED ENV{PICO_BOARD_CMAKE_DIRS}) - set(PICO_BOARD_CMAKE_DIRS $ENV{PICO_BOARD_CMAKE_DIRS}) - message("Using PICO_BOARD_CMAKE_DIRS from environment ('${PICO_BOARD_CMAKE_DIRS}')") -endif() - -list(APPEND PICO_BOARD_CMAKE_DIRS ${CMAKE_CURRENT_LIST_DIR}/boards) - -pico_find_in_paths(PICO_BOARD_CMAKE_FILE PICO_BOARD_CMAKE_DIRS ${PICO_BOARD}.cmake) -if (EXISTS "${PICO_BOARD_CMAKE_FILE}") - message("Using CMake board configuration from ${PICO_BOARD_CMAKE_FILE}") - include(${PICO_BOARD_CMAKE_FILE} board_config) -else() - include(boards/generic_board.cmake) -endif() - -list(APPEND PICO_INCLUDE_DIRS ${CMAKE_CURRENT_LIST_DIR}/boards/include) # so boards/foo.h can be explicitly included diff --git a/src/boards/BUILD.bazel b/src/boards/BUILD.bazel index ba0dfa27d..94d1b3ed2 100644 --- a/src/boards/BUILD.bazel +++ b/src/boards/BUILD.bazel @@ -5,41 +5,84 @@ package(default_visibility = ["//visibility:public"]) # Known board choices: BOARD_CHOICES = [ + "0xcb_helios", + "adafruit_feather_rp2040_usb_host", "adafruit_feather_rp2040", "adafruit_itsybitsy_rp2040", "adafruit_kb2040", "adafruit_macropad_rp2040", "adafruit_qtpy_rp2040", "adafruit_trinkey_qt2040", + "amethyst_fpga", + "archi", "arduino_nano_rp2040_connect", + "cytron_maker_pi_rp2040", "datanoisetv_rp2040_dsp", + "defcon32_badge", "eetree_gamekit_rp2040", "garatronic_pybstick26_rp2040", + "gen4_rp2350_24", + "gen4_rp2350_24ct", + "gen4_rp2350_24t", + "gen4_rp2350_28", + "gen4_rp2350_28ct", + "gen4_rp2350_28t", + "gen4_rp2350_32", + "gen4_rp2350_32ct", + "gen4_rp2350_32t", + "gen4_rp2350_35", + "gen4_rp2350_35ct", + "gen4_rp2350_35t", + "hellbender_2350A_devboard", + "ilabs_challenger_rp2350_bconnect", + "ilabs_challenger_rp2350_wifi_ble", + "ilabs_opendec02", + "melopero_perpetuo_rp2350_lora", "melopero_shake_rp2040", + "metrotech_xerxes_rp2040", + "net8086_usb_interposer", "none", "nullbits_bit_c_pro", - "pico", + "phyx_rick_tny_rp2350", + "pi-plates_micropi", "pico_w", + "pico", + "pico2", "pimoroni_badger2040", "pimoroni_interstate75", "pimoroni_keybow2040", "pimoroni_motor2040", "pimoroni_pga2040", + "pimoroni_pga2350", + "pimoroni_pico_plus2_rp2350", "pimoroni_picolipo_16mb", "pimoroni_picolipo_4mb", "pimoroni_picosystem", "pimoroni_plasma2040", + "pimoroni_plasma2350", "pimoroni_servo2040", - "pimoroni_tiny2040", "pimoroni_tiny2040_2mb", + "pimoroni_tiny2040", + "pimoroni_tiny2350", "pololu_3pi_2040_robot", + "pololu_zumo_2040_robot", "seeed_xiao_rp2040", - "solderparty_rp2040_stamp", + "seeed_xiao_rp2350", "solderparty_rp2040_stamp_carrier", "solderparty_rp2040_stamp_round_carrier", + "solderparty_rp2040_stamp", + "solderparty_rp2350_stamp_xl", + "solderparty_rp2350_stamp", "sparkfun_micromod", + "sparkfun_promicro_rp2350", "sparkfun_promicro", "sparkfun_thingplus", + "switchscience_picossci2_conta_base", + "switchscience_picossci2_dev_board", + "switchscience_picossci2_micro", + "switchscience_picossci2_rp2350_breakout", + "switchscience_picossci2_tiny", + "tinycircuits_thumby_color_rp2350", "vgaboard", "waveshare_rp2040_lcd_0.96", "waveshare_rp2040_lcd_1.28", @@ -47,14 +90,11 @@ BOARD_CHOICES = [ "waveshare_rp2040_plus_16mb", "waveshare_rp2040_plus_4mb", "waveshare_rp2040_zero", - "wiznet_w5100s_evb_pico", - "cytron_maker_pi_rp2040", - "metrotech_xerxes_rp2040", - "pololu_zumo_2040_robot", "weact_studio_rp2040_16mb", "weact_studio_rp2040_2mb", "weact_studio_rp2040_4mb", "weact_studio_rp2040_8mb", + "wiznet_w5100s_evb_pico", ] BOARD_CHOICE_FILES = ["include/boards/" + c + ".h" for c in BOARD_CHOICES] diff --git a/src/boards/include/boards/0xcb_helios.h b/src/boards/include/boards/0xcb_helios.h index e9df358eb..e06c552b5 100644 --- a/src/boards/include/boards/0xcb_helios.h +++ b/src/boards/include/boards/0xcb_helios.h @@ -12,6 +12,8 @@ //------------------------------------------------------------------------------------------ // Board definition for the 0xCB Helios +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_0XCB_HELIOS_H #define _BOARDS_0XCB_HELIOS_H @@ -71,10 +73,10 @@ #endif // board has 16M onboard flash +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED diff --git a/src/boards/include/boards/adafruit_feather_rp2040.h b/src/boards/include/boards/adafruit_feather_rp2040.h index 2da8e7009..c9a6d618d 100644 --- a/src/boards/include/boards/adafruit_feather_rp2040.h +++ b/src/boards/include/boards/adafruit_feather_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ADAFRUIT_FEATHER_RP2040_H #define _BOARDS_ADAFRUIT_FEATHER_RP2040_H @@ -81,10 +83,10 @@ #define PICO_FLASH_SPI_CLKDIV 4 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/adafruit_feather_rp2040_usb_host.h b/src/boards/include/boards/adafruit_feather_rp2040_usb_host.h index 79193e395..6175b9423 100644 --- a/src/boards/include/boards/adafruit_feather_rp2040_usb_host.h +++ b/src/boards/include/boards/adafruit_feather_rp2040_usb_host.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ADAFRUIT_FEATHER_RP2040_USB_HOST_H #define _BOARDS_ADAFRUIT_FEATHER_RP2040_USB_HOST_H @@ -77,6 +79,7 @@ #define PICO_FLASH_SPI_CLKDIV 4 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif diff --git a/src/boards/include/boards/adafruit_itsybitsy_rp2040.h b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h index c56f079dc..ee5cf9cd4 100644 --- a/src/boards/include/boards/adafruit_itsybitsy_rp2040.h +++ b/src/boards/include/boards/adafruit_itsybitsy_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H #define _BOARDS_ADAFRUIT_ITSYBITSY_RP2040_H @@ -84,10 +86,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/adafruit_kb2040.h b/src/boards/include/boards/adafruit_kb2040.h index 935308273..f63fc77e3 100644 --- a/src/boards/include/boards/adafruit_kb2040.h +++ b/src/boards/include/boards/adafruit_kb2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ADAFRUIT_KB2040_H #define _BOARDS_ADAFRUIT_KB2040_H @@ -76,10 +78,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/adafruit_macropad_rp2040.h b/src/boards/include/boards/adafruit_macropad_rp2040.h index 3c0c525b5..672ada963 100644 --- a/src/boards/include/boards/adafruit_macropad_rp2040.h +++ b/src/boards/include/boards/adafruit_macropad_rp2040.h @@ -12,6 +12,8 @@ #ifndef _BOARDS_ADAFRUIT_MACROPAD_RP2040_H #define _BOARDS_ADAFRUIT_MACROPAD_RP2040_H +// pico_cmake_set PICO_PLATFORM=rp2040 + // For board detection #define ADAFRUIT_MACROPAD_RP2040 @@ -171,10 +173,10 @@ #define PICO_FLASH_SPI_CLKDIV 4 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_FLOAT_SUPPORT_ROM_V1 #define PICO_FLOAT_SUPPORT_ROM_V1 0 diff --git a/src/boards/include/boards/adafruit_qtpy_rp2040.h b/src/boards/include/boards/adafruit_qtpy_rp2040.h index 24184c27f..722d23003 100644 --- a/src/boards/include/boards/adafruit_qtpy_rp2040.h +++ b/src/boards/include/boards/adafruit_qtpy_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ADAFRUIT_QTPY_RP2040_H #define _BOARDS_ADAFRUIT_QTPY_RP2040_H @@ -83,10 +85,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/adafruit_trinkey_qt2040.h b/src/boards/include/boards/adafruit_trinkey_qt2040.h index f9b49df74..06e294940 100644 --- a/src/boards/include/boards/adafruit_trinkey_qt2040.h +++ b/src/boards/include/boards/adafruit_trinkey_qt2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ADAFRUIT_TRINKEY_QT2040_H #define _BOARDS_ADAFRUIT_TRINKEY_QT2040_H @@ -61,10 +63,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/amethyst_fpga.h b/src/boards/include/boards/amethyst_fpga.h new file mode 100644 index 000000000..d41dff41e --- /dev/null +++ b/src/boards/include/boards/amethyst_fpga.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// FIXME delete this file before release (board file for Amethyst FPGA platform) + +#ifndef _BOARDS_AMETHYST_FPGA_H +#define _BOARDS_AMETHYST_FPGA_H + +#if !PICO_RP2350 +#error "Invalid PICO_PLATFORM for amethyst_fpga.h: must be rp2350 or rp2350-riscv" +#endif + +// For board detection +#define RASPBERRYPI_AMETHYST_FPGA + +#define PICO_NO_FPGA_CHECK 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 46 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 47 +#endif +// Match bootrom UART baud rate of 1 Mbaud: +#ifndef PICO_DEFAULT_UART_BAUD_RATE +#define PICO_DEFAULT_UART_BAUD_RATE 1000000 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +#define PICO_SD_CLK_PIN 18 +#define PICO_SD_CMD_PIN 19 +#define PICO_SD_DAT0_PIN 20 + +#define PICO_ON_FPGA 1 + +#define PICO_SCANVIDEO_COLOR_PIN_COUNT 16 +#define PICO_SCANVIDEO_DPI_PIXEL_RSHIFT 0u +#define PICO_SCANVIDEO_DPI_PIXEL_GSHIFT 6u +#define PICO_SCANVIDEO_DPI_PIXEL_BSHIFT 11u + +#define PICO_SCANVIDEO_48MHZ 1 +#define PICO_AUDIO_I2S_DATA_PIN 29 +#define PICO_AUDIO_I2S_CLOCK_PIN_BASE 30 + +#define PICO_AUDIO_PWM_L_PIN 28 +#define PICO_AUDIO_PWM_R_PIN 27 + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif +#endif diff --git a/src/boards/include/boards/archi.h b/src/boards/include/boards/archi.h index 4cf0356a5..13b7d7ea0 100644 --- a/src/boards/include/boards/archi.h +++ b/src/boards/include/boards/archi.h @@ -11,6 +11,8 @@ // This header may be included by other board headers as "boards/archi.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ARCHI_H #define _BOARDS_ARCHI_H @@ -102,9 +104,9 @@ #define PICO_FLASH_SPI_CLKDIV 4 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) #endif - #endif diff --git a/src/boards/include/boards/arduino_nano_rp2040_connect.h b/src/boards/include/boards/arduino_nano_rp2040_connect.h index 39c6564fb..9cd3035f5 100644 --- a/src/boards/include/boards/arduino_nano_rp2040_connect.h +++ b/src/boards/include/boards/arduino_nano_rp2040_connect.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H #define _BOARDS_ARDUINO_NANO_RP2040_CONNECT_H @@ -72,10 +74,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/cytron_maker_pi_rp2040.h b/src/boards/include/boards/cytron_maker_pi_rp2040.h index 77dd424c0..9d2f0eb69 100644 --- a/src/boards/include/boards/cytron_maker_pi_rp2040.h +++ b/src/boards/include/boards/cytron_maker_pi_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_CYTRON_MAKER_PI_RP2040_H #define _BOARDS_CYTRON_MAKER_PI_RP2040_H @@ -177,10 +179,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/datanoisetv_rp2040_dsp.h b/src/boards/include/boards/datanoisetv_rp2040_dsp.h index 49a357bc6..ae583baa4 100644 --- a/src/boards/include/boards/datanoisetv_rp2040_dsp.h +++ b/src/boards/include/boards/datanoisetv_rp2040_dsp.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/datanoisetv_rp2040_dsp.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_DATANOISETV_RP2040_DSP_H #define _BOARDS_DATANOISETV_RP2040_DSP_H @@ -38,10 +40,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 #endif diff --git a/src/boards/include/boards/defcon32_badge.h b/src/boards/include/boards/defcon32_badge.h new file mode 100644 index 000000000..6e99ca58a --- /dev/null +++ b/src/boards/include/boards/defcon32_badge.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// NOTE: since there is no UART on the badge, you should probably pass: +// -DPICO_BOARD=defcon32_badge -DPICO_STDIO_USB=1 -DPICO_STDIO_UART+0 +// when building to set up stdio over USB CDC by default +#define PICO_DEFAULT_UART 0 +#define PICO_DEFAULT_UART_TX_PIN 30 +#define PICO_DEFAULT_UART_RX_PIN 31 + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_DEFCON32_BADGE_H +#define _BOARDS_DEFCON32_BADGE_H + +// For board detection +#define DEFCON32_BADGE + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +#define DEFCON32_BADGE_SRAM_CS_PIN 0 +#define DEFCON32_BADGE_TOUCH_INT_PIN 1 +#define DEFCON32_BADGE_I2C_SDA_PIN 2 +#define DEFCON32_BADGE_I2C_SDL_PIN 3 +#define DEFCON32_BADGE_WS2812_PIN 4 +#define DEFCON32_BADGE_DISPLAY_RS_PIN 5 +#define DEFCON32_BADGE_DISPLAY_DO_PIN 6 +#define DEFCON32_BADGE_IR_SD_PIN 7 +#define DEFCON32_BADGE_DISPLAY_SCK_PIN 8 +#define DEFCON32_BADGE_DISPLAY_CS_PIN 9 +#define DEFCON32_BADGE_DISPLAY_BL_PIN 10 +#define DEFCON32_BADGE_SYS_POWER_CONTROL_PIN 11 +#define DEFCON32_BADGE_SPI_MISO_PIN 12 +#define DEFCON32_BADGE_SD_CS_PIN 13 +#define DEFCON32_BADGE_SPI_CK_PIN 14 +#define DEFCON32_BADGE_SPI_MOSI_PIN 15 +#define DEFCON32_BADGE_SW_RIGHT_PIN 16 +#define DEFCON32_BADGE_SW_DOWN_PIN 17 +#define DEFCON32_BADGE_SW_UP_PIN 18 +#define DEFCON32_BADGE_SW_LEFT_PIN 19 +#define DEFCON32_BADGE_SW_B_PIN 20 +#define DEFCON32_BADGE_SW_A_PIN 21 +#define DEFCON32_BADGE_SW_START_PIN 22 +#define DEFCON32_BADGE_SW_SELECT_PIN 23 +#define DEFCON32_BADGE_SW_FN_PIN 24 +#define DEFCON32_BADGE_SPEAKER_OUT_PIN 25 +#define DEFCON32_BADGE_IR_RX_PIN 27 +#define DEFCON32_BADGE_IR_TX_PIN 28 + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN DEFCON32_BADGE_WS2812_PIN +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN DEFCON32_BADGE_I2C_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN DEFCON32_BADGE_I2C_SDL_PIN +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN DEFCON32_BADGE_SPI_CK_PIN +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN DEFCON32_BADGE_SPI_MISO_PIN +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN DEFCON32_BADGE_SPI_MOSI_PIN +#endif +// multiple devices, so this doesn't make much sense +// no PICO_DEFAULT_SPI_CSN_PIN + +#ifndef PICO_AUDIO_PWM_L_PIN +#define PICO_AUDIO_PWM_L_PIN DEFCON32_BADGE_SPEAKER_OUT_PIN +#endif + +#ifndef PICO_AUDIO_PWM_MONO_PIN +#define PICO_AUDIO_PWM_MONO_PIN PICO_AUDIO_PWM_L_PIN +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif + + diff --git a/src/boards/include/boards/eetree_gamekit_rp2040.h b/src/boards/include/boards/eetree_gamekit_rp2040.h index f00714733..3df871988 100644 --- a/src/boards/include/boards/eetree_gamekit_rp2040.h +++ b/src/boards/include/boards/eetree_gamekit_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_EETREE_GAMEKIT_RP2040_H #define _BOARDS_EETREE_GAMEKIT_RP2040_H @@ -67,6 +69,7 @@ #ifndef PICO_FLASH_SPI_CLKDIV #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif diff --git a/src/boards/include/boards/garatronic_pybstick26_rp2040.h b/src/boards/include/boards/garatronic_pybstick26_rp2040.h index d1c0298d4..d245c8209 100644 --- a/src/boards/include/boards/garatronic_pybstick26_rp2040.h +++ b/src/boards/include/boards/garatronic_pybstick26_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_GARATRONIC_PYBSTICK26_RP2040_H #define _BOARDS_GARATRONIC_PYBSTICK26_RP2040_H @@ -68,10 +70,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (1 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (1 * 1024 * 1024) #endif - // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) // Linear regulator on Pybstick26 //#define PICO_SMPS_MODE_PIN 23 diff --git a/src/boards/include/boards/gen4_rp2350_24.h b/src/boards/include/boards/gen4_rp2350_24.h new file mode 100644 index 000000000..c569c15cb --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_24.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_24 +#define _BOARDS_GEN4_RP2350_24 + +// For board detection +#define GEN4_RP2350_24 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_NONE +#define LCD_TOUCH_POINTS 0 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_24ct.h b/src/boards/include/boards/gen4_rp2350_24ct.h new file mode 100644 index 000000000..2f6f15429 --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_24ct.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_24CT +#define _BOARDS_GEN4_RP2350_24CT + +// For board detection +#define GEN4_RP2350_24CT // CLB variants are exactly the same in operation + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_CTP_FT +#define LCD_TOUCH_POINTS 2 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_24t.h b/src/boards/include/boards/gen4_rp2350_24t.h new file mode 100644 index 000000000..2d01017b8 --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_24t.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_24T +#define _BOARDS_GEN4_RP2350_24T + +// For board detection +#define GEN4_RP2350_24T + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_4WIRE +#define LCD_TOUCH_POINTS 1 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_28.h b/src/boards/include/boards/gen4_rp2350_28.h new file mode 100644 index 000000000..804b2a99d --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_28.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_28 +#define _BOARDS_GEN4_RP2350_28 + +// For board detection +#define GEN4_RP2350_28 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_NONE +#define LCD_TOUCH_POINTS 0 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_28ct.h b/src/boards/include/boards/gen4_rp2350_28ct.h new file mode 100644 index 000000000..1714ef115 --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_28ct.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_28CT +#define _BOARDS_GEN4_RP2350_28CT + +// For board detection +#define GEN4_RP2350_28CT // CLB variants are exactly the same in operation + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_CTP_FT +#define LCD_TOUCH_POINTS 2 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_28t.h b/src/boards/include/boards/gen4_rp2350_28t.h new file mode 100644 index 000000000..b61c230e8 --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_28t.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_28T +#define _BOARDS_GEN4_RP2350_28T + +// For board detection +#define GEN4_RP2350_28T + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_4WIRE +#define LCD_TOUCH_POINTS 1 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_32.h b/src/boards/include/boards/gen4_rp2350_32.h new file mode 100644 index 000000000..9660a4776 --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_32.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_32 +#define _BOARDS_GEN4_RP2350_32 + +// For board detection +#define GEN4_RP2350_32 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_NONE +#define LCD_TOUCH_POINTS 0 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_32ct.h b/src/boards/include/boards/gen4_rp2350_32ct.h new file mode 100644 index 000000000..9f883d4fb --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_32ct.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_32CT +#define _BOARDS_GEN4_RP2350_32CT + +// For board detection +#define GEN4_RP2350_32CT // CLB variants are exactly the same in operation + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_CTP_FT +#define LCD_TOUCH_POINTS 5 +#define LCD_TOUCH_MIRROR_Y + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_32t.h b/src/boards/include/boards/gen4_rp2350_32t.h new file mode 100644 index 000000000..04f4e0c0b --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_32t.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_32T +#define _BOARDS_GEN4_RP2350_32T + +// For board detection +#define GEN4_RP2350_32T + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 240 +#define LCD_HEIGHT 320 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_4WIRE +#define LCD_TOUCH_POINTS 1 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_35.h b/src/boards/include/boards/gen4_rp2350_35.h new file mode 100644 index 000000000..d333c22f4 --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_35.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_35 +#define _BOARDS_GEN4_RP2350_35 + +// For board detection +#define GEN4_RP2350_35 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 320 +#define LCD_HEIGHT 480 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_NONE +#define LCD_TOUCH_POINTS 0 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_35ct.h b/src/boards/include/boards/gen4_rp2350_35ct.h new file mode 100644 index 000000000..778e1995e --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_35ct.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_35CT +#define _BOARDS_GEN4_RP2350_35CT + +// For board detection +#define GEN4_RP2350_35CT // CLB variants are exactly the same in operation + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 320 +#define LCD_HEIGHT 480 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_CTP_FT +#define LCD_TOUCH_POINTS 5 +#define LCD_TOUCH_MIRROR_Y + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/gen4_rp2350_35t.h b/src/boards/include/boards/gen4_rp2350_35t.h new file mode 100644 index 000000000..832337253 --- /dev/null +++ b/src/boards/include/boards/gen4_rp2350_35t.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_GEN4_RP2350_35T +#define _BOARDS_GEN4_RP2350_35T + +// For board detection +#define GEN4_RP2350_35T + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 4 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 5 +#endif + +// --- LED --- +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 8 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 9 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 42 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 43 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 44 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 45 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// 4DLCD Interface + +#define PORTRAIT 0 +#define LANDSCAPE 1 +#define PORTRAIT_R 2 +#define LANDSCAPE_R 3 + +#define LCD_ORIENTATION PORTRAIT +#define LCD_WIDTH 320 +#define LCD_HEIGHT 480 +#define LCD_BACKLIGHT 17 +#define LCD_RS_PIN 18 +#define LCD_WR_PIN 19 +#define LCD_RD_PIN 20 +#define LCD_DATA0_PIN 21 +#define LCD_RESET 37 +#define LCD_TOUCH_INT 38 +#define LCD_TOUCH_SCL 39 +#define LCD_TOUCH_SDA 46 +#define LCD_TOUCH_RST 47 +#define LCD_TOUCH_YD LCD_TOUCH_INT +#define LCD_TOUCH_XL LCD_TOUCH_SCL +#define LCD_TOUCH_YU LCD_TOUCH_RST +#define LCD_TOUCH_XR LCD_TOUCH_SDA +#define LCD_TOUCH_I2C i2c1 +#define LCD_TOUCH_4WIRE +#define LCD_TOUCH_POINTS 1 + +#define LCD_SD_CLK 10 +#define LCD_SD_CMD 11 +#define LCD_SD_D0 12 +#define LCD_SD_D1 13 +#define LCD_SD_D2 14 +#define LCD_SD_D3 15 + +#endif diff --git a/src/boards/include/boards/hellbender_2350A_devboard.h b/src/boards/include/boards/hellbender_2350A_devboard.h new file mode 100644 index 000000000..03895e1b4 --- /dev/null +++ b/src/boards/include/boards/hellbender_2350A_devboard.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +#ifndef _BOARDS_HB_2350A_H +#define _BOARDS_HB_2350A_H + +// pico_cmake_set PICO_PLATFORM=rp2350 + +// For board detection +#define HELLBENDER_2350A_DEVBOARD + +// Pin aliases +#define HB_2350A_XIP_CS1_PIN 0 +#define HB_2350A_IMU_INT_PIN 1 +#define HB_2350A_USER_QWIIC_SDA_PIN 2 +#define HB_2350A_USER_QWIIC_SCL_PIN 3 +#define HB_2350A_RTC_INT_PIN 8 +#define HB_2350A_SDCARD_CS_PIN 9 +#define HB_2350A_LORA_IO1_PIN 10 +#define HB_2350A_LORA_IO3_PIN 11 +#define HB_2350A_LORA_CS_PIN 21 +#define HB_2350A_RTC_CLKIN_PIN 22 +#define HB_2350A_IMU_CLKOUT_PIN 23 +#define HB_2350A_LORA_BUSY_PIN 24 +#define HB_2350A_FUSB307_INT_PIN 25 +#define HB_2350A_LORA_RESET_PIN 29 + +// --- UART --- +// Note, conflicts with HSTX range +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 12 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 13 +#endif + +// no PICO_DEFAULT_LED_PIN +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 7 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/ilabs_challenger_rp2350_bconnect.h b/src/boards/include/boards/ilabs_challenger_rp2350_bconnect.h new file mode 100644 index 000000000..b0bbebe28 --- /dev/null +++ b/src/boards/include/boards/ilabs_challenger_rp2350_bconnect.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/ilabs_challenger_rp2350_bconnect.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_CHALLENGER_RP2350_BCONNECT_H +#define _BOARDS_CHALLENGER_RP2350_BCONNECT_H + +// For board detection +#define ILABS_CHALLENGER_RP2350_BCONNECT + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 12 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 13 +#endif + +// PICO_DEFAULT_LED_PIN +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 7 +#endif + +// PICO_DEFAULT_WS2812_PIN +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 22 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 20 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 21 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/ilabs_challenger_rp2350_wifi_ble.h b/src/boards/include/boards/ilabs_challenger_rp2350_wifi_ble.h new file mode 100644 index 000000000..29ac3df3e --- /dev/null +++ b/src/boards/include/boards/ilabs_challenger_rp2350_wifi_ble.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/ilabs_challenger_rp2350_wifi_ble.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_CHALLENGER_RP2350_WIFI_BLE_H +#define _BOARDS_CHALLENGER_RP2350_WIFI_BLE_H + +// For board detection +#define ILABS_CHALLENGER_RP2350_WIFI_BLE + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 12 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 13 +#endif + +// PICO_DEFAULT_LED_PIN +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 7 +#endif + +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 20 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 21 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// Board specific helper macros +// Types of valid modules on the board +#define ESP32C6_MINI_1 1 +#define ESP32C3_MINI_1 2 + +// Specifies the default module used on this board +#ifndef ILABS_ONBOARD_ESP_MODULE +#define ILABS_ONBOARD_ESP_MODULE ESP32C6_MINI_1 +#endif + +// ESP module control signals +#ifndef ILABS_DEFAULT_ESP_MODULE_RST_PIN +#define ILABS_DEFAULT_ESP_MODULE_RST_PIN 15 +#endif + +#ifndef ILABS_DEFAULT_ESP_MODULE_BOOT_MODE_PIN +#define ILABS_DEFAULT_ESP_MODULE_BOOT_MODE_PIN 14 +#endif + +// ESP module UART definitions +#ifndef ILABS_ESP_AT_UART +#define ILABS_ESP_AT_UART 1 +#endif + +#ifndef ILABS_DEFAULT_ESP_AT_TX_PIN +#define ILABS_DEFAULT_ESP_AT_TX_PIN 4 +#endif + +#ifndef ILABS_DEFAULT_ESP_AT_RX_PIN +#define ILABS_DEFAULT_ESP_AT_RX_PIN 5 +#endif + +// ESP module SPI definitions +#ifndef ILABS_DEFAULT_ESP_SPI +#define ILABS_DEFAULT_ESP_SPI 1 +#endif + +#ifndef ILABS_DEFAULT_ESP_SPI_MISO_PIN +#define ILABS_DEFAULT_ESP_SPI_MISO_PIN 8 +#endif + +#ifndef ILABS_DEFAULT_ESP_SPI_MOSI_PIN +#define ILABS_DEFAULT_ESP_SPI_MOSI_PIN 11 +#endif + +#ifndef ILABS_DEFAULT_ESP_SPI_SCK_PIN +#define ILABS_DEFAULT_ESP_SPI_SCK_PIN 10 +#endif + +#ifndef ILABS_DEFAULT_ESP_SPI_SS_PIN +#define ILABS_DEFAULT_ESP_SPI_SS_PIN 9 +#endif + +#ifndef ILABS_DEFAULT_ESP_SPI_HS_PIN +#define ILABS_DEFAULT_ESP_SPI_HS_PIN 22 +#endif + +#endif diff --git a/src/boards/include/boards/ilabs_opendec02.h b/src/boards/include/boards/ilabs_opendec02.h index 3fa7197bf..197a024ec 100644 --- a/src/boards/include/boards/ilabs_opendec02.h +++ b/src/boards/include/boards/ilabs_opendec02.h @@ -12,6 +12,8 @@ //------------------------------------------------------------------------------------------ // Board definition for the opendec02 open source dcc decoder // +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_ILABS_OPENDEC02_H #define _BOARDS_ILABS_OPENDEC02_H @@ -48,10 +50,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/melopero_perpetuo_rp2350_lora.h b/src/boards/include/boards/melopero_perpetuo_rp2350_lora.h new file mode 100644 index 000000000..cc358de34 --- /dev/null +++ b/src/boards/include/boards/melopero_perpetuo_rp2350_lora.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/melopero_perpetuo_rp2350_lora.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_MELOPERO_PERPETUO_RP2350_LORA_H +#define _BOARDS_MELOPERO_PERPETUO_RP2350_LORA_H + +// For board detection +#define MELOPERO_PERPETUO_RP2350_LORA + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 16 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 17 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 23 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 24 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 25 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + + + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// Board specific +#define MELOPERO_PERPETUO_ENABLE_WS2812 14 +#define MELOPERO_PERPETUO_WS2812 15 +#define MELOPERO_PERPETUO_LED 23 +#define MELOPERO_PERPETUO_ENABLE_VSEN 0 +#define MELOPERO_PERPETUO_FUEL_ALERT 3 +#define MELOPERO_PERPETUO_CHARGER_STAT1 1 +#define MELOPERO_PERPETUO_CHARGER_STAT2 2 + + +#endif diff --git a/src/boards/include/boards/melopero_shake_rp2040.h b/src/boards/include/boards/melopero_shake_rp2040.h index d07ca6123..49059c9ab 100644 --- a/src/boards/include/boards/melopero_shake_rp2040.h +++ b/src/boards/include/boards/melopero_shake_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_MELOPERO_SHAKE_RP2040_H #define _BOARDS_MELOPERO_SHAKE_RP2040_H @@ -80,10 +82,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 #endif diff --git a/src/boards/include/boards/metrotech_xerxes_rp2040.h b/src/boards/include/boards/metrotech_xerxes_rp2040.h index 16f111333..a78e3ea9a 100644 --- a/src/boards/include/boards/metrotech_xerxes_rp2040.h +++ b/src/boards/include/boards/metrotech_xerxes_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_METROTECH_XERXES_RP2040_H #define _BOARDS_METROTECH_XERXES_RP2040_H @@ -145,6 +147,7 @@ #define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 16 #endif // !PICO_XOSC_STARTUP_DELAY_MULTIPLIER +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES /** * @brief 16MiB, Flash size in bytes diff --git a/src/boards/include/boards/net8086_usb_interposer.h b/src/boards/include/boards/net8086_usb_interposer.h index efa57d964..4de560f44 100644 --- a/src/boards/include/boards/net8086_usb_interposer.h +++ b/src/boards/include/boards/net8086_usb_interposer.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_NET8086_USB_INTERPOSER_H #define _BOARDS_NET8086_USB_INTERPOSER_H @@ -60,6 +62,7 @@ #define PICO_FLASH_SPI_CLKDIV 4 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif diff --git a/src/boards/include/boards/nullbits_bit_c_pro.h b/src/boards/include/boards/nullbits_bit_c_pro.h index 169e0c19f..58bb1adc8 100644 --- a/src/boards/include/boards/nullbits_bit_c_pro.h +++ b/src/boards/include/boards/nullbits_bit_c_pro.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/nullbits_bit_c_pro.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_NULLBITS_BIT_C_PRO_H #define _BOARDS_NULLBITS_BIT_C_PRO_H @@ -98,10 +100,10 @@ #endif // Bit-C PRO has 4MB SPI flash +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) #endif - // All boards have B1+ RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/phyx_rick_tny_rp2350.h b/src/boards/include/boards/phyx_rick_tny_rp2350.h new file mode 100644 index 000000000..eb9e678f1 --- /dev/null +++ b/src/boards/include/boards/phyx_rick_tny_rp2350.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/phyx_rick_tny_rp2350.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_PHYX_RICK_TNY_RP2350_H +#define _BOARDS_PHYX_RICK_TNY_RP2350_H + +// For board detection +#define PHYX_RICK_TNY_RP2350 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 16 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 17 +#endif + +// no PICO_DEFAULT_LED_PIN + +// --- Neopixel --- +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 11 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 23 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +// no PICO_DEFAULT_SPI_CSN_PIN + + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/pi-plates_micropi.h b/src/boards/include/boards/pi-plates_micropi.h index 4e081e5b2..9c0dd62f2 100644 --- a/src/boards/include/boards/pi-plates_micropi.h +++ b/src/boards/include/boards/pi-plates_micropi.h @@ -11,6 +11,8 @@ // Board definition for the Pi-Plates MICROPi processor board +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PI_PLATES_MICROPI_H #define _BOARDS_PI_PLATES_MICROPI_H @@ -70,6 +72,7 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) //change to (16 * 1024 * 1024) on final product #endif diff --git a/src/boards/include/boards/pico.h b/src/boards/include/boards/pico.h index 139c0d397..800feb364 100644 --- a/src/boards/include/boards/pico.h +++ b/src/boards/include/boards/pico.h @@ -11,6 +11,8 @@ // This header may be included by other board headers as "boards/pico.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PICO_H #define _BOARDS_PICO_H @@ -70,10 +72,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) #define PICO_SMPS_MODE_PIN 23 diff --git a/src/boards/include/boards/pico2.h b/src/boards/include/boards/pico2.h new file mode 100644 index 000000000..4146f397c --- /dev/null +++ b/src/boards/include/boards/pico2.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/pico.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_PICO2_H +#define _BOARDS_PICO2_H + +// For board detection +#define RASPBERRYPI_PICO2 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// The GPIO Pin used to read VBUS to determine if the device is battery powered. +#ifndef PICO_VBUS_PIN +#define PICO_VBUS_PIN 24 +#endif + +// The GPIO Pin used to monitor VSYS. Typically you would use this with ADC. +// There is an example in adc/read_vsys in pico-examples. +#ifndef PICO_VSYS_PIN +#define PICO_VSYS_PIN 29 +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/pico_w.h b/src/boards/include/boards/pico_w.h index ba80a49b5..9e7464cef 100644 --- a/src/boards/include/boards/pico_w.h +++ b/src/boards/include/boards/pico_w.h @@ -9,6 +9,9 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM = rp2040 +// pico_cmake_set PICO_CYW43_SUPPORTED = 1 + // This header may be included by other board headers as "boards/pico_w.h" #ifndef _BOARDS_PICO_W_H @@ -68,10 +71,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // note the SMSP mode pin is on WL_GPIO1 // #define PICO_SMPS_MODE_PIN diff --git a/src/boards/include/boards/pimoroni_badger2040.h b/src/boards/include/boards/pimoroni_badger2040.h index 0749450dd..d05c4d4b5 100644 --- a/src/boards/include/boards/pimoroni_badger2040.h +++ b/src/boards/include/boards/pimoroni_badger2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_BADGER2040_H #define _BOARDS_PIMORONI_BADGER2040_H @@ -104,10 +106,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_interstate75.h b/src/boards/include/boards/pimoroni_interstate75.h index 5b5bf06f1..e7baa07b2 100644 --- a/src/boards/include/boards/pimoroni_interstate75.h +++ b/src/boards/include/boards/pimoroni_interstate75.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_INTERSTATE75_H #define _BOARDS_PIMORONI_INTERSTATE75_H @@ -94,10 +96,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_keybow2040.h b/src/boards/include/boards/pimoroni_keybow2040.h index baf0c408a..083140294 100644 --- a/src/boards/include/boards/pimoroni_keybow2040.h +++ b/src/boards/include/boards/pimoroni_keybow2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_KEYBOW2040_H #define _BOARDS_PIMORONI_KEYBOW2040_H @@ -83,10 +85,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_motor2040.h b/src/boards/include/boards/pimoroni_motor2040.h index 00fd91aec..e183090c3 100644 --- a/src/boards/include/boards/pimoroni_motor2040.h +++ b/src/boards/include/boards/pimoroni_motor2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_MOTOR2040_H #define _BOARDS_PIMORONI_MOTOR2040_H @@ -126,10 +128,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_pga2040.h b/src/boards/include/boards/pimoroni_pga2040.h index 980f16800..25b9dd2b5 100644 --- a/src/boards/include/boards/pimoroni_pga2040.h +++ b/src/boards/include/boards/pimoroni_pga2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_PGA2040_H #define _BOARDS_PIMORONI_PGA2040_H @@ -67,10 +69,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_pga2350.h b/src/boards/include/boards/pimoroni_pga2350.h new file mode 100644 index 000000000..9690f130c --- /dev/null +++ b/src/boards/include/boards/pimoroni_pga2350.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/pimoroni_pga2350.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_PIMORONI_PGA2350_H +#define _BOARDS_PIMORONI_PGA2350_H + +// For board detection +#define PIMORONI_PGA2350 +#define PIMORONI_PGA2350_16MB + +// --- BOARD SPECIFIC --- +#define PIMORONI_PGA2350_PSRAM_CS_PIN 47 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// no PICO_SMPS_MODE_PIN +// no PICO_VBUS_PIN +// no PICO_VSYS_PIN + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/pimoroni_pico_plus2_rp2350.h b/src/boards/include/boards/pimoroni_pico_plus2_rp2350.h new file mode 100644 index 000000000..13328f308 --- /dev/null +++ b/src/boards/include/boards/pimoroni_pico_plus2_rp2350.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/pimoroni_pico_plus2_rp2350.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_PIMORONI_PICO_PLUS2_RP2350_H +#define _BOARDS_PIMORONI_PICO_PLUS2_RP2350_H + +// For board detection +#define PIMORONI_PICO_PLUS2_RP2350 + +// --- BOARD SPECIFIC --- +#define SPICE_SPI 0 +#define SPICE_TX_MISO_PIN 32 +#define SPICE_RX_CS_PIN 33 +#define SPICE_NETLIGHT_SCK_PIN 34 +#define SPICE_RESET_MOSI_PIN 35 +#define SPICE_PWRKEY_BL_PIN 36 + +#define PIMORONI_PICO_PLUS2_USER_SW_PIN 45 +#define PIMORONI_PICO_PLUS2_PSRAM_CS_PIN 47 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN SPICE_NETLIGHT_SCK_PIN +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN SPICE_RESET_MOSI_PIN +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN SPICE_TX_MISO_PIN +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN SPICE_RX_CS_PIN +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// The GPIO Pin used to read VBUS to determine if the device is battery powered. +#ifndef PICO_VBUS_PIN +#define PICO_VBUS_PIN 24 +#endif + +// The GPIO Pin used to monitor VSYS. Typically you would use this with ADC. +// There is an example in adc/read_vsys in pico-examples. +#ifndef PICO_VSYS_PIN +#define PICO_VSYS_PIN 43 +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/pimoroni_picolipo_16mb.h b/src/boards/include/boards/pimoroni_picolipo_16mb.h index dfad76736..ad5bdf37c 100644 --- a/src/boards/include/boards/pimoroni_picolipo_16mb.h +++ b/src/boards/include/boards/pimoroni_picolipo_16mb.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_PICOLIPO_16MB_H #define _BOARDS_PIMORONI_PICOLIPO_16MB_H @@ -72,10 +74,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_picolipo_4mb.h b/src/boards/include/boards/pimoroni_picolipo_4mb.h index aea767d4d..981156fc3 100644 --- a/src/boards/include/boards/pimoroni_picolipo_4mb.h +++ b/src/boards/include/boards/pimoroni_picolipo_4mb.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_PICOLIPO_4MB_H #define _BOARDS_PIMORONI_PICOLIPO_4MB_H @@ -72,10 +74,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_picosystem.h b/src/boards/include/boards/pimoroni_picosystem.h index 0717b052e..bacbd5734 100644 --- a/src/boards/include/boards/pimoroni_picosystem.h +++ b/src/boards/include/boards/pimoroni_picosystem.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_PICOSYSTEM_H #define _BOARDS_PIMORONI_PICOSYSTEM_H @@ -89,10 +91,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_plasma2040.h b/src/boards/include/boards/pimoroni_plasma2040.h index 2cdb4c56a..c9937ef2f 100644 --- a/src/boards/include/boards/pimoroni_plasma2040.h +++ b/src/boards/include/boards/pimoroni_plasma2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_PLASMA2040_H #define _BOARDS_PIMORONI_PLASMA2040_H @@ -81,10 +83,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_plasma2350.h b/src/boards/include/boards/pimoroni_plasma2350.h new file mode 100644 index 000000000..9fb63eb8f --- /dev/null +++ b/src/boards/include/boards/pimoroni_plasma2350.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/pimoroni_plasma2350.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_PIMORONI_PLASMA2350_H +#define _BOARDS_PIMORONI_PLASMA2350_H + +// For board detection +#define PIMORONI_PLASMA2350 + +// --- BOARD SPECIFIC --- +#define SPICE_SPI 0 +#define SPICE_TX_MISO_PIN 8 +#define SPICE_RX_CS_PIN 9 +#define SPICE_NETLIGHT_SCK_PIN 10 +#define SPICE_RESET_MOSI_PIN 11 +#define SPICE_PWRKEY_BL_PIN 7 + +#define PLASMA2350_SW_A_PIN 12 + +#define PLASMA2350_CLK_PIN 14 +#define PLASMA2350_DATA_PIN 15 + +#define PLASMA2350_LED_R_PIN 16 +#define PLASMA2350_LED_G_PIN 17 +#define PLASMA2350_LED_B_PIN 18 + +#define PLASMA2350_I2C 0 +#define PLASMA2350_INT_PIN 19 +#define PLASMA2350_SDA_PIN 20 +#define PLASMA2350_SCL_PIN 21 + +#define PLASMA2350_USER_SW_PIN 22 + +#define PLASMA2350_A0_PIN 26 +#define PLASMA2350_A1_PIN 27 +#define PLASMA2350_A2_PIN 28 +#define PLASMA2350_NUM_ADC_PINS 3 + +#define PLASMA2350_CURRENT_SENSE_PIN 29 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +// no PICO_DEFAULT_UART +// no PICO_DEFAULT_UART_TX_PIN +// no PICO_DEFAULT_UART_RX_PIN + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN TINY2350_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +#ifndef PICO_DEFAULT_LED_PIN_INVERTED +#define PICO_DEFAULT_LED_PIN_INVERTED 1 +#endif + +// --- I2C --- +// routed to Qw/St connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C PLASMA2350_I2C +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN PLASMA2350_SDA_PIN +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN PLASMA2350_SCL_PIN +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN SPICE_NETLIGHT_SCK_PIN +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN SPICE_RESET_MOSI_PIN +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN SPICE_TX_MISO_PIN +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN SPICE_RX_CS_PIN +#endif + +// --- FLASH --- +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// no PICO_VBUS_PIN +// no PICO_VSYS_PIN + +#endif diff --git a/src/boards/include/boards/pimoroni_servo2040.h b/src/boards/include/boards/pimoroni_servo2040.h index 17fd76f4b..21f7049d7 100644 --- a/src/boards/include/boards/pimoroni_servo2040.h +++ b/src/boards/include/boards/pimoroni_servo2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_SERVO2040_H #define _BOARDS_PIMORONI_SERVO2040_H @@ -102,10 +104,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_tiny2040.h b/src/boards/include/boards/pimoroni_tiny2040.h index f4070080f..34e21f908 100644 --- a/src/boards/include/boards/pimoroni_tiny2040.h +++ b/src/boards/include/boards/pimoroni_tiny2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_TINY2040_H #define _BOARDS_PIMORONI_TINY2040_H @@ -90,10 +92,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_tiny2040_2mb.h b/src/boards/include/boards/pimoroni_tiny2040_2mb.h index 7aa07b2f8..8e411cfdb 100644 --- a/src/boards/include/boards/pimoroni_tiny2040_2mb.h +++ b/src/boards/include/boards/pimoroni_tiny2040_2mb.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_PIMORONI_TINY2040_2MB_H #define _BOARDS_PIMORONI_TINY2040_2MB_H @@ -90,10 +92,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/pimoroni_tiny2350.h b/src/boards/include/boards/pimoroni_tiny2350.h new file mode 100644 index 000000000..f6472a619 --- /dev/null +++ b/src/boards/include/boards/pimoroni_tiny2350.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/pimoroni_tiny2350.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_PIMORONI_TINY2350_H +#define _BOARDS_PIMORONI_TINY2350_H + +// For board detection +#define PIMORONI_TINY2350 +#define PIMORONI_TINY2350_8MB + +// --- BOARD SPECIFIC --- +#define TINY2350_LED_R_PIN 18 +#define TINY2350_LED_G_PIN 19 +#define TINY2350_LED_B_PIN 20 + +#define TINY2350_USER_SW_PIN 23 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN TINY2350_LED_G_PIN +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +// routed to Qw/St connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 12 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 13 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 6 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 7 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 5 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +// no PICO_VBUS_PIN +// no PICO_VSYS_PIN + +#endif diff --git a/src/boards/include/boards/pololu_3pi_2040_robot.h b/src/boards/include/boards/pololu_3pi_2040_robot.h index 94be451a6..53e0db449 100644 --- a/src/boards/include/boards/pololu_3pi_2040_robot.h +++ b/src/boards/include/boards/pololu_3pi_2040_robot.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_POLOLU_3PI_2040_ROBOT_H #define _BOARDS_POLOLU_3PI_2040_ROBOT_H @@ -18,6 +20,7 @@ #define PICO_DEFAULT_LED_PIN 25 #define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 #define PICO_FLASH_SPI_CLKDIV 2 +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) // All boards have at least the B1 revision diff --git a/src/boards/include/boards/pololu_zumo_2040_robot.h b/src/boards/include/boards/pololu_zumo_2040_robot.h index 7eb1cf0e0..756b45a82 100644 --- a/src/boards/include/boards/pololu_zumo_2040_robot.h +++ b/src/boards/include/boards/pololu_zumo_2040_robot.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_POLOLU_ZUMO_2040_ROBOT_H #define _BOARDS_POLOLU_ZUMO_2040_ROBOT_H @@ -18,6 +20,7 @@ #define PICO_DEFAULT_LED_PIN 25 #define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 #define PICO_FLASH_SPI_CLKDIV 2 +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) // All boards have at least the B1 revision diff --git a/src/boards/include/boards/seeed_xiao_rp2040.h b/src/boards/include/boards/seeed_xiao_rp2040.h index 2fd3687fd..efdb4cb18 100644 --- a/src/boards/include/boards/seeed_xiao_rp2040.h +++ b/src/boards/include/boards/seeed_xiao_rp2040.h @@ -9,6 +9,8 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_SEEED_XIAO_RP2040_H #define _BOARDS_SEEED_XIAO_RP2040_H @@ -88,10 +90,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/seeed_xiao_rp2350.h b/src/boards/include/boards/seeed_xiao_rp2350.h new file mode 100644 index 000000000..5c5859402 --- /dev/null +++ b/src/boards/include/boards/seeed_xiao_rp2350.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SEEED_XIAO_RP2350_H +#define _BOARDS_SEEED_XIAO_RP2350_H + +// For board detection +#define SEEED_XIAO_RP2350 + +//------------- UART -------------// +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif + +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif + +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +#ifndef PICO_UART1_TX_PIN +#define PICO_UART1_TX_PIN 20 +#endif + +#ifndef PICO_UART1_RX_PIN +#define PICO_UART1_RX_PIN 21 +#endif + +//------------- LED -------------// +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 22 +#endif + +#ifndef PICO_DEFAULT_WS2812_POWER_PIN +#define PICO_DEFAULT_WS2812_POWER_PIN 23 +#endif + +//------------- I2C -------------// +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif + +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif + +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +#ifndef PICO_I2C0_SDA_PIN +#define PICO_I2C0_SDA_PIN 16 +#endif + +#ifndef PICO_I2C0_SCL_PIN +#define PICO_I2C0_SCL_PIN 17 +#endif + +//------------- SPI -------------// +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif + +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 2 +#endif + +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 3 +#endif + +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif + +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 5 +#endif + +#ifndef PICO_SPI1_CSN_PIN +#define PICO_SPI1_CSN_PIN 9 +#endif + +#ifndef PICO_SPI1_SCK_PIN +#define PICO_SPI1_SCK_PIN 10 +#endif + +#ifndef PICO_SPI1_TX_PIN +#define PICO_SPI1_TX_PIN 11 +#endif + +#ifndef PICO_SPI1_RX_PIN +#define PICO_SPI1_RX_PIN 12 +#endif + +//------------- ADC -------------// +#ifndef PICO_ADC_A0_PIN +#define PICO_ADC_A0_PIN 26 +#endif + +#ifndef PICO_ADC_A1_PIN +#define PICO_ADC_A1_PIN 27 +#endif + +#ifndef PICO_ADC_A2_PIN +#define PICO_ADC_A2_PIN 28 +#endif + +#ifndef PICO_ADC_BAT_PIN +#define PICO_ADC_BAT_PIN 29 +#endif +#ifndef PICO_ADC_BAT_EN_PIN +#define PICO_ADC_BAT_EN_PIN 19 +#endif + +//------------- FLASH -------------// + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/solderparty_rp2040_stamp.h b/src/boards/include/boards/solderparty_rp2040_stamp.h index fb3c5b9ce..af107f65a 100644 --- a/src/boards/include/boards/solderparty_rp2040_stamp.h +++ b/src/boards/include/boards/solderparty_rp2040_stamp.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/solderparty_rp2040_stamp.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_SOLDERPARTY_RP2040_STAMP_H #define _BOARDS_SOLDERPARTY_RP2040_STAMP_H @@ -71,10 +73,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - // All production boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/solderparty_rp2040_stamp_carrier.h b/src/boards/include/boards/solderparty_rp2040_stamp_carrier.h index aac45f427..811f13c46 100644 --- a/src/boards/include/boards/solderparty_rp2040_stamp_carrier.h +++ b/src/boards/include/boards/solderparty_rp2040_stamp_carrier.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/solderparty_rp2040_stamp_carrier.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_SOLDERPARTY_RP2040_STAMP_CARRIER_H #define _BOARDS_SOLDERPARTY_RP2040_STAMP_CARRIER_H diff --git a/src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h b/src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h index bb9d3351c..3dc0f6013 100644 --- a/src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h +++ b/src/boards/include/boards/solderparty_rp2040_stamp_round_carrier.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/solderparty_rp2040_stamp_round_carrier.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_SOLDERPARTY_RP2040_STAMP_ROUND_CARRIER_H #define _BOARDS_SOLDERPARTY_RP2040_STAMP_ROUND_CARRIER_H diff --git a/src/boards/include/boards/solderparty_rp2350_stamp.h b/src/boards/include/boards/solderparty_rp2350_stamp.h new file mode 100644 index 000000000..fee982c8c --- /dev/null +++ b/src/boards/include/boards/solderparty_rp2350_stamp.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/solderparty_rp2350_stamp.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SOLDERPARTY_RP2350_STAMP_H +#define _BOARDS_SOLDERPARTY_RP2350_STAMP_H + +// For board detection +#define SOLDERPARTY_RP2350_STAMP + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// no PICO_DEFAULT_LED_PIN + +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/solderparty_rp2350_stamp_xl.h b/src/boards/include/boards/solderparty_rp2350_stamp_xl.h new file mode 100644 index 000000000..97fa0bf18 --- /dev/null +++ b/src/boards/include/boards/solderparty_rp2350_stamp_xl.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/solderparty_rp2350_stamp_xl.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SOLDERPARTY_RP2350_STAMP_XL_H +#define _BOARDS_SOLDERPARTY_RP2350_STAMP_XL_H + +// For board detection +#define SOLDERPARTY_RP2350_STAMP_XL + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// no PICO_DEFAULT_LED_PIN + +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/sparkfun_micromod.h b/src/boards/include/boards/sparkfun_micromod.h index 0c6e5687c..5806bd19e 100644 --- a/src/boards/include/boards/sparkfun_micromod.h +++ b/src/boards/include/boards/sparkfun_micromod.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/sparkfun_micromod.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_SPARKFUN_MICROMOD_H #define _BOARDS_SPARKFUN_MICROMOD_H @@ -73,10 +75,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED diff --git a/src/boards/include/boards/sparkfun_promicro.h b/src/boards/include/boards/sparkfun_promicro.h index 45bb4a244..da48c45f8 100644 --- a/src/boards/include/boards/sparkfun_promicro.h +++ b/src/boards/include/boards/sparkfun_promicro.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/sparkfun_promicro.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_SPARKFUN_PROMICRO_H #define _BOARDS_SPARKFUN_PROMICRO_H @@ -30,7 +32,7 @@ #define PICO_DEFAULT_UART_RX_PIN 1 #endif -// The PRO Micro doesnt have a plain LED, but a WS2812 +// The PRO Micro doesn't have a plain LED, but a WS2812 //#ifndef PICO_DEFAULT_LED_PIN //#define PICO_DEFAULT_LED_PIN 25 //#endif @@ -73,10 +75,10 @@ #endif // board has 16M onboard flash +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED diff --git a/src/boards/include/boards/sparkfun_promicro_rp2350.h b/src/boards/include/boards/sparkfun_promicro_rp2350.h new file mode 100644 index 000000000..fd12de506 --- /dev/null +++ b/src/boards/include/boards/sparkfun_promicro_rp2350.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- +// +//------------------------------------------------------------------------------------------ +// Board definition for the SparkFun ProMicro RP2350 +// +// This header may be included by other board headers as "boards/sparkfun_promicro_rp2350.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SPARKFUN_PROMICRO_RP2350_H +#define _BOARDS_SPARKFUN_PROMICRO_RP2350_H + +// For board detection +#define SPARKFUN_PROMICRO_RP2350 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// The PRO Micro doesn't have a plain LED, but a WS2812 +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 25 +#endif + +// Default I2C - for the onboard qwiic connector +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 16 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 17 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 23 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// board has 16M onboard flash +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/sparkfun_thingplus.h b/src/boards/include/boards/sparkfun_thingplus.h index 3d7d69abe..1ed52b86c 100644 --- a/src/boards/include/boards/sparkfun_thingplus.h +++ b/src/boards/include/boards/sparkfun_thingplus.h @@ -14,6 +14,8 @@ // // This header may be included by other board headers as "boards/sparkfun_thingplus.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_SPARKFUN_THINGPLUS_H #define _BOARDS_SPARKFUN_THINGPLUS_H @@ -72,10 +74,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // The thing plus has a SD Card. #define PICO_SD_CLK_PIN 14 #define PICO_SD_CMD_PIN 15 diff --git a/src/boards/include/boards/switchscience_picossci2_conta_base.h b/src/boards/include/boards/switchscience_picossci2_conta_base.h new file mode 100644 index 000000000..fcd7d85b2 --- /dev/null +++ b/src/boards/include/boards/switchscience_picossci2_conta_base.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/switchscience_picossci2_conta_base.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SWITCHSCIENCE_PICOSSCI2_CONTA_BASE_H +#define _BOARDS_SWITCHSCIENCE_PICOSSCI2_CONTA_BASE_H + +// For board detection +#define SWITCHSCIENCE_PICOSSCI2_CONTA_BASE_H + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 6 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 7 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 2 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 3 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 4 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 5 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/switchscience_picossci2_dev_board.h b/src/boards/include/boards/switchscience_picossci2_dev_board.h new file mode 100644 index 000000000..432d2d9b1 --- /dev/null +++ b/src/boards/include/boards/switchscience_picossci2_dev_board.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/switchscience_picossci2_dev_board.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SWITCHSCIENCE_PICOSSCI2_DEV_BOARD_H +#define _BOARDS_SWITCHSCIENCE_PICOSSCI2_DEV_BOARD_H + +// For board detection +#define SWITCHSCIENCE_PICOSSCI2_DEV_BOARD + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// board has 4MB onboard flash +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/switchscience_picossci2_micro.h b/src/boards/include/boards/switchscience_picossci2_micro.h new file mode 100644 index 000000000..5d664997e --- /dev/null +++ b/src/boards/include/boards/switchscience_picossci2_micro.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/switchscience_picossci2_micro.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SWITCHSCIENCE_PICOSSCI2_MICRO_H +#define _BOARDS_SWITCHSCIENCE_PICOSSCI2_MICRO_H + +// For board detection +#define SWITCHSCIENCE_PICOSSCI2_MICRO + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- Picossci2 Micro doesn't have an LED connected to GPIO --- + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 22 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 23 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// board has 4MB onboard flash +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/switchscience_picossci2_rp2350_breakout.h b/src/boards/include/boards/switchscience_picossci2_rp2350_breakout.h new file mode 100644 index 000000000..0ac128b13 --- /dev/null +++ b/src/boards/include/boards/switchscience_picossci2_rp2350_breakout.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/switchscience_picossci2_rp2350_breakout.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SWITCHSCIENCE_PICOSSCI2_RP2350_BREAKOUT_H +#define _BOARDS_SWITCHSCIENCE_PICOSSCI2_RP2350_BREAKOUT_H + +// For board detection +#define SWITCHSCIENCE_PICOSSCI2_RP2350_BREAKOUT_H + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/switchscience_picossci2_tiny.h b/src/boards/include/boards/switchscience_picossci2_tiny.h new file mode 100644 index 000000000..48e3a9e83 --- /dev/null +++ b/src/boards/include/boards/switchscience_picossci2_tiny.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/switchscience_picossci2_tiny.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_SWITCHSCIENCE_PICOSSCI2_TINY_H +#define _BOARDS_SWITCHSCIENCE_PICOSSCI2_TINY_H + +// For board detection +#define SWITCHSCIENCE_PICOSSCI2_TINY_H + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 28 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 29 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 1 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 2 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 3 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 20 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 21 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/tinycircuits_thumby_color_rp2350.h b/src/boards/include/boards/tinycircuits_thumby_color_rp2350.h new file mode 100644 index 000000000..0a3c14a68 --- /dev/null +++ b/src/boards/include/boards/tinycircuits_thumby_color_rp2350.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// This header may be included by other board headers as "boards/tinycircuits_thumby_color_rp2350.h" + +// pico_cmake_set PICO_PLATFORM=rp2350 + +#ifndef _BOARDS_TINYCIRCUITS_THUMBY_COLOR_RP2350_H +#define _BOARDS_TINYCIRCUITS_THUMBY_COLOR_RP2350_H + +// For board detection +#define TINYCIRCUITS_THUMBY_COLOR_RP2350 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 1 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 25 +#endif +// no PICO_DEFAULT_WS2812_PIN + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 4 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 5 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 0 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 18 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 19 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 16 +#endif +#ifndef PICO_DEFAULT_SPI_CSN_PIN +#define PICO_DEFAULT_SPI_CSN_PIN 17 +#endif + +// --- FLASH --- + +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) +#endif +// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) +#define PICO_SMPS_MODE_PIN 23 + +// The GPIO Pin used to read VBUS to determine if the device is battery powered. +#ifndef PICO_VBUS_PIN +#define PICO_VBUS_PIN 24 +#endif + +// The GPIO Pin used to monitor VSYS. Typically you would use this with ADC. +// There is an example in adc/read_vsys in pico-examples. +#ifndef PICO_VSYS_PIN +#define PICO_VSYS_PIN 29 +#endif + +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h b/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h index ff0e84b20..079187059 100644 --- a/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h +++ b/src/boards/include/boards/waveshare_rp2040_lcd_0.96.h @@ -9,6 +9,7 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 #ifndef _BOARDS_WAVESHARE_RP2040_LCD_0_96_H #define _BOARDS_WAVESHARE_RP2040_LCD_0_96_H @@ -88,10 +89,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) #define PICO_SMPS_MODE_PIN 23 diff --git a/src/boards/include/boards/waveshare_rp2040_lcd_1.28.h b/src/boards/include/boards/waveshare_rp2040_lcd_1.28.h index eea45254f..816aec2e1 100644 --- a/src/boards/include/boards/waveshare_rp2040_lcd_1.28.h +++ b/src/boards/include/boards/waveshare_rp2040_lcd_1.28.h @@ -9,6 +9,7 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 #ifndef _BOARDS_WAVESHARE_RP2040_LCD_1_28_H #define _BOARDS_WAVESHARE_RP2040_LCD_1_28_H @@ -91,10 +92,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/waveshare_rp2040_one.h b/src/boards/include/boards/waveshare_rp2040_one.h index 3f6c6c494..389d2992d 100644 --- a/src/boards/include/boards/waveshare_rp2040_one.h +++ b/src/boards/include/boards/waveshare_rp2040_one.h @@ -9,6 +9,7 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 #ifndef _BOARDS_WAVESHARE_RP2040_ONE_H #define _BOARDS_WAVESHARE_RP2040_ONE_H @@ -67,10 +68,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/waveshare_rp2040_plus_16mb.h b/src/boards/include/boards/waveshare_rp2040_plus_16mb.h index 6f5e1441c..2d32acc9c 100644 --- a/src/boards/include/boards/waveshare_rp2040_plus_16mb.h +++ b/src/boards/include/boards/waveshare_rp2040_plus_16mb.h @@ -9,6 +9,7 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 #ifndef _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H #define _BOARDS_WAVESHARE_RP2040_PLUS_16MB_H @@ -69,10 +70,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) #define PICO_SMPS_MODE_PIN 23 diff --git a/src/boards/include/boards/waveshare_rp2040_plus_4mb.h b/src/boards/include/boards/waveshare_rp2040_plus_4mb.h index d8dd8f6b3..f5be65768 100644 --- a/src/boards/include/boards/waveshare_rp2040_plus_4mb.h +++ b/src/boards/include/boards/waveshare_rp2040_plus_4mb.h @@ -9,6 +9,7 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 #ifndef _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H #define _BOARDS_WAVESHARE_RP2040_PLUS_4MB_H @@ -69,10 +70,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) #endif - // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) #define PICO_SMPS_MODE_PIN 23 diff --git a/src/boards/include/boards/waveshare_rp2040_zero.h b/src/boards/include/boards/waveshare_rp2040_zero.h index 8dadd5536..85be7c7f9 100644 --- a/src/boards/include/boards/waveshare_rp2040_zero.h +++ b/src/boards/include/boards/waveshare_rp2040_zero.h @@ -9,6 +9,7 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- +// pico_cmake_set PICO_PLATFORM=rp2040 #ifndef _BOARDS_WAVESHARE_RP2040_ZERO_H #define _BOARDS_WAVESHARE_RP2040_ZERO_H @@ -67,10 +68,10 @@ #define PICO_FLASH_SPI_CLKDIV 4 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // All boards have B1 RP2040 #ifndef PICO_RP2040_B0_SUPPORTED #define PICO_RP2040_B0_SUPPORTED 0 diff --git a/src/boards/include/boards/weact_studio_rp2040_16mb.h b/src/boards/include/boards/weact_studio_rp2040_16mb.h index bd45b1f3e..c8d3aa2ef 100644 --- a/src/boards/include/boards/weact_studio_rp2040_16mb.h +++ b/src/boards/include/boards/weact_studio_rp2040_16mb.h @@ -11,6 +11,8 @@ // This header may be included by other board headers as "boards/weact_studio_rp2040_16mb.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_WEACT_STUDIO_RP2040_16MB_H #define _BOARDS_WEACT_STUDIO_RP2040_16MB_H @@ -73,8 +75,8 @@ #define PICO_RP2040_B0_SUPPORTED 0 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024) #endif - #endif diff --git a/src/boards/include/boards/weact_studio_rp2040_2mb.h b/src/boards/include/boards/weact_studio_rp2040_2mb.h index d058ce34b..4b0c00590 100644 --- a/src/boards/include/boards/weact_studio_rp2040_2mb.h +++ b/src/boards/include/boards/weact_studio_rp2040_2mb.h @@ -11,6 +11,8 @@ // This header may be included by other board headers as "boards/weact_studio_rp2040_2mb.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_WEACT_STUDIO_RP2040_2MB_H #define _BOARDS_WEACT_STUDIO_RP2040_2MB_H @@ -73,8 +75,8 @@ #define PICO_RP2040_B0_SUPPORTED 0 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - #endif diff --git a/src/boards/include/boards/weact_studio_rp2040_4mb.h b/src/boards/include/boards/weact_studio_rp2040_4mb.h index 6b49a4f33..405620d47 100644 --- a/src/boards/include/boards/weact_studio_rp2040_4mb.h +++ b/src/boards/include/boards/weact_studio_rp2040_4mb.h @@ -11,6 +11,8 @@ // This header may be included by other board headers as "boards/weact_studio_rp2040_4mb.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_WEACT_STUDIO_RP2040_4MB_H #define _BOARDS_WEACT_STUDIO_RP2040_4MB_H @@ -73,8 +75,8 @@ #define PICO_RP2040_B0_SUPPORTED 0 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (4 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (4 * 1024 * 1024) #endif - #endif diff --git a/src/boards/include/boards/weact_studio_rp2040_8mb.h b/src/boards/include/boards/weact_studio_rp2040_8mb.h index bdddd227e..72778c178 100644 --- a/src/boards/include/boards/weact_studio_rp2040_8mb.h +++ b/src/boards/include/boards/weact_studio_rp2040_8mb.h @@ -11,6 +11,8 @@ // This header may be included by other board headers as "boards/weact_studio_rp2040_8mb.h" +// pico_cmake_set PICO_PLATFORM=rp2040 + #ifndef _BOARDS_WEACT_STUDIO_RP2040_8MB_H #define _BOARDS_WEACT_STUDIO_RP2040_8MB_H @@ -73,8 +75,8 @@ #define PICO_RP2040_B0_SUPPORTED 0 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) #endif - #endif diff --git a/src/boards/include/boards/wiznet_w5100s_evb_pico.h b/src/boards/include/boards/wiznet_w5100s_evb_pico.h index 585f1d118..0640eadfb 100644 --- a/src/boards/include/boards/wiznet_w5100s_evb_pico.h +++ b/src/boards/include/boards/wiznet_w5100s_evb_pico.h @@ -9,7 +9,7 @@ // SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES // ----------------------------------------------------- - +// pico_cmake_set PICO_PLATFORM=rp2040 #ifndef _BOARDS_WIZNET_W5100S_EVB_PICO_H #define _BOARDS_WIZNET_W5100S_EVB_PICO_H @@ -89,10 +89,10 @@ #define PICO_FLASH_SPI_CLKDIV 2 #endif +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (2 * 1024 * 1024) #ifndef PICO_FLASH_SIZE_BYTES #define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) #endif - // Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads) #define PICO_SMPS_MODE_PIN 23 diff --git a/src/boards/pico_w.cmake b/src/boards/pico_w.cmake deleted file mode 100644 index 7aeaaeefc..000000000 --- a/src/boards/pico_w.cmake +++ /dev/null @@ -1,3 +0,0 @@ -set(PICO_CYW43_SUPPORTED "1") -pico_register_common_scope_var(PICO_CYW43_SUPPORTED) -include(${CMAKE_CURRENT_LIST_DIR}/generic_board.cmake) diff --git a/src/cmake/no_hardware.cmake b/src/cmake/no_hardware.cmake new file mode 100644 index 000000000..95a034be0 --- /dev/null +++ b/src/cmake/no_hardware.cmake @@ -0,0 +1,26 @@ +macro(pico_set_float_implementation TARGET IMPL) + # ignore +endmacro() + +macro(pico_set_double_implementation TARGET IMPL) + # ignore +endmacro() + +macro(pico_set_binary_type TARGET IMPL) + # ignore +endmacro() + +macro(pico_set_boot_stage2 TARGET IMPL) + # ignore +endmacro() + +set(PICO_HOST_DIR "${CMAKE_CURRENT_LIST_DIR}/host" CACHE INTERNAL "") +function(pico_define_boot_stage2 NAME) + add_executable(${NAME} ${PICO_HOST_DIR}/boot_stage2.c) +endfunction() + +function(pico_add_extra_outputs TARGET) +endfunction() + +set(PICO_NO_HARDWARE "1" CACHE INTERNAL "") +set(PICO_ON_DEVICE "0" CACHE INTERNAL "") \ No newline at end of file diff --git a/src/cmake/on_device.cmake b/src/cmake/on_device.cmake new file mode 100644 index 000000000..3b2d8869a --- /dev/null +++ b/src/cmake/on_device.cmake @@ -0,0 +1,97 @@ +# include targets for all for PICO on device + +enable_language(ASM) + +function(pico_get_runtime_output_directory TARGET output_path_name) + get_target_property(${TARGET}_runtime_directory ${TARGET} RUNTIME_OUTPUT_DIRECTORY) + if (${TARGET}_runtime_directory) + get_filename_component(output_path "${${TARGET}_runtime_directory}" + REALPATH BASE_DIR "${CMAKE_CURRENT_BINARY_DIR}") + file(MAKE_DIRECTORY "${output_path}") + set(output_path "${output_path}/") + else() + set(output_path "") + endif() + set(${output_path_name} ${output_path} PARENT_SCOPE) +endfunction() + +function(pico_add_hex_output TARGET) + pico_get_runtime_output_directory(${TARGET} output_path) + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex $ ${output_path}$>,$,$>.hex VERBATIM) +endfunction() + +function(pico_add_bin_output TARGET) + pico_get_runtime_output_directory(${TARGET} output_path) + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${output_path}$>,$,$>.bin VERBATIM) +endfunction() + +function(pico_add_dis_output TARGET) + pico_get_runtime_output_directory(${TARGET} output_path) + + # PICO_CMAKE_CONFIG: PICO_NO_COPRO_DIS, Disable disassembly listing postprocessing that disassembles RP2350 coprocessor instructions, type=bool, default=0, group=build + if (NOT (PICO_NO_COPRO_DIS OR PICO_NO_PICOTOOL)) + pico_init_picotool() + if(picotool_FOUND) + # add custom disassembly if we have picotool + set(EXTRA_COMMAND COMMAND picotool coprodis --quiet ${output_path}$>,$,$>.dis ${output_path}$>,$,$>.dis) + endif() + endif() + + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${CMAKE_OBJDUMP} -h $ > ${output_path}$>,$,$>.dis + COMMAND ${CMAKE_OBJDUMP} -d $ >> ${output_path}$>,$,$>.dis + ${EXTRA_COMMAND} || ${CMAKE_COMMAND} -E echo "WARNING: Disassembly is not correct" + VERBATIM + ) +endfunction() + +function(pico_add_extra_outputs TARGET) + # Disassembly will be nonsense for encrypted binaries, + # so disassemble before picotool processing + pico_add_dis_output(${TARGET}) + + # Picotool processing (signing/encrypting/etc) + # PICO_CMAKE_CONFIG: PICO_NO_PICOTOOL, Disable use/requirement for picotool meaning that UF2 output and signing/hashing and coprocoessor disassembly will all be unavailable, type=bool, default=0, group=build + if (NOT PICO_NO_PICOTOOL) + picotool_postprocess_binary(${TARGET} IS_ENCRYPTED) + endif() + + if (PICO_32BIT) + pico_add_hex_output(${TARGET}) + endif() + pico_add_bin_output(${TARGET}) + pico_add_map_output(${TARGET}) + + # PICO_CMAKE_CONFIG: PICO_NO_TARGET_NAME, Don't define PICO_TARGET_NAME, type=bool, default=0, group=build + # PICO_BUILD_DEFINE: PICO_TARGET_NAME, The name of the build target being compiled (unless PICO_NO_TARGET_NAME set in build), type=string, default=target name, group=build + if (NOT PICO_NO_TARGET_NAME) + target_compile_definitions(${TARGET} PRIVATE + PICO_TARGET_NAME="${TARGET}" + ) + endif() + + if (PICO_SYMLINK_ELF_AS_FILENAME) + add_custom_target(${TARGET}_symlinked) + add_dependencies(${TARGET}_symlinked ${TARGET}) + + add_custom_command(TARGET ${TARGET}_symlinked POST_BUILD + COMMAND rm -f "${PICO_SYMLINK_ELF_AS_FILENAME}" + COMMAND ln -s -r $ "${PICO_SYMLINK_ELF_AS_FILENAME}" + COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}" + ) + endif () + # PICO_CMAKE_CONFIG: PICO_NO_UF2, Disable UF2 output, type=bool, default=0, group=build + if (NOT (PICO_NO_UF2 OR PICO_NO_PICOTOOL)) + pico_add_uf2_output(${TARGET}) + endif() +endfunction() + +# PICO_CMAKE_CONFIG: PICO_NO_HARDWARE, Option as to whether the build is not targeting an RP2040 or RP2350 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build +# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 or RP2350 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build +set(PICO_NO_HARDWARE "0" CACHE INTERNAL "") +# PICO_CMAKE_CONFIG: PICO_ON_DEVICE, Option as to whether the build is targeting an RP2040 or RP2350 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build +# PICO_BUILD_DEFINE: PICO_ON_DEVICE, Whether the build is targeting an RP2040 or RP2350 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build +set(PICO_ON_DEVICE "1" CACHE INTERNAL "") + +set(CMAKE_EXECUTABLE_SUFFIX .elf) +set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE) \ No newline at end of file diff --git a/src/cmake/rp2_common.cmake b/src/cmake/rp2_common.cmake new file mode 100644 index 000000000..494b1202b --- /dev/null +++ b/src/cmake/rp2_common.cmake @@ -0,0 +1,162 @@ +# Used for RP2040 and RP2350 + +include(cmake/on_device.cmake) + +# PICO_CMAKE_CONFIG: PICO_NO_FLASH, Option to default all binaries to not use flash i.e. run from SRAM, type=bool, default=0, group=build, docref=cmake-binary-type-config +option(PICO_NO_FLASH "Default binaries to not not use flash") +# PICO_CMAKE_CONFIG: PICO_COPY_TO_RAM, Option to default all binaries to copy code from flash to SRAM before running, type=bool, default=0, group=build, docref=cmake-binary-type-config +option(PICO_COPY_TO_RAM "Default binaries to copy code to RAM when booting from flash") + +# COMMON +pico_add_subdirectory(common/boot_picobin_headers) +pico_add_subdirectory(common/boot_picoboot_headers) +pico_add_subdirectory(common/boot_uf2_headers) +pico_add_subdirectory(common/pico_base_headers) +pico_add_subdirectory(common/pico_usb_reset_interface_headers) + +# PICO_CMAKE_CONFIG: PICO_BARE_METAL, Flag to exclude anything except base headers from the build, type=bool, default=0, group=build +if (NOT PICO_BARE_METAL) + pico_add_subdirectory(common/pico_bit_ops_headers) + pico_add_subdirectory(common/pico_binary_info) + pico_add_subdirectory(common/pico_divider_headers) + pico_add_subdirectory(common/pico_sync) + pico_add_subdirectory(common/pico_time) + pico_add_subdirectory(common/pico_util) + pico_add_subdirectory(common/pico_stdlib_headers) +endif() +pico_add_subdirectory(common/hardware_claim) +# +# RP2040/RP2350 specific From standard build variants +pico_add_subdirectory(${RP2_VARIANT_DIR}/pico_platform) +pico_add_subdirectory(${RP2_VARIANT_DIR}/hardware_regs) +pico_add_subdirectory(${RP2_VARIANT_DIR}/hardware_structs) +pico_add_subdirectory(${RP2_VARIANT_DIR}/boot_stage2) + +pico_add_subdirectory(rp2_common/hardware_base) +# HAL items which expose a public (inline rp2_common) functions/macro API above the raw hardware +pico_add_subdirectory(rp2_common/hardware_adc) +pico_add_subdirectory(rp2_common/hardware_boot_lock) +pico_add_subdirectory(rp2_common/hardware_clocks) +pico_add_subdirectory(rp2_common/hardware_divider) +pico_add_subdirectory(rp2_common/hardware_dma) +pico_add_subdirectory(rp2_common/hardware_exception) +pico_add_subdirectory(rp2_common/hardware_flash) +pico_add_subdirectory(rp2_common/hardware_gpio) +pico_add_subdirectory(rp2_common/hardware_i2c) +pico_add_subdirectory(rp2_common/hardware_interp) +pico_add_subdirectory(rp2_common/hardware_irq) +pico_add_subdirectory(rp2_common/hardware_pio) +pico_add_subdirectory(rp2_common/hardware_pll) +pico_add_subdirectory(rp2_common/hardware_pwm) +pico_add_subdirectory(rp2_common/hardware_resets) +if (PICO_RP2040 OR PICO_COMBINED_DOCS) + pico_add_subdirectory(rp2_common/hardware_rtc) +endif() +pico_add_subdirectory(rp2_common/hardware_spi) +pico_add_subdirectory(rp2_common/hardware_sync) +pico_add_subdirectory(rp2_common/hardware_sync_spin_lock) +pico_add_subdirectory(rp2_common/hardware_ticks) +pico_add_subdirectory(rp2_common/hardware_timer) +pico_add_subdirectory(rp2_common/hardware_uart) +pico_add_subdirectory(rp2_common/hardware_vreg) +pico_add_subdirectory(rp2_common/hardware_watchdog) +pico_add_subdirectory(rp2_common/hardware_xosc) + +if (PICO_RP2350 OR PICO_COMBINED_DOCS) + pico_add_subdirectory(rp2_common/hardware_powman) + # Note in spite of the name this is usable on Arm as well as RISC-V: + pico_add_subdirectory(rp2_common/hardware_riscv_platform_timer) + pico_add_subdirectory(rp2_common/hardware_sha256) +endif() + +if (PICO_RP2350 OR PICO_COMBINED_DOCS) + pico_add_subdirectory(rp2_common/hardware_dcp) + pico_add_subdirectory(rp2_common/hardware_rcp) +endif() + +if (PICO_RISCV OR PICO_COMBINED_DOCS) + pico_add_subdirectory(rp2_common/hardware_riscv) + pico_add_subdirectory(rp2_common/hardware_hazard3) +endif() + +# Helper functions to connect to data/functions in the bootrom +pico_add_subdirectory(rp2_common/pico_bootrom) + +pico_add_subdirectory(rp2_common/pico_platform_compiler) +pico_add_subdirectory(rp2_common/pico_platform_sections) +pico_add_subdirectory(rp2_common/pico_platform_panic) + +if (NOT PICO_BARE_METAL) + # NOTE THE ORDERING HERE IS IMPORTANT AS SOME TARGETS CHECK ON EXISTENCE OF OTHER TARGETS + pico_add_subdirectory(rp2_common/pico_aon_timer) + pico_add_subdirectory(rp2_common/pico_bootsel_via_double_reset) + pico_add_subdirectory(rp2_common/pico_multicore) + pico_add_subdirectory(rp2_common/pico_unique_id) + + pico_add_subdirectory(rp2_common/pico_atomic) + pico_add_subdirectory(rp2_common/pico_bit_ops) + pico_add_subdirectory(rp2_common/pico_divider) + pico_add_subdirectory(rp2_common/pico_double) + pico_add_subdirectory(rp2_common/pico_int64_ops) + pico_add_subdirectory(rp2_common/pico_flash) + pico_add_subdirectory(rp2_common/pico_float) + pico_add_subdirectory(rp2_common/pico_mem_ops) + pico_add_subdirectory(rp2_common/pico_malloc) + pico_add_subdirectory(rp2_common/pico_printf) + pico_add_subdirectory(rp2_common/pico_rand) + + if (PICO_RP2350 OR PICO_COMBINED_DOCS) + pico_add_subdirectory(rp2_common/pico_sha256) + endif() + + pico_add_subdirectory(rp2_common/pico_stdio_semihosting) + pico_add_subdirectory(rp2_common/pico_stdio_uart) + pico_add_subdirectory(rp2_common/pico_stdio_rtt) + + if (NOT PICO_RISCV) + pico_add_subdirectory(rp2_common/cmsis) + endif() + pico_add_subdirectory(rp2_common/tinyusb) + pico_add_subdirectory(rp2_common/pico_stdio_usb) + pico_add_subdirectory(rp2_common/pico_i2c_slave) + + # networking libraries - note dependency order is important + pico_add_subdirectory(rp2_common/pico_async_context) + pico_add_subdirectory(rp2_common/pico_btstack) + pico_add_subdirectory(rp2_common/pico_cyw43_driver) + pico_add_subdirectory(rp2_common/pico_lwip) + pico_add_subdirectory(rp2_common/pico_cyw43_arch) + pico_add_subdirectory(rp2_common/pico_mbedtls) + + pico_add_subdirectory(rp2_common/pico_time_adapter) + + pico_add_subdirectory(rp2_common/pico_crt0) + pico_add_subdirectory(rp2_common/pico_clib_interface) + pico_add_subdirectory(rp2_common/pico_cxx_options) + pico_add_subdirectory(rp2_common/pico_standard_binary_info) + pico_add_subdirectory(rp2_common/pico_standard_link) + + pico_add_subdirectory(rp2_common/pico_fix) + + # at the end as it includes a lot of other stuff + pico_add_subdirectory(rp2_common/pico_runtime_init) + pico_add_subdirectory(rp2_common/pico_runtime) + + # this requires all the pico_stdio_ libraries + pico_add_subdirectory(rp2_common/pico_stdio) + # this requires runtime + pico_add_subdirectory(rp2_common/pico_stdlib) +endif() + +# configure doxygen directories +#pico_add_doxygen(${COMMON_DIR}) +#pico_add_doxygen(${RP2_VARIANT_DIR}) +pico_add_doxygen_exclude(${RP2_VARIANT_DIR}/hardware_regs) # very very big +# but we DO want dreq.h; it doesn't change much, so lets just use configure_file +configure_file(${RP2_VARIANT_DIR}/hardware_regs/include/hardware/regs/dreq.h ${CMAKE_CURRENT_BINARY_DIR}/extra_doxygen/dreq.h COPYONLY) +# also intctrl.h +configure_file(${RP2_VARIANT_DIR}/hardware_regs/include/hardware/regs/intctrl.h ${CMAKE_CURRENT_BINARY_DIR}/extra_doxygen/intctrl.h COPYONLY) +pico_add_doxygen(${CMAKE_CURRENT_BINARY_DIR}/extra_doxygen) + +#pico_add_doxygen(rp2_common) +pico_add_doxygen_exclude(rp2_common/cmsis) # very big diff --git a/src/combined-docs.cmake b/src/combined-docs.cmake new file mode 100644 index 000000000..3af6c906d --- /dev/null +++ b/src/combined-docs.cmake @@ -0,0 +1,32 @@ +# This is not a platform proper; but is used to build a merged set of documentation + +set(PICO_RP2040 "1" CACHE INTERNAL "") +set(PICO_RP2350 "1" CACHE INTERNAL "") +set(PICO_RISCV "1" CACHE INTERNAL "") +set(PICO_ARM "1" CACHE INTERNAL "") +set(PICO_COMBINED_DOCS "1" CACHE INTERNAL "") +# have to pick one for platform stuff, so lets go with rp2350 +set(RP2_VARIANT_DIR ${CMAKE_CURRENT_LIST_DIR}/rp2350) +# pick latest version +set(PICO_PIO_VERSION "1" CACHE INTERNAL "") +set(PICO_CMSIS_DEVICE "RP2350" CACHE INTERNAL "") + +# Add RP2040 structs too, since there are distinct enums in there +pico_add_doxygen(rp2040/hardware_structs) +# but we DO want dreq.h; it doesn't change much, so lets just use configure_file +# (note we don't add rp2040/hardware_regs because of the size) +configure_file(rp2040/hardware_regs/include/hardware/regs/dreq.h ${CMAKE_CURRENT_BINARY_DIR}/extra_doxygen/dreq_rp2040.h COPYONLY) +# also intctrl.h +configure_file(rp2040/hardware_regs/include/hardware/regs/intctrl.h ${CMAKE_CURRENT_BINARY_DIR}/extra_doxygen/intctrl_rp2040.h COPYONLY) +pico_add_doxygen(${CMAKE_CURRENT_BINARY_DIR}/extra_doxygen) + +pico_add_doxygen_pre_define("PICO_RP2040=1") +pico_add_doxygen_pre_define("PICO_RP2350=1") +pico_add_doxygen_pre_define("PICO_COMBINED_DOCS=1") +pico_add_doxygen_pre_define("NUM_DOORBELLS=1") # we have functions that are gated by this +pico_add_doxygen_enabled_section(combined_docs) +pico_add_doxygen_enabled_section(rp2040_specific) +pico_add_doxygen_enabled_section(rp2350_specific) + +include(cmake/rp2_common.cmake) + diff --git a/src/common/CMakeLists.txt b/src/common/CMakeLists.txt deleted file mode 100644 index 38cf23818..000000000 --- a/src/common/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -pico_add_subdirectory(boot_picoboot) -pico_add_subdirectory(boot_uf2) -pico_add_subdirectory(pico_base) -pico_add_subdirectory(pico_usb_reset_interface) - -# PICO_CMAKE_CONFIG: PICO_BARE_METAL, Flag to exclude anything except base headers from the build, type=bool, default=0, group=build -if (NOT PICO_BARE_METAL) - pico_add_subdirectory(pico_bit_ops) - pico_add_subdirectory(pico_binary_info) - pico_add_subdirectory(pico_divider) - pico_add_subdirectory(pico_sync) - pico_add_subdirectory(pico_time) - pico_add_subdirectory(pico_util) - pico_add_subdirectory(pico_stdlib) -endif() - -pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) - -pico_promote_common_scope_vars() \ No newline at end of file diff --git a/src/common/boot_picobin_headers/BUILD.bazel b/src/common/boot_picobin_headers/BUILD.bazel new file mode 100644 index 000000000..2adc55690 --- /dev/null +++ b/src/common/boot_picobin_headers/BUILD.bazel @@ -0,0 +1,10 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "boot_picobin_headers", + hdrs = ["include/boot/picobin.h"], + includes = ["include"], + deps = [ + "//src:pico_platform_internal", + ], +) diff --git a/src/common/boot_picobin_headers/CMakeLists.txt b/src/common/boot_picobin_headers/CMakeLists.txt new file mode 100644 index 000000000..fb600b14f --- /dev/null +++ b/src/common/boot_picobin_headers/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(boot_picobin_headers INTERFACE) +target_include_directories(boot_picobin_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/src/common/boot_picobin_headers/include/boot/picobin.h b/src/common/boot_picobin_headers/include/boot/picobin.h new file mode 100644 index 000000000..44ce9909a --- /dev/null +++ b/src/common/boot_picobin_headers/include/boot/picobin.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT_PICOBIN_H +#define _BOOT_PICOBIN_H + +#ifndef NO_PICO_PLATFORM +#include "pico/platform.h" +#else +#ifndef _u +#define _u(x) x ## u +#endif +#endif + +/** \file picobin.h +* \defgroup boot_picobin_headers boot_picobin_headers +* +* \brief Constants for PICOBIN format +*/ + +// these are designed to not look like (likely) 16/32-bit ARM or RISC-V instructions or look like valid pointers +#define PICOBIN_BLOCK_MARKER_START _u(0xffffded3) +#define PICOBIN_BLOCK_MARKER_END _u(0xab123579) + +#define PICOBIN_MAX_BLOCK_SIZE _u(0x280) +#define PICOBIN_MAX_IMAGE_DEF_BLOCK_SIZE _u(0x180) +#define PICOBIN_MAX_PARTITION_TABLE_BLOCK_SIZE _u(0x280) + +// note bit 6 is used to make parity even +#define PICOBIN_BLOCK_ITEM_1BS_NEXT_BLOCK_OFFSET _u(0x41) +#define PICOBIN_BLOCK_ITEM_1BS_IMAGE_TYPE _u(0x42) +#define PICOBIN_BLOCK_ITEM_1BS_VECTOR_TABLE _u(0x03) +#define PICOBIN_BLOCK_ITEM_1BS_ENTRY_POINT _u(0x44) +#define PICOBIN_BLOCK_ITEM_1BS_ROLLING_WINDOW_DELTA _u(0x05) +#define PICOBIN_BLOCK_ITEM_LOAD_MAP _u(0x06) +#define PICOBIN_BLOCK_ITEM_1BS_HASH_DEF _u(0x47) +#define PICOBIN_BLOCK_ITEM_1BS_VERSION _u(0x48) +#define PICOBIN_BLOCK_ITEM_SIGNATURE _u(0x09) +#define PICOBIN_BLOCK_ITEM_PARTITION_TABLE _u(0x0a) +#define PICOBIN_BLOCK_ITEM_HASH_VALUE _u(0x4b) +#define PICOBIN_BLOCK_ITEM_SALT _u(0x0c) + +#define PICOBIN_BLOCK_ITEM_2BS_IGNORED (_u(0x80) | _u(0x7e)) +#define PICOBIN_BLOCK_ITEM_2BS_LAST (_u(0x80) | _u(0x7f)) + +// ---- + +#define PICOBIN_INDEX_TO_BITS(y, x) (y ## _ ## x << y ## _LSB) + +#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_LSB _u(0) +#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_BITS _u(0x000f) +#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_INVALID _u(0x0) +#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_EXE _u(0x1) +#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_DATA _u(0x2) +#define PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_IMAGE_TYPE, x) + +#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_LSB _u(4) +#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_BITS _u(0x0030) +#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_UNSPECIFIED _u(0x0) +#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_NS _u(0x1) +#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_S _u(0x2) +#define PICOBIN_IMAGE_TYPE_EXE_SECURITY_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_EXE_SECURITY, x) + +#define PICOBIN_IMAGE_TYPE_EXE_CPU_LSB _u(8) +#define PICOBIN_IMAGE_TYPE_EXE_CPU_BITS _u(0x0700) +#define PICOBIN_IMAGE_TYPE_EXE_CPU_ARM _u(0) +#define PICOBIN_IMAGE_TYPE_EXE_CPU_RISCV _u(1) +#define PICOBIN_IMAGE_TYPE_EXE_CPU_VARMULET _u(2) +#define PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_EXE_CPU, x) + +#define PICOBIN_IMAGE_TYPE_EXE_CHIP_LSB _u(12) +#define PICOBIN_IMAGE_TYPE_EXE_CHIP_BITS _u(0x7000) +#define PICOBIN_IMAGE_TYPE_EXE_CHIP_RP2040 _u(0) +#define PICOBIN_IMAGE_TYPE_EXE_CHIP_RP2350 _u(1) +#define PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_IMAGE_TYPE_EXE_CHIP, x) + +#define PICOBIN_IMAGE_TYPE_EXE_TBYB_BITS _u(0x8000) + +// todo assert no overlap ^ + +#define PICOBIN_PARTITION_PERMISSIONS_LSB _u(26) +#define PICOBIN_PARTITION_PERMISSIONS_BITS _u(0xfc000000) + +#define PICOBIN_PARTITION_PERMISSION_S_R_BITS _u(0x04000000) +#define PICOBIN_PARTITION_PERMISSION_S_W_BITS _u(0x08000000) +#define PICOBIN_PARTITION_PERMISSION_NS_R_BITS _u(0x10000000) +#define PICOBIN_PARTITION_PERMISSION_NS_W_BITS _u(0x20000000) +#define PICOBIN_PARTITION_PERMISSION_NSBOOT_R_BITS _u(0x40000000) +#define PICOBIN_PARTITION_PERMISSION_NSBOOT_W_BITS _u(0x80000000) + +#define PICOBIN_PARTITION_LOCATION_FIRST_SECTOR_LSB _u(0) +#define PICOBIN_PARTITION_LOCATION_FIRST_SECTOR_BITS _u(0x00001fff) +#define PICOBIN_PARTITION_LOCATION_LAST_SECTOR_LSB _u(13) +#define PICOBIN_PARTITION_LOCATION_LAST_SECTOR_BITS _u(0x03ffe000) + +#define PICOBIN_PARTITION_FLAGS_HAS_ID_BITS _u(0x00000001) +#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_LSB _u(1) +#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_BITS _u(0x00000006) +#define PICOBIN_PARTITION_FLAGS_LINK_VALUE_LSB _u(3) +#define PICOBIN_PARTITION_FLAGS_LINK_VALUE_BITS _u(0x00000078) + +#define PICOBIN_PARTITION_MAX_EXTRA_FAMILIES _u(3) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_NUM_EXTRA_FAMILIES_LSB _u(7) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_NUM_EXTRA_FAMILIES_BITS _u(0x00000180) +// these are an optimization when booting in either ARM or RISC-V, to avoid looking at partitions +// which are known not to contain the right sort of binary, OR as a way to prevent +// auto-architecture-switch. NOTE: the first partition that can be booted, will be, +// so if you have a RISC-V binary in the first partition, and auto-arhcitecture-switch enabled, then +// even if booting under ARM, with an ARM binary in a later partition, the RISC-V binary +// will be booted by default; setting PICOBIN_PARTITION_FLAGS_IGNORED_DURING_ARM_BOOT_BITS +// on the partition, will have the RISC-V binary containing partition ignored under ARM +// boot +#define PICOBIN_PARTITION_FLAGS_IGNORED_DURING_ARM_BOOT_BITS _u(0x00000200) +#define PICOBIN_PARTITION_FLAGS_IGNORED_DURING_RISCV_BOOT_BITS _u(0x00000400) +#define PICOBIN_PARTITION_FLAGS_UF2_DOWNLOAD_AB_NON_BOOTABLE_OWNER_AFFINITY _u(0x00000800) +#define PICOBIN_PARTITION_FLAGS_HAS_NAME_BITS _u(0x00001000) +#define PICOBIN_PARTITION_FLAGS_UF2_DOWNLOAD_NO_REBOOT_BITS _u(0x00002000) +// we have a bit for each well known family-id .. note we expect there to be more in the future with new chips, +// but we have plenty of space for now. +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILIES_LSB _u(14) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2040_BITS _u(0x00004000) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_ABSOLUTE_BITS _u(0x00008000) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_DATA_BITS _u(0x00010000) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2350_ARM_S_BITS _u(0x00020000) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2350_RISCV_BITS _u(0x00040000) +#define PICOBIN_PARTITION_FLAGS_ACCEPTS_DEFAULT_FAMILY_RP2350_ARM_NS_BITS _u(0x00080000) + +#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_NONE _u(0) +#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_A_PARTITION _u(1) +#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_OWNER_PARTITION _u(2) +#define PICOBIN_PARTITION_FLAGS_LINK_TYPE_AS_BITS(x) PICOBIN_INDEX_TO_BITS(PICOBIN_PARTITION_FLAGS_LINK_TYPE, x) + + +#define PICOBIN_HASH_SHA256 _u(0x01) + +#define PICOBIN_SIGNATURE_SECP256K1 _u(0x01) + +#ifndef __ASSEMBLER__ + +#include + +typedef struct { + // these must all be word aligned + uint32_t storage_address_rel; + uint32_t runtime_address; + uint32_t size; +} picobin_load_map_entry; + +typedef struct { + uint32_t header; + picobin_load_map_entry entries[]; +} picobin_load_map; + +static inline unsigned int picobin_load_map_entry_count(const picobin_load_map *lm) { + return (lm->header << 1) >> 25; +} + +static inline bool picobin_load_map_is_relative(const picobin_load_map *lm) { + return (int32_t)lm->header >= 0; +} + +#endif + +#endif diff --git a/src/common/boot_picoboot/BUILD.bazel b/src/common/boot_picoboot/BUILD.bazel deleted file mode 100644 index 5007a2333..000000000 --- a/src/common/boot_picoboot/BUILD.bazel +++ /dev/null @@ -1,8 +0,0 @@ -package(default_visibility = ["//visibility:public"]) - -cc_library( - name = "boot_picoboot", - hdrs = ["include/boot/picoboot.h"], - includes = ["include"], - deps = ["//src/common/pico_base:pico_platform"], -) diff --git a/src/common/boot_picoboot/CMakeLists.txt b/src/common/boot_picoboot/CMakeLists.txt deleted file mode 100644 index 463fde42d..000000000 --- a/src/common/boot_picoboot/CMakeLists.txt +++ /dev/null @@ -1,2 +0,0 @@ -add_library(boot_picoboot_headers INTERFACE) -target_include_directories(boot_picoboot_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/src/common/boot_picoboot_headers/BUILD.bazel b/src/common/boot_picoboot_headers/BUILD.bazel new file mode 100644 index 000000000..ec09b7d44 --- /dev/null +++ b/src/common/boot_picoboot_headers/BUILD.bazel @@ -0,0 +1,11 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "boot_picoboot_headers", + hdrs = [ + "include/boot/picoboot.h", + "include/boot/picoboot_constants.h", + ], + includes = ["include"], + deps = ["//src:pico_platform_internal"], +) diff --git a/src/common/boot_picoboot_headers/CMakeLists.txt b/src/common/boot_picoboot_headers/CMakeLists.txt new file mode 100644 index 000000000..ad32efd02 --- /dev/null +++ b/src/common/boot_picoboot_headers/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(boot_picoboot_headers INTERFACE) +target_include_directories(boot_picoboot_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/src/common/boot_picoboot/include/boot/picoboot.h b/src/common/boot_picoboot_headers/include/boot/picoboot.h similarity index 64% rename from src/common/boot_picoboot/include/boot/picoboot.h rename to src/common/boot_picoboot_headers/include/boot/picoboot.h index fa9d4637f..8645d52d7 100644 --- a/src/common/boot_picoboot/include/boot/picoboot.h +++ b/src/common/boot_picoboot_headers/include/boot/picoboot.h @@ -16,18 +16,20 @@ #endif /** \file picoboot.h -* \defgroup boot_picoboot boot_picoboot +* \defgroup boot_picoboot_headers boot_picoboot_headers * -* \brief Header file for the PICOBOOT USB interface exposed by an RP2040 in BOOTSEL mode. +* \brief Header file for the PICOBOOT USB interface exposed by an RP2xxx chip in BOOTSEL mode */ +#include "picoboot_constants.h" + #define PICOBOOT_MAGIC 0x431fd10bu // -------------------------------------------- // CONTROL REQUESTS FOR THE PICOBOOT INTERFACE // -------------------------------------------- -// size 0 OUT - unstall EPs and reset +// size 0 OUT - un-stall EPs and reset #define PICOBOOT_IF_RESET 0x41 // size 16 IN - return the status of the last command @@ -47,11 +49,17 @@ enum picoboot_cmd_id { PC_REBOOT = 0x2, PC_FLASH_ERASE = 0x3, PC_READ = 0x84, // either RAM or FLASH - PC_WRITE = 5, // either RAM or FLASH (does no erase) + PC_WRITE = 0x5, // either RAM or FLASH (does no erase) PC_EXIT_XIP = 0x6, PC_ENTER_CMD_XIP = 0x7, PC_EXEC = 0x8, - PC_VECTORIZE_FLASH = 0x9 + PC_VECTORIZE_FLASH = 0x9, + // RP2350 only below here + PC_REBOOT2 = 0xa, + PC_GET_INFO = 0x8b, + PC_OTP_READ = 0x8c, + PC_OTP_WRITE = 0xd, + //PC_EXEC2 = 0xe, // currently unused }; enum picoboot_status { @@ -64,14 +72,32 @@ enum picoboot_status { PICOBOOT_INTERLEAVED_WRITE = 6, PICOBOOT_REBOOTING = 7, PICOBOOT_UNKNOWN_ERROR = 8, + PICOBOOT_INVALID_STATE = 9, + PICOBOOT_NOT_PERMITTED = 10, + PICOBOOT_INVALID_ARG = 11, + PICOBOOT_BUFFER_TOO_SMALL = 12, + PICOBOOT_PRECONDITION_NOT_MET = 13, + PICOBOOT_MODIFIED_DATA = 14, + PICOBOOT_INVALID_DATA = 15, + PICOBOOT_NOT_FOUND = 16, + PICOBOOT_UNSUPPORTED_MODIFICATION = 17, }; struct __packed picoboot_reboot_cmd { - uint32_t dPC; // 0 means reset into bootrom + uint32_t dPC; // 0 means reset into regular boot path uint32_t dSP; uint32_t dDelayMS; }; + +// note this (with pc_sp) union member has the same layout as picoboot_reboot_cmd except with extra dFlags +struct __packed picoboot_reboot2_cmd { + uint32_t dFlags; + uint32_t dDelayMS; + uint32_t dParam0; + uint32_t dParam1; +}; + // used for EXEC, VECTORIZE_FLASH struct __packed picoboot_address_only_cmd { uint32_t dAddr; @@ -83,6 +109,13 @@ struct __packed picoboot_range_cmd { uint32_t dSize; }; +struct __packed picoboot_exec2_cmd { + uint32_t image_base; + uint32_t image_size; + uint32_t workarea_base; + uint32_t workarea_size; +}; + enum picoboot_exclusive_type { NOT_EXCLUSIVE = 0, EXCLUSIVE, @@ -93,6 +126,20 @@ struct __packed picoboot_exclusive_cmd { uint8_t bExclusive; }; +struct __packed picoboot_otp_cmd { + uint16_t wRow; // OTP row + uint16_t wRowCount; // number of rows to transfer + uint8_t bEcc; // use error correction (16 bit per register vs 24 (stored as 32) bit raw) +}; + + +struct __packed picoboot_get_info_cmd { + uint8_t bType; + uint8_t bParam; + uint16_t wParam; + uint32_t dParams[3]; +}; + // little endian struct __packed __aligned(4) picoboot_cmd { uint32_t dMagic; @@ -107,9 +154,12 @@ struct __packed __aligned(4) picoboot_cmd { struct picoboot_range_cmd range_cmd; struct picoboot_address_only_cmd address_only_cmd; struct picoboot_exclusive_cmd exclusive_cmd; + struct picoboot_reboot2_cmd reboot2_cmd; + struct picoboot_otp_cmd otp_cmd; + struct picoboot_get_info_cmd get_info_cmd; + struct picoboot_exec2_cmd exec2_cmd; }; }; - static_assert(32 == sizeof(struct picoboot_cmd), "picoboot_cmd must be 32 bytes big"); struct __packed __aligned(4) picoboot_cmd_status { @@ -121,4 +171,5 @@ struct __packed __aligned(4) picoboot_cmd_status { }; static_assert(16 == sizeof(struct picoboot_cmd_status), "picoboot_cmd_status must be 16 bytes big"); + #endif diff --git a/src/common/boot_picoboot_headers/include/boot/picoboot_constants.h b/src/common/boot_picoboot_headers/include/boot/picoboot_constants.h new file mode 100644 index 000000000..ac78ea213 --- /dev/null +++ b/src/common/boot_picoboot_headers/include/boot/picoboot_constants.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT_PICOBOOT_CONSTANTS_H +#define _BOOT_PICOBOOT_CONSTANTS_H + +#define REBOOT2_TYPE_MASK 0x0f + +// note these match REBOOT_TYPE in pico/bootrom_constants.h (also 0 is used for PC_SP for backwards compatibility with RP2040) +// values 0-7 are secure/non-secure +#define REBOOT2_FLAG_REBOOT_TYPE_NORMAL 0x0 // param0 = diagnostic partition +#define REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL 0x2 // param0 = bootsel_flags, param1 = gpio_config +#define REBOOT2_FLAG_REBOOT_TYPE_RAM_IMAGE 0x3 // param0 = image_base, param1 = image_end +#define REBOOT2_FLAG_REBOOT_TYPE_FLASH_UPDATE 0x4 // param0 = update_base + +// values 8-15 are secure only +#define REBOOT2_FLAG_REBOOT_TYPE_PC_SP 0xd + +#define REBOOT2_FLAG_REBOOT_TO_ARM 0x10 +#define REBOOT2_FLAG_REBOOT_TO_RISCV 0x20 + +#define REBOOT2_FLAG_NO_RETURN_ON_SUCCESS 0x100 + +#define BOOTSEL_FLAG_DISABLE_MSD_INTERFACE 0x01 +#define BOOTSEL_FLAG_DISABLE_PICOBOOT_INTERFACE 0x02 +#define BOOTSEL_FLAG_GPIO_PIN_ACTIVE_LOW 0x10 +#define BOOTSEL_FLAG_GPIO_PIN_SPECIFIED 0x20 + +#define PICOBOOT_GET_INFO_SYS 1 +#define PICOBOOT_GET_INFO_PARTTION_TABLE 2 +#define PICOBOOT_GET_INFO_UF2_TARGET_PARTITION 3 +#define PICOBOOT_GET_INFO_UF2_STATUS 4 + +#define UF2_STATUS_IGNORED_FAMILY 0x01 +#define UF2_STATUS_ABORT_EXCLUSIVELY_LOCKED 0x10 +#define UF2_STATUS_ABORT_BAD_ADDRESS 0x20 +#define UF2_STATUS_ABORT_WRITE_ERROR 0x40 +#define UF2_STATUS_ABORT_REBOOT_FAILED 0x80 +#endif \ No newline at end of file diff --git a/src/common/boot_uf2/CMakeLists.txt b/src/common/boot_uf2/CMakeLists.txt deleted file mode 100644 index 6ca5c2063..000000000 --- a/src/common/boot_uf2/CMakeLists.txt +++ /dev/null @@ -1,2 +0,0 @@ -add_library(boot_uf2_headers INTERFACE) -target_include_directories(boot_uf2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/src/common/boot_uf2/BUILD.bazel b/src/common/boot_uf2_headers/BUILD.bazel similarity index 80% rename from src/common/boot_uf2/BUILD.bazel rename to src/common/boot_uf2_headers/BUILD.bazel index a170f6967..e0df04f7f 100644 --- a/src/common/boot_uf2/BUILD.bazel +++ b/src/common/boot_uf2_headers/BUILD.bazel @@ -1,7 +1,7 @@ package(default_visibility = ["//visibility:public"]) cc_library( - name = "boot_uf2", + name = "boot_uf2_headers", hdrs = ["include/boot/uf2.h"], includes = ["include"], ) diff --git a/src/common/boot_uf2_headers/CMakeLists.txt b/src/common/boot_uf2_headers/CMakeLists.txt new file mode 100644 index 000000000..a314c6fec --- /dev/null +++ b/src/common/boot_uf2_headers/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(boot_uf2_headers INTERFACE) +target_include_directories(boot_uf2_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/src/common/boot_uf2/include/boot/uf2.h b/src/common/boot_uf2_headers/include/boot/uf2.h similarity index 65% rename from src/common/boot_uf2/include/boot/uf2.h rename to src/common/boot_uf2_headers/include/boot/uf2.h index e360cf483..271540a20 100644 --- a/src/common/boot_uf2/include/boot/uf2.h +++ b/src/common/boot_uf2_headers/include/boot/uf2.h @@ -11,9 +11,9 @@ #include /** \file uf2.h -* \defgroup boot_uf2 boot_uf2 +* \defgroup boot_uf2_headers boot_uf2_headers * -* \brief Header file for the UF2 format supported by an RP2040 in BOOTSEL mode. +* \brief Header file for the UF2 format supported by a RP2xxx chip in BOOTSEL mode */ #define UF2_MAGIC_START0 0x0A324655u @@ -25,7 +25,14 @@ #define UF2_FLAG_FAMILY_ID_PRESENT 0x00002000u #define UF2_FLAG_MD5_PRESENT 0x00004000u -#define RP2040_FAMILY_ID 0xe48bff56 +#define RP2040_FAMILY_ID 0xe48bff56u +#define ABSOLUTE_FAMILY_ID 0xe48bff57u +#define DATA_FAMILY_ID 0xe48bff58u +#define RP2350_ARM_S_FAMILY_ID 0xe48bff59u +#define RP2350_RISCV_FAMILY_ID 0xe48bff5au +#define RP2350_ARM_NS_FAMILY_ID 0xe48bff5bu +#define FAMILY_ID_MAX 0xe48bff5bu + struct uf2_block { // 32 byte header diff --git a/src/common/hardware_claim/BUILD.bazel b/src/common/hardware_claim/BUILD.bazel new file mode 100644 index 000000000..e8ca0f39e --- /dev/null +++ b/src/common/hardware_claim/BUILD.bazel @@ -0,0 +1,19 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_claim", + srcs = ["claim.c"], + hdrs = ["include/hardware/claim.h"], + includes = ["include"], + deps = [ + ] + select({ + "//bazel/constraint:host": [ + "//src/host/hardware_sync", + ], + "//conditions:default": [ + "//src:pico_platform_internal", + "//src/rp2_common/hardware_sync:hardware_sync_headers", + "//src/rp2_common/hardware_sync_spin_lock", + ], + }), +) diff --git a/src/rp2_common/hardware_claim/CMakeLists.txt b/src/common/hardware_claim/CMakeLists.txt similarity index 100% rename from src/rp2_common/hardware_claim/CMakeLists.txt rename to src/common/hardware_claim/CMakeLists.txt diff --git a/src/rp2_common/hardware_claim/claim.c b/src/common/hardware_claim/claim.c similarity index 100% rename from src/rp2_common/hardware_claim/claim.c rename to src/common/hardware_claim/claim.c diff --git a/src/rp2_common/hardware_claim/include/hardware/claim.h b/src/common/hardware_claim/include/hardware/claim.h similarity index 98% rename from src/rp2_common/hardware_claim/include/hardware/claim.h rename to src/common/hardware_claim/include/hardware/claim.h index 9d696913b..f9501440c 100644 --- a/src/rp2_common/hardware_claim/include/hardware/claim.h +++ b/src/common/hardware_claim/include/hardware/claim.h @@ -12,8 +12,7 @@ /** \file claim.h * \defgroup hardware_claim hardware_claim - * - * \brief Lightweight hardware resource management + * \brief Lightweight hardware resource management API * * `hardware_claim` provides a simple API for management of hardware resources at runtime. * diff --git a/src/common/pico_base/include/pico/error.h b/src/common/pico_base/include/pico/error.h deleted file mode 100644 index 7508f1644..000000000 --- a/src/common/pico_base/include/pico/error.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_ERROR_H -#define _PICO_ERROR_H - -#ifndef __ASSEMBLER__ - -/*! - * \brief Common return codes from pico_sdk methods that return a status - * \ingroup pico_base - */ -enum pico_error_codes { - PICO_OK = 0, - PICO_ERROR_NONE = 0, - PICO_ERROR_TIMEOUT = -1, - PICO_ERROR_GENERIC = -2, - PICO_ERROR_NO_DATA = -3, - PICO_ERROR_NOT_PERMITTED = -4, - PICO_ERROR_INVALID_ARG = -5, - PICO_ERROR_IO = -6, - PICO_ERROR_BADAUTH = -7, - PICO_ERROR_CONNECT_FAILED = -8, - PICO_ERROR_INSUFFICIENT_RESOURCES = -9, -}; - -#endif // !__ASSEMBLER__ - -#endif \ No newline at end of file diff --git a/src/common/pico_base/BUILD.bazel b/src/common/pico_base_headers/BUILD.bazel similarity index 51% rename from src/common/pico_base/BUILD.bazel rename to src/common/pico_base_headers/BUILD.bazel index 4204efdfe..5525c309b 100644 --- a/src/common/pico_base/BUILD.bazel +++ b/src/common/pico_base_headers/BUILD.bazel @@ -2,23 +2,23 @@ load("@bazel_skylib//rules:run_binary.bzl", "run_binary") package(default_visibility = ["//visibility:public"]) -# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base +# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_STRING, SDK version string, type=string, default=Current SDK version string, group=pico_base PICO_SDK_VERSION_STRING = module_version() if module_version() != None else "0.0.1-WORKSPACE" _version_parts = PICO_SDK_VERSION_STRING.split(".") -# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, group=pico_base +# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, default=Current SDK major version, group=pico_base PICO_SDK_VERSION_MAJOR = int(_version_parts[0]) -# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base +# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, default=Current SDK minor version, group=pico_base PICO_SDK_VERSION_MINOR = int(_version_parts[1]) _revision_parts = _version_parts[2].split("-") -# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base +# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, default=Current SDK revision, group=pico_base PICO_SDK_VERSION_REVISION = int(_revision_parts[0]) -# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base +# PICO_BAZEL_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, Optional SDK pre-release version identifier, default=Current SDK pre-release identifier, type=string, group=pico_base PICO_SDK_VERSION_PRE_RELEASE_ID = _revision_parts[1] if len(_revision_parts) > 1 else None run_binary( @@ -34,43 +34,27 @@ run_binary( visibility = ["//visibility:private"], ) -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, group=pico_base -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, group=pico_base -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, group=pico_base -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, optional SDK pre-release version identifier, type=string, group=pico_base -# PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version, type=string, group=pico_base +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MAJOR, SDK major version number, type=int, default=Current SDK major version, group=pico_base +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_MINOR, SDK minor version number, type=int, default=Current SDK minor version, group=pico_base +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_REVISION, SDK version revision, type=int, default=Current SDK revision, group=pico_base +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, Optional SDK pre-release version identifier, default=Current SDK pre-release identifier, type=string, group=pico_base +# PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version string, type=string, default=Current SDK version string, group=pico_base cc_library( name = "version", hdrs = ["generated_include/pico/version.h"], defines = [ 'PICO_SDK_VERSION_STRING=\\"{}\\"'.format(PICO_SDK_VERSION_STRING), "PICO_SDK_VERSION_MAJOR={}".format(PICO_SDK_VERSION_MAJOR), - 'PICO_SDK_VERSION_MINOR={}"'.format(PICO_SDK_VERSION_MINOR), - 'PICO_SDK_VERSION_REVISION={}"'.format(PICO_SDK_VERSION_REVISION), + "PICO_SDK_VERSION_MINOR={}".format(PICO_SDK_VERSION_MINOR), + "PICO_SDK_VERSION_REVISION={}".format(PICO_SDK_VERSION_REVISION), ] + [] if PICO_SDK_VERSION_PRE_RELEASE_ID == None else ['PICO_SDK_VERSION_PRE_RELEASE_ID=\\"{}\\"'.format(PICO_SDK_VERSION_PRE_RELEASE_ID)], includes = ["generated_include"], ) -alias( - name = "platform_defs", - actual = select({ - "//bazel/constraint:host": "//src/host/pico_platform:platform_defs", - "//conditions:default": "//src/rp2_common/pico_platform:platform_defs", - }), -) - -alias( - name = "pico_platform", - actual = select({ - "//bazel/constraint:host": "//src/host/pico_platform:pico_platform", - "//conditions:default": "//src/rp2_common/pico_platform:pico_platform", - }), -) - -# PICO_BAZEL_CONFIG: PICO_NO_HARDWARE, OPTION: Whether the build is not targeting an RP2040 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build -# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build -# PICO_BAZEL_CONFIG: PICO_ON_DEVICE, OPTION: Whether the build is targeting an RP2040 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build -# PICO_BUILD_DEFINE: PICO_ON_DEVICE, Whether the build is targeting an RP2040 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build +# PICO_BAZEL_CONFIG: PICO_NO_HARDWARE, Option as to whether the build is not targeting an RP2040 or RP2350 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build +# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 or RP2350 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build +# PICO_BAZEL_CONFIG: PICO_ON_DEVICE, Option as to whether the build is targeting an RP2040 or RP2350 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build +# PICO_BUILD_DEFINE: PICO_ON_DEVICE, Whether the build is targeting an RP2040 or RP2350 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build # PICO_BUILD is undocumented in CMake. cc_library( name = "common_sdk_defines", @@ -85,11 +69,19 @@ cc_library( "PICO_NO_HARDWARE=0", "PICO_BUILD=1", ], + }) + select({ + "//bazel/constraint:rp2040": ["PICO_RP2040=1"], + "//bazel/constraint:rp2350": ["PICO_RP2350=1"], + "//conditions:default": [], }), ) +# While this provides the "pico.h" header, nearly everything should +# instead depend on `//src/rp2_common:pico_platform` to get these headers. If +# you try to depend on just `pico_base_headers`, you'll end up with missing +# symbols. cc_library( - name = "pico_base_interface", + name = "pico_base_headers", hdrs = [ "include/pico.h", "include/pico/assert.h", @@ -98,57 +90,38 @@ cc_library( "include/pico/types.h", ], includes = ["include"], - - # Be extra careful about who references this for now; if users depend on - # this but not `pico_base` they'll end up with undefined symbols. - # It's generally safe for anything that circularly depends on - # //src/common/pico_base:pico_base to be added to this allowlist because - # that implicitly means the transitive dependencies of pico_base will get - # linked in. visibility = [ - "//src/common/pico_binary_info:__pkg__", - "//src/common/pico_sync:__pkg__", - "//src/common/pico_time:__pkg__", - "//src/common/pico_util:__pkg__", + "//src/common:__subpackages__", + "//src/host/hardware_sync:__pkg__", "//src/host/hardware_timer:__pkg__", "//src/host/pico_platform:__pkg__", - "//src/rp2_common/boot_stage2:__pkg__", - "//src/rp2_common/hardware_claim:__pkg__", + "//src/rp2040/boot_stage2:__pkg__", + "//src/rp2040/pico_platform:__pkg__", + "//src/rp2350/boot_stage2:__pkg__", + "//src/rp2350/pico_platform:__pkg__", + "//src/rp2_common/hardware_base:__pkg__", + "//src/rp2_common/hardware_boot_lock:__pkg__", "//src/rp2_common/hardware_clocks:__pkg__", "//src/rp2_common/hardware_gpio:__pkg__", - "//src/rp2_common/hardware_irq:__pkg__", "//src/rp2_common/hardware_pll:__pkg__", "//src/rp2_common/hardware_resets:__pkg__", "//src/rp2_common/hardware_sync:__pkg__", + "//src/rp2_common/hardware_sync_spin_lock:__pkg__", + "//src/rp2_common/hardware_ticks:__pkg__", "//src/rp2_common/hardware_timer:__pkg__", "//src/rp2_common/hardware_watchdog:__pkg__", "//src/rp2_common/hardware_xosc:__pkg__", - "//src/rp2_common/pico_bootrom:__pkg__", - "//src/rp2_common/pico_malloc:__pkg__", - "//src/rp2_common/pico_platform:__pkg__", + "//src/rp2_common/pico_crt0:__pkg__", "//src/rp2_common/pico_printf:__pkg__", "//src/rp2_common/pico_runtime:__pkg__", - "//src/rp2_common/pico_standard_link:__pkg__", + "//src/rp2_common/pico_runtime_init:__pkg__", + "//src/rp2_common/pico_time_adapter:__pkg__", + "@picotool//:__subpackages__", ], deps = [ ":common_sdk_defines", ":version", "//bazel/config:PICO_CONFIG_HEADER", - ], -) - -cc_library( - name = "pico_base", - implementation_deps = select({ - "//bazel/constraint:host": [], - "//conditions:default": [ - "//src/rp2_common/pico_platform:platform_link_deps", - ], - }), - deps = [ - # :pico_platform creates circular dependencies, so break them - # via an intermediate. - ":pico_platform", - ":pico_base_interface", + "//src:pico_platform_internal", ], ) diff --git a/src/common/pico_base/CMakeLists.txt b/src/common/pico_base_headers/CMakeLists.txt similarity index 81% rename from src/common/pico_base/CMakeLists.txt rename to src/common/pico_base_headers/CMakeLists.txt index ef051bb72..57973fea7 100644 --- a/src/common/pico_base/CMakeLists.txt +++ b/src/common/pico_base_headers/CMakeLists.txt @@ -1,6 +1,6 @@ if (NOT TARGET pico_base_headers) pico_add_library(pico_base NOFLAG) - target_include_directories(pico_base_headers INTERFACE include ${CMAKE_BINARY_DIR}/generated/pico_base) + target_include_directories(pico_base_headers SYSTEM INTERFACE include ${CMAKE_BINARY_DIR}/generated/pico_base) # PICO_BUILD_DEFINE: PICO_BOARD, Name of board, type=string, default=CMake PICO_BOARD variable, group=pico_base target_compile_definitions(pico_base_headers INTERFACE diff --git a/src/common/pico_base/generate_config_header.cmake b/src/common/pico_base_headers/generate_config_header.cmake similarity index 60% rename from src/common/pico_base/generate_config_header.cmake rename to src/common/pico_base_headers/generate_config_header.cmake index 5cc6aff69..46b4e13ef 100644 --- a/src/common/pico_base/generate_config_header.cmake +++ b/src/common/pico_base_headers/generate_config_header.cmake @@ -2,6 +2,7 @@ set(header_content "// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO__CONFIG_HEADER_FILES\n// DO NOT EDIT!\n") string(TOUPPER ${PICO_PLATFORM} PICO_PLATFORM_UPPER) +string(REGEX REPLACE "-" "_" PICO_PLATFORM_UPPER "${PICO_PLATFORM_UPPER}") macro(add_header_content_from_var VAR) set(header_content "${header_content}\n\n// based on ${VAR}:\n") @@ -13,9 +14,12 @@ endmacro() # PICO_CMAKE_CONFIG: PICO_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for all platforms, type=list, group=pico_base add_header_content_from_var(PICO_CONFIG_HEADER_FILES) -# PICO_CMAKE_CONFIG: PICO_RP2040_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for rp2040 platform, type=list, group=pico_base -# PICO_CMAKE_CONFIG: PICO_HOST_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for host platform, type=list, group=pico_base +# PICO_CMAKE_CONFIG: PICO_RP2040_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the rp2040 platform only, type=list, group=pico_base +# PICO_CMAKE_CONFIG: PICO_RP2350_ARM_S_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the rp2350-arm-s platform only, type=list, group=pico_base +# PICO_CMAKE_CONFIG: PICO_RP2350_RISCV_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the riscv platform only, type=list, group=pico_base +# PICO_CMAKE_CONFIG: PICO_HOST_CONFIG_HEADER_FILES, List of extra header files to include from pico/config.h for the host platform only, type=list, group=pico_base add_header_content_from_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES) +pico_register_common_scope_var(PICO_${PICO_PLATFORM_UPPER}_CONFIG_HEADER_FILES) file(GENERATE OUTPUT ${CMAKE_BINARY_DIR}/generated/pico_base/pico/config_autogen.h @@ -25,5 +29,5 @@ file(GENERATE configure_file( ${CMAKE_CURRENT_LIST_DIR}/include/pico/version.h.in ${CMAKE_BINARY_DIR}/generated/pico_base/pico/version.h) foreach(DIR IN LISTS PICO_INCLUDE_DIRS) - target_include_directories(pico_base_headers INTERFACE ${DIR}) + target_include_directories(pico_base_headers SYSTEM INTERFACE ${DIR}) endforeach() diff --git a/src/common/pico_base/include/pico.h b/src/common/pico_base_headers/include/pico.h similarity index 75% rename from src/common/pico_base/include/pico.h rename to src/common/pico_base_headers/include/pico.h index 5b7dbe9ee..3b0f2f14a 100644 --- a/src/common/pico_base/include/pico.h +++ b/src/common/pico_base_headers/include/pico.h @@ -10,13 +10,15 @@ /** \file pico.h * \defgroup pico_base pico_base * - * \brief Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code + * \brief Core types and macros for the Raspberry Pi Pico SDK. + * + * This header is intended to be included by all source code * as it includes configuration headers and overrides in the correct order * * This header may be included by assembly code */ -// We may be included by assembly which cant include +// We may be included by assembly which can't include #define __PICO_STRING(x) #x #define __PICO_XSTRING(x) __PICO_STRING(x) #define __PICO_CONCAT1(x, y) x ## y @@ -24,7 +26,7 @@ #include "pico/types.h" #include "pico/version.h" -// PICO_CONFIG: PICO_CONFIG_HEADER, unquoted path to header include in place of the default pico/config.h which may be desirable for build systems which can't easily generate the config_autogen header, group=pico_base +// PICO_CONFIG: PICO_CONFIG_HEADER, Unquoted path to header include in place of the default pico/config.h which may be desirable for build systems which can't easily generate the config_autogen header, group=pico_base #ifdef PICO_CONFIG_HEADER #include __PICO_XSTRING(PICO_CONFIG_HEADER) #else diff --git a/src/common/pico_base/include/pico/assert.h b/src/common/pico_base_headers/include/pico/assert.h similarity index 90% rename from src/common/pico_base/include/pico/assert.h rename to src/common/pico_base_headers/include/pico/assert.h index 8910ebdb8..36e25efae 100644 --- a/src/common/pico_base/include/pico/assert.h +++ b/src/common/pico_base_headers/include/pico/assert.h @@ -34,6 +34,7 @@ extern "C" { #define invalid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test));}) #define valid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(test);}) #define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));}) +#define invalid_params_if_and_return(x, test, rc) ({/*if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test)); */ if (test) return rc; }) #ifdef NDEBUG extern void hard_assertion_failure(void); diff --git a/src/common/pico_base/include/pico/config.h b/src/common/pico_base_headers/include/pico/config.h similarity index 92% rename from src/common/pico_base/include/pico/config.h rename to src/common/pico_base_headers/include/pico/config.h index 6bd6a97fc..df0a04347 100644 --- a/src/common/pico_base/include/pico/config.h +++ b/src/common/pico_base_headers/include/pico/config.h @@ -18,7 +18,7 @@ #include "pico/config_autogen.h" -// PICO_CONFIG: PICO_CONFIG_RTOS_ADAPTER_HEADER, unquoted path to header include in the default pico/config.h for RTOS integration defines that must be included in all sources, group=pico_base +// PICO_CONFIG: PICO_CONFIG_RTOS_ADAPTER_HEADER, Unquoted path to header include in the default pico/config.h for RTOS integration defines that must be included in all sources, group=pico_base #ifdef PICO_CONFIG_RTOS_ADAPTER_HEADER #include __PICO_XSTRING(PICO_CONFIG_RTOS_ADAPTER_HEADER) #endif diff --git a/src/common/pico_base_headers/include/pico/error.h b/src/common/pico_base_headers/include/pico/error.h new file mode 100644 index 000000000..9212eda81 --- /dev/null +++ b/src/common/pico_base_headers/include/pico/error.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_ERROR_H +#define _PICO_ERROR_H + +#ifndef __ASSEMBLER__ + +/*! + * \brief Common return codes from pico_sdk methods that return a status + * + * All `PICO_ERROR_` values are negative so they can be returned from functions that also + * want to return a zero or positive value on success. + * + * Note these error codes may be returned via bootrom functions too. + * + * \ingroup pico_base + */ +enum pico_error_codes { + PICO_OK = 0, ///< No error; the operation succeeded + PICO_ERROR_NONE = 0, ///< No error; the operation succeeded + PICO_ERROR_GENERIC = -1, ///< An unspecified error occurred + PICO_ERROR_TIMEOUT = -2, ///< The function failed due to timeout + PICO_ERROR_NO_DATA = -3, ///< Attempt for example to read from an empty buffer/FIFO + PICO_ERROR_NOT_PERMITTED = -4, ///< Permission violation e.g. write to read-only flash partition, or security violation + PICO_ERROR_INVALID_ARG = -5, ///< Argument is outside of range of supported values` + PICO_ERROR_IO = -6, ///< An I/O error occurred + PICO_ERROR_BADAUTH = -7, ///< The authorization failed due to bad credentials + PICO_ERROR_CONNECT_FAILED = -8, ///< The connection failed + PICO_ERROR_INSUFFICIENT_RESOURCES = -9, ///< Dynamic allocation of resources failed + PICO_ERROR_INVALID_ADDRESS = -10, ///< Address argument was out-of-bounds or was determined to be an address that the caller may not access + PICO_ERROR_BAD_ALIGNMENT = -11, ///< Address was mis-aligned (usually not on word boundary) + PICO_ERROR_INVALID_STATE = -12, ///< Something happened or failed to happen in the past, and consequently we (currently) can't service the request + PICO_ERROR_BUFFER_TOO_SMALL = -13, ///< A user-allocated buffer was too small to hold the result or working state of this function + PICO_ERROR_PRECONDITION_NOT_MET = -14, ///< The call failed because another function must be called first + PICO_ERROR_MODIFIED_DATA = -15, ///< Cached data was determined to be inconsistent with the actual version of the data + PICO_ERROR_INVALID_DATA = -16, ///< A data structure failed to validate + PICO_ERROR_NOT_FOUND = -17, ///< Attempted to access something that does not exist; or, a search failed + PICO_ERROR_UNSUPPORTED_MODIFICATION = -18, ///< Write is impossible based on previous writes; e.g. attempted to clear an OTP bit + PICO_ERROR_LOCK_REQUIRED = -19, ///< A required lock is not owned + PICO_ERROR_VERSION_MISMATCH = -20, ///< A version mismatch occurred (e.g. trying to run PIO version 1 code on RP2040) + PICO_ERROR_RESOURCE_IN_USE = -21 ///< The call could not proceed because requires resourcesw were unavailable +}; + +#endif // !__ASSEMBLER__ + +#endif \ No newline at end of file diff --git a/src/common/pico_base/include/pico/types.h b/src/common/pico_base_headers/include/pico/types.h similarity index 76% rename from src/common/pico_base/include/pico/types.h rename to src/common/pico_base_headers/include/pico/types.h index 7dbb0b9f2..2e9c39642 100644 --- a/src/common/pico_base/include/pico/types.h +++ b/src/common/pico_base_headers/include/pico/types.h @@ -17,22 +17,30 @@ typedef unsigned int uint; +// PICO_CONFIG: PICO_OPAQUE_ABSOLUTE_TIME_T, Enable opaque type for absolute_time_t to help catch inadvertent confusing uint64_t delays with absolute times, default=0, advanced=true, group=pico_base +#ifndef PICO_OPAQUE_ABSOLUTE_TIME_T +#define PICO_OPAQUE_ABSOLUTE_TIME_T 0 +#endif + /*! \typedef absolute_time_t \brief An opaque 64 bit timestamp in microseconds The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong - time units where an absolute time is required. It is equivalent to uint64_t in release builds. + time units where an absolute time is required. + + note: As of SDK 2.0.0 this type defaults to being a uin64_t (i.e. no protection); it is enabled + by setting PICO_OPAQUE_ABSOLUTE_TIME_T to 1 \see to_us_since_boot() \see update_us_since_boot() \ingroup timestamp */ -#ifdef NDEBUG -typedef uint64_t absolute_time_t; -#else +#if PICO_OPAQUE_ABSOLUTE_TIME_T typedef struct { uint64_t _private_us_since_boot; } absolute_time_t; +#else +typedef uint64_t absolute_time_t; #endif /*! fn to_us_since_boot @@ -42,10 +50,10 @@ typedef struct { * \ingroup timestamp */ static inline uint64_t to_us_since_boot(absolute_time_t t) { -#ifdef NDEBUG - return t; -#else +#ifdef PICO_DEBUG_ABSOLUTE_TIME_T return t._private_us_since_boot; +#else + return t; #endif } @@ -57,11 +65,11 @@ static inline uint64_t to_us_since_boot(absolute_time_t t) { * \ingroup timestamp */ static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) { -#ifdef NDEBUG - *t = us_since_boot; -#else +#ifdef PICO_DEBUG_ABSOLUTE_TIME_T assert(us_since_boot <= INT64_MAX); t->_private_us_since_boot = us_since_boot; +#else + *t = us_since_boot; #endif } @@ -83,6 +91,12 @@ static inline absolute_time_t from_us_since_boot(uint64_t us_since_boot) { #define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value} #endif +// PICO_CONFIG: PICO_INCLUDE_RTC_DATETIME, Whether to include the datetime_t type used with the RP2040 RTC hardware, default=1 on RP2040, group=util_datetime +#ifndef PICO_INCLUDE_RTC_DATETIME +#define PICO_INCLUDE_RTC_DATETIME PICO_RP2040 +#endif + +#if PICO_INCLUDE_RTC_DATETIME /** \struct datetime_t * \ingroup util_datetime * \brief Structure containing date and time information @@ -99,6 +113,7 @@ typedef struct { int8_t min; ///< 0..59 int8_t sec; ///< 0..59 } datetime_t; +#endif #define bool_to_bit(x) ((uint)!!(x)) diff --git a/src/common/pico_base/include/pico/version.h.in b/src/common/pico_base_headers/include/pico/version.h.in similarity index 100% rename from src/common/pico_base/include/pico/version.h.in rename to src/common/pico_base_headers/include/pico/version.h.in diff --git a/src/common/pico_binary_info/BUILD.bazel b/src/common/pico_binary_info/BUILD.bazel index c4fa71bed..fa660e70c 100644 --- a/src/common/pico_binary_info/BUILD.bazel +++ b/src/common/pico_binary_info/BUILD.bazel @@ -1,5 +1,16 @@ +load("//bazel/util:sdk_define.bzl", "pico_sdk_define") + package(default_visibility = ["//visibility:public"]) +pico_sdk_define( + name = "LIB_PICO_BINARY_INFO", + define_name = "LIB_PICO_BINARY_INFO", + from_flag = "//bazel/config:PICO_BINARY_INFO_ENABLED", +) + +# The actual sources and defines for pico_binary_info are provided +# in the //src/rp2_common/pico_standard_link package. + cc_library( name = "pico_binary_info", hdrs = [ @@ -10,7 +21,8 @@ cc_library( ], includes = ["include"], deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/common/pico_base:pico_platform", + ":LIB_PICO_BINARY_INFO", + "//src:pico_platform_internal", + "//src/common/pico_base_headers", ], ) diff --git a/src/common/pico_binary_info/CMakeLists.txt b/src/common/pico_binary_info/CMakeLists.txt index bcaad6f9e..d2bfd6914 100644 --- a/src/common/pico_binary_info/CMakeLists.txt +++ b/src/common/pico_binary_info/CMakeLists.txt @@ -1,11 +1,10 @@ add_library(pico_binary_info_headers INTERFACE) -target_include_directories(pico_binary_info_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_binary_info_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +add_library(pico_binary_info INTERFACE) if (COMMAND pico_add_platform_library) pico_add_platform_library(pico_binary_info) -else() - add_library(pico_binary_info INTERFACE) endif() target_link_libraries(pico_binary_info INTERFACE pico_binary_info_headers) diff --git a/src/common/pico_binary_info/binary_info.bzl b/src/common/pico_binary_info/binary_info.bzl index a07a2c6fe..dd74a902d 100644 --- a/src/common/pico_binary_info/binary_info.bzl +++ b/src/common/pico_binary_info/binary_info.bzl @@ -28,12 +28,12 @@ def custom_pico_binary_info(name = None, program_name = None, program_descriptio "@pico-sdk//bazel/constraint:pico_no_target_name_enabled": [], "//conditions:default": _build_target_name_defines, }), - srcs = ["@pico-sdk//src/rp2_common/pico_standard_link:binary_info_srcs"], + srcs = ["@pico-sdk//src/rp2_common/pico_standard_binary_info:binary_info_srcs"], deps = [ - "@pico-sdk//src/rp2_common/pico_standard_link:PICO_BAZEL_BUILD_TYPE", - "@pico-sdk//src/common/pico_base:version", + "@pico-sdk//src/rp2_common/pico_standard_binary_info:PICO_BAZEL_BUILD_TYPE", + "@pico-sdk//src/common/pico_base_headers:version", "@pico-sdk//src/common/pico_binary_info", - "@pico-sdk//src/rp2_common/boot_stage2:config", + "@pico-sdk//src/rp2_common:boot_stage2_config", ], alwayslink = True, ) diff --git a/src/common/pico_binary_info/include/pico/binary_info.h b/src/common/pico_binary_info/include/pico/binary_info.h index 58fb4c7b1..594e8f702 100644 --- a/src/common/pico_binary_info/include/pico/binary_info.h +++ b/src/common/pico_binary_info/include/pico/binary_info.h @@ -10,7 +10,7 @@ /** \file binary_info.h * \defgroup pico_binary_info pico_binary_info * - * \brief Binary info is intended for embedding machine readable information with the binary in FLASH. + * \brief Binary info is intended for embedding machine readable information with the binary in FLASH * * Example uses include: * @@ -22,6 +22,8 @@ #include "pico/binary_info/defs.h" #include "pico/binary_info/structure.h" + +// PICO_CONFIG: PICO_NO_BINARY_INFO, Don't include "binary info" in the output binary, type=bool, default=0 except for `PICO_PLATFORM` `host`, group=pico_runtime_init #if !PICO_ON_DEVICE && !defined(PICO_NO_BINARY_INFO) #define PICO_NO_BINARY_INFO 1 #endif diff --git a/src/common/pico_binary_info/include/pico/binary_info/code.h b/src/common/pico_binary_info/include/pico/binary_info/code.h index bd72edfee..bc2126f5f 100644 --- a/src/common/pico_binary_info/include/pico/binary_info/code.h +++ b/src/common/pico_binary_info/include/pico/binary_info/code.h @@ -71,6 +71,33 @@ .value = _value, \ } +#define __bi_ptr_int32_with_name(_tag, _id, _label, _value) \ + static const struct _binary_info_ptr_int32_with_name __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_PTR_INT32_WITH_NAME), \ + .tag = _tag, \ + },\ + .id = _id, \ + .value = &_value, \ + .label = _label, \ + } + +#define bi_ptr_int32(_tag, _id, _var, _default) __attribute__((section(".data"))) static int _var = _default; __bi_ptr_int32_with_name(_tag, _id, __STRING(_var), _var) + +#define __bi_ptr_string_with_name(_tag, _id, _label, _value, _len) \ + static const struct _binary_info_ptr_string_with_name __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_PTR_STRING_WITH_NAME), \ + .tag = _tag, \ + },\ + .id = _id, \ + .value = _value, \ + .label = _label, \ + .len = _len, \ + } + +#define bi_ptr_string(_tag, _id, _var, _default, _max_len) static char _var[_max_len] = _default; __bi_ptr_string_with_name(_tag, _id, __STRING(_var), _var, _max_len) + #define bi_block_device(_tag, _name, _address, _size, _extra, _flags) \ static const struct _binary_info_block_device __bi_lineno_var_name = { \ .core = { \ @@ -93,6 +120,15 @@ .pin_encoding = _encoding \ } +#define __bi_encoded_pins_64_with_func(_encoding) \ + static const struct _binary_info_pins64_with_func __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS64_WITH_FUNC), \ + .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ + },\ + .pin_encoding = _encoding \ + } + #define __bi_pins_with_name(_mask, _label) \ static const struct _binary_info_pins_with_name __bi_lineno_var_name = { \ .core = { \ @@ -103,6 +139,16 @@ .label = _label \ } +#define __bi_pins_64_with_name(_mask, _label) \ + static const struct _binary_info_pins64_with_name __bi_lineno_var_name = { \ + .core = { \ + .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS64_WITH_NAME), \ + .tag = BINARY_INFO_TAG_RASPBERRY_PI, \ + },\ + .pin_mask = _mask, \ + .label = _label \ + } + #define __bi_named_group(_parent_tag, _parent_id, _group_tag, _group_id, _label, _flags) \ static const struct _binary_info_named_group __bi_lineno_var_name = { \ .core = { \ @@ -128,6 +174,12 @@ static const struct _binary_info_named_group __bi_lineno_var_name = { \ #define bi_program_feature_group(tag, id, name) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, 0) #define bi_program_feature_group_with_flags(tag, id, name, flags) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, flags) + +#ifndef PICO_BINARY_INFO_USE_PINS_64 +#define PICO_BINARY_INFO_USE_PINS_64 (NUM_BANK0_GPIOS > 32) +#endif + +#if !PICO_BINARY_INFO_USE_PINS_64 #define bi_1pin_with_func(p0, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p0) << 12)) #define bi_2pins_with_func(p0, p1, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p1) << 17)) #define bi_3pins_with_func(p0, p1, p2, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p2) << 22)) @@ -138,9 +190,26 @@ static const struct _binary_info_named_group __bi_lineno_var_name = { \ #define bi_pin_mask_with_name(pmask, label) __bi_pins_with_name((pmask), (label)) // names are separated by | ... i.e. "name1|name2|name3" #define bi_pin_mask_with_names(pmask, label) __bi_pins_with_name((pmask), (label)) -#define bi_1pin_with_name(p0, name) bi_pin_mask_with_name(1u << (p0), name) -#define bi_2pins_with_names(p0, name0, p1, name1) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)), name0 "|" name1) -#define bi_3pins_with_names(p0, name0, p1, name1, p2, name2) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)), name0 "|" name1 "|" name2) -#define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)) | (1u << (p3)), name0 "|" name1 "|" name2 "|" name3) +#else +#define bi_1pin_with_func(p0, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p0) << 16)) +#define bi_2pins_with_func(p0, p1, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p1) << 24)) +#define bi_3pins_with_func(p0, p1, p2, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p2) << 32)) +#define bi_4pins_with_func(p0, p1, p2, p3, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p3) << 40)) +#define bi_5pins_with_func(p0, p1, p2, p3, p4, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p4) << 40) | ((uint64_t)(p4) << 48)) +#define bi_pin_range_with_func(plo, phi, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_RANGE | ((func << 3)) | ((plo) << 8) | ((phi) << 16)) + +#define bi_pin_mask_with_name(pmask, label) __bi_pins_64_with_name((uint64_t)(pmask), (label)) +// names are separated by | ... i.e. "name1|name2|name3" +#define bi_pin_mask_with_names(pmask, label) __bi_pins_64_with_name((uint64_t)(pmask), (label)) +#endif + +// 6 and 7 pins require pins_64 +#define bi_6pins_with_func(p0, p1, p2, p3, p4, p5, func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p4) << 40) | ((uint64_t)(p5) << 48) | ((uint64_t)(p5) << 56)) +#define bi_7pins_with_func(p0, p1, p2, p3, p4, p5, p6,func) __bi_encoded_pins_64_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 8) | ((p1) << 16) | ((p2) << 24) | ((uint64_t)(p3) << 32) | ((uint64_t)(p4) << 40) | ((uint64_t)(p5) << 48) | ((uint64_t)(p6) << 56)) + +#define bi_1pin_with_name(p0, name) bi_pin_mask_with_name(1ull << (p0), name) +#define bi_2pins_with_names(p0, name0, p1, name1) bi_pin_mask_with_names((1ull << (p0)) | (1ull << (p1)), name0 "|" name1) +#define bi_3pins_with_names(p0, name0, p1, name1, p2, name2) bi_pin_mask_with_names((1ull << (p0)) | (1ull << (p1)) | (1ull << (p2)), name0 "|" name1 "|" name2) +#define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3) bi_pin_mask_with_names((1ull << (p0)) | (1ull << (p1)) | (1ull << (p2)) | (1ull << (p3)), name0 "|" name1 "|" name2 "|" name3) #endif diff --git a/src/common/pico_binary_info/include/pico/binary_info/structure.h b/src/common/pico_binary_info/include/pico/binary_info/structure.h index 480804872..1cda5a9bb 100644 --- a/src/common/pico_binary_info/include/pico/binary_info/structure.h +++ b/src/common/pico_binary_info/include/pico/binary_info/structure.h @@ -33,8 +33,11 @@ typedef struct _binary_info_core binary_info_t; #define BINARY_INFO_TYPE_BLOCK_DEVICE 7 #define BINARY_INFO_TYPE_PINS_WITH_FUNC 8 #define BINARY_INFO_TYPE_PINS_WITH_NAME 9 -#define BINARY_INFO_TYPE_PINS_WITH_NAMES 9 #define BINARY_INFO_TYPE_NAMED_GROUP 10 +#define BINARY_INFO_TYPE_PTR_INT32_WITH_NAME 11 +#define BINARY_INFO_TYPE_PTR_STRING_WITH_NAME 12 +#define BINARY_INFO_TYPE_PINS64_WITH_FUNC 13 +#define BINARY_INFO_TYPE_PINS64_WITH_NAME 14 // note plan is to reserve c1 = 0->31 for "collision tags"; i.e. // for which you should always use random IDs with the binary_info, @@ -94,6 +97,21 @@ typedef struct __packed _binary_info_id_and_string { bi_ptr_of(const char) value; } binary_info_id_and_string_t; +typedef struct __packed _binary_info_ptr_int32_with_name { + struct _binary_info_core core; + int32_t id; + bi_ptr_of(const int) value; + bi_ptr_of(const char) label; +} binary_info_ptr_int32_with_name_t; + +typedef struct __packed _binary_info_ptr_string_with_name { + struct _binary_info_core core; + int32_t id; + bi_ptr_of(const char) value; + bi_ptr_of(const char) label; + uint32_t len; +} binary_info_ptr_string_with_name_t; + typedef struct __packed _binary_info_block_device { struct _binary_info_core core; bi_ptr_of(const char) name; // optional static name (independent of what is formatted) @@ -113,12 +131,25 @@ typedef struct __packed _binary_info_pins_with_func { uint32_t pin_encoding; } binary_info_pins_with_func_t; +typedef struct __packed _binary_info_pins64_with_func { + struct _binary_info_core core; + // p6_8 : p5_8 : p4_8 : p3_8 : p2_8 : p1_8 : p0_8 : func_5 : 010_3 //individual pins p0,p1,p2 ... if fewer than 7 then duplicate p + // phi_8 : plo_8 : func_5 : 001_3 // pin range plo-phi inclusive + uint64_t pin_encoding; +} binary_info_pins64_with_func_t; + typedef struct __packed _binary_info_pins_with_name { struct _binary_info_core core; uint32_t pin_mask; bi_ptr_of(const char) label; } binary_info_pins_with_name_t; +typedef struct __packed _binary_info_pins64_with_name { + struct _binary_info_core core; + uint64_t pin_mask; + bi_ptr_of(const char) label; +} binary_info_pins64_with_name_t; + #define BI_NAMED_GROUP_SHOW_IF_EMPTY 0x0001 // default is to hide #define BI_NAMED_GROUP_SEPARATE_COMMAS 0x0002 // default is newlines #define BI_NAMED_GROUP_SORT_ALPHA 0x0004 // default is no sort @@ -134,8 +165,7 @@ typedef struct __packed _binary_info_named_group { } binary_info_named_group_t; enum { - BINARY_INFO_BLOCK_DEV_FLAG_READ = - 1 << 0, // if not readable, then it is basically hidden, but tools may choose to avoid overwriting it + BINARY_INFO_BLOCK_DEV_FLAG_READ = 1 << 0, // if not readable, then it is basically hidden, but tools may choose to avoid overwriting it BINARY_INFO_BLOCK_DEV_FLAG_WRITE = 1 << 1, BINARY_INFO_BLOCK_DEV_FLAG_REFORMAT = 1 << 2, // may be reformatted.. diff --git a/src/common/pico_bit_ops/BUILD.bazel b/src/common/pico_bit_ops_headers/BUILD.bazel similarity index 85% rename from src/common/pico_bit_ops/BUILD.bazel rename to src/common/pico_bit_ops_headers/BUILD.bazel index 0d55f1e92..5e6eca224 100644 --- a/src/common/pico_bit_ops/BUILD.bazel +++ b/src/common/pico_bit_ops_headers/BUILD.bazel @@ -4,7 +4,7 @@ package(default_visibility = ["//visibility:public"]) # this library and the bit ops implementations. # Application code should always use :pico_bit_ops instead. cc_library( - name = "pico_bit_ops_headers", + name = "pico_bit_ops_interface", hdrs = ["include/pico/bit_ops.h"], includes = ["include"], visibility = [ @@ -12,16 +12,16 @@ cc_library( "//src/rp2_common/pico_bit_ops:__pkg__", ], deps = [ - "//src/common/pico_base", + "//src/common/pico_base_headers", ], ) cc_library( - name = "pico_bit_ops", + name = "pico_bit_ops_headers", hdrs = ["include/pico/bit_ops.h"], includes = ["include"], deps = [ - "//src/common/pico_base", + "//src/common/pico_base_headers", ] + select({ "//bazel/constraint:host": ["//src/host/pico_bit_ops"], "//conditions:default": ["//src/rp2_common/pico_bit_ops"], diff --git a/src/common/pico_bit_ops/CMakeLists.txt b/src/common/pico_bit_ops_headers/CMakeLists.txt similarity index 61% rename from src/common/pico_bit_ops/CMakeLists.txt rename to src/common/pico_bit_ops_headers/CMakeLists.txt index 603a52060..ff2e90006 100644 --- a/src/common/pico_bit_ops/CMakeLists.txt +++ b/src/common/pico_bit_ops_headers/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_bit_ops_headers) add_library(pico_bit_ops_headers INTERFACE) - target_include_directories(pico_bit_ops_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_bit_ops_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(pico_bit_ops_headers INTERFACE pico_base_headers) endif() \ No newline at end of file diff --git a/src/common/pico_bit_ops/include/pico/bit_ops.h b/src/common/pico_bit_ops_headers/include/pico/bit_ops.h similarity index 94% rename from src/common/pico_bit_ops/include/pico/bit_ops.h rename to src/common/pico_bit_ops_headers/include/pico/bit_ops.h index d3a1dd5af..4324e5246 100644 --- a/src/common/pico_bit_ops/include/pico/bit_ops.h +++ b/src/common/pico_bit_ops_headers/include/pico/bit_ops.h @@ -16,7 +16,8 @@ extern "C" { /** \file bit_ops.h * \defgroup pico_bit_ops pico_bit_ops * -* \brief Optimized bit manipulation functions. +* \brief Optimized bit manipulation functions +* * Additionally provides replacement implementations of the compiler built-ins __builtin_popcount, __builtin_clz * and __bulitin_ctz */ diff --git a/src/common/pico_divider/BUILD.bazel b/src/common/pico_divider/BUILD.bazel deleted file mode 100644 index ed77bcc06..000000000 --- a/src/common/pico_divider/BUILD.bazel +++ /dev/null @@ -1,13 +0,0 @@ -package(default_visibility = ["//visibility:public"]) - -cc_library( - name = "pico_divider", - hdrs = ["include/pico/divider.h"], - includes = ["include"], - deps = [ - "//src/common/pico_base", - ] + select({ - "//bazel/constraint:host": ["//src/host/hardware_divider"], - "//conditions:default": ["//src/rp2_common/pico_divider"], - }), -) diff --git a/src/common/pico_divider_headers/BUILD.bazel b/src/common/pico_divider_headers/BUILD.bazel new file mode 100644 index 000000000..9d27f3558 --- /dev/null +++ b/src/common/pico_divider_headers/BUILD.bazel @@ -0,0 +1,10 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_divider_headers", + hdrs = ["include/pico/divider.h"], + includes = ["include"], + deps = [ + "//src/common/pico_base_headers", + ], +) diff --git a/src/common/pico_divider/CMakeLists.txt b/src/common/pico_divider_headers/CMakeLists.txt similarity index 52% rename from src/common/pico_divider/CMakeLists.txt rename to src/common/pico_divider_headers/CMakeLists.txt index aed07d292..39195788a 100644 --- a/src/common/pico_divider/CMakeLists.txt +++ b/src/common/pico_divider_headers/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_divider_headers) add_library(pico_divider_headers INTERFACE) - target_include_directories(pico_divider_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) - target_link_libraries(pico_divider_headers INTERFACE pico_base_headers) + target_include_directories(pico_divider_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_link_libraries(pico_divider_headers INTERFACE pico_base_headers hardware_divider_headers) endif() \ No newline at end of file diff --git a/src/common/pico_divider/include/pico/divider.h b/src/common/pico_divider_headers/include/pico/divider.h similarity index 98% rename from src/common/pico_divider/include/pico/divider.h rename to src/common/pico_divider_headers/include/pico/divider.h index 574ad38fa..45c448db8 100644 --- a/src/common/pico_divider/include/pico/divider.h +++ b/src/common/pico_divider_headers/include/pico/divider.h @@ -16,7 +16,8 @@ extern "C" { /** * \defgroup pico_divider pico_divider - * \brief Optimized 32 and 64 bit division functions accelerated by the RP2040 hardware divider. + * \brief Optimized 32 and 64 bit division functions accelerated by the RP2040 hardware divider + * * Additionally provides integration with the C `/` and `%` operators */ @@ -203,7 +204,7 @@ int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem); * * Do not use in interrupts */ -int64_t divmod_s32s32_unsafe(int32_t a, int32_t b); +divmod_result_t divmod_s32s32_unsafe(int32_t a, int32_t b); /** * \brief Unsafe integer divide of two unsigned 32-bit values @@ -240,7 +241,7 @@ uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem); * * Do not use in interrupts */ -uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b); +divmod_result_t divmod_u32u32_unsafe(uint32_t a, uint32_t b); /** * \brief Unsafe integer divide of two signed 64-bit values diff --git a/src/common/pico_stdlib/BUILD.bazel b/src/common/pico_stdlib/BUILD.bazel deleted file mode 100644 index a332e1ff4..000000000 --- a/src/common/pico_stdlib/BUILD.bazel +++ /dev/null @@ -1,51 +0,0 @@ -package(default_visibility = ["//visibility:public"]) - -# This exists to break a header dependency cycle from rp2_common/pico_stdlib. -# Do not directly depend on this. -cc_library( - name = "pico_stdlib_interface", - hdrs = ["include/pico/stdlib.h"], - includes = ["include"], - visibility = [ - "//src/host/pico_stdio:__pkg__", - "//src/host/pico_stdlib:__pkg__", - "//src/rp2_common/pico_stdlib:__pkg__", - "//src/rp2_common/tinyusb:__pkg__", - ], - deps = [ - "//src/common/pico_base", - "//src/common/pico_time", - ] + select({ - "//bazel/constraint:host": [ - "//src/host/hardware_gpio", - "//src/host/hardware_uart", - ], - "//conditions:default": [ - "//src/rp2_common/hardware_gpio", - "//src/rp2_common/hardware_uart", - ], - }), -) - -cc_library( - name = "pico_stdlib", - hdrs = ["include/pico/stdlib.h"], - includes = ["include"], - deps = [ - "//src/common/pico_base", - "//src/common/pico_time", - ] + select({ - "//bazel/constraint:host": [ - "//src/host/hardware_gpio", - "//src/host/hardware_uart", - "//src/host/pico_stdio", - "//src/host/pico_stdlib", - ], - "//conditions:default": [ - "//src/rp2_common/hardware_gpio", - "//src/rp2_common/hardware_uart", - "//src/rp2_common/pico_stdio", - "//src/rp2_common/pico_stdlib", - ], - }), -) diff --git a/src/common/pico_stdlib_headers/BUILD.bazel b/src/common/pico_stdlib_headers/BUILD.bazel new file mode 100644 index 000000000..e20a65603 --- /dev/null +++ b/src/common/pico_stdlib_headers/BUILD.bazel @@ -0,0 +1,16 @@ +package(default_visibility = ["//visibility:public"]) + +# Use //host/pico_stdlib or //rp2_common/pico_stdlib to get the +# implementation of this header, along with other critical defines headers. +cc_library( + name = "pico_stdlib_headers", + hdrs = ["include/pico/stdlib.h"], + includes = ["include"], + visibility = [ + "//src/host/pico_stdio:__pkg__", + "//src/host/pico_stdlib:__pkg__", + "//src/rp2_common/pico_stdio:__pkg__", + "//src/rp2_common/pico_stdlib:__pkg__", + "//src/rp2_common/tinyusb:__pkg__", + ], +) diff --git a/src/common/pico_stdlib/CMakeLists.txt b/src/common/pico_stdlib_headers/CMakeLists.txt similarity index 62% rename from src/common/pico_stdlib/CMakeLists.txt rename to src/common/pico_stdlib_headers/CMakeLists.txt index 7523d084c..a93257ca1 100644 --- a/src/common/pico_stdlib/CMakeLists.txt +++ b/src/common/pico_stdlib_headers/CMakeLists.txt @@ -1,5 +1,5 @@ if (NOT TARGET pico_stdlib_headers) add_library(pico_stdlib_headers INTERFACE) - target_include_directories(pico_stdlib_headers INTERFACE include) + target_include_directories(pico_stdlib_headers SYSTEM INTERFACE include) # dependencies handled in implementation CMakeLists.txt -endif() \ No newline at end of file +endif() diff --git a/src/common/pico_stdlib/include/pico/stdlib.h b/src/common/pico_stdlib_headers/include/pico/stdlib.h similarity index 51% rename from src/common/pico_stdlib/include/pico/stdlib.h rename to src/common/pico_stdlib_headers/include/pico/stdlib.h index 1de172ae1..811f565c9 100644 --- a/src/common/pico_stdlib/include/pico/stdlib.h +++ b/src/common/pico_stdlib_headers/include/pico/stdlib.h @@ -21,18 +21,19 @@ extern "C" { * \defgroup pico_stdlib pico_stdlib * * \brief Aggregation of a core subset of Raspberry Pi Pico SDK libraries used by most executables along with some additional - * utility methods. Including pico_stdlib gives you everything you need to get a basic program running + * utility methods + * + * Including pico_stdlib gives you everything you need to get a basic program running * which prints to stdout or flashes a LED * * This library aggregates: - * - @ref hardware_uart + * - @ref hardware_divider * - @ref hardware_gpio - * - @ref pico_binary_info + * - @ref hardware_uart * - @ref pico_runtime * - @ref pico_platform - * - @ref pico_printf * - @ref pico_stdio - * - @ref pico_standard_link + * - @ref pico_time * - @ref pico_util * * There are some basic default values used by these functions that will default to @@ -56,7 +57,7 @@ extern "C" { #include "pico/stdio_semihosting.h" #endif -// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, group=pico_stdlib +// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, default=Usually provided via board header, group=pico_stdlib // PICO_CONFIG: PICO_DEFAULT_LED_PIN_INVERTED, 1 if LED is inverted or 0 if not, type=int, default=0, group=pico_stdlib #ifndef PICO_DEFAULT_LED_PIN_INVERTED @@ -83,57 +84,6 @@ extern "C" { */ void setup_default_uart(void); -/*! \brief Initialise the system clock to 48MHz - * \ingroup pico_stdlib - * - * Set the system clock to 48MHz, and set the peripheral clock to match. - */ -void set_sys_clock_48mhz(void); - -/*! \brief Initialise the system clock - * \ingroup pico_stdlib - * - * \param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL - * \param post_div1 The first post divider for the SYS PLL - * \param post_div2 The second post divider for the SYS PLL. - * - * See the PLL documentation in the datasheet for details of driving the PLLs. - */ -void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2); - -/*! \brief Check if a given system clock frequency is valid/attainable - * \ingroup pico_stdlib - * - * \param freq_khz Requested frequency - * \param vco_freq_out On success, the voltage controlled oscillator frequency to be used by the SYS PLL - * \param post_div1_out On success, The first post divider for the SYS PLL - * \param post_div2_out On success, The second post divider for the SYS PLL. - * @return true if the frequency is possible and the output parameters have been written. - */ -bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out); - -/*! \brief Attempt to set a system clock frequency in khz - * \ingroup pico_stdlib - * - * Note that not all clock frequencies are possible; it is preferred that you - * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters - * for use with set_sys_clock_pll - * - * \param freq_khz Requested frequency - * \param required if true then this function will assert if the frequency is not attainable. - * \return true if the clock was configured - */ -static inline bool set_sys_clock_khz(uint32_t freq_khz, bool required) { - uint vco, postdiv1, postdiv2; - if (check_sys_clock_khz(freq_khz, &vco, &postdiv1, &postdiv2)) { - set_sys_clock_pll(vco, postdiv1, postdiv2); - return true; - } else if (required) { - panic("System clock of %u kHz cannot be exactly achieved", freq_khz); - } - return false; -} - #ifdef __cplusplus } #endif diff --git a/src/common/pico_sync/BUILD.bazel b/src/common/pico_sync/BUILD.bazel index 53c56b4c3..4b65e8921 100644 --- a/src/common/pico_sync/BUILD.bazel +++ b/src/common/pico_sync/BUILD.bazel @@ -1,13 +1,9 @@ +load("@pico-sdk//bazel:defs.bzl", "incompatible_with_config") + package(default_visibility = ["//visibility:public"]) cc_library( - name = "pico_sync", - srcs = [ - "critical_section.c", - "lock_core.c", - "mutex.c", - "sem.c", - ], + name = "pico_sync_headers", hdrs = [ "include/pico/critical_section.h", "include/pico/lock_core.h", @@ -16,15 +12,35 @@ cc_library( "include/pico/sync.h", ], includes = ["include"], + visibility = [ + "//src/rp2_common/hardware_sync:__pkg__", + "//src/rp2_common/hardware_sync_spin_lock:__pkg__", + ], +) + +cc_library( + name = "pico_sync", + srcs = [ + "critical_section.c", + "lock_core.c", + "mutex.c", + "sem.c", + ], + # valid_params_if() uses Statement Expressions, which aren't supported in MSVC. + target_compatible_with = incompatible_with_config("@rules_cc//cc/compiler:msvc-cl"), deps = [ - "//src/common/pico_base:pico_base_interface", + ":pico_sync_headers", + "//src/common/pico_base_headers", "//src/common/pico_time:pico_time_headers", ] + select({ "//bazel/constraint:host": [ "//src/host/hardware_sync", + "//src/host/pico_runtime", ], "//conditions:default": [ "//src/rp2_common/hardware_sync", + "//src/rp2_common/hardware_sync_spin_lock", + "//src/rp2_common/pico_runtime_init", ], }), ) diff --git a/src/common/pico_sync/CMakeLists.txt b/src/common/pico_sync/CMakeLists.txt index 05b969cd0..07e9291e2 100644 --- a/src/common/pico_sync/CMakeLists.txt +++ b/src/common/pico_sync/CMakeLists.txt @@ -7,7 +7,7 @@ endif() if (NOT TARGET pico_sync) pico_add_impl_library(pico_sync) - target_include_directories(pico_sync_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_sync_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_sync INTERFACE pico_sync_sem pico_sync_mutex pico_sync_critical_section pico_time hardware_sync) endif() diff --git a/src/common/pico_sync/critical_section.c b/src/common/pico_sync/critical_section.c index 7cbb6227d..d51bf76f2 100644 --- a/src/common/pico_sync/critical_section.c +++ b/src/common/pico_sync/critical_section.c @@ -6,7 +6,7 @@ #include "pico/critical_section.h" -#if !PICO_NO_HARDWARE +#if PICO_32BIT static_assert(sizeof(critical_section_t) == 8, ""); #endif diff --git a/src/common/pico_sync/include/pico/lock_core.h b/src/common/pico_sync/include/pico/lock_core.h index fbfa7cbce..babd28595 100644 --- a/src/common/pico_sync/include/pico/lock_core.h +++ b/src/common/pico_sync/include/pico/lock_core.h @@ -14,7 +14,7 @@ /** \file lock_core.h * \defgroup lock_core lock_core * \ingroup pico_sync - * \brief base synchronization/lock primitive support + * \brief base synchronization/lock primitive support. * * Most of the pico_sync locking primitives contain a lock_core_t structure member. This currently just holds a spin * lock which is used only to protect the contents of the rest of the structure as part of implementing the synchronization @@ -34,7 +34,7 @@ * and those that notify, to wake a blocked task which isn't on processor. At least the wait macro implementation needs to be atomic with the protecting * spin_lock unlock from the callers point of view; i.e. the task should unlock the spin lock when it starts its wait. Such implementation is * up to the RTOS integration, however the macros are defined such that such operations are always combined into a single call - * (so they can be perfomed atomically) even though the default implementation does not need this, as a WFE which starts + * (so they can be performed atomically) even though the default implementation does not need this, as a WFE which starts * following the corresponding SEV is not missed. */ diff --git a/src/common/pico_sync/include/pico/mutex.h b/src/common/pico_sync/include/pico/mutex.h index 75fa1ef5a..32eb7a079 100644 --- a/src/common/pico_sync/include/pico/mutex.h +++ b/src/common/pico_sync/include/pico/mutex.h @@ -44,7 +44,7 @@ extern "C" { /*! \brief recursive mutex instance * \ingroup mutex */ -typedef struct __packed_aligned { +typedef struct { lock_core_t core; lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned uint8_t enter_count; //! ownership count @@ -57,7 +57,7 @@ typedef struct __packed_aligned { * \ingroup mutex */ #if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY -typedef struct __packed_aligned mutex { +typedef struct mutex { lock_core_t core; lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned } mutex_t; @@ -305,6 +305,8 @@ static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) { */ #define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core = { .spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }, .owner = 0, .enter_count = 0 } +void runtime_init_mutex(void); + #ifdef __cplusplus } #endif diff --git a/src/common/pico_sync/include/pico/sem.h b/src/common/pico_sync/include/pico/sem.h index 9bb573123..832f1499b 100644 --- a/src/common/pico_sync/include/pico/sem.h +++ b/src/common/pico_sync/include/pico/sem.h @@ -28,7 +28,7 @@ #ifdef __cplusplus extern "C" { #endif -typedef struct __packed_aligned semaphore { +typedef struct semaphore { struct lock_core core; int16_t permits; int16_t max_permits; diff --git a/src/common/pico_sync/mutex.c b/src/common/pico_sync/mutex.c index 828be68c9..66e947687 100644 --- a/src/common/pico_sync/mutex.c +++ b/src/common/pico_sync/mutex.c @@ -6,6 +6,39 @@ #include "pico/mutex.h" #include "pico/time.h" +#include "pico/runtime_init.h" + +#if !PICO_RUNTIME_NO_INIT_MUTEX +void __weak runtime_init_mutex(void) { + // this is an array of either mutex_t or recursive_mutex_t (i.e. not necessarily the same size) + // however each starts with a lock_core_t, and the spin_lock is initialized to address 1 for a recursive + // spinlock and 0 for a regular one. + + static_assert(!(sizeof(mutex_t)&3), ""); + static_assert(!(sizeof(recursive_mutex_t)&3), ""); + static_assert(!offsetof(mutex_t, core), ""); + static_assert(!offsetof(recursive_mutex_t, core), ""); + extern lock_core_t __mutex_array_start; + extern lock_core_t __mutex_array_end; + + for (lock_core_t *l = &__mutex_array_start; l < &__mutex_array_end; ) { + if (l->spin_lock) { + assert(1 == (uintptr_t)l->spin_lock); // indicator for a recursive mutex + recursive_mutex_t *rm = (recursive_mutex_t *)l; + recursive_mutex_init(rm); + l = &rm[1].core; // next + } else { + mutex_t *m = (mutex_t *)l; + mutex_init(m); + l = &m[1].core; // next + } + } +} +#endif + +#if defined(PICO_RUNTIME_INIT_MUTEX) && !PICO_RUNTIME_SKIP_INIT_MUTEX +PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_mutex, PICO_RUNTIME_INIT_MUTEX); +#endif void mutex_init(mutex_t *mtx) { lock_init(&mtx->core, next_striped_spin_lock_num()); diff --git a/src/common/pico_time/BUILD.bazel b/src/common/pico_time/BUILD.bazel index b429dc5a6..acf877488 100644 --- a/src/common/pico_time/BUILD.bazel +++ b/src/common/pico_time/BUILD.bazel @@ -1,3 +1,5 @@ +load("@pico-sdk//bazel:defs.bzl", "incompatible_with_config") + package(default_visibility = ["//visibility:public"]) # This exists to break a dependency cycle between @@ -10,8 +12,11 @@ cc_library( "include/pico/timeout_helper.h", ], includes = ["include"], + # invalid_params_if() uses Statement Expressions, which aren't supported in MSVC. + target_compatible_with = incompatible_with_config("@rules_cc//cc/compiler:msvc-cl"), visibility = [ "//src/common/pico_sync:__pkg__", + "//src/host/pico_time_adapter:__pkg__", "//src/rp2_common/tinyusb:__pkg__", ], deps = select({ @@ -34,17 +39,29 @@ cc_library( "include/pico/time.h", "include/pico/timeout_helper.h", ], + # macOS defines __weak as part of Xcode, and the semantics are unfortunately + # different. + copts = select({ + "@platforms//os:macos": ["-Wno-ignored-attributes"], + "//conditions:default": [], + }), includes = ["include"], deps = [ - "//src/common/pico_base:pico_base_interface", + "//src/common/pico_base_headers", "//src/common/pico_sync", "//src/common/pico_util", ] + select({ "//bazel/constraint:host": [ + "//src/host/hardware_gpio", "//src/host/hardware_timer", + "//src/host/pico_runtime", + "//src/host/pico_time_adapter", ], "//conditions:default": [ + "//src/rp2_common/hardware_gpio", "//src/rp2_common/hardware_timer", + "//src/rp2_common/pico_runtime_init", + "//src/rp2_common/pico_time_adapter", ], }), ) diff --git a/src/common/pico_time/CMakeLists.txt b/src/common/pico_time/CMakeLists.txt index 658b6b451..9cbe5dcc0 100644 --- a/src/common/pico_time/CMakeLists.txt +++ b/src/common/pico_time/CMakeLists.txt @@ -1,6 +1,6 @@ if (NOT TARGET pico_time_headers) add_library(pico_time_headers INTERFACE) - target_include_directories(pico_time_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_time_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(pico_time_headers INTERFACE hardware_timer_headers pico_sync_headers pico_util_headers) endif() diff --git a/src/common/pico_time/include/pico/time.h b/src/common/pico_time/include/pico/time.h index 050cdcc38..699523e9e 100644 --- a/src/common/pico_time/include/pico/time.h +++ b/src/common/pico_time/include/pico/time.h @@ -29,19 +29,24 @@ extern "C" { * \sa \ref hardware_timer */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIME, Enable/disable assertions in the time module, type=bool, default=0, group=pico_time -#ifndef PARAM_ASSERTIONS_ENABLED_TIME -#define PARAM_ASSERTIONS_ENABLED_TIME 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PICO_TIME, Enable/disable assertions in the pico_time module, type=bool, default=0, group=pico_time +#ifndef PARAM_ASSERTIONS_ENABLED_PICO_TIME +#ifdef PARAM_ASSERTIONS_ENABLED_PICO_TIME // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_PICO_TIME PARAM_ASSERTIONS_ENABLED_TIME +#else +#define PARAM_ASSERTIONS_ENABLED_PICO_TIME 0 +#endif #endif // PICO_CONFIG: PICO_TIME_SLEEP_OVERHEAD_ADJUST_US, How many microseconds to wake up early (and then busy_wait) to account for timer overhead when sleeping in low power mode, type=int, default=6, group=pico_time #ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 6 #endif + /*! * \defgroup timestamp timestamp * \ingroup pico_time - * \brief Timestamp functions relating to points in time (including the current time) + * \brief Timestamp functions relating to points in time (including the current time). * * These are functions for dealing with timestamps (i.e. instants in time) represented by the type absolute_time_t. This opaque * type is provided to help prevent accidental mixing of timestamps and relative time values. @@ -291,9 +296,9 @@ bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); * \brief Alarm functions for scheduling future execution * * Alarms are added to alarm pools, which may hold a certain fixed number of active alarms. Each alarm pool - * utilizes one of four underlying hardware alarms, thus you may have up to four alarm pools. An alarm pool + * utilizes one of four underlying timer_alarms, thus you may have up to four alarm pools. An alarm pool * calls (except when the callback would happen before or during being set) the callback on the core from which - * the alarm pool was created. Callbacks are called from the hardware alarm IRQ handler, so care must + * the alarm pool was created. Callbacks are called from the timer_alarm IRQ handler, so care must * be taken in their implementation. * * A default pool is created the core specified by PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM @@ -306,7 +311,7 @@ bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); // PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_DISABLED, Disable the default alarm pool, type=bool, default=0, advanced=true, group=pico_time #ifndef PICO_TIME_DEFAULT_ALARM_POOL_DISABLED /*! - * \brief If 1 then the default alarm pool is disabled (so no hardware alarm is claimed for the pool) + * \brief If 1 then the default alarm pool is disabled (so no timer_alarm is claimed for the pool) * * \note Setting to 1 may cause some code not to compile as default timer pool related methods are removed * @@ -323,7 +328,7 @@ bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); // PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, Select which HW alarm is used for the default alarm pool, min=0, max=3, default=3, advanced=true, group=pico_time #ifndef PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM /*! - * \brief Selects which hardware alarm is used for the default alarm pool + * \brief Selects which timer_alarm is used for the default alarm pool * \ingroup alarm * \sa alarm_pool_get_default() */ @@ -346,7 +351,7 @@ bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); /** * \brief The identifier for an alarm * - * \note this identifier is signed because -1 is used as an error condition when creating alarms + * \note this identifier is signed because <0 is used as an error condition when creating alarms * * \note alarm ids may be reused, however for convenience the implementation makes an attempt to defer * reusing as long as possible. You should certainly expect it to be hundreds of ids before one is @@ -354,9 +359,10 @@ bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp); * alarms or other functionality based on alarms when the alarm may have expired, as eventually * the alarm id may be reused for another alarm. * + * \see pico_error_codes * \ingroup alarm */ -typedef int32_t alarm_id_t; // note this is signed because we use -1 as a meaningful error value +typedef int32_t alarm_id_t; // note this is signed because we use <0 as a meaningful error value /** * \brief User alarm callback @@ -370,12 +376,14 @@ typedef int32_t alarm_id_t; // note this is signed because we use -1 as a meanin typedef int64_t (*alarm_callback_t)(alarm_id_t id, void *user_data); typedef struct alarm_pool alarm_pool_t; +typedef void alarm_pool_timer_t; /** * \brief Create the default alarm pool (if not already created or disabled) * \ingroup alarm */ void alarm_pool_init_default(void); +void runtime_init_default_alarm_pool(void); #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED /*! @@ -388,6 +396,12 @@ void alarm_pool_init_default(void); alarm_pool_t *alarm_pool_get_default(void); #endif +alarm_pool_t *alarm_pool_create_on_timer(alarm_pool_timer_t *timer, uint timer_alarm_num, uint max_timers); + +alarm_pool_timer_t *alarm_pool_timer_for_timer_num(uint timer_num); + +alarm_pool_timer_t *alarm_pool_get_default_timer(void); + /** * \brief Create an alarm pool * @@ -397,19 +411,23 @@ alarm_pool_t *alarm_pool_get_default(void); * might want to create another if you want alarm callbacks on core 1 or require alarm pools of * different priority (IRQ priority based preemption of callbacks) * - * \note This method will hard assert if the hardware alarm is already claimed. + * \note This method will hard assert if the timer_alarm is already claimed. * * \ingroup alarm - * \param hardware_alarm_num the hardware alarm to use to back this pool + * \param timer_alarm_num the timer_alarm to use to back this pool * \param max_timers the maximum number of timers * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255 * \sa alarm_pool_get_default() * \sa hardware_claiming */ -alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers); +static inline alarm_pool_t *alarm_pool_create(uint timer_alarm_num, uint max_timers) { + return alarm_pool_create_on_timer(alarm_pool_get_default_timer(), timer_alarm_num, max_timers); +} + +alarm_pool_t *alarm_pool_create_on_timer_with_unused_hardware_alarm(alarm_pool_timer_t *timer, uint max_timers); /** - * \brief Create an alarm pool, claiming an used hardware alarm to back it. + * \brief Create an alarm pool, claiming an used timer_alarm to back it. * * The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from. * @@ -425,16 +443,21 @@ alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers); * \sa alarm_pool_get_default() * \sa hardware_claiming */ -alarm_pool_t *alarm_pool_create_with_unused_hardware_alarm(uint max_timers); +static inline alarm_pool_t *alarm_pool_create_with_unused_hardware_alarm(uint max_timers) { + return alarm_pool_create_on_timer_with_unused_hardware_alarm(alarm_pool_get_default_timer(), max_timers); +} /** - * \brief Return the hardware alarm used by an alarm pool + * \brief Return the timer alarm used by an alarm pool * \ingroup alarm * \param pool the pool - * \return the hardware alarm used by the pool + * \return the timer_alarm used by the pool */ -uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool); - +uint alarm_pool_timer_alarm_num(alarm_pool_t *pool); +// backwards compatibility +static inline uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool) { + return alarm_pool_timer_alarm_num(pool); +} /** * \brief Return the core number the alarm pool was initialized on (and hence callbacks are called on) * \ingroup alarm @@ -444,7 +467,7 @@ uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool); uint alarm_pool_core_num(alarm_pool_t *pool); /** - * \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm + * \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying timer_alarm * \ingroup alarm * \param pool the pool */ @@ -461,17 +484,15 @@ void alarm_pool_destroy(alarm_pool_t *pool); * * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. * - * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback) + * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) * @param time the timestamp when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, * then the callback should be called during (by) this function instead * @return >0 the alarm id for an active (at the time of return) alarm - * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. - * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), - * or if the callback was called during this method but the callback cancelled itself by returning 0 - * @return -1 if there were no alarm slots available + * @return 0 if the alarm time passed before or during the call and fire_if_past was false + * @return <0 if there were no alarm slots available, or other error occurred */ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past); @@ -485,12 +506,12 @@ alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, ala * * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. * - * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback) + * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) * @param time the timestamp when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function * @return >0 the alarm id for an active (at the time of return) alarm - * @return -1 if there were no alarm slots available + * @return <0 if there were no alarm slots available, or other error occurred */ alarm_id_t alarm_pool_add_alarm_at_force_in_context(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data); @@ -505,17 +526,15 @@ alarm_id_t alarm_pool_add_alarm_at_force_in_context(alarm_pool_t *pool, absolute * * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. * - * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback) + * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) * @param us the delay (from now) in microseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. - * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), - * or if the callback was called during this method but the callback cancelled itself by returning 0 - * @return -1 if there were no alarm slots available + * @return 0 if the alarm time passed before or during the call and fire_if_past was false + * @return <0 if there were no alarm slots available, or other error occurred */ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { return alarm_pool_add_alarm_at(pool, delayed_by_us(get_absolute_time(), us), callback, user_data, fire_if_past); @@ -532,22 +551,44 @@ static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t * * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. * - * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback) + * @param pool the alarm pool to use for scheduling the callback (this determines which timer_alarm is used, and which core calls the callback) * @param ms the delay (from now) in milliseconds when (after which) the callback should fire * @param callback the callback function * @param user_data user data to pass to the callback function * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. - * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), - * or if the callback was called during this method but the callback cancelled itself by returning 0 - * @return -1 if there were no alarm slots available + * @return 0 if the alarm time passed before or during the call and fire_if_past was false + * @return <0 if there were no alarm slots available, or other error occurred */ static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { return alarm_pool_add_alarm_at(pool, delayed_by_ms(get_absolute_time(), ms), callback, user_data, fire_if_past); } +/*! + * \brief Return the time remaining before the next trigger of an alarm + * \ingroup alarm + * + * @param pool the alarm_pool containing the alarm + * @param alarm_id the alarm + * + * @return >=0 the number of microseconds before the next trigger + * @return <0 if either the given alarm is not in progress or it has passed + */ +int64_t alarm_pool_remaining_alarm_time_us(alarm_pool_t *pool, alarm_id_t alarm_id); + +/*! + * \brief Return the time remaining before the next trigger of an alarm + * \ingroup alarm + * + * @param pool the alarm_pool containing the alarm + * @param alarm_id the alarm + * + * @return >=0 the number of microseconds before the next trigger (INT32_MAX if the number of ms is higher than can be represented0 + * @return <0 if either the given alarm is not in progress or it has passed + */ +int32_t alarm_pool_remaining_alarm_time_ms(alarm_pool_t *pool, alarm_id_t alarm_id); + /*! * \brief Cancel an alarm * \ingroup alarm @@ -576,10 +617,8 @@ bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id); * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set, * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. - * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), - * or if the callback was called during this method but the callback cancelled itself by returning 0 - * @return -1 if there were no alarm slots available + * @return 0 if the alarm time passed before or during the call and fire_if_past was false + * @return <0 if there were no alarm slots available, or other error occurred */ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) { return alarm_pool_add_alarm_at(alarm_pool_get_default(), time, callback, user_data, fire_if_past); @@ -602,10 +641,8 @@ static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t cal * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. - * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), - * or if the callback was called during this method but the callback cancelled itself by returning 0 - * @return -1 if there were no alarm slots available + * @return 0 if the alarm time passed before or during the call and fire_if_past was false + * @return <0 if there were no alarm slots available, or other error occurred */ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) { return alarm_pool_add_alarm_in_us(alarm_pool_get_default(), us, callback, user_data, fire_if_past); @@ -628,10 +665,8 @@ static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set, * then the callback should be called during (by) this function instead * @return >0 the alarm id - * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of. - * The latter can either happen because fire_if_past was false (i.e. no timer was ever created), - * or if the callback was called during this method but the callback cancelled itself by returning 0 - * @return -1 if there were no alarm slots available + * @return 0 if the alarm time passed before or during the call and fire_if_past was false + * @return <0 if there were no alarm slots available, or other error occurred */ static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) { return alarm_pool_add_alarm_in_ms(alarm_pool_get_default(), ms, callback, user_data, fire_if_past); @@ -647,6 +682,29 @@ static inline bool cancel_alarm(alarm_id_t alarm_id) { return alarm_pool_cancel_alarm(alarm_pool_get_default(), alarm_id); } +/*! + * \brief Return the time remaining before the next trigger of an alarm + * \ingroup alarm + * + * @param pool the alarm_pool containing the alarm + * @param alarm_id the alarm + * + * @return >=0 the number of microseconds before the next trigger + * @return <0 if either the given alarm is not in progress or it has passed + */ +int64_t remaining_alarm_time_us(alarm_id_t alarm_id); + +/*! + * \brief Return the time remaining before the next trigger of an alarm + * \ingroup alarm + * + * @param alarm_id the alarm + * + * @return >=0 the number of microseconds before the next trigger (INT32_MAX if the number of ms is higher than can be represented0 + * @return <0 if either the given alarm is not in progress or it has passed + */ +int32_t remaining_alarm_time_ms(alarm_id_t alarm_id); + #endif /*! @@ -693,7 +751,7 @@ struct repeating_timer { * * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. * - * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback) + * @param pool the alarm pool to use for scheduling the repeating timer (this determines which timer_alarm is used, and which core calls the callback) * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 * @param callback the repeating timer callback function * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. @@ -713,7 +771,7 @@ bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, rep * * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core. * - * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback) + * @param pool the alarm pool to use for scheduling the repeating timer (this determines which timer_alarm is used, and which core calls the callback) * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond * @param callback the repeating timer callback function * @param user_data user data to pass to store in the repeating_timer structure for use by the callback. diff --git a/src/common/pico_time/include/pico/timeout_helper.h b/src/common/pico_time/include/pico/timeout_helper.h index e757f7305..88de8d85d 100644 --- a/src/common/pico_time/include/pico/timeout_helper.h +++ b/src/common/pico_time/include/pico/timeout_helper.h @@ -18,7 +18,7 @@ typedef struct timeout_state { uint64_t param; } timeout_state_t; -typedef bool (*check_timeout_fn)(timeout_state_t *ts); +typedef bool (*check_timeout_fn)(timeout_state_t *ts, bool reset); check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target); check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us); diff --git a/src/common/pico_time/time.c b/src/common/pico_time/time.c index d4511f4db..118547d8a 100644 --- a/src/common/pico_time/time.c +++ b/src/common/pico_time/time.c @@ -4,205 +4,287 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include -#include -#include #include #include "pico.h" #include "pico/time.h" -#include "pico/util/pheap.h" #include "pico/sync.h" +#include "pico/runtime_init.h" const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0); const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, INT64_MAX); typedef struct alarm_pool_entry { - absolute_time_t target; + // next entry link or -1 + int16_t next; + // low 15 bits are a sequence number used in the low word of the alarm_id so that + // the alarm_id for this entry only repeats every 32767 adds (note this value is never zero) + // the top bit is a cancellation flag. + volatile uint16_t sequence; + int64_t target; alarm_callback_t callback; void *user_data; } alarm_pool_entry_t; struct alarm_pool { - pheap_t *heap; + uint8_t timer_alarm_num; + uint8_t core_num; + // this is protected by the lock (threads allocate from it, and the IRQ handler adds back to it) + int16_t free_head; + // this is protected by the lock (threads add to it, the IRQ handler removes from it) + volatile int16_t new_head; + volatile bool has_pending_cancellations; + + // this is owned by the IRQ handler so doesn't need additional locking + int16_t ordered_head; + uint16_t num_entries; + alarm_pool_timer_t *timer; spin_lock_t *lock; alarm_pool_entry_t *entries; - // one byte per entry, used to provide more longevity to public IDs than heap node ids do - // (this is increment every time the heap node id is re-used) - uint8_t *entry_ids_high; - alarm_id_t alarm_in_progress; // this is set during a callback from the IRQ handler... it can be cleared by alarm_cancel to prevent repeats - uint8_t hardware_alarm_num; - uint8_t core_num; }; #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED // To avoid bringing in calloc, we statically allocate the arrays and the heap -PHEAP_DEFINE_STATIC(default_alarm_pool_heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS); static alarm_pool_entry_t default_alarm_pool_entries[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS]; -static uint8_t default_alarm_pool_entry_ids_high[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS]; -static lock_core_t sleep_notifier; static alarm_pool_t default_alarm_pool = { - .heap = &default_alarm_pool_heap, .entries = default_alarm_pool_entries, - .entry_ids_high = default_alarm_pool_entry_ids_high, }; static inline bool default_alarm_pool_initialized(void) { return default_alarm_pool.lock != NULL; } + +static lock_core_t sleep_notifier; #endif -static alarm_pool_t *pools[NUM_TIMERS]; -static void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num); +#include "pico/time_adapter.h" +static alarm_pool_t *pools[TA_NUM_TIMERS][TA_NUM_TIMER_ALARMS]; -static inline alarm_pool_entry_t *get_entry(alarm_pool_t *pool, pheap_node_id_t id) { - assert(id && id <= pool->heap->max_nodes); - return pool->entries + id - 1; -} +static void alarm_pool_post_alloc_init(alarm_pool_t *pool, alarm_pool_timer_t *timer, uint hardware_alarm_num, uint max_timers); -static inline uint8_t *get_entry_id_high(alarm_pool_t *pool, pheap_node_id_t id) { - assert(id && id <= pool->heap->max_nodes); - return pool->entry_ids_high + id - 1; +static inline int16_t alarm_index(alarm_id_t id) { + return (int16_t)(id >> 16); } -bool timer_pool_entry_comparator(void *user_data, pheap_node_id_t a, pheap_node_id_t b) { - alarm_pool_t *pool = (alarm_pool_t *)user_data; - return to_us_since_boot(get_entry(pool, a)->target) < to_us_since_boot(get_entry(pool, b)->target); +static inline uint16_t alarm_sequence(alarm_id_t id) { + return (uint16_t)id; } -static inline alarm_id_t make_public_id(uint8_t id_high, pheap_node_id_t id) { - return (alarm_id_t)(((uint)id_high << 8u * sizeof(id)) | id); +static alarm_id_t make_alarm_id(int index, uint16_t counter) { + return index << 16 | counter; } -void alarm_pool_init_default() { +#if !PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL +void __weak runtime_init_default_alarm_pool(void) { #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED // allow multiple calls for ease of use from host tests if (!default_alarm_pool_initialized()) { - ph_post_alloc_init(default_alarm_pool.heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS, - timer_pool_entry_comparator, &default_alarm_pool); - hardware_alarm_claim(PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM); + alarm_pool_timer_t *timer = alarm_pool_get_default_timer(); + ta_hardware_alarm_claim(timer, PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM); alarm_pool_post_alloc_init(&default_alarm_pool, - PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM); + timer, + PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, + PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS); } lock_init(&sleep_notifier, PICO_SPINLOCK_ID_TIMER); #endif } +#endif + +void alarm_pool_init_default(void) { + runtime_init_default_alarm_pool(); +} #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED -alarm_pool_t *alarm_pool_get_default() { +alarm_pool_t *alarm_pool_get_default(void) { assert(default_alarm_pool_initialized()); return &default_alarm_pool; } + +#if defined(PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL) && !PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL +PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_default_alarm_pool, PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL); +#endif #endif -static pheap_node_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, - void *user_data, pheap_node_id_t reuse_id, bool create_if_past, bool *missed) { - pheap_node_id_t id; - if (reuse_id) { - assert(!ph_contains_node(pool->heap, reuse_id)); - id = reuse_id; - } else { - id = ph_new_node(pool->heap); +// note the timer is created with IRQs on this core +alarm_pool_t *alarm_pool_create_on_timer(alarm_pool_timer_t *timer, uint hardware_alarm_num, uint max_timers) { + alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t)); + if (pool) { + pool->entries = (alarm_pool_entry_t *) calloc(max_timers, sizeof(alarm_pool_entry_t)); + ta_hardware_alarm_claim(timer, hardware_alarm_num); + alarm_pool_post_alloc_init(pool, timer, hardware_alarm_num, max_timers); } - if (id) { - alarm_pool_entry_t *entry = get_entry(pool, id); - entry->target = time; - entry->callback = callback; - entry->user_data = user_data; - if (id == ph_insert_node(pool->heap, id)) { - bool is_missed = hardware_alarm_set_target(pool->hardware_alarm_num, time); - if (is_missed && !create_if_past) { - ph_remove_and_free_node(pool->heap, id); - } - if (missed) *missed = is_missed; - } + return pool; +} + +alarm_pool_t *alarm_pool_create_on_timer_with_unused_hardware_alarm(alarm_pool_timer_t *timer, uint max_timers) { + alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t)); + if (pool) { + pool->entries = (alarm_pool_entry_t *) calloc(max_timers, sizeof(alarm_pool_entry_t)); + alarm_pool_post_alloc_init(pool, timer, (uint) ta_hardware_alarm_claim_unused(timer, true), max_timers); } - return id; + return pool; } -static void alarm_pool_alarm_callback(uint alarm_num) { - // note this is called from timer IRQ handler - alarm_pool_t *pool = pools[alarm_num]; - bool again; +static void alarm_pool_irq_handler(void); + +// marker which we can use in place of handler function to indicate we are a repeating timer + +#define repeating_timer_marker ((alarm_callback_t)alarm_pool_irq_handler) +#include "hardware/gpio.h" +static void alarm_pool_irq_handler(void) { + // This IRQ handler does the main work, as it always (assuming the IRQ hasn't been enabled on both cores + // which is unsupported) run on the alarm pool's core, and can't be preempted by itself, meaning + // that it doesn't need locks except to protect against linked list access + uint timer_alarm_num; + alarm_pool_timer_t *timer = ta_from_current_irq(&timer_alarm_num); + uint timer_num = ta_timer_num(timer); + alarm_pool_t *pool = pools[timer_num][timer_alarm_num]; + assert(pool->timer_alarm_num == timer_alarm_num); + int64_t now = (int64_t) ta_time_us_64(timer); + int64_t earliest_target; + // 1. clear force bits if we were forced (do this outside the loop, as forcing is hopefully rare) + ta_clear_force_irq(timer, timer_alarm_num); do { - absolute_time_t now = get_absolute_time(); - alarm_callback_t callback = NULL; - absolute_time_t target = nil_time; - void *user_data = NULL; - uint8_t id_high; - again = false; - uint32_t save = spin_lock_blocking(pool->lock); - pheap_node_id_t next_id = ph_peek_head(pool->heap); - if (next_id) { - alarm_pool_entry_t *entry = get_entry(pool, next_id); - if (absolute_time_diff_us(now, entry->target) <= 0) { - // we don't free the id in case we need to re-add the timer - pheap_node_id_t __unused removed_id = ph_remove_head(pool->heap, false); - assert(removed_id == next_id); // will be true under lock - target = entry->target; - callback = entry->callback; - user_data = entry->user_data; - assert(callback); - id_high = *get_entry_id_high(pool, next_id); - pool->alarm_in_progress = make_public_id(id_high, removed_id); - } else { - if (hardware_alarm_set_target(alarm_num, entry->target)) { - again = true; + // 2. clear the IRQ if it was fired + ta_clear_irq(timer, timer_alarm_num); + // 3. we look at the earliest existing alarm first; the reasoning here is that we + // don't want to delay an existing callback because a later one is added, and + // if both are due now, then we have a race anyway (but we prefer to fire existing + // timers before new ones anyway. + int16_t earliest_index = pool->ordered_head; + // by default, we loop if there was any event pending (we will mark it false + // later if there is no work to do) + if (earliest_index >= 0) { + alarm_pool_entry_t *earliest_entry = &pool->entries[earliest_index]; + earliest_target = earliest_entry->target; + if ((now - earliest_target) >= 0) { + // time to call the callback now (or in the past) + // note that an entry->target of < 0 means the entry has been canceled (not this is set + // by this function, in response to the entry having been queued by the cancel_alarm API + // meaning that we don't need to worry about tearing of the 64 bit value) + int64_t delta; + if (earliest_target >= 0) { + // special case repeating timer without making another function call which adds overhead + if (earliest_entry->callback == repeating_timer_marker) { + repeating_timer_t *rpt = (repeating_timer_t *)earliest_entry->user_data; + delta = rpt->callback(rpt) ? rpt->delay_us : 0; + } else { + alarm_id_t id = make_alarm_id(pool->ordered_head, earliest_entry->sequence); + delta = earliest_entry->callback(id, earliest_entry->user_data); + } + } else { + // negative target means cancel alarm + delta = 0; + } + if (delta) { + int64_t next_time; + if (delta < 0) { + // delta is (positive) delta from last fire time + next_time = earliest_target - delta; + } else { + // delta is relative to now + next_time = (int64_t) ta_time_us_64(timer) + delta; + } + earliest_entry->target = next_time; + // need to re-add, unless we are the only entry or already at the front + if (earliest_entry->next >= 0 && next_time - pool->entries[earliest_entry->next].target >= 0) { + // unlink this item + pool->ordered_head = earliest_entry->next; + int16_t *prev = &pool->ordered_head; + // find insertion point; note >= as if we add a new item for the same time as another, then it follows + while (*prev >= 0 && (next_time - pool->entries[*prev].target) >= 0) { + prev = &pool->entries[*prev].next; + } + earliest_entry->next = *prev; + *prev = earliest_index; + } + } else { + // need to remove the item + pool->ordered_head = earliest_entry->next; + // and add it back to the free list (under lock) + uint32_t save = spin_lock_blocking(pool->lock); + earliest_entry->next = pool->free_head; + pool->free_head = earliest_index; + spin_unlock(pool->lock, save); } } } - spin_unlock(pool->lock, save); - if (callback) { - int64_t repeat = callback(make_public_id(id_high, next_id), user_data); - save = spin_lock_blocking(pool->lock); - // todo think more about whether we want to keep calling - if (repeat < 0 && pool->alarm_in_progress) { - assert(pool->alarm_in_progress == make_public_id(id_high, next_id)); - add_alarm_under_lock(pool, delayed_by_us(target, (uint64_t)-repeat), callback, user_data, next_id, true, NULL); - } else if (repeat > 0 && pool->alarm_in_progress) { - assert(pool->alarm_in_progress == make_public_id(id_high, next_id)); - add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), (uint64_t)repeat), callback, user_data, next_id, - true, NULL); - } else { - // need to return the id to the heap - ph_free_node(pool->heap, next_id); - (*get_entry_id_high(pool, next_id))++; // we bump it for next use of id - } - pool->alarm_in_progress = 0; + // if we have any new alarms, add them to the ordered list + if (pool->new_head >= 0) { + uint32_t save = spin_lock_blocking(pool->lock); + // must re-read new head under lock + int16_t new_index = pool->new_head; + // clear the list + pool->new_head = -1; spin_unlock(pool->lock, save); - again = true; + // insert each of the new items + while (new_index >= 0) { + alarm_pool_entry_t *new_entry = &pool->entries[new_index]; + int64_t new_entry_time = new_entry->target; + int16_t *prev = &pool->ordered_head; + // find insertion point; note >= as if we add a new item for the same time as another, then it follows + while (*prev >= 0 && (new_entry_time - pool->entries[*prev].target) >= 0) { + prev = &pool->entries[*prev].next; + } + int16_t next = *prev; + *prev = new_index; + new_index = new_entry->next; + new_entry->next = next; + } } - } while (again); -} - -// note the timer is create with IRQs on this core -alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers) { - alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t)); - pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool); - pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t)); - pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t)); - hardware_alarm_claim(hardware_alarm_num); - alarm_pool_post_alloc_init(pool, hardware_alarm_num); - return pool; -} - -alarm_pool_t *alarm_pool_create_with_unused_hardware_alarm(uint max_timers) { - alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t)); - pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool); - pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t)); - pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t)); - alarm_pool_post_alloc_init(pool, (uint)hardware_alarm_claim_unused(true)); - return pool; + // if we have any canceled alarms, then mark them for removal by setting their due time to -1 (which will + // cause them to be handled the next time round and removed) + if (pool->has_pending_cancellations) { + pool->has_pending_cancellations = false; + __compiler_memory_barrier(); + int16_t *prev = &pool->ordered_head; + // set target for canceled items to -1, and move to front of the list + for(int16_t index = pool->ordered_head; index != -1; ) { + alarm_pool_entry_t *entry = &pool->entries[index]; + int16_t next = entry->next; + if ((int16_t)entry->sequence < 0) { + // mark for deletion + entry->target = -1; + if (index != pool->ordered_head) { + // move to start of queue + *prev = entry->next; + entry->next = pool->ordered_head; + pool->ordered_head = index; + } + } else { + prev = &entry->next; + } + index = next; + } + } + now = (int64_t) ta_time_us_64(timer); + earliest_index = pool->ordered_head; + if (earliest_index < 0) break; + // need to wait + alarm_pool_entry_t *earliest_entry = &pool->entries[earliest_index]; + earliest_target = earliest_entry->target; + ta_set_timeout(timer, timer_alarm_num, earliest_target); + // check we haven't now past the target time; if not we don't want to loop again + } while ((earliest_target - now) <= 0); } -void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num) { - hardware_alarm_cancel(hardware_alarm_num); - hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback); +void alarm_pool_post_alloc_init(alarm_pool_t *pool, alarm_pool_timer_t *timer, uint hardware_alarm_num, uint max_timers) { + pool->timer = timer; pool->lock = spin_lock_instance(next_striped_spin_lock_num()); - pool->hardware_alarm_num = (uint8_t) hardware_alarm_num; + pool->timer_alarm_num = (uint8_t) hardware_alarm_num; + invalid_params_if(PICO_TIME, max_timers > 65536); + pool->num_entries = (uint16_t)max_timers; pool->core_num = (uint8_t) get_core_num(); - pools[hardware_alarm_num] = pool; + pool->new_head = pool->ordered_head = -1; + pool->free_head = (int16_t)(max_timers - 1); + for(uint i=0;ientries[i].next = (int16_t)(i-1); + } + pools[ta_timer_num(timer)][hardware_alarm_num] = pool; + + ta_enable_irq_handler(timer, hardware_alarm_num, alarm_pool_irq_handler); } void alarm_pool_destroy(alarm_pool_t *pool) { @@ -212,164 +294,85 @@ void alarm_pool_destroy(alarm_pool_t *pool) { return; } #endif - assert(pools[pool->hardware_alarm_num] == pool); - pools[pool->hardware_alarm_num] = NULL; - // todo clear out timers - ph_destroy(pool->heap); - hardware_alarm_set_callback(pool->hardware_alarm_num, NULL); - hardware_alarm_unclaim(pool->hardware_alarm_num); - free(pool->entry_ids_high); + ta_disable_irq_handler(pool->timer, pool->timer_alarm_num, alarm_pool_irq_handler); + assert(pools[ta_timer_num(pool->timer)][pool->timer_alarm_num] == pool); + pools[ta_timer_num(pool->timer)][pool->timer_alarm_num] = NULL; free(pool->entries); free(pool); } alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) { - bool missed = false; - - alarm_id_t public_id; - do { - uint8_t id_high = 0; - uint32_t save = spin_lock_blocking(pool->lock); - - pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, false, &missed); - if (id) id_high = *get_entry_id_high(pool, id); - - spin_unlock(pool->lock, save); - - if (!id) { - // no space in pheap to allocate an alarm - return -1; - } - - // note that if missed was true, then the id was never added to the pheap (because we - // passed false for create_if_past arg above) - public_id = missed ? 0 : make_public_id(id_high, id); - if (missed && fire_if_past) { - // ... so if fire_if_past == true we call the callback - int64_t repeat = callback(public_id, user_data); - // if not repeated we have no id to return so set public_id to 0, - // otherwise we need to repeat, but will assign a new id next time - // todo arguably this does mean that the id passed to the first callback may differ from subsequent calls - if (!repeat) { - public_id = 0; - break; - } else if (repeat < 0) { - time = delayed_by_us(time, (uint64_t)-repeat); - } else { - time = delayed_by_us(get_absolute_time(), (uint64_t)repeat); - } - } else { - // either: - // a) missed == false && public_id is > 0 - // b) missed == true && fire_if_past == false && public_id = 0 - // but we are done in either case - break; - } - } while (true); - return public_id; + if (!fire_if_past) { + absolute_time_t t = get_absolute_time(); + if (absolute_time_diff_us(t, time) < 0) return 0; + } + return alarm_pool_add_alarm_at_force_in_context(pool, time, callback, user_data); } alarm_id_t alarm_pool_add_alarm_at_force_in_context(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data) { - bool missed = false; - - uint8_t id_high = 0; + // ---- take a free pool entry uint32_t save = spin_lock_blocking(pool->lock); - - pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, true, &missed); - if (id) id_high = *get_entry_id_high(pool, id); - spin_unlock(pool->lock, save); - if (!id) return -1; - if (missed) { - // we want to fire the timer forcibly because it is in the past. Note that we do - // not care about racing with other timers, as it is harmless to have the IRQ - // wake up one time too many, we just need to make sure it does wake up - hardware_alarm_force_irq(pool->hardware_alarm_num); + int16_t index = pool->free_head; + alarm_pool_entry_t *entry = &pool->entries[index]; + if (index >= 0) { + // remove from free list + pool->free_head = entry->next; } - return make_public_id(id_high, id); + spin_unlock(pool->lock, save); + if (index < 0) return PICO_ERROR_GENERIC; // PICO_ERROR_INSUFFICIENT_RESOURCES - not using to preserve previous -1 return code + + // ---- initialize the pool entry + entry->callback = callback; + entry->user_data = user_data; + entry->target = (int64_t)to_us_since_boot(time); + uint16_t next_sequence = (entry->sequence + 1) & 0x7fff; + if (!next_sequence) next_sequence = 1; // zero is not allowed + entry->sequence = next_sequence; + alarm_id_t id = make_alarm_id(index, next_sequence); + + // ---- and add it to the new list + save = spin_lock_blocking(pool->lock); + entry->next = pool->new_head; + pool->new_head = index; + spin_unlock(pool->lock, save); + + // force the IRQ + ta_force_irq(pool->timer, pool->timer_alarm_num); + return id; } bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id) { - if (!alarm_id) return false; - bool rc = false; + int16_t index = alarm_index(alarm_id); + if (index >= pool->num_entries) return false; + uint16_t sequence = alarm_sequence(alarm_id); + bool canceled = false; + alarm_pool_entry_t *entry = &pool->entries[index]; uint32_t save = spin_lock_blocking(pool->lock); - pheap_node_id_t id = (pheap_node_id_t) alarm_id; - if (ph_contains_node(pool->heap, id)) { - assert(alarm_id != pool->alarm_in_progress); // it shouldn't be in the heap if it is in progress - // check we have the right high value - uint8_t id_high = (uint8_t)((uint)alarm_id >> 8u * sizeof(pheap_node_id_t)); - if (id_high == *get_entry_id_high(pool, id)) { - rc = ph_remove_and_free_node(pool->heap, id); - // note we don't bother to remove the actual hardware alarm timeout... - // it will either do callbacks or not depending on other alarms, and reset the next timeout itself - assert(rc); - } - } else { - if (alarm_id == pool->alarm_in_progress) { - // make sure the alarm doesn't repeat - pool->alarm_in_progress = 0; - } + // note this will not be true if the entry is already canceled (as the entry->sequence + // will have the top bit set) + uint current_sequence = entry->sequence; + if (sequence == current_sequence) { + entry->sequence = (uint16_t)(current_sequence | 0x8000); + __compiler_memory_barrier(); + pool->has_pending_cancellations = true; + canceled = true; } spin_unlock(pool->lock, save); - return rc; + // force the IRQ if we need to clean up an alarm id + if (canceled) ta_force_irq(pool->timer, pool->timer_alarm_num); + return canceled; } -uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool) { - return pool->hardware_alarm_num; +uint alarm_pool_timer_alarm_num(alarm_pool_t *pool) { + return pool->timer_alarm_num; } uint alarm_pool_core_num(alarm_pool_t *pool) { return pool->core_num; } -static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) { - alarm_pool_t *pool = (alarm_pool_t *)user_data; -#if PICO_ON_DEVICE - printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id)); -#else - printf("%"PRIu64, to_us_since_boot(get_entry(pool, id)->target)); -#endif -} - -static int64_t repeating_timer_callback(__unused alarm_id_t id, void *user_data) { - repeating_timer_t *rt = (repeating_timer_t *)user_data; - if (rt->callback(rt)) { - return rt->delay_us; - } else { - rt->alarm_id = 0; - return 0; - } -} - -bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { - if (!delay_us) delay_us = 1; - out->pool = pool; - out->callback = callback; - out->delay_us = delay_us; - out->user_data = user_data; - out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)), - repeating_timer_callback, out, true); - // note that if out->alarm_id is 0, then the callback was called during the above call (fire_if_past == true) - // and then the callback removed itself. - return out->alarm_id >= 0; -} - -bool cancel_repeating_timer(repeating_timer_t *timer) { - bool rc = false; - if (timer->alarm_id) { - rc = alarm_pool_cancel_alarm(timer->pool, timer->alarm_id); - timer->alarm_id = 0; - } - return rc; -} - -void alarm_pool_dump(alarm_pool_t *pool) { - uint32_t save = spin_lock_blocking(pool->lock); - ph_dump(pool->heap, alarm_pool_dump_key, pool); - spin_unlock(pool->lock, save); -} - #if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED static int64_t sleep_until_callback(__unused alarm_id_t id, __unused void *user_data) { uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock); @@ -419,7 +422,7 @@ void sleep_us(uint64_t us) { absolute_time_t t = make_timeout_time_us(us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US); sync_internal_yield_until_before(t); - // then wait the rest of thw way + // then wait the rest of the way busy_wait_until(t); } #endif @@ -441,7 +444,18 @@ bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) { tight_loop_contents(); return time_reached(timeout_timestamp); } else { + // the above alarm add now may force an IRQ which will wake us up, + // so we want to consume one __wfe.. we do an explicit __sev + // just to make sure there is one + __sev(); // make sure there is an event sow ee don't block __wfe(); + if (!time_reached(timeout_timestamp)) + { + // ^ at the point above the timer hadn't fired, so it is safe + // to wait; the event will happen due to IRQ at some point between + // then and the correct wakeup time + __wfe(); + } // we need to clean up if it wasn't us that caused the wfe; if it was this will be a noop. cancel_alarm(id); return time_reached(timeout_timestamp); @@ -452,3 +466,75 @@ bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) { return time_reached(timeout_timestamp); #endif } + +bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) { + if (!delay_us) delay_us = 1; + out->pool = pool; + out->callback = callback; + out->delay_us = delay_us; + out->user_data = user_data; + out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)), + repeating_timer_marker, out, true); + return out->alarm_id > 0; +} + +bool cancel_repeating_timer(repeating_timer_t *timer) { + bool rc = false; + if (timer->alarm_id) { + rc = alarm_pool_cancel_alarm(timer->pool, timer->alarm_id); + timer->alarm_id = 0; + } + return rc; +} + +alarm_pool_timer_t *alarm_pool_timer_for_timer_num(uint timer_num) { + return ta_timer_instance(timer_num); +} + +alarm_pool_timer_t *alarm_pool_get_default_timer(void) { + return ta_default_timer_instance(); +} + +int64_t alarm_pool_remaining_alarm_time_us(alarm_pool_t *pool, alarm_id_t alarm_id) { + // note there is no point distinguishing between invalid alarm_id and timer passed, + // since an alarm_id that has fired without being re-enabled becomes logically invalid after + // that point anyway + int64_t rc = -1; + int16_t index = alarm_index(alarm_id); + if ((uint16_t)index < pool->num_entries) { + uint16_t sequence = alarm_sequence(alarm_id); + alarm_pool_entry_t *entry = &pool->entries[index]; + if (entry->sequence == sequence) { + uint32_t save = spin_lock_blocking(pool->lock); + int16_t search_index = pool->ordered_head; + while (search_index >= 0) { + entry = &pool->entries[search_index]; + if (index == search_index) { + if (entry->sequence == sequence) { + rc = entry->target - (int64_t) ta_time_us_64(pool->timer); + } + break; + } + search_index = entry->next; + } + spin_unlock(pool->lock, save); + } + } + return rc; +} + +int32_t alarm_pool_remaining_alarm_time_ms(alarm_pool_t *pool, alarm_id_t alarm_id) { + int64_t rc = alarm_pool_remaining_alarm_time_us(pool, alarm_id); + if (rc >= 0) rc /= 1000; + return rc >= INT32_MAX ? INT32_MAX : (int32_t) rc; +} + +#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +int64_t remaining_alarm_time_us(alarm_id_t alarm_id) { + return alarm_pool_remaining_alarm_time_us(alarm_pool_get_default(), alarm_id); +} + +int32_t remaining_alarm_time_ms(alarm_id_t alarm_id) { + return alarm_pool_remaining_alarm_time_ms(alarm_pool_get_default(), alarm_id); +} +#endif \ No newline at end of file diff --git a/src/common/pico_time/timeout_helper.c b/src/common/pico_time/timeout_helper.c index d9abe5a33..3f2245743 100644 --- a/src/common/pico_time/timeout_helper.c +++ b/src/common/pico_time/timeout_helper.c @@ -6,7 +6,7 @@ #include "pico/timeout_helper.h" -static bool check_single_timeout_us(timeout_state_t *ts) { +static bool check_single_timeout_us(timeout_state_t *ts, __unused bool reset) { return time_reached(ts->next_timeout); } @@ -15,11 +15,13 @@ check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t return check_single_timeout_us; } -static bool check_per_iteration_timeout_us(timeout_state_t *ts) { +static bool check_per_iteration_timeout_us(timeout_state_t *ts, bool reset) { + if (reset) { + ts->next_timeout = make_timeout_time_us(ts->param); + } if (time_reached(ts->next_timeout)) { return true; } - ts->next_timeout = make_timeout_time_us(ts->param); return false; } @@ -27,4 +29,4 @@ check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per ts->next_timeout = make_timeout_time_us(per_iteration_timeout_us); ts->param = per_iteration_timeout_us; return check_per_iteration_timeout_us; -} +} \ No newline at end of file diff --git a/src/common/pico_usb_reset_interface/BUILD.bazel b/src/common/pico_usb_reset_interface_headers/BUILD.bazel similarity index 75% rename from src/common/pico_usb_reset_interface/BUILD.bazel rename to src/common/pico_usb_reset_interface_headers/BUILD.bazel index 14f4a3420..880792dd3 100644 --- a/src/common/pico_usb_reset_interface/BUILD.bazel +++ b/src/common/pico_usb_reset_interface_headers/BUILD.bazel @@ -1,7 +1,7 @@ package(default_visibility = ["//visibility:public"]) cc_library( - name = "pico_usb_reset_interface", + name = "pico_usb_reset_interface_headers", hdrs = ["include/pico/usb_reset_interface.h"], includes = ["include"], ) diff --git a/src/common/pico_usb_reset_interface/CMakeLists.txt b/src/common/pico_usb_reset_interface_headers/CMakeLists.txt similarity index 70% rename from src/common/pico_usb_reset_interface/CMakeLists.txt rename to src/common/pico_usb_reset_interface_headers/CMakeLists.txt index 7d2b4e7bc..6be755edc 100644 --- a/src/common/pico_usb_reset_interface/CMakeLists.txt +++ b/src/common/pico_usb_reset_interface_headers/CMakeLists.txt @@ -3,4 +3,4 @@ add_library(pico_usb_reset_interface_headers INTERFACE) add_library(pico_usb_reset_interface INTERFACE) target_link_libraries(pico_usb_reset_interface INTERFACE pico_usb_reset_interface_headers) -target_include_directories(pico_usb_reset_interface_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_usb_reset_interface_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) diff --git a/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h b/src/common/pico_usb_reset_interface_headers/include/pico/usb_reset_interface.h similarity index 88% rename from src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h rename to src/common/pico_usb_reset_interface_headers/include/pico/usb_reset_interface.h index 908ec0c69..d5269ecf8 100644 --- a/src/common/pico_usb_reset_interface/include/pico/usb_reset_interface.h +++ b/src/common/pico_usb_reset_interface_headers/include/pico/usb_reset_interface.h @@ -8,7 +8,7 @@ #define _PICO_USB_RESET_INTERFACE_H /** \file usb_reset_interface.h - * \defgroup pico_usb_reset_interface pico_usb_reset_interface + * \defgroup pico_usb_reset_interface_headers pico_usb_reset_interface_headers * * \brief Definition for the reset interface that may be exposed by the pico_stdio_usb library */ diff --git a/src/common/pico_util/BUILD.bazel b/src/common/pico_util/BUILD.bazel index 7eed87ade..6ee64a311 100644 --- a/src/common/pico_util/BUILD.bazel +++ b/src/common/pico_util/BUILD.bazel @@ -1,3 +1,5 @@ +load("@pico-sdk//bazel:defs.bzl", "incompatible_with_config") + package(default_visibility = ["//visibility:public"]) cc_library( @@ -13,8 +15,10 @@ cc_library( "include/pico/util/queue.h", ], includes = ["include"], + # invalid_params_if() uses Statement Expressions, which aren't supported in MSVC. + target_compatible_with = incompatible_with_config("@rules_cc//cc/compiler:msvc-cl"), deps = [ - "//src/common/pico_base:pico_base_interface", + "//src/common/pico_base_headers", "//src/common/pico_sync", ] + select({ "//bazel/constraint:host": [ diff --git a/src/common/pico_util/CMakeLists.txt b/src/common/pico_util/CMakeLists.txt index 3a4d7cde9..86921dd4e 100644 --- a/src/common/pico_util/CMakeLists.txt +++ b/src/common/pico_util/CMakeLists.txt @@ -1,6 +1,6 @@ if (NOT TARGET pico_util_headers) add_library(pico_util_headers INTERFACE) - target_include_directories(pico_util_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_util_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(pico_util_headers INTERFACE pico_base_headers hardware_sync_headers) endif() diff --git a/src/common/pico_util/datetime.c b/src/common/pico_util/datetime.c index e035515d3..c113ce466 100644 --- a/src/common/pico_util/datetime.c +++ b/src/common/pico_util/datetime.c @@ -2,6 +2,7 @@ #include +#if PICO_INCLUDE_RTC_DATETIME static const char *DATETIME_MONTHS[12] = { "January", "February", @@ -38,4 +39,57 @@ void datetime_to_str(char *buf, uint buf_size, const datetime_t *t) { t->min, t->sec, t->year); -}; \ No newline at end of file +}; + + +bool time_to_datetime(time_t time, datetime_t *dt) { + struct tm local; + if (localtime_r(&time, &local)) { + dt->year = (int16_t) (local.tm_year + 1900); // 0..4095 + dt->month = (int8_t) (local.tm_mon + 1); // 1..12, 1 is January + dt->day = (int8_t) local.tm_mday; // 1..28,29,30,31 depending on month + dt->dotw = (int8_t) local.tm_wday; // 0..6, 0 is Sunday + dt->hour = (int8_t) local.tm_hour; // 0..23 + dt->min = (int8_t) local.tm_min; // 0..59 + dt->sec = (int8_t) local.tm_sec; // 0..59 + return true; + } + return false; +} + +bool datetime_to_time(const datetime_t *dt, time_t *time) { + struct tm local; + local.tm_year = dt->year - 1900; + local.tm_mon = dt->month - 1; + local.tm_mday = dt->day; + local.tm_hour = dt->hour; + local.tm_min = dt->min; + local.tm_sec = dt->sec; + *time = mktime(&local); + return *time >= 0; +} + +#endif + +uint64_t timespec_to_ms(const struct timespec *ts) { + int64_t rc = ts->tv_sec * 1000; + rc += ts->tv_nsec / 1000000; + return (uint64_t) rc; +} + +void ms_to_timespec(uint64_t ms, struct timespec *ts) { + ts->tv_sec = (time_t)((int64_t)ms / 1000); + ts->tv_nsec = ((long)((int64_t)ms % 1000)) * 1000000; +} + +uint64_t timespec_to_us(const struct timespec *ts) { + int64_t rc = ts->tv_sec * 1000000; + rc += ts->tv_nsec / 1000; + return (uint64_t) rc; +} + +void us_to_timespec(uint64_t ms, struct timespec *ts) { + ts->tv_sec = (time_t)((int64_t)ms / 1000000); + ts->tv_nsec = ((long)((int64_t)ms % 1000000)) * 1000; +} + diff --git a/src/common/pico_util/include/pico/util/datetime.h b/src/common/pico_util/include/pico/util/datetime.h index a897f6ea4..92e6d6460 100644 --- a/src/common/pico_util/include/pico/util/datetime.h +++ b/src/common/pico_util/include/pico/util/datetime.h @@ -19,6 +19,9 @@ extern "C" { * \ingroup pico_util */ +#if PICO_INCLUDE_RTC_DATETIME +#include + /*! \brief Convert a datetime_t structure to a string * \ingroup util_datetime * @@ -28,6 +31,16 @@ extern "C" { */ void datetime_to_str(char *buf, uint buf_size, const datetime_t *t); +bool time_to_datetime(time_t time, datetime_t *dt); +bool datetime_to_time(const datetime_t *dt, time_t *time); +#endif + +#include +uint64_t timespec_to_ms(const struct timespec *ts); +uint64_t timespec_to_us(const struct timespec *ts); +void ms_to_timespec(uint64_t ms, struct timespec *ts); +void us_to_timespec(uint64_t ms, struct timespec *ts); + #ifdef __cplusplus } #endif diff --git a/src/common/pico_util/include/pico/util/queue.h b/src/common/pico_util/include/pico/util/queue.h index 282298581..998b434dc 100644 --- a/src/common/pico_util/include/pico/util/queue.h +++ b/src/common/pico_util/include/pico/util/queue.h @@ -17,7 +17,7 @@ /** \file queue.h * \defgroup queue queue - * \brief Multi-core and IRQ safe queue implementation. + * \brief Multi-core and IRQ safe queue implementation * * Note that this queue stores values of a specified size, and pushed values are copied into the queue * \ingroup pico_util @@ -169,7 +169,7 @@ bool queue_try_add(queue_t *q, const void *data); * \ingroup queue * * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the removed value + * \param data Pointer to the location to receive the removed value, or NULL if the data isn't required * \return true if a value was removed * * If the queue is not empty function will copy the removed value into the location provided and return @@ -181,7 +181,7 @@ bool queue_try_remove(queue_t *q, void *data); * \ingroup queue * * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the peeked value + * \param data Pointer to the location to receive the peeked value, or NULL if the data isn't required * \return true if there was a value to peek * * If the queue is not empty this function will return immediately with true with the peeked entry @@ -205,7 +205,7 @@ void queue_add_blocking(queue_t *q, const void *data); * \ingroup queue * * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the removed value + * \param data Pointer to the location to receive the removed value, or NULL if the data isn't required * * If the queue is empty this function will block until a value is added. */ @@ -215,7 +215,7 @@ void queue_remove_blocking(queue_t *q, void *data); * \ingroup queue * * \param q Pointer to a queue_t structure, used as a handle - * \param data Pointer to the location to receive the peeked value + * \param data Pointer to the location to receive the peeked value, or NULL if the data isn't required * * If the queue is empty function will block until a value is added */ diff --git a/src/common/pico_util/queue.c b/src/common/pico_util/queue.c index a5c8e181f..9209407d5 100644 --- a/src/common/pico_util/queue.c +++ b/src/common/pico_util/queue.c @@ -63,7 +63,9 @@ static bool queue_remove_internal(queue_t *q, void *data, bool block) { do { uint32_t save = spin_lock_blocking(q->core.spin_lock); if (queue_get_level_unsafe(q) != 0) { - memcpy(data, element_ptr(q, q->rptr), q->element_size); + if (data) { + memcpy(data, element_ptr(q, q->rptr), q->element_size); + } q->rptr = inc_index(q, q->rptr); lock_internal_spin_unlock_with_notify(&q->core, save); return true; @@ -81,7 +83,9 @@ static bool queue_peek_internal(queue_t *q, void *data, bool block) { do { uint32_t save = spin_lock_blocking(q->core.spin_lock); if (queue_get_level_unsafe(q) != 0) { - memcpy(data, element_ptr(q, q->rptr), q->element_size); + if (data) { + memcpy(data, element_ptr(q, q->rptr), q->element_size); + } lock_internal_spin_unlock_with_notify(&q->core, save); return true; } diff --git a/src/host.cmake b/src/host.cmake index 5a3f3584a..3399866f7 100644 --- a/src/host.cmake +++ b/src/host.cmake @@ -1,10 +1,40 @@ -# For targeting the host for testing purposes +set(CMAKE_DIR cmake) +set(COMMON_DIR common) +set(HOST_DIR host) -function(pico_add_extra_outputs TARGET) -endfunction() +include (${CMAKE_DIR}/no_hardware.cmake) -set(PICO_NO_HARDWARE "1" CACHE INTERNAL "") -set(PICO_ON_DEVICE "0" CACHE INTERNAL "") -add_subdirectory(common) -add_subdirectory(host) \ No newline at end of file +# common + pico_add_subdirectory(${COMMON_DIR}/boot_picobin_headers) + pico_add_subdirectory(${COMMON_DIR}/boot_picoboot_headers) + pico_add_subdirectory(${COMMON_DIR}/boot_uf2_headers) + pico_add_subdirectory(${COMMON_DIR}/pico_base_headers) + pico_add_subdirectory(${COMMON_DIR}/pico_usb_reset_interface_headers) + pico_add_subdirectory(${COMMON_DIR}/pico_bit_ops_headers) + pico_add_subdirectory(${COMMON_DIR}/pico_binary_info) + pico_add_subdirectory(${COMMON_DIR}/pico_divider_headers) + pico_add_subdirectory(${COMMON_DIR}/pico_sync) + pico_add_subdirectory(${COMMON_DIR}/pico_time) + pico_add_subdirectory(${COMMON_DIR}/pico_util) + pico_add_subdirectory(${COMMON_DIR}/pico_stdlib_headers) + +# host-specific + pico_add_subdirectory(${HOST_DIR}/hardware_divider) + pico_add_subdirectory(${HOST_DIR}/hardware_gpio) + pico_add_subdirectory(${HOST_DIR}/hardware_sync) + pico_add_subdirectory(${HOST_DIR}/hardware_timer) + pico_add_subdirectory(${HOST_DIR}/hardware_uart) + pico_add_subdirectory(${HOST_DIR}/pico_bit_ops) + pico_add_subdirectory(${HOST_DIR}/pico_divider) + pico_add_subdirectory(${HOST_DIR}/pico_multicore) + pico_add_subdirectory(${HOST_DIR}/pico_platform) + pico_add_subdirectory(${HOST_DIR}/pico_runtime) + pico_add_subdirectory(${HOST_DIR}/pico_printf) + pico_add_subdirectory(${HOST_DIR}/pico_stdio) + pico_add_subdirectory(${HOST_DIR}/pico_stdlib) + pico_add_subdirectory(${HOST_DIR}/pico_time_adapter) + +unset(CMAKE_DIR) +unset(COMMON_DIR) +unset(HOST_DIR) \ No newline at end of file diff --git a/src/host/BUILD.bazel b/src/host/BUILD.bazel new file mode 100644 index 000000000..6dbf95554 --- /dev/null +++ b/src/host/BUILD.bazel @@ -0,0 +1,8 @@ +package(default_visibility = ["//visibility:public"]) + +# This is currently unused in Bazel. +cc_binary( + name = "boot_stage2", + srcs = ["boot_stage2.c"], + target_compatible_with = ["//bazel/constraint:host"], +) diff --git a/src/host/CMakeLists.txt b/src/host/CMakeLists.txt deleted file mode 100644 index 9edcd7b09..000000000 --- a/src/host/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -pico_add_subdirectory(hardware_divider) -pico_add_subdirectory(hardware_gpio) -pico_add_subdirectory(hardware_sync) -pico_add_subdirectory(hardware_timer) -pico_add_subdirectory(hardware_uart) -pico_add_subdirectory(pico_bit_ops) -pico_add_subdirectory(pico_divider) -pico_add_subdirectory(pico_multicore) -pico_add_subdirectory(pico_platform) -pico_add_subdirectory(pico_printf) -pico_add_subdirectory(pico_stdio) -pico_add_subdirectory(pico_stdlib) - -pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) - -macro(pico_set_float_implementation TARGET IMPL) - # ignore -endmacro() - -macro(pico_set_double_implementation TARGET IMPL) - # ignore -endmacro() - -macro(pico_set_binary_type TARGET IMPL) - # ignore -endmacro() - -macro(pico_set_boot_stage2 TARGET IMPL) - # ignore -endmacro() - -set(PICO_HOST_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") -function(pico_define_boot_stage2 NAME) - add_executable(${NAME} ${PICO_HOST_DIR}/boot_stage2.c) -endfunction() - -pico_promote_common_scope_vars() \ No newline at end of file diff --git a/src/host/README.md b/src/host/README.md index c6d89622a..cc2c1f9f0 100644 --- a/src/host/README.md +++ b/src/host/README.md @@ -3,7 +3,7 @@ running on your computer (Raspberry Pi OS, Linux, macOS or Windows using Cygwin It is selected by `PICO_PLATFORM=host` in your CMake build This can be extremely useful for testing and debugging higher level application code, or porting code which is not yet small enough -to run on the RP2040 device itself. +to run on the RP2040 or RP2350 device itself. This base level host library provides a minimal environment to compile programs, but is likely sufficient for programs that don't access hardware directly. diff --git a/src/host/boot_stage2.c b/src/host/boot_stage2.c index 52794b155..704dacc68 100644 --- a/src/host/boot_stage2.c +++ b/src/host/boot_stage2.c @@ -1,3 +1,3 @@ -void main() { +int main() { } \ No newline at end of file diff --git a/src/host/hardware_divider/BUILD.bazel b/src/host/hardware_divider/BUILD.bazel index 3548f1b7b..023340bff 100644 --- a/src/host/hardware_divider/BUILD.bazel +++ b/src/host/hardware_divider/BUILD.bazel @@ -6,5 +6,5 @@ cc_library( hdrs = ["include/hardware/divider.h"], includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], - deps = ["//src/common/pico_base"], + deps = ["//src/host/pico_platform"], ) diff --git a/src/host/hardware_divider/include/hardware/divider.h b/src/host/hardware_divider/include/hardware/divider.h index 0a6eccc07..6e546ea3c 100644 --- a/src/host/hardware_divider/include/hardware/divider.h +++ b/src/host/hardware_divider/include/hardware/divider.h @@ -22,11 +22,11 @@ static inline int __sign_of(int32_t v) { /*! \brief Do an unsigned HW divide and wait for result * \ingroup hardware_divider * - * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. + * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value. * * \param a The dividend * \param b The divisor - * \return Results of divide as a pair of 32-bit quotient/remainder values. + * \return Results of divide as a 32p32 fixed point value. */ static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this @@ -36,11 +36,11 @@ static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { /*! \brief Do a signed HW divide and wait for result * \ingroup hardware_divider * - * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. + * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value. * * \param a The dividend * \param b The divisor - * \return Results of divide as a pair of 32-bit quotient/remainder values. + * \return Results of divide as a 32p32 fixed point value. */ static inline divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b) { if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a)); @@ -108,7 +108,7 @@ static inline void hw_divider_wait_ready(void) {} /*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point * \ingroup hardware_divider * - * \param r A pair of 32-bit quotient/remainder values. + * \param r 32p32 fixed point value. * \return Unsigned quotient */ inline static uint32_t to_quotient_u32(divmod_result_t r) { @@ -118,7 +118,7 @@ inline static uint32_t to_quotient_u32(divmod_result_t r) { /*! \brief Efficient extraction of signed quotient from 32p32 fixed point * \ingroup hardware_divider * - * \param r A pair of 32-bit quotient/remainder values. + * \param r 32p32 fixed point value. * \return Unsigned quotient */ inline static int32_t to_quotient_s32(divmod_result_t r) { @@ -128,7 +128,7 @@ inline static int32_t to_quotient_s32(divmod_result_t r) { /*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point * \ingroup hardware_divider * - * \param r A pair of 32-bit quotient/remainder values. + * \param r 32p32 fixed point value. * \return Unsigned remainder * * \note On Arm this is just a 32 bit register move or a nop @@ -140,7 +140,7 @@ inline static uint32_t to_remainder_u32(divmod_result_t r) { /*! \brief Efficient extraction of signed remainder from 32p32 fixed point * \ingroup hardware_divider * - * \param r A pair of 32-bit quotient/remainder values. + * \param r 32p32 fixed point value. * \return Signed remainder * * \note On arm this is just a 32 bit register move or a nop diff --git a/src/host/hardware_gpio/BUILD.bazel b/src/host/hardware_gpio/BUILD.bazel index 816ebb4d3..29c13aaee 100644 --- a/src/host/hardware_gpio/BUILD.bazel +++ b/src/host/hardware_gpio/BUILD.bazel @@ -6,5 +6,8 @@ cc_library( hdrs = ["include/hardware/gpio.h"], includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], - deps = ["//src/common/pico_base"], + deps = [ + "//src/common/pico_binary_info:LIB_PICO_BINARY_INFO", + "//src/host/pico_platform", + ], ) diff --git a/src/host/hardware_gpio/include/hardware/gpio.h b/src/host/hardware_gpio/include/hardware/gpio.h index ee2f7f6bc..592a562af 100644 --- a/src/host/hardware_gpio/include/hardware/gpio.h +++ b/src/host/hardware_gpio/include/hardware/gpio.h @@ -42,8 +42,6 @@ enum gpio_drive_strength { #define GPIO_OUT 1 #define GPIO_IN 0 -#define NUM_BANK0_GPIOS 30 - // ---------------------------------------------------------------------------- // Pad Controls + IO Muxing // ---------------------------------------------------------------------------- diff --git a/src/host/hardware_irq/BUILD.bazel b/src/host/hardware_irq/BUILD.bazel new file mode 100644 index 000000000..af055a468 --- /dev/null +++ b/src/host/hardware_irq/BUILD.bazel @@ -0,0 +1,14 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_irq", + srcs = ["irq.c"], + hdrs = ["include/hardware/irq.h"], + includes = ["include"], + tags = ["manual"], # TODO: No hardware/regs/intctrl.h for host yet. + target_compatible_with = ["//bazel/constraint:host"], + deps = [ + "//src/host/hardware_claim", + "//src/host/pico_platform", + ], +) diff --git a/src/host/hardware_irq/CMakeLists.txt b/src/host/hardware_irq/CMakeLists.txt new file mode 100644 index 000000000..7b23468a1 --- /dev/null +++ b/src/host/hardware_irq/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(irq) \ No newline at end of file diff --git a/src/host/hardware_irq/include/hardware/irq.h b/src/host/hardware_irq/include/hardware/irq.h new file mode 100644 index 000000000..83c3a8487 --- /dev/null +++ b/src/host/hardware_irq/include/hardware/irq.h @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_IRQ_H +#define _HARDWARE_IRQ_H + +// These two config items are also used by assembler, so keeping separate +// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq +#ifndef PICO_MAX_SHARED_IRQ_HANDLERS +#define PICO_MAX_SHARED_IRQ_HANDLERS 4 +#endif + +// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq +#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS +#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0 +#endif + +// PICO_CONFIG: PICO_VTABLE_PER_CORE, user is using separate vector tables per core, type=bool, default=0, group=hardware_irq +#ifndef PICO_VTABLE_PER_CORE +#define PICO_VTABLE_PER_CORE 0 +#endif + +#include "pico.h" +#include "hardware/regs/intctrl.h" + +/** \file irq.h + * \defgroup hardware_irq hardware_irq + * + * \brief Hardware interrupt handling + * + * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC). + * + * Interrupts are identified by a number from 0 to 31. + * + * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing). + * + * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts + * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be + * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank. + * + * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function). + * + * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions + * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts + * on the other core. + * + * There are three different ways to set handlers for an IRQ: + * - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source + * - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core + * - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and + * you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used). + * + * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will + * be in register r0. + * + * \section interrupt_nums Interrupt Numbers + * + * Interrupts are numbered as follows, a set of defines is available (intctrl.h) with these names to avoid using the numbers directly. + * + * IRQ | Interrupt Source + * ----|----------------- + * 0 | TIMER_IRQ_0 + * 1 | TIMER_IRQ_1 + * 2 | TIMER_IRQ_2 + * 3 | TIMER_IRQ_3 + * 4 | PWM_IRQ_WRAP + * 5 | USBCTRL_IRQ + * 6 | XIP_IRQ + * 7 | PIO0_IRQ_0 + * 8 | PIO0_IRQ_1 + * 9 | PIO1_IRQ_0 + * 10 | PIO1_IRQ_1 + * 11 | DMA_IRQ_0 + * 12 | DMA_IRQ_1 + * 13 | IO_IRQ_BANK0 + * 14 | IO_IRQ_QSPI + * 15 | SIO_IRQ_PROC0 + * 16 | SIO_IRQ_PROC1 + * 17 | CLOCKS_IRQ + * 18 | SPI0_IRQ + * 19 | SPI1_IRQ + * 20 | UART0_IRQ + * 21 | UART1_IRQ + * 22 | ADC0_IRQ_FIFO + * 23 | I2C0_IRQ + * 24 | I2C1_IRQ + * 25 | RTC_IRQ + * + */ + +// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq +#ifndef PICO_DEFAULT_IRQ_PRIORITY +#define PICO_DEFAULT_IRQ_PRIORITY 0x80 +#endif + +#define PICO_LOWEST_IRQ_PRIORITY 0xff +#define PICO_HIGHEST_IRQ_PRIORITY 0x00 + +// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq +#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY +#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80 +#endif + +#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff +#define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00 + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ +#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0 +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Interrupt handler function type + * \ingroup hardware_irq + * + * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions + */ +typedef void (*irq_handler_t)(void); + +static inline void check_irq_param(__unused uint num) { + invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS); +} + +/*! \brief Set specified interrupt's priority + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \param hardware_priority Priority to set. + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority) though only the + * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * higher or lower priorities than the default, all IRQ priorities are + * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. + * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 + */ +void irq_set_priority(uint num, uint8_t hardware_priority); + +/*! \brief Get specified interrupt's priority + * \ingroup hardware_irq + * + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority) though only the + * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * higher or lower priorities than the default, all IRQ priorities are + * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. + * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 + * + * \param num Interrupt number \ref interrupt_nums + * \return the IRQ priority + */ +uint irq_get_priority(uint num); + +/*! \brief Enable or disable a specific interrupt on the executing core + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \param enabled true to enable the interrupt, false to disable + */ +void irq_set_enabled(uint num, bool enabled); + +/*! \brief Determine if a specific interrupt is enabled on the executing core + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \return true if the interrupt is enabled + */ +bool irq_is_enabled(uint num); + +/*! \brief Enable/disable multiple interrupts on the executing core + * \ingroup hardware_irq + * + * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums + * \param enabled true to enable the interrupts, false to disable them. + */ +void irq_set_mask_enabled(uint32_t mask, bool enabled); + +/*! \brief Enable/disable multiple interrupts on the executing core + * \ingroup hardware_irq + * + * \param n the index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. + * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums + * \param enabled true to enable the interrupts, false to disable them. + */ +void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled); + +/*! \brief Set an exclusive interrupt handler for an interrupt on the executing core. + * \ingroup hardware_irq + * + * Use this method to set a handler for single IRQ source interrupts, or when + * your code, use case or performance requirements dictate that there should + * no other handlers for the interrupt. + * + * This method will assert if there is already any sort of interrupt handler installed + * for the specified irq number. + * + * \param num Interrupt number \ref interrupt_nums + * \param handler The handler to set. See \ref irq_handler_t + * \see irq_add_shared_handler() + */ +void irq_set_exclusive_handler(uint num, irq_handler_t handler); + +/*! \brief Get the exclusive interrupt handler for an interrupt on the executing core. + * \ingroup hardware_irq + * + * This method will return an exclusive IRQ handler set on this core + * by irq_set_exclusive_handler if there is one. + * + * \param num Interrupt number \ref interrupt_nums + * \see irq_set_exclusive_handler() + * \return handler The handler if an exclusive handler is set for the IRQ, + * NULL if no handler is set or shared/shareable handlers are installed + */ +irq_handler_t irq_get_exclusive_handler(uint num); + +/*! \brief Add a shared interrupt handler for an interrupt on the executing core + * \ingroup hardware_irq + * + * Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs). + * Handlers added by this method will all be called in sequence from highest order_priority to lowest. The + * irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt. + * + * This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if + * the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers + * would be exceeded. + * + * \param num Interrupt number \ref interrupt_nums + * \param handler The handler to set. See \ref irq_handler_t + * \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called. + * The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based + * on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good + * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of + * the priority range by default. + * + * \note The order_priority uses \em higher values for higher priorities which is the \em opposite of the CPU interrupt priorities passed + * to irq_set_priority() which use lower values for higher priorities. + * + * \see irq_set_exclusive_handler() + */ +void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority); + +/*! \brief Remove a specific interrupt handler for the given irq number on the executing core + * \ingroup hardware_irq + * + * This method may be used to remove an irq set via either irq_set_exclusive_handler() or + * irq_add_shared_handler(), and will assert if the handler is not currently installed for the given + * IRQ number + * + * \note This method may *only* be called from user (non IRQ code) or from within the handler + * itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call + * from another IRQ will cause an assertion. + * + * \param num Interrupt number \ref interrupt_nums + * \param handler The handler to removed. + * \see irq_set_exclusive_handler() + * \see irq_add_shared_handler() + */ +void irq_remove_handler(uint num, irq_handler_t handler); + +/*! \brief Determine if the current handler for the given number is shared + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \return true if the specified IRQ has a shared handler + */ +bool irq_has_shared_handler(uint num); + +/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR) + * of the execution core + * \ingroup hardware_irq + * + * \param num Interrupt number \ref interrupt_nums + * \return the address stored in the VTABLE for the given irq number + */ +irq_handler_t irq_get_vtable_handler(uint num); + +/*! \brief Clear a specific interrupt on the executing core + * \ingroup hardware_irq + * + * This method is only useful for "software" IRQs that are not connected to hardware (i.e. IRQs 26-31) + * as the the NVIC always reflects the current state of the IRQ state of the hardware for hardware IRQs, and clearing + * of the IRQ state of the hardware is performed via the hardware's registers instead. + * + * \param int_num Interrupt number \ref interrupt_nums + */ +void irq_clear(uint int_num); + +/*! \brief Force an interrupt to be pending on the executing core + * \ingroup hardware_irq + * + * This should generally not be used for IRQs connected to hardware. + * + * \param num Interrupt number \ref interrupt_nums + */ +void irq_set_pending(uint num); + + +/*! \brief Perform IRQ priority initialization for the current core + * + * \note This is an internal method and user should generally not call it. + */ +void irq_init_priorities(void); + +/*! \brief Claim ownership of a user IRQ on the calling core + * \ingroup hardware_irq + * + * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions + * dealing with Uer IRQs affect only the calling core + * + * This method explicitly claims ownership of a user IRQ, so other code can know it is being used. + * + * \param irq_num the user IRQ to claim + */ +void user_irq_claim(uint irq_num); + +/*! \brief Mark a user IRQ as no longer used on the calling core + * \ingroup hardware_irq + * + * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions + * dealing with Uer IRQs affect only the calling core + * + * This method explicitly releases ownership of a user IRQ, so other code can know it is free to use. + * + * \note it is customary to have disabled the irq and removed the handler prior to calling this method. + * + * \param irq_num the irq irq_num to unclaim + */ +void user_irq_unclaim(uint irq_num); + +/*! \brief Claim ownership of a free user IRQ on the calling core + * \ingroup hardware_irq + * + * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions + * dealing with Uer IRQs affect only the calling core + * + * This method explicitly claims ownership of an unused user IRQ if there is one, so other code can know it is being used. + * + * \param required if true the function will panic if none are available + * \return the user IRQ number or -1 if required was false, and none were free + */ +int user_irq_claim_unused(bool required); + +/* +*! \brief Check if a user IRQ is in use on the calling core + * \ingroup hardware_irq + * + * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions + * dealing with Uer IRQs affect only the calling core + * + * \param irq_num the irq irq_num + * \return true if the irq_num is claimed, false otherwise + * \sa user_irq_claim + * \sa user_irq_unclaim + * \sa user_irq_claim_unused + */ +bool user_irq_is_claimed(uint irq_num); + +void __unhandled_user_irq(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/host/hardware_irq/irq.c b/src/host/hardware_irq/irq.c new file mode 100644 index 000000000..ad793c19d --- /dev/null +++ b/src/host/hardware_irq/irq.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/irq.h" +#include "hardware/claim.h" + +// totally non-functional IRQ + +#if PICO_VTABLE_PER_CORE +static uint8_t user_irq_claimed[NUM_CORES]; +static inline uint8_t *user_irq_claimed_ptr(void) { + return &user_irq_claimed[get_core_num()]; +} +#else +static uint8_t user_irq_claimed; +static inline uint8_t *user_irq_claimed_ptr(void) { + return &user_irq_claimed; +} +#endif + +PICO_WEAK_FUNCTION_DEF(irq_set_enabled) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_enabled)(uint num, bool enabled) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_is_enabled) +bool PICO_WEAK_FUNCTION_IMPL_NAME(irq_is_enabled)(uint num) { + return false; +} + +PICO_WEAK_FUNCTION_DEF(irq_set_mask_enabled) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_enabled)(uint32_t mask, bool enabled) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_set_mask_n_enabled) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_n_enabled)(uint n, uint32_t mask, bool enabled) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_set_pending) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_pending)(uint num) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_has_shared_handler) +bool PICO_WEAK_FUNCTION_IMPL_NAME(irq_has_shared_handler)(uint irq_num) { + return false; +} + +PICO_WEAK_FUNCTION_DEF(irq_get_vtable_handler) +irq_handler_t PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_vtable_handler)(uint num) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_set_exclusive_handler) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_exclusive_handler)(uint num, irq_handler_t handler) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_get_exclusive_handler) +irq_handler_t PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_exclusive_handler)(uint num) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_add_shared_handler) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_add_shared_handler)(uint num, irq_handler_t handler, uint8_t order_priority) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_remove_handler) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_remove_handler)(uint num, irq_handler_t handler) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_set_priority) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_priority)(uint num, uint8_t hardware_priority) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_get_priority) +uint PICO_WEAK_FUNCTION_IMPL_NAME(irq_get_priority)(uint num) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_clear) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_clear)(uint int_num) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(irq_init_priorities) +void PICO_WEAK_FUNCTION_IMPL_NAME(irq_init_priorities)() { +} + +static uint get_user_irq_claim_index(uint irq_num) { + invalid_params_if(HARDWARE_IRQ, irq_num < FIRST_USER_IRQ || irq_num >= NUM_IRQS); + // we count backwards from the last, to match the existing hard coded uses of user IRQs in the SDK which were previously using 31 + static_assert(NUM_IRQS - FIRST_USER_IRQ <= 8, ""); // we only use a single byte's worth of claim bits today. + return NUM_IRQS - irq_num - 1u; +} + +PICO_WEAK_FUNCTION_DEF(user_irq_claim) +void PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_claim)(uint irq_num) { + hw_claim_or_assert(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num), "User IRQ is already claimed"); +} + +PICO_WEAK_FUNCTION_DEF(user_irq_unclaim) +void PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_unclaim)(uint irq_num) { + hw_claim_clear(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num)); +} + +PICO_WEAK_FUNCTION_DEF(user_irq_claim_unused) +int PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_claim_unused)(bool required) { + int bit = hw_claim_unused_from_range(user_irq_claimed_ptr(), required, 0, NUM_USER_IRQS - 1, "No user IRQs are available"); + if (bit >= 0) bit = (int)NUM_IRQS - bit - 1; + return bit; +} + +PICO_WEAK_FUNCTION_DEF(user_irq_is_claimed) +bool PICO_WEAK_FUNCTION_IMPL_NAME(user_irq_is_claimed)(uint irq_num) { + return hw_is_claimed(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num)); +} diff --git a/src/host/hardware_sync/BUILD.bazel b/src/host/hardware_sync/BUILD.bazel index f218d3625..0e42fca2d 100644 --- a/src/host/hardware_sync/BUILD.bazel +++ b/src/host/hardware_sync/BUILD.bazel @@ -1,5 +1,15 @@ package(default_visibility = ["//visibility:public"]) +cc_library( + name = "hardware_sync_headers", + srcs = ["sync_core0_only.c"], + hdrs = ["include/hardware/sync.h"], + implementation_deps = ["//src/host/pico_platform:platform_defs"], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:host"], + deps = ["//src/common/pico_base_headers"], +) + cc_library( name = "hardware_sync", srcs = ["sync_core0_only.c"], @@ -7,5 +17,5 @@ cc_library( implementation_deps = ["//src/host/pico_platform:platform_defs"], includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], - deps = ["//src/common/pico_base"], + deps = ["//src/host/pico_platform"], ) diff --git a/src/host/hardware_sync/include/hardware/sync.h b/src/host/hardware_sync/include/hardware/sync.h index 58426f5e2..f31c21630 100644 --- a/src/host/hardware_sync/include/hardware/sync.h +++ b/src/host/hardware_sync/include/hardware/sync.h @@ -26,18 +26,65 @@ static inline void atomic_thread_fence(uint x) {} #endif +/// PICO_CONFIG: PICO_SPINLOCK_ID_ATOMIC, Spinlock ID for atomic protection, min=0, max=31, default=8, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_ATOMIC +#define PICO_SPINLOCK_ID_ATOMIC 8 +#endif + +/// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_IRQ +#define PICO_SPINLOCK_ID_IRQ 9 +#endif + +/// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync #ifndef PICO_SPINLOCK_ID_TIMER #define PICO_SPINLOCK_ID_TIMER 10 #endif +/// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM +#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 +#endif + +/// PICO_CONFIG: PICO_SPINLOCK_ID_RAND, Spinlock ID for Random Number Generator, min=0, max=31, default=12, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_RAND +#define PICO_SPINLOCK_ID_RAND 12 +#endif + +/// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS1 +#define PICO_SPINLOCK_ID_OS1 14 +#endif + +/// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS2 +#define PICO_SPINLOCK_ID_OS2 15 +#endif + +/// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync #ifndef PICO_SPINLOCK_ID_STRIPED_FIRST #define PICO_SPINLOCK_ID_STRIPED_FIRST 16 #endif +/// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync #ifndef PICO_SPINLOCK_ID_STRIPED_LAST #define PICO_SPINLOCK_ID_STRIPED_LAST 23 #endif +/// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST +#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 +#endif + +#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END +#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST +#endif + +/// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST +#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31 +#endif + typedef struct _spin_lock_t spin_lock_t; inline static void __mem_fence_acquire() { @@ -72,6 +119,8 @@ uint32_t save_and_disable_interrupts(); void restore_interrupts(uint32_t status); +void restore_interrupts_from_disabled(uint32_t status); + uint spin_lock_get_num(spin_lock_t *lock); spin_lock_t *spin_lock_instance(uint lock_num); @@ -89,6 +138,7 @@ void spin_unlock(spin_lock_t *lock, uint32_t saved_irq); spin_lock_t *spin_lock_init(uint lock_num); void clear_spin_locks(void); +#define spin_locks_reset() clear_spin_locks() uint next_striped_spin_lock_num(); diff --git a/src/host/hardware_sync/sync_core0_only.c b/src/host/hardware_sync/sync_core0_only.c index 878eba68f..47d0f2f5b 100644 --- a/src/host/hardware_sync/sync_core0_only.c +++ b/src/host/hardware_sync/sync_core0_only.c @@ -26,6 +26,12 @@ PICO_WEAK_FUNCTION_DEF(restore_interrupts) void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts)(uint32_t status) { } +PICO_WEAK_FUNCTION_DEF(restore_interrupts_from_disabled) + +void PICO_WEAK_FUNCTION_IMPL_NAME(restore_interrupts_from_disabled)(uint32_t status) { +} + + PICO_WEAK_FUNCTION_DEF(spin_lock_instance) spin_lock_t *PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_instance)(uint lock_num) { @@ -98,12 +104,6 @@ void PICO_WEAK_FUNCTION_IMPL_NAME(__wfe)() { while (!event_fired) tight_loop_contents(); } -PICO_WEAK_FUNCTION_DEF(get_core_num) - -uint PICO_WEAK_FUNCTION_IMPL_NAME(get_core_num)() { - return 0; -} - PICO_WEAK_FUNCTION_DEF(clear_spin_locks) void PICO_WEAK_FUNCTION_IMPL_NAME(clear_spin_locks)(void) { diff --git a/src/host/hardware_timer/BUILD.bazel b/src/host/hardware_timer/BUILD.bazel index af37e2f46..57bc42555 100644 --- a/src/host/hardware_timer/BUILD.bazel +++ b/src/host/hardware_timer/BUILD.bazel @@ -16,7 +16,7 @@ cc_library( includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], visibility = ["//src/common/pico_time:__pkg__"], - deps = ["//src/common/pico_base:pico_base_interface"], + deps = ["//src/common/pico_base_headers"], ) cc_library( @@ -26,5 +26,5 @@ cc_library( defines = _DEFINES, includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], - deps = ["//src/common/pico_base"], + deps = ["//src/host/pico_platform"], ) diff --git a/src/host/hardware_timer/include/hardware/timer.h b/src/host/hardware_timer/include/hardware/timer.h index 1c070d374..6bb592321 100644 --- a/src/host/hardware_timer/include/hardware/timer.h +++ b/src/host/hardware_timer/include/hardware/timer.h @@ -13,19 +13,24 @@ extern "C" { #endif - -#ifndef PARAM_ASSERTIONS_ENABLED_TIMER -#define PARAM_ASSERTIONS_ENABLED_TIMER 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER, Enable/disable assertions in the hardware_timer module, type=bool, default=0, group=hardware_timer +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER +#ifdef PARAM_ASSERTIONS_ENABLED_TIMER // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER PARAM_ASSERTIONS_ENABLED_TIMER +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER 0 +#endif #endif static inline void check_hardware_alarm_num_param(uint alarm_num) { - invalid_params_if(TIMER, alarm_num >= NUM_TIMERS); + invalid_params_if(HARDWARE_TIMER, alarm_num >= NUM_ALARMS); } uint32_t time_us_32(); uint64_t time_us_64(); void busy_wait_us_32(uint32_t delay_us); void busy_wait_us(uint64_t delay_us); +void busy_wait_ms(uint32_t delay_m); void busy_wait_until(absolute_time_t t); bool time_reached(absolute_time_t t); typedef void (*hardware_alarm_callback_t)(uint alarm_num); diff --git a/src/host/hardware_timer/timer.c b/src/host/hardware_timer/timer.c index 3ae825e36..a110be27e 100644 --- a/src/host/hardware_timer/timer.c +++ b/src/host/hardware_timer/timer.c @@ -99,7 +99,7 @@ void hardware_alarm_unclaim(uint alarm_num) { int hardware_alarm_claim_unused(bool required) { int alarm_id = claimed_alarms ? __builtin_clz(~claimed_alarms) : 1; - if (alarm_id >= NUM_TIMERS) return -1; + if (alarm_id >= NUM_ALARMS) return -1; claimed_alarms |= 1u << alarm_id; return alarm_id; } diff --git a/src/host/hardware_uart/BUILD.bazel b/src/host/hardware_uart/BUILD.bazel index 5288d1402..1e0c49686 100644 --- a/src/host/hardware_uart/BUILD.bazel +++ b/src/host/hardware_uart/BUILD.bazel @@ -6,5 +6,5 @@ cc_library( hdrs = ["include/hardware/uart.h"], includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], - deps = ["//src/common/pico_base"], + deps = ["//src/host/pico_platform"], ) diff --git a/src/host/hardware_uart/include/hardware/uart.h b/src/host/hardware_uart/include/hardware/uart.h index 0c5e890ad..b0fa974bc 100644 --- a/src/host/hardware_uart/include/hardware/uart.h +++ b/src/host/hardware_uart/include/hardware/uart.h @@ -9,8 +9,13 @@ #include "pico.h" -#ifndef PARAM_ASSERTIONS_ENABLED_UART -#define PARAM_ASSERTIONS_ENABLED_UART 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_UART, Enable/disable assertions in the hardware_uart module, type=bool, default=0, group=hardware_uart +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_UART +#ifdef PARAM_ASSERTIONS_ENABLED_UART // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART PARAM_ASSERTIONS_ENABLED_UART +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART 0 +#endif #endif #ifdef __cplusplus @@ -51,18 +56,18 @@ void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts); void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity); // Enable the UART's interrupt output. Need to install an interrupt handler first. -void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data); +void uart_set_irqs_enabled(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data); // ---------------------------------------------------------------------------- // Generic input/output // If returns 0, no space is available in the UART to write more data. // If returns nonzero, at least that many bytes can be written without blocking. -size_t uart_is_writable(uart_inst_t *uart); +bool uart_is_writable(uart_inst_t *uart); // If returns 0, no data is available to be read from UART. // If returns nonzero, at least that many bytes can be written without blocking. -size_t uart_is_readable(uart_inst_t *uart); +bool uart_is_readable(uart_inst_t *uart); // Write len bytes directly from src to the UART void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len); @@ -75,6 +80,8 @@ void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len); void uart_putc(uart_inst_t *uart, char c); +void uart_putc_raw(uart_inst_t *uart, char c); + void uart_puts(uart_inst_t *uart, const char *s); char uart_getc(uart_inst_t *uart); @@ -84,6 +91,8 @@ void uart_set_break(uart_inst_t *uart, bool en); void uart_default_tx_wait_blocking(); +#define UART_FUNCSEL_NUM(uart, gpio) 0 + #ifdef __cplusplus } #endif diff --git a/src/host/hardware_uart/uart.c b/src/host/hardware_uart/uart.c index e61040283..066714547 100644 --- a/src/host/hardware_uart/uart.c +++ b/src/host/hardware_uart/uart.c @@ -77,13 +77,13 @@ uint uart_init(uart_inst_t *uart, uint baud_rate) { return baud_rate; } -size_t uart_is_writable(uart_inst_t *uart) { +bool uart_is_writable(uart_inst_t *uart) { return 1; } // If returns 0, no data is available to be read from UART. // If returns nonzero, at least that many bytes can be written without blocking. -size_t uart_is_readable(uart_inst_t *uart) { +bool uart_is_readable(uart_inst_t *uart) { return _peekchar() ? 1 : 0; } @@ -108,6 +108,10 @@ void uart_putc(uart_inst_t *uart, char c) { putchar(c); } +void uart_putc_raw(uart_inst_t *uart, char c) { + putchar(c); +} + void uart_puts(uart_inst_t *uart, const char *s) { puts(s); } diff --git a/src/host/pico_bit_ops/BUILD.bazel b/src/host/pico_bit_ops/BUILD.bazel index a0e7dc48f..2b2419f67 100644 --- a/src/host/pico_bit_ops/BUILD.bazel +++ b/src/host/pico_bit_ops/BUILD.bazel @@ -3,6 +3,6 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "pico_bit_ops", srcs = ["bit_ops.c"], - implementation_deps = ["//src/common/pico_bit_ops:pico_bit_ops_headers"], target_compatible_with = ["//bazel/constraint:host"], + deps = ["//src/common/pico_bit_ops_headers:pico_bit_ops_interface"], ) diff --git a/src/host/pico_divider/BUILD.bazel b/src/host/pico_divider/BUILD.bazel index e82785f6c..e97563fd8 100644 --- a/src/host/pico_divider/BUILD.bazel +++ b/src/host/pico_divider/BUILD.bazel @@ -3,6 +3,9 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "pico_divider", srcs = ["divider.c"], - implementation_deps = ["//src/common/pico_divider"], target_compatible_with = ["//bazel/constraint:host"], + deps = [ + "//src/common/pico_divider_headers", + "//src/host/hardware_divider", + ], ) diff --git a/src/host/pico_divider/divider.c b/src/host/pico_divider/divider.c index 25ede84b3..709e3bba8 100644 --- a/src/host/pico_divider/divider.c +++ b/src/host/pico_divider/divider.c @@ -99,7 +99,7 @@ uint64_t divmod_u64u64(uint64_t a, uint64_t b) { int32_t div_s32s32_unsafe(int32_t a, int32_t b) { return div_s32s32(a,b); } int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem) { return divmod_s32s32_rem(a, b, rem); } -int64_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); } +divmod_result_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); } uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b) { return div_u32u32(a, b); } uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem) { return divmod_u32u32_rem(a, b, rem); } diff --git a/src/host/pico_multicore/BUILD.bazel b/src/host/pico_multicore/BUILD.bazel index 61b109233..b837fb5de 100644 --- a/src/host/pico_multicore/BUILD.bazel +++ b/src/host/pico_multicore/BUILD.bazel @@ -5,5 +5,5 @@ cc_library( hdrs = ["include/pico/multicore.h"], includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], - deps = ["//src/common/pico_base"], + deps = ["//src/host/pico_platform"], ) diff --git a/src/host/pico_multicore/CMakeLists.txt b/src/host/pico_multicore/CMakeLists.txt index 8b9fc0688..f72d25c84 100644 --- a/src/host/pico_multicore/CMakeLists.txt +++ b/src/host/pico_multicore/CMakeLists.txt @@ -1,7 +1,7 @@ if (NOT TARGET pico_multicore) pico_add_library(pico_multicore) - target_include_directories(pico_multicore_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_multicore_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_multicore INTERFACE pico_base) endif() diff --git a/src/host/pico_platform/BUILD.bazel b/src/host/pico_platform/BUILD.bazel index d89fd3af8..610a38352 100644 --- a/src/host/pico_platform/BUILD.bazel +++ b/src/host/pico_platform/BUILD.bazel @@ -9,16 +9,26 @@ cc_library( target_compatible_with = ["//bazel/constraint:host"], ) +# Resolves circular dependencies. cc_library( - name = "pico_platform", - srcs = ["platform_base.c"], + name = "pico_platform_internal", hdrs = [ "include/pico/platform.h", ], includes = ["include"], + visibility = ["//src:__pkg__"], + deps = [ + ":platform_defs", + ], +) + +cc_library( + name = "pico_platform", + srcs = ["platform_base.c"], target_compatible_with = ["//bazel/constraint:host"], deps = [ + ":pico_platform_internal", ":platform_defs", - "//src/common/pico_base:pico_base_interface", + "//src/common/pico_base_headers", ], ) diff --git a/src/host/pico_platform/CMakeLists.txt b/src/host/pico_platform/CMakeLists.txt index c78e330bc..116995362 100644 --- a/src/host/pico_platform/CMakeLists.txt +++ b/src/host/pico_platform/CMakeLists.txt @@ -9,7 +9,7 @@ if (NOT TARGET pico_platform_headers) PICO_BUILD=1 ) - target_include_directories(pico_platform_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_platform_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) endif() if (NOT TARGET pico_platform) diff --git a/src/host/pico_platform/include/hardware/platform_defs.h b/src/host/pico_platform/include/hardware/platform_defs.h index 95952ba05..924336a92 100644 --- a/src/host/pico_platform/include/hardware/platform_defs.h +++ b/src/host/pico_platform/include/hardware/platform_defs.h @@ -11,16 +11,19 @@ #define NUM_DMA_CHANNELS 12u -#define NUM_TIMERS 4u +#define NUM_GENERIC_TIMERS 1u +#define NUM_ALARMS 4u #define NUM_IRQS 32u #define NUM_SPIN_LOCKS 32u -#define XOSC_KHZ 12000u +#define XOSC_HZ 12000000u #define NUM_SPIN_LOCKS 32u +#define NUM_BANK0_GPIOS 30 + #ifndef _u #define _u(x) x ## u #endif diff --git a/src/host/pico_platform/include/pico/platform.h b/src/host/pico_platform/include/pico/platform.h index f9a7308bb..dca69f265 100644 --- a/src/host/pico_platform/include/pico/platform.h +++ b/src/host/pico_platform/include/pico/platform.h @@ -67,6 +67,9 @@ extern void tight_loop_contents(); #define PICO_WEAK_FUNCTION_DEF(x) _Pragma(__STRING(weak x)) #define PICO_WEAK_FUNCTION_IMPL_NAME(x) x +#ifndef __weak +#define __weak __attribute__((weak)) +#endif #else #ifndef __noreturn #define __noreturn __declspec(noreturn) diff --git a/src/host/pico_platform/platform_base.c b/src/host/pico_platform/platform_base.c index be1dbd444..25acbf1db 100644 --- a/src/host/pico_platform/platform_base.c +++ b/src/host/pico_platform/platform_base.c @@ -14,12 +14,14 @@ void PICO_WEAK_FUNCTION_IMPL_NAME(tight_loop_contents)() { } -void __noreturn panic_unsupported() { - panic("not supported"); + +PICO_WEAK_FUNCTION_DEF(get_core_num) +uint PICO_WEAK_FUNCTION_IMPL_NAME(get_core_num)() { + return 0; } -void hard_assertion_failure(void) { - panic("Hard assert"); +void __noreturn panic_unsupported() { + panic("not supported"); } void panic(const char *fmt, ...) { diff --git a/src/host/pico_runtime/BUILD.bazel b/src/host/pico_runtime/BUILD.bazel new file mode 100644 index 000000000..a988f00e4 --- /dev/null +++ b/src/host/pico_runtime/BUILD.bazel @@ -0,0 +1,17 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_runtime", + srcs = ["runtime.c"], + hdrs = [ + "include/pico/runtime.h", + "include/pico/runtime_init.h", + ], + copts = select({ + "@platforms//os:windows": [], # TODO: MSVC flags. + "//conditions:default": ["-Wno-ignored-attributes"], + }), + includes = ["include"], + target_compatible_with = ["//bazel/constraint:host"], + deps = ["//src/host/pico_platform"], +) diff --git a/src/host/pico_runtime/CMakeLists.txt b/src/host/pico_runtime/CMakeLists.txt new file mode 100644 index 000000000..da9a8a47e --- /dev/null +++ b/src/host/pico_runtime/CMakeLists.txt @@ -0,0 +1,7 @@ +pico_add_library(pico_runtime) + +target_include_directories(pico_runtime_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +pico_mirrored_target_link_libraries(pico_runtime INTERFACE + pico_base +) \ No newline at end of file diff --git a/src/host/pico_runtime/include/pico/runtime.h b/src/host/pico_runtime/include/pico/runtime.h new file mode 100644 index 000000000..90d83f5a0 --- /dev/null +++ b/src/host/pico_runtime/include/pico/runtime.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_RUNTIME_H +#define _PICO_RUNTIME_H + +#include "pico.h" + +/** \file runtime.h +* \defgroup pico_runtime pico_runtime +* \brief Basic runtime support for running pre-main initializers provided by other libraries +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PICO_RUNTIME_INIT_TYPE_HW 0 +#define PICO_RUNTIME_INIT_TYPE_RUNTIME 1 +#define PICO_RUNTIME_INIT_TYPE_PER_CORE 2 + +#ifndef PICO_RUNTIME_INIT_FUNC_FLAGS +#define PICO_RUNTIME_INIT_FUNC_FLAGS(func, flags, priority_string1, priority_string2) +#endif +#define PICO_RUNTIME_INIT_FUNC_HW(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_HW, priority_string1, priority_string2) +#define PICO_RUNTIME_INIT_FUNC_RUNTIME(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_RUNTIME, priority_string1, priority_string2) +#define PICO_RUNTIME_INIT_FUNC_PER_CORE(func, priority_string1, priority_string2) PICO_RUNTIME_INIT_FUNC_FLAGS(func, PICO_RUNTIME_INIT_TYPE_PER_CORE, priority_string1, priority_string2) + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/host/pico_runtime/include/pico/runtime_init.h b/src/host/pico_runtime/include/pico/runtime_init.h new file mode 100644 index 000000000..9cccc27bb --- /dev/null +++ b/src/host/pico_runtime/include/pico/runtime_init.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_RUNTIME_INIT_H +#define _PICO_RUNTIME_INIT_H + +#include "pico.h" +#include "pico/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * The runtime initialization is registration based. + * + * For each step of the initialization there is a 5 digit ordinal which indicates + * the ordering (alphabetic increasing sort of the 5 digits) of the steps. + * + * e.g. for the step "bootrom_reset", there is: + * + * \code + * #ifndef PICO_RUNTIME_INIT_BOOTROM_RESET + * #define PICO_RUNTIME_INIT_BOOTROM_RESET "00050" + * #endif + * \endcode + * + * The user can override the order if they wish, by redefining PICO_RUNTIME_INIT_BOOTROM_RESET + * + * For each step, the automatic initialization may be skipped by defining (in this case) + * PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET = 1. The user can then choose to either omit the step + * completely or register their own replacement initialization. + * + * The default method used to perform the initialization is provided, in case the user + * wishes to call it manually; in this case: + * + * \code + * void runtime_init_bootrom_reset(void); + * \endcode + * + * If PICO_RUNTIME_NO_INIT_BOOTOROM_RESET define is set (NO vs SKIP above), then the function + * is not defined, allowing the user to provide a replacement (and also avoiding + * cases where the default implementation won't compile due to missing dependencies) + */ + +// must have no dependency on any other initialization code +#define PICO_RUNTIME_INIT_EARLIEST "00001" + +#define PICO_RUNTIME_INIT_LATEST "99999" + +// not supported on host at, (needs custom section) +#define PICO_RUNTIME_NO_INIT_MUTEX 1 + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/host/pico_runtime/runtime.c b/src/host/pico_runtime/runtime.c new file mode 100644 index 000000000..02d82daf8 --- /dev/null +++ b/src/host/pico_runtime/runtime.c @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/runtime.h" + +void __weak hard_assertion_failure(void) { + panic("Hard assert"); +} diff --git a/src/host/pico_stdio/BUILD.bazel b/src/host/pico_stdio/BUILD.bazel index abdc993bf..2866130b6 100644 --- a/src/host/pico_stdio/BUILD.bazel +++ b/src/host/pico_stdio/BUILD.bazel @@ -1,13 +1,29 @@ package(default_visibility = ["//visibility:public"]) +cc_library( + name = "pico_stdio_headers", + hdrs = ["include/pico/stdio.h"], + defines = ["LIB_PICO_STDIO=1"], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:host"], + visibility = [ + "//src/host/pico_stdlib:__pkg__", + ], +) + cc_library( name = "pico_stdio", srcs = ["stdio.c"], - hdrs = ["include/pico/stdio.h"], implementation_deps = [ - "//src/common/pico_stdlib:pico_stdlib_interface", "//src/host/hardware_uart", ], - includes = ["include"], target_compatible_with = ["//bazel/constraint:host"], + deps = [ + ":pico_stdio_headers", + "//src/common/pico_stdlib_headers", + "//src/common/pico_time", + "//src/host/hardware_gpio", + "//src/host/hardware_uart", + "//src/host/pico_platform", + ], ) diff --git a/src/host/pico_stdio/CMakeLists.txt b/src/host/pico_stdio/CMakeLists.txt index e05bfb918..9c65d1fbe 100644 --- a/src/host/pico_stdio/CMakeLists.txt +++ b/src/host/pico_stdio/CMakeLists.txt @@ -1,7 +1,7 @@ if (NOT TARGET pico_stdio) pico_add_library(pico_stdio) - target_include_directories(pico_stdio_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_stdio_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_sources(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdio.c diff --git a/src/host/pico_stdlib/BUILD.bazel b/src/host/pico_stdlib/BUILD.bazel index 245f6939f..225cb881c 100644 --- a/src/host/pico_stdlib/BUILD.bazel +++ b/src/host/pico_stdlib/BUILD.bazel @@ -3,9 +3,12 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "pico_stdlib", srcs = ["stdlib.c"], - implementation_deps = [ - "//src/common/pico_stdlib:pico_stdlib_interface", + target_compatible_with = ["//bazel/constraint:host"], + deps = [ + "//src/common/pico_time", + "//src/host/hardware_gpio", + "//src/host/hardware_uart", + "//src/host/pico_platform", "//src/host/pico_stdio", ], - target_compatible_with = ["//bazel/constraint:host"], ) diff --git a/src/host/pico_stdlib/CMakeLists.txt b/src/host/pico_stdlib/CMakeLists.txt index 49ed2dae9..157365322 100644 --- a/src/host/pico_stdlib/CMakeLists.txt +++ b/src/host/pico_stdlib/CMakeLists.txt @@ -12,6 +12,7 @@ if (NOT TARGET pico_stdlib) pico_divider pico_binary_info pico_printf + pico_runtime pico_stdio hardware_gpio hardware_uart diff --git a/src/host/pico_time_adapter/BUILD.bazel b/src/host/pico_time_adapter/BUILD.bazel new file mode 100644 index 000000000..9b4b963bf --- /dev/null +++ b/src/host/pico_time_adapter/BUILD.bazel @@ -0,0 +1,14 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_time_adapter", + srcs = ["time_adapter.c"], + hdrs = ["include/pico/time_adapter.h"], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:host"], + deps = [ + "//src/common/pico_time:pico_time_headers", + "//src/host/pico_platform", + ], + alwayslink = True, +) diff --git a/src/host/pico_time_adapter/CMakeLists.txt b/src/host/pico_time_adapter/CMakeLists.txt new file mode 100644 index 000000000..4f2442ebf --- /dev/null +++ b/src/host/pico_time_adapter/CMakeLists.txt @@ -0,0 +1,9 @@ +pico_add_library(pico_time_adapter) + +target_sources(pico_time_adapter INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/time_adapter.c +) + +target_include_directories(pico_time_adapter_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +pico_mirrored_target_link_libraries(pico_time INTERFACE pico_time_adapter) \ No newline at end of file diff --git a/src/host/pico_time_adapter/include/pico/time_adapter.h b/src/host/pico_time_adapter/include/pico/time_adapter.h new file mode 100644 index 000000000..14475c72e --- /dev/null +++ b/src/host/pico_time_adapter/include/pico/time_adapter.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_TIME_ADAPTER_H +#define _PICO_TIME_ADAPTER_H + +#ifndef TA_NUM_TIMERS +#define TA_NUM_TIMERS 1 +#endif + +#ifndef TA_NUM_TIMER_ALARMS +#define TA_NUM_TIMER_ALARMS 4 +#endif + +void ta_clear_force_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num); +void ta_clear_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num); +void ta_force_irq(alarm_pool_timer_t *timer, uint hardware_alarm_num); +void ta_set_timeout(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target); +void ta_enable_irq_handler(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)); +void ta_disable_irq_handler(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)); +void ta_hardware_alarm_claim(alarm_pool_timer_t *timer, uint hardware_alarm_num); +int ta_hardware_alarm_claim_unused(alarm_pool_timer_t *timer, bool required); +alarm_pool_timer_t *ta_from_current_irq(uint *alarm_num); +uint ta_timer_num(alarm_pool_timer_t *timer); +static inline uint64_t ta_time_us_64(__unused alarm_pool_timer_t *timer) { + return time_us_64(); +} +alarm_pool_timer_t *ta_timer_instance(uint instance_num); +alarm_pool_timer_t *ta_default_timer_instance(void); + +#endif diff --git a/src/host/pico_time_adapter/time_adapter.c b/src/host/pico_time_adapter/time_adapter.c new file mode 100644 index 000000000..1a5d7085f --- /dev/null +++ b/src/host/pico_time_adapter/time_adapter.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/time.h" +#include "pico/time_adapter.h" + +PICO_WEAK_FUNCTION_DEF(ta_clear_force_irq) +void PICO_WEAK_FUNCTION_IMPL_NAME(ta_clear_force_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_clear_irq) +void PICO_WEAK_FUNCTION_IMPL_NAME(ta_clear_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_force_irq) +void PICO_WEAK_FUNCTION_IMPL_NAME(ta_force_irq)(alarm_pool_timer_t *timer, uint hardware_alarm_num) { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_get_handler_hardware_alarm_num) +int PICO_WEAK_FUNCTION_IMPL_NAME(ta_get_handler_hardware_alarm_num)() { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_set_timeout) +void PICO_WEAK_FUNCTION_IMPL_NAME(ta_set_timeout)(alarm_pool_timer_t *timer, uint hardware_alarm_num, int64_t target) { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_enable_irq_handler) +void PICO_WEAK_FUNCTION_IMPL_NAME(ta_enable_irq_handler)(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)) { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_disable_irq_handler) +void PICO_WEAK_FUNCTION_IMPL_NAME(ta_disable_irq_handler)(alarm_pool_timer_t *timer, uint hardware_alarm_num, void (*irq_handler)(void)) { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_hardware_alarm_claim) +void PICO_WEAK_FUNCTION_IMPL_NAME(ta_hardware_alarm_claim)(alarm_pool_timer_t *timer, uint hardware_alaram_num) { + panic_unsupported(); +} +PICO_WEAK_FUNCTION_DEF(ta_hardware_alarm_claim_unused) +int PICO_WEAK_FUNCTION_IMPL_NAME(ta_hardware_alarm_claim_unused)(alarm_pool_timer_t *timer, bool required) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(ta_from_current_irq); +alarm_pool_timer_t *PICO_WEAK_FUNCTION_IMPL_NAME(ta_from_current_irq)(uint *alarm_num) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(ta_timer_num); +uint ta_timer_num(alarm_pool_timer_t *timer) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(ta_timer_instance); +alarm_pool_timer_t *ta_timer_instance(uint instance_num) { + panic_unsupported(); +} + +PICO_WEAK_FUNCTION_DEF(ta_default_timer_instance); +alarm_pool_timer_t *ta_default_timer_instance(void) { + panic_unsupported(); + +} + diff --git a/src/rp2040.cmake b/src/rp2040.cmake index c68df450a..a0d97f4fc 100644 --- a/src/rp2040.cmake +++ b/src/rp2040.cmake @@ -1,6 +1,17 @@ # include everything needed to build against rp2040 -include(rp2_common.cmake) +set(RP2_VARIANT_DIR ${CMAKE_CURRENT_LIST_DIR}/rp2040) +set(PICO_RP2040 "1" CACHE INTERNAL "") +set(PICO_RP2350 "0" CACHE INTERNAL "") +set(PICO_RISCV "0" CACHE INTERNAL "") +set(PICO_ARM "1" CACHE INTERNAL "") +set(PICO_CMSIS_DEVICE "RP2040" CACHE INTERNAL "") +set(PICO_DEFAULT_FLASH_SIZE_BYTES "2 * 1024 * 1024") -add_subdirectory(rp2040) +pico_add_doxygen_pre_define("PICO_RP2040=1") +pico_add_doxygen_pre_define("PICO_RP2350=0") +#pico_add_doxygen_pre_define("NUM_DOORBELLS=0") # we have functions that are gated by this +pico_add_doxygen_enabled_section(rp2040_specific) + +include(cmake/rp2_common.cmake) diff --git a/src/rp2040/CMakeLists.txt b/src/rp2040/CMakeLists.txt deleted file mode 100644 index a19ea5ceb..000000000 --- a/src/rp2040/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Targets specific to B0 silicon -pico_add_subdirectory(hardware_regs) -pico_add_subdirectory(hardware_structs) - -pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) -pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/hardware_regs) # very very big - -pico_promote_common_scope_vars() \ No newline at end of file diff --git a/src/rp2040/README.md b/src/rp2040/README.md index b705b35a9..06b86be59 100644 --- a/src/rp2040/README.md +++ b/src/rp2040/README.md @@ -1,5 +1,4 @@ -This directory contains header files defining the RP2040 hardware. It is selected when -`PICO_PLATFORM=rp2040` (the default) is specified for the build +This directory contains files specific to the RP2040 hardware. It is only used when building for the RP2040 platforms i.e. `PICO_PLATFORM=rp2040` `hardware_regs` contains low level hardware register #defines autogenerated from the RP2040 chip definition itself. diff --git a/src/rp2_common/boot_stage2/BUILD.bazel b/src/rp2040/boot_stage2/BUILD.bazel similarity index 85% rename from src/rp2_common/boot_stage2/BUILD.bazel rename to src/rp2040/boot_stage2/BUILD.bazel index 1edd11504..65c9e76b2 100644 --- a/src/rp2_common/boot_stage2/BUILD.bazel +++ b/src/rp2040/boot_stage2/BUILD.bazel @@ -1,7 +1,9 @@ +# Always include these libraries through //src/rp2_common:*! +# This ensures that you'll get the right headers for the MCU you're targeting. + load("@bazel_skylib//rules:copy_file.bzl", "copy_file") load("@bazel_skylib//rules:run_binary.bzl", "run_binary") load("@rules_python//python:defs.bzl", "py_binary") -load("//bazel:defs.bzl", "compatible_with_rp2") load("//bazel/toolchain:objcopy.bzl", "objcopy_to_bin") load("//bazel/util:multiple_choice_flag.bzl", "declare_flag_choices", "flag_choice") load("//bazel/util:transition.bzl", "rp2040_bootloader_binary") @@ -47,7 +49,7 @@ cc_library( "asminclude", "include", ], - target_compatible_with = compatible_with_rp2(), + target_compatible_with = ["//bazel/constraint:rp2040"], visibility = ["//visibility:public"], ) @@ -65,6 +67,7 @@ filegroup( ":__pkg__", BOOT2_CHOICE_FILE_MAP, )), + visibility = ["//src/rp2_common:__pkg__"], ) cc_binary( @@ -76,18 +79,19 @@ cc_binary( linkopts = [ "-Wl,--no-gc-sections", "-nostartfiles", + "-Wl,--entry=_stage2_boot", "-T$(location boot_stage2.ld)", ], # this does nothing if someone passes --custom_malloc, so the # rp2040_bootloader_binary transition forcibly clobbers --custom_malloc. malloc = "//bazel:empty_cc_lib", tags = ["manual"], # Only build as an explicit dependency. - target_compatible_with = compatible_with_rp2(), + target_compatible_with = ["//bazel/constraint:rp2040"], deps = [ "boot_stage2.ld", ":config", - "//src/common/pico_base:pico_base_interface", - "//src/common/pico_base:pico_platform", + "//src/common/pico_base_headers", + "//src/rp2_common:pico_platform_internal", ], ) @@ -101,7 +105,7 @@ objcopy_to_bin( name = "boot_stage2_bin", src = ":boot_stage2_elf", out = "boot_stage2.bin", - target_compatible_with = compatible_with_rp2(), + target_compatible_with = ["//bazel/constraint:rp2040"], ) # WORKAROUND: Python rules always require a .py extension. @@ -127,15 +131,15 @@ run_binary( "$(location boot_stage2_bin)", "$(location boot_stage2.S)", ], - target_compatible_with = compatible_with_rp2(), + target_compatible_with = ["//bazel/constraint:rp2040"], tool = ":pad_checksum_tool", ) cc_library( name = "boot_stage2", srcs = [":boot_stage2_padded"], - target_compatible_with = compatible_with_rp2(), - visibility = ["//visibility:public"], + target_compatible_with = ["//bazel/constraint:rp2040"], + visibility = ["//src/rp2_common:__pkg__"], # This isn't referenced as a symbol, so alwayslink is required to ensure # it doesn't get dropped before the linker script can find it. alwayslink = True, diff --git a/src/rp2_common/boot_stage2/CMakeLists.txt b/src/rp2040/boot_stage2/CMakeLists.txt similarity index 94% rename from src/rp2_common/boot_stage2/CMakeLists.txt rename to src/rp2040/boot_stage2/CMakeLists.txt index 26363734d..c5768785b 100644 --- a/src/rp2_common/boot_stage2/CMakeLists.txt +++ b/src/rp2040/boot_stage2/CMakeLists.txt @@ -1,5 +1,5 @@ # PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, type=string, group=build -# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the file is src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, type=string, default=compile_time_choice, group=build +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the latter is set to src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, type=string, default=compile_time_choice, group=build if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) @@ -31,7 +31,7 @@ pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE) set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") add_library(boot_stage2_headers INTERFACE) -target_include_directories(boot_stage2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(boot_stage2_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) # by convention the first source file name without extension is used for the binary info name function(pico_define_boot_stage2 NAME SOURCES) diff --git a/src/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S b/src/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S similarity index 100% rename from src/rp2_common/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S rename to src/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S diff --git a/src/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S b/src/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S similarity index 100% rename from src/rp2_common/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S rename to src/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S diff --git a/src/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S b/src/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S similarity index 100% rename from src/rp2_common/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S rename to src/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S diff --git a/src/rp2040/boot_stage2/boot2_at25sf128a.S b/src/rp2040/boot_stage2/boot2_at25sf128a.S new file mode 100644 index 000000000..72f751ed9 --- /dev/null +++ b/src/rp2040/boot_stage2/boot2_at25sf128a.S @@ -0,0 +1,282 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Adesto AT25SF128A +// Based on W25Q080 code: main difference is the QE bit is being set +// via command 0x31 +// +// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode +// +// Details: * Check status register 2 to determine if QSPI mode is enabled, +// and perform an SR2 programming cycle if necessary. +// * Use SSI to perform a dummy 0xEB read command, with the mode +// continuation bits set, so that the flash will not require +// 0xEB instruction prefix on subsequent reads. +// * Configure SSI to write address, mode bits, but no instruction. +// SSI + flash are now jointly in a state where continuous reads +// can take place. +// * Jump to exit pointer passed in via lr. Bootrom passes null, +// in which case this code uses a default 256 byte flash offset +// +// Building: * This code must be position-independent, and use stack only +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" +#include "hardware/regs/pads_qspi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive, even integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif +#if PICO_FLASH_SPI_CLKDIV & 1 +#error PICO_FLASH_SPI_CLKDIV must be even +#endif + +// Define interface width: single/dual/quad IO +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD + +// For W25Q080 this is the "Read data fast quad IO" instruction: +#define CMD_READ 0xeb + +// "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Quad I/O" command sequence. +// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the +// next read does not require the 0xeb instruction prefix. +#define MODE_CONTINUOUS_READ 0x20 + +// The number of address + mode bits, divided by 4 (always 4, not function of +// interface width). +#define ADDR_L 8 + +// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles +// are required. +#define WAIT_CYCLES 4 + +// If defined, we will read status reg, compare to SREG_DATA, and overwrite +// with our value if the SR doesn't match. +// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to +// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. +// This isn't great because it will remove block protections. +// A better solution is to use a volatile SR write if your device supports it. +#define PROGRAM_STATUS_REG + +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS 0x05 +#define CMD_READ_STATUS2 0x35 +#define CMD_WRITE_STATUS 0x01 +#define CMD_WRITE_STATUS2 0x31 +#define SREG_DATA 0x02 // Enable quad-SPI mode + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +pico_default_asm_setup + +.section .text + +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot + push {lr} + + // Set pad configuration: + // - SCLK 8mA drive, no slew limiting + // - SDx disable input Schmitt to reduce delay + + ldr r3, =PADS_QSPI_BASE + movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS) + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] + ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS + bics r0, r1 + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] + + ldr r3, =XIP_SSI_BASE + + // Disable SSI to allow further config + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Set baud rate + movs r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] + + // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means, + // if the flash launches data on SCLK posedge, we capture it at the time that + // the next SCLK posedge is launched. This is shortly before that posedge + // arrives at the flash, so data hold time should be ok. For + // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect. + + movs r1, #1 + movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance + str r1, [r3, r2] + + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: +#define CTRL0_SPI_TXRX \ + (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ + (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRL0_SPI_TXRX) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + // Enable SSI and select slave 0 + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Check whether SR needs updating + movs r0, #CMD_READ_STATUS2 + bl read_flash_sreg + movs r2, #SREG_DATA + cmp r0, r2 + beq skip_sreg_programming + + // Send write enable command + movs r1, #CMD_WRITE_ENABLE + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Send status write command followed by data bytes + movs r1, #CMD_WRITE_STATUS2 + str r1, [r3, #SSI_DR0_OFFSET] + str r2, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Poll status register for write completion +1: + movs r0, #CMD_READ_STATUS + bl read_flash_sreg + movs r1, #1 + tst r0, r1 + bne 1b + +skip_sreg_programming: + + // Disable SSI again so that it can be reconfigured + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] +#endif + +// Currently the flash expects an 8 bit serial command prefix on every +// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O +// command, with mode bits set such that the flash will not expect a serial +// command prefix on *subsequent* transfers. We don't care about the results +// of the read, the important part is the mode bits. + +dummy_read: +#define CTRLR0_ENTER_XIP \ + (FRAME_FORMAT /* Quad I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + movs r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#define SPI_CTRLR0_ENTER_XIP \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + movs r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + movs r1, #CMD_READ + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + + // Poll for completion + bl wait_ssi_ready + +// The flash is in a state where we can blast addresses in parallel, and get +// parallel data back. Now configure the SSI to translate XIP bus accesses +// into QSPI transfers of this form. + + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD +configure_ssi: +#define SPI_CTRLR0_XIP \ + (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// Bus accesses to the XIP window will now be transparently serviced by the +// external flash on cache miss. We are ready to run code from flash. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +// Common functions +#include "boot2_helpers/wait_ssi_ready.S" +#ifdef PROGRAM_STATUS_REG +#include "boot2_helpers/read_flash_sreg.S" +#endif + +.global literals +literals: +.ltorg + +.end diff --git a/src/rp2_common/boot_stage2/boot2_generic_03h.S b/src/rp2040/boot_stage2/boot2_generic_03h.S similarity index 90% rename from src/rp2_common/boot_stage2/boot2_generic_03h.S rename to src/rp2040/boot_stage2/boot2_generic_03h.S index 3c8715f07..effef930b 100644 --- a/src/rp2_common/boot_stage2/boot2_generic_03h.S +++ b/src/rp2040/boot_stage2/boot2_generic_03h.S @@ -57,6 +57,13 @@ pico_default_asm_setup .section .text +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. regular_func _stage2_boot push {lr} diff --git a/src/rp2040/boot_stage2/boot2_is25lp080.S b/src/rp2040/boot_stage2/boot2_is25lp080.S new file mode 100644 index 000000000..fda0f992f --- /dev/null +++ b/src/rp2040/boot_stage2/boot2_is25lp080.S @@ -0,0 +1,264 @@ +// ---------------------------------------------------------------------------- +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: ISSI IS25LP080D +// Based on W25Q080 code: main difference is the QE bit being in +// SR1 instead of SR2. +// +// Description: Configures IS25LP080D to run in Quad I/O continuous read XIP mode +// +// Details: * Check status register to determine if QSPI mode is enabled, +// and perform an SR programming cycle if necessary. +// * Use SSI to perform a dummy 0xEB read command, with the mode +// continuation bits set, so that the flash will not require +// 0xEB instruction prefix on subsequent reads. +// * Configure SSI to write address, mode bits, but no instruction. +// SSI + flash are now jointly in a state where continuous reads +// can take place. +// * Set VTOR = 0x10000100 (user vector table immediately after +// this boot2 image). +// * Read stack pointer (MSP) and reset vector from the flash +// vector table; set SP and jump, as though the processor had +// booted directly from flash. +// +// Building: * This code must be linked to run at 0x20027f00 +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive, even integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif + + +// Define interface width: single/dual/quad IO +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD + +// For W25Q080 this is the "Read data fast quad IO" instruction: +#define CMD_READ 0xeb + +// "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Quad I/O" command sequence. +// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the +// next read does not require the 0xeb instruction prefix. +#define MODE_CONTINUOUS_READ 0xa0 + +// The number of address + mode bits, divided by 4 (always 4, not function of +// interface width). +#define ADDR_L 8 + +// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles +// are required. +#define WAIT_CYCLES 4 + +// If defined, we will read status reg, compare to SREG_DATA, and overwrite +// with our value if the SR doesn't match. +// This isn't great because it will remove block protections. +// A better solution is to use a volatile SR write if your device supports it. +#define PROGRAM_STATUS_REG + +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS 0x05 +#define CMD_WRITE_STATUS 0x01 +#define SREG_DATA 0x40 // Enable quad-SPI mode + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +pico_default_asm_setup + +.section .text +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot + push {lr} + + ldr r3, =XIP_SSI_BASE // Use as base address where possible + + // Disable SSI to allow further config + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Set baud rate + movs r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: +#define CTRL0_SPI_TXRX \ + (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \ + (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRL0_SPI_TXRX) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + // Enable SSI and select slave 0 + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] + + // Check whether SR needs updating + ldr r0, =CMD_READ_STATUS + bl read_flash_sreg + ldr r2, =SREG_DATA + cmp r0, r2 + beq skip_sreg_programming + + // Send write enable command + movs r1, #CMD_WRITE_ENABLE + str r1, [r3, #SSI_DR0_OFFSET] + + // Poll for completion and discard RX + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Send status write command followed by data bytes + movs r1, #CMD_WRITE_STATUS + str r1, [r3, #SSI_DR0_OFFSET] + movs r0, #0 + str r2, [r3, #SSI_DR0_OFFSET] + + bl wait_ssi_ready + ldr r1, [r3, #SSI_DR0_OFFSET] + ldr r1, [r3, #SSI_DR0_OFFSET] + + // Poll status register for write completion +1: + ldr r0, =CMD_READ_STATUS + bl read_flash_sreg + movs r1, #1 + tst r0, r1 + bne 1b + +skip_sreg_programming: + + // Send a 0xA3 high-performance-mode instruction +// ldr r1, =0xa3 +// str r1, [r3, #SSI_DR0_OFFSET] +// bl wait_ssi_ready + + // Disable SSI again so that it can be reconfigured + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] +#endif + + +// First we need to send the initial command to get us in to Fast Read Quad I/O +// mode. As this transaction requires a command, we can't send it in XIP mode. +// To enter Continuous Read mode as well we need to append 4'b0010 to the address +// bits and then add a further 4 don't care bits. We will construct this by +// specifying a 28-bit address, with the least significant bits being 4'b0010. +// This is just a dummy transaction so we'll perform a read from address zero +// and then discard what comes back. All we really care about is that at the +// end of the transaction, the flash device is in Continuous Read mode +// and from then on will only expect to receive addresses. +dummy_read: +#define CTRLR0_ENTER_XIP \ + (FRAME_FORMAT /* Quad I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + movs r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#define SPI_CTRLR0_ENTER_XIP \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + movs r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + movs r1, #CMD_READ + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + + // Poll for completion + bl wait_ssi_ready + +// At this point CN# will be deasserted and the SPI clock will not be running. +// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and +// only expecting address bits after the next CN# assertion. So long as we +// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address +// then the Winbond device will remain in continuous read mode. This is the +// ideal mode for Execute-In-Place. +// (If we want to exit continuous read mode then we will need to switch back +// to APM mode and generate a 28-bit address phase with the extra nibble set +// to 4'b0000). + + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD +configure_ssi: +#define SPI_CTRLR0_XIP \ + (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \ + (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// We are now in XIP mode, with all transactions using Dual I/O and only +// needing to send 24-bit addresses (plus mode bits) for each read transaction. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +// Common functions +#include "boot2_helpers/wait_ssi_ready.S" +#ifdef PROGRAM_STATUS_REG +#include "boot2_helpers/read_flash_sreg.S" +#endif + +.global literals +literals: +.ltorg + +.end diff --git a/src/rp2_common/boot_stage2/boot2_usb_blinky.S b/src/rp2040/boot_stage2/boot2_usb_blinky.S similarity index 100% rename from src/rp2_common/boot_stage2/boot2_usb_blinky.S rename to src/rp2040/boot_stage2/boot2_usb_blinky.S diff --git a/src/rp2_common/boot_stage2/boot2_w25q080.S b/src/rp2040/boot_stage2/boot2_w25q080.S similarity index 96% rename from src/rp2_common/boot_stage2/boot2_w25q080.S rename to src/rp2040/boot_stage2/boot2_w25q080.S index 7309f53bd..c35fb81fa 100644 --- a/src/rp2_common/boot_stage2/boot2_w25q080.S +++ b/src/rp2040/boot_stage2/boot2_w25q080.S @@ -90,11 +90,13 @@ pico_default_asm_setup .section .text -// The exit point is passed in lr. If entered from bootrom, this will be the -// flash address immediately following this second stage (0x10000100). -// Otherwise it will be a return address -- second stage being called as a -// function by user code, after copying out of XIP region. r3 holds SSI base, -// r0...2 used as temporaries. Other GPRs not used. +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. regular_func _stage2_boot push {lr} diff --git a/src/rp2040/boot_stage2/boot2_w25x10cl.S b/src/rp2040/boot_stage2/boot2_w25x10cl.S new file mode 100644 index 000000000..9aa51ac57 --- /dev/null +++ b/src/rp2040/boot_stage2/boot2_w25x10cl.S @@ -0,0 +1,197 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Winbond W25X10CL +// +// Description: Configures W25X10CL to run in Dual I/O continuous read XIP mode +// +// Details: * Disable SSI +// * Configure SSI to generate 8b command + 28b address + 2 wait, +// with address and data using dual SPI mode +// * Enable SSI +// * Generate dummy read with command = 0xBB, top 24b of address +// of 0x000000 followed by M[7:0]=0010zzzz (with the HiZ being +// generated by 2 wait cycles). This leaves the W25X10CL in +// continuous read mode +// * Disable SSI +// * Configure SSI to generate 0b command + 28b address + 2 wait, +// with the extra 4 bits of address LSB being 0x2 to keep the +// W25X10CL in continuous read mode forever +// * Enable SSI +// * Set VTOR = 0x10000100 +// * Read MSP reset vector from 0x10000100 and write to MSP (this +// will also enable XIP mode in the SSI wrapper) +// * Read PC reset vector from 0x10000104 and jump to it +// +// Building: * This code must be linked to run at 0x20000000 +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/ssi.h" + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be an even number. +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif + +pico_default_asm_setup + +// ---------------------------------------------------------------------------- +// The "System Control Block" is a set of internal Cortex-M0+ control registers +// that are memory mapped and accessed like any other H/W register. They have +// fixed addresses in the address map of every Cortex-M0+ system. +// ---------------------------------------------------------------------------- + +.equ SCB_VTOR, 0xE000ED08 // RW Vector Table Offset Register + +// ---------------------------------------------------------------------------- +// Winbond W25X10CL Supported Commands +// Taken from "w25x10cl_reg_021714.pdf" +// ---------------------------------------------------------------------------- + +.equ W25X10CL_CMD_READ_DATA_FAST_DUAL_IO, 0xbb + +// ---------------------------------------------------------------------------- +// Winbond W25X10CL "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Dual I/O" command sequence. +// Of M[7:4], they say M[7:6] are reserved (set to zero), and bits M[3:0] +// are don't care (we HiZ). Only M[5:4] are used, and they must be set +// to M[5:4] = 2'b10 to enable continuous read mode. +// ---------------------------------------------------------------------------- + +.equ W25X10CL_MODE_CONTINUOUS_READ, 0x20 + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +.org 0 + +.section .text + +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot + push {lr} + ldr r3, =XIP_SSI_BASE // Use as base address where possible + +// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read + + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config + +// The Boot ROM sets a very conservative SPI clock frequency to be sure it can +// read the initial 256 bytes from any device. Here we can be more aggressive. + + movs r1, #PICO_FLASH_SPI_CLKDIV + str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock + +// First we need to send the initial command to get us in to Fast Read Dual I/O +// mode. As this transaction requires a command, we can't send it in XIP mode. +// To enter Continuous Read mode as well we need to append 4'b0010 to the address +// bits and then add a further 4 don't care bits. We will construct this by +// specifying a 28-bit address, with the least significant bits being 4'b0010. +// This is just a dummy transaction so we'll perform a read from address zero +// and then discard what comes back. All we really care about is that at the +// end of the transaction, the Winbond W25X10CL device is in Continuous Read mode +// and from then on will only expect to receive addresses. + +#define CTRLR0_ENTER_XIP \ + (SSI_CTRLR0_SPI_FRF_VALUE_DUAL /* Dual I/O mode */ \ + << SSI_CTRLR0_SPI_FRF_LSB) | \ + (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \ + (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \ + << SSI_CTRLR0_TMOD_LSB) + + ldr r1, =(CTRLR0_ENTER_XIP) + str r1, [r3, #SSI_CTRLR0_OFFSET] + + movs r1, #0x0 // NDF=0 (single 32b read) + str r1, [r3, #SSI_CTRLR1_OFFSET] + +#define SPI_CTRLR0_ENTER_XIP \ + (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ + (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_8B \ + << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Dual I/O mode */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_ENTER_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register + str r1, [r0] + + movs r1, #1 // Re-enable SSI + str r1, [r3, #SSI_SSIENR_OFFSET] + + movs r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB + str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO + movs r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10 + str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction + +// Now we wait for the read transaction to complete by monitoring the SSI +// status register and checking for the "RX FIFO Not Empty" flag to assert. + + movs r1, #SSI_SR_RFNE_BITS +00: + ldr r0, [r3, #SSI_SR_OFFSET] // Read status register + tst r0, r1 // RFNE status flag set? + beq 00b // If not then wait + +// At this point CN# will be deasserted and the SPI clock will not be running. +// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and +// only expecting address bits after the next CN# assertion. So long as we +// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address +// then the Winbond device will remain in continuous read mode. This is the +// ideal mode for Execute-In-Place. +// (If we want to exit continuous read mode then we will need to switch back +// to APM mode and generate a 28-bit address phase with the extra nibble set +// to 4'b0000). + + movs r1, #0 + str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config + +// Note that the INST_L field is used to select what XIP data gets pushed into +// the TX FIFO: +// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD +// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD + +#define SPI_CTRLR0_XIP \ + (W25X10CL_MODE_CONTINUOUS_READ /* Mode bits to keep Winbond in continuous read mode */ \ + << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \ + (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Send 28 bits (24 address + 4 mode) */ \ + (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \ + (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \ + << SSI_SPI_CTRLR0_INST_L_LSB) | \ + (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Dual I/O mode (and Command but that is zero bits long) */ \ + << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) + + ldr r1, =(SPI_CTRLR0_XIP) + ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) + str r1, [r0] + + movs r1, #1 + str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI + +// We are now in XIP mode, with all transactions using Dual I/O and only +// needing to send 24-bit addresses (plus mode bits) for each read transaction. + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +.global literals +literals: +.ltorg + +.end diff --git a/src/rp2_common/boot_stage2/boot_stage2.ld b/src/rp2040/boot_stage2/boot_stage2.ld similarity index 100% rename from src/rp2_common/boot_stage2/boot_stage2.ld rename to src/rp2040/boot_stage2/boot_stage2.ld diff --git a/src/rp2_common/boot_stage2/compile_time_choice.S b/src/rp2040/boot_stage2/compile_time_choice.S similarity index 100% rename from src/rp2_common/boot_stage2/compile_time_choice.S rename to src/rp2040/boot_stage2/compile_time_choice.S diff --git a/src/rp2_common/boot_stage2/doc.h b/src/rp2040/boot_stage2/doc.h similarity index 100% rename from src/rp2_common/boot_stage2/doc.h rename to src/rp2040/boot_stage2/doc.h diff --git a/src/rp2_common/boot_stage2/include/boot_stage2/config.h b/src/rp2040/boot_stage2/include/boot_stage2/config.h similarity index 100% rename from src/rp2_common/boot_stage2/include/boot_stage2/config.h rename to src/rp2040/boot_stage2/include/boot_stage2/config.h diff --git a/src/rp2_common/boot_stage2/pad_checksum b/src/rp2040/boot_stage2/pad_checksum similarity index 100% rename from src/rp2_common/boot_stage2/pad_checksum rename to src/rp2040/boot_stage2/pad_checksum diff --git a/src/rp2040/hardware_regs/BUILD.bazel b/src/rp2040/hardware_regs/BUILD.bazel index d2793e60f..cb19e2849 100644 --- a/src/rp2040/hardware_regs/BUILD.bazel +++ b/src/rp2040/hardware_regs/BUILD.bazel @@ -1,7 +1,12 @@ -# Always include these libraries through //src/rp2_common/pico_platform:*! +# Always include these libraries through //src/rp2_common:*! # This ensures that you'll get the right headers for the MCU you're targeting. -package(default_visibility = ["//src/rp2_common/pico_platform:__pkg__"]) +package( + default_visibility = [ + "//src/rp2040:__subpackages__", + "//src/rp2_common:__pkg__", + ], +) cc_library( name = "platform_defs", diff --git a/src/rp2040/hardware_regs/CMakeLists.txt b/src/rp2040/hardware_regs/CMakeLists.txt index 1be70033c..082d44a7e 100644 --- a/src/rp2040/hardware_regs/CMakeLists.txt +++ b/src/rp2040/hardware_regs/CMakeLists.txt @@ -1,4 +1,4 @@ add_library(hardware_regs INTERFACE) add_library(hardware_regs_headers INTERFACE) -target_include_directories(hardware_regs_headers INTERFACE include) +target_include_directories(hardware_regs_headers SYSTEM INTERFACE include) pico_mirrored_target_link_libraries(hardware_regs INTERFACE hardware_base) diff --git a/src/rp2040/hardware_regs/RP2040.svd b/src/rp2040/hardware_regs/RP2040.svd new file mode 100644 index 000000000..7ffdf3868 --- /dev/null +++ b/src/rp2040/hardware_regs/RP2040.svd @@ -0,0 +1,51025 @@ + + + + Raspberry Pi + RP2040 + RP + 0.1 + + Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz + 264KB on-chip SRAM + 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels + 1 x USB 1.1 controller and PHY, with host and device support + 8 x Programmable I/O (PIO) state machines for custom peripheral support + Supported input power 1.8-5.5V DC + Operating temperature -20C to +85C + Drag-and-drop programming using mass storage over USB + Low-power sleep and dormant modes + Accurate on-chip clock + Temperature sensor + Accelerated integer and floating-point libraries on-chip + + 32 + 32 + 0xffffffff + 0x00000000 + read-write + + Copyright (c) 2024 Raspberry Pi Ltd. + + SPDX-License-Identifier: BSD-3-Clause + + + CM0PLUS + r0p1 + little + true + false + 1 + 2 + false + 26 + + 8 + + + RESETS + 0x4000c000 + + 0 + 12 + registers + + + + RESET + 0x00000000 + Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. + 0x01ffffff + + + USBCTRL + [24:24] + read-write + + + UART1 + [23:23] + read-write + + + UART0 + [22:22] + read-write + + + TIMER + [21:21] + read-write + + + TBMAN + [20:20] + read-write + + + SYSINFO + [19:19] + read-write + + + SYSCFG + [18:18] + read-write + + + SPI1 + [17:17] + read-write + + + SPI0 + [16:16] + read-write + + + RTC + [15:15] + read-write + + + PWM + [14:14] + read-write + + + PLL_USB + [13:13] + read-write + + + PLL_SYS + [12:12] + read-write + + + PIO1 + [11:11] + read-write + + + PIO0 + [10:10] + read-write + + + PADS_QSPI + [9:9] + read-write + + + PADS_BANK0 + [8:8] + read-write + + + JTAG + [7:7] + read-write + + + IO_QSPI + [6:6] + read-write + + + IO_BANK0 + [5:5] + read-write + + + I2C1 + [4:4] + read-write + + + I2C0 + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + WDSEL + 0x00000004 + Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. + 0x00000000 + + + USBCTRL + [24:24] + read-write + + + UART1 + [23:23] + read-write + + + UART0 + [22:22] + read-write + + + TIMER + [21:21] + read-write + + + TBMAN + [20:20] + read-write + + + SYSINFO + [19:19] + read-write + + + SYSCFG + [18:18] + read-write + + + SPI1 + [17:17] + read-write + + + SPI0 + [16:16] + read-write + + + RTC + [15:15] + read-write + + + PWM + [14:14] + read-write + + + PLL_USB + [13:13] + read-write + + + PLL_SYS + [12:12] + read-write + + + PIO1 + [11:11] + read-write + + + PIO0 + [10:10] + read-write + + + PADS_QSPI + [9:9] + read-write + + + PADS_BANK0 + [8:8] + read-write + + + JTAG + [7:7] + read-write + + + IO_QSPI + [6:6] + read-write + + + IO_BANK0 + [5:5] + read-write + + + I2C1 + [4:4] + read-write + + + I2C0 + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + RESET_DONE + 0x00000008 + Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. + 0x00000000 + + + USBCTRL + [24:24] + read-only + + + UART1 + [23:23] + read-only + + + UART0 + [22:22] + read-only + + + TIMER + [21:21] + read-only + + + TBMAN + [20:20] + read-only + + + SYSINFO + [19:19] + read-only + + + SYSCFG + [18:18] + read-only + + + SPI1 + [17:17] + read-only + + + SPI0 + [16:16] + read-only + + + RTC + [15:15] + read-only + + + PWM + [14:14] + read-only + + + PLL_USB + [13:13] + read-only + + + PLL_SYS + [12:12] + read-only + + + PIO1 + [11:11] + read-only + + + PIO0 + [10:10] + read-only + + + PADS_QSPI + [9:9] + read-only + + + PADS_BANK0 + [8:8] + read-only + + + JTAG + [7:7] + read-only + + + IO_QSPI + [6:6] + read-only + + + IO_BANK0 + [5:5] + read-only + + + I2C1 + [4:4] + read-only + + + I2C0 + [3:3] + read-only + + + DMA + [2:2] + read-only + + + BUSCTRL + [1:1] + read-only + + + ADC + [0:0] + read-only + + + + + + + PSM + 0x40010000 + + 0 + 16 + registers + + + + FRCE_ON + 0x00000000 + Force block out of reset (i.e. power it on) + 0x00000000 + + + PROC1 + [16:16] + read-write + + + PROC0 + [15:15] + read-write + + + SIO + [14:14] + read-write + + + VREG_AND_CHIP_RESET + [13:13] + read-write + + + XIP + [12:12] + read-write + + + SRAM5 + [11:11] + read-write + + + SRAM4 + [10:10] + read-write + + + SRAM3 + [9:9] + read-write + + + SRAM2 + [8:8] + read-write + + + SRAM1 + [7:7] + read-write + + + SRAM0 + [6:6] + read-write + + + ROM + [5:5] + read-write + + + BUSFABRIC + [4:4] + read-write + + + RESETS + [3:3] + read-write + + + CLOCKS + [2:2] + read-write + + + XOSC + [1:1] + read-write + + + ROSC + [0:0] + read-write + + + + + FRCE_OFF + 0x00000004 + Force into reset (i.e. power it off) + 0x00000000 + + + PROC1 + [16:16] + read-write + + + PROC0 + [15:15] + read-write + + + SIO + [14:14] + read-write + + + VREG_AND_CHIP_RESET + [13:13] + read-write + + + XIP + [12:12] + read-write + + + SRAM5 + [11:11] + read-write + + + SRAM4 + [10:10] + read-write + + + SRAM3 + [9:9] + read-write + + + SRAM2 + [8:8] + read-write + + + SRAM1 + [7:7] + read-write + + + SRAM0 + [6:6] + read-write + + + ROM + [5:5] + read-write + + + BUSFABRIC + [4:4] + read-write + + + RESETS + [3:3] + read-write + + + CLOCKS + [2:2] + read-write + + + XOSC + [1:1] + read-write + + + ROSC + [0:0] + read-write + + + + + WDSEL + 0x00000008 + Set to 1 if this peripheral should be reset when the watchdog fires. + 0x00000000 + + + PROC1 + [16:16] + read-write + + + PROC0 + [15:15] + read-write + + + SIO + [14:14] + read-write + + + VREG_AND_CHIP_RESET + [13:13] + read-write + + + XIP + [12:12] + read-write + + + SRAM5 + [11:11] + read-write + + + SRAM4 + [10:10] + read-write + + + SRAM3 + [9:9] + read-write + + + SRAM2 + [8:8] + read-write + + + SRAM1 + [7:7] + read-write + + + SRAM0 + [6:6] + read-write + + + ROM + [5:5] + read-write + + + BUSFABRIC + [4:4] + read-write + + + RESETS + [3:3] + read-write + + + CLOCKS + [2:2] + read-write + + + XOSC + [1:1] + read-write + + + ROSC + [0:0] + read-write + + + + + DONE + 0x0000000c + Indicates the peripheral's registers are ready to access. + 0x00000000 + + + PROC1 + [16:16] + read-only + + + PROC0 + [15:15] + read-only + + + SIO + [14:14] + read-only + + + VREG_AND_CHIP_RESET + [13:13] + read-only + + + XIP + [12:12] + read-only + + + SRAM5 + [11:11] + read-only + + + SRAM4 + [10:10] + read-only + + + SRAM3 + [9:9] + read-only + + + SRAM2 + [8:8] + read-only + + + SRAM1 + [7:7] + read-only + + + SRAM0 + [6:6] + read-only + + + ROM + [5:5] + read-only + + + BUSFABRIC + [4:4] + read-only + + + RESETS + [3:3] + read-only + + + CLOCKS + [2:2] + read-only + + + XOSC + [1:1] + read-only + + + ROSC + [0:0] + read-only + + + + + + + CLOCKS + 0x40008000 + + 0 + 200 + registers + + + CLOCKS_IRQ + 17 + + + + CLK_GPOUT0_CTRL + 0x00000000 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT0_DIV + 0x00000004 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT0_SELECTED + 0x00000008 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_GPOUT0_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_GPOUT1_CTRL + 0x0000000c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT1_DIV + 0x00000010 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT1_SELECTED + 0x00000014 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_GPOUT1_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_GPOUT2_CTRL + 0x00000018 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT2_DIV + 0x0000001c + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT2_SELECTED + 0x00000020 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_GPOUT2_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_GPOUT3_CTRL + 0x00000024 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clk_sys + 6 + + + clk_usb + 7 + + + clk_adc + 8 + + + clk_rtc + 9 + + + clk_ref + 10 + + + + + + + CLK_GPOUT3_DIV + 0x00000028 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_GPOUT3_SELECTED + 0x0000002c + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_GPOUT3_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_REF_CTRL + 0x00000030 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [6:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [1:0] + read-write + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + + + + + CLK_REF_DIV + 0x00000034 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [9:8] + read-write + + + + + CLK_REF_SELECTED + 0x00000038 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_REF_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [31:0] + read-only + + + + + CLK_SYS_CTRL + 0x0000003c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [0:0] + read-write + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + + + + + CLK_SYS_DIV + 0x00000040 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_SYS_SELECTED + 0x00000044 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_SYS_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [31:0] + read-only + + + + + CLK_PERI_CTRL + 0x00000048 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + + + + + CLK_PERI_DIV + 0x0000004c + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_PERI_SELECTED + 0x00000050 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_PERI_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_USB_CTRL + 0x00000054 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_USB_DIV + 0x00000058 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [9:8] + read-write + + + + + CLK_USB_SELECTED + 0x0000005c + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_USB_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_ADC_CTRL + 0x00000060 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_ADC_DIV + 0x00000064 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [9:8] + read-write + + + + + CLK_ADC_SELECTED + 0x00000068 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_ADC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_RTC_CTRL + 0x0000006c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_RTC_DIV + 0x00000070 + Clock divisor, can be changed on-the-fly + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + + + CLK_RTC_SELECTED + 0x00000074 + Indicates which SRC is currently selected by the glitchless mux (one-hot). + 0x00000001 + + + CLK_RTC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + + + + CLK_SYS_RESUS_CTRL + 0x00000078 + 0x000000ff + + + CLEAR + For clearing the resus after the fault that triggered it has been corrected + [16:16] + read-write + + + FRCE + Force a resus, for test purposes only + [12:12] + read-write + + + ENABLE + Enable resus + [8:8] + read-write + + + TIMEOUT + This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq + [7:0] + read-write + + + + + CLK_SYS_RESUS_STATUS + 0x0000007c + 0x00000000 + + + RESUSSED + Clock has been resuscitated, correct the error then send ctrl_clear=1 + [0:0] + read-only + + + + + FC0_REF_KHZ + 0x00000080 + Reference clock frequency in kHz + 0x00000000 + + + FC0_REF_KHZ + [19:0] + read-write + + + + + FC0_MIN_KHZ + 0x00000084 + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + 0x00000000 + + + FC0_MIN_KHZ + [24:0] + read-write + + + + + FC0_MAX_KHZ + 0x00000088 + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + 0x01ffffff + + + FC0_MAX_KHZ + [24:0] + read-write + + + + + FC0_DELAY + 0x0000008c + Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period + 0x00000001 + + + FC0_DELAY + [2:0] + read-write + + + + + FC0_INTERVAL + 0x00000090 + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us + 0x00000008 + + + FC0_INTERVAL + [3:0] + read-write + + + + + FC0_SRC + 0x00000094 + Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count + 0x00000000 + + + FC0_SRC + [7:0] + read-write + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_rtc + 13 + + + + + + + FC0_STATUS + 0x00000098 + Frequency counter status + 0x00000000 + + + DIED + Test clock stopped during test + [28:28] + read-only + + + FAST + Test clock faster than expected, only valid when status_done=1 + [24:24] + read-only + + + SLOW + Test clock slower than expected, only valid when status_done=1 + [20:20] + read-only + + + FAIL + Test failed + [16:16] + read-only + + + WAITING + Waiting for test clock to start + [12:12] + read-only + + + RUNNING + Test running + [8:8] + read-only + + + DONE + Test complete + [4:4] + read-only + + + PASS + Test passed + [0:0] + read-only + + + + + FC0_RESULT + 0x0000009c + Result of frequency measurement, only valid when status_done=1 + 0x00000000 + + + KHZ + [29:5] + read-only + + + FRAC + [4:0] + read-only + + + + + WAKE_EN0 + 0x000000a0 + enable clock in wake mode + 0xffffffff + + + CLK_SYS_SRAM3 + [31:31] + read-write + + + CLK_SYS_SRAM2 + [30:30] + read-write + + + CLK_SYS_SRAM1 + [29:29] + read-write + + + CLK_SYS_SRAM0 + [28:28] + read-write + + + CLK_SYS_SPI1 + [27:27] + read-write + + + CLK_PERI_SPI1 + [26:26] + read-write + + + CLK_SYS_SPI0 + [25:25] + read-write + + + CLK_PERI_SPI0 + [24:24] + read-write + + + CLK_SYS_SIO + [23:23] + read-write + + + CLK_SYS_RTC + [22:22] + read-write + + + CLK_RTC_RTC + [21:21] + read-write + + + CLK_SYS_ROSC + [20:20] + read-write + + + CLK_SYS_ROM + [19:19] + read-write + + + CLK_SYS_RESETS + [18:18] + read-write + + + CLK_SYS_PWM + [17:17] + read-write + + + CLK_SYS_PSM + [16:16] + read-write + + + CLK_SYS_PLL_USB + [15:15] + read-write + + + CLK_SYS_PLL_SYS + [14:14] + read-write + + + CLK_SYS_PIO1 + [13:13] + read-write + + + CLK_SYS_PIO0 + [12:12] + read-write + + + CLK_SYS_PADS + [11:11] + read-write + + + CLK_SYS_VREG_AND_CHIP_RESET + [10:10] + read-write + + + CLK_SYS_JTAG + [9:9] + read-write + + + CLK_SYS_IO + [8:8] + read-write + + + CLK_SYS_I2C1 + [7:7] + read-write + + + CLK_SYS_I2C0 + [6:6] + read-write + + + CLK_SYS_DMA + [5:5] + read-write + + + CLK_SYS_BUSFABRIC + [4:4] + read-write + + + CLK_SYS_BUSCTRL + [3:3] + read-write + + + CLK_SYS_ADC + [2:2] + read-write + + + CLK_ADC_ADC + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + WAKE_EN1 + 0x000000a4 + enable clock in wake mode + 0x00007fff + + + CLK_SYS_XOSC + [14:14] + read-write + + + CLK_SYS_XIP + [13:13] + read-write + + + CLK_SYS_WATCHDOG + [12:12] + read-write + + + CLK_USB_USBCTRL + [11:11] + read-write + + + CLK_SYS_USBCTRL + [10:10] + read-write + + + CLK_SYS_UART1 + [9:9] + read-write + + + CLK_PERI_UART1 + [8:8] + read-write + + + CLK_SYS_UART0 + [7:7] + read-write + + + CLK_PERI_UART0 + [6:6] + read-write + + + CLK_SYS_TIMER + [5:5] + read-write + + + CLK_SYS_TBMAN + [4:4] + read-write + + + CLK_SYS_SYSINFO + [3:3] + read-write + + + CLK_SYS_SYSCFG + [2:2] + read-write + + + CLK_SYS_SRAM5 + [1:1] + read-write + + + CLK_SYS_SRAM4 + [0:0] + read-write + + + + + SLEEP_EN0 + 0x000000a8 + enable clock in sleep mode + 0xffffffff + + + CLK_SYS_SRAM3 + [31:31] + read-write + + + CLK_SYS_SRAM2 + [30:30] + read-write + + + CLK_SYS_SRAM1 + [29:29] + read-write + + + CLK_SYS_SRAM0 + [28:28] + read-write + + + CLK_SYS_SPI1 + [27:27] + read-write + + + CLK_PERI_SPI1 + [26:26] + read-write + + + CLK_SYS_SPI0 + [25:25] + read-write + + + CLK_PERI_SPI0 + [24:24] + read-write + + + CLK_SYS_SIO + [23:23] + read-write + + + CLK_SYS_RTC + [22:22] + read-write + + + CLK_RTC_RTC + [21:21] + read-write + + + CLK_SYS_ROSC + [20:20] + read-write + + + CLK_SYS_ROM + [19:19] + read-write + + + CLK_SYS_RESETS + [18:18] + read-write + + + CLK_SYS_PWM + [17:17] + read-write + + + CLK_SYS_PSM + [16:16] + read-write + + + CLK_SYS_PLL_USB + [15:15] + read-write + + + CLK_SYS_PLL_SYS + [14:14] + read-write + + + CLK_SYS_PIO1 + [13:13] + read-write + + + CLK_SYS_PIO0 + [12:12] + read-write + + + CLK_SYS_PADS + [11:11] + read-write + + + CLK_SYS_VREG_AND_CHIP_RESET + [10:10] + read-write + + + CLK_SYS_JTAG + [9:9] + read-write + + + CLK_SYS_IO + [8:8] + read-write + + + CLK_SYS_I2C1 + [7:7] + read-write + + + CLK_SYS_I2C0 + [6:6] + read-write + + + CLK_SYS_DMA + [5:5] + read-write + + + CLK_SYS_BUSFABRIC + [4:4] + read-write + + + CLK_SYS_BUSCTRL + [3:3] + read-write + + + CLK_SYS_ADC + [2:2] + read-write + + + CLK_ADC_ADC + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + SLEEP_EN1 + 0x000000ac + enable clock in sleep mode + 0x00007fff + + + CLK_SYS_XOSC + [14:14] + read-write + + + CLK_SYS_XIP + [13:13] + read-write + + + CLK_SYS_WATCHDOG + [12:12] + read-write + + + CLK_USB_USBCTRL + [11:11] + read-write + + + CLK_SYS_USBCTRL + [10:10] + read-write + + + CLK_SYS_UART1 + [9:9] + read-write + + + CLK_PERI_UART1 + [8:8] + read-write + + + CLK_SYS_UART0 + [7:7] + read-write + + + CLK_PERI_UART0 + [6:6] + read-write + + + CLK_SYS_TIMER + [5:5] + read-write + + + CLK_SYS_TBMAN + [4:4] + read-write + + + CLK_SYS_SYSINFO + [3:3] + read-write + + + CLK_SYS_SYSCFG + [2:2] + read-write + + + CLK_SYS_SRAM5 + [1:1] + read-write + + + CLK_SYS_SRAM4 + [0:0] + read-write + + + + + ENABLED0 + 0x000000b0 + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_SRAM3 + [31:31] + read-only + + + CLK_SYS_SRAM2 + [30:30] + read-only + + + CLK_SYS_SRAM1 + [29:29] + read-only + + + CLK_SYS_SRAM0 + [28:28] + read-only + + + CLK_SYS_SPI1 + [27:27] + read-only + + + CLK_PERI_SPI1 + [26:26] + read-only + + + CLK_SYS_SPI0 + [25:25] + read-only + + + CLK_PERI_SPI0 + [24:24] + read-only + + + CLK_SYS_SIO + [23:23] + read-only + + + CLK_SYS_RTC + [22:22] + read-only + + + CLK_RTC_RTC + [21:21] + read-only + + + CLK_SYS_ROSC + [20:20] + read-only + + + CLK_SYS_ROM + [19:19] + read-only + + + CLK_SYS_RESETS + [18:18] + read-only + + + CLK_SYS_PWM + [17:17] + read-only + + + CLK_SYS_PSM + [16:16] + read-only + + + CLK_SYS_PLL_USB + [15:15] + read-only + + + CLK_SYS_PLL_SYS + [14:14] + read-only + + + CLK_SYS_PIO1 + [13:13] + read-only + + + CLK_SYS_PIO0 + [12:12] + read-only + + + CLK_SYS_PADS + [11:11] + read-only + + + CLK_SYS_VREG_AND_CHIP_RESET + [10:10] + read-only + + + CLK_SYS_JTAG + [9:9] + read-only + + + CLK_SYS_IO + [8:8] + read-only + + + CLK_SYS_I2C1 + [7:7] + read-only + + + CLK_SYS_I2C0 + [6:6] + read-only + + + CLK_SYS_DMA + [5:5] + read-only + + + CLK_SYS_BUSFABRIC + [4:4] + read-only + + + CLK_SYS_BUSCTRL + [3:3] + read-only + + + CLK_SYS_ADC + [2:2] + read-only + + + CLK_ADC_ADC + [1:1] + read-only + + + CLK_SYS_CLOCKS + [0:0] + read-only + + + + + ENABLED1 + 0x000000b4 + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_XOSC + [14:14] + read-only + + + CLK_SYS_XIP + [13:13] + read-only + + + CLK_SYS_WATCHDOG + [12:12] + read-only + + + CLK_USB_USBCTRL + [11:11] + read-only + + + CLK_SYS_USBCTRL + [10:10] + read-only + + + CLK_SYS_UART1 + [9:9] + read-only + + + CLK_PERI_UART1 + [8:8] + read-only + + + CLK_SYS_UART0 + [7:7] + read-only + + + CLK_PERI_UART0 + [6:6] + read-only + + + CLK_SYS_TIMER + [5:5] + read-only + + + CLK_SYS_TBMAN + [4:4] + read-only + + + CLK_SYS_SYSINFO + [3:3] + read-only + + + CLK_SYS_SYSCFG + [2:2] + read-only + + + CLK_SYS_SRAM5 + [1:1] + read-only + + + CLK_SYS_SRAM4 + [0:0] + read-only + + + + + INTR + 0x000000b8 + Raw Interrupts + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + INTE + 0x000000bc + Interrupt Enable + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTF + 0x000000c0 + Interrupt Force + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTS + 0x000000c4 + Interrupt status after masking & forcing + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + + + PADS_BANK0 + 0x4001c000 + + 0 + 132 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO0 + 0x00000004 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO1 + 0x00000008 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO2 + 0x0000000c + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO3 + 0x00000010 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO4 + 0x00000014 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO5 + 0x00000018 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO6 + 0x0000001c + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO7 + 0x00000020 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO8 + 0x00000024 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO9 + 0x00000028 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO10 + 0x0000002c + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO11 + 0x00000030 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO12 + 0x00000034 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO13 + 0x00000038 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO14 + 0x0000003c + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO15 + 0x00000040 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO16 + 0x00000044 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO17 + 0x00000048 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO18 + 0x0000004c + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO19 + 0x00000050 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO20 + 0x00000054 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO21 + 0x00000058 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO22 + 0x0000005c + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO23 + 0x00000060 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO24 + 0x00000064 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO25 + 0x00000068 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO26 + 0x0000006c + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO27 + 0x00000070 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO28 + 0x00000074 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO29 + 0x00000078 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWCLK + 0x0000007c + Pad control register + 0x000000da + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWD + 0x00000080 + Pad control register + 0x0000005a + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + PADS_QSPI + 0x40020000 + + 0 + 28 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO_QSPI_SCLK + 0x00000004 + Pad control register + 0x00000056 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD0 + 0x00000008 + Pad control register + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD1 + 0x0000000c + Pad control register + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD2 + 0x00000010 + Pad control register + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD3 + 0x00000014 + Pad control register + 0x00000052 + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SS + 0x00000018 + Pad control register + 0x0000005a + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + IO_QSPI + 0x40018000 + + 0 + 88 + registers + + + IO_IRQ_QSPI + 14 + + + + GPIO_QSPI_SCLK_STATUS + 0x00000000 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SCLK_CTRL + 0x00000004 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sclk + 0 + + + sio_30 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SS_STATUS + 0x00000008 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SS_CTRL + 0x0000000c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_ss_n + 0 + + + sio_31 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD0_STATUS + 0x00000010 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD0_CTRL + 0x00000014 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd0 + 0 + + + sio_32 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD1_STATUS + 0x00000018 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD1_CTRL + 0x0000001c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd1 + 0 + + + sio_33 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD2_STATUS + 0x00000020 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD2_CTRL + 0x00000024 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd2 + 0 + + + sio_34 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD3_STATUS + 0x00000028 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO_QSPI_SD3_CTRL + 0x0000002c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd3 + 0 + + + sio_35 + 5 + + + null + 31 + + + + + + + INTR + 0x00000030 + Raw Interrupts + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE + 0x00000034 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF + 0x00000038 + Interrupt Force for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS + 0x0000003c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE + 0x00000040 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF + 0x00000044 + Interrupt Force for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS + 0x00000048 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE + 0x0000004c + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF + 0x00000050 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS + 0x00000054 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [8:8] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [7:7] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [6:6] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [5:5] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [4:4] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [3:3] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [2:2] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [1:1] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [0:0] + read-only + + + + + + + IO_BANK0 + 0x40014000 + + 0 + 400 + registers + + + IO_IRQ_BANK0 + 13 + + + + GPIO0_STATUS + 0x00000000 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO0_CTRL + 0x00000004 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tck + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + sio_0 + 5 + + + pio0_0 + 6 + + + pio1_0 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO1_STATUS + 0x00000008 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO1_CTRL + 0x0000000c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tms + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + sio_1 + 5 + + + pio0_1 + 6 + + + pio1_1 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO2_STATUS + 0x00000010 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO2_CTRL + 0x00000014 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdi + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + sio_2 + 5 + + + pio0_2 + 6 + + + pio1_2 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO3_STATUS + 0x00000018 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO3_CTRL + 0x0000001c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdo + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + sio_3 + 5 + + + pio0_3 + 6 + + + pio1_3 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO4_STATUS + 0x00000020 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO4_CTRL + 0x00000024 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + sio_4 + 5 + + + pio0_4 + 6 + + + pio1_4 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO5_STATUS + 0x00000028 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO5_CTRL + 0x0000002c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + sio_5 + 5 + + + pio0_5 + 6 + + + pio1_5 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO6_STATUS + 0x00000030 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO6_CTRL + 0x00000034 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + sio_6 + 5 + + + pio0_6 + 6 + + + pio1_6 + 7 + + + usb_muxing_extphy_softcon + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO7_STATUS + 0x00000038 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO7_CTRL + 0x0000003c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + sio_7 + 5 + + + pio0_7 + 6 + + + pio1_7 + 7 + + + usb_muxing_extphy_oe_n + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO8_STATUS + 0x00000040 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO8_CTRL + 0x00000044 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + sio_8 + 5 + + + pio0_8 + 6 + + + pio1_8 + 7 + + + usb_muxing_extphy_rcv + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO9_STATUS + 0x00000048 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO9_CTRL + 0x0000004c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + sio_9 + 5 + + + pio0_9 + 6 + + + pio1_9 + 7 + + + usb_muxing_extphy_vp + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO10_STATUS + 0x00000050 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO10_CTRL + 0x00000054 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + sio_10 + 5 + + + pio0_10 + 6 + + + pio1_10 + 7 + + + usb_muxing_extphy_vm + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO11_STATUS + 0x00000058 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO11_CTRL + 0x0000005c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + sio_11 + 5 + + + pio0_11 + 6 + + + pio1_11 + 7 + + + usb_muxing_extphy_suspnd + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO12_STATUS + 0x00000060 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO12_CTRL + 0x00000064 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + sio_12 + 5 + + + pio0_12 + 6 + + + pio1_12 + 7 + + + usb_muxing_extphy_speed + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO13_STATUS + 0x00000068 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO13_CTRL + 0x0000006c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + sio_13 + 5 + + + pio0_13 + 6 + + + pio1_13 + 7 + + + usb_muxing_extphy_vpo + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO14_STATUS + 0x00000070 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO14_CTRL + 0x00000074 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + sio_14 + 5 + + + pio0_14 + 6 + + + pio1_14 + 7 + + + usb_muxing_extphy_vmo + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO15_STATUS + 0x00000078 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO15_CTRL + 0x0000007c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + sio_15 + 5 + + + pio0_15 + 6 + + + pio1_15 + 7 + + + usb_muxing_digital_dp + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO16_STATUS + 0x00000080 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO16_CTRL + 0x00000084 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + sio_16 + 5 + + + pio0_16 + 6 + + + pio1_16 + 7 + + + usb_muxing_digital_dm + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO17_STATUS + 0x00000088 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO17_CTRL + 0x0000008c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + sio_17 + 5 + + + pio0_17 + 6 + + + pio1_17 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO18_STATUS + 0x00000090 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO18_CTRL + 0x00000094 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + sio_18 + 5 + + + pio0_18 + 6 + + + pio1_18 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO19_STATUS + 0x00000098 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO19_CTRL + 0x0000009c + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + sio_19 + 5 + + + pio0_19 + 6 + + + pio1_19 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO20_STATUS + 0x000000a0 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO20_CTRL + 0x000000a4 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + sio_20 + 5 + + + pio0_20 + 6 + + + pio1_20 + 7 + + + clocks_gpin_0 + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO21_STATUS + 0x000000a8 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO21_CTRL + 0x000000ac + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + sio_21 + 5 + + + pio0_21 + 6 + + + pio1_21 + 7 + + + clocks_gpout_0 + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO22_STATUS + 0x000000b0 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO22_CTRL + 0x000000b4 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + sio_22 + 5 + + + pio0_22 + 6 + + + pio1_22 + 7 + + + clocks_gpin_1 + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO23_STATUS + 0x000000b8 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO23_CTRL + 0x000000bc + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + sio_23 + 5 + + + pio0_23 + 6 + + + pio1_23 + 7 + + + clocks_gpout_1 + 8 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO24_STATUS + 0x000000c0 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO24_CTRL + 0x000000c4 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + sio_24 + 5 + + + pio0_24 + 6 + + + pio1_24 + 7 + + + clocks_gpout_2 + 8 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO25_STATUS + 0x000000c8 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO25_CTRL + 0x000000cc + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + sio_25 + 5 + + + pio0_25 + 6 + + + pio1_25 + 7 + + + clocks_gpout_3 + 8 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO26_STATUS + 0x000000d0 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO26_CTRL + 0x000000d4 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + sio_26 + 5 + + + pio0_26 + 6 + + + pio1_26 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + GPIO27_STATUS + 0x000000d8 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO27_CTRL + 0x000000dc + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + sio_27 + 5 + + + pio0_27 + 6 + + + pio1_27 + 7 + + + usb_muxing_overcurr_detect + 9 + + + null + 31 + + + + + + + GPIO28_STATUS + 0x000000e0 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO28_CTRL + 0x000000e4 + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + sio_28 + 5 + + + pio0_28 + 6 + + + pio1_28 + 7 + + + usb_muxing_vbus_detect + 9 + + + null + 31 + + + + + + + GPIO29_STATUS + 0x000000e8 + GPIO status + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + IRQFROMPAD + interrupt from pad before override is applied + [24:24] + read-only + + + INTOPERI + input signal to peripheral, after override is applied + [19:19] + read-only + + + INFROMPAD + input signal from pad, before override is applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OEFROMPERI + output enable from selected peripheral, before register override is applied + [12:12] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + OUTFROMPERI + output signal from selected peripheral, before register override is applied + [8:8] + read-only + + + + + GPIO29_CTRL + 0x000000ec + GPIO control including function select and overrides. + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [13:12] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [9:8] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + sio_29 + 5 + + + pio0_29 + 6 + + + pio1_29 + 7 + + + usb_muxing_vbus_en + 9 + + + null + 31 + + + + + + + INTR0 + 0x000000f0 + Raw Interrupts + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO7_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO6_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO3_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO2_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO1_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO0_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + INTR1 + 0x000000f4 + Raw Interrupts + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO15_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO14_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO13_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO12_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO11_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO10_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO9_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO8_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + INTR2 + 0x000000f8 + Raw Interrupts + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO23_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO22_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO21_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO20_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO19_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO18_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO17_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO16_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + INTR3 + 0x000000fc + Raw Interrupts + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO29_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO28_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO27_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO26_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO25_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO24_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE0 + 0x00000100 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE1 + 0x00000104 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE2 + 0x00000108 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE3 + 0x0000010c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF0 + 0x00000110 + Interrupt Force for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF1 + 0x00000114 + Interrupt Force for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF2 + 0x00000118 + Interrupt Force for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF3 + 0x0000011c + Interrupt Force for proc0 + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS0 + 0x00000120 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS1 + 0x00000124 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS2 + 0x00000128 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS3 + 0x0000012c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE0 + 0x00000130 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE1 + 0x00000134 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE2 + 0x00000138 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE3 + 0x0000013c + Interrupt Enable for proc1 + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF0 + 0x00000140 + Interrupt Force for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF1 + 0x00000144 + Interrupt Force for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF2 + 0x00000148 + Interrupt Force for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF3 + 0x0000014c + Interrupt Force for proc1 + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS0 + 0x00000150 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS1 + 0x00000154 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS2 + 0x00000158 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS3 + 0x0000015c + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE0 + 0x00000160 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE1 + 0x00000164 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE2 + 0x00000168 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE3 + 0x0000016c + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF0 + 0x00000170 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF1 + 0x00000174 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF2 + 0x00000178 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF3 + 0x0000017c + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS0 + 0x00000180 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS1 + 0x00000184 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS2 + 0x00000188 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS3 + 0x0000018c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + + + SYSINFO + 0x40000000 + + 0 + 20 + registers + + + + CHIP_ID + 0x00000000 + JEDEC JEP-106 compliant chip identifier. + 0x00000000 + + + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:0] + read-only + + + + + PLATFORM + 0x00000004 + Platform register. Allows software to know what environment it is running in. + 0x00000000 + + + ASIC + [1:1] + read-only + + + FPGA + [0:0] + read-only + + + + + GITREF_RP2040 + 0x00000010 + Git hash of the chip source. Used to identify chip version. + 0x00000000 + + + GITREF_RP2040 + [31:0] + read-only + + + + + + + PPB + 0xe0000000 + + 0 + 60836 + registers + + + + SYST_CSR + 0x0000e010 + Use the SysTick Control and Status Register to enable the SysTick features. + 0x00000000 + + + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only + + + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock. + [2:2] + read-write + + + TICKINT + Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request. + [1:1] + read-write + + + ENABLE + Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled. + [0:0] + read-write + + + + + SYST_RVR + 0x0000e014 + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0x00000000 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] + read-write + + + + + SYST_CVR + 0x0000e018 + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0x00000000 + + + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] + read-write + + + + + SYST_CALIB + 0x0000e01c + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0x00000000 + + + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only + + + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only + + + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + + NVIC_ISER + 0x0000e100 + Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. + If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. + 0x00000000 + + + SETENA + Interrupt set-enable bits. + Write: + 0 = No effect. + 1 = Enable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled. + [31:0] + read-write + + + + + NVIC_ICER + 0x0000e180 + Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. + 0x00000000 + + + CLRENA + Interrupt clear-enable bits. + Write: + 0 = No effect. + 1 = Disable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled. + [31:0] + read-write + + + + + NVIC_ISPR + 0x0000e200 + The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. + 0x00000000 + + + SETPEND + Interrupt set-pending bits. + Write: + 0 = No effect. + 1 = Changes interrupt state to pending. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending. + Note: Writing 1 to the NVIC_ISPR bit corresponding to: + An interrupt that is pending has no effect. + A disabled interrupt sets the state of that interrupt to pending. + [31:0] + read-write + + + + + NVIC_ICPR + 0x0000e280 + Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. + 0x00000000 + + + CLRPEND + Interrupt clear-pending bits. + Write: + 0 = No effect. + 1 = Removes pending state and interrupt. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending. + [31:0] + read-write + + + + + NVIC_IPR0 + 0x0000e400 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. + These registers are only word-accessible + 0x00000000 + + + IP_3 + Priority of interrupt 3 + [31:30] + read-write + + + IP_2 + Priority of interrupt 2 + [23:22] + read-write + + + IP_1 + Priority of interrupt 1 + [15:14] + read-write + + + IP_0 + Priority of interrupt 0 + [7:6] + read-write + + + + + NVIC_IPR1 + 0x0000e404 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0x00000000 + + + IP_7 + Priority of interrupt 7 + [31:30] + read-write + + + IP_6 + Priority of interrupt 6 + [23:22] + read-write + + + IP_5 + Priority of interrupt 5 + [15:14] + read-write + + + IP_4 + Priority of interrupt 4 + [7:6] + read-write + + + + + NVIC_IPR2 + 0x0000e408 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0x00000000 + + + IP_11 + Priority of interrupt 11 + [31:30] + read-write + + + IP_10 + Priority of interrupt 10 + [23:22] + read-write + + + IP_9 + Priority of interrupt 9 + [15:14] + read-write + + + IP_8 + Priority of interrupt 8 + [7:6] + read-write + + + + + NVIC_IPR3 + 0x0000e40c + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0x00000000 + + + IP_15 + Priority of interrupt 15 + [31:30] + read-write + + + IP_14 + Priority of interrupt 14 + [23:22] + read-write + + + IP_13 + Priority of interrupt 13 + [15:14] + read-write + + + IP_12 + Priority of interrupt 12 + [7:6] + read-write + + + + + NVIC_IPR4 + 0x0000e410 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0x00000000 + + + IP_19 + Priority of interrupt 19 + [31:30] + read-write + + + IP_18 + Priority of interrupt 18 + [23:22] + read-write + + + IP_17 + Priority of interrupt 17 + [15:14] + read-write + + + IP_16 + Priority of interrupt 16 + [7:6] + read-write + + + + + NVIC_IPR5 + 0x0000e414 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0x00000000 + + + IP_23 + Priority of interrupt 23 + [31:30] + read-write + + + IP_22 + Priority of interrupt 22 + [23:22] + read-write + + + IP_21 + Priority of interrupt 21 + [15:14] + read-write + + + IP_20 + Priority of interrupt 20 + [7:6] + read-write + + + + + NVIC_IPR6 + 0x0000e418 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0x00000000 + + + IP_27 + Priority of interrupt 27 + [31:30] + read-write + + + IP_26 + Priority of interrupt 26 + [23:22] + read-write + + + IP_25 + Priority of interrupt 25 + [15:14] + read-write + + + IP_24 + Priority of interrupt 24 + [7:6] + read-write + + + + + NVIC_IPR7 + 0x0000e41c + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0x00000000 + + + IP_31 + Priority of interrupt 31 + [31:30] + read-write + + + IP_30 + Priority of interrupt 30 + [23:22] + read-write + + + IP_29 + Priority of interrupt 29 + [15:14] + read-write + + + IP_28 + Priority of interrupt 28 + [7:6] + read-write + + + + + CPUID + 0x0000ed00 + Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. + 0x410cc601 + + + IMPLEMENTER + Implementor code: 0x41 = ARM + [31:24] + read-only + + + VARIANT + Major revision number n in the rnpm revision status: + 0x0 = Revision 0. + [23:20] + read-only + + + ARCHITECTURE + Constant that defines the architecture of the processor: + 0xC = ARMv6-M architecture. + [19:16] + read-only + + + PARTNO + Number of processor within family: 0xC60 = Cortex-M0+ + [15:4] + read-only + + + REVISION + Minor revision number m in the rnpm revision status: + 0x1 = Patch 1. + [3:0] + read-only + + + + + ICSR + 0x0000ed04 + Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. + 0x00000000 + + + NMIPENDSET + Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. + NMI set-pending bit. + Write: + 0 = No effect. + 1 = Changes NMI exception state to pending. + Read: + 0 = NMI exception is not pending. + 1 = NMI exception is pending. + Because NMI is the highest-priority exception, normally the processor enters the NMI + exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears + this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the + NMI signal is reasserted while the processor is executing that handler. + [31:31] + read-write + + + PENDSVSET + PendSV set-pending bit. + Write: + 0 = No effect. + 1 = Changes PendSV exception state to pending. + Read: + 0 = PendSV exception is not pending. + 1 = PendSV exception is pending. + Writing 1 to this bit is the only way to set the PendSV exception state to pending. + [28:28] + read-write + + + PENDSVCLR + PendSV clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the PendSV exception. + [27:27] + read-write + + + PENDSTSET + SysTick exception set-pending bit. + Write: + 0 = No effect. + 1 = Changes SysTick exception state to pending. + Read: + 0 = SysTick exception is not pending. + 1 = SysTick exception is pending. + [26:26] + read-write + + + PENDSTCLR + SysTick exception clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the SysTick exception. + This bit is WO. On a register read its value is Unknown. + [25:25] + read-write + + + ISRPREEMPT + The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. + [23:23] + read-only + + + ISRPENDING + External interrupt pending flag + [22:22] + read-only + + + VECTPENDING + Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. + [20:12] + read-only + + + VECTACTIVE + Active exception number field. Reset clears the VECTACTIVE field. + [8:0] + read-only + + + + + VTOR + 0x0000ed08 + The VTOR holds the vector table offset address. + 0x00000000 + + + TBLOFF + Bits [31:8] of the indicate the vector table offset address. + [31:8] + read-write + + + + + AIRCR + 0x0000ed0c + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0x00000000 + + + VECTKEY + Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] + read-write + + + ENDIANESS + Data endianness implemented: + 0 = Little-endian. + [15:15] + read-only + + + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + [2:2] + read-write + + + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + [1:1] + read-write + + + + + SCR + 0x0000ed10 + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0x00000000 + + + SEVONPEND + Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] + read-write + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] + read-write + + + + + CCR + 0x0000ed14 + The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. + 0x00000000 + + + STKALIGN + Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. + [9:9] + read-only + + + UNALIGN_TRP + Always reads as one, indicates that all unaligned accesses generate a HardFault. + [3:3] + read-only + + + + + SHPR2 + 0x0000ed1c + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. + 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + [31:30] + read-write + + + + + SHPR3 + 0x0000ed20 + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. + 0x00000000 + + + PRI_15 + Priority of system handler 15, SysTick + [31:30] + read-write + + + PRI_14 + Priority of system handler 14, PendSV + [23:22] + read-write + + + + + SHCSR + 0x0000ed24 + Use the System Handler Control and State Register to determine or clear the pending status of SVCall. + 0x00000000 + + + SVCALLPENDED + Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. + [15:15] + read-write + + + + + MPU_TYPE + 0x0000ed90 + Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. + 0x00000800 + + + IREGION + Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. + [23:16] + read-only + + + DREGION + Number of regions supported by the MPU. + [15:8] + read-only + + + SEPARATE + Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. + [0:0] + read-only + + + + + MPU_CTRL + 0x0000ed94 + Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. + 0x00000000 + + + PRIVDEFENA + Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. + 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not + covered by any enabled region causes a fault. + 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. + When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. + [2:2] + read-write + + + HFNMIENA + Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. + When the MPU is enabled: + 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. + 1 = the MPU is enabled during HardFault and NMI handlers. + [1:1] + read-write + + + ENABLE + Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. + 0 = MPU disabled. + 1 = MPU enabled. + [0:0] + read-write + + + + + MPU_RNR + 0x0000ed98 + Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. + 0x00000000 + + + REGION + Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. + The MPU supports 8 memory regions, so the permitted values of this field are 0-7. + [3:0] + read-write + + + + + MPU_RBAR + 0x0000ed9c + Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. + 0x00000000 + + + ADDR + Base address of the region. + [31:8] + read-write + + + VALID + On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. + Write: + 0 = MPU_RNR not changed, and the processor: + Updates the base address for the region specified in the MPU_RNR. + Ignores the value of the REGION field. + 1 = The processor: + Updates the value of the MPU_RNR to the value of the REGION field. + Updates the base address for the region specified in the REGION field. + Always reads as zero. + [4:4] + read-write + + + REGION + On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. + [3:0] + read-write + + + + + MPU_RASR + 0x0000eda0 + Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. + 0x00000000 + + + ATTRS + The MPU Region Attribute field. Use to define the region attribute control. + 28 = XN: Instruction access disable bit: + 0 = Instruction fetches enabled. + 1 = Instruction fetches disabled. + 26:24 = AP: Access permission field + 18 = S: Shareable bit + 17 = C: Cacheable bit + 16 = B: Bufferable bit + [31:16] + read-write + + + SRD + Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. + [15:8] + read-write + + + SIZE + Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes + [5:1] + read-write + + + ENABLE + Enables the region. + [0:0] + read-write + + + + + + + SSI + DW_apb_ssi has the following features: + * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. + * APB3 and APB4 protocol support. + * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. + * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. + * Programmable Dual/Quad/Octal SPI support in Master Mode. + * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. + * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. + * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. + * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. + * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. + * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. + * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. + * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. + * Programmable features: + - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. + - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. + - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. + * Configured features: + - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. + - 1 slave select output. + - Hardware slave-select – Dedicated hardware slave-select line. + - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. + - Interrupt polarity – active high interrupt lines. + - Serial clock polarity – low serial-clock polarity directly after reset. + - Serial clock phase – capture on first edge of serial-clock directly after reset. + 0x18000000 + + 0 + 252 + registers + + + + CTRLR0 + 0x00000000 + Control register 0 + 0x00000000 + + + SSTE + Slave select toggle enable + [24:24] + read-write + + + SPI_FRF + SPI frame format + [22:21] + read-write + + + STD + 0 + Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex + + + DUAL + 1 + Dual-SPI frame format; two bits per SCK, half-duplex + + + QUAD + 2 + Quad-SPI frame format; four bits per SCK, half-duplex + + + + + DFS_32 + Data frame size in 32b transfer mode + Value of n -> n+1 clocks per frame. + [20:16] + read-write + + + CFS + Control frame size + Value of n -> n+1 clocks per frame. + [15:12] + read-write + + + SRL + Shift register loop (test mode) + [11:11] + read-write + + + SLV_OE + Slave output enable + [10:10] + read-write + + + TMOD + Transfer mode + [9:8] + read-write + + + TX_AND_RX + 0 + Both transmit and receive + + + TX_ONLY + 1 + Transmit only (not for FRF == 0, standard SPI mode) + + + RX_ONLY + 2 + Receive only (not for FRF == 0, standard SPI mode) + + + EEPROM_READ + 3 + EEPROM read mode (TX then RX; RX starts after control data TX'd) + + + + + SCPOL + Serial clock polarity + [7:7] + read-write + + + SCPH + Serial clock phase + [6:6] + read-write + + + FRF + Frame format + [5:4] + read-write + + + DFS + Data frame size + [3:0] + read-write + + + + + CTRLR1 + 0x00000004 + Master Control register 1 + 0x00000000 + + + NDF + Number of data frames + [15:0] + read-write + + + + + SSIENR + 0x00000008 + SSI Enable + 0x00000000 + + + SSI_EN + SSI enable + [0:0] + read-write + + + + + MWCR + 0x0000000c + Microwire Control + 0x00000000 + + + MHS + Microwire handshaking + [2:2] + read-write + + + MDD + Microwire control + [1:1] + read-write + + + MWMOD + Microwire transfer mode + [0:0] + read-write + + + + + SER + 0x00000010 + Slave enable + 0x00000000 + + + SER + For each bit: + 0 -> slave not selected + 1 -> slave selected + [0:0] + read-write + + + + + BAUDR + 0x00000014 + Baud rate + 0x00000000 + + + SCKDV + SSI clock divider + [15:0] + read-write + + + + + TXFTLR + 0x00000018 + TX FIFO threshold level + 0x00000000 + + + TFT + Transmit FIFO threshold + [7:0] + read-write + + + + + RXFTLR + 0x0000001c + RX FIFO threshold level + 0x00000000 + + + RFT + Receive FIFO threshold + [7:0] + read-write + + + + + TXFLR + 0x00000020 + TX FIFO level + 0x00000000 + + + TFTFL + Transmit FIFO level + [7:0] + read-only + + + + + RXFLR + 0x00000024 + RX FIFO level + 0x00000000 + + + RXTFL + Receive FIFO level + [7:0] + read-only + + + + + SR + 0x00000028 + Status register + 0x00000000 + + + DCOL + Data collision error + [6:6] + read-only + + + TXE + Transmission error + [5:5] + read-only + + + RFF + Receive FIFO full + [4:4] + read-only + + + RFNE + Receive FIFO not empty + [3:3] + read-only + + + TFE + Transmit FIFO empty + [2:2] + read-only + + + TFNF + Transmit FIFO not full + [1:1] + read-only + + + BUSY + SSI busy flag + [0:0] + read-only + + + + + IMR + 0x0000002c + Interrupt mask + 0x00000000 + + + MSTIM + Multi-master contention interrupt mask + [5:5] + read-write + + + RXFIM + Receive FIFO full interrupt mask + [4:4] + read-write + + + RXOIM + Receive FIFO overflow interrupt mask + [3:3] + read-write + + + RXUIM + Receive FIFO underflow interrupt mask + [2:2] + read-write + + + TXOIM + Transmit FIFO overflow interrupt mask + [1:1] + read-write + + + TXEIM + Transmit FIFO empty interrupt mask + [0:0] + read-write + + + + + ISR + 0x00000030 + Interrupt status + 0x00000000 + + + MSTIS + Multi-master contention interrupt status + [5:5] + read-only + + + RXFIS + Receive FIFO full interrupt status + [4:4] + read-only + + + RXOIS + Receive FIFO overflow interrupt status + [3:3] + read-only + + + RXUIS + Receive FIFO underflow interrupt status + [2:2] + read-only + + + TXOIS + Transmit FIFO overflow interrupt status + [1:1] + read-only + + + TXEIS + Transmit FIFO empty interrupt status + [0:0] + read-only + + + + + RISR + 0x00000034 + Raw interrupt status + 0x00000000 + + + MSTIR + Multi-master contention raw interrupt status + [5:5] + read-only + + + RXFIR + Receive FIFO full raw interrupt status + [4:4] + read-only + + + RXOIR + Receive FIFO overflow raw interrupt status + [3:3] + read-only + + + RXUIR + Receive FIFO underflow raw interrupt status + [2:2] + read-only + + + TXOIR + Transmit FIFO overflow raw interrupt status + [1:1] + read-only + + + TXEIR + Transmit FIFO empty raw interrupt status + [0:0] + read-only + + + + + TXOICR + 0x00000038 + TX FIFO overflow interrupt clear + 0x00000000 + + + TXOICR + Clear-on-read transmit FIFO overflow interrupt + [0:0] + read-only + + + + + RXOICR + 0x0000003c + RX FIFO overflow interrupt clear + 0x00000000 + + + RXOICR + Clear-on-read receive FIFO overflow interrupt + [0:0] + read-only + + + + + RXUICR + 0x00000040 + RX FIFO underflow interrupt clear + 0x00000000 + + + RXUICR + Clear-on-read receive FIFO underflow interrupt + [0:0] + read-only + + + + + MSTICR + 0x00000044 + Multi-master interrupt clear + 0x00000000 + + + MSTICR + Clear-on-read multi-master contention interrupt + [0:0] + read-only + + + + + ICR + 0x00000048 + Interrupt clear + 0x00000000 + + + ICR + Clear-on-read all active interrupts + [0:0] + read-only + + + + + DMACR + 0x0000004c + DMA control + 0x00000000 + + + TDMAE + Transmit DMA enable + [1:1] + read-write + + + RDMAE + Receive DMA enable + [0:0] + read-write + + + + + DMATDLR + 0x00000050 + DMA TX data level + 0x00000000 + + + DMATDL + Transmit data watermark level + [7:0] + read-write + + + + + DMARDLR + 0x00000054 + DMA RX data level + 0x00000000 + + + DMARDL + Receive data watermark level (DMARDLR+1) + [7:0] + read-write + + + + + IDR + 0x00000058 + Identification register + 0x51535049 + + + IDCODE + Peripheral dentification code + [31:0] + read-only + + + + + SSI_VERSION_ID + 0x0000005c + Version ID + 0x3430312a + + + SSI_COMP_VERSION + SNPS component version (format X.YY) + [31:0] + read-only + + + + + DR0 + 0x00000060 + Data Register 0 (of 36) + 0x00000000 + + + DR + First data register of 36 + [31:0] + read-write + + + + + RX_SAMPLE_DLY + 0x000000f0 + RX sample delay + 0x00000000 + + + RSD + RXD sample delay (in SCLK cycles) + [7:0] + read-write + + + + + SPI_CTRLR0 + 0x000000f4 + SPI control + 0x03000000 + + + XIP_CMD + SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) + [31:24] + read-write + + + SPI_RXDS_EN + Read data strobe enable + [18:18] + read-write + + + INST_DDR_EN + Instruction DDR transfer enable + [17:17] + read-write + + + SPI_DDR_EN + SPI DDR transfer enable + [16:16] + read-write + + + WAIT_CYCLES + Wait cycles between control frame transmit and data reception (in SCLK cycles) + [15:11] + read-write + + + INST_L + Instruction length (0/4/8/16b) + [9:8] + read-write + + + NONE + 0 + No instruction + + + 4B + 1 + 4-bit instruction + + + 8B + 2 + 8-bit instruction + + + 16B + 3 + 16-bit instruction + + + + + ADDR_L + Address length (0b-60b in 4b increments) + [5:2] + read-write + + + TRANS_TYPE + Address and instruction transfer format + [1:0] + read-write + + + 1C1A + 0 + Command and address both in standard SPI frame format + + + 1C2A + 1 + Command in standard SPI format, address in format specified by FRF + + + 2C2A + 2 + Command and address both in format specified by FRF (e.g. Dual-SPI) + + + + + + + TXD_DRIVE_EDGE + 0x000000f8 + TX drive edge + 0x00000000 + + + TDE + TXD drive edge + [7:0] + read-write + + + + + + + XIP_CTRL + QSPI flash execute-in-place block + 0x14000000 + + 0 + 32 + registers + + + XIP_IRQ + 6 + + + + CTRL + 0x00000000 + Cache control + 0x00000003 + + + POWER_DOWN + When 1, the cache memories are powered down. They retain state, + but can not be accessed. This reduces static power dissipation. + Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot + be enabled when powered down. + Cache-as-SRAM accesses will produce a bus error response when + the cache is powered down. + [3:3] + read-write + + + ERR_BADWRITE + When 1, writes to any alias other than 0x0 (caching, allocating) + will produce a bus fault. When 0, these writes are silently ignored. + In either case, writes to the 0x0 alias will deallocate on tag match, + as usual. + [1:1] + read-write + + + EN + When 1, enable the cache. When the cache is disabled, all XIP accesses + will go straight to the flash, without querying the cache. When enabled, + cacheable XIP accesses will query the cache, and the flash will + not be accessed if the tag matches and the valid bit is set. + + If the cache is enabled, cache-as-SRAM accesses have no effect on the + cache data RAM, and will produce a bus error response. + [0:0] + read-write + + + + + FLUSH + 0x00000004 + Cache Flush control + 0x00000000 + + + FLUSH + Write 1 to flush the cache. This clears the tag memory, but + the data memory retains its contents. (This means cache-as-SRAM + contents is not affected by flush or reset.) + Reading will hold the bus (stall the processor) until the flush + completes. Alternatively STAT can be polled until completion. + [0:0] + write-only + + + + + STAT + 0x00000008 + Cache Status + 0x00000002 + + + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. + [2:2] + read-only + + + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. + [1:1] + read-only + + + FLUSH_READY + Reads as 0 while a cache flush is in progress, and 1 otherwise. + The cache is flushed whenever the XIP block is reset, and also + when requested via the FLUSH register. + [0:0] + read-only + + + + + CTR_HIT + 0x0000000c + Cache Hit counter + 0x00000000 + + + CTR_HIT + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + CTR_ACC + 0x00000010 + Cache Access counter + 0x00000000 + + + CTR_ACC + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + STREAM_ADDR + 0x00000014 + FIFO stream address + 0x00000000 + + + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + + STREAM_CTR + 0x00000018 + FIFO stream control + 0x00000000 + + + STREAM_CTR + Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + + STREAM_FIFO + 0x0000001c + FIFO stream data + 0x00000000 + + + STREAM_FIFO + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + [31:0] + read-only + modify + + + + + + + SYSCFG + Register block for various chip control signals + 0x40004000 + + 0 + 28 + registers + + + + PROC0_NMI_MASK + 0x00000000 + Processor core 0 NMI source mask + 0x00000000 + + + PROC0_NMI_MASK + Set a bit high to enable NMI from that IRQ + [31:0] + read-write + + + + + PROC1_NMI_MASK + 0x00000004 + Processor core 1 NMI source mask + 0x00000000 + + + PROC1_NMI_MASK + Set a bit high to enable NMI from that IRQ + [31:0] + read-write + + + + + PROC_CONFIG + 0x00000008 + Configuration for processors + 0x10000000 + + + PROC1_DAP_INSTID + Configure proc1 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP + [31:28] + read-write + + + PROC0_DAP_INSTID + Configure proc0 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP + [27:24] + read-write + + + PROC1_HALTED + Indication that proc1 has halted + [1:1] + read-only + + + PROC0_HALTED + Indication that proc0 has halted + [0:0] + read-only + + + + + PROC_IN_SYNC_BYPASS + 0x0000000c + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...29. + 0x00000000 + + + PROC_IN_SYNC_BYPASS + [29:0] + read-write + + + + + PROC_IN_SYNC_BYPASS_HI + 0x00000010 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 30...35 (the QSPI IOs). + 0x00000000 + + + PROC_IN_SYNC_BYPASS_HI + [5:0] + read-write + + + + + DBGFORCE + 0x00000014 + Directly control the SWD debug port of either processor + 0x00000066 + + + PROC1_ATTACH + Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. + [7:7] + read-write + + + PROC1_SWCLK + Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + [6:6] + read-write + + + PROC1_SWDI + Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + [5:5] + read-write + + + PROC1_SWDO + Observe the value of processor 1 SWDIO output. + [4:4] + read-only + + + PROC0_ATTACH + Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. + [3:3] + read-write + + + PROC0_SWCLK + Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + [2:2] + read-write + + + PROC0_SWDI + Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + [1:1] + read-write + + + PROC0_SWDO + Observe the value of processor 0 SWDIO output. + [0:0] + read-only + + + + + MEMPOWERDOWN + 0x00000018 + Control power downs to memories. Set high to power down memories. + Use with extreme caution + 0x00000000 + + + ROM + [7:7] + read-write + + + USB + [6:6] + read-write + + + SRAM5 + [5:5] + read-write + + + SRAM4 + [4:4] + read-write + + + SRAM3 + [3:3] + read-write + + + SRAM2 + [2:2] + read-write + + + SRAM1 + [1:1] + read-write + + + SRAM0 + [0:0] + read-write + + + + + + + XOSC + Controls the crystal oscillator + 0x40024000 + + 0 + 32 + registers + + + + CTRL + 0x00000000 + Crystal Oscillator Control + 0x00000000 + + + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. + [11:0] + read-write + + + 1_15MHZ + 2720 + + + RESERVED_1 + 2721 + + + RESERVED_2 + 2722 + + + RESERVED_3 + 2723 + + + + + + + STATUS + 0x00000004 + Crystal Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting, always reads 0 + [1:0] + read-only + + + 1_15MHZ + 0 + + + RESERVED_1 + 1 + + + RESERVED_2 + 2 + + + RESERVED_3 + 3 + + + + + + + DORMANT + 0x00000008 + Crystal Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: stop the PLLs before selecting dormant mode + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + STARTUP + 0x0000000c + Controls the startup delay + 0x00000000 + + + X4 + Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write + + + + + COUNT + 0x0000001c + A down counter running at the xosc frequency which counts to zero and stops. + To start the counter write a non-zero value. + Can be used for short software pauses when setting up time sensitive hardware. + 0x00000000 + + + COUNT + [7:0] + read-write + + + + + + + PLL_SYS + 0x40028000 + + 0 + 16 + registers + + + + CS + 0x00000000 + Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz + 0x00000001 + + + LOCK + PLL is locked + [31:31] + read-only + + + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] + read-write + + + REFDIV + Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] + read-write + + + + + PWR + 0x00000004 + Controls the PLL power modes. + 0x0000002d + + + VCOPD + PLL VCO powerdown + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown + To save power set high when PLL output not required or bypass=1. + [3:3] + read-write + + + DSMPD + PLL DSM powerdown + Nothing is achieved by setting this low. + [2:2] + read-write + + + PD + PLL powerdown + To save power set high when PLL output not required. + [0:0] + read-write + + + + + FBDIV_INT + 0x00000008 + Feedback divisor + (note: this PLL does not support fractional division) + 0x00000000 + + + FBDIV_INT + see ctrl reg description for constraints + [11:0] + read-write + + + + + PRIM + 0x0000000c + Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 + 0x00077000 + + + POSTDIV1 + divide by 1-7 + [18:16] + read-write + + + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + + + PLL_USB + 0x4002c000 + + + UART0 + 0x40034000 + + 0 + 4096 + registers + + + UART0_IRQ + 20 + + + + UARTDR + 0x00000000 + Data Register, UARTDR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] + read-only + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] + read-only + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] + read-only + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] + read-only + + + DATA + Receive (read) data character. Transmit (write) data character. + [7:0] + read-write + modify + + + + + UARTRSR + 0x00000004 + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + [3:3] + read-write + oneToClear + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + [2:2] + read-write + oneToClear + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [1:1] + read-write + oneToClear + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [0:0] + read-write + oneToClear + + + + + UARTFR + 0x00000018 + Flag Register, UARTFR + 0x00000090 + + + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] + read-only + + + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] + read-only + + + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] + read-only + + + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] + read-only + + + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + [3:3] + read-only + + + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + [2:2] + read-only + + + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + [1:1] + read-only + + + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + [0:0] + read-only + + + + + UARTILPR + 0x00000020 + IrDA Low-Power Counter Register, UARTILPR + 0x00000000 + + + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] + read-write + + + + + UARTIBRD + 0x00000024 + Integer Baud Rate Register, UARTIBRD + 0x00000000 + + + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] + read-write + + + + + UARTFBRD + 0x00000028 + Fractional Baud Rate Register, UARTFBRD + 0x00000000 + + + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write + + + + + UARTLCR_H + 0x0000002c + Line Control Register, UARTLCR_H + 0x00000000 + + + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write + + + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + + + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write + + + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write + + + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write + + + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write + + + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write + + + + + UARTCR + 0x00000030 + Control Register, UARTCR + 0x00000300 + + + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write + + + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write + + + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + [10:10] + read-write + + + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + [9:9] + read-write + + + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + [8:8] + read-write + + + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + [7:7] + read-write + + + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] + read-write + + + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] + read-write + + + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] + read-write + + + + + UARTIFLS + 0x00000034 + Interrupt FIFO Level Select Register, UARTIFLS + 0x00000012 + + + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] + read-write + + + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] + read-write + + + + + UARTIMSC + 0x00000038 + Interrupt Mask Set/Clear Register, UARTIMSC + 0x00000000 + + + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + [10:10] + read-write + + + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] + read-write + + + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] + read-write + + + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write + + + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] + read-write + + + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] + read-write + + + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] + read-write + + + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] + read-write + + + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] + read-write + + + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] + read-write + + + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] + read-write + + + + + UARTRIS + 0x0000003c + Raw Interrupt Status Register, UARTRIS + 0x00000000 + + + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + [6:6] + read-only + + + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTMIS + 0x00000040 + Masked Interrupt Status Register, UARTMIS + 0x00000000 + + + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + 0x00000044 + Interrupt Clear Register, UARTICR + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + [10:10] + read-write + oneToClear + + + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. + [9:9] + read-write + oneToClear + + + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + [8:8] + read-write + oneToClear + + + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + [7:7] + read-write + oneToClear + + + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + [6:6] + read-write + oneToClear + + + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + [5:5] + read-write + oneToClear + + + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. + [4:4] + read-write + oneToClear + + + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + [3:3] + read-write + oneToClear + + + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + [2:2] + read-write + oneToClear + + + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + [1:1] + read-write + oneToClear + + + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + [0:0] + read-write + oneToClear + + + + + UARTDMACR + 0x00000048 + DMA Control Register, UARTDMACR + 0x00000000 + + + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write + + + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + UARTPERIPHID0 + 0x00000fe0 + UARTPeriphID0 Register + 0x00000011 + + + PARTNUMBER0 + These bits read back as 0x11 + [7:0] + read-only + + + + + UARTPERIPHID1 + 0x00000fe4 + UARTPeriphID1 Register + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + UARTPERIPHID2 + 0x00000fe8 + UARTPeriphID2 Register + 0x00000034 + + + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + UARTPERIPHID3 + 0x00000fec + UARTPeriphID3 Register + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + UARTPCELLID0 + 0x00000ff0 + UARTPCellID0 Register + 0x0000000d + + + UARTPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + UARTPCELLID1 + 0x00000ff4 + UARTPCellID1 Register + 0x000000f0 + + + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + UARTPCELLID2 + 0x00000ff8 + UARTPCellID2 Register + 0x00000005 + + + UARTPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + UARTPCELLID3 + 0x00000ffc + UARTPCellID3 Register + 0x000000b1 + + + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + UART1 + 0x40038000 + + UART1_IRQ + 21 + + + + ROSC + 0x40060000 + + 0 + 36 + registers + + + + CTRL + 0x00000000 + Ring Oscillator control + 0x00000aa0 + + + ENABLE + On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 2 to 7 + HIGH uses stages 4 to 7 + TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + + + + + FREQA + 0x00000004 + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS3 + Stage 3 drive strength + [14:12] + read-write + + + DS2 + Stage 2 drive strength + [10:8] + read-write + + + DS1 + Stage 1 drive strength + [6:4] + read-write + + + DS0 + Stage 0 drive strength + [2:0] + read-write + + + + + FREQB + 0x00000008 + For a detailed description see freqa register + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write + + + + + DORMANT + 0x0000000c + Ring Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + DIV + 0x00000010 + Controls the output divider + 0x00000000 + + + DIV + set to 0xaa0 + div where + div = 0 divides by 32 + div = 1-31 divides by div + any other value sets div=31 + this register resets to div=16 + [11:0] + read-write + + + PASS + 2720 + + + + + + + PHASE + 0x00000014 + Controls the phase shifted output + 0x00000008 + + + PASSWD + set to 0xaa + any other value enables the output with shift=0 + [11:4] + read-write + + + ENABLE + enable the phase-shifted output + this can be changed on-the-fly + [3:3] + read-write + + + FLIP + invert the phase-shifted output + this is ignored when div=1 + [2:2] + read-write + + + SHIFT + phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1 + [1:0] + read-write + + + + + STATUS + 0x00000018 + Ring Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + [24:24] + read-write + oneToClear + + + DIV_RUNNING + post-divider is running + this resets to 0 but transitions to 1 during chip startup + [16:16] + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup + [12:12] + read-only + + + + + RANDOMBIT + 0x0000001c + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x00000001 + + + RANDOMBIT + [0:0] + read-only + + + + + COUNT + 0x00000020 + A down counter running at the ROSC frequency which counts to zero and stops. + To start the counter write a non-zero value. + Can be used for short software pauses when setting up time sensitive hardware. + 0x00000000 + + + COUNT + [7:0] + read-write + + + + + + + WATCHDOG + 0x40058000 + + 0 + 48 + registers + + + + CTRL + 0x00000000 + Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + 0x07000000 + + + TRIGGER + Trigger a watchdog reset + [31:31] + write-only + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] + read-write + + + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] + read-write + + + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write + + + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write + + + TIME + Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered + [23:0] + read-only + + + + + LOAD + 0x00000004 + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). + 0x00000000 + + + LOAD + [23:0] + write-only + + + + + REASON + 0x00000008 + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + 0x00000000 + + + FORCE + [1:1] + read-only + + + TIMER + [0:0] + read-only + + + + + SCRATCH0 + 0x0000000c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x00000010 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x00000014 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x00000018 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x0000001c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x00000020 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x00000024 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x00000028 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + TICK + 0x0000002c + Controls the tick generator + 0x00000200 + + + COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [19:11] + read-only + + + RUNNING + Is the tick generator running? + [10:10] + read-only + + + ENABLE + start / stop tick generation + [9:9] + read-write + + + CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + + + DMA + DMA with separate read and write masters + 0x50000000 + + 0 + 2760 + registers + + + DMA_IRQ_0 + 11 + + + DMA_IRQ_1 + 12 + + + + CH0_READ_ADDR + 0x00000000 + DMA Channel 0 Read Address pointer + 0x00000000 + + + CH0_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH0_WRITE_ADDR + 0x00000004 + DMA Channel 0 Write Address pointer + 0x00000000 + + + CH0_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH0_TRANS_COUNT + 0x00000008 + DMA Channel 0 Transfer Count + 0x00000000 + + + CH0_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH0_CTRL_TRIG + 0x0000000c + DMA Channel 0 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH0_AL1_CTRL + 0x00000010 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL1_CTRL + [31:0] + read-write + + + + + CH0_AL1_READ_ADDR + 0x00000014 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL1_READ_ADDR + [31:0] + read-write + + + + + CH0_AL1_WRITE_ADDR + 0x00000018 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL1_TRANS_COUNT_TRIG + 0x0000001c + Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH0_AL2_CTRL + 0x00000020 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL2_CTRL + [31:0] + read-write + + + + + CH0_AL2_TRANS_COUNT + 0x00000024 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL2_READ_ADDR + 0x00000028 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL2_READ_ADDR + [31:0] + read-write + + + + + CH0_AL2_WRITE_ADDR_TRIG + 0x0000002c + Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH0_AL3_CTRL + 0x00000030 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL3_CTRL + [31:0] + read-write + + + + + CH0_AL3_WRITE_ADDR + 0x00000034 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL3_TRANS_COUNT + 0x00000038 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL3_READ_ADDR_TRIG + 0x0000003c + Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH1_READ_ADDR + 0x00000040 + DMA Channel 1 Read Address pointer + 0x00000000 + + + CH1_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH1_WRITE_ADDR + 0x00000044 + DMA Channel 1 Write Address pointer + 0x00000000 + + + CH1_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH1_TRANS_COUNT + 0x00000048 + DMA Channel 1 Transfer Count + 0x00000000 + + + CH1_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH1_CTRL_TRIG + 0x0000004c + DMA Channel 1 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH1_AL1_CTRL + 0x00000050 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL1_CTRL + [31:0] + read-write + + + + + CH1_AL1_READ_ADDR + 0x00000054 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL1_READ_ADDR + [31:0] + read-write + + + + + CH1_AL1_WRITE_ADDR + 0x00000058 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL1_TRANS_COUNT_TRIG + 0x0000005c + Alias for channel 1 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH1_AL2_CTRL + 0x00000060 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL2_CTRL + [31:0] + read-write + + + + + CH1_AL2_TRANS_COUNT + 0x00000064 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL2_READ_ADDR + 0x00000068 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL2_READ_ADDR + [31:0] + read-write + + + + + CH1_AL2_WRITE_ADDR_TRIG + 0x0000006c + Alias for channel 1 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH1_AL3_CTRL + 0x00000070 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL3_CTRL + [31:0] + read-write + + + + + CH1_AL3_WRITE_ADDR + 0x00000074 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL3_TRANS_COUNT + 0x00000078 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL3_READ_ADDR_TRIG + 0x0000007c + Alias for channel 1 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH2_READ_ADDR + 0x00000080 + DMA Channel 2 Read Address pointer + 0x00000000 + + + CH2_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH2_WRITE_ADDR + 0x00000084 + DMA Channel 2 Write Address pointer + 0x00000000 + + + CH2_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH2_TRANS_COUNT + 0x00000088 + DMA Channel 2 Transfer Count + 0x00000000 + + + CH2_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH2_CTRL_TRIG + 0x0000008c + DMA Channel 2 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH2_AL1_CTRL + 0x00000090 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL1_CTRL + [31:0] + read-write + + + + + CH2_AL1_READ_ADDR + 0x00000094 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL1_READ_ADDR + [31:0] + read-write + + + + + CH2_AL1_WRITE_ADDR + 0x00000098 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL1_TRANS_COUNT_TRIG + 0x0000009c + Alias for channel 2 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH2_AL2_CTRL + 0x000000a0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL2_CTRL + [31:0] + read-write + + + + + CH2_AL2_TRANS_COUNT + 0x000000a4 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL2_READ_ADDR + 0x000000a8 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL2_READ_ADDR + [31:0] + read-write + + + + + CH2_AL2_WRITE_ADDR_TRIG + 0x000000ac + Alias for channel 2 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH2_AL3_CTRL + 0x000000b0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL3_CTRL + [31:0] + read-write + + + + + CH2_AL3_WRITE_ADDR + 0x000000b4 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL3_TRANS_COUNT + 0x000000b8 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL3_READ_ADDR_TRIG + 0x000000bc + Alias for channel 2 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH3_READ_ADDR + 0x000000c0 + DMA Channel 3 Read Address pointer + 0x00000000 + + + CH3_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH3_WRITE_ADDR + 0x000000c4 + DMA Channel 3 Write Address pointer + 0x00000000 + + + CH3_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH3_TRANS_COUNT + 0x000000c8 + DMA Channel 3 Transfer Count + 0x00000000 + + + CH3_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH3_CTRL_TRIG + 0x000000cc + DMA Channel 3 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH3_AL1_CTRL + 0x000000d0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL1_CTRL + [31:0] + read-write + + + + + CH3_AL1_READ_ADDR + 0x000000d4 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL1_READ_ADDR + [31:0] + read-write + + + + + CH3_AL1_WRITE_ADDR + 0x000000d8 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL1_TRANS_COUNT_TRIG + 0x000000dc + Alias for channel 3 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH3_AL2_CTRL + 0x000000e0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL2_CTRL + [31:0] + read-write + + + + + CH3_AL2_TRANS_COUNT + 0x000000e4 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL2_READ_ADDR + 0x000000e8 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL2_READ_ADDR + [31:0] + read-write + + + + + CH3_AL2_WRITE_ADDR_TRIG + 0x000000ec + Alias for channel 3 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH3_AL3_CTRL + 0x000000f0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL3_CTRL + [31:0] + read-write + + + + + CH3_AL3_WRITE_ADDR + 0x000000f4 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL3_TRANS_COUNT + 0x000000f8 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL3_READ_ADDR_TRIG + 0x000000fc + Alias for channel 3 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH4_READ_ADDR + 0x00000100 + DMA Channel 4 Read Address pointer + 0x00000000 + + + CH4_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH4_WRITE_ADDR + 0x00000104 + DMA Channel 4 Write Address pointer + 0x00000000 + + + CH4_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH4_TRANS_COUNT + 0x00000108 + DMA Channel 4 Transfer Count + 0x00000000 + + + CH4_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH4_CTRL_TRIG + 0x0000010c + DMA Channel 4 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH4_AL1_CTRL + 0x00000110 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL1_CTRL + [31:0] + read-write + + + + + CH4_AL1_READ_ADDR + 0x00000114 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL1_READ_ADDR + [31:0] + read-write + + + + + CH4_AL1_WRITE_ADDR + 0x00000118 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL1_TRANS_COUNT_TRIG + 0x0000011c + Alias for channel 4 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH4_AL2_CTRL + 0x00000120 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL2_CTRL + [31:0] + read-write + + + + + CH4_AL2_TRANS_COUNT + 0x00000124 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL2_READ_ADDR + 0x00000128 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL2_READ_ADDR + [31:0] + read-write + + + + + CH4_AL2_WRITE_ADDR_TRIG + 0x0000012c + Alias for channel 4 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH4_AL3_CTRL + 0x00000130 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL3_CTRL + [31:0] + read-write + + + + + CH4_AL3_WRITE_ADDR + 0x00000134 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL3_TRANS_COUNT + 0x00000138 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL3_READ_ADDR_TRIG + 0x0000013c + Alias for channel 4 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH5_READ_ADDR + 0x00000140 + DMA Channel 5 Read Address pointer + 0x00000000 + + + CH5_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH5_WRITE_ADDR + 0x00000144 + DMA Channel 5 Write Address pointer + 0x00000000 + + + CH5_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH5_TRANS_COUNT + 0x00000148 + DMA Channel 5 Transfer Count + 0x00000000 + + + CH5_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH5_CTRL_TRIG + 0x0000014c + DMA Channel 5 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH5_AL1_CTRL + 0x00000150 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL1_CTRL + [31:0] + read-write + + + + + CH5_AL1_READ_ADDR + 0x00000154 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL1_READ_ADDR + [31:0] + read-write + + + + + CH5_AL1_WRITE_ADDR + 0x00000158 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL1_TRANS_COUNT_TRIG + 0x0000015c + Alias for channel 5 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH5_AL2_CTRL + 0x00000160 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL2_CTRL + [31:0] + read-write + + + + + CH5_AL2_TRANS_COUNT + 0x00000164 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL2_READ_ADDR + 0x00000168 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL2_READ_ADDR + [31:0] + read-write + + + + + CH5_AL2_WRITE_ADDR_TRIG + 0x0000016c + Alias for channel 5 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH5_AL3_CTRL + 0x00000170 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL3_CTRL + [31:0] + read-write + + + + + CH5_AL3_WRITE_ADDR + 0x00000174 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL3_TRANS_COUNT + 0x00000178 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL3_READ_ADDR_TRIG + 0x0000017c + Alias for channel 5 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH6_READ_ADDR + 0x00000180 + DMA Channel 6 Read Address pointer + 0x00000000 + + + CH6_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH6_WRITE_ADDR + 0x00000184 + DMA Channel 6 Write Address pointer + 0x00000000 + + + CH6_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH6_TRANS_COUNT + 0x00000188 + DMA Channel 6 Transfer Count + 0x00000000 + + + CH6_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH6_CTRL_TRIG + 0x0000018c + DMA Channel 6 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH6_AL1_CTRL + 0x00000190 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL1_CTRL + [31:0] + read-write + + + + + CH6_AL1_READ_ADDR + 0x00000194 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL1_READ_ADDR + [31:0] + read-write + + + + + CH6_AL1_WRITE_ADDR + 0x00000198 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL1_TRANS_COUNT_TRIG + 0x0000019c + Alias for channel 6 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH6_AL2_CTRL + 0x000001a0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL2_CTRL + [31:0] + read-write + + + + + CH6_AL2_TRANS_COUNT + 0x000001a4 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL2_READ_ADDR + 0x000001a8 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL2_READ_ADDR + [31:0] + read-write + + + + + CH6_AL2_WRITE_ADDR_TRIG + 0x000001ac + Alias for channel 6 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH6_AL3_CTRL + 0x000001b0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL3_CTRL + [31:0] + read-write + + + + + CH6_AL3_WRITE_ADDR + 0x000001b4 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL3_TRANS_COUNT + 0x000001b8 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL3_READ_ADDR_TRIG + 0x000001bc + Alias for channel 6 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH7_READ_ADDR + 0x000001c0 + DMA Channel 7 Read Address pointer + 0x00000000 + + + CH7_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH7_WRITE_ADDR + 0x000001c4 + DMA Channel 7 Write Address pointer + 0x00000000 + + + CH7_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH7_TRANS_COUNT + 0x000001c8 + DMA Channel 7 Transfer Count + 0x00000000 + + + CH7_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH7_CTRL_TRIG + 0x000001cc + DMA Channel 7 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH7_AL1_CTRL + 0x000001d0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL1_CTRL + [31:0] + read-write + + + + + CH7_AL1_READ_ADDR + 0x000001d4 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL1_READ_ADDR + [31:0] + read-write + + + + + CH7_AL1_WRITE_ADDR + 0x000001d8 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL1_TRANS_COUNT_TRIG + 0x000001dc + Alias for channel 7 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH7_AL2_CTRL + 0x000001e0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL2_CTRL + [31:0] + read-write + + + + + CH7_AL2_TRANS_COUNT + 0x000001e4 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL2_READ_ADDR + 0x000001e8 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL2_READ_ADDR + [31:0] + read-write + + + + + CH7_AL2_WRITE_ADDR_TRIG + 0x000001ec + Alias for channel 7 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH7_AL3_CTRL + 0x000001f0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL3_CTRL + [31:0] + read-write + + + + + CH7_AL3_WRITE_ADDR + 0x000001f4 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL3_TRANS_COUNT + 0x000001f8 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL3_READ_ADDR_TRIG + 0x000001fc + Alias for channel 7 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH8_READ_ADDR + 0x00000200 + DMA Channel 8 Read Address pointer + 0x00000000 + + + CH8_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH8_WRITE_ADDR + 0x00000204 + DMA Channel 8 Write Address pointer + 0x00000000 + + + CH8_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH8_TRANS_COUNT + 0x00000208 + DMA Channel 8 Transfer Count + 0x00000000 + + + CH8_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH8_CTRL_TRIG + 0x0000020c + DMA Channel 8 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH8_AL1_CTRL + 0x00000210 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL1_CTRL + [31:0] + read-write + + + + + CH8_AL1_READ_ADDR + 0x00000214 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL1_READ_ADDR + [31:0] + read-write + + + + + CH8_AL1_WRITE_ADDR + 0x00000218 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL1_TRANS_COUNT_TRIG + 0x0000021c + Alias for channel 8 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH8_AL2_CTRL + 0x00000220 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL2_CTRL + [31:0] + read-write + + + + + CH8_AL2_TRANS_COUNT + 0x00000224 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL2_READ_ADDR + 0x00000228 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL2_READ_ADDR + [31:0] + read-write + + + + + CH8_AL2_WRITE_ADDR_TRIG + 0x0000022c + Alias for channel 8 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH8_AL3_CTRL + 0x00000230 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL3_CTRL + [31:0] + read-write + + + + + CH8_AL3_WRITE_ADDR + 0x00000234 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL3_TRANS_COUNT + 0x00000238 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL3_READ_ADDR_TRIG + 0x0000023c + Alias for channel 8 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH9_READ_ADDR + 0x00000240 + DMA Channel 9 Read Address pointer + 0x00000000 + + + CH9_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH9_WRITE_ADDR + 0x00000244 + DMA Channel 9 Write Address pointer + 0x00000000 + + + CH9_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH9_TRANS_COUNT + 0x00000248 + DMA Channel 9 Transfer Count + 0x00000000 + + + CH9_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH9_CTRL_TRIG + 0x0000024c + DMA Channel 9 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH9_AL1_CTRL + 0x00000250 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL1_CTRL + [31:0] + read-write + + + + + CH9_AL1_READ_ADDR + 0x00000254 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL1_READ_ADDR + [31:0] + read-write + + + + + CH9_AL1_WRITE_ADDR + 0x00000258 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL1_TRANS_COUNT_TRIG + 0x0000025c + Alias for channel 9 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH9_AL2_CTRL + 0x00000260 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL2_CTRL + [31:0] + read-write + + + + + CH9_AL2_TRANS_COUNT + 0x00000264 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL2_READ_ADDR + 0x00000268 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL2_READ_ADDR + [31:0] + read-write + + + + + CH9_AL2_WRITE_ADDR_TRIG + 0x0000026c + Alias for channel 9 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH9_AL3_CTRL + 0x00000270 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL3_CTRL + [31:0] + read-write + + + + + CH9_AL3_WRITE_ADDR + 0x00000274 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL3_TRANS_COUNT + 0x00000278 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL3_READ_ADDR_TRIG + 0x0000027c + Alias for channel 9 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH10_READ_ADDR + 0x00000280 + DMA Channel 10 Read Address pointer + 0x00000000 + + + CH10_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH10_WRITE_ADDR + 0x00000284 + DMA Channel 10 Write Address pointer + 0x00000000 + + + CH10_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH10_TRANS_COUNT + 0x00000288 + DMA Channel 10 Transfer Count + 0x00000000 + + + CH10_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH10_CTRL_TRIG + 0x0000028c + DMA Channel 10 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH10_AL1_CTRL + 0x00000290 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL1_CTRL + [31:0] + read-write + + + + + CH10_AL1_READ_ADDR + 0x00000294 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL1_READ_ADDR + [31:0] + read-write + + + + + CH10_AL1_WRITE_ADDR + 0x00000298 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL1_TRANS_COUNT_TRIG + 0x0000029c + Alias for channel 10 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH10_AL2_CTRL + 0x000002a0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL2_CTRL + [31:0] + read-write + + + + + CH10_AL2_TRANS_COUNT + 0x000002a4 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL2_READ_ADDR + 0x000002a8 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL2_READ_ADDR + [31:0] + read-write + + + + + CH10_AL2_WRITE_ADDR_TRIG + 0x000002ac + Alias for channel 10 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH10_AL3_CTRL + 0x000002b0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL3_CTRL + [31:0] + read-write + + + + + CH10_AL3_WRITE_ADDR + 0x000002b4 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL3_TRANS_COUNT + 0x000002b8 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL3_READ_ADDR_TRIG + 0x000002bc + Alias for channel 10 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH11_READ_ADDR + 0x000002c0 + DMA Channel 11 Read Address pointer + 0x00000000 + + + CH11_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH11_WRITE_ADDR + 0x000002c4 + DMA Channel 11 Write Address pointer + 0x00000000 + + + CH11_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH11_TRANS_COUNT + 0x000002c8 + DMA Channel 11 Transfer Count + 0x00000000 + + + CH11_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] + read-write + + + + + CH11_CTRL_TRIG + 0x000002cc + DMA Channel 11 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + SPI0_TX + 16 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 17 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 18 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 19 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 20 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 21 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 22 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 23 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 24 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 25 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 26 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 27 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 28 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 29 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 30 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 31 + Select PWM Counter 7's Wrap Value as TREQ + + + I2C0_TX + 32 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 33 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 34 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 35 + Select I2C1's RX FIFO as TREQ + + + ADC + 36 + Select the ADC as TREQ + + + XIP_STREAM + 37 + Select the XIP Streaming FIFO as TREQ + + + XIP_SSITX + 38 + Select the XIP SSI TX FIFO as TREQ + + + XIP_SSIRX + 39 + Select the XIP SSI RX FIFO as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + [14:11] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH11_AL1_CTRL + 0x000002d0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL1_CTRL + [31:0] + read-write + + + + + CH11_AL1_READ_ADDR + 0x000002d4 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL1_READ_ADDR + [31:0] + read-write + + + + + CH11_AL1_WRITE_ADDR + 0x000002d8 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL1_TRANS_COUNT_TRIG + 0x000002dc + Alias for channel 11 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH11_AL2_CTRL + 0x000002e0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL2_CTRL + [31:0] + read-write + + + + + CH11_AL2_TRANS_COUNT + 0x000002e4 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL2_READ_ADDR + 0x000002e8 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL2_READ_ADDR + [31:0] + read-write + + + + + CH11_AL2_WRITE_ADDR_TRIG + 0x000002ec + Alias for channel 11 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH11_AL3_CTRL + 0x000002f0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL3_CTRL + [31:0] + read-write + + + + + CH11_AL3_WRITE_ADDR + 0x000002f4 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL3_TRANS_COUNT + 0x000002f8 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL3_READ_ADDR_TRIG + 0x000002fc + Alias for channel 11 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + INTR + 0x00000400 + Interrupt Status (raw) + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. + + Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. + + This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. + + It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. + [15:0] + read-write + oneToClear + + + + + INTE0 + 0x00000404 + Interrupt Enables for IRQ 0 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + [15:0] + read-write + + + + + INTF0 + 0x00000408 + Force Interrupts + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + 0x0000040c + Interrupt Status for IRQ 0 + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + [15:0] + read-write + oneToClear + + + + + INTR1 + 0x00000410 + Interrupt Status (raw) + 0x00000000 + + + INTR1 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. + + Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. + + This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. + + It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. + [15:0] + read-write + oneToClear + + + + + INTE1 + 0x00000414 + Interrupt Enables for IRQ 1 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + [15:0] + read-write + + + + + INTF1 + 0x00000418 + Force Interrupts for IRQ 1 + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS1 + 0x0000041c + Interrupt Status (masked) for IRQ 1 + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + [15:0] + read-write + oneToClear + + + + + TIMER0 + 0x00000420 + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + 0x00000424 + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + 0x00000428 + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + 0x0000042c + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + 0x00000430 + Trigger one or more channels simultaneously + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + write-only + + + + + SNIFF_CTRL + 0x00000434 + Sniffer Control + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + 0 + Calculate a CRC-32 (IEEE802.3 polynomial) + + + CRC32R + 1 + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + + + CRC16 + 2 + Calculate a CRC-16-CCITT + + + CRC16R + 3 + Calculate a CRC-16-CCITT with bit reversed data + + + EVEN + 14 + XOR reduction over all data. == 1 if the total 1 population count is odd. + + + SUM + 15 + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + 0x00000438 + Data accumulator for sniff hardware + 0x00000000 + + + SNIFF_DATA + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + [31:0] + read-write + + + + + FIFO_LEVELS + 0x00000440 + Debug RAF, WAF, TDF levels + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + 0x00000444 + Abort an in-progress transfer sequence on one or more channels + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + write-only + + + + + N_CHANNELS + 0x00000448 + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + CH0_DBG_CTDREQ + 0x00000800 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + 0x00000804 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH0_DBG_TCR + [31:0] + read-only + + + + + CH1_DBG_CTDREQ + 0x00000840 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + 0x00000844 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH1_DBG_TCR + [31:0] + read-only + + + + + CH2_DBG_CTDREQ + 0x00000880 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + 0x00000884 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH2_DBG_TCR + [31:0] + read-only + + + + + CH3_DBG_CTDREQ + 0x000008c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + 0x000008c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH3_DBG_TCR + [31:0] + read-only + + + + + CH4_DBG_CTDREQ + 0x00000900 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + 0x00000904 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH4_DBG_TCR + [31:0] + read-only + + + + + CH5_DBG_CTDREQ + 0x00000940 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + 0x00000944 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH5_DBG_TCR + [31:0] + read-only + + + + + CH6_DBG_CTDREQ + 0x00000980 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + 0x00000984 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH6_DBG_TCR + [31:0] + read-only + + + + + CH7_DBG_CTDREQ + 0x000009c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + 0x000009c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH7_DBG_TCR + [31:0] + read-only + + + + + CH8_DBG_CTDREQ + 0x00000a00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + 0x00000a04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH8_DBG_TCR + [31:0] + read-only + + + + + CH9_DBG_CTDREQ + 0x00000a40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + 0x00000a44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH9_DBG_TCR + [31:0] + read-only + + + + + CH10_DBG_CTDREQ + 0x00000a80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + 0x00000a84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH10_DBG_TCR + [31:0] + read-only + + + + + CH11_DBG_CTDREQ + 0x00000ac0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + 0x00000ac4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH11_DBG_TCR + [31:0] + read-only + + + + + + + TIMER + Controls time and alarms + time is a 64 bit value indicating the time in usec since power-on + timeh is the top 32 bits of time & timel is the bottom 32 bits + to change time write to timelw before timehw + to read time read from timelr before timehr + An alarm is set by setting alarm_enable and writing to the corresponding alarm register + When an alarm is pending, the corresponding alarm_running signal will be high + An alarm can be cancelled before it has finished by clearing the alarm_enable + When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared + To clear the interrupt write a 1 to the corresponding alarm_irq + 0x40054000 + + 0 + 68 + registers + + + TIMER_IRQ_0 + 0 + + + TIMER_IRQ_1 + 1 + + + TIMER_IRQ_2 + 2 + + + TIMER_IRQ_3 + 3 + + + + TIMEHW + 0x00000000 + Write to bits 63:32 of time + always write timelw before timehw + 0x00000000 + + + TIMEHW + [31:0] + write-only + + + + + TIMELW + 0x00000004 + Write to bits 31:0 of time + writes do not get copied to time until timehw is written + 0x00000000 + + + TIMELW + [31:0] + write-only + + + + + TIMEHR + 0x00000008 + Read from bits 63:32 of time + always read timelr before timehr + 0x00000000 + + + TIMEHR + [31:0] + read-only + + + + + TIMELR + 0x0000000c + Read from bits 31:0 of time + 0x00000000 + + + TIMELR + [31:0] + read-only + modify + + + + + ALARM0 + 0x00000010 + Arm alarm 0, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM0 + [31:0] + read-write + + + + + ALARM1 + 0x00000014 + Arm alarm 1, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM1 + [31:0] + read-write + + + + + ALARM2 + 0x00000018 + Arm alarm 2, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM2 + [31:0] + read-write + + + + + ALARM3 + 0x0000001c + Arm alarm 3, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM3 + [31:0] + read-write + + + + + ARMED + 0x00000020 + Indicates the armed/disarmed status of each alarm. + A write to the corresponding ALARMx register arms the alarm. + Alarms automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + 0x00000024 + Raw read from bits 63:32 of time (no side effects) + 0x00000000 + + + TIMERAWH + [31:0] + read-only + + + + + TIMERAWL + 0x00000028 + Raw read from bits 31:0 of time (no side effects) + 0x00000000 + + + TIMERAWL + [31:0] + read-only + + + + + DBGPAUSE + 0x0000002c + Set bits high to enable pause when the corresponding debug ports are active + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + 0x00000030 + Set high to pause the timer + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + INTR + 0x00000034 + Raw Interrupts + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000038 + Interrupt Enable + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + 0x0000003c + Interrupt Force + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + 0x00000040 + Interrupt status after masking & forcing + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + PWM + Simple PWM + 0x40050000 + + 0 + 180 + registers + + + PWM_IRQ_WRAP + 4 + + + + CH0_CSR + 0x00000000 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH0_DIV + 0x00000004 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH0_CTR + 0x00000008 + Direct access to the PWM counter + 0x00000000 + + + CH0_CTR + [15:0] + read-write + + + + + CH0_CC + 0x0000000c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH0_TOP + 0x00000010 + Counter wrap value + 0x0000ffff + + + CH0_TOP + [15:0] + read-write + + + + + CH1_CSR + 0x00000014 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH1_DIV + 0x00000018 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH1_CTR + 0x0000001c + Direct access to the PWM counter + 0x00000000 + + + CH1_CTR + [15:0] + read-write + + + + + CH1_CC + 0x00000020 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH1_TOP + 0x00000024 + Counter wrap value + 0x0000ffff + + + CH1_TOP + [15:0] + read-write + + + + + CH2_CSR + 0x00000028 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH2_DIV + 0x0000002c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH2_CTR + 0x00000030 + Direct access to the PWM counter + 0x00000000 + + + CH2_CTR + [15:0] + read-write + + + + + CH2_CC + 0x00000034 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH2_TOP + 0x00000038 + Counter wrap value + 0x0000ffff + + + CH2_TOP + [15:0] + read-write + + + + + CH3_CSR + 0x0000003c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH3_DIV + 0x00000040 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH3_CTR + 0x00000044 + Direct access to the PWM counter + 0x00000000 + + + CH3_CTR + [15:0] + read-write + + + + + CH3_CC + 0x00000048 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH3_TOP + 0x0000004c + Counter wrap value + 0x0000ffff + + + CH3_TOP + [15:0] + read-write + + + + + CH4_CSR + 0x00000050 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH4_DIV + 0x00000054 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH4_CTR + 0x00000058 + Direct access to the PWM counter + 0x00000000 + + + CH4_CTR + [15:0] + read-write + + + + + CH4_CC + 0x0000005c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH4_TOP + 0x00000060 + Counter wrap value + 0x0000ffff + + + CH4_TOP + [15:0] + read-write + + + + + CH5_CSR + 0x00000064 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH5_DIV + 0x00000068 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH5_CTR + 0x0000006c + Direct access to the PWM counter + 0x00000000 + + + CH5_CTR + [15:0] + read-write + + + + + CH5_CC + 0x00000070 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH5_TOP + 0x00000074 + Counter wrap value + 0x0000ffff + + + CH5_TOP + [15:0] + read-write + + + + + CH6_CSR + 0x00000078 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH6_DIV + 0x0000007c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH6_CTR + 0x00000080 + Direct access to the PWM counter + 0x00000000 + + + CH6_CTR + [15:0] + read-write + + + + + CH6_CC + 0x00000084 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH6_TOP + 0x00000088 + Counter wrap value + 0x0000ffff + + + CH6_TOP + [15:0] + read-write + + + + + CH7_CSR + 0x0000008c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH7_DIV + 0x00000090 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH7_CTR + 0x00000094 + Direct access to the PWM counter + 0x00000000 + + + CH7_CTR + [15:0] + read-write + + + + + CH7_CC + 0x00000098 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH7_TOP + 0x0000009c + Counter wrap value + 0x0000ffff + + + CH7_TOP + [15:0] + read-write + + + + + EN + 0x000000a0 + This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + 0x000000a4 + Raw Interrupts + 0x00000000 + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + INTE + 0x000000a8 + Interrupt Enable + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTF + 0x000000ac + Interrupt Force + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTS + 0x000000b0 + Interrupt status after masking & forcing + 0x00000000 + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + ADC + Control and data interface to SAR ADC + 0x4004c000 + + 0 + 36 + registers + + + ADC_IRQ_FIFO + 22 + + + + CS + 0x00000000 + ADC Control and Status + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel. + [20:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + [14:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + write-only + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock. + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + 0x00000004 + Result of most recent ADC conversion + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + 0x00000008 + FIFO control and status + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + 0x0000000c + Conversion result FIFO + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + modify + + + VAL + [11:0] + read-only + modify + + + + + DIV + 0x00000010 + Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + 0x00000014 + Raw Interrupts + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + 0x00000018 + Interrupt Enable + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + 0x0000001c + Interrupt Force + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + 0x00000020 + Interrupt status after masking & forcing + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + I2C0 + DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 + 0x40044000 + + 0 + 256 + registers + + + I2C0_IRQ + 23 + + + + IC_CON + 0x00000000 + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + 0 + Overflow when RX_FIFO is full + + + ENABLED + 1 + Hold bus when RX_FIFO is full + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + 0 + Default behaviour of TX_EMPTY interrupt + + + ENABLED + 1 + Controlled generation of TX_EMPTY interrupt + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + 0 + slave issues STOP_DET intr always + + + ENABLED + 1 + slave issues STOP_DET intr only if addressed + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + 0 + Slave mode is enabled + + + SLAVE_DISABLED + 1 + Slave mode is disabled + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + 0 + Master restart disabled + + + ENABLED + 1 + Master restart enabled + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + 0 + Master 7Bit addressing mode + + + ADDR_10BITS + 1 + Master 10Bit addressing mode + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + 0 + Slave 7Bit addressing + + + ADDR_10BITS + 1 + Slave 10Bit addressing + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + 1 + Standard Speed mode of operation + + + FAST + 2 + Fast or Fast Plus mode of operation + + + HIGH + 3 + High Speed mode of operation + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + 0 + Master mode is disabled + + + ENABLED + 1 + Master mode is enabled + + + + + + + IC_TAR + 0x00000004 + I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + 0 + Disables programming of GENERAL_CALL or START_BYTE transmission + + + ENABLED + 1 + Enables programming of GENERAL_CALL or START_BYTE transmission + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + 0 + GENERAL_CALL byte transmission + + + START_BYTE + 1 + START byte transmission + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + 0x00000008 + I2C Slave Address Register + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + 0x00000010 + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + 0 + Sequential data byte received + + + ACTIVE + 1 + Non sequential data byte received + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0 + [10:10] + write-only + + + DISABLE + 0 + Don't Issue RESTART before this command + + + ENABLE + 1 + Issue RESTART before this command + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + write-only + + + DISABLE + 0 + Don't Issue STOP after this command + + + ENABLE + 1 + Issue STOP after this command + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0 + [8:8] + write-only + + + WRITE + 0 + Master Write Command + + + READ + 1 + Master Read Command + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + 0x00000014 + Standard Speed I2C Clock SCL High Count Register + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + 0x00000018 + Standard Speed I2C Clock SCL Low Count Register + 0x0000002f + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + 0x0000001c + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + 0x00000020 + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x0000000d + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + 0x0000002c + I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + R_RESTART_DET interrupt is inactive + + + ACTIVE + 1 + R_RESTART_DET interrupt is active + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + R_GEN_CALL interrupt is inactive + + + ACTIVE + 1 + R_GEN_CALL interrupt is active + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + R_START_DET interrupt is inactive + + + ACTIVE + 1 + R_START_DET interrupt is active + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + R_STOP_DET interrupt is inactive + + + ACTIVE + 1 + R_STOP_DET interrupt is active + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + R_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + R_ACTIVITY interrupt is active + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + R_RX_DONE interrupt is inactive + + + ACTIVE + 1 + R_RX_DONE interrupt is active + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + R_TX_ABRT interrupt is inactive + + + ACTIVE + 1 + R_TX_ABRT interrupt is active + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + R_RD_REQ interrupt is inactive + + + ACTIVE + 1 + R_RD_REQ interrupt is active + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + 0 + R_TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + R_TX_EMPTY interrupt is active + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + R_TX_OVER interrupt is inactive + + + ACTIVE + 1 + R_TX_OVER interrupt is active + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + R_RX_FULL interrupt is inactive + + + ACTIVE + 1 + R_RX_FULL interrupt is active + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + R_RX_OVER interrupt is inactive + + + ACTIVE + 1 + R_RX_OVER interrupt is active + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_INTR_MASK + 0x00000030 + I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x000008ff + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + 0 + RESTART_DET interrupt is masked + + + DISABLED + 1 + RESTART_DET interrupt is unmasked + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + 0 + GEN_CALL interrupt is masked + + + DISABLED + 1 + GEN_CALL interrupt is unmasked + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + 0 + START_DET interrupt is masked + + + DISABLED + 1 + START_DET interrupt is unmasked + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + 0 + STOP_DET interrupt is masked + + + DISABLED + 1 + STOP_DET interrupt is unmasked + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + 0 + ACTIVITY interrupt is masked + + + DISABLED + 1 + ACTIVITY interrupt is unmasked + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + 0 + RX_DONE interrupt is masked + + + DISABLED + 1 + RX_DONE interrupt is unmasked + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + 0 + TX_ABORT interrupt is masked + + + DISABLED + 1 + TX_ABORT interrupt is unmasked + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + 0 + RD_REQ interrupt is masked + + + DISABLED + 1 + RD_REQ interrupt is unmasked + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + 0 + TX_EMPTY interrupt is masked + + + DISABLED + 1 + TX_EMPTY interrupt is unmasked + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + 0 + TX_OVER interrupt is masked + + + DISABLED + 1 + TX_OVER interrupt is unmasked + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + 0 + RX_FULL interrupt is masked + + + DISABLED + 1 + RX_FULL interrupt is unmasked + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + 0 + RX_OVER interrupt is masked + + + DISABLED + 1 + RX_OVER interrupt is unmasked + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + 0 + RX_UNDER interrupt is masked + + + DISABLED + 1 + RX_UNDER interrupt is unmasked + + + + + + + IC_RAW_INTR_STAT + 0x00000034 + I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + RESTART_DET interrupt is inactive + + + ACTIVE + 1 + RESTART_DET interrupt is active + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + GEN_CALL interrupt is inactive + + + ACTIVE + 1 + GEN_CALL interrupt is active + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + START_DET interrupt is inactive + + + ACTIVE + 1 + START_DET interrupt is active + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + STOP_DET interrupt is inactive + + + ACTIVE + 1 + STOP_DET interrupt is active + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + RAW_INTR_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + RAW_INTR_ACTIVITY interrupt is active + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + RX_DONE interrupt is inactive + + + ACTIVE + 1 + RX_DONE interrupt is active + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + TX_ABRT interrupt is inactive + + + ACTIVE + 1 + TX_ABRT interrupt is active + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + RD_REQ interrupt is inactive + + + ACTIVE + 1 + RD_REQ interrupt is active + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + 0 + TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + TX_EMPTY interrupt is active + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + TX_OVER interrupt is inactive + + + ACTIVE + 1 + TX_OVER interrupt is active + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + RX_FULL interrupt is inactive + + + ACTIVE + 1 + RX_FULL interrupt is active + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + RX_OVER interrupt is inactive + + + ACTIVE + 1 + RX_OVER interrupt is active + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_RX_TL + 0x00000038 + I2C Receive FIFO Threshold Register + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + 0x0000003c + I2C Transmit FIFO Threshold Register + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + 0x00000040 + Clear Combined and Individual Interrupt Register + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + 0x00000044 + Clear RX_UNDER Interrupt Register + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + 0x00000048 + Clear RX_OVER Interrupt Register + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + 0x0000004c + Clear TX_OVER Interrupt Register + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + 0x00000050 + Clear RD_REQ Interrupt Register + 0x00000000 + + + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_ABRT + 0x00000054 + Clear TX_ABRT Interrupt Register + 0x00000000 + + + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_DONE + 0x00000058 + Clear RX_DONE Interrupt Register + 0x00000000 + + + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_ACTIVITY + 0x0000005c + Clear ACTIVITY Interrupt Register + 0x00000000 + + + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + 0x00000060 + Clear STOP_DET Interrupt Register + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + 0x00000064 + Clear START_DET Interrupt Register + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + 0x00000068 + Clear GEN_CALL Interrupt Register + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + 0x0000006c + I2C Enable Register + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] + read-write + + + NOT_BLOCKED + 0 + Tx Command execution not blocked + + + BLOCKED + 1 + Tx Command execution blocked + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + 0 + ABORT operation not in progress + + + ENABLED + 1 + ABORT operation in progress + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + I2C is disabled + + + ENABLED + 1 + I2C is enabled + + + + + + + IC_STATUS + 0x00000070 + I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + 0 + Slave is idle + + + ACTIVE + 1 + Slave not idle + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0 + [5:5] + read-only + + + IDLE + 0 + Master is idle + + + ACTIVE + 1 + Master not idle + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + 0 + Rx FIFO not full + + + FULL + 1 + Rx FIFO is full + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + 0 + Rx FIFO is empty + + + NOT_EMPTY + 1 + Rx FIFO not empty + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + 0 + Tx FIFO not empty + + + EMPTY + 1 + Tx FIFO is empty + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + 0 + Tx FIFO is full + + + NOT_FULL + 1 + Tx FIFO not full + + + + + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + I2C is idle + + + ACTIVE + 1 + I2C is active + + + + + + + IC_TXFLR + 0x00000074 + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x00000000 + + + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_RXFLR + 0x00000078 + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x00000000 + + + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_SDA_HOLD + 0x0000007c + I2C SDA Hold Time Length Register + + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE[0]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x00000001 + + + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] + read-write + + + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + [15:0] + read-write + + + + + IC_TX_ABRT_SOURCE + 0x00000080 + I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x00000000 + + + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only + + + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + 0 + Transfer abort detected by master- scenario not present + + + ABRT_USER_ABRT_GENERATED + 1 + Transfer abort detected by master + + + + + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + 0 + Slave trying to transmit to remote master in read mode- scenario not present + + + ABRT_SLVRD_INTX_GENERATED + 1 + Slave trying to transmit to remote master in read mode + + + + + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + 0 + Slave lost arbitration to remote master- scenario not present + + + ABRT_SLV_ARBLOST_GENERATED + 1 + Slave lost arbitration to remote master + + + + + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + 0 + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + 1 + Slave flushes existing data in TX-FIFO upon getting read command + + + + + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + 0 + Master or Slave-Transmitter lost arbitration- scenario not present + + + ABRT_LOST_GENERATED + 1 + Master or Slave-Transmitter lost arbitration + + + + + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [11:11] + read-only + + + ABRT_MASTER_DIS_VOID + 0 + User initiating master operation when MASTER disabled- scenario not present + + + ABRT_MASTER_DIS_GENERATED + 1 + User initiating master operation when MASTER disabled + + + + + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver + [10:10] + read-only + + + ABRT_10B_RD_VOID + 0 + Master not trying to read in 10Bit addressing mode when RESTART disabled + + + ABRT_10B_RD_GENERATED + 1 + Master trying to read in 10Bit addressing mode when RESTART disabled + + + + + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [9:9] + read-only + + + ABRT_SBYTE_NORSTRT_VOID + 0 + User trying to send START byte when RESTART disabled- scenario not present + + + ABRT_SBYTE_NORSTRT_GENERATED + 1 + User trying to send START byte when RESTART disabled + + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + + + ABRT_HS_NORSTRT_VOID + 0 + User trying to switch Master to HS mode when RESTART disabled- scenario not present + + + ABRT_HS_NORSTRT_GENERATED + 1 + User trying to switch Master to HS mode when RESTART disabled + + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [7:7] + read-only + + + ABRT_SBYTE_ACKDET_VOID + 0 + ACK detected for START byte- scenario not present + + + ABRT_SBYTE_ACKDET_GENERATED + 1 + ACK detected for START byte + + + + + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [6:6] + read-only + + + ABRT_HS_ACK_VOID + 0 + HS Master code ACKed in HS Mode- scenario not present + + + ABRT_HS_ACK_GENERATED + 1 + HS Master code ACKed in HS Mode + + + + + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [5:5] + read-only + + + ABRT_GCALL_READ_VOID + 0 + GCALL is followed by read from bus-scenario not present + + + ABRT_GCALL_READ_GENERATED + 1 + GCALL is followed by read from bus + + + + + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [4:4] + read-only + + + ABRT_GCALL_NOACK_VOID + 0 + GCALL not ACKed by any slave-scenario not present + + + ABRT_GCALL_NOACK_GENERATED + 1 + GCALL not ACKed by any slave + + + + + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + 0 + Transmitted data non-ACKed by addressed slave-scenario not present + + + ABRT_TXDATA_NOACK_GENERATED + 1 + Transmitted data not ACKed by addressed slave + + + + + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 2 of 10Bit Address not ACKed by any slave + + + + + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 1 of 10Bit Address not ACKed by any slave + + + + + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + This abort is generated because of NOACK for 7-bit address + + + + + + + IC_SLV_DATA_NACK_ONLY + 0x00000084 + Generate Slave Data NACK Register + + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. + + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x00000000 + + + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Slave receiver generates NACK normally + + + ENABLED + 1 + Slave receiver generates NACK upon data reception only + + + + + + + IC_DMA_CR + 0x00000088 + DMA Control Register + + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x00000000 + + + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] + read-write + + + DISABLED + 0 + transmit FIFO DMA channel disabled + + + ENABLED + 1 + Transmit FIFO DMA channel enabled + + + + + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Receive FIFO DMA channel disabled + + + ENABLED + 1 + Receive FIFO DMA channel enabled + + + + + + + IC_DMA_TDLR + 0x0000008c + DMA Transmit Data Level Register + 0x00000000 + + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_DMA_RDLR + 0x00000090 + I2C Receive Data Level Register + 0x00000000 + + + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_SDA_SETUP + 0x00000094 + I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE[0] = 0. + + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x00000064 + + + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] + read-write + + + + + IC_ACK_GENERAL_CALL + 0x00000098 + I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x00000001 + + + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] + read-write + + + DISABLED + 0 + Generate NACK for a General Call + + + ENABLED + 1 + Generate ACK for a General Call + + + + + + + IC_ENABLE_STATUS + 0x0000009c + I2C Enable Status Register + + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. + + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. + + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. + + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x00000000 + + + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + Slave RX Data is not lost + + + ACTIVE + 1 + Slave RX Data is lost + + + + + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + Slave is disabled when it is idle + + + ACTIVE + 1 + Slave is disabled when it is active + + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0 + [0:0] + read-only + + + DISABLED + 0 + I2C disabled + + + ENABLED + 1 + I2C enabled + + + + + + + IC_FS_SPKLEN + 0x000000a0 + I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0x00000007 + + + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] + read-write + + + + + IC_CLR_RESTART_DET + 0x000000a8 + Clear RESTART_DET Interrupt Register + 0x00000000 + + + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_COMP_PARAM_1 + 0x000000f4 + Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0x00000000 + + + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only + + + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + 0x000000f8 + I2C Component Version Register + 0x3230312a + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + 0x000000fc + I2C Component Type Register + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + + + + I2C1 + 0x40048000 + + I2C1_IRQ + 24 + + + + SPI0 + 0x4003c000 + + 0 + 4096 + registers + + + SPI0_IRQ + 18 + + + + SSPCR0 + 0x00000000 + Control register 0, SSPCR0 on page 3-4 + 0x00000000 + + + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] + read-write + + + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] + read-write + + + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] + read-write + + + FRF + Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. + [5:4] + read-write + + + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] + read-write + + + + + SSPCR1 + 0x00000004 + Control register 1, SSPCR1 on page 3-5 + 0x00000000 + + + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] + read-write + + + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] + read-write + + + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] + read-write + + + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] + read-write + + + + + SSPDR + 0x00000008 + Data register, SSPDR on page 3-6 + 0x00000000 + + + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + modify + + + + + SSPSR + 0x0000000c + Status register, SSPSR on page 3-7 + 0x00000003 + + + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only + + + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only + + + + + SSPCPSR + 0x00000010 + Clock prescale register, SSPCPSR on page 3-8 + 0x00000000 + + + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + SSPIMSC + 0x00000014 + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x00000000 + + + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] + read-write + + + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] + read-write + + + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] + read-write + + + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] + read-write + + + + + SSPRIS + 0x00000018 + Raw interrupt status register, SSPRIS on page 3-10 + 0x00000008 + + + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPMIS + 0x0000001c + Masked interrupt status register, SSPMIS on page 3-11 + 0x00000000 + + + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPICR + 0x00000020 + Interrupt clear register, SSPICR on page 3-11 + 0x00000000 + + + RTIC + Clears the SSPRTINTR interrupt + [1:1] + read-write + oneToClear + + + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + 0x00000024 + DMA control register, SSPDMACR on page 3-12 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + SSPPERIPHID0 + 0x00000fe0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000022 + + + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only + + + + + SSPPERIPHID1 + 0x00000fe4 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + SSPPERIPHID2 + 0x00000fe8 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + 0x00000fec + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + SSPPCELLID0 + 0x00000ff0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0000000d + + + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + SSPPCELLID1 + 0x00000ff4 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000f0 + + + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + SSPPCELLID2 + 0x00000ff8 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x00000005 + + + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + SSPPCELLID3 + 0x00000ffc + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000b1 + + + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + SPI1 + 0x40040000 + + SPI1_IRQ + 19 + + + + PIO0 + Programmable IO block + 0x50200000 + + 0 + 324 + registers + + + PIO0_IRQ_0 + 7 + + + PIO0_IRQ_1 + 8 + + + + CTRL + 0x00000000 + PIO control register + 0x00000000 + + + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + write-only + + + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. + + The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + write-only + + + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] + read-write + + + + + FSTAT + 0x00000004 + FIFO status register + 0x0f000f00 + + + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only + + + TXFULL + State machine TX FIFO is full + [19:16] + read-only + + + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only + + + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + + FDEBUG + 0x00000008 + FIFO debug register + 0x00000000 + + + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] + read-write + oneToClear + + + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] + read-write + oneToClear + + + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] + read-write + oneToClear + + + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] + read-write + oneToClear + + + + + FLEVEL + 0x0000000c + FIFO levels + 0x00000000 + + + RX3 + [31:28] + read-only + + + TX3 + [27:24] + read-only + + + RX2 + [23:20] + read-only + + + TX2 + [19:16] + read-only + + + RX1 + [15:12] + read-only + + + TX1 + [11:8] + read-only + + + RX0 + [7:4] + read-only + + + TX0 + [3:0] + read-only + + + + + TXF0 + 0x00000010 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF0 + [31:0] + write-only + + + + + TXF1 + 0x00000014 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF1 + [31:0] + write-only + + + + + TXF2 + 0x00000018 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF2 + [31:0] + write-only + + + + + TXF3 + 0x0000001c + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF3 + [31:0] + write-only + + + + + RXF0 + 0x00000020 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF0 + [31:0] + read-only + modify + + + + + RXF1 + 0x00000024 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF1 + [31:0] + read-only + modify + + + + + RXF2 + 0x00000028 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF2 + [31:0] + read-only + modify + + + + + RXF3 + 0x0000002c + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF3 + [31:0] + read-only + modify + + + + + IRQ + 0x00000030 + State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x00000000 + + + IRQ + [7:0] + read-write + oneToClear + + + + + IRQ_FORCE + 0x00000034 + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x00000000 + + + IRQ_FORCE + [7:0] + write-only + + + + + INPUT_SYNC_BYPASS + 0x00000038 + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + 0x00000000 + + + INPUT_SYNC_BYPASS + [31:0] + read-write + + + + + DBG_PADOUT + 0x0000003c + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOUT + [31:0] + read-only + + + + + DBG_PADOE + 0x00000040 + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOE + [31:0] + read-only + + + + + DBG_CFGINFO + 0x00000044 + The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + 0x00000000 + + + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only + + + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only + + + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. + [5:0] + read-only + + + + + INSTR_MEM0 + 0x00000048 + Write-only access to instruction memory location 0 + 0x00000000 + + + INSTR_MEM0 + [15:0] + write-only + + + + + INSTR_MEM1 + 0x0000004c + Write-only access to instruction memory location 1 + 0x00000000 + + + INSTR_MEM1 + [15:0] + write-only + + + + + INSTR_MEM2 + 0x00000050 + Write-only access to instruction memory location 2 + 0x00000000 + + + INSTR_MEM2 + [15:0] + write-only + + + + + INSTR_MEM3 + 0x00000054 + Write-only access to instruction memory location 3 + 0x00000000 + + + INSTR_MEM3 + [15:0] + write-only + + + + + INSTR_MEM4 + 0x00000058 + Write-only access to instruction memory location 4 + 0x00000000 + + + INSTR_MEM4 + [15:0] + write-only + + + + + INSTR_MEM5 + 0x0000005c + Write-only access to instruction memory location 5 + 0x00000000 + + + INSTR_MEM5 + [15:0] + write-only + + + + + INSTR_MEM6 + 0x00000060 + Write-only access to instruction memory location 6 + 0x00000000 + + + INSTR_MEM6 + [15:0] + write-only + + + + + INSTR_MEM7 + 0x00000064 + Write-only access to instruction memory location 7 + 0x00000000 + + + INSTR_MEM7 + [15:0] + write-only + + + + + INSTR_MEM8 + 0x00000068 + Write-only access to instruction memory location 8 + 0x00000000 + + + INSTR_MEM8 + [15:0] + write-only + + + + + INSTR_MEM9 + 0x0000006c + Write-only access to instruction memory location 9 + 0x00000000 + + + INSTR_MEM9 + [15:0] + write-only + + + + + INSTR_MEM10 + 0x00000070 + Write-only access to instruction memory location 10 + 0x00000000 + + + INSTR_MEM10 + [15:0] + write-only + + + + + INSTR_MEM11 + 0x00000074 + Write-only access to instruction memory location 11 + 0x00000000 + + + INSTR_MEM11 + [15:0] + write-only + + + + + INSTR_MEM12 + 0x00000078 + Write-only access to instruction memory location 12 + 0x00000000 + + + INSTR_MEM12 + [15:0] + write-only + + + + + INSTR_MEM13 + 0x0000007c + Write-only access to instruction memory location 13 + 0x00000000 + + + INSTR_MEM13 + [15:0] + write-only + + + + + INSTR_MEM14 + 0x00000080 + Write-only access to instruction memory location 14 + 0x00000000 + + + INSTR_MEM14 + [15:0] + write-only + + + + + INSTR_MEM15 + 0x00000084 + Write-only access to instruction memory location 15 + 0x00000000 + + + INSTR_MEM15 + [15:0] + write-only + + + + + INSTR_MEM16 + 0x00000088 + Write-only access to instruction memory location 16 + 0x00000000 + + + INSTR_MEM16 + [15:0] + write-only + + + + + INSTR_MEM17 + 0x0000008c + Write-only access to instruction memory location 17 + 0x00000000 + + + INSTR_MEM17 + [15:0] + write-only + + + + + INSTR_MEM18 + 0x00000090 + Write-only access to instruction memory location 18 + 0x00000000 + + + INSTR_MEM18 + [15:0] + write-only + + + + + INSTR_MEM19 + 0x00000094 + Write-only access to instruction memory location 19 + 0x00000000 + + + INSTR_MEM19 + [15:0] + write-only + + + + + INSTR_MEM20 + 0x00000098 + Write-only access to instruction memory location 20 + 0x00000000 + + + INSTR_MEM20 + [15:0] + write-only + + + + + INSTR_MEM21 + 0x0000009c + Write-only access to instruction memory location 21 + 0x00000000 + + + INSTR_MEM21 + [15:0] + write-only + + + + + INSTR_MEM22 + 0x000000a0 + Write-only access to instruction memory location 22 + 0x00000000 + + + INSTR_MEM22 + [15:0] + write-only + + + + + INSTR_MEM23 + 0x000000a4 + Write-only access to instruction memory location 23 + 0x00000000 + + + INSTR_MEM23 + [15:0] + write-only + + + + + INSTR_MEM24 + 0x000000a8 + Write-only access to instruction memory location 24 + 0x00000000 + + + INSTR_MEM24 + [15:0] + write-only + + + + + INSTR_MEM25 + 0x000000ac + Write-only access to instruction memory location 25 + 0x00000000 + + + INSTR_MEM25 + [15:0] + write-only + + + + + INSTR_MEM26 + 0x000000b0 + Write-only access to instruction memory location 26 + 0x00000000 + + + INSTR_MEM26 + [15:0] + write-only + + + + + INSTR_MEM27 + 0x000000b4 + Write-only access to instruction memory location 27 + 0x00000000 + + + INSTR_MEM27 + [15:0] + write-only + + + + + INSTR_MEM28 + 0x000000b8 + Write-only access to instruction memory location 28 + 0x00000000 + + + INSTR_MEM28 + [15:0] + write-only + + + + + INSTR_MEM29 + 0x000000bc + Write-only access to instruction memory location 29 + 0x00000000 + + + INSTR_MEM29 + [15:0] + write-only + + + + + INSTR_MEM30 + 0x000000c0 + Write-only access to instruction memory location 30 + 0x00000000 + + + INSTR_MEM30 + [15:0] + write-only + + + + + INSTR_MEM31 + 0x000000c4 + Write-only access to instruction memory location 31 + 0x00000000 + + + INSTR_MEM31 + [15:0] + write-only + + + + + SM0_CLKDIV + 0x000000c8 + Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM0_EXECCTRL + 0x000000cc + Execution/behavioural settings for state machine 0 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM0_SHIFTCTRL + 0x000000d0 + Control behaviour of the input/output shift registers for state machine 0 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM0_ADDR + 0x000000d4 + Current instruction address of state machine 0 + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM0_INSTR + 0x000000d8 + Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM0_PINCTRL + 0x000000dc + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM1_CLKDIV + 0x000000e0 + Clock divisor register for state machine 1 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM1_EXECCTRL + 0x000000e4 + Execution/behavioural settings for state machine 1 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM1_SHIFTCTRL + 0x000000e8 + Control behaviour of the input/output shift registers for state machine 1 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM1_ADDR + 0x000000ec + Current instruction address of state machine 1 + 0x00000000 + + + SM1_ADDR + [4:0] + read-only + + + + + SM1_INSTR + 0x000000f0 + Read to see the instruction currently addressed by state machine 1's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM1_INSTR + [15:0] + read-write + + + + + SM1_PINCTRL + 0x000000f4 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM2_CLKDIV + 0x000000f8 + Clock divisor register for state machine 2 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM2_EXECCTRL + 0x000000fc + Execution/behavioural settings for state machine 2 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM2_SHIFTCTRL + 0x00000100 + Control behaviour of the input/output shift registers for state machine 2 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM2_ADDR + 0x00000104 + Current instruction address of state machine 2 + 0x00000000 + + + SM2_ADDR + [4:0] + read-only + + + + + SM2_INSTR + 0x00000108 + Read to see the instruction currently addressed by state machine 2's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM2_INSTR + [15:0] + read-write + + + + + SM2_PINCTRL + 0x0000010c + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM3_CLKDIV + 0x00000110 + Clock divisor register for state machine 3 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM3_EXECCTRL + 0x00000114 + Execution/behavioural settings for state machine 3 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM3_SHIFTCTRL + 0x00000118 + Control behaviour of the input/output shift registers for state machine 3 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM3_ADDR + 0x0000011c + Current instruction address of state machine 3 + 0x00000000 + + + SM3_ADDR + [4:0] + read-only + + + + + SM3_INSTR + 0x00000120 + Read to see the instruction currently addressed by state machine 3's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM3_INSTR + [15:0] + read-write + + + + + SM3_PINCTRL + 0x00000124 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + INTR + 0x00000128 + Raw Interrupts + 0x00000000 + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ0_INTE + 0x0000012c + Interrupt Enable for irq0 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTF + 0x00000130 + Interrupt Force for irq0 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000134 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ1_INTE + 0x00000138 + Interrupt Enable for irq1 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTF + 0x0000013c + Interrupt Force for irq1 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTS + 0x00000140 + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 9 + + + PIO1_IRQ_1 + 10 + + + + BUSCTRL + Register block for busfabric control signals and performance counters + 0x40030000 + + 0 + 40 + registers + + + + BUS_PRIORITY + 0x00000000 + Set the priority of each master for bus arbitration. + 0x00000000 + + + DMA_W + 0 - low priority, 1 - high priority + [12:12] + read-write + + + DMA_R + 0 - low priority, 1 - high priority + [8:8] + read-write + + + PROC1 + 0 - low priority, 1 - high priority + [4:4] + read-write + + + PROC0 + 0 - low priority, 1 - high priority + [0:0] + read-write + + + + + BUS_PRIORITY_ACK + 0x00000004 + Bus priority acknowledge + 0x00000000 + + + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + + PERFCTR0 + 0x00000008 + Bus fabric performance counter 0 + 0x00000000 + + + PERFCTR0 + Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] + read-write + oneToClear + + + + + PERFSEL0 + 0x0000000c + Bus fabric performance event select for PERFCTR0 + 0x0000001f + + + PERFSEL0 + Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + PERFCTR1 + 0x00000010 + Bus fabric performance counter 1 + 0x00000000 + + + PERFCTR1 + Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] + read-write + oneToClear + + + + + PERFSEL1 + 0x00000014 + Bus fabric performance event select for PERFCTR1 + 0x0000001f + + + PERFSEL1 + Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + PERFCTR2 + 0x00000018 + Bus fabric performance counter 2 + 0x00000000 + + + PERFCTR2 + Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] + read-write + oneToClear + + + + + PERFSEL2 + 0x0000001c + Bus fabric performance event select for PERFCTR2 + 0x0000001f + + + PERFSEL2 + Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + PERFCTR3 + 0x00000020 + Bus fabric performance counter 3 + 0x00000000 + + + PERFCTR3 + Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + + PERFSEL3 + 0x00000024 + Bus fabric performance event select for PERFCTR3 + 0x0000001f + + + PERFSEL3 + Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + + + SIO + Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xd0000000 + + 0 + 384 + registers + + + SIO_IRQ_PROC0 + 15 + + + SIO_IRQ_PROC1 + 16 + + + + CPUID + 0x00000000 + Processor core identifier + 0x00000000 + + + CPUID + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + [31:0] + read-only + + + + + GPIO_IN + 0x00000004 + Input value for GPIO pins + 0x00000000 + + + GPIO_IN + Input value for GPIO0...29 + [29:0] + read-only + + + + + GPIO_HI_IN + 0x00000008 + Input value for QSPI pins + 0x00000000 + + + GPIO_HI_IN + Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 + [5:0] + read-only + + + + + GPIO_OUT + 0x00000010 + GPIO output value + 0x00000000 + + + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...29. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [29:0] + read-write + + + + + GPIO_OUT_SET + 0x00000014 + GPIO output value set + 0x00000000 + + + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [29:0] + write-only + + + + + GPIO_OUT_CLR + 0x00000018 + GPIO output value clear + 0x00000000 + + + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [29:0] + write-only + + + + + GPIO_OUT_XOR + 0x0000001c + GPIO output value XOR + 0x00000000 + + + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [29:0] + write-only + + + + + GPIO_OE + 0x00000020 + GPIO output enable + 0x00000000 + + + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...29. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [29:0] + read-write + + + + + GPIO_OE_SET + 0x00000024 + GPIO output enable set + 0x00000000 + + + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [29:0] + write-only + + + + + GPIO_OE_CLR + 0x00000028 + GPIO output enable clear + 0x00000000 + + + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [29:0] + write-only + + + + + GPIO_OE_XOR + 0x0000002c + GPIO output enable XOR + 0x00000000 + + + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [29:0] + write-only + + + + + GPIO_HI_OUT + 0x00000030 + QSPI output value + 0x00000000 + + + GPIO_HI_OUT + Set output level (1/0 -> high/low) for QSPI IO0...5. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [5:0] + read-write + + + + + GPIO_HI_OUT_SET + 0x00000034 + QSPI output value set + 0x00000000 + + + GPIO_HI_OUT_SET + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + [5:0] + write-only + + + + + GPIO_HI_OUT_CLR + 0x00000038 + QSPI output value clear + 0x00000000 + + + GPIO_HI_OUT_CLR + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + [5:0] + write-only + + + + + GPIO_HI_OUT_XOR + 0x0000003c + QSPI output value XOR + 0x00000000 + + + GPIO_HI_OUT_XOR + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + [5:0] + write-only + + + + + GPIO_HI_OE + 0x00000040 + QSPI output enable + 0x00000000 + + + GPIO_HI_OE + Set output enable (1/0 -> output/input) for QSPI IO0...5. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [5:0] + read-write + + + + + GPIO_HI_OE_SET + 0x00000044 + QSPI output enable set + 0x00000000 + + + GPIO_HI_OE_SET + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + [5:0] + write-only + + + + + GPIO_HI_OE_CLR + 0x00000048 + QSPI output enable clear + 0x00000000 + + + GPIO_HI_OE_CLR + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + [5:0] + write-only + + + + + GPIO_HI_OE_XOR + 0x0000004c + QSPI output enable XOR + 0x00000000 + + + GPIO_HI_OE_XOR + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + [5:0] + write-only + + + + + FIFO_ST + 0x00000050 + Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x00000002 + + + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] + read-write + oneToClear + + + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] + read-write + oneToClear + + + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only + + + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + + FIFO_WR + 0x00000054 + Write access to this core's TX FIFO + 0x00000000 + + + FIFO_WR + [31:0] + write-only + + + + + FIFO_RD + 0x00000058 + Read access to this core's RX FIFO + 0x00000000 + + + FIFO_RD + [31:0] + read-only + modify + + + + + SPINLOCK_ST + 0x0000005c + Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + 0x00000000 + + + SPINLOCK_ST + [31:0] + read-only + + + + + DIV_UDIVIDEND + 0x00000060 + Divider unsigned dividend + Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an + unsigned calculation, and the S alias starts a signed calculation. + 0x00000000 + + + DIV_UDIVIDEND + [31:0] + read-write + + + + + DIV_UDIVISOR + 0x00000064 + Divider unsigned divisor + Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an + unsigned calculation, and the S alias starts a signed calculation. + 0x00000000 + + + DIV_UDIVISOR + [31:0] + read-write + + + + + DIV_SDIVIDEND + 0x00000068 + Divider signed dividend + The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. + 0x00000000 + + + DIV_SDIVIDEND + [31:0] + read-write + + + + + DIV_SDIVISOR + 0x0000006c + Divider signed divisor + The same as UDIVISOR, but starts a signed calculation, rather than unsigned. + 0x00000000 + + + DIV_SDIVISOR + [31:0] + read-write + + + + + DIV_QUOTIENT + 0x00000070 + Divider result quotient + The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. + For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. + This register can be written to directly, for context save/restore purposes. This halts any + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order + REMAINDER, QUOTIENT if CSR_DIRTY is used. + 0x00000000 + + + DIV_QUOTIENT + [31:0] + read-write + + + + + DIV_REMAINDER + 0x00000074 + Divider result remainder + The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. + For signed calculations, REMAINDER is negative only when DIVIDEND is negative. + This register can be written to directly, for context save/restore purposes. This halts any + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + 0x00000000 + + + DIV_REMAINDER + [31:0] + read-write + + + + + DIV_CSR + 0x00000078 + Control and status register for divider. + 0x00000001 + + + DIRTY + Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. + Software can use this flag to make save/restore more efficient (skip if not DIRTY). + If the flag is used in this way, it's recommended to either read QUOTIENT only, + or REMAINDER and then QUOTIENT, to prevent data loss on context switch. + [1:1] + read-only + + + READY + Reads as 0 when a calculation is in progress, 1 otherwise. + Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no + matter if one is already in progress. + Writing to a result register will immediately terminate any in-progress calculation + and set the READY and DIRTY flags. + [0:0] + read-only + + + + + INTERP0_ACCUM0 + 0x00000080 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP0_ACCUM0 + [31:0] + read-write + + + + + INTERP0_ACCUM1 + 0x00000084 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP0_ACCUM1 + [31:0] + read-write + + + + + INTERP0_BASE0 + 0x00000088 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP0_BASE0 + [31:0] + read-write + + + + + INTERP0_BASE1 + 0x0000008c + Read/write access to BASE1 register. + 0x00000000 + + + INTERP0_BASE1 + [31:0] + read-write + + + + + INTERP0_BASE2 + 0x00000090 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP0_BASE2 + [31:0] + read-write + + + + + INTERP0_POP_LANE0 + 0x00000094 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE0 + [31:0] + read-only + + + + + INTERP0_POP_LANE1 + 0x00000098 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE1 + [31:0] + read-only + + + + + INTERP0_POP_FULL + 0x0000009c + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_FULL + [31:0] + read-only + + + + + INTERP0_PEEK_LANE0 + 0x000000a0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP0_PEEK_LANE1 + 0x000000a4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP0_PEEK_FULL + 0x000000a8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_FULL + [31:0] + read-only + + + + + INTERP0_CTRL_LANE0 + 0x000000ac + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + [21:21] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP0_CTRL_LANE1 + 0x000000b0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP0_ACCUM0_ADD + 0x000000b4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP0_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP0_ACCUM1_ADD + 0x000000b8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP0_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP0_BASE_1AND0 + 0x000000bc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP0_BASE_1AND0 + [31:0] + write-only + + + + + INTERP1_ACCUM0 + 0x000000c0 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP1_ACCUM0 + [31:0] + read-write + + + + + INTERP1_ACCUM1 + 0x000000c4 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP1_ACCUM1 + [31:0] + read-write + + + + + INTERP1_BASE0 + 0x000000c8 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP1_BASE0 + [31:0] + read-write + + + + + INTERP1_BASE1 + 0x000000cc + Read/write access to BASE1 register. + 0x00000000 + + + INTERP1_BASE1 + [31:0] + read-write + + + + + INTERP1_BASE2 + 0x000000d0 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP1_BASE2 + [31:0] + read-write + + + + + INTERP1_POP_LANE0 + 0x000000d4 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE0 + [31:0] + read-only + + + + + INTERP1_POP_LANE1 + 0x000000d8 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE1 + [31:0] + read-only + + + + + INTERP1_POP_FULL + 0x000000dc + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_FULL + [31:0] + read-only + + + + + INTERP1_PEEK_LANE0 + 0x000000e0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP1_PEEK_LANE1 + 0x000000e4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP1_PEEK_FULL + 0x000000e8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_FULL + [31:0] + read-only + + + + + INTERP1_CTRL_LANE0 + 0x000000ec + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP1_CTRL_LANE1 + 0x000000f0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] + read-write + + + + + INTERP1_ACCUM0_ADD + 0x000000f4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP1_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP1_ACCUM1_ADD + 0x000000f8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP1_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP1_BASE_1AND0 + 0x000000fc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP1_BASE_1AND0 + [31:0] + write-only + + + + + SPINLOCK0 + 0x00000100 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK0 + [31:0] + read-write + modify + + + + + SPINLOCK1 + 0x00000104 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK1 + [31:0] + read-write + modify + + + + + SPINLOCK2 + 0x00000108 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK2 + [31:0] + read-write + modify + + + + + SPINLOCK3 + 0x0000010c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK3 + [31:0] + read-write + modify + + + + + SPINLOCK4 + 0x00000110 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK4 + [31:0] + read-write + modify + + + + + SPINLOCK5 + 0x00000114 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK5 + [31:0] + read-write + modify + + + + + SPINLOCK6 + 0x00000118 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK6 + [31:0] + read-write + modify + + + + + SPINLOCK7 + 0x0000011c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK7 + [31:0] + read-write + modify + + + + + SPINLOCK8 + 0x00000120 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK8 + [31:0] + read-write + modify + + + + + SPINLOCK9 + 0x00000124 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK9 + [31:0] + read-write + modify + + + + + SPINLOCK10 + 0x00000128 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK10 + [31:0] + read-write + modify + + + + + SPINLOCK11 + 0x0000012c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK11 + [31:0] + read-write + modify + + + + + SPINLOCK12 + 0x00000130 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK12 + [31:0] + read-write + modify + + + + + SPINLOCK13 + 0x00000134 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK13 + [31:0] + read-write + modify + + + + + SPINLOCK14 + 0x00000138 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK14 + [31:0] + read-write + modify + + + + + SPINLOCK15 + 0x0000013c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK15 + [31:0] + read-write + modify + + + + + SPINLOCK16 + 0x00000140 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK16 + [31:0] + read-write + modify + + + + + SPINLOCK17 + 0x00000144 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK17 + [31:0] + read-write + modify + + + + + SPINLOCK18 + 0x00000148 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK18 + [31:0] + read-write + modify + + + + + SPINLOCK19 + 0x0000014c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK19 + [31:0] + read-write + modify + + + + + SPINLOCK20 + 0x00000150 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK20 + [31:0] + read-write + modify + + + + + SPINLOCK21 + 0x00000154 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK21 + [31:0] + read-write + modify + + + + + SPINLOCK22 + 0x00000158 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK22 + [31:0] + read-write + modify + + + + + SPINLOCK23 + 0x0000015c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK23 + [31:0] + read-write + modify + + + + + SPINLOCK24 + 0x00000160 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK24 + [31:0] + read-write + modify + + + + + SPINLOCK25 + 0x00000164 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK25 + [31:0] + read-write + modify + + + + + SPINLOCK26 + 0x00000168 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK26 + [31:0] + read-write + modify + + + + + SPINLOCK27 + 0x0000016c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK27 + [31:0] + read-write + modify + + + + + SPINLOCK28 + 0x00000170 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK28 + [31:0] + read-write + modify + + + + + SPINLOCK29 + 0x00000174 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK29 + [31:0] + read-write + modify + + + + + SPINLOCK30 + 0x00000178 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK30 + [31:0] + read-write + modify + + + + + SPINLOCK31 + 0x0000017c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK31 + [31:0] + read-write + modify + + + + + + + USB + USB FS/LS controller device registers + 0x50110000 + + 0 + 156 + registers + + + USBCTRL_IRQ + 5 + + + + ADDR_ENDP + 0x00000000 + Device address and endpoint control + 0x00000000 + + + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] + read-write + + + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] + read-write + + + + + ADDR_ENDP1 + 0x00000004 + Interrupt endpoint 1. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP2 + 0x00000008 + Interrupt endpoint 2. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP3 + 0x0000000c + Interrupt endpoint 3. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP4 + 0x00000010 + Interrupt endpoint 4. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP5 + 0x00000014 + Interrupt endpoint 5. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP6 + 0x00000018 + Interrupt endpoint 6. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP7 + 0x0000001c + Interrupt endpoint 7. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP8 + 0x00000020 + Interrupt endpoint 8. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP9 + 0x00000024 + Interrupt endpoint 9. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP10 + 0x00000028 + Interrupt endpoint 10. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP11 + 0x0000002c + Interrupt endpoint 11. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP12 + 0x00000030 + Interrupt endpoint 12. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP13 + 0x00000034 + Interrupt endpoint 13. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP14 + 0x00000038 + Interrupt endpoint 14. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP15 + 0x0000003c + Interrupt endpoint 15. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + MAIN_CTRL + 0x00000040 + Main control register + 0x00000000 + + + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write + + + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write + + + CONTROLLER_EN + Enable controller + [0:0] + read-write + + + + + SOF_WR + 0x00000044 + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x00000000 + + + COUNT + [10:0] + write-only + + + + + SOF_RD + 0x00000048 + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x00000000 + + + COUNT + [10:0] + read-only + + + + + SIE_CTRL + 0x0000004c + SIE control register + 0x00000000 + + + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] + read-write + + + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] + read-write + + + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] + read-write + + + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] + read-write + + + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] + read-write + + + DIRECT_EN + Direct bus drive enable + [26:26] + read-write + + + DIRECT_DP + Direct control of DP + [25:25] + read-write + + + DIRECT_DM + Direct control of DM + [24:24] + read-write + + + TRANSCEIVER_PD + Power down bus transceiver + [18:18] + read-write + + + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] + read-write + + + PULLUP_EN + Device: Enable pull up resistor + [16:16] + read-write + + + PULLDOWN_EN + Host: Enable pull down resistors + [15:15] + read-write + + + RESET_BUS + Host: Reset bus + [13:13] + write-only + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. + [12:12] + write-only + + + VBUS_EN + Host: Enable VBUS + [11:11] + read-write + + + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) + [10:10] + read-write + + + SOF_EN + Host: Enable SOF generation (for full speed bus) + [9:9] + read-write + + + SOF_SYNC + Host: Delay packet(s) until after SOF + [8:8] + read-write + + + PREAMBLE_EN + Host: Preable enable for LS device on FS hub + [6:6] + read-write + + + STOP_TRANS + Host: Stop transaction + [4:4] + write-only + + + RECEIVE_DATA + Host: Receive transaction (IN to host) + [3:3] + read-write + + + SEND_DATA + Host: Send transaction (OUT from host) + [2:2] + read-write + + + SEND_SETUP + Host: Send Setup packet + [1:1] + read-write + + + START_TRANS + Host: Start transaction + [0:0] + write-only + + + + + SIE_STATUS + 0x00000050 + SIE status register + 0x00000000 + + + DATA_SEQ_ERROR + Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear + + + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear + + + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear + + + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear + + + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear + + + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear + + + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear + + + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received + [19:19] + read-write + oneToClear + + + TRANS_COMPLETE + Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + [18:18] + read-write + oneToClear + + + SETUP_REC + Device: Setup packet received + [17:17] + read-write + oneToClear + + + CONNECTED + Device: connected + [16:16] + read-only + + + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] + read-write + oneToClear + + + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only + + + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-only + + + SUSPENDED + Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] + read-only + + + LINE_STATE + USB bus line state + [3:2] + read-only + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + 0x00000054 + interrupt endpoint control register + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 => 15 + [15:1] + read-write + + + + + BUFF_STATUS + 0x00000058 + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + BUFF_CPU_SHOULD_HANDLE + 0x0000005c + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x00000000 + + + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT + [19:19] + read-only + + + EP9_IN + [18:18] + read-only + + + EP8_OUT + [17:17] + read-only + + + EP8_IN + [16:16] + read-only + + + EP7_OUT + [15:15] + read-only + + + EP7_IN + [14:14] + read-only + + + EP6_OUT + [13:13] + read-only + + + EP6_IN + [12:12] + read-only + + + EP5_OUT + [11:11] + read-only + + + EP5_IN + [10:10] + read-only + + + EP4_OUT + [9:9] + read-only + + + EP4_IN + [8:8] + read-only + + + EP3_OUT + [7:7] + read-only + + + EP3_IN + [6:6] + read-only + + + EP2_OUT + [5:5] + read-only + + + EP2_IN + [4:4] + read-only + + + EP1_OUT + [3:3] + read-only + + + EP1_IN + [2:2] + read-only + + + EP0_OUT + [1:1] + read-only + + + EP0_IN + [0:0] + read-only + + + + + EP_ABORT + 0x00000060 + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] + read-write + + + EP11_OUT + [23:23] + read-write + + + EP11_IN + [22:22] + read-write + + + EP10_OUT + [21:21] + read-write + + + EP10_IN + [20:20] + read-write + + + EP9_OUT + [19:19] + read-write + + + EP9_IN + [18:18] + read-write + + + EP8_OUT + [17:17] + read-write + + + EP8_IN + [16:16] + read-write + + + EP7_OUT + [15:15] + read-write + + + EP7_IN + [14:14] + read-write + + + EP6_OUT + [13:13] + read-write + + + EP6_IN + [12:12] + read-write + + + EP5_OUT + [11:11] + read-write + + + EP5_IN + [10:10] + read-write + + + EP4_OUT + [9:9] + read-write + + + EP4_IN + [8:8] + read-write + + + EP3_OUT + [7:7] + read-write + + + EP3_IN + [6:6] + read-write + + + EP2_OUT + [5:5] + read-write + + + EP2_IN + [4:4] + read-write + + + EP1_OUT + [3:3] + read-write + + + EP1_IN + [2:2] + read-write + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + EP_ABORT_DONE + 0x00000064 + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + EP_STALL_ARM + 0x00000068 + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + 0x0000006c + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x00100010 + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + 0x00000070 + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + 0x00000074 + Where to connect the USB controller. Should be to_phy by default. + 0x00000000 + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + 0x00000078 + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value. + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT + [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + 0x0000007c + Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation + Use in conjunction with usbphy_direct_override register + 0x00000000 + + + DM_OVV + Status bit from USB PHY + [22:22] + read-only + + + DP_OVV + Status bit from USB PHY + [21:21] + read-only + + + DM_OVCN + Status bit from USB PHY + [20:20] + read-only + + + DP_OVCN + Status bit from USB PHY + [19:19] + read-only + + + RX_DM + Status bit from USB PHY + DPM pin state + [18:18] + read-only + + + RX_DP + Status bit from USB PHY + DPP pin state + [17:17] + read-only + + + RX_DD + Status bit from USB PHY + RX Diff data + [16:16] + read-only + + + TX_DIFFMODE + [15:15] + read-write + + + TX_FSSLEW + [14:14] + read-write + + + TX_PD + [13:13] + read-write + + + RX_PD + [12:12] + read-write + + + TX_DM + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, Ignored + TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write + + + TX_DP + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, Ignored. + TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + 1 - Enable Rpd on DPM + [6:6] + read-write + + + DM_PULLUP_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + 1 - Enable Rpu on DPM + [5:5] + read-write + + + DM_PULLUP_HISEL + when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + 1 - Enable Rpd on DPP + [2:2] + read-write + + + DP_PULLUP_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + [1:1] + read-write + + + DP_PULLUP_HISEL + when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + + + USBPHY_DIRECT_OVERRIDE + 0x00000080 + 0x00000000 + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + + + + USBPHY_TRIM + 0x00000084 + Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation + 0x00001f1f + + + DM_PULLDN_TRIM + Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write + + + + + INTR + 0x0000008c + Raw Interrupts + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + INTE + 0x00000090 + Interrupt Enable + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTF + 0x00000094 + Interrupt Force + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTS + 0x00000098 + Interrupt status after masking & forcing + 0x00000000 + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + + + USB_DPRAM + DPRAM layout for USB device. + 0x50100000 + + 0 + 256 + registers + + + + SETUP_PACKET_LOW + 0x00000000 + Bytes 0-3 of the SETUP packet from the host. + 0x00000000 + + + WVALUE + [31:16] + read-write + + + BREQUEST + [15:8] + read-write + + + BMREQUESTTYPE + [7:0] + read-write + + + + + SETUP_PACKET_HIGH + 0x00000004 + Bytes 4-7 of the setup packet from the host. + 0x00000000 + + + WLENGTH + [31:16] + read-write + + + WINDEX + [15:0] + read-write + + + + + EP1_IN_CONTROL + 0x00000008 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP1_OUT_CONTROL + 0x0000000c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_IN_CONTROL + 0x00000010 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_OUT_CONTROL + 0x00000014 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_IN_CONTROL + 0x00000018 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_OUT_CONTROL + 0x0000001c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_IN_CONTROL + 0x00000020 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_OUT_CONTROL + 0x00000024 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_IN_CONTROL + 0x00000028 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_OUT_CONTROL + 0x0000002c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_IN_CONTROL + 0x00000030 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_OUT_CONTROL + 0x00000034 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_IN_CONTROL + 0x00000038 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_OUT_CONTROL + 0x0000003c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_IN_CONTROL + 0x00000040 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_OUT_CONTROL + 0x00000044 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_IN_CONTROL + 0x00000048 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_OUT_CONTROL + 0x0000004c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_IN_CONTROL + 0x00000050 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_OUT_CONTROL + 0x00000054 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_IN_CONTROL + 0x00000058 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_OUT_CONTROL + 0x0000005c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_IN_CONTROL + 0x00000060 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_OUT_CONTROL + 0x00000064 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_IN_CONTROL + 0x00000068 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_OUT_CONTROL + 0x0000006c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_IN_CONTROL + 0x00000070 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_OUT_CONTROL + 0x00000074 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_IN_CONTROL + 0x00000078 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_OUT_CONTROL + 0x0000007c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP0_IN_BUFFER_CONTROL + 0x00000080 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP0_OUT_BUFFER_CONTROL + 0x00000084 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP1_IN_BUFFER_CONTROL + 0x00000088 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP1_OUT_BUFFER_CONTROL + 0x0000008c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP2_IN_BUFFER_CONTROL + 0x00000090 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP2_OUT_BUFFER_CONTROL + 0x00000094 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP3_IN_BUFFER_CONTROL + 0x00000098 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP3_OUT_BUFFER_CONTROL + 0x0000009c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP4_IN_BUFFER_CONTROL + 0x000000a0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP4_OUT_BUFFER_CONTROL + 0x000000a4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP5_IN_BUFFER_CONTROL + 0x000000a8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP5_OUT_BUFFER_CONTROL + 0x000000ac + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP6_IN_BUFFER_CONTROL + 0x000000b0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP6_OUT_BUFFER_CONTROL + 0x000000b4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP7_IN_BUFFER_CONTROL + 0x000000b8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP7_OUT_BUFFER_CONTROL + 0x000000bc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP8_IN_BUFFER_CONTROL + 0x000000c0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP8_OUT_BUFFER_CONTROL + 0x000000c4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP9_IN_BUFFER_CONTROL + 0x000000c8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP9_OUT_BUFFER_CONTROL + 0x000000cc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP10_IN_BUFFER_CONTROL + 0x000000d0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP10_OUT_BUFFER_CONTROL + 0x000000d4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP11_IN_BUFFER_CONTROL + 0x000000d8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP11_OUT_BUFFER_CONTROL + 0x000000dc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP12_IN_BUFFER_CONTROL + 0x000000e0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP12_OUT_BUFFER_CONTROL + 0x000000e4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP13_IN_BUFFER_CONTROL + 0x000000e8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP13_OUT_BUFFER_CONTROL + 0x000000ec + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP14_IN_BUFFER_CONTROL + 0x000000f0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP14_OUT_BUFFER_CONTROL + 0x000000f4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP15_IN_BUFFER_CONTROL + 0x000000f8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + EP15_OUT_BUFFER_CONTROL + 0x000000fc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 0. + [9:0] + read-write + + + + + + + TBMAN + Testbench manager. Allows the programmer to know what platform their software is running on. + 0x4006c000 + + 0 + 4 + registers + + + + PLATFORM + 0x00000000 + Indicates the type of platform in use + 0x00000005 + + + FPGA + Indicates the platform is an FPGA + [1:1] + read-only + + + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + VREG_AND_CHIP_RESET + control and status for on-chip voltage regulator and chip level reset subsystem + 0x40064000 + + 0 + 12 + registers + + + + VREG + 0x00000000 + Voltage regulator control and status + 0x000000b1 + + + ROK + regulation status + 0=not in regulation, 1=in regulation + [12:12] + read-only + + + VSEL + output voltage select + 0000 to 0101 - 0.80V + 0110 - 0.85V + 0111 - 0.90V + 1000 - 0.95V + 1001 - 1.00V + 1010 - 1.05V + 1011 - 1.10V (default) + 1100 - 1.15V + 1101 - 1.20V + 1110 - 1.25V + 1111 - 1.30V + [7:4] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + EN + enable + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD + 0x00000004 + brown-out detection control + 0x00000091 + + + VSEL + threshold select + 0000 - 0.473V + 0001 - 0.516V + 0010 - 0.559V + 0011 - 0.602V + 0100 - 0.645V + 0101 - 0.688V + 0110 - 0.731V + 0111 - 0.774V + 1000 - 0.817V + 1001 - 0.860V (default) + 1010 - 0.903V + 1011 - 0.946V + 1100 - 0.989V + 1101 - 1.032V + 1110 - 1.075V + 1111 - 1.118V + [7:4] + read-write + + + EN + enable + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + CHIP_RESET + 0x00000008 + Chip reset control and status + 0x00000000 + + + PSM_RESTART_FLAG + This is set by psm_restart from the debugger. + Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. + In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. + [24:24] + read-write + oneToClear + + + HAD_PSM_RESTART + Last reset was from the debug port + [20:20] + read-only + + + HAD_RUN + Last reset was from the RUN pin + [16:16] + read-only + + + HAD_POR + Last reset was from the power-on reset or brown-out detection blocks + [8:8] + read-only + + + + + + + RTC + Register block to control RTC + 0x4005c000 + + 0 + 48 + registers + + + RTC_IRQ + 25 + + + + CLKDIV_M1 + 0x00000000 + Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. + 0x00000000 + + + CLKDIV_M1 + [15:0] + read-write + + + + + SETUP_0 + 0x00000004 + RTC setup register 0 + 0x00000000 + + + YEAR + Year + [23:12] + read-write + + + MONTH + Month (1..12) + [11:8] + read-write + + + DAY + Day of the month (1..31) + [4:0] + read-write + + + + + SETUP_1 + 0x00000008 + RTC setup register 1 + 0x00000000 + + + DOTW + Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 + [26:24] + read-write + + + HOUR + Hours + [20:16] + read-write + + + MIN + Minutes + [13:8] + read-write + + + SEC + Seconds + [5:0] + read-write + + + + + CTRL + 0x0000000c + RTC Control and status + 0x00000000 + + + FORCE_NOTLEAPYEAR + If set, leapyear is forced off. + Useful for years divisible by 100 but not by 400 + [8:8] + read-write + + + LOAD + Load RTC + [4:4] + write-only + + + RTC_ACTIVE + RTC enabled (running) + [1:1] + read-only + + + RTC_ENABLE + Enable RTC + [0:0] + read-write + + + + + IRQ_SETUP_0 + 0x00000010 + Interrupt setup register 0 + 0x00000000 + + + MATCH_ACTIVE + [29:29] + read-only + + + MATCH_ENA + Global match enable. Don't change any other value while this one is enabled + [28:28] + read-write + + + YEAR_ENA + Enable year matching + [26:26] + read-write + + + MONTH_ENA + Enable month matching + [25:25] + read-write + + + DAY_ENA + Enable day matching + [24:24] + read-write + + + YEAR + Year + [23:12] + read-write + + + MONTH + Month (1..12) + [11:8] + read-write + + + DAY + Day of the month (1..31) + [4:0] + read-write + + + + + IRQ_SETUP_1 + 0x00000014 + Interrupt setup register 1 + 0x00000000 + + + DOTW_ENA + Enable day of the week matching + [31:31] + read-write + + + HOUR_ENA + Enable hour matching + [30:30] + read-write + + + MIN_ENA + Enable minute matching + [29:29] + read-write + + + SEC_ENA + Enable second matching + [28:28] + read-write + + + DOTW + Day of the week + [26:24] + read-write + + + HOUR + Hours + [20:16] + read-write + + + MIN + Minutes + [13:8] + read-write + + + SEC + Seconds + [5:0] + read-write + + + + + RTC_1 + 0x00000018 + RTC register 1. + 0x00000000 + + + YEAR + Year + [23:12] + read-only + + + MONTH + Month (1..12) + [11:8] + read-only + + + DAY + Day of the month (1..31) + [4:0] + read-only + + + + + RTC_0 + 0x0000001c + RTC register 0 + Read this before RTC 1! + 0x00000000 + + + DOTW + Day of the week + [26:24] + read-only + modify + + + HOUR + Hours + [20:16] + read-only + modify + + + MIN + Minutes + [13:8] + read-only + modify + + + SEC + Seconds + [5:0] + read-only + modify + + + + + INTR + 0x00000020 + Raw Interrupts + 0x00000000 + + + RTC + [0:0] + read-only + + + + + INTE + 0x00000024 + Interrupt Enable + 0x00000000 + + + RTC + [0:0] + read-write + + + + + INTF + 0x00000028 + Interrupt Force + 0x00000000 + + + RTC + [0:0] + read-write + + + + + INTS + 0x0000002c + Interrupt status after masking & forcing + 0x00000000 + + + RTC + [0:0] + read-only + + + + + + + diff --git a/src/rp2040/hardware_regs/include/hardware/platform_defs.h b/src/rp2040/hardware_regs/include/hardware/platform_defs.h index 5d635aed0..54d9344c8 100644 --- a/src/rp2040/hardware_regs/include/hardware/platform_defs.h +++ b/src/rp2040/hardware_regs/include/hardware/platform_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,40 +20,72 @@ #define NUM_CORES _u(2) #define NUM_DMA_CHANNELS _u(12) #define NUM_DMA_TIMERS _u(4) +#define NUM_DMA_IRQS _u(2) #define NUM_IRQS _u(32) #define NUM_USER_IRQS _u(6) #define NUM_PIOS _u(2) #define NUM_PIO_STATE_MACHINES _u(4) +#define NUM_PIO_IRQS _u(2) #define NUM_PWM_SLICES _u(8) +#define NUM_PWM_IRQS _u(1) #define NUM_SPIN_LOCKS _u(32) #define NUM_UARTS _u(2) #define NUM_I2CS _u(2) #define NUM_SPIS _u(2) -#define NUM_TIMERS _u(4) +#define NUM_GENERIC_TIMERS _u(1) +#define NUM_ALARMS _u(4) +#define ADC_BASE_PIN _u(26) #define NUM_ADC_CHANNELS _u(5) - +#define NUM_RESETS _u(24) #define NUM_BANK0_GPIOS _u(30) #define NUM_QSPI_GPIOS _u(6) #define PIO_INSTRUCTION_COUNT _u(32) -// PICO_CONFIG: XOSC_KHZ, The crystal oscillator frequency in kHz, type=int, default=12000, advanced=true, group=hardware_base +#define USBCTRL_DPRAM_SIZE _u(4096) + +#define HAS_SIO_DIVIDER 1 +#define HAS_RP2040_RTC 1 +// PICO_CONFIG: XOSC_HZ, Crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base // NOTE: The system and USB clocks are generated from the frequency using two PLLs. -// If you override this define, or SYS_CLK_KHZ/USB_CLK_KHZ below, you will *also* need to add your own adjusted PLL set-up defines to +// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to // override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h // Please see the comments there about calculating the new PLL setting values. -#ifndef XOSC_KHZ -#define XOSC_KHZ _u(12000) +#ifndef XOSC_HZ +#ifdef XOSC_KHZ +#define XOSC_HZ ((XOSC_KHZ) * _u(1000)) +#elif defined(XOSC_MHZ) +#define XOSC_HZ ((XOSC_MHZ) * _u(1000000)) +#else +#define XOSC_HZ _u(12000000) +#endif #endif -// PICO_CONFIG: SYS_CLK_KHZ, The system operating frequency in kHz, type=int, default=125000, advanced=true, group=hardware_base -#ifndef SYS_CLK_KHZ -#define SYS_CLK_KHZ _u(125000) +// PICO_CONFIG: SYS_CLK_HZ, System operating frequency in Hz, type=int, default=125000000, advanced=true, group=hardware_base +#ifndef SYS_CLK_HZ +#ifdef SYS_CLK_KHZ +#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000)) +#elif defined(SYS_CLK_MHZ) +#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000)) +#else +#define SYS_CLK_HZ _u(125000000) +#endif #endif -// PICO_CONFIG: USB_CLK_KHZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000, advanced=true, group=hardware_base -#ifndef USB_CLK_KHZ -#define USB_CLK_KHZ _u(48000) +// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base +#ifndef USB_CLK_HZ +#ifdef USB_CLK_KHZ +#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000)) +#elif defined(USB_CLK_MHZ) +#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000)) +#else +#define USB_CLK_HZ _u(48000000) +#endif +#endif + +// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz. +#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0) +#define XOSC_KHZ (XOSC_HZ / 1000) #endif // For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz. @@ -61,11 +93,21 @@ #define XOSC_MHZ (XOSC_KHZ / 1000) #endif +// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0) +#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000) +#endif + // For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz. #if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0) #define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000) #endif +// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0) +#define USB_CLK_KHZ (USB_CLK_HZ / 1000) +#endif + // For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz. #if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0) #define USB_CLK_MHZ (USB_CLK_KHZ / 1000) @@ -75,4 +117,3 @@ #define VTABLE_FIRST_IRQ 16 #endif - diff --git a/src/rp2040/hardware_regs/include/hardware/regs/adc.h b/src/rp2040/hardware_regs/include/hardware/regs/adc.h index 47510be51..3077f1624 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/adc.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/adc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Control and data interface to SAR ADC // ============================================================================= -#ifndef HARDWARE_REGS_ADC_DEFINED -#define HARDWARE_REGS_ADC_DEFINED +#ifndef _HARDWARE_REGS_ADC_H +#define _HARDWARE_REGS_ADC_H // ============================================================================= // Register : ADC_CS // Description : ADC Control and Status @@ -25,8 +27,8 @@ // round-robin fashion. // The first channel to be sampled will be the one currently // indicated by AINSEL. -// AINSEL will be updated after each conversion with the -// newly-selected channel. +// AINSEL will be updated after each conversion with the newly- +// selected channel. #define ADC_CS_RROBIN_RESET _u(0x00) #define ADC_CS_RROBIN_BITS _u(0x001f0000) #define ADC_CS_RROBIN_MSB _u(20) @@ -153,7 +155,6 @@ #define ADC_FCS_UNDER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_FCS_FULL -// Description : None #define ADC_FCS_FULL_RESET _u(0x0) #define ADC_FCS_FULL_BITS _u(0x00000200) #define ADC_FCS_FULL_MSB _u(9) @@ -161,7 +162,6 @@ #define ADC_FCS_FULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_EMPTY -// Description : None #define ADC_FCS_EMPTY_RESET _u(0x0) #define ADC_FCS_EMPTY_BITS _u(0x00000100) #define ADC_FCS_EMPTY_MSB _u(8) @@ -218,7 +218,6 @@ #define ADC_FIFO_ERR_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : ADC_FIFO_VAL -// Description : None #define ADC_FIFO_VAL_RESET "-" #define ADC_FIFO_VAL_BITS _u(0x00000fff) #define ADC_FIFO_VAL_MSB _u(11) @@ -311,4 +310,5 @@ #define ADC_INTS_FIFO_LSB _u(0) #define ADC_INTS_FIFO_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_ADC_DEFINED +#endif // _HARDWARE_REGS_ADC_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h b/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h index b39ab45fd..61da68c5b 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/addressmap.h @@ -1,18 +1,24 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _ADDRESSMAP_H_ -#define _ADDRESSMAP_H_ +#ifndef _ADDRESSMAP_H +#define _ADDRESSMAP_H + +/** + * \file rp2040/addressmap.h + */ #include "hardware/platform_defs.h" // Register address offsets for atomic RMW aliases -#define REG_ALIAS_RW_BITS (0x0u << 12u) -#define REG_ALIAS_XOR_BITS (0x1u << 12u) -#define REG_ALIAS_SET_BITS (0x2u << 12u) -#define REG_ALIAS_CLR_BITS (0x3u << 12u) +#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) +#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) +#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) +#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) #define ROM_BASE _u(0x00000000) #define XIP_BASE _u(0x10000000) @@ -71,4 +77,5 @@ #define SIO_BASE _u(0xd0000000) #define PPB_BASE _u(0xe0000000) -#endif // _ADDRESSMAP_H_ +#endif // _ADDRESSMAP_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h b/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h index 8be0d8666..ee5f153e2 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/busctrl.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +12,8 @@ // Description : Register block for busfabric control signals and performance // counters // ============================================================================= -#ifndef HARDWARE_REGS_BUSCTRL_DEFINED -#define HARDWARE_REGS_BUSCTRL_DEFINED +#ifndef _HARDWARE_REGS_BUSCTRL_H +#define _HARDWARE_REGS_BUSCTRL_H // ============================================================================= // Register : BUSCTRL_BUS_PRIORITY // Description : Set the priority of each master for bus arbitration. @@ -102,32 +104,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c) -#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL0_MSB _u(4) -#define BUSCTRL_PERFSEL0_LSB _u(0) -#define BUSCTRL_PERFSEL0_ACCESS "RW" -#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c) +#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL0_MSB _u(4) +#define BUSCTRL_PERFSEL0_LSB _u(0) +#define BUSCTRL_PERFSEL0_ACCESS "RW" +#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR1 // Description : Bus fabric performance counter 1 @@ -166,32 +168,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014) -#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL1_MSB _u(4) -#define BUSCTRL_PERFSEL1_LSB _u(0) -#define BUSCTRL_PERFSEL1_ACCESS "RW" -#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014) +#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL1_MSB _u(4) +#define BUSCTRL_PERFSEL1_LSB _u(0) +#define BUSCTRL_PERFSEL1_ACCESS "RW" +#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR2 // Description : Bus fabric performance counter 2 @@ -230,32 +232,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c) -#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL2_MSB _u(4) -#define BUSCTRL_PERFSEL2_LSB _u(0) -#define BUSCTRL_PERFSEL2_ACCESS "RW" -#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c) +#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL2_MSB _u(4) +#define BUSCTRL_PERFSEL2_LSB _u(0) +#define BUSCTRL_PERFSEL2_ACCESS "RW" +#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR3 // Description : Bus fabric performance counter 3 @@ -294,31 +296,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024) -#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL3_MSB _u(4) -#define BUSCTRL_PERFSEL3_LSB _u(0) -#define BUSCTRL_PERFSEL3_ACCESS "RW" -#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024) +#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL3_MSB _u(4) +#define BUSCTRL_PERFSEL3_LSB _u(0) +#define BUSCTRL_PERFSEL3_ACCESS "RW" +#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13) // ============================================================================= -#endif // HARDWARE_REGS_BUSCTRL_DEFINED +#endif // _HARDWARE_REGS_BUSCTRL_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/clocks.h b/src/rp2040/hardware_regs/include/hardware/regs/clocks.h index c0d2eaba4..7c604b9b6 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/clocks.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/clocks.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : CLOCKS // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_CLOCKS_DEFINED -#define HARDWARE_REGS_CLOCKS_DEFINED +#ifndef _HARDWARE_REGS_CLOCKS_H +#define _HARDWARE_REGS_CLOCKS_H // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) @@ -75,22 +76,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_DIV // Description : Clock divisor, can be changed on-the-fly @@ -190,22 +191,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_DIV // Description : Clock divisor, can be changed on-the-fly @@ -305,22 +306,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_DIV // Description : Clock divisor, can be changed on-the-fly @@ -420,22 +421,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_DIV // Description : Clock divisor, can be changed on-the-fly @@ -483,29 +484,29 @@ // 0x0 -> clksrc_pll_usb // 0x1 -> clksrc_gpin0 // 0x2 -> clksrc_gpin1 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed -// on-the-fly +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly // 0x0 -> rosc_clksrc_ph // 0x1 -> clksrc_clk_ref_aux // 0x2 -> xosc_clksrc -#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" -#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) -#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) -#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) +#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" +#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) +#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) #define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) // ============================================================================= // Register : CLOCKS_CLK_REF_DIV // Description : Clock divisor, can be changed on-the-fly @@ -553,29 +554,29 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed -// on-the-fly +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly // 0x0 -> clk_ref // 0x1 -> clksrc_clk_sys_aux -#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) #define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) // ============================================================================= // Register : CLOCKS_CLK_SYS_DIV @@ -649,18 +650,18 @@ // 0x4 -> xosc_clksrc // 0x5 -> clksrc_gpin0 // 0x6 -> clksrc_gpin1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) // ============================================================================= // Register : CLOCKS_CLK_PERI_SELECTED // Description : Indicates which SRC is currently selected by the glitchless mux @@ -725,17 +726,17 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_USB_DIV // Description : Clock divisor, can be changed on-the-fly @@ -814,17 +815,17 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_ADC_DIV // Description : Clock divisor, can be changed on-the-fly @@ -903,17 +904,17 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_RTC_DIV // Description : Clock divisor, can be changed on-the-fly @@ -951,7 +952,6 @@ #define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_CTRL -// Description : None #define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078) #define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) #define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) @@ -991,7 +991,6 @@ #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_STATUS -// Description : None #define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c) #define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) #define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) @@ -1073,26 +1072,26 @@ // 0x0b -> clk_usb // 0x0c -> clk_adc // 0x0d -> clk_rtc -#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094) -#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) -#define CLOCKS_FC0_SRC_RESET _u(0x00000000) -#define CLOCKS_FC0_SRC_MSB _u(7) -#define CLOCKS_FC0_SRC_LSB _u(0) -#define CLOCKS_FC0_SRC_ACCESS "RW" -#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) +#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094) +#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) +#define CLOCKS_FC0_SRC_RESET _u(0x00000000) +#define CLOCKS_FC0_SRC_MSB _u(7) +#define CLOCKS_FC0_SRC_LSB _u(0) +#define CLOCKS_FC0_SRC_ACCESS "RW" +#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) #define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) #define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) -#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) -#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) -#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) -#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) -#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) -#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) -#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) +#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) +#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) +#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d) // ============================================================================= // Register : CLOCKS_FC0_STATUS // Description : Frequency counter status @@ -1171,7 +1170,6 @@ #define CLOCKS_FC0_RESULT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_KHZ -// Description : None #define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) #define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) #define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) @@ -1179,7 +1177,6 @@ #define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_FRAC -// Description : None #define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) #define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) #define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) @@ -1193,7 +1190,6 @@ #define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _u(31) @@ -1201,7 +1197,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _u(30) @@ -1209,7 +1204,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _u(29) @@ -1217,7 +1211,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _u(28) @@ -1225,7 +1218,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _u(27) @@ -1233,7 +1225,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _u(26) @@ -1241,7 +1232,6 @@ #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _u(25) @@ -1249,7 +1239,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _u(24) @@ -1257,7 +1246,6 @@ #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x00800000) #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(23) @@ -1265,7 +1253,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _u(0x00400000) #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _u(22) @@ -1273,7 +1260,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC -// Description : None #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _u(0x00200000) #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _u(21) @@ -1281,7 +1267,6 @@ #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(20) @@ -1289,7 +1274,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x00080000) #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(19) @@ -1297,7 +1281,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(18) @@ -1305,7 +1288,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x00020000) #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(17) @@ -1313,7 +1295,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x00010000) #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(16) @@ -1321,7 +1302,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(15) @@ -1329,7 +1309,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(14) @@ -1337,7 +1316,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(13) @@ -1345,7 +1323,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(12) @@ -1353,7 +1330,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00000800) #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(11) @@ -1361,7 +1337,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) @@ -1369,7 +1344,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(9) @@ -1377,7 +1351,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_IO -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00000100) #define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(8) @@ -1385,7 +1358,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(7) @@ -1393,7 +1365,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(6) @@ -1401,7 +1372,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000020) #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(5) @@ -1409,7 +1379,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) @@ -1417,7 +1386,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(3) @@ -1425,7 +1393,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000004) #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(2) @@ -1433,7 +1400,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC -// Description : None #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _u(0x00000002) #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _u(1) @@ -1441,7 +1407,6 @@ #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) @@ -1455,7 +1420,6 @@ #define CLOCKS_WAKE_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(14) @@ -1463,7 +1427,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x00002000) #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(13) @@ -1471,7 +1434,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(12) @@ -1479,7 +1441,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL -// Description : None #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _u(11) @@ -1487,7 +1448,6 @@ #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(10) @@ -1495,7 +1455,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x00000200) #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(9) @@ -1503,7 +1462,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 -// Description : None #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x00000100) #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(8) @@ -1511,7 +1469,6 @@ #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00000080) #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(7) @@ -1519,7 +1476,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 -// Description : None #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00000040) #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(6) @@ -1527,7 +1483,6 @@ #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _u(5) @@ -1535,7 +1490,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(4) @@ -1543,7 +1497,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(3) @@ -1551,7 +1504,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(2) @@ -1559,7 +1511,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(1) @@ -1567,7 +1518,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(0) @@ -1581,7 +1531,6 @@ #define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _u(31) @@ -1589,7 +1538,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _u(30) @@ -1597,7 +1545,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _u(29) @@ -1605,7 +1552,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _u(28) @@ -1613,7 +1559,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _u(27) @@ -1621,7 +1566,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _u(26) @@ -1629,7 +1573,6 @@ #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _u(25) @@ -1637,7 +1580,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _u(24) @@ -1645,7 +1587,6 @@ #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x00800000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(23) @@ -1653,7 +1594,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _u(0x00400000) #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _u(22) @@ -1661,7 +1601,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _u(0x00200000) #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _u(21) @@ -1669,7 +1608,6 @@ #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(20) @@ -1677,7 +1615,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x00080000) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(19) @@ -1685,7 +1622,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(18) @@ -1693,7 +1629,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x00020000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(17) @@ -1701,7 +1636,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x00010000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(16) @@ -1709,7 +1643,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(15) @@ -1717,7 +1650,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(14) @@ -1725,7 +1657,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(13) @@ -1733,7 +1664,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(12) @@ -1741,7 +1671,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00000800) #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(11) @@ -1749,7 +1678,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) @@ -1757,7 +1685,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(9) @@ -1765,7 +1692,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00000100) #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(8) @@ -1773,7 +1699,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(7) @@ -1781,7 +1706,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(6) @@ -1789,7 +1713,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000020) #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(5) @@ -1797,7 +1720,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) @@ -1805,7 +1727,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(3) @@ -1813,7 +1734,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000004) #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(2) @@ -1821,7 +1741,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _u(0x00000002) #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _u(1) @@ -1829,7 +1748,6 @@ #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) @@ -1843,7 +1761,6 @@ #define CLOCKS_SLEEP_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(14) @@ -1851,7 +1768,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x00002000) #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(13) @@ -1859,7 +1775,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(12) @@ -1867,7 +1782,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL -// Description : None #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _u(11) @@ -1875,7 +1789,6 @@ #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(10) @@ -1883,7 +1796,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x00000200) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(9) @@ -1891,7 +1803,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x00000100) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(8) @@ -1899,7 +1810,6 @@ #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00000080) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(7) @@ -1907,7 +1817,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00000040) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(6) @@ -1915,7 +1824,6 @@ #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _u(5) @@ -1923,7 +1831,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(4) @@ -1931,7 +1838,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(3) @@ -1939,7 +1845,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(2) @@ -1947,7 +1852,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(1) @@ -1955,7 +1859,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(0) @@ -1969,7 +1872,6 @@ #define CLOCKS_ENABLED0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _u(0x80000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _u(31) @@ -1977,7 +1879,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _u(0x40000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _u(30) @@ -1985,7 +1886,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _u(0x20000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _u(29) @@ -1993,7 +1893,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _u(0x10000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _u(28) @@ -2001,7 +1900,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _u(0x08000000) #define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _u(27) @@ -2009,7 +1907,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI1 -// Description : None #define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _u(0x04000000) #define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _u(26) @@ -2017,7 +1914,6 @@ #define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _u(0x02000000) #define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _u(25) @@ -2025,7 +1921,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI0 -// Description : None #define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _u(0x01000000) #define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _u(24) @@ -2033,7 +1928,6 @@ #define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SIO -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x00800000) #define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(23) @@ -2041,7 +1935,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RTC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _u(0x00400000) #define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _u(22) @@ -2049,7 +1942,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_RTC_RTC -// Description : None #define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _u(0x00200000) #define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _u(21) @@ -2057,7 +1949,6 @@ #define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROSC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x00100000) #define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(20) @@ -2065,7 +1956,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROM -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x00080000) #define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(19) @@ -2073,7 +1963,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RESETS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x00040000) #define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(18) @@ -2081,7 +1970,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PWM -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x00020000) #define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(17) @@ -2089,7 +1977,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PSM -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x00010000) #define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(16) @@ -2097,7 +1984,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00008000) #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(15) @@ -2105,7 +1991,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(14) @@ -2113,7 +1998,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00002000) #define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(13) @@ -2121,7 +2005,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00001000) #define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(12) @@ -2129,7 +2012,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PADS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00000800) #define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(11) @@ -2137,7 +2019,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) @@ -2145,7 +2026,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_JTAG -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00000200) #define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(9) @@ -2153,7 +2033,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_IO -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00000100) #define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(8) @@ -2161,7 +2040,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00000080) #define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(7) @@ -2169,7 +2047,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000040) #define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(6) @@ -2177,7 +2054,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_DMA -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000020) #define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(5) @@ -2185,7 +2061,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(4) @@ -2193,7 +2068,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(3) @@ -2201,7 +2075,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ADC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000004) #define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(2) @@ -2209,7 +2082,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_ADC_ADC -// Description : None #define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _u(0x00000002) #define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _u(1) @@ -2217,7 +2089,6 @@ #define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) @@ -2231,7 +2102,6 @@ #define CLOCKS_ENABLED1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XOSC -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x00004000) #define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(14) @@ -2239,7 +2109,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XIP -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x00002000) #define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(13) @@ -2247,7 +2116,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(12) @@ -2255,7 +2123,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL -// Description : None #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _u(0x00000800) #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _u(11) @@ -2263,7 +2130,6 @@ #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x00000400) #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(10) @@ -2271,7 +2137,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART1 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x00000200) #define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(9) @@ -2279,7 +2144,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART1 -// Description : None #define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x00000100) #define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(8) @@ -2287,7 +2151,6 @@ #define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART0 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00000080) #define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(7) @@ -2295,7 +2158,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART0 -// Description : None #define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00000040) #define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(6) @@ -2303,7 +2165,6 @@ #define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TIMER -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _u(0x00000020) #define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _u(5) @@ -2311,7 +2172,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00000010) #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(4) @@ -2319,7 +2179,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00000008) #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(3) @@ -2327,7 +2186,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00000004) #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(2) @@ -2335,7 +2193,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000002) #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(1) @@ -2343,7 +2200,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000001) #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(0) @@ -2357,7 +2213,6 @@ #define CLOCKS_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTR_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) @@ -2371,7 +2226,6 @@ #define CLOCKS_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTE_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) @@ -2385,7 +2239,6 @@ #define CLOCKS_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTF_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) @@ -2399,11 +2252,11 @@ #define CLOCKS_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTS_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) #define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_CLOCKS_DEFINED +#endif // _HARDWARE_REGS_CLOCKS_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dma.h b/src/rp2040/hardware_regs/include/hardware/regs/dma.h index e14a9b014..62a37ec09 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/dma.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/dma.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : DMA with separate read and write masters // ============================================================================= -#ifndef HARDWARE_REGS_DMA_DEFINED -#define HARDWARE_REGS_DMA_DEFINED +#ifndef _HARDWARE_REGS_DMA_H +#define _HARDWARE_REGS_DMA_H // ============================================================================= // Register : DMA_CH0_READ_ADDR // Description : DMA Channel 0 Read Address pointer @@ -124,8 +126,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -168,15 +170,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_CHAIN_TO @@ -209,11 +211,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_INCR_WRITE @@ -247,14 +249,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -512,8 +514,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -556,15 +558,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_CHAIN_TO @@ -597,11 +599,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_INCR_WRITE @@ -635,14 +637,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -900,8 +902,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -944,15 +946,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_CHAIN_TO @@ -985,11 +987,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_INCR_WRITE @@ -1023,14 +1025,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1288,8 +1290,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -1332,15 +1334,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_CHAIN_TO @@ -1373,11 +1375,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_INCR_WRITE @@ -1411,14 +1413,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1676,8 +1678,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -1720,15 +1722,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_CHAIN_TO @@ -1761,11 +1763,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_INCR_WRITE @@ -1799,14 +1801,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2064,8 +2066,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -2108,15 +2110,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_CHAIN_TO @@ -2149,11 +2151,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_INCR_WRITE @@ -2187,14 +2189,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2452,8 +2454,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -2496,15 +2498,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_CHAIN_TO @@ -2537,11 +2539,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_INCR_WRITE @@ -2575,14 +2577,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2840,8 +2842,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -2884,15 +2886,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_CHAIN_TO @@ -2925,11 +2927,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_INCR_WRITE @@ -2963,14 +2965,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3228,8 +3230,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -3272,15 +3274,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_CHAIN_TO @@ -3313,11 +3315,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_INCR_WRITE @@ -3351,14 +3353,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3616,8 +3618,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -3660,15 +3662,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_CHAIN_TO @@ -3701,11 +3703,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_INCR_WRITE @@ -3739,14 +3741,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4004,8 +4006,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -4048,15 +4050,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_CHAIN_TO @@ -4089,11 +4091,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_INCR_WRITE @@ -4127,14 +4129,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4392,8 +4394,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -4436,15 +4438,15 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_CHAIN_TO @@ -4477,11 +4479,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_INCR_WRITE @@ -4515,14 +4517,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4925,26 +4927,23 @@ #define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_CALC -// Description : 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) -// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit -// reversed data +// 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data // 0x2 -> Calculate a CRC-16-CCITT // 0x3 -> Calculate a CRC-16-CCITT with bit reversed data -// 0xe -> XOR reduction over all data. == 1 if the total 1 -// population count is odd. -// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 -// bit accumulator) -#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) -#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) -#define DMA_SNIFF_CTRL_CALC_MSB _u(8) -#define DMA_SNIFF_CTRL_CALC_LSB _u(5) -#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) +// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) +#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) +#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) +#define DMA_SNIFF_CTRL_CALC_MSB _u(8) +#define DMA_SNIFF_CTRL_CALC_LSB _u(5) +#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) #define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) #define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) -#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) -#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_DMACH // Description : DMA channel for Sniffer to observe @@ -5298,4 +5297,5 @@ #define DMA_CH11_DBG_TCR_LSB _u(0) #define DMA_CH11_DBG_TCR_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_DMA_DEFINED +#endif // _HARDWARE_REGS_DMA_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/dreq.h b/src/rp2040/hardware_regs/include/hardware/regs/dreq.h index 9de9dd5fd..d3359f846 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/dreq.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/dreq.h @@ -1,50 +1,117 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _DREQ_H_ -#define _DREQ_H_ +#ifndef _DREQ_H +#define _DREQ_H + +/** + * \file rp2040/dreq.h + */ + +#ifdef __ASSEMBLER__ +#define DREQ_PIO0_TX0 0 +#define DREQ_PIO0_TX1 1 +#define DREQ_PIO0_TX2 2 +#define DREQ_PIO0_TX3 3 +#define DREQ_PIO0_RX0 4 +#define DREQ_PIO0_RX1 5 +#define DREQ_PIO0_RX2 6 +#define DREQ_PIO0_RX3 7 +#define DREQ_PIO1_TX0 8 +#define DREQ_PIO1_TX1 9 +#define DREQ_PIO1_TX2 10 +#define DREQ_PIO1_TX3 11 +#define DREQ_PIO1_RX0 12 +#define DREQ_PIO1_RX1 13 +#define DREQ_PIO1_RX2 14 +#define DREQ_PIO1_RX3 15 +#define DREQ_SPI0_TX 16 +#define DREQ_SPI0_RX 17 +#define DREQ_SPI1_TX 18 +#define DREQ_SPI1_RX 19 +#define DREQ_UART0_TX 20 +#define DREQ_UART0_RX 21 +#define DREQ_UART1_TX 22 +#define DREQ_UART1_RX 23 +#define DREQ_PWM_WRAP0 24 +#define DREQ_PWM_WRAP1 25 +#define DREQ_PWM_WRAP2 26 +#define DREQ_PWM_WRAP3 27 +#define DREQ_PWM_WRAP4 28 +#define DREQ_PWM_WRAP5 29 +#define DREQ_PWM_WRAP6 30 +#define DREQ_PWM_WRAP7 31 +#define DREQ_I2C0_TX 32 +#define DREQ_I2C0_RX 33 +#define DREQ_I2C1_TX 34 +#define DREQ_I2C1_RX 35 +#define DREQ_ADC 36 +#define DREQ_XIP_STREAM 37 +#define DREQ_XIP_SSITX 38 +#define DREQ_XIP_SSIRX 39 +#define DREQ_DMA_TIMER0 59 +#define DREQ_DMA_TIMER1 60 +#define DREQ_DMA_TIMER2 61 +#define DREQ_DMA_TIMER3 62 +#define DREQ_FORCE 63 +#else +/** + * \brief DREQ numbers for DMA pacing on RP2040 (used as typedef \ref dreq_num_t) + * \ingroup hardware_dma + */ +typedef enum dreq_num_rp2040 { + DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ + DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ + DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ + DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ + DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ + DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ + DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ + DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ + DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ + DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ + DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ + DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ + DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ + DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ + DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ + DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ + DREQ_SPI0_TX = 16, ///< Select SPI0's TX FIFO as DREQ + DREQ_SPI0_RX = 17, ///< Select SPI0's RX FIFO as DREQ + DREQ_SPI1_TX = 18, ///< Select SPI1's TX FIFO as DREQ + DREQ_SPI1_RX = 19, ///< Select SPI1's RX FIFO as DREQ + DREQ_UART0_TX = 20, ///< Select UART0's TX FIFO as DREQ + DREQ_UART0_RX = 21, ///< Select UART0's RX FIFO as DREQ + DREQ_UART1_TX = 22, ///< Select UART1's TX FIFO as DREQ + DREQ_UART1_RX = 23, ///< Select UART1's RX FIFO as DREQ + DREQ_PWM_WRAP0 = 24, ///< Select PWM Counter 0's Wrap Value as DREQ + DREQ_PWM_WRAP1 = 25, ///< Select PWM Counter 1's Wrap Value as DREQ + DREQ_PWM_WRAP2 = 26, ///< Select PWM Counter 2's Wrap Value as DREQ + DREQ_PWM_WRAP3 = 27, ///< Select PWM Counter 3's Wrap Value as DREQ + DREQ_PWM_WRAP4 = 28, ///< Select PWM Counter 4's Wrap Value as DREQ + DREQ_PWM_WRAP5 = 29, ///< Select PWM Counter 5's Wrap Value as DREQ + DREQ_PWM_WRAP6 = 30, ///< Select PWM Counter 6's Wrap Value as DREQ + DREQ_PWM_WRAP7 = 31, ///< Select PWM Counter 7's Wrap Value as DREQ + DREQ_I2C0_TX = 32, ///< Select I2C0's TX FIFO as DREQ + DREQ_I2C0_RX = 33, ///< Select I2C0's RX FIFO as DREQ + DREQ_I2C1_TX = 34, ///< Select I2C1's TX FIFO as DREQ + DREQ_I2C1_RX = 35, ///< Select I2C1's RX FIFO as DREQ + DREQ_ADC = 36, ///< Select the ADC as DREQ + DREQ_XIP_STREAM = 37, ///< Select the XIP Streaming FIFO as DREQ + DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ + DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ + DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ + DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ + DREQ_FORCE = 63, ///< Select FORCE as DREQ + DREQ_COUNT +} dreq_num_t; +#endif -#define DREQ_PIO0_TX0 0x0 -#define DREQ_PIO0_TX1 0x1 -#define DREQ_PIO0_TX2 0x2 -#define DREQ_PIO0_TX3 0x3 -#define DREQ_PIO0_RX0 0x4 -#define DREQ_PIO0_RX1 0x5 -#define DREQ_PIO0_RX2 0x6 -#define DREQ_PIO0_RX3 0x7 -#define DREQ_PIO1_TX0 0x8 -#define DREQ_PIO1_TX1 0x9 -#define DREQ_PIO1_TX2 0xa -#define DREQ_PIO1_TX3 0xb -#define DREQ_PIO1_RX0 0xc -#define DREQ_PIO1_RX1 0xd -#define DREQ_PIO1_RX2 0xe -#define DREQ_PIO1_RX3 0xf -#define DREQ_SPI0_TX 0x10 -#define DREQ_SPI0_RX 0x11 -#define DREQ_SPI1_TX 0x12 -#define DREQ_SPI1_RX 0x13 -#define DREQ_UART0_TX 0x14 -#define DREQ_UART0_RX 0x15 -#define DREQ_UART1_TX 0x16 -#define DREQ_UART1_RX 0x17 -#define DREQ_PWM_WRAP0 0x18 -#define DREQ_PWM_WRAP1 0x19 -#define DREQ_PWM_WRAP2 0x1a -#define DREQ_PWM_WRAP3 0x1b -#define DREQ_PWM_WRAP4 0x1c -#define DREQ_PWM_WRAP5 0x1d -#define DREQ_PWM_WRAP6 0x1e -#define DREQ_PWM_WRAP7 0x1f -#define DREQ_I2C0_TX 0x20 -#define DREQ_I2C0_RX 0x21 -#define DREQ_I2C1_TX 0x22 -#define DREQ_I2C1_RX 0x23 -#define DREQ_ADC 0x24 -#define DREQ_XIP_STREAM 0x25 -#define DREQ_XIP_SSITX 0x26 -#define DREQ_XIP_SSIRX 0x27 +#endif // _DREQ_H -#endif // _DREQ_H_ diff --git a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h index dcddb06a0..f44ceb440 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/i2c.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/i2c.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,8 +85,8 @@ // IC_DEFAULT_UFM_SPKLEN ............. 0x1 // IC_TX_BUFFER_DEPTH ................ 16 // ============================================================================= -#ifndef HARDWARE_REGS_I2C_DEFINED -#define HARDWARE_REGS_I2C_DEFINED +#ifndef _HARDWARE_REGS_I2C_H +#define _HARDWARE_REGS_I2C_H // ============================================================================= // Register : I2C_IC_CON // Description : I2C Control Register. This register can be written only when @@ -116,13 +118,13 @@ // Reset value: 0x0. // 0x0 -> Overflow when RX_FIFO is full // 0x1 -> Hold bus when RX_FIFO is full -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" #define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_TX_EMPTY_CTRL // Description : This bit controls the generation of the TX_EMPTY interrupt, as @@ -131,13 +133,13 @@ // Reset value: 0x0. // 0x0 -> Default behaviour of TX_EMPTY interrupt // 0x1 -> Controlled generation of TX_EMPTY interrupt -#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) -#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" #define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_STOP_DET_IFADDRESSED // Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when @@ -151,13 +153,13 @@ // transmitted address matches the slave address (SAR). // 0x0 -> slave issues STOP_DET intr always // 0x1 -> slave issues STOP_DET intr only if addressed -#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" #define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_SLAVE_DISABLE // Description : This bit controls whether I2C has its slave disabled, which @@ -172,12 +174,12 @@ // 0, then bit 0 should also be written with a 0. // 0x0 -> Slave mode is enabled // 0x1 -> Slave mode is disabled -#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) -#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) -#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) #define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_RESTART_EN @@ -186,25 +188,25 @@ // conditions; however, RESTART conditions are used in several // DW_apb_i2c operations. When RESTART is disabled, the master is // prohibited from performing the following functions: - Sending a -// START BYTE - Performing any high-speed mode operation - -// High-speed mode operation - Performing direction changes in -// combined format mode - Performing a read operation with a -// 10-bit address By replacing RESTART condition followed by a -// STOP and a subsequent START condition, split operations are -// broken down into multiple DW_apb_i2c transfers. If the above -// operations are performed, it will result in setting bit 6 -// (TX_ABRT) of the IC_RAW_INTR_STAT register. +// START BYTE - Performing any high-speed mode operation - High- +// speed mode operation - Performing direction changes in combined +// format mode - Performing a read operation with a 10-bit address +// By replacing RESTART condition followed by a STOP and a +// subsequent START condition, split operations are broken down +// into multiple DW_apb_i2c transfers. If the above operations are +// performed, it will result in setting bit 6 (TX_ABRT) of the +// IC_RAW_INTR_STAT register. // // Reset value: ENABLED // 0x0 -> Master restart disabled // 0x1 -> Master restart enabled -#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) -#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) -#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" +#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) +#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" #define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_MASTER // Description : Controls whether the DW_apb_i2c starts its transfers in 7- or @@ -212,12 +214,12 @@ // addressing - 1: 10-bit addressing // 0x0 -> Master 7Bit addressing mode // 0x1 -> Master 10Bit addressing mode -#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) -#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) #define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_SLAVE @@ -230,12 +232,12 @@ // that match the full 10 bits of the IC_SAR register. // 0x0 -> Slave 7Bit addressing // 0x1 -> Slave 10Bit addressing -#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) #define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_SPEED @@ -260,14 +262,14 @@ // 0x1 -> Standard Speed mode of operation // 0x2 -> Fast or Fast Plus mode of operation // 0x3 -> High Speed mode of operation -#define I2C_IC_CON_SPEED_RESET _u(0x2) -#define I2C_IC_CON_SPEED_BITS _u(0x00000006) -#define I2C_IC_CON_SPEED_MSB _u(2) -#define I2C_IC_CON_SPEED_LSB _u(1) -#define I2C_IC_CON_SPEED_ACCESS "RW" +#define I2C_IC_CON_SPEED_RESET _u(0x2) +#define I2C_IC_CON_SPEED_BITS _u(0x00000006) +#define I2C_IC_CON_SPEED_MSB _u(2) +#define I2C_IC_CON_SPEED_LSB _u(1) +#define I2C_IC_CON_SPEED_ACCESS "RW" #define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) -#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) -#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) +#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) +#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_MASTER_MODE // Description : This bit controls whether the DW_apb_i2c master is enabled. @@ -276,13 +278,13 @@ // '1' then bit 6 should also be written with a '1'. // 0x0 -> Master mode is disabled // 0x1 -> Master mode is enabled -#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) -#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) -#define I2C_IC_CON_MASTER_MODE_MSB _u(0) -#define I2C_IC_CON_MASTER_MODE_LSB _u(0) -#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" +#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) +#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) +#define I2C_IC_CON_MASTER_MODE_MSB _u(0) +#define I2C_IC_CON_MASTER_MODE_LSB _u(0) +#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" #define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_TAR // Description : I2C Target Address Register @@ -307,17 +309,15 @@ // GC_OR_START and use IC_TAR normally - 1: perform special I2C // command as specified in Device_ID or GC_OR_START bit Reset // value: 0x0 -// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE -// transmission -// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE -// transmission -#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) -#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) -#define I2C_IC_TAR_SPECIAL_MSB _u(11) -#define I2C_IC_TAR_SPECIAL_LSB _u(11) -#define I2C_IC_TAR_SPECIAL_ACCESS "RW" +// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE transmission +// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE transmission +#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) +#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) +#define I2C_IC_TAR_SPECIAL_MSB _u(11) +#define I2C_IC_TAR_SPECIAL_LSB _u(11) +#define I2C_IC_TAR_SPECIAL_ACCESS "RW" #define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) -#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_GC_OR_START // Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to @@ -330,13 +330,13 @@ // value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 // 0x0 -> GENERAL_CALL byte transmission // 0x1 -> START byte transmission -#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) -#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) -#define I2C_IC_TAR_GC_OR_START_MSB _u(10) -#define I2C_IC_TAR_GC_OR_START_LSB _u(10) -#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" +#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) +#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) +#define I2C_IC_TAR_GC_OR_START_MSB _u(10) +#define I2C_IC_TAR_GC_OR_START_LSB _u(10) +#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" #define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) -#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_IC_TAR // Description : This is the target address for any master transaction. When @@ -421,13 +421,13 @@ // FIRST_DATA_BYTE status. // 0x0 -> Sequential data byte received // 0x1 -> Non sequential data byte received -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" #define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_RESTART // Description : This bit controls whether a RESTART is issued before the byte @@ -447,13 +447,13 @@ // Reset value: 0x0 // 0x0 -> Don't Issue RESTART before this command // 0x1 -> Issue RESTART before this command -#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) -#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" +#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) +#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" #define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_STOP // Description : This bit controls whether a STOP is issued after the byte is @@ -471,13 +471,13 @@ // is available in the Tx FIFO. Reset value: 0x0 // 0x0 -> Don't Issue STOP after this command // 0x1 -> Issue STOP after this command -#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) -#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) -#define I2C_IC_DATA_CMD_STOP_MSB _u(9) -#define I2C_IC_DATA_CMD_STOP_LSB _u(9) -#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" +#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) +#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) +#define I2C_IC_DATA_CMD_STOP_MSB _u(9) +#define I2C_IC_DATA_CMD_STOP_LSB _u(9) +#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" #define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_CMD // Description : This bit controls whether a read or a write is performed. This @@ -502,13 +502,13 @@ // Reset value: 0x0 // 0x0 -> Master Write Command // 0x1 -> Master Read Command -#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) -#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) -#define I2C_IC_DATA_CMD_CMD_MSB _u(8) -#define I2C_IC_DATA_CMD_CMD_LSB _u(8) -#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" +#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) +#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) +#define I2C_IC_DATA_CMD_CMD_MSB _u(8) +#define I2C_IC_DATA_CMD_CMD_LSB _u(8) +#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" #define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) -#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) +#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_DAT // Description : This register contains the data to be transmitted or received @@ -626,9 +626,9 @@ // Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT // Description : This register must be set before any I2C bus transaction can // take place to ensure proper I/O timing. This register sets the -// SCL clock low period count for fast speed. It is used in -// high-speed mode to send the Master Code and START BYTE or -// General CALL. For more information, refer to 'IC_CLK Frequency +// SCL clock low period count for fast speed. It is used in high- +// speed mode to send the Master Code and START BYTE or General +// CALL. For more information, refer to 'IC_CLK Frequency // Configuration'. // // This register goes away and becomes read-only returning 0s if @@ -669,13 +669,13 @@ // Reset value: 0x0 // 0x0 -> R_RESTART_DET interrupt is inactive // 0x1 -> R_RESTART_DET interrupt is active -#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_GEN_CALL // Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL @@ -684,13 +684,13 @@ // Reset value: 0x0 // 0x0 -> R_GEN_CALL interrupt is inactive // 0x1 -> R_GEN_CALL interrupt is active -#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" #define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_START_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET @@ -699,13 +699,13 @@ // Reset value: 0x0 // 0x0 -> R_START_DET interrupt is inactive // 0x1 -> R_START_DET interrupt is active -#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" #define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_STOP_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET @@ -714,13 +714,13 @@ // Reset value: 0x0 // 0x0 -> R_STOP_DET interrupt is inactive // 0x1 -> R_STOP_DET interrupt is active -#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" #define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_ACTIVITY // Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY @@ -729,13 +729,13 @@ // Reset value: 0x0 // 0x0 -> R_ACTIVITY interrupt is inactive // 0x1 -> R_ACTIVITY interrupt is active -#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" #define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_DONE // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE @@ -744,13 +744,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_DONE interrupt is inactive // 0x1 -> R_RX_DONE interrupt is active -#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_ABRT // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT @@ -759,13 +759,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_ABRT interrupt is inactive // 0x1 -> R_TX_ABRT interrupt is active -#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" #define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RD_REQ // Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ @@ -774,13 +774,13 @@ // Reset value: 0x0 // 0x0 -> R_RD_REQ interrupt is inactive // 0x1 -> R_RD_REQ interrupt is active -#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_EMPTY // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY @@ -789,13 +789,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_EMPTY interrupt is inactive // 0x1 -> R_TX_EMPTY interrupt is active -#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" #define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER @@ -804,13 +804,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_OVER interrupt is inactive // 0x1 -> R_TX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" #define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_FULL // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL @@ -819,13 +819,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_FULL interrupt is inactive // 0x1 -> R_RX_FULL interrupt is active -#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER @@ -834,13 +834,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_OVER interrupt is inactive // 0x1 -> R_RX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_UNDER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER @@ -849,13 +849,13 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_INTR_MASK // Description : I2C Interrupt Mask Register. @@ -874,12 +874,12 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is masked // 0x1 -> RESTART_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_GEN_CALL @@ -889,12 +889,12 @@ // Reset value: 0x1 // 0x0 -> GEN_CALL interrupt is masked // 0x1 -> GEN_CALL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_START_DET @@ -904,12 +904,12 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is masked // 0x1 -> START_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_STOP_DET @@ -919,12 +919,12 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is masked // 0x1 -> STOP_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_ACTIVITY @@ -934,12 +934,12 @@ // Reset value: 0x0 // 0x0 -> ACTIVITY interrupt is masked // 0x1 -> ACTIVITY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_DONE @@ -949,12 +949,12 @@ // Reset value: 0x1 // 0x0 -> RX_DONE interrupt is masked // 0x1 -> RX_DONE interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_ABRT @@ -964,12 +964,12 @@ // Reset value: 0x1 // 0x0 -> TX_ABORT interrupt is masked // 0x1 -> TX_ABORT interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RD_REQ @@ -978,12 +978,12 @@ // Reset value: 0x1 // 0x0 -> RD_REQ interrupt is masked // 0x1 -> RD_REQ interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_EMPTY @@ -993,12 +993,12 @@ // Reset value: 0x1 // 0x0 -> TX_EMPTY interrupt is masked // 0x1 -> TX_EMPTY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_OVER @@ -1008,12 +1008,12 @@ // Reset value: 0x1 // 0x0 -> TX_OVER interrupt is masked // 0x1 -> TX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_FULL @@ -1023,12 +1023,12 @@ // Reset value: 0x1 // 0x0 -> RX_FULL interrupt is masked // 0x1 -> RX_FULL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_OVER @@ -1038,12 +1038,12 @@ // Reset value: 0x1 // 0x0 -> RX_OVER interrupt is masked // 0x1 -> RX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_UNDER @@ -1053,12 +1053,12 @@ // Reset value: 0x1 // 0x0 -> RX_UNDER interrupt is masked // 0x1 -> RX_UNDER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) // ============================================================================= // Register : I2C_IC_RAW_INTR_STAT @@ -1085,13 +1085,13 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is inactive // 0x1 -> RESTART_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_GEN_CALL // Description : Set only when a General Call address is received and it is @@ -1103,13 +1103,13 @@ // Reset value: 0x0 // 0x0 -> GEN_CALL interrupt is inactive // 0x1 -> GEN_CALL interrupt is active -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_START_DET // Description : Indicates whether a START or RESTART condition has occurred on @@ -1119,13 +1119,13 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is inactive // 0x1 -> START_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) -#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_STOP_DET // Description : Indicates whether a STOP condition has occurred on the I2C @@ -1148,13 +1148,13 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is inactive // 0x1 -> STOP_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_ACTIVITY // Description : This bit captures DW_apb_i2c activity and stays set until it is @@ -1168,13 +1168,13 @@ // Reset value: 0x0 // 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive // 0x1 -> RAW_INTR_ACTIVITY interrupt is active -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_DONE // Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit @@ -1185,13 +1185,13 @@ // Reset value: 0x0 // 0x0 -> RX_DONE interrupt is inactive // 0x1 -> RX_DONE interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_ABRT // Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is @@ -1211,13 +1211,13 @@ // Reset value: 0x0 // 0x0 -> TX_ABRT interrupt is inactive // 0x1 -> TX_ABRT interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RD_REQ // Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and @@ -1233,13 +1233,13 @@ // Reset value: 0x0 // 0x0 -> RD_REQ interrupt is inactive // 0x1 -> RD_REQ interrupt is active -#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY // Description : The behavior of the TX_EMPTY interrupt status differs based on @@ -1261,13 +1261,13 @@ // Reset value: 0x0. // 0x0 -> TX_EMPTY interrupt is inactive // 0x1 -> TX_EMPTY interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_OVER // Description : Set during transmit if the transmit buffer is filled to @@ -1280,13 +1280,13 @@ // Reset value: 0x0 // 0x0 -> TX_OVER interrupt is inactive // 0x1 -> TX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_FULL // Description : Set when the receive buffer reaches or goes above the RX_TL @@ -1300,13 +1300,13 @@ // Reset value: 0x0 // 0x0 -> RX_FULL interrupt is inactive // 0x1 -> RX_FULL interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_OVER // Description : Set if the receive buffer is completely filled to @@ -1324,13 +1324,13 @@ // Reset value: 0x0 // 0x0 -> RX_OVER interrupt is inactive // 0x1 -> RX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_UNDER // Description : Set if the processor attempts to read the receive buffer when @@ -1342,13 +1342,13 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_RX_TL // Description : I2C Receive FIFO Threshold Register @@ -1613,13 +1613,13 @@ // value: IC_TX_CMD_BLOCK_DEFAULT // 0x0 -> Tx Command execution not blocked // 0x1 -> Tx Command execution blocked -#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" #define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_ABORT // Description : When set, the controller initiates the transfer abort. - 0: @@ -1639,11 +1639,11 @@ // Reset value: 0x0 // 0x0 -> ABORT operation not in progress // 0x1 -> ABORT operation in progress -#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) -#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) -#define I2C_IC_ENABLE_ABORT_MSB _u(1) -#define I2C_IC_ENABLE_ABORT_LSB _u(1) -#define I2C_IC_ENABLE_ABORT_ACCESS "RW" +#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) +#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) +#define I2C_IC_ENABLE_ABORT_MSB _u(1) +#define I2C_IC_ENABLE_ABORT_LSB _u(1) +#define I2C_IC_ENABLE_ABORT_ACCESS "RW" #define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) #define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- @@ -1673,13 +1673,13 @@ // Reset value: 0x0 // 0x0 -> I2C is disabled // 0x1 -> I2C is enabled -#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) -#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) -#define I2C_IC_ENABLE_ENABLE_MSB _u(0) -#define I2C_IC_ENABLE_ENABLE_LSB _u(0) -#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" +#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) +#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) +#define I2C_IC_ENABLE_ENABLE_MSB _u(0) +#define I2C_IC_ENABLE_ENABLE_LSB _u(0) +#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" #define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_STATUS // Description : I2C Status Register @@ -1705,12 +1705,12 @@ // DW_apb_i2c is Active Reset value: 0x0 // 0x0 -> Slave is idle // 0x1 -> Slave not idle -#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) -#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) #define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_MST_ACTIVITY @@ -1724,12 +1724,12 @@ // Reset value: 0x0 // 0x0 -> Master is idle // 0x1 -> Master not idle -#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) -#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) +#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) #define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFF @@ -1740,13 +1740,13 @@ // 0x0 // 0x0 -> Rx FIFO not full // 0x1 -> Rx FIFO is full -#define I2C_IC_STATUS_RFF_RESET _u(0x0) -#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) -#define I2C_IC_STATUS_RFF_MSB _u(4) -#define I2C_IC_STATUS_RFF_LSB _u(4) -#define I2C_IC_STATUS_RFF_ACCESS "RO" +#define I2C_IC_STATUS_RFF_RESET _u(0x0) +#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) +#define I2C_IC_STATUS_RFF_MSB _u(4) +#define I2C_IC_STATUS_RFF_LSB _u(4) +#define I2C_IC_STATUS_RFF_ACCESS "RO" #define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) -#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) +#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFNE // Description : Receive FIFO Not Empty. This bit is set when the receive FIFO @@ -1755,12 +1755,12 @@ // not empty Reset value: 0x0 // 0x0 -> Rx FIFO is empty // 0x1 -> Rx FIFO not empty -#define I2C_IC_STATUS_RFNE_RESET _u(0x0) -#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) -#define I2C_IC_STATUS_RFNE_MSB _u(3) -#define I2C_IC_STATUS_RFNE_LSB _u(3) -#define I2C_IC_STATUS_RFNE_ACCESS "RO" -#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) +#define I2C_IC_STATUS_RFNE_RESET _u(0x0) +#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) +#define I2C_IC_STATUS_RFNE_MSB _u(3) +#define I2C_IC_STATUS_RFNE_LSB _u(3) +#define I2C_IC_STATUS_RFNE_ACCESS "RO" +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) #define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFE @@ -1771,13 +1771,13 @@ // Transmit FIFO is empty Reset value: 0x1 // 0x0 -> Tx FIFO not empty // 0x1 -> Tx FIFO is empty -#define I2C_IC_STATUS_TFE_RESET _u(0x1) -#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) -#define I2C_IC_STATUS_TFE_MSB _u(2) -#define I2C_IC_STATUS_TFE_LSB _u(2) -#define I2C_IC_STATUS_TFE_ACCESS "RO" +#define I2C_IC_STATUS_TFE_RESET _u(0x1) +#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) +#define I2C_IC_STATUS_TFE_MSB _u(2) +#define I2C_IC_STATUS_TFE_LSB _u(2) +#define I2C_IC_STATUS_TFE_ACCESS "RO" #define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) -#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) +#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFNF // Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one @@ -1786,25 +1786,25 @@ // value: 0x1 // 0x0 -> Tx FIFO is full // 0x1 -> Tx FIFO not full -#define I2C_IC_STATUS_TFNF_RESET _u(0x1) -#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) -#define I2C_IC_STATUS_TFNF_MSB _u(1) -#define I2C_IC_STATUS_TFNF_LSB _u(1) -#define I2C_IC_STATUS_TFNF_ACCESS "RO" -#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) +#define I2C_IC_STATUS_TFNF_RESET _u(0x1) +#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) +#define I2C_IC_STATUS_TFNF_MSB _u(1) +#define I2C_IC_STATUS_TFNF_LSB _u(1) +#define I2C_IC_STATUS_TFNF_ACCESS "RO" +#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) #define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_ACTIVITY // Description : I2C Activity Status. Reset value: 0x0 // 0x0 -> I2C is idle // 0x1 -> I2C is active -#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" #define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_TXFLR // Description : I2C Transmit FIFO Level Register This register contains the @@ -1944,12 +1944,12 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> Transfer abort detected by master- scenario not present // 0x1 -> Transfer abort detected by master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX @@ -1960,15 +1960,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave trying to transmit to remote master in read mode- -// scenario not present +// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present // 0x1 -> Slave trying to transmit to remote master in read mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST @@ -1984,15 +1983,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave lost arbitration to remote master- scenario not -// present +// 0x0 -> Slave lost arbitration to remote master- scenario not present // 0x1 -> Slave lost arbitration to remote master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO @@ -2003,16 +2001,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read -// command- scenario not present -// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read -// command -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST @@ -2023,15 +2019,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario -// not present +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present // 0x1 -> Master or Slave-Transmitter lost arbitration -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS @@ -2041,15 +2036,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User initiating master operation when MASTER disabled- -// scenario not present +// 0x0 -> User initiating master operation when MASTER disabled- scenario not present // 0x1 -> User initiating master operation when MASTER disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT @@ -2060,16 +2054,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Receiver -// 0x0 -> Master not trying to read in 10Bit addressing mode when -// RESTART disabled -// 0x1 -> Master trying to read in 10Bit addressing mode when -// RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) +// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT @@ -2088,15 +2080,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master -// 0x0 -> User trying to send START byte when RESTART disabled- -// scenario not present +// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present // 0x1 -> User trying to send START byte when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT @@ -2107,16 +2098,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User trying to switch Master to HS mode when RESTART -// disabled- scenario not present -// 0x1 -> User trying to switch Master to HS mode when RESTART -// disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) +// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present +// 0x1 -> User trying to switch Master to HS mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET @@ -2128,12 +2117,12 @@ // Role of DW_apb_i2c: Master // 0x0 -> ACK detected for START byte- scenario not present // 0x1 -> ACK detected for START byte -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET @@ -2145,12 +2134,12 @@ // Role of DW_apb_i2c: Master // 0x0 -> HS Master code ACKed in HS Mode- scenario not present // 0x1 -> HS Master code ACKed in HS Mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ @@ -2164,12 +2153,12 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL is followed by read from bus-scenario not present // 0x1 -> GCALL is followed by read from bus -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK @@ -2182,12 +2171,12 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL not ACKed by any slave-scenario not present // 0x1 -> GCALL not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK @@ -2199,15 +2188,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario -// not present +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present // 0x1 -> Transmitted data not ACKed by addressed slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK @@ -2220,13 +2208,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK // Description : This field indicates that the Master is in 10-bit address mode @@ -2238,13 +2226,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK // Description : This field indicates that the Master is in 7-bit addressing @@ -2254,15 +2242,14 @@ // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated -// 0x1 -> This abort is generated because of NOACK for 7-bit -// address -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" +// 0x1 -> This abort is generated because of NOACK for 7-bit address +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" #define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_SLV_DATA_NACK_ONLY // Description : Generate Slave Data NACK Register @@ -2296,13 +2283,13 @@ // value: 0x0 // 0x0 -> Slave receiver generates NACK normally // 0x1 -> Slave receiver generates NACK upon data reception only -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" #define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_CR // Description : DMA Control Register @@ -2319,26 +2306,26 @@ // FIFO DMA channel. Reset value: 0x0 // 0x0 -> transmit FIFO DMA channel disabled // 0x1 -> Transmit FIFO DMA channel enabled -#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) -#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) +#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" #define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_CR_RDMAE // Description : Receive DMA Enable. This bit enables/disables the receive FIFO // DMA channel. Reset value: 0x0 // 0x0 -> Receive FIFO DMA channel disabled // 0x1 -> Receive FIFO DMA channel enabled -#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) -#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) +#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" #define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_TDLR // Description : DMA Transmit Data Level Register @@ -2434,13 +2421,13 @@ // ic_data_oe). // 0x0 -> Generate NACK for a General Call // 0x1 -> Generate ACK for a General Call -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" #define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_ENABLE_STATUS // Description : I2C Enable Status Register @@ -2463,14 +2450,14 @@ #define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST -// Description : Slave Received Data Lost. This bit indicates if a -// Slave-Receiver operation has been aborted with at least one -// data byte received from an I2C transfer due to the setting bit -// 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is -// deemed to have been actively engaged in an aborted I2C transfer -// (with matching address) and the data phase of the I2C transfer -// has been entered, even though a data byte has been responded -// with a NACK. +// Description : Slave Received Data Lost. This bit indicates if a Slave- +// Receiver operation has been aborted with at least one data byte +// received from an I2C transfer due to the setting bit 0 of +// IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to +// have been actively engaged in an aborted I2C transfer (with +// matching address) and the data phase of the I2C transfer has +// been entered, even though a data byte has been responded with a +// NACK. // // Note: If the remote I2C master terminates the transfer with a // STOP condition before the DW_apb_i2c has a chance to NACK a @@ -2478,8 +2465,8 @@ // also set to 1. // // When read as 0, DW_apb_i2c is deemed to have been disabled -// without being actively involved in the data phase of a -// Slave-Receiver transfer. +// without being actively involved in the data phase of a Slave- +// Receiver transfer. // // Note: The CPU can safely read this bit when IC_EN (bit 0) is // read as 0. @@ -2487,13 +2474,13 @@ // Reset value: 0x0 // 0x0 -> Slave RX Data is not lost // 0x1 -> Slave RX Data is lost -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" #define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY // Description : Slave Disabled While Busy (Transmit, Receive). This bit @@ -2502,8 +2489,8 @@ // 1 to 0. This bit is set when the CPU writes a 0 to the // IC_ENABLE register while: // -// (a) DW_apb_i2c is receiving the address byte of the -// Slave-Transmitter operation from a remote master; +// (a) DW_apb_i2c is receiving the address byte of the Slave- +// Transmitter operation from a remote master; // // OR, // @@ -2530,13 +2517,13 @@ // Reset value: 0x0 // 0x0 -> Slave is disabled when it is idle // 0x1 -> Slave is disabled when it is active -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" #define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_IC_EN // Description : ic_en Status. This bit always reflects the value driven on the @@ -2549,13 +2536,13 @@ // Reset value: 0x0 // 0x0 -> I2C disabled // 0x1 -> I2C enabled -#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) -#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" #define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_FS_SPKLEN // Description : I2C SS, FS or FM+ spike suppression limit @@ -2687,7 +2674,6 @@ #define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION -// Description : None #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) @@ -2710,4 +2696,5 @@ #define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) #define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_I2C_DEFINED +#endif // _HARDWARE_REGS_I2C_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h b/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h index dec7e36ea..3190b413d 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/intctrl.h @@ -1,11 +1,18 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _INTCTRL_H_ -#define _INTCTRL_H_ +#ifndef _INTCTRL_H +#define _INTCTRL_H + +/** + * \file rp2040/intctrl.h + */ +#ifdef __ASSEMBLER__ #define TIMER_IRQ_0 0 #define TIMER_IRQ_1 1 #define TIMER_IRQ_2 2 @@ -32,6 +39,41 @@ #define I2C0_IRQ 23 #define I2C1_IRQ 24 #define RTC_IRQ 25 +#else +/** + * \brief Interrupt numbers on RP2040 (used as typedef \ref irq_num_t) + * \ingroup hardware_irq + */ +typedef enum irq_num_rp2040 { + TIMER_IRQ_0 = 0, ///< Select TIMER's IRQ 0 output + TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output + TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output + TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output + PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output + USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output + XIP_IRQ = 6, ///< Select XIP's IRQ output + PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output + PIO0_IRQ_1 = 8, ///< Select PIO0's IRQ 1 output + PIO1_IRQ_0 = 9, ///< Select PIO1's IRQ 0 output + PIO1_IRQ_1 = 10, ///< Select PIO1's IRQ 1 output + DMA_IRQ_0 = 11, ///< Select DMA's IRQ 0 output + DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output + IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output + IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output + SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output + SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output + CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output + SPI0_IRQ = 18, ///< Select SPI0's IRQ output + SPI1_IRQ = 19, ///< Select SPI1's IRQ output + UART0_IRQ = 20, ///< Select UART0's IRQ output + UART1_IRQ = 21, ///< Select UART1's IRQ output + ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output + I2C0_IRQ = 23, ///< Select I2C0's IRQ output + I2C1_IRQ = 24, ///< Select I2C1's IRQ output + RTC_IRQ = 25, ///< Select RTC's IRQ output + IRQ_COUNT +} irq_num_t; +#endif #define isr_timer_0 isr_irq0 #define isr_timer_1 isr_irq1 @@ -60,4 +102,5 @@ #define isr_i2c1 isr_irq24 #define isr_rtc isr_irq25 -#endif // _INTCTRL_H_ +#endif // _INTCTRL_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h index 26f139e36..c0ebaf9f9 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/io_bank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : IO_BANK0 // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_IO_BANK0_DEFINED -#define HARDWARE_REGS_IO_BANK0_DEFINED +#ifndef _HARDWARE_REGS_IO_BANK0_H +#define _HARDWARE_REGS_IO_BANK0_H // ============================================================================= // Register : IO_BANK0_GPIO0_STATUS // Description : GPIO status @@ -91,67 +92,64 @@ #define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -166,21 +164,21 @@ // 0x07 -> pio1_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO1_STATUS // Description : GPIO status @@ -261,67 +259,64 @@ #define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -336,21 +331,21 @@ // 0x07 -> pio1_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO2_STATUS // Description : GPIO status @@ -431,67 +426,64 @@ #define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -506,21 +498,21 @@ // 0x07 -> pio1_2 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO3_STATUS // Description : GPIO status @@ -601,67 +593,64 @@ #define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -676,21 +665,21 @@ // 0x07 -> pio1_3 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO4_STATUS // Description : GPIO status @@ -771,67 +760,64 @@ #define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -845,20 +831,20 @@ // 0x07 -> pio1_4 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO5_STATUS // Description : GPIO status @@ -939,67 +925,64 @@ #define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1013,20 +996,20 @@ // 0x07 -> pio1_5 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO6_STATUS // Description : GPIO status @@ -1107,67 +1090,64 @@ #define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1182,21 +1162,21 @@ // 0x08 -> usb_muxing_extphy_softcon // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO7_STATUS // Description : GPIO status @@ -1277,67 +1257,64 @@ #define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1352,21 +1329,21 @@ // 0x08 -> usb_muxing_extphy_oe_n // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO8_STATUS // Description : GPIO status @@ -1447,67 +1424,64 @@ #define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1522,21 +1496,21 @@ // 0x08 -> usb_muxing_extphy_rcv // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO9_STATUS // Description : GPIO status @@ -1617,67 +1591,64 @@ #define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1692,21 +1663,21 @@ // 0x08 -> usb_muxing_extphy_vp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO10_STATUS // Description : GPIO status @@ -1787,67 +1758,64 @@ #define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1862,21 +1830,21 @@ // 0x08 -> usb_muxing_extphy_vm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO11_STATUS // Description : GPIO status @@ -1957,67 +1925,64 @@ #define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2032,21 +1997,21 @@ // 0x08 -> usb_muxing_extphy_suspnd // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO12_STATUS // Description : GPIO status @@ -2127,67 +2092,64 @@ #define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2202,21 +2164,21 @@ // 0x08 -> usb_muxing_extphy_speed // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO13_STATUS // Description : GPIO status @@ -2297,67 +2259,64 @@ #define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2372,21 +2331,21 @@ // 0x08 -> usb_muxing_extphy_vpo // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO14_STATUS // Description : GPIO status @@ -2467,67 +2426,64 @@ #define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2542,21 +2498,21 @@ // 0x08 -> usb_muxing_extphy_vmo // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO15_STATUS // Description : GPIO status @@ -2637,67 +2593,64 @@ #define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2712,21 +2665,21 @@ // 0x08 -> usb_muxing_digital_dp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO16_STATUS // Description : GPIO status @@ -2807,67 +2760,64 @@ #define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2882,21 +2832,21 @@ // 0x08 -> usb_muxing_digital_dm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO17_STATUS // Description : GPIO status @@ -2977,67 +2927,64 @@ #define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3051,20 +2998,20 @@ // 0x07 -> pio1_17 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO18_STATUS // Description : GPIO status @@ -3145,67 +3092,64 @@ #define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3219,20 +3163,20 @@ // 0x07 -> pio1_18 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO19_STATUS // Description : GPIO status @@ -3313,67 +3257,64 @@ #define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3387,20 +3328,20 @@ // 0x07 -> pio1_19 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO20_STATUS // Description : GPIO status @@ -3481,67 +3422,64 @@ #define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3556,21 +3494,21 @@ // 0x08 -> clocks_gpin_0 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO21_STATUS // Description : GPIO status @@ -3651,67 +3589,64 @@ #define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3726,21 +3661,21 @@ // 0x08 -> clocks_gpout_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO22_STATUS // Description : GPIO status @@ -3821,67 +3756,64 @@ #define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3896,21 +3828,21 @@ // 0x08 -> clocks_gpin_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO23_STATUS // Description : GPIO status @@ -3991,67 +3923,64 @@ #define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4066,21 +3995,21 @@ // 0x08 -> clocks_gpout_1 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO24_STATUS // Description : GPIO status @@ -4161,67 +4090,64 @@ #define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4236,21 +4162,21 @@ // 0x08 -> clocks_gpout_2 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO25_STATUS // Description : GPIO status @@ -4331,67 +4257,64 @@ #define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4406,21 +4329,21 @@ // 0x08 -> clocks_gpout_3 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO26_STATUS // Description : GPIO status @@ -4501,67 +4424,64 @@ #define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4575,20 +4495,20 @@ // 0x07 -> pio1_26 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO27_STATUS // Description : GPIO status @@ -4669,67 +4589,64 @@ #define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4743,20 +4660,20 @@ // 0x07 -> pio1_27 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO28_STATUS // Description : GPIO status @@ -4837,67 +4754,64 @@ #define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4911,20 +4825,20 @@ // 0x07 -> pio1_28 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO29_STATUS // Description : GPIO status @@ -5005,67 +4919,64 @@ #define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -5079,20 +4990,20 @@ // 0x07 -> pio1_29 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_INTR0 // Description : Raw Interrupts @@ -5101,7 +5012,6 @@ #define IO_BANK0_INTR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -5109,7 +5019,6 @@ #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) @@ -5117,7 +5026,6 @@ #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -5125,7 +5033,6 @@ #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -5133,7 +5040,6 @@ #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -5141,7 +5047,6 @@ #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) @@ -5149,7 +5054,6 @@ #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -5157,7 +5061,6 @@ #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -5165,7 +5068,6 @@ #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -5173,7 +5075,6 @@ #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) @@ -5181,7 +5082,6 @@ #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -5189,7 +5089,6 @@ #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -5197,7 +5096,6 @@ #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -5205,7 +5103,6 @@ #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) @@ -5213,7 +5110,6 @@ #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -5221,7 +5117,6 @@ #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -5229,7 +5124,6 @@ #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -5237,7 +5131,6 @@ #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) @@ -5245,7 +5138,6 @@ #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -5253,7 +5145,6 @@ #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -5261,7 +5152,6 @@ #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -5269,7 +5159,6 @@ #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) @@ -5277,7 +5166,6 @@ #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -5285,7 +5173,6 @@ #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -5293,7 +5180,6 @@ #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -5301,7 +5187,6 @@ #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) @@ -5309,7 +5194,6 @@ #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -5317,7 +5201,6 @@ #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -5325,7 +5208,6 @@ #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -5333,7 +5215,6 @@ #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) @@ -5341,7 +5222,6 @@ #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -5349,7 +5229,6 @@ #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -5363,7 +5242,6 @@ #define IO_BANK0_INTR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -5371,7 +5249,6 @@ #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) @@ -5379,7 +5256,6 @@ #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -5387,7 +5263,6 @@ #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -5395,7 +5270,6 @@ #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -5403,7 +5277,6 @@ #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) @@ -5411,7 +5284,6 @@ #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -5419,7 +5291,6 @@ #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -5427,7 +5298,6 @@ #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -5435,7 +5305,6 @@ #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) @@ -5443,7 +5312,6 @@ #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -5451,7 +5319,6 @@ #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -5459,7 +5326,6 @@ #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -5467,7 +5333,6 @@ #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) @@ -5475,7 +5340,6 @@ #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -5483,7 +5347,6 @@ #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -5491,7 +5354,6 @@ #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -5499,7 +5361,6 @@ #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) @@ -5507,7 +5368,6 @@ #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -5515,7 +5375,6 @@ #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -5523,7 +5382,6 @@ #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -5531,7 +5389,6 @@ #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) @@ -5539,7 +5396,6 @@ #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -5547,7 +5403,6 @@ #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -5555,7 +5410,6 @@ #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -5563,7 +5417,6 @@ #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) @@ -5571,7 +5424,6 @@ #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -5579,7 +5431,6 @@ #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -5587,7 +5438,6 @@ #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -5595,7 +5445,6 @@ #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) @@ -5603,7 +5452,6 @@ #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -5611,7 +5459,6 @@ #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -5625,7 +5472,6 @@ #define IO_BANK0_INTR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -5633,7 +5479,6 @@ #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) @@ -5641,7 +5486,6 @@ #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -5649,7 +5493,6 @@ #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -5657,7 +5500,6 @@ #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -5665,7 +5507,6 @@ #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) @@ -5673,7 +5514,6 @@ #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -5681,7 +5521,6 @@ #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -5689,7 +5528,6 @@ #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -5697,7 +5535,6 @@ #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) @@ -5705,7 +5542,6 @@ #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -5713,7 +5549,6 @@ #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -5721,7 +5556,6 @@ #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -5729,7 +5563,6 @@ #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) @@ -5737,7 +5570,6 @@ #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -5745,7 +5577,6 @@ #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -5753,7 +5584,6 @@ #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -5761,7 +5591,6 @@ #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) @@ -5769,7 +5598,6 @@ #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -5777,7 +5605,6 @@ #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -5785,7 +5612,6 @@ #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -5793,7 +5619,6 @@ #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) @@ -5801,7 +5626,6 @@ #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -5809,7 +5633,6 @@ #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -5817,7 +5640,6 @@ #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -5825,7 +5647,6 @@ #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) @@ -5833,7 +5654,6 @@ #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -5841,7 +5661,6 @@ #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -5849,7 +5668,6 @@ #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -5857,7 +5675,6 @@ #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) @@ -5865,7 +5682,6 @@ #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -5873,7 +5689,6 @@ #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -5887,7 +5702,6 @@ #define IO_BANK0_INTR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -5895,7 +5709,6 @@ #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) @@ -5903,7 +5716,6 @@ #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -5911,7 +5723,6 @@ #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -5919,7 +5730,6 @@ #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -5927,7 +5737,6 @@ #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) @@ -5935,7 +5744,6 @@ #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -5943,7 +5751,6 @@ #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -5951,7 +5758,6 @@ #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -5959,7 +5765,6 @@ #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) @@ -5967,7 +5772,6 @@ #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -5975,7 +5779,6 @@ #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -5983,7 +5786,6 @@ #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -5991,7 +5793,6 @@ #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) @@ -5999,7 +5800,6 @@ #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -6007,7 +5807,6 @@ #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -6015,7 +5814,6 @@ #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -6023,7 +5821,6 @@ #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) @@ -6031,7 +5828,6 @@ #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -6039,7 +5835,6 @@ #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -6047,7 +5842,6 @@ #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -6055,7 +5849,6 @@ #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) @@ -6063,7 +5856,6 @@ #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -6071,7 +5863,6 @@ #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -6085,7 +5876,6 @@ #define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -6093,7 +5883,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) @@ -6101,7 +5890,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -6109,7 +5897,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -6117,7 +5904,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -6125,7 +5911,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) @@ -6133,7 +5918,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -6141,7 +5925,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -6149,7 +5932,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -6157,7 +5939,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) @@ -6165,7 +5946,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -6173,7 +5953,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -6181,7 +5960,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -6189,7 +5967,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) @@ -6197,7 +5974,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -6205,7 +5981,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -6213,7 +5988,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -6221,7 +5995,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) @@ -6229,7 +6002,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -6237,7 +6009,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -6245,7 +6016,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -6253,7 +6023,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) @@ -6261,7 +6030,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -6269,7 +6037,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -6277,7 +6044,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -6285,7 +6051,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) @@ -6293,7 +6058,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -6301,7 +6065,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -6309,7 +6072,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -6317,7 +6079,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) @@ -6325,7 +6086,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -6333,7 +6093,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -6347,7 +6106,6 @@ #define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -6355,7 +6113,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) @@ -6363,7 +6120,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -6371,7 +6127,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -6379,7 +6134,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -6387,7 +6141,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) @@ -6395,7 +6148,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -6403,7 +6155,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -6411,7 +6162,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -6419,7 +6169,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) @@ -6427,7 +6176,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -6435,7 +6183,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -6443,7 +6190,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -6451,7 +6197,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) @@ -6459,7 +6204,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -6467,7 +6211,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -6475,7 +6218,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -6483,7 +6225,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) @@ -6491,7 +6232,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -6499,7 +6239,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -6507,7 +6246,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -6515,7 +6253,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) @@ -6523,7 +6260,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -6531,7 +6267,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -6539,7 +6274,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -6547,7 +6281,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) @@ -6555,7 +6288,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -6563,7 +6295,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -6571,7 +6302,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -6579,7 +6309,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) @@ -6587,7 +6316,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -6595,7 +6323,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -6609,7 +6336,6 @@ #define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -6617,7 +6343,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) @@ -6625,7 +6350,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -6633,7 +6357,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -6641,7 +6364,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -6649,7 +6371,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) @@ -6657,7 +6378,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -6665,7 +6385,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -6673,7 +6392,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -6681,7 +6399,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) @@ -6689,7 +6406,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -6697,7 +6413,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -6705,7 +6420,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -6713,7 +6427,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) @@ -6721,7 +6434,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -6729,7 +6441,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -6737,7 +6448,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -6745,7 +6455,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) @@ -6753,7 +6462,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -6761,7 +6469,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -6769,7 +6476,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -6777,7 +6483,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) @@ -6785,7 +6490,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -6793,7 +6497,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -6801,7 +6504,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -6809,7 +6511,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) @@ -6817,7 +6518,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -6825,7 +6525,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -6833,7 +6532,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -6841,7 +6539,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) @@ -6849,7 +6546,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -6857,7 +6553,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -6871,7 +6566,6 @@ #define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -6879,7 +6573,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) @@ -6887,7 +6580,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -6895,7 +6587,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -6903,7 +6594,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -6911,7 +6601,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) @@ -6919,7 +6608,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -6927,7 +6615,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -6935,7 +6622,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -6943,7 +6629,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) @@ -6951,7 +6636,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -6959,7 +6643,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -6967,7 +6650,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -6975,7 +6657,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) @@ -6983,7 +6664,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -6991,7 +6671,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -6999,7 +6678,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -7007,7 +6685,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) @@ -7015,7 +6692,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -7023,7 +6699,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -7031,7 +6706,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -7039,7 +6713,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) @@ -7047,7 +6720,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -7055,7 +6727,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -7069,7 +6740,6 @@ #define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -7077,7 +6747,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) @@ -7085,7 +6754,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -7093,7 +6761,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -7101,7 +6768,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -7109,7 +6775,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) @@ -7117,7 +6782,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -7125,7 +6789,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -7133,7 +6796,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -7141,7 +6803,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) @@ -7149,7 +6810,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -7157,7 +6817,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -7165,7 +6824,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -7173,7 +6831,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) @@ -7181,7 +6838,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -7189,7 +6845,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -7197,7 +6852,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -7205,7 +6859,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) @@ -7213,7 +6866,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -7221,7 +6873,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -7229,7 +6880,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -7237,7 +6887,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) @@ -7245,7 +6894,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -7253,7 +6901,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -7261,7 +6908,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -7269,7 +6915,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) @@ -7277,7 +6922,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -7285,7 +6929,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -7293,7 +6936,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -7301,7 +6943,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) @@ -7309,7 +6950,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -7317,7 +6957,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -7331,7 +6970,6 @@ #define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -7339,7 +6977,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) @@ -7347,7 +6984,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -7355,7 +6991,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -7363,7 +6998,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -7371,7 +7005,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) @@ -7379,7 +7012,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -7387,7 +7019,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -7395,7 +7026,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -7403,7 +7033,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) @@ -7411,7 +7040,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -7419,7 +7047,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -7427,7 +7054,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -7435,7 +7061,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) @@ -7443,7 +7068,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -7451,7 +7075,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -7459,7 +7082,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -7467,7 +7089,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) @@ -7475,7 +7096,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -7483,7 +7103,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -7491,7 +7110,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -7499,7 +7117,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) @@ -7507,7 +7124,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -7515,7 +7131,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -7523,7 +7138,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -7531,7 +7145,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) @@ -7539,7 +7152,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -7547,7 +7159,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -7555,7 +7166,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -7563,7 +7173,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) @@ -7571,7 +7180,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -7579,7 +7187,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -7593,7 +7200,6 @@ #define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -7601,7 +7207,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) @@ -7609,7 +7214,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -7617,7 +7221,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -7625,7 +7228,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -7633,7 +7235,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) @@ -7641,7 +7242,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -7649,7 +7249,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -7657,7 +7256,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -7665,7 +7263,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) @@ -7673,7 +7270,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -7681,7 +7277,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -7689,7 +7284,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -7697,7 +7291,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) @@ -7705,7 +7298,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -7713,7 +7305,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -7721,7 +7312,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -7729,7 +7319,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) @@ -7737,7 +7326,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -7745,7 +7333,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -7753,7 +7340,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -7761,7 +7347,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) @@ -7769,7 +7354,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -7777,7 +7361,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -7785,7 +7368,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -7793,7 +7375,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) @@ -7801,7 +7382,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -7809,7 +7389,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -7817,7 +7396,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -7825,7 +7403,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) @@ -7833,7 +7410,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -7841,7 +7417,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -7855,7 +7430,6 @@ #define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -7863,7 +7437,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) @@ -7871,7 +7444,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -7879,7 +7451,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -7887,7 +7458,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -7895,7 +7465,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) @@ -7903,7 +7472,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -7911,7 +7479,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -7919,7 +7486,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -7927,7 +7493,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) @@ -7935,7 +7500,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -7943,7 +7507,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -7951,7 +7514,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -7959,7 +7521,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) @@ -7967,7 +7528,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -7975,7 +7535,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -7983,7 +7542,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -7991,7 +7549,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) @@ -7999,7 +7556,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -8007,7 +7563,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -8015,7 +7570,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -8023,7 +7577,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) @@ -8031,7 +7584,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -8039,7 +7591,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -8053,7 +7604,6 @@ #define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -8061,7 +7611,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) @@ -8069,7 +7618,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -8077,7 +7625,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -8085,7 +7632,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -8093,7 +7639,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) @@ -8101,7 +7646,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -8109,7 +7653,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -8117,7 +7660,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -8125,7 +7667,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) @@ -8133,7 +7674,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -8141,7 +7681,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -8149,7 +7688,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -8157,7 +7695,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) @@ -8165,7 +7702,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -8173,7 +7709,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -8181,7 +7716,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -8189,7 +7723,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) @@ -8197,7 +7730,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -8205,7 +7737,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -8213,7 +7744,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -8221,7 +7751,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) @@ -8229,7 +7758,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -8237,7 +7765,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -8245,7 +7772,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -8253,7 +7779,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) @@ -8261,7 +7786,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -8269,7 +7793,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -8277,7 +7800,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -8285,7 +7807,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) @@ -8293,7 +7814,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -8301,7 +7821,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -8315,7 +7834,6 @@ #define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -8323,7 +7841,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) @@ -8331,7 +7848,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -8339,7 +7855,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -8347,7 +7862,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -8355,7 +7869,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) @@ -8363,7 +7876,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -8371,7 +7883,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -8379,7 +7890,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -8387,7 +7897,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) @@ -8395,7 +7904,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -8403,7 +7911,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -8411,7 +7918,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -8419,7 +7925,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) @@ -8427,7 +7932,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -8435,7 +7939,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -8443,7 +7946,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -8451,7 +7953,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) @@ -8459,7 +7960,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -8467,7 +7967,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -8475,7 +7974,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -8483,7 +7981,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) @@ -8491,7 +7988,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -8499,7 +7995,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -8507,7 +8002,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -8515,7 +8009,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) @@ -8523,7 +8016,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -8531,7 +8023,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -8539,7 +8030,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -8547,7 +8037,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) @@ -8555,7 +8044,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -8563,7 +8051,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -8577,7 +8064,6 @@ #define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -8585,7 +8071,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) @@ -8593,7 +8078,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -8601,7 +8085,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -8609,7 +8092,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -8617,7 +8099,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) @@ -8625,7 +8106,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -8633,7 +8113,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -8641,7 +8120,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -8649,7 +8127,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) @@ -8657,7 +8134,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -8665,7 +8141,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -8673,7 +8148,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -8681,7 +8155,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) @@ -8689,7 +8162,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -8697,7 +8169,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -8705,7 +8176,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -8713,7 +8183,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) @@ -8721,7 +8190,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -8729,7 +8197,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -8737,7 +8204,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -8745,7 +8211,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) @@ -8753,7 +8218,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -8761,7 +8225,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -8769,7 +8232,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -8777,7 +8239,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) @@ -8785,7 +8246,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -8793,7 +8253,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -8801,7 +8260,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -8809,7 +8267,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) @@ -8817,7 +8274,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -8825,7 +8281,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -8839,7 +8294,6 @@ #define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -8847,7 +8301,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) @@ -8855,7 +8308,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -8863,7 +8315,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -8871,7 +8322,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -8879,7 +8329,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) @@ -8887,7 +8336,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -8895,7 +8343,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -8903,7 +8350,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -8911,7 +8357,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) @@ -8919,7 +8364,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -8927,7 +8371,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -8935,7 +8378,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -8943,7 +8385,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) @@ -8951,7 +8392,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -8959,7 +8399,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -8967,7 +8406,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -8975,7 +8413,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) @@ -8983,7 +8420,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -8991,7 +8427,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -8999,7 +8434,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -9007,7 +8441,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) @@ -9015,7 +8448,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -9023,7 +8455,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -9037,7 +8468,6 @@ #define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -9045,7 +8475,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) @@ -9053,7 +8482,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -9061,7 +8489,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -9069,7 +8496,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -9077,7 +8503,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) @@ -9085,7 +8510,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -9093,7 +8517,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -9101,7 +8524,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -9109,7 +8531,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) @@ -9117,7 +8538,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -9125,7 +8545,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -9133,7 +8552,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -9141,7 +8559,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) @@ -9149,7 +8566,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -9157,7 +8573,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -9165,7 +8580,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -9173,7 +8587,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) @@ -9181,7 +8594,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -9189,7 +8601,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -9197,7 +8608,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -9205,7 +8615,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) @@ -9213,7 +8622,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -9221,7 +8629,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -9229,7 +8636,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -9237,7 +8643,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) @@ -9245,7 +8650,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -9253,7 +8657,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -9261,7 +8664,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -9269,7 +8671,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) @@ -9277,7 +8678,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -9285,7 +8685,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -9299,7 +8698,6 @@ #define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -9307,7 +8705,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) @@ -9315,7 +8712,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -9323,7 +8719,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -9331,7 +8726,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -9339,7 +8733,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) @@ -9347,7 +8740,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -9355,7 +8747,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -9363,7 +8754,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -9371,7 +8761,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) @@ -9379,7 +8768,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -9387,7 +8775,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -9395,7 +8782,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -9403,7 +8789,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) @@ -9411,7 +8796,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -9419,7 +8803,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -9427,7 +8810,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -9435,7 +8817,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) @@ -9443,7 +8824,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -9451,7 +8831,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -9459,7 +8838,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -9467,7 +8845,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) @@ -9475,7 +8852,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -9483,7 +8859,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -9491,7 +8866,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -9499,7 +8873,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) @@ -9507,7 +8880,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -9515,7 +8887,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -9523,7 +8894,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -9531,7 +8901,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) @@ -9539,7 +8908,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -9547,7 +8915,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -9561,7 +8928,6 @@ #define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -9569,7 +8935,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) @@ -9577,7 +8942,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -9585,7 +8949,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -9593,7 +8956,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -9601,7 +8963,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) @@ -9609,7 +8970,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -9617,7 +8977,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -9625,7 +8984,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -9633,7 +8991,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) @@ -9641,7 +8998,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -9649,7 +9005,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -9657,7 +9012,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -9665,7 +9019,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) @@ -9673,7 +9026,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -9681,7 +9033,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -9689,7 +9040,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -9697,7 +9047,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) @@ -9705,7 +9054,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -9713,7 +9061,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -9721,7 +9068,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -9729,7 +9075,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) @@ -9737,7 +9082,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -9745,7 +9089,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -9753,7 +9096,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -9761,7 +9103,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) @@ -9769,7 +9110,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -9777,7 +9117,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -9785,7 +9124,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -9793,7 +9131,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) @@ -9801,7 +9138,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -9809,7 +9145,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -9823,7 +9158,6 @@ #define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -9831,7 +9165,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) @@ -9839,7 +9172,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -9847,7 +9179,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -9855,7 +9186,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -9863,7 +9193,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) @@ -9871,7 +9200,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -9879,7 +9207,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -9887,7 +9214,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -9895,7 +9221,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) @@ -9903,7 +9228,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -9911,7 +9235,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -9919,7 +9242,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -9927,7 +9249,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) @@ -9935,7 +9256,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -9943,7 +9263,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -9951,7 +9270,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -9959,7 +9277,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) @@ -9967,7 +9284,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -9975,7 +9291,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -9983,7 +9298,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -9991,7 +9305,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) @@ -9999,7 +9312,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -10007,7 +9319,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -10021,7 +9332,6 @@ #define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -10029,7 +9339,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) @@ -10037,7 +9346,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -10045,7 +9353,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -10053,7 +9360,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -10061,7 +9367,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) @@ -10069,7 +9374,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -10077,7 +9381,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -10085,7 +9388,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -10093,7 +9395,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) @@ -10101,7 +9402,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -10109,7 +9409,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -10117,7 +9416,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -10125,7 +9423,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) @@ -10133,7 +9430,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -10141,7 +9437,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -10149,7 +9444,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -10157,7 +9451,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) @@ -10165,7 +9458,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -10173,7 +9465,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -10181,7 +9472,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -10189,7 +9479,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) @@ -10197,7 +9486,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -10205,7 +9493,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -10213,7 +9500,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -10221,7 +9507,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) @@ -10229,7 +9514,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -10237,7 +9521,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -10245,7 +9528,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -10253,7 +9535,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) @@ -10261,7 +9542,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -10269,7 +9549,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -10283,7 +9562,6 @@ #define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -10291,7 +9569,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) @@ -10299,7 +9576,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -10307,7 +9583,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -10315,7 +9590,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -10323,7 +9597,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) @@ -10331,7 +9604,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -10339,7 +9611,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -10347,7 +9618,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -10355,7 +9625,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) @@ -10363,7 +9632,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -10371,7 +9639,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -10379,7 +9646,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -10387,7 +9653,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) @@ -10395,7 +9660,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -10403,7 +9667,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -10411,7 +9674,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -10419,7 +9681,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) @@ -10427,7 +9688,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -10435,7 +9695,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -10443,7 +9702,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -10451,7 +9709,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) @@ -10459,7 +9716,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -10467,7 +9723,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -10475,7 +9730,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -10483,7 +9737,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) @@ -10491,7 +9744,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -10499,7 +9751,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -10507,7 +9758,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -10515,7 +9765,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) @@ -10523,7 +9772,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -10531,7 +9779,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -10545,7 +9792,6 @@ #define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -10553,7 +9799,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) @@ -10561,7 +9806,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -10569,7 +9813,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -10577,7 +9820,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -10585,7 +9827,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) @@ -10593,7 +9834,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -10601,7 +9841,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -10609,7 +9848,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -10617,7 +9855,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) @@ -10625,7 +9862,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -10633,7 +9869,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -10641,7 +9876,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -10649,7 +9883,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) @@ -10657,7 +9890,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -10665,7 +9897,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -10673,7 +9904,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -10681,7 +9911,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) @@ -10689,7 +9918,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -10697,7 +9925,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -10705,7 +9932,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -10713,7 +9939,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) @@ -10721,7 +9946,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -10729,7 +9953,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -10737,7 +9960,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -10745,7 +9967,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) @@ -10753,7 +9974,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -10761,7 +9981,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -10769,7 +9988,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -10777,7 +9995,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) @@ -10785,7 +10002,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -10793,7 +10009,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -10807,7 +10022,6 @@ #define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -10815,7 +10029,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) @@ -10823,7 +10036,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -10831,7 +10043,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -10839,7 +10050,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -10847,7 +10057,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) @@ -10855,7 +10064,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -10863,7 +10071,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -10871,7 +10078,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -10879,7 +10085,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) @@ -10887,7 +10092,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -10895,7 +10099,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -10903,7 +10106,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -10911,7 +10113,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) @@ -10919,7 +10120,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -10927,7 +10127,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -10935,7 +10134,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -10943,7 +10141,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) @@ -10951,7 +10148,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -10959,7 +10155,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -10967,7 +10162,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -10975,7 +10169,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) @@ -10983,7 +10176,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -10991,7 +10183,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -11005,7 +10196,6 @@ #define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -11013,7 +10203,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) @@ -11021,7 +10210,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -11029,7 +10217,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -11037,7 +10224,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -11045,7 +10231,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) @@ -11053,7 +10238,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -11061,7 +10245,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -11069,7 +10252,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -11077,7 +10259,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) @@ -11085,7 +10266,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -11093,7 +10273,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -11101,7 +10280,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -11109,7 +10287,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) @@ -11117,7 +10294,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -11125,7 +10301,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -11133,7 +10308,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -11141,7 +10315,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) @@ -11149,7 +10322,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -11157,7 +10329,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -11165,7 +10336,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -11173,7 +10343,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) @@ -11181,7 +10350,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -11189,7 +10357,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -11197,7 +10364,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -11205,7 +10371,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) @@ -11213,7 +10378,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -11221,7 +10385,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -11229,7 +10392,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -11237,7 +10399,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) @@ -11245,7 +10406,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -11253,7 +10413,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -11267,7 +10426,6 @@ #define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -11275,7 +10433,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) @@ -11283,7 +10440,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -11291,7 +10447,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -11299,7 +10454,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -11307,7 +10461,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) @@ -11315,7 +10468,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -11323,7 +10475,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -11331,7 +10482,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -11339,7 +10489,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) @@ -11347,7 +10496,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -11355,7 +10503,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -11363,7 +10510,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -11371,7 +10517,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) @@ -11379,7 +10524,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -11387,7 +10531,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -11395,7 +10538,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -11403,7 +10545,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) @@ -11411,7 +10552,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -11419,7 +10559,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -11427,7 +10566,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -11435,7 +10573,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) @@ -11443,7 +10580,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -11451,7 +10587,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -11459,7 +10594,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -11467,7 +10601,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) @@ -11475,7 +10608,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -11483,7 +10615,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -11491,7 +10622,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -11499,7 +10629,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) @@ -11507,7 +10636,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -11515,7 +10643,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -11529,7 +10656,6 @@ #define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -11537,7 +10663,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) @@ -11545,7 +10670,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -11553,7 +10677,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -11561,7 +10684,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -11569,7 +10691,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) @@ -11577,7 +10698,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -11585,7 +10705,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -11593,7 +10712,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -11601,7 +10719,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) @@ -11609,7 +10726,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -11617,7 +10733,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -11625,7 +10740,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -11633,7 +10747,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) @@ -11641,7 +10754,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -11649,7 +10761,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -11657,7 +10768,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -11665,7 +10775,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) @@ -11673,7 +10782,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -11681,7 +10789,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -11689,7 +10796,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -11697,7 +10803,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) @@ -11705,7 +10810,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -11713,7 +10817,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -11721,7 +10824,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -11729,7 +10831,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) @@ -11737,7 +10838,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -11745,7 +10845,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -11753,7 +10852,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -11761,7 +10859,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) @@ -11769,7 +10866,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -11777,7 +10873,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -11791,7 +10886,6 @@ #define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -11799,7 +10893,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) @@ -11807,7 +10900,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -11815,7 +10907,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -11823,7 +10914,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -11831,7 +10921,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) @@ -11839,7 +10928,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -11847,7 +10935,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -11855,7 +10942,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -11863,7 +10949,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) @@ -11871,7 +10956,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -11879,7 +10963,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -11887,7 +10970,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -11895,7 +10977,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) @@ -11903,7 +10984,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -11911,7 +10991,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -11919,7 +10998,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -11927,7 +11005,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) @@ -11935,7 +11012,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -11943,7 +11019,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -11951,7 +11026,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -11959,7 +11033,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) @@ -11967,7 +11040,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -11975,7 +11047,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -11989,7 +11060,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -11997,7 +11067,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) @@ -12005,7 +11074,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -12013,7 +11081,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -12021,7 +11088,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -12029,7 +11095,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) @@ -12037,7 +11102,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -12045,7 +11109,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -12053,7 +11116,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -12061,7 +11123,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) @@ -12069,7 +11130,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -12077,7 +11137,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -12085,7 +11144,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -12093,7 +11151,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) @@ -12101,7 +11158,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -12109,7 +11165,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -12117,7 +11172,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -12125,7 +11179,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) @@ -12133,7 +11186,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -12141,7 +11193,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -12149,7 +11200,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -12157,7 +11207,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) @@ -12165,7 +11214,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -12173,7 +11221,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -12181,7 +11228,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -12189,7 +11235,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) @@ -12197,7 +11242,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -12205,7 +11249,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -12213,7 +11256,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -12221,7 +11263,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) @@ -12229,7 +11270,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -12237,7 +11277,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -12251,7 +11290,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -12259,7 +11297,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) @@ -12267,7 +11304,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -12275,7 +11311,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -12283,7 +11318,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -12291,7 +11325,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) @@ -12299,7 +11332,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -12307,7 +11339,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -12315,7 +11346,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -12323,7 +11353,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) @@ -12331,7 +11360,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -12339,7 +11367,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -12347,7 +11374,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -12355,7 +11381,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) @@ -12363,7 +11388,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -12371,7 +11395,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -12379,7 +11402,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -12387,7 +11409,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) @@ -12395,7 +11416,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -12403,7 +11423,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -12411,7 +11430,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -12419,7 +11437,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) @@ -12427,7 +11444,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -12435,7 +11451,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -12443,7 +11458,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -12451,7 +11465,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) @@ -12459,7 +11472,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -12467,7 +11479,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -12475,7 +11486,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -12483,7 +11493,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) @@ -12491,7 +11500,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -12499,7 +11507,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -12513,7 +11520,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -12521,7 +11527,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) @@ -12529,7 +11534,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -12537,7 +11541,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -12545,7 +11548,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -12553,7 +11555,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) @@ -12561,7 +11562,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -12569,7 +11569,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -12577,7 +11576,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -12585,7 +11583,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) @@ -12593,7 +11590,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -12601,7 +11597,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -12609,7 +11604,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -12617,7 +11611,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) @@ -12625,7 +11618,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -12633,7 +11625,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -12641,7 +11632,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -12649,7 +11639,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) @@ -12657,7 +11646,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -12665,7 +11653,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -12673,7 +11660,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -12681,7 +11667,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) @@ -12689,7 +11674,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -12697,7 +11681,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -12705,7 +11688,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -12713,7 +11695,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) @@ -12721,7 +11702,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -12729,7 +11709,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -12737,7 +11716,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -12745,7 +11723,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) @@ -12753,7 +11730,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -12761,7 +11737,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -12775,7 +11750,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -12783,7 +11757,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) @@ -12791,7 +11764,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -12799,7 +11771,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -12807,7 +11778,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -12815,7 +11785,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) @@ -12823,7 +11792,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -12831,7 +11799,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -12839,7 +11806,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -12847,7 +11813,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) @@ -12855,7 +11820,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -12863,7 +11827,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -12871,7 +11834,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -12879,7 +11841,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) @@ -12887,7 +11848,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -12895,7 +11855,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -12903,7 +11862,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -12911,7 +11869,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) @@ -12919,7 +11876,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -12927,7 +11883,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -12935,7 +11890,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -12943,7 +11897,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) @@ -12951,7 +11904,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -12959,7 +11911,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -12973,7 +11924,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -12981,7 +11931,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) @@ -12989,7 +11938,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -12997,7 +11945,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -13005,7 +11952,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -13013,7 +11959,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) @@ -13021,7 +11966,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -13029,7 +11973,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -13037,7 +11980,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -13045,7 +11987,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) @@ -13053,7 +11994,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -13061,7 +12001,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -13069,7 +12008,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -13077,7 +12015,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) @@ -13085,7 +12022,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -13093,7 +12029,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -13101,7 +12036,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -13109,7 +12043,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) @@ -13117,7 +12050,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -13125,7 +12057,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -13133,7 +12064,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -13141,7 +12071,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) @@ -13149,7 +12078,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -13157,7 +12085,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -13165,7 +12092,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -13173,7 +12099,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) @@ -13181,7 +12106,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -13189,7 +12113,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -13197,7 +12120,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -13205,7 +12127,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) @@ -13213,7 +12134,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -13221,7 +12141,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -13235,7 +12154,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -13243,7 +12161,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) @@ -13251,7 +12168,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -13259,7 +12175,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -13267,7 +12182,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -13275,7 +12189,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) @@ -13283,7 +12196,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -13291,7 +12203,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -13299,7 +12210,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -13307,7 +12217,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) @@ -13315,7 +12224,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -13323,7 +12231,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -13331,7 +12238,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -13339,7 +12245,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) @@ -13347,7 +12252,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -13355,7 +12259,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -13363,7 +12266,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -13371,7 +12273,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) @@ -13379,7 +12280,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -13387,7 +12287,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -13395,7 +12294,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -13403,7 +12301,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) @@ -13411,7 +12308,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -13419,7 +12315,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -13427,7 +12322,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -13435,7 +12329,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) @@ -13443,7 +12336,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -13451,7 +12343,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -13459,7 +12350,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -13467,7 +12357,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) @@ -13475,7 +12364,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -13483,7 +12371,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -13497,7 +12384,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -13505,7 +12391,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) @@ -13513,7 +12398,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -13521,7 +12405,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -13529,7 +12412,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -13537,7 +12419,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) @@ -13545,7 +12426,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -13553,7 +12433,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -13561,7 +12440,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -13569,7 +12447,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) @@ -13577,7 +12454,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -13585,7 +12461,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -13593,7 +12468,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -13601,7 +12475,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) @@ -13609,7 +12482,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -13617,7 +12489,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -13625,7 +12496,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -13633,7 +12503,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) @@ -13641,7 +12510,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -13649,7 +12517,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -13657,7 +12524,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -13665,7 +12531,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) @@ -13673,7 +12538,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -13681,7 +12545,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -13689,7 +12552,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -13697,7 +12559,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) @@ -13705,7 +12566,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -13713,7 +12573,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -13721,7 +12580,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -13729,7 +12587,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) @@ -13737,7 +12594,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -13745,7 +12601,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -13759,7 +12614,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -13767,7 +12621,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) @@ -13775,7 +12628,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -13783,7 +12635,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -13791,7 +12642,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -13799,7 +12649,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) @@ -13807,7 +12656,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -13815,7 +12663,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -13823,7 +12670,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -13831,7 +12677,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) @@ -13839,7 +12684,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -13847,7 +12691,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -13855,7 +12698,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -13863,7 +12705,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) @@ -13871,7 +12712,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -13879,7 +12719,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -13887,7 +12726,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -13895,7 +12733,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) @@ -13903,7 +12740,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -13911,7 +12747,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -13919,7 +12754,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -13927,7 +12761,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) @@ -13935,7 +12768,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -13943,7 +12775,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -13957,7 +12788,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -13965,7 +12795,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) @@ -13973,7 +12802,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -13981,7 +12809,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -13989,7 +12816,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -13997,7 +12823,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) @@ -14005,7 +12830,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -14013,7 +12837,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -14021,7 +12844,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -14029,7 +12851,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) @@ -14037,7 +12858,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -14045,7 +12865,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -14053,7 +12872,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -14061,7 +12879,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) @@ -14069,7 +12886,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -14077,7 +12893,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -14085,7 +12900,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -14093,7 +12907,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) @@ -14101,7 +12914,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -14109,7 +12921,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -14117,7 +12928,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -14125,7 +12935,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) @@ -14133,7 +12942,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -14141,7 +12949,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -14149,7 +12956,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -14157,7 +12963,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) @@ -14165,7 +12970,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -14173,7 +12977,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -14181,7 +12984,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -14189,7 +12991,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) @@ -14197,7 +12998,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -14205,7 +13005,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -14219,7 +13018,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -14227,7 +13025,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) @@ -14235,7 +13032,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -14243,7 +13039,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -14251,7 +13046,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -14259,7 +13053,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) @@ -14267,7 +13060,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -14275,7 +13067,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -14283,7 +13074,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -14291,7 +13081,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) @@ -14299,7 +13088,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -14307,7 +13095,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -14315,7 +13102,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -14323,7 +13109,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) @@ -14331,7 +13116,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -14339,7 +13123,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -14347,7 +13130,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -14355,7 +13137,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) @@ -14363,7 +13144,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -14371,7 +13151,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -14379,7 +13158,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -14387,7 +13165,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) @@ -14395,7 +13172,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -14403,7 +13179,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -14411,7 +13186,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -14419,7 +13193,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) @@ -14427,7 +13200,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -14435,7 +13207,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -14443,7 +13214,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -14451,7 +13221,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) @@ -14459,7 +13228,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -14467,7 +13235,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -14481,7 +13248,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -14489,7 +13255,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) @@ -14497,7 +13262,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -14505,7 +13269,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -14513,7 +13276,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -14521,7 +13283,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) @@ -14529,7 +13290,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -14537,7 +13297,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -14545,7 +13304,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -14553,7 +13311,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) @@ -14561,7 +13318,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -14569,7 +13325,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -14577,7 +13332,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -14585,7 +13339,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) @@ -14593,7 +13346,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -14601,7 +13353,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -14609,7 +13360,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -14617,7 +13367,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) @@ -14625,7 +13374,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -14633,7 +13381,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -14641,7 +13388,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -14649,7 +13395,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) @@ -14657,7 +13402,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -14665,7 +13409,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -14673,7 +13416,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -14681,7 +13423,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) @@ -14689,7 +13430,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -14697,7 +13437,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -14705,7 +13444,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -14713,7 +13451,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) @@ -14721,7 +13458,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -14729,7 +13465,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -14743,7 +13478,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -14751,7 +13485,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) @@ -14759,7 +13492,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -14767,7 +13499,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -14775,7 +13506,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -14783,7 +13513,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) @@ -14791,7 +13520,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -14799,7 +13527,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -14807,7 +13534,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -14815,7 +13541,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) @@ -14823,7 +13548,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -14831,7 +13555,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -14839,7 +13562,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -14847,7 +13569,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) @@ -14855,7 +13576,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -14863,7 +13583,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -14871,7 +13590,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -14879,7 +13597,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) @@ -14887,7 +13604,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -14895,7 +13611,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -14903,7 +13618,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -14911,7 +13625,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) @@ -14919,7 +13632,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -14927,11 +13639,11 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_IO_BANK0_DEFINED +#endif // _HARDWARE_REGS_IO_BANK0_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h index 7c381b7a5..5ed0ddbad 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/io_qspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : IO_QSPI // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_IO_QSPI_DEFINED -#define HARDWARE_REGS_IO_QSPI_DEFINED +#ifndef _HARDWARE_REGS_IO_QSPI_H +#define _HARDWARE_REGS_IO_QSPI_H // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS // Description : GPIO status @@ -91,67 +92,64 @@ #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -159,14 +157,14 @@ // 0x00 -> xip_sclk // 0x05 -> sio_30 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SS_STATUS // Description : GPIO status @@ -247,67 +245,64 @@ #define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -315,14 +310,14 @@ // 0x00 -> xip_ss_n // 0x05 -> sio_31 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD0_STATUS // Description : GPIO status @@ -403,67 +398,64 @@ #define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -471,14 +463,14 @@ // 0x00 -> xip_sd0 // 0x05 -> sio_32 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD1_STATUS // Description : GPIO status @@ -559,67 +551,64 @@ #define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -627,14 +616,14 @@ // 0x00 -> xip_sd1 // 0x05 -> sio_33 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD2_STATUS // Description : GPIO status @@ -715,67 +704,64 @@ #define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -783,14 +769,14 @@ // 0x00 -> xip_sd2 // 0x05 -> sio_34 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD3_STATUS // Description : GPIO status @@ -871,67 +857,64 @@ #define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -939,14 +922,14 @@ // 0x00 -> xip_sd3 // 0x05 -> sio_35 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_INTR // Description : Raw Interrupts @@ -955,7 +938,6 @@ #define IO_QSPI_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -963,7 +945,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -971,7 +952,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -979,7 +959,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -987,7 +966,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -995,7 +973,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1003,7 +980,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1011,7 +987,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1019,7 +994,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1027,7 +1001,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1035,7 +1008,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1043,7 +1015,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1051,7 +1022,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1059,7 +1029,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1067,7 +1036,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1075,7 +1043,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1083,7 +1050,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1091,7 +1057,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1099,7 +1064,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1107,7 +1071,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1115,7 +1078,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1123,7 +1085,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1131,7 +1092,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1139,7 +1099,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1153,7 +1112,6 @@ #define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1161,7 +1119,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1169,7 +1126,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1177,7 +1133,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1185,7 +1140,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1193,7 +1147,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1201,7 +1154,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1209,7 +1161,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1217,7 +1168,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1225,7 +1175,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1233,7 +1182,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1241,7 +1189,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1249,7 +1196,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1257,7 +1203,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1265,7 +1210,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1273,7 +1217,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1281,7 +1224,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1289,7 +1231,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1297,7 +1238,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1305,7 +1245,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1313,7 +1252,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1321,7 +1259,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1329,7 +1266,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1337,7 +1273,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1351,7 +1286,6 @@ #define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1359,7 +1293,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1367,7 +1300,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1375,7 +1307,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1383,7 +1314,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1391,7 +1321,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1399,7 +1328,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1407,7 +1335,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1415,7 +1342,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1423,7 +1349,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1431,7 +1356,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1439,7 +1363,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1447,7 +1370,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1455,7 +1377,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1463,7 +1384,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1471,7 +1391,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1479,7 +1398,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1487,7 +1405,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1495,7 +1412,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1503,7 +1419,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1511,7 +1426,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1519,7 +1433,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1527,7 +1440,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1535,7 +1447,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1549,7 +1460,6 @@ #define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1557,7 +1467,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1565,7 +1474,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1573,7 +1481,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1581,7 +1488,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1589,7 +1495,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1597,7 +1502,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1605,7 +1509,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1613,7 +1516,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1621,7 +1523,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1629,7 +1530,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1637,7 +1537,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1645,7 +1544,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1653,7 +1551,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1661,7 +1558,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1669,7 +1565,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1677,7 +1572,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1685,7 +1579,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1693,7 +1586,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1701,7 +1593,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1709,7 +1600,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1717,7 +1607,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1725,7 +1614,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1733,7 +1621,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1747,7 +1634,6 @@ #define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1755,7 +1641,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1763,7 +1648,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1771,7 +1655,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1779,7 +1662,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1787,7 +1669,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1795,7 +1676,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1803,7 +1683,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1811,7 +1690,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1819,7 +1697,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1827,7 +1704,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1835,7 +1711,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1843,7 +1718,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1851,7 +1725,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1859,7 +1732,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1867,7 +1739,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1875,7 +1746,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1883,7 +1753,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1891,7 +1760,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1899,7 +1767,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1907,7 +1774,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1915,7 +1781,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1923,7 +1788,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1931,7 +1795,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1945,7 +1808,6 @@ #define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1953,7 +1815,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1961,7 +1822,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1969,7 +1829,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1977,7 +1836,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1985,7 +1843,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1993,7 +1850,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2001,7 +1857,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2009,7 +1864,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2017,7 +1871,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2025,7 +1878,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2033,7 +1885,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2041,7 +1892,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2049,7 +1899,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2057,7 +1906,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2065,7 +1913,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2073,7 +1920,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2081,7 +1927,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2089,7 +1934,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2097,7 +1941,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2105,7 +1948,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2113,7 +1955,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2121,7 +1962,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2129,7 +1969,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2143,7 +1982,6 @@ #define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2151,7 +1989,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2159,7 +1996,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2167,7 +2003,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2175,7 +2010,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2183,7 +2017,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2191,7 +2024,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2199,7 +2031,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2207,7 +2038,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2215,7 +2045,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2223,7 +2052,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2231,7 +2059,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2239,7 +2066,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2247,7 +2073,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2255,7 +2080,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2263,7 +2087,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2271,7 +2094,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2279,7 +2101,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2287,7 +2108,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2295,7 +2115,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2303,7 +2122,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2311,7 +2129,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2319,7 +2136,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2327,7 +2143,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2341,7 +2156,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2349,7 +2163,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2357,7 +2170,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2365,7 +2177,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2373,7 +2184,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2381,7 +2191,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2389,7 +2198,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2397,7 +2205,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2405,7 +2212,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2413,7 +2219,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2421,7 +2226,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2429,7 +2233,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2437,7 +2240,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2445,7 +2247,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2453,7 +2254,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2461,7 +2261,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2469,7 +2268,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2477,7 +2275,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2485,7 +2282,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2493,7 +2289,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2501,7 +2296,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2509,7 +2303,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2517,7 +2310,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2525,7 +2317,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2539,7 +2330,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2547,7 +2337,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2555,7 +2344,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2563,7 +2351,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2571,7 +2358,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2579,7 +2365,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2587,7 +2372,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2595,7 +2379,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2603,7 +2386,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2611,7 +2393,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2619,7 +2400,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2627,7 +2407,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2635,7 +2414,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2643,7 +2421,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2651,7 +2428,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2659,7 +2435,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2667,7 +2442,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2675,7 +2449,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2683,7 +2456,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2691,7 +2463,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2699,7 +2470,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2707,7 +2477,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2715,7 +2484,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2723,7 +2491,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2737,7 +2504,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2745,7 +2511,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2753,7 +2518,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2761,7 +2525,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2769,7 +2532,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2777,7 +2539,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2785,7 +2546,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2793,7 +2553,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2801,7 +2560,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2809,7 +2567,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2817,7 +2574,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2825,7 +2581,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2833,7 +2588,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2841,7 +2595,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2849,7 +2602,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2857,7 +2609,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2865,7 +2616,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2873,7 +2623,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2881,7 +2630,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2889,7 +2637,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2897,7 +2644,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2905,7 +2651,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2913,7 +2658,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2921,11 +2665,11 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_IO_QSPI_DEFINED +#endif // _HARDWARE_REGS_IO_QSPI_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h b/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h index cef5ab0a1..028e5ad85 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/m0plus.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : M0PLUS // Version : 1 // Bus type : ahbl -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_M0PLUS_DEFINED -#define HARDWARE_REGS_M0PLUS_DEFINED +#ifndef _HARDWARE_REGS_M0PLUS_H +#define _HARDWARE_REGS_M0PLUS_H // ============================================================================= // Register : M0PLUS_SYST_CSR // Description : Use the SysTick Control and Status Register to enable the @@ -610,11 +611,11 @@ #define M0PLUS_CPUID_REVISION_ACCESS "RO" // ============================================================================= // Register : M0PLUS_ICSR -// Description : Use the Interrupt Control State Register to set a pending -// Non-Maskable Interrupt (NMI), set or clear a pending PendSV, -// set or clear a pending SysTick, check for pending exceptions, -// check the vector number of the highest priority pended -// exception, check the vector number of the active exception. +// Description : Use the Interrupt Control State Register to set a pending Non- +// Maskable Interrupt (NMI), set or clear a pending PendSV, set or +// clear a pending SysTick, check for pending exceptions, check +// the vector number of the highest priority pended exception, +// check the vector number of the active exception. #define M0PLUS_ICSR_OFFSET _u(0x0000ed04) #define M0PLUS_ICSR_BITS _u(0x9edff1ff) #define M0PLUS_ICSR_RESET _u(0x00000000) @@ -1146,4 +1147,5 @@ #define M0PLUS_MPU_RASR_ENABLE_LSB _u(0) #define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_M0PLUS_DEFINED +#endif // _HARDWARE_REGS_M0PLUS_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h b/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h index 06102ac97..04c5e3971 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/pads_bank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,21 +9,20 @@ // Register block : PADS_BANK0 // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PADS_BANK0_DEFINED -#define HARDWARE_REGS_PADS_BANK0_DEFINED +#ifndef _HARDWARE_REGS_PADS_BANK0_H +#define _HARDWARE_REGS_PADS_BANK0_H // ============================================================================= // Register : PADS_BANK0_VOLTAGE_SELECT // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" #define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) #define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= @@ -54,14 +55,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_PUE @@ -125,14 +126,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_PUE @@ -196,14 +197,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_PUE @@ -267,14 +268,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_PUE @@ -338,14 +339,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_PUE @@ -409,14 +410,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_PUE @@ -480,14 +481,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_PUE @@ -551,14 +552,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_PUE @@ -622,14 +623,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_PUE @@ -693,14 +694,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_PUE @@ -764,14 +765,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_PUE @@ -835,14 +836,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_PUE @@ -906,14 +907,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_PUE @@ -977,14 +978,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_PUE @@ -1048,14 +1049,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_PUE @@ -1119,14 +1120,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_PUE @@ -1190,14 +1191,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_PUE @@ -1261,14 +1262,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_PUE @@ -1332,14 +1333,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_PUE @@ -1403,14 +1404,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_PUE @@ -1474,14 +1475,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_PUE @@ -1545,14 +1546,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_PUE @@ -1616,14 +1617,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_PUE @@ -1687,14 +1688,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_PUE @@ -1758,14 +1759,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_PUE @@ -1829,14 +1830,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_PUE @@ -1900,14 +1901,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_PUE @@ -1971,14 +1972,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_PUE @@ -2042,14 +2043,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_PUE @@ -2113,14 +2114,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_PUE @@ -2184,14 +2185,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) -#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) -#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) +#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) +#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_PUE @@ -2255,14 +2256,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWD_DRIVE_MSB _u(5) -#define PADS_BANK0_SWD_DRIVE_LSB _u(4) -#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWD_DRIVE_MSB _u(5) +#define PADS_BANK0_SWD_DRIVE_LSB _u(4) +#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_PUE @@ -2297,4 +2298,5 @@ #define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) #define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_PADS_BANK0_DEFINED +#endif // _HARDWARE_REGS_PADS_BANK0_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h b/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h index b3a09e900..4cd27ea7c 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/pads_qspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,21 +9,20 @@ // Register block : PADS_QSPI // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED -#define HARDWARE_REGS_PADS_QSPI_DEFINED +#ifndef _HARDWARE_REGS_PADS_QSPI_H +#define _HARDWARE_REGS_PADS_QSPI_H // ============================================================================= // Register : PADS_QSPI_VOLTAGE_SELECT // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" #define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) #define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= @@ -54,14 +55,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE @@ -125,14 +126,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_PUE @@ -196,14 +197,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_PUE @@ -267,14 +268,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_PUE @@ -338,14 +339,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_PUE @@ -409,14 +410,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_PUE @@ -451,4 +452,5 @@ #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_PADS_QSPI_DEFINED +#endif // _HARDWARE_REGS_PADS_QSPI_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pio.h b/src/rp2040/hardware_regs/include/hardware/regs/pio.h index 43a65d72d..d10de90f2 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/pio.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/pio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahbl // Description : Programmable IO block // ============================================================================= -#ifndef HARDWARE_REGS_PIO_DEFINED -#define HARDWARE_REGS_PIO_DEFINED +#ifndef _HARDWARE_REGS_PIO_H +#define _HARDWARE_REGS_PIO_H // ============================================================================= // Register : PIO_CTRL // Description : PIO control register @@ -169,7 +171,6 @@ #define PIO_FLEVEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX3 -// Description : None #define PIO_FLEVEL_RX3_RESET _u(0x0) #define PIO_FLEVEL_RX3_BITS _u(0xf0000000) #define PIO_FLEVEL_RX3_MSB _u(31) @@ -177,7 +178,6 @@ #define PIO_FLEVEL_RX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX3 -// Description : None #define PIO_FLEVEL_TX3_RESET _u(0x0) #define PIO_FLEVEL_TX3_BITS _u(0x0f000000) #define PIO_FLEVEL_TX3_MSB _u(27) @@ -185,7 +185,6 @@ #define PIO_FLEVEL_TX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX2 -// Description : None #define PIO_FLEVEL_RX2_RESET _u(0x0) #define PIO_FLEVEL_RX2_BITS _u(0x00f00000) #define PIO_FLEVEL_RX2_MSB _u(23) @@ -193,7 +192,6 @@ #define PIO_FLEVEL_RX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX2 -// Description : None #define PIO_FLEVEL_TX2_RESET _u(0x0) #define PIO_FLEVEL_TX2_BITS _u(0x000f0000) #define PIO_FLEVEL_TX2_MSB _u(19) @@ -201,7 +199,6 @@ #define PIO_FLEVEL_TX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX1 -// Description : None #define PIO_FLEVEL_RX1_RESET _u(0x0) #define PIO_FLEVEL_RX1_BITS _u(0x0000f000) #define PIO_FLEVEL_RX1_MSB _u(15) @@ -209,7 +206,6 @@ #define PIO_FLEVEL_RX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX1 -// Description : None #define PIO_FLEVEL_TX1_RESET _u(0x0) #define PIO_FLEVEL_TX1_BITS _u(0x00000f00) #define PIO_FLEVEL_TX1_MSB _u(11) @@ -217,7 +213,6 @@ #define PIO_FLEVEL_TX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX0 -// Description : None #define PIO_FLEVEL_RX0_RESET _u(0x0) #define PIO_FLEVEL_RX0_BITS _u(0x000000f0) #define PIO_FLEVEL_RX0_MSB _u(7) @@ -225,7 +220,6 @@ #define PIO_FLEVEL_RX0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX0 -// Description : None #define PIO_FLEVEL_TX0_RESET _u(0x0) #define PIO_FLEVEL_TX0_BITS _u(0x0000000f) #define PIO_FLEVEL_TX0_MSB _u(3) @@ -851,11 +845,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -1026,10 +1020,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -1182,11 +1176,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -1357,10 +1351,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -1513,11 +1507,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -1688,10 +1682,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -1844,11 +1838,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -2019,10 +2013,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -2057,7 +2051,6 @@ #define PIO_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3 -// Description : None #define PIO_INTR_SM3_RESET _u(0x0) #define PIO_INTR_SM3_BITS _u(0x00000800) #define PIO_INTR_SM3_MSB _u(11) @@ -2065,7 +2058,6 @@ #define PIO_INTR_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2 -// Description : None #define PIO_INTR_SM2_RESET _u(0x0) #define PIO_INTR_SM2_BITS _u(0x00000400) #define PIO_INTR_SM2_MSB _u(10) @@ -2073,7 +2065,6 @@ #define PIO_INTR_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1 -// Description : None #define PIO_INTR_SM1_RESET _u(0x0) #define PIO_INTR_SM1_BITS _u(0x00000200) #define PIO_INTR_SM1_MSB _u(9) @@ -2081,7 +2072,6 @@ #define PIO_INTR_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0 -// Description : None #define PIO_INTR_SM0_RESET _u(0x0) #define PIO_INTR_SM0_BITS _u(0x00000100) #define PIO_INTR_SM0_MSB _u(8) @@ -2089,7 +2079,6 @@ #define PIO_INTR_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_TXNFULL -// Description : None #define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_INTR_SM3_TXNFULL_MSB _u(7) @@ -2097,7 +2086,6 @@ #define PIO_INTR_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_TXNFULL -// Description : None #define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_INTR_SM2_TXNFULL_MSB _u(6) @@ -2105,7 +2093,6 @@ #define PIO_INTR_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_TXNFULL -// Description : None #define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_INTR_SM1_TXNFULL_MSB _u(5) @@ -2113,7 +2100,6 @@ #define PIO_INTR_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_TXNFULL -// Description : None #define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_INTR_SM0_TXNFULL_MSB _u(4) @@ -2121,7 +2107,6 @@ #define PIO_INTR_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_RXNEMPTY -// Description : None #define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) @@ -2129,7 +2114,6 @@ #define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_RXNEMPTY -// Description : None #define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) @@ -2137,7 +2121,6 @@ #define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_RXNEMPTY -// Description : None #define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) @@ -2145,7 +2128,6 @@ #define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_RXNEMPTY -// Description : None #define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) @@ -2159,7 +2141,6 @@ #define PIO_IRQ0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3 -// Description : None #define PIO_IRQ0_INTE_SM3_RESET _u(0x0) #define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) #define PIO_IRQ0_INTE_SM3_MSB _u(11) @@ -2167,7 +2148,6 @@ #define PIO_IRQ0_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2 -// Description : None #define PIO_IRQ0_INTE_SM2_RESET _u(0x0) #define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) #define PIO_IRQ0_INTE_SM2_MSB _u(10) @@ -2175,7 +2155,6 @@ #define PIO_IRQ0_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1 -// Description : None #define PIO_IRQ0_INTE_SM1_RESET _u(0x0) #define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) #define PIO_IRQ0_INTE_SM1_MSB _u(9) @@ -2183,7 +2162,6 @@ #define PIO_IRQ0_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0 -// Description : None #define PIO_IRQ0_INTE_SM0_RESET _u(0x0) #define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) #define PIO_IRQ0_INTE_SM0_MSB _u(8) @@ -2191,7 +2169,6 @@ #define PIO_IRQ0_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) @@ -2199,7 +2176,6 @@ #define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) @@ -2207,7 +2183,6 @@ #define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) @@ -2215,7 +2190,6 @@ #define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) @@ -2223,7 +2197,6 @@ #define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) @@ -2231,7 +2204,6 @@ #define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) @@ -2239,7 +2211,6 @@ #define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) @@ -2247,7 +2218,6 @@ #define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) @@ -2261,7 +2231,6 @@ #define PIO_IRQ0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3 -// Description : None #define PIO_IRQ0_INTF_SM3_RESET _u(0x0) #define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) #define PIO_IRQ0_INTF_SM3_MSB _u(11) @@ -2269,7 +2238,6 @@ #define PIO_IRQ0_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2 -// Description : None #define PIO_IRQ0_INTF_SM2_RESET _u(0x0) #define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) #define PIO_IRQ0_INTF_SM2_MSB _u(10) @@ -2277,7 +2245,6 @@ #define PIO_IRQ0_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1 -// Description : None #define PIO_IRQ0_INTF_SM1_RESET _u(0x0) #define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) #define PIO_IRQ0_INTF_SM1_MSB _u(9) @@ -2285,7 +2252,6 @@ #define PIO_IRQ0_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0 -// Description : None #define PIO_IRQ0_INTF_SM0_RESET _u(0x0) #define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) #define PIO_IRQ0_INTF_SM0_MSB _u(8) @@ -2293,7 +2259,6 @@ #define PIO_IRQ0_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) @@ -2301,7 +2266,6 @@ #define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) @@ -2309,7 +2273,6 @@ #define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) @@ -2317,7 +2280,6 @@ #define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) @@ -2325,7 +2287,6 @@ #define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) @@ -2333,7 +2294,6 @@ #define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) @@ -2341,7 +2301,6 @@ #define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) @@ -2349,7 +2308,6 @@ #define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) @@ -2363,7 +2321,6 @@ #define PIO_IRQ0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3 -// Description : None #define PIO_IRQ0_INTS_SM3_RESET _u(0x0) #define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) #define PIO_IRQ0_INTS_SM3_MSB _u(11) @@ -2371,7 +2328,6 @@ #define PIO_IRQ0_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2 -// Description : None #define PIO_IRQ0_INTS_SM2_RESET _u(0x0) #define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) #define PIO_IRQ0_INTS_SM2_MSB _u(10) @@ -2379,7 +2335,6 @@ #define PIO_IRQ0_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1 -// Description : None #define PIO_IRQ0_INTS_SM1_RESET _u(0x0) #define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) #define PIO_IRQ0_INTS_SM1_MSB _u(9) @@ -2387,7 +2342,6 @@ #define PIO_IRQ0_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0 -// Description : None #define PIO_IRQ0_INTS_SM0_RESET _u(0x0) #define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) #define PIO_IRQ0_INTS_SM0_MSB _u(8) @@ -2395,7 +2349,6 @@ #define PIO_IRQ0_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) @@ -2403,7 +2356,6 @@ #define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) @@ -2411,7 +2363,6 @@ #define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) @@ -2419,7 +2370,6 @@ #define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) @@ -2427,7 +2377,6 @@ #define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) @@ -2435,7 +2384,6 @@ #define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) @@ -2443,7 +2391,6 @@ #define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) @@ -2451,7 +2398,6 @@ #define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) @@ -2465,7 +2411,6 @@ #define PIO_IRQ1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3 -// Description : None #define PIO_IRQ1_INTE_SM3_RESET _u(0x0) #define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) #define PIO_IRQ1_INTE_SM3_MSB _u(11) @@ -2473,7 +2418,6 @@ #define PIO_IRQ1_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2 -// Description : None #define PIO_IRQ1_INTE_SM2_RESET _u(0x0) #define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) #define PIO_IRQ1_INTE_SM2_MSB _u(10) @@ -2481,7 +2425,6 @@ #define PIO_IRQ1_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1 -// Description : None #define PIO_IRQ1_INTE_SM1_RESET _u(0x0) #define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) #define PIO_IRQ1_INTE_SM1_MSB _u(9) @@ -2489,7 +2432,6 @@ #define PIO_IRQ1_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0 -// Description : None #define PIO_IRQ1_INTE_SM0_RESET _u(0x0) #define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) #define PIO_IRQ1_INTE_SM0_MSB _u(8) @@ -2497,7 +2439,6 @@ #define PIO_IRQ1_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) @@ -2505,7 +2446,6 @@ #define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) @@ -2513,7 +2453,6 @@ #define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) @@ -2521,7 +2460,6 @@ #define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) @@ -2529,7 +2467,6 @@ #define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) @@ -2537,7 +2474,6 @@ #define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) @@ -2545,7 +2481,6 @@ #define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) @@ -2553,7 +2488,6 @@ #define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) @@ -2567,7 +2501,6 @@ #define PIO_IRQ1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3 -// Description : None #define PIO_IRQ1_INTF_SM3_RESET _u(0x0) #define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) #define PIO_IRQ1_INTF_SM3_MSB _u(11) @@ -2575,7 +2508,6 @@ #define PIO_IRQ1_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2 -// Description : None #define PIO_IRQ1_INTF_SM2_RESET _u(0x0) #define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) #define PIO_IRQ1_INTF_SM2_MSB _u(10) @@ -2583,7 +2515,6 @@ #define PIO_IRQ1_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1 -// Description : None #define PIO_IRQ1_INTF_SM1_RESET _u(0x0) #define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) #define PIO_IRQ1_INTF_SM1_MSB _u(9) @@ -2591,7 +2522,6 @@ #define PIO_IRQ1_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0 -// Description : None #define PIO_IRQ1_INTF_SM0_RESET _u(0x0) #define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) #define PIO_IRQ1_INTF_SM0_MSB _u(8) @@ -2599,7 +2529,6 @@ #define PIO_IRQ1_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) @@ -2607,7 +2536,6 @@ #define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) @@ -2615,7 +2543,6 @@ #define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) @@ -2623,7 +2550,6 @@ #define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) @@ -2631,7 +2557,6 @@ #define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) @@ -2639,7 +2564,6 @@ #define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) @@ -2647,7 +2571,6 @@ #define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) @@ -2655,7 +2578,6 @@ #define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) @@ -2669,7 +2591,6 @@ #define PIO_IRQ1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3 -// Description : None #define PIO_IRQ1_INTS_SM3_RESET _u(0x0) #define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) #define PIO_IRQ1_INTS_SM3_MSB _u(11) @@ -2677,7 +2598,6 @@ #define PIO_IRQ1_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2 -// Description : None #define PIO_IRQ1_INTS_SM2_RESET _u(0x0) #define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) #define PIO_IRQ1_INTS_SM2_MSB _u(10) @@ -2685,7 +2605,6 @@ #define PIO_IRQ1_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1 -// Description : None #define PIO_IRQ1_INTS_SM1_RESET _u(0x0) #define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) #define PIO_IRQ1_INTS_SM1_MSB _u(9) @@ -2693,7 +2612,6 @@ #define PIO_IRQ1_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0 -// Description : None #define PIO_IRQ1_INTS_SM0_RESET _u(0x0) #define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) #define PIO_IRQ1_INTS_SM0_MSB _u(8) @@ -2701,7 +2619,6 @@ #define PIO_IRQ1_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) @@ -2709,7 +2626,6 @@ #define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) @@ -2717,7 +2633,6 @@ #define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) @@ -2725,7 +2640,6 @@ #define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) @@ -2733,7 +2647,6 @@ #define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) @@ -2741,7 +2654,6 @@ #define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) @@ -2749,7 +2661,6 @@ #define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) @@ -2757,11 +2668,11 @@ #define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_PIO_DEFINED +#endif // _HARDWARE_REGS_PIO_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pll.h b/src/rp2040/hardware_regs/include/hardware/regs/pll.h index 9dba689ab..345982e85 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/pll.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/pll.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : PLL // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PLL_DEFINED -#define HARDWARE_REGS_PLL_DEFINED +#ifndef _HARDWARE_REGS_PLL_H +#define _HARDWARE_REGS_PLL_H // ============================================================================= // Register : PLL_CS // Description : Control and Status @@ -132,4 +133,5 @@ #define PLL_PRIM_POSTDIV2_LSB _u(12) #define PLL_PRIM_POSTDIV2_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_PLL_DEFINED +#endif // _HARDWARE_REGS_PLL_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/psm.h b/src/rp2040/hardware_regs/include/hardware/regs/psm.h index 8810ae8bb..3433f6dc4 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/psm.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/psm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : PSM // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PSM_DEFINED -#define HARDWARE_REGS_PSM_DEFINED +#ifndef _HARDWARE_REGS_PSM_H +#define _HARDWARE_REGS_PSM_H // ============================================================================= // Register : PSM_FRCE_ON // Description : Force block out of reset (i.e. power it on) @@ -19,7 +20,6 @@ #define PSM_FRCE_ON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC1 -// Description : None #define PSM_FRCE_ON_PROC1_RESET _u(0x0) #define PSM_FRCE_ON_PROC1_BITS _u(0x00010000) #define PSM_FRCE_ON_PROC1_MSB _u(16) @@ -27,7 +27,6 @@ #define PSM_FRCE_ON_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC0 -// Description : None #define PSM_FRCE_ON_PROC0_RESET _u(0x0) #define PSM_FRCE_ON_PROC0_BITS _u(0x00008000) #define PSM_FRCE_ON_PROC0_MSB _u(15) @@ -35,7 +34,6 @@ #define PSM_FRCE_ON_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SIO -// Description : None #define PSM_FRCE_ON_SIO_RESET _u(0x0) #define PSM_FRCE_ON_SIO_BITS _u(0x00004000) #define PSM_FRCE_ON_SIO_MSB _u(14) @@ -43,7 +41,6 @@ #define PSM_FRCE_ON_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET -// Description : None #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13) @@ -51,7 +48,6 @@ #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XIP -// Description : None #define PSM_FRCE_ON_XIP_RESET _u(0x0) #define PSM_FRCE_ON_XIP_BITS _u(0x00001000) #define PSM_FRCE_ON_XIP_MSB _u(12) @@ -59,7 +55,6 @@ #define PSM_FRCE_ON_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM5 -// Description : None #define PSM_FRCE_ON_SRAM5_RESET _u(0x0) #define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800) #define PSM_FRCE_ON_SRAM5_MSB _u(11) @@ -67,7 +62,6 @@ #define PSM_FRCE_ON_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM4 -// Description : None #define PSM_FRCE_ON_SRAM4_RESET _u(0x0) #define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400) #define PSM_FRCE_ON_SRAM4_MSB _u(10) @@ -75,7 +69,6 @@ #define PSM_FRCE_ON_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM3 -// Description : None #define PSM_FRCE_ON_SRAM3_RESET _u(0x0) #define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200) #define PSM_FRCE_ON_SRAM3_MSB _u(9) @@ -83,7 +76,6 @@ #define PSM_FRCE_ON_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM2 -// Description : None #define PSM_FRCE_ON_SRAM2_RESET _u(0x0) #define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100) #define PSM_FRCE_ON_SRAM2_MSB _u(8) @@ -91,7 +83,6 @@ #define PSM_FRCE_ON_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM1 -// Description : None #define PSM_FRCE_ON_SRAM1_RESET _u(0x0) #define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080) #define PSM_FRCE_ON_SRAM1_MSB _u(7) @@ -99,7 +90,6 @@ #define PSM_FRCE_ON_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM0 -// Description : None #define PSM_FRCE_ON_SRAM0_RESET _u(0x0) #define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040) #define PSM_FRCE_ON_SRAM0_MSB _u(6) @@ -107,7 +97,6 @@ #define PSM_FRCE_ON_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROM -// Description : None #define PSM_FRCE_ON_ROM_RESET _u(0x0) #define PSM_FRCE_ON_ROM_BITS _u(0x00000020) #define PSM_FRCE_ON_ROM_MSB _u(5) @@ -115,7 +104,6 @@ #define PSM_FRCE_ON_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_BUSFABRIC -// Description : None #define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) #define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010) #define PSM_FRCE_ON_BUSFABRIC_MSB _u(4) @@ -123,7 +111,6 @@ #define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_RESETS -// Description : None #define PSM_FRCE_ON_RESETS_RESET _u(0x0) #define PSM_FRCE_ON_RESETS_BITS _u(0x00000008) #define PSM_FRCE_ON_RESETS_MSB _u(3) @@ -131,7 +118,6 @@ #define PSM_FRCE_ON_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_CLOCKS -// Description : None #define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) #define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004) #define PSM_FRCE_ON_CLOCKS_MSB _u(2) @@ -139,7 +125,6 @@ #define PSM_FRCE_ON_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XOSC -// Description : None #define PSM_FRCE_ON_XOSC_RESET _u(0x0) #define PSM_FRCE_ON_XOSC_BITS _u(0x00000002) #define PSM_FRCE_ON_XOSC_MSB _u(1) @@ -147,7 +132,6 @@ #define PSM_FRCE_ON_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROSC -// Description : None #define PSM_FRCE_ON_ROSC_RESET _u(0x0) #define PSM_FRCE_ON_ROSC_BITS _u(0x00000001) #define PSM_FRCE_ON_ROSC_MSB _u(0) @@ -161,7 +145,6 @@ #define PSM_FRCE_OFF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC1 -// Description : None #define PSM_FRCE_OFF_PROC1_RESET _u(0x0) #define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000) #define PSM_FRCE_OFF_PROC1_MSB _u(16) @@ -169,7 +152,6 @@ #define PSM_FRCE_OFF_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC0 -// Description : None #define PSM_FRCE_OFF_PROC0_RESET _u(0x0) #define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000) #define PSM_FRCE_OFF_PROC0_MSB _u(15) @@ -177,7 +159,6 @@ #define PSM_FRCE_OFF_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SIO -// Description : None #define PSM_FRCE_OFF_SIO_RESET _u(0x0) #define PSM_FRCE_OFF_SIO_BITS _u(0x00004000) #define PSM_FRCE_OFF_SIO_MSB _u(14) @@ -185,7 +166,6 @@ #define PSM_FRCE_OFF_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET -// Description : None #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13) @@ -193,7 +173,6 @@ #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XIP -// Description : None #define PSM_FRCE_OFF_XIP_RESET _u(0x0) #define PSM_FRCE_OFF_XIP_BITS _u(0x00001000) #define PSM_FRCE_OFF_XIP_MSB _u(12) @@ -201,7 +180,6 @@ #define PSM_FRCE_OFF_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM5 -// Description : None #define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800) #define PSM_FRCE_OFF_SRAM5_MSB _u(11) @@ -209,7 +187,6 @@ #define PSM_FRCE_OFF_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM4 -// Description : None #define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400) #define PSM_FRCE_OFF_SRAM4_MSB _u(10) @@ -217,7 +194,6 @@ #define PSM_FRCE_OFF_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM3 -// Description : None #define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200) #define PSM_FRCE_OFF_SRAM3_MSB _u(9) @@ -225,7 +201,6 @@ #define PSM_FRCE_OFF_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM2 -// Description : None #define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100) #define PSM_FRCE_OFF_SRAM2_MSB _u(8) @@ -233,7 +208,6 @@ #define PSM_FRCE_OFF_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM1 -// Description : None #define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080) #define PSM_FRCE_OFF_SRAM1_MSB _u(7) @@ -241,7 +215,6 @@ #define PSM_FRCE_OFF_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM0 -// Description : None #define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040) #define PSM_FRCE_OFF_SRAM0_MSB _u(6) @@ -249,7 +222,6 @@ #define PSM_FRCE_OFF_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROM -// Description : None #define PSM_FRCE_OFF_ROM_RESET _u(0x0) #define PSM_FRCE_OFF_ROM_BITS _u(0x00000020) #define PSM_FRCE_OFF_ROM_MSB _u(5) @@ -257,7 +229,6 @@ #define PSM_FRCE_OFF_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_BUSFABRIC -// Description : None #define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) #define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010) #define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4) @@ -265,7 +236,6 @@ #define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_RESETS -// Description : None #define PSM_FRCE_OFF_RESETS_RESET _u(0x0) #define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008) #define PSM_FRCE_OFF_RESETS_MSB _u(3) @@ -273,7 +243,6 @@ #define PSM_FRCE_OFF_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_CLOCKS -// Description : None #define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) #define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004) #define PSM_FRCE_OFF_CLOCKS_MSB _u(2) @@ -281,7 +250,6 @@ #define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XOSC -// Description : None #define PSM_FRCE_OFF_XOSC_RESET _u(0x0) #define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002) #define PSM_FRCE_OFF_XOSC_MSB _u(1) @@ -289,7 +257,6 @@ #define PSM_FRCE_OFF_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROSC -// Description : None #define PSM_FRCE_OFF_ROSC_RESET _u(0x0) #define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001) #define PSM_FRCE_OFF_ROSC_MSB _u(0) @@ -304,7 +271,6 @@ #define PSM_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC1 -// Description : None #define PSM_WDSEL_PROC1_RESET _u(0x0) #define PSM_WDSEL_PROC1_BITS _u(0x00010000) #define PSM_WDSEL_PROC1_MSB _u(16) @@ -312,7 +278,6 @@ #define PSM_WDSEL_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC0 -// Description : None #define PSM_WDSEL_PROC0_RESET _u(0x0) #define PSM_WDSEL_PROC0_BITS _u(0x00008000) #define PSM_WDSEL_PROC0_MSB _u(15) @@ -320,7 +285,6 @@ #define PSM_WDSEL_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SIO -// Description : None #define PSM_WDSEL_SIO_RESET _u(0x0) #define PSM_WDSEL_SIO_BITS _u(0x00004000) #define PSM_WDSEL_SIO_MSB _u(14) @@ -328,7 +292,6 @@ #define PSM_WDSEL_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_VREG_AND_CHIP_RESET -// Description : None #define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13) @@ -336,7 +299,6 @@ #define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XIP -// Description : None #define PSM_WDSEL_XIP_RESET _u(0x0) #define PSM_WDSEL_XIP_BITS _u(0x00001000) #define PSM_WDSEL_XIP_MSB _u(12) @@ -344,7 +306,6 @@ #define PSM_WDSEL_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM5 -// Description : None #define PSM_WDSEL_SRAM5_RESET _u(0x0) #define PSM_WDSEL_SRAM5_BITS _u(0x00000800) #define PSM_WDSEL_SRAM5_MSB _u(11) @@ -352,7 +313,6 @@ #define PSM_WDSEL_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM4 -// Description : None #define PSM_WDSEL_SRAM4_RESET _u(0x0) #define PSM_WDSEL_SRAM4_BITS _u(0x00000400) #define PSM_WDSEL_SRAM4_MSB _u(10) @@ -360,7 +320,6 @@ #define PSM_WDSEL_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM3 -// Description : None #define PSM_WDSEL_SRAM3_RESET _u(0x0) #define PSM_WDSEL_SRAM3_BITS _u(0x00000200) #define PSM_WDSEL_SRAM3_MSB _u(9) @@ -368,7 +327,6 @@ #define PSM_WDSEL_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM2 -// Description : None #define PSM_WDSEL_SRAM2_RESET _u(0x0) #define PSM_WDSEL_SRAM2_BITS _u(0x00000100) #define PSM_WDSEL_SRAM2_MSB _u(8) @@ -376,7 +334,6 @@ #define PSM_WDSEL_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM1 -// Description : None #define PSM_WDSEL_SRAM1_RESET _u(0x0) #define PSM_WDSEL_SRAM1_BITS _u(0x00000080) #define PSM_WDSEL_SRAM1_MSB _u(7) @@ -384,7 +341,6 @@ #define PSM_WDSEL_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM0 -// Description : None #define PSM_WDSEL_SRAM0_RESET _u(0x0) #define PSM_WDSEL_SRAM0_BITS _u(0x00000040) #define PSM_WDSEL_SRAM0_MSB _u(6) @@ -392,7 +348,6 @@ #define PSM_WDSEL_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROM -// Description : None #define PSM_WDSEL_ROM_RESET _u(0x0) #define PSM_WDSEL_ROM_BITS _u(0x00000020) #define PSM_WDSEL_ROM_MSB _u(5) @@ -400,7 +355,6 @@ #define PSM_WDSEL_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_BUSFABRIC -// Description : None #define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) #define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010) #define PSM_WDSEL_BUSFABRIC_MSB _u(4) @@ -408,7 +362,6 @@ #define PSM_WDSEL_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_RESETS -// Description : None #define PSM_WDSEL_RESETS_RESET _u(0x0) #define PSM_WDSEL_RESETS_BITS _u(0x00000008) #define PSM_WDSEL_RESETS_MSB _u(3) @@ -416,7 +369,6 @@ #define PSM_WDSEL_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_CLOCKS -// Description : None #define PSM_WDSEL_CLOCKS_RESET _u(0x0) #define PSM_WDSEL_CLOCKS_BITS _u(0x00000004) #define PSM_WDSEL_CLOCKS_MSB _u(2) @@ -424,7 +376,6 @@ #define PSM_WDSEL_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XOSC -// Description : None #define PSM_WDSEL_XOSC_RESET _u(0x0) #define PSM_WDSEL_XOSC_BITS _u(0x00000002) #define PSM_WDSEL_XOSC_MSB _u(1) @@ -432,7 +383,6 @@ #define PSM_WDSEL_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROSC -// Description : None #define PSM_WDSEL_ROSC_RESET _u(0x0) #define PSM_WDSEL_ROSC_BITS _u(0x00000001) #define PSM_WDSEL_ROSC_MSB _u(0) @@ -446,7 +396,6 @@ #define PSM_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC1 -// Description : None #define PSM_DONE_PROC1_RESET _u(0x0) #define PSM_DONE_PROC1_BITS _u(0x00010000) #define PSM_DONE_PROC1_MSB _u(16) @@ -454,7 +403,6 @@ #define PSM_DONE_PROC1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC0 -// Description : None #define PSM_DONE_PROC0_RESET _u(0x0) #define PSM_DONE_PROC0_BITS _u(0x00008000) #define PSM_DONE_PROC0_MSB _u(15) @@ -462,7 +410,6 @@ #define PSM_DONE_PROC0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SIO -// Description : None #define PSM_DONE_SIO_RESET _u(0x0) #define PSM_DONE_SIO_BITS _u(0x00004000) #define PSM_DONE_SIO_MSB _u(14) @@ -470,7 +417,6 @@ #define PSM_DONE_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_VREG_AND_CHIP_RESET -// Description : None #define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13) @@ -478,7 +424,6 @@ #define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XIP -// Description : None #define PSM_DONE_XIP_RESET _u(0x0) #define PSM_DONE_XIP_BITS _u(0x00001000) #define PSM_DONE_XIP_MSB _u(12) @@ -486,7 +431,6 @@ #define PSM_DONE_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM5 -// Description : None #define PSM_DONE_SRAM5_RESET _u(0x0) #define PSM_DONE_SRAM5_BITS _u(0x00000800) #define PSM_DONE_SRAM5_MSB _u(11) @@ -494,7 +438,6 @@ #define PSM_DONE_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM4 -// Description : None #define PSM_DONE_SRAM4_RESET _u(0x0) #define PSM_DONE_SRAM4_BITS _u(0x00000400) #define PSM_DONE_SRAM4_MSB _u(10) @@ -502,7 +445,6 @@ #define PSM_DONE_SRAM4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM3 -// Description : None #define PSM_DONE_SRAM3_RESET _u(0x0) #define PSM_DONE_SRAM3_BITS _u(0x00000200) #define PSM_DONE_SRAM3_MSB _u(9) @@ -510,7 +452,6 @@ #define PSM_DONE_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM2 -// Description : None #define PSM_DONE_SRAM2_RESET _u(0x0) #define PSM_DONE_SRAM2_BITS _u(0x00000100) #define PSM_DONE_SRAM2_MSB _u(8) @@ -518,7 +459,6 @@ #define PSM_DONE_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM1 -// Description : None #define PSM_DONE_SRAM1_RESET _u(0x0) #define PSM_DONE_SRAM1_BITS _u(0x00000080) #define PSM_DONE_SRAM1_MSB _u(7) @@ -526,7 +466,6 @@ #define PSM_DONE_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM0 -// Description : None #define PSM_DONE_SRAM0_RESET _u(0x0) #define PSM_DONE_SRAM0_BITS _u(0x00000040) #define PSM_DONE_SRAM0_MSB _u(6) @@ -534,7 +473,6 @@ #define PSM_DONE_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROM -// Description : None #define PSM_DONE_ROM_RESET _u(0x0) #define PSM_DONE_ROM_BITS _u(0x00000020) #define PSM_DONE_ROM_MSB _u(5) @@ -542,7 +480,6 @@ #define PSM_DONE_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_BUSFABRIC -// Description : None #define PSM_DONE_BUSFABRIC_RESET _u(0x0) #define PSM_DONE_BUSFABRIC_BITS _u(0x00000010) #define PSM_DONE_BUSFABRIC_MSB _u(4) @@ -550,7 +487,6 @@ #define PSM_DONE_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_RESETS -// Description : None #define PSM_DONE_RESETS_RESET _u(0x0) #define PSM_DONE_RESETS_BITS _u(0x00000008) #define PSM_DONE_RESETS_MSB _u(3) @@ -558,7 +494,6 @@ #define PSM_DONE_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_CLOCKS -// Description : None #define PSM_DONE_CLOCKS_RESET _u(0x0) #define PSM_DONE_CLOCKS_BITS _u(0x00000004) #define PSM_DONE_CLOCKS_MSB _u(2) @@ -566,7 +501,6 @@ #define PSM_DONE_CLOCKS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XOSC -// Description : None #define PSM_DONE_XOSC_RESET _u(0x0) #define PSM_DONE_XOSC_BITS _u(0x00000002) #define PSM_DONE_XOSC_MSB _u(1) @@ -574,11 +508,11 @@ #define PSM_DONE_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROSC -// Description : None #define PSM_DONE_ROSC_RESET _u(0x0) #define PSM_DONE_ROSC_BITS _u(0x00000001) #define PSM_DONE_ROSC_MSB _u(0) #define PSM_DONE_ROSC_LSB _u(0) #define PSM_DONE_ROSC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_PSM_DEFINED +#endif // _HARDWARE_REGS_PSM_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/pwm.h b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h index a85359787..29a24f8d0 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/pwm.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/pwm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Simple PWM // ============================================================================= -#ifndef HARDWARE_REGS_PWM_DEFINED -#define HARDWARE_REGS_PWM_DEFINED +#ifndef _HARDWARE_REGS_PWM_H +#define _HARDWARE_REGS_PWM_H // ============================================================================= // Register : PWM_CH0_CSR // Description : Control and status register @@ -42,21 +44,19 @@ #define PWM_CH0_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH0_CSR_DIVMODE_MSB _u(5) -#define PWM_CH0_CSR_DIVMODE_LSB _u(4) -#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH0_CSR_DIVMODE_MSB _u(5) +#define PWM_CH0_CSR_DIVMODE_LSB _u(4) +#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_B_INV // Description : Invert output B @@ -99,7 +99,6 @@ #define PWM_CH0_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_INT -// Description : None #define PWM_CH0_DIV_INT_RESET _u(0x01) #define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH0_DIV_INT_MSB _u(11) @@ -107,7 +106,6 @@ #define PWM_CH0_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_FRAC -// Description : None #define PWM_CH0_DIV_FRAC_RESET _u(0x0) #define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH0_DIV_FRAC_MSB _u(3) @@ -130,7 +128,6 @@ #define PWM_CH0_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_B -// Description : None #define PWM_CH0_CC_B_RESET _u(0x0000) #define PWM_CH0_CC_B_BITS _u(0xffff0000) #define PWM_CH0_CC_B_MSB _u(31) @@ -138,7 +135,6 @@ #define PWM_CH0_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_A -// Description : None #define PWM_CH0_CC_A_RESET _u(0x0000) #define PWM_CH0_CC_A_BITS _u(0x0000ffff) #define PWM_CH0_CC_A_MSB _u(15) @@ -184,21 +180,19 @@ #define PWM_CH1_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH1_CSR_DIVMODE_MSB _u(5) -#define PWM_CH1_CSR_DIVMODE_LSB _u(4) -#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH1_CSR_DIVMODE_MSB _u(5) +#define PWM_CH1_CSR_DIVMODE_LSB _u(4) +#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_B_INV // Description : Invert output B @@ -241,7 +235,6 @@ #define PWM_CH1_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_INT -// Description : None #define PWM_CH1_DIV_INT_RESET _u(0x01) #define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH1_DIV_INT_MSB _u(11) @@ -249,7 +242,6 @@ #define PWM_CH1_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_FRAC -// Description : None #define PWM_CH1_DIV_FRAC_RESET _u(0x0) #define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH1_DIV_FRAC_MSB _u(3) @@ -272,7 +264,6 @@ #define PWM_CH1_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_B -// Description : None #define PWM_CH1_CC_B_RESET _u(0x0000) #define PWM_CH1_CC_B_BITS _u(0xffff0000) #define PWM_CH1_CC_B_MSB _u(31) @@ -280,7 +271,6 @@ #define PWM_CH1_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_A -// Description : None #define PWM_CH1_CC_A_RESET _u(0x0000) #define PWM_CH1_CC_A_BITS _u(0x0000ffff) #define PWM_CH1_CC_A_MSB _u(15) @@ -326,21 +316,19 @@ #define PWM_CH2_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH2_CSR_DIVMODE_MSB _u(5) -#define PWM_CH2_CSR_DIVMODE_LSB _u(4) -#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH2_CSR_DIVMODE_MSB _u(5) +#define PWM_CH2_CSR_DIVMODE_LSB _u(4) +#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_B_INV // Description : Invert output B @@ -383,7 +371,6 @@ #define PWM_CH2_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_INT -// Description : None #define PWM_CH2_DIV_INT_RESET _u(0x01) #define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH2_DIV_INT_MSB _u(11) @@ -391,7 +378,6 @@ #define PWM_CH2_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_FRAC -// Description : None #define PWM_CH2_DIV_FRAC_RESET _u(0x0) #define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH2_DIV_FRAC_MSB _u(3) @@ -414,7 +400,6 @@ #define PWM_CH2_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_B -// Description : None #define PWM_CH2_CC_B_RESET _u(0x0000) #define PWM_CH2_CC_B_BITS _u(0xffff0000) #define PWM_CH2_CC_B_MSB _u(31) @@ -422,7 +407,6 @@ #define PWM_CH2_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_A -// Description : None #define PWM_CH2_CC_A_RESET _u(0x0000) #define PWM_CH2_CC_A_BITS _u(0x0000ffff) #define PWM_CH2_CC_A_MSB _u(15) @@ -468,21 +452,19 @@ #define PWM_CH3_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH3_CSR_DIVMODE_MSB _u(5) -#define PWM_CH3_CSR_DIVMODE_LSB _u(4) -#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH3_CSR_DIVMODE_MSB _u(5) +#define PWM_CH3_CSR_DIVMODE_LSB _u(4) +#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_B_INV // Description : Invert output B @@ -525,7 +507,6 @@ #define PWM_CH3_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_INT -// Description : None #define PWM_CH3_DIV_INT_RESET _u(0x01) #define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH3_DIV_INT_MSB _u(11) @@ -533,7 +514,6 @@ #define PWM_CH3_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_FRAC -// Description : None #define PWM_CH3_DIV_FRAC_RESET _u(0x0) #define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH3_DIV_FRAC_MSB _u(3) @@ -556,7 +536,6 @@ #define PWM_CH3_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_B -// Description : None #define PWM_CH3_CC_B_RESET _u(0x0000) #define PWM_CH3_CC_B_BITS _u(0xffff0000) #define PWM_CH3_CC_B_MSB _u(31) @@ -564,7 +543,6 @@ #define PWM_CH3_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_A -// Description : None #define PWM_CH3_CC_A_RESET _u(0x0000) #define PWM_CH3_CC_A_BITS _u(0x0000ffff) #define PWM_CH3_CC_A_MSB _u(15) @@ -610,21 +588,19 @@ #define PWM_CH4_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH4_CSR_DIVMODE_MSB _u(5) -#define PWM_CH4_CSR_DIVMODE_LSB _u(4) -#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH4_CSR_DIVMODE_MSB _u(5) +#define PWM_CH4_CSR_DIVMODE_LSB _u(4) +#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_B_INV // Description : Invert output B @@ -667,7 +643,6 @@ #define PWM_CH4_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_INT -// Description : None #define PWM_CH4_DIV_INT_RESET _u(0x01) #define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH4_DIV_INT_MSB _u(11) @@ -675,7 +650,6 @@ #define PWM_CH4_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_FRAC -// Description : None #define PWM_CH4_DIV_FRAC_RESET _u(0x0) #define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH4_DIV_FRAC_MSB _u(3) @@ -698,7 +672,6 @@ #define PWM_CH4_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_B -// Description : None #define PWM_CH4_CC_B_RESET _u(0x0000) #define PWM_CH4_CC_B_BITS _u(0xffff0000) #define PWM_CH4_CC_B_MSB _u(31) @@ -706,7 +679,6 @@ #define PWM_CH4_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_A -// Description : None #define PWM_CH4_CC_A_RESET _u(0x0000) #define PWM_CH4_CC_A_BITS _u(0x0000ffff) #define PWM_CH4_CC_A_MSB _u(15) @@ -752,21 +724,19 @@ #define PWM_CH5_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH5_CSR_DIVMODE_MSB _u(5) -#define PWM_CH5_CSR_DIVMODE_LSB _u(4) -#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH5_CSR_DIVMODE_MSB _u(5) +#define PWM_CH5_CSR_DIVMODE_LSB _u(4) +#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_B_INV // Description : Invert output B @@ -809,7 +779,6 @@ #define PWM_CH5_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_INT -// Description : None #define PWM_CH5_DIV_INT_RESET _u(0x01) #define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH5_DIV_INT_MSB _u(11) @@ -817,7 +786,6 @@ #define PWM_CH5_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_FRAC -// Description : None #define PWM_CH5_DIV_FRAC_RESET _u(0x0) #define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH5_DIV_FRAC_MSB _u(3) @@ -840,7 +808,6 @@ #define PWM_CH5_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_B -// Description : None #define PWM_CH5_CC_B_RESET _u(0x0000) #define PWM_CH5_CC_B_BITS _u(0xffff0000) #define PWM_CH5_CC_B_MSB _u(31) @@ -848,7 +815,6 @@ #define PWM_CH5_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_A -// Description : None #define PWM_CH5_CC_A_RESET _u(0x0000) #define PWM_CH5_CC_A_BITS _u(0x0000ffff) #define PWM_CH5_CC_A_MSB _u(15) @@ -894,21 +860,19 @@ #define PWM_CH6_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH6_CSR_DIVMODE_MSB _u(5) -#define PWM_CH6_CSR_DIVMODE_LSB _u(4) -#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH6_CSR_DIVMODE_MSB _u(5) +#define PWM_CH6_CSR_DIVMODE_LSB _u(4) +#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_B_INV // Description : Invert output B @@ -951,7 +915,6 @@ #define PWM_CH6_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_INT -// Description : None #define PWM_CH6_DIV_INT_RESET _u(0x01) #define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH6_DIV_INT_MSB _u(11) @@ -959,7 +922,6 @@ #define PWM_CH6_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_FRAC -// Description : None #define PWM_CH6_DIV_FRAC_RESET _u(0x0) #define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH6_DIV_FRAC_MSB _u(3) @@ -982,7 +944,6 @@ #define PWM_CH6_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_B -// Description : None #define PWM_CH6_CC_B_RESET _u(0x0000) #define PWM_CH6_CC_B_BITS _u(0xffff0000) #define PWM_CH6_CC_B_MSB _u(31) @@ -990,7 +951,6 @@ #define PWM_CH6_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_A -// Description : None #define PWM_CH6_CC_A_RESET _u(0x0000) #define PWM_CH6_CC_A_BITS _u(0x0000ffff) #define PWM_CH6_CC_A_MSB _u(15) @@ -1036,21 +996,19 @@ #define PWM_CH7_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH7_CSR_DIVMODE_MSB _u(5) -#define PWM_CH7_CSR_DIVMODE_LSB _u(4) -#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH7_CSR_DIVMODE_MSB _u(5) +#define PWM_CH7_CSR_DIVMODE_LSB _u(4) +#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_B_INV // Description : Invert output B @@ -1093,7 +1051,6 @@ #define PWM_CH7_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_INT -// Description : None #define PWM_CH7_DIV_INT_RESET _u(0x01) #define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH7_DIV_INT_MSB _u(11) @@ -1101,7 +1058,6 @@ #define PWM_CH7_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_FRAC -// Description : None #define PWM_CH7_DIV_FRAC_RESET _u(0x0) #define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH7_DIV_FRAC_MSB _u(3) @@ -1124,7 +1080,6 @@ #define PWM_CH7_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_B -// Description : None #define PWM_CH7_CC_B_RESET _u(0x0000) #define PWM_CH7_CC_B_BITS _u(0xffff0000) #define PWM_CH7_CC_B_MSB _u(31) @@ -1132,7 +1087,6 @@ #define PWM_CH7_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_A -// Description : None #define PWM_CH7_CC_A_RESET _u(0x0000) #define PWM_CH7_CC_A_BITS _u(0x0000ffff) #define PWM_CH7_CC_A_MSB _u(15) @@ -1159,7 +1113,6 @@ #define PWM_EN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_EN_CH7 -// Description : None #define PWM_EN_CH7_RESET _u(0x0) #define PWM_EN_CH7_BITS _u(0x00000080) #define PWM_EN_CH7_MSB _u(7) @@ -1167,7 +1120,6 @@ #define PWM_EN_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH6 -// Description : None #define PWM_EN_CH6_RESET _u(0x0) #define PWM_EN_CH6_BITS _u(0x00000040) #define PWM_EN_CH6_MSB _u(6) @@ -1175,7 +1127,6 @@ #define PWM_EN_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH5 -// Description : None #define PWM_EN_CH5_RESET _u(0x0) #define PWM_EN_CH5_BITS _u(0x00000020) #define PWM_EN_CH5_MSB _u(5) @@ -1183,7 +1134,6 @@ #define PWM_EN_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH4 -// Description : None #define PWM_EN_CH4_RESET _u(0x0) #define PWM_EN_CH4_BITS _u(0x00000010) #define PWM_EN_CH4_MSB _u(4) @@ -1191,7 +1141,6 @@ #define PWM_EN_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH3 -// Description : None #define PWM_EN_CH3_RESET _u(0x0) #define PWM_EN_CH3_BITS _u(0x00000008) #define PWM_EN_CH3_MSB _u(3) @@ -1199,7 +1148,6 @@ #define PWM_EN_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH2 -// Description : None #define PWM_EN_CH2_RESET _u(0x0) #define PWM_EN_CH2_BITS _u(0x00000004) #define PWM_EN_CH2_MSB _u(2) @@ -1207,7 +1155,6 @@ #define PWM_EN_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH1 -// Description : None #define PWM_EN_CH1_RESET _u(0x0) #define PWM_EN_CH1_BITS _u(0x00000002) #define PWM_EN_CH1_MSB _u(1) @@ -1215,7 +1162,6 @@ #define PWM_EN_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH0 -// Description : None #define PWM_EN_CH0_RESET _u(0x0) #define PWM_EN_CH0_BITS _u(0x00000001) #define PWM_EN_CH0_MSB _u(0) @@ -1229,7 +1175,6 @@ #define PWM_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH7 -// Description : None #define PWM_INTR_CH7_RESET _u(0x0) #define PWM_INTR_CH7_BITS _u(0x00000080) #define PWM_INTR_CH7_MSB _u(7) @@ -1237,7 +1182,6 @@ #define PWM_INTR_CH7_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH6 -// Description : None #define PWM_INTR_CH6_RESET _u(0x0) #define PWM_INTR_CH6_BITS _u(0x00000040) #define PWM_INTR_CH6_MSB _u(6) @@ -1245,7 +1189,6 @@ #define PWM_INTR_CH6_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH5 -// Description : None #define PWM_INTR_CH5_RESET _u(0x0) #define PWM_INTR_CH5_BITS _u(0x00000020) #define PWM_INTR_CH5_MSB _u(5) @@ -1253,7 +1196,6 @@ #define PWM_INTR_CH5_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH4 -// Description : None #define PWM_INTR_CH4_RESET _u(0x0) #define PWM_INTR_CH4_BITS _u(0x00000010) #define PWM_INTR_CH4_MSB _u(4) @@ -1261,7 +1203,6 @@ #define PWM_INTR_CH4_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH3 -// Description : None #define PWM_INTR_CH3_RESET _u(0x0) #define PWM_INTR_CH3_BITS _u(0x00000008) #define PWM_INTR_CH3_MSB _u(3) @@ -1269,7 +1210,6 @@ #define PWM_INTR_CH3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH2 -// Description : None #define PWM_INTR_CH2_RESET _u(0x0) #define PWM_INTR_CH2_BITS _u(0x00000004) #define PWM_INTR_CH2_MSB _u(2) @@ -1277,7 +1217,6 @@ #define PWM_INTR_CH2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH1 -// Description : None #define PWM_INTR_CH1_RESET _u(0x0) #define PWM_INTR_CH1_BITS _u(0x00000002) #define PWM_INTR_CH1_MSB _u(1) @@ -1285,7 +1224,6 @@ #define PWM_INTR_CH1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH0 -// Description : None #define PWM_INTR_CH0_RESET _u(0x0) #define PWM_INTR_CH0_BITS _u(0x00000001) #define PWM_INTR_CH0_MSB _u(0) @@ -1299,7 +1237,6 @@ #define PWM_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH7 -// Description : None #define PWM_INTE_CH7_RESET _u(0x0) #define PWM_INTE_CH7_BITS _u(0x00000080) #define PWM_INTE_CH7_MSB _u(7) @@ -1307,7 +1244,6 @@ #define PWM_INTE_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH6 -// Description : None #define PWM_INTE_CH6_RESET _u(0x0) #define PWM_INTE_CH6_BITS _u(0x00000040) #define PWM_INTE_CH6_MSB _u(6) @@ -1315,7 +1251,6 @@ #define PWM_INTE_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH5 -// Description : None #define PWM_INTE_CH5_RESET _u(0x0) #define PWM_INTE_CH5_BITS _u(0x00000020) #define PWM_INTE_CH5_MSB _u(5) @@ -1323,7 +1258,6 @@ #define PWM_INTE_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH4 -// Description : None #define PWM_INTE_CH4_RESET _u(0x0) #define PWM_INTE_CH4_BITS _u(0x00000010) #define PWM_INTE_CH4_MSB _u(4) @@ -1331,7 +1265,6 @@ #define PWM_INTE_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH3 -// Description : None #define PWM_INTE_CH3_RESET _u(0x0) #define PWM_INTE_CH3_BITS _u(0x00000008) #define PWM_INTE_CH3_MSB _u(3) @@ -1339,7 +1272,6 @@ #define PWM_INTE_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH2 -// Description : None #define PWM_INTE_CH2_RESET _u(0x0) #define PWM_INTE_CH2_BITS _u(0x00000004) #define PWM_INTE_CH2_MSB _u(2) @@ -1347,7 +1279,6 @@ #define PWM_INTE_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH1 -// Description : None #define PWM_INTE_CH1_RESET _u(0x0) #define PWM_INTE_CH1_BITS _u(0x00000002) #define PWM_INTE_CH1_MSB _u(1) @@ -1355,7 +1286,6 @@ #define PWM_INTE_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH0 -// Description : None #define PWM_INTE_CH0_RESET _u(0x0) #define PWM_INTE_CH0_BITS _u(0x00000001) #define PWM_INTE_CH0_MSB _u(0) @@ -1369,7 +1299,6 @@ #define PWM_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH7 -// Description : None #define PWM_INTF_CH7_RESET _u(0x0) #define PWM_INTF_CH7_BITS _u(0x00000080) #define PWM_INTF_CH7_MSB _u(7) @@ -1377,7 +1306,6 @@ #define PWM_INTF_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH6 -// Description : None #define PWM_INTF_CH6_RESET _u(0x0) #define PWM_INTF_CH6_BITS _u(0x00000040) #define PWM_INTF_CH6_MSB _u(6) @@ -1385,7 +1313,6 @@ #define PWM_INTF_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH5 -// Description : None #define PWM_INTF_CH5_RESET _u(0x0) #define PWM_INTF_CH5_BITS _u(0x00000020) #define PWM_INTF_CH5_MSB _u(5) @@ -1393,7 +1320,6 @@ #define PWM_INTF_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH4 -// Description : None #define PWM_INTF_CH4_RESET _u(0x0) #define PWM_INTF_CH4_BITS _u(0x00000010) #define PWM_INTF_CH4_MSB _u(4) @@ -1401,7 +1327,6 @@ #define PWM_INTF_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH3 -// Description : None #define PWM_INTF_CH3_RESET _u(0x0) #define PWM_INTF_CH3_BITS _u(0x00000008) #define PWM_INTF_CH3_MSB _u(3) @@ -1409,7 +1334,6 @@ #define PWM_INTF_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH2 -// Description : None #define PWM_INTF_CH2_RESET _u(0x0) #define PWM_INTF_CH2_BITS _u(0x00000004) #define PWM_INTF_CH2_MSB _u(2) @@ -1417,7 +1341,6 @@ #define PWM_INTF_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH1 -// Description : None #define PWM_INTF_CH1_RESET _u(0x0) #define PWM_INTF_CH1_BITS _u(0x00000002) #define PWM_INTF_CH1_MSB _u(1) @@ -1425,7 +1348,6 @@ #define PWM_INTF_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH0 -// Description : None #define PWM_INTF_CH0_RESET _u(0x0) #define PWM_INTF_CH0_BITS _u(0x00000001) #define PWM_INTF_CH0_MSB _u(0) @@ -1439,7 +1361,6 @@ #define PWM_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH7 -// Description : None #define PWM_INTS_CH7_RESET _u(0x0) #define PWM_INTS_CH7_BITS _u(0x00000080) #define PWM_INTS_CH7_MSB _u(7) @@ -1447,7 +1368,6 @@ #define PWM_INTS_CH7_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH6 -// Description : None #define PWM_INTS_CH6_RESET _u(0x0) #define PWM_INTS_CH6_BITS _u(0x00000040) #define PWM_INTS_CH6_MSB _u(6) @@ -1455,7 +1375,6 @@ #define PWM_INTS_CH6_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH5 -// Description : None #define PWM_INTS_CH5_RESET _u(0x0) #define PWM_INTS_CH5_BITS _u(0x00000020) #define PWM_INTS_CH5_MSB _u(5) @@ -1463,7 +1382,6 @@ #define PWM_INTS_CH5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH4 -// Description : None #define PWM_INTS_CH4_RESET _u(0x0) #define PWM_INTS_CH4_BITS _u(0x00000010) #define PWM_INTS_CH4_MSB _u(4) @@ -1471,7 +1389,6 @@ #define PWM_INTS_CH4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH3 -// Description : None #define PWM_INTS_CH3_RESET _u(0x0) #define PWM_INTS_CH3_BITS _u(0x00000008) #define PWM_INTS_CH3_MSB _u(3) @@ -1479,7 +1396,6 @@ #define PWM_INTS_CH3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH2 -// Description : None #define PWM_INTS_CH2_RESET _u(0x0) #define PWM_INTS_CH2_BITS _u(0x00000004) #define PWM_INTS_CH2_MSB _u(2) @@ -1487,7 +1403,6 @@ #define PWM_INTS_CH2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH1 -// Description : None #define PWM_INTS_CH1_RESET _u(0x0) #define PWM_INTS_CH1_BITS _u(0x00000002) #define PWM_INTS_CH1_MSB _u(1) @@ -1495,11 +1410,11 @@ #define PWM_INTS_CH1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH0 -// Description : None #define PWM_INTS_CH0_RESET _u(0x0) #define PWM_INTS_CH0_BITS _u(0x00000001) #define PWM_INTS_CH0_MSB _u(0) #define PWM_INTS_CH0_LSB _u(0) #define PWM_INTS_CH0_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_PWM_DEFINED +#endif // _HARDWARE_REGS_PWM_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/resets.h b/src/rp2040/hardware_regs/include/hardware/regs/resets.h index 689a358b0..03a56e75d 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/resets.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/resets.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : RESETS // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_RESETS_DEFINED -#define HARDWARE_REGS_RESETS_DEFINED +#ifndef _HARDWARE_REGS_RESETS_H +#define _HARDWARE_REGS_RESETS_H // ============================================================================= // Register : RESETS_RESET // Description : Reset control. If a bit is set it means the peripheral is in @@ -20,7 +21,6 @@ #define RESETS_RESET_RESET _u(0x01ffffff) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_USBCTRL -// Description : None #define RESETS_RESET_USBCTRL_RESET _u(0x1) #define RESETS_RESET_USBCTRL_BITS _u(0x01000000) #define RESETS_RESET_USBCTRL_MSB _u(24) @@ -28,7 +28,6 @@ #define RESETS_RESET_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART1 -// Description : None #define RESETS_RESET_UART1_RESET _u(0x1) #define RESETS_RESET_UART1_BITS _u(0x00800000) #define RESETS_RESET_UART1_MSB _u(23) @@ -36,7 +35,6 @@ #define RESETS_RESET_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART0 -// Description : None #define RESETS_RESET_UART0_RESET _u(0x1) #define RESETS_RESET_UART0_BITS _u(0x00400000) #define RESETS_RESET_UART0_MSB _u(22) @@ -44,7 +42,6 @@ #define RESETS_RESET_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TIMER -// Description : None #define RESETS_RESET_TIMER_RESET _u(0x1) #define RESETS_RESET_TIMER_BITS _u(0x00200000) #define RESETS_RESET_TIMER_MSB _u(21) @@ -52,7 +49,6 @@ #define RESETS_RESET_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TBMAN -// Description : None #define RESETS_RESET_TBMAN_RESET _u(0x1) #define RESETS_RESET_TBMAN_BITS _u(0x00100000) #define RESETS_RESET_TBMAN_MSB _u(20) @@ -60,7 +56,6 @@ #define RESETS_RESET_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSINFO -// Description : None #define RESETS_RESET_SYSINFO_RESET _u(0x1) #define RESETS_RESET_SYSINFO_BITS _u(0x00080000) #define RESETS_RESET_SYSINFO_MSB _u(19) @@ -68,7 +63,6 @@ #define RESETS_RESET_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSCFG -// Description : None #define RESETS_RESET_SYSCFG_RESET _u(0x1) #define RESETS_RESET_SYSCFG_BITS _u(0x00040000) #define RESETS_RESET_SYSCFG_MSB _u(18) @@ -76,7 +70,6 @@ #define RESETS_RESET_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI1 -// Description : None #define RESETS_RESET_SPI1_RESET _u(0x1) #define RESETS_RESET_SPI1_BITS _u(0x00020000) #define RESETS_RESET_SPI1_MSB _u(17) @@ -84,7 +77,6 @@ #define RESETS_RESET_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI0 -// Description : None #define RESETS_RESET_SPI0_RESET _u(0x1) #define RESETS_RESET_SPI0_BITS _u(0x00010000) #define RESETS_RESET_SPI0_MSB _u(16) @@ -92,7 +84,6 @@ #define RESETS_RESET_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_RTC -// Description : None #define RESETS_RESET_RTC_RESET _u(0x1) #define RESETS_RESET_RTC_BITS _u(0x00008000) #define RESETS_RESET_RTC_MSB _u(15) @@ -100,7 +91,6 @@ #define RESETS_RESET_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PWM -// Description : None #define RESETS_RESET_PWM_RESET _u(0x1) #define RESETS_RESET_PWM_BITS _u(0x00004000) #define RESETS_RESET_PWM_MSB _u(14) @@ -108,7 +98,6 @@ #define RESETS_RESET_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_USB -// Description : None #define RESETS_RESET_PLL_USB_RESET _u(0x1) #define RESETS_RESET_PLL_USB_BITS _u(0x00002000) #define RESETS_RESET_PLL_USB_MSB _u(13) @@ -116,7 +105,6 @@ #define RESETS_RESET_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_SYS -// Description : None #define RESETS_RESET_PLL_SYS_RESET _u(0x1) #define RESETS_RESET_PLL_SYS_BITS _u(0x00001000) #define RESETS_RESET_PLL_SYS_MSB _u(12) @@ -124,7 +112,6 @@ #define RESETS_RESET_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO1 -// Description : None #define RESETS_RESET_PIO1_RESET _u(0x1) #define RESETS_RESET_PIO1_BITS _u(0x00000800) #define RESETS_RESET_PIO1_MSB _u(11) @@ -132,7 +119,6 @@ #define RESETS_RESET_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO0 -// Description : None #define RESETS_RESET_PIO0_RESET _u(0x1) #define RESETS_RESET_PIO0_BITS _u(0x00000400) #define RESETS_RESET_PIO0_MSB _u(10) @@ -140,7 +126,6 @@ #define RESETS_RESET_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_QSPI -// Description : None #define RESETS_RESET_PADS_QSPI_RESET _u(0x1) #define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200) #define RESETS_RESET_PADS_QSPI_MSB _u(9) @@ -148,7 +133,6 @@ #define RESETS_RESET_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_BANK0 -// Description : None #define RESETS_RESET_PADS_BANK0_RESET _u(0x1) #define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100) #define RESETS_RESET_PADS_BANK0_MSB _u(8) @@ -156,7 +140,6 @@ #define RESETS_RESET_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_JTAG -// Description : None #define RESETS_RESET_JTAG_RESET _u(0x1) #define RESETS_RESET_JTAG_BITS _u(0x00000080) #define RESETS_RESET_JTAG_MSB _u(7) @@ -164,7 +147,6 @@ #define RESETS_RESET_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_QSPI -// Description : None #define RESETS_RESET_IO_QSPI_RESET _u(0x1) #define RESETS_RESET_IO_QSPI_BITS _u(0x00000040) #define RESETS_RESET_IO_QSPI_MSB _u(6) @@ -172,7 +154,6 @@ #define RESETS_RESET_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_BANK0 -// Description : None #define RESETS_RESET_IO_BANK0_RESET _u(0x1) #define RESETS_RESET_IO_BANK0_BITS _u(0x00000020) #define RESETS_RESET_IO_BANK0_MSB _u(5) @@ -180,7 +161,6 @@ #define RESETS_RESET_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C1 -// Description : None #define RESETS_RESET_I2C1_RESET _u(0x1) #define RESETS_RESET_I2C1_BITS _u(0x00000010) #define RESETS_RESET_I2C1_MSB _u(4) @@ -188,7 +168,6 @@ #define RESETS_RESET_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C0 -// Description : None #define RESETS_RESET_I2C0_RESET _u(0x1) #define RESETS_RESET_I2C0_BITS _u(0x00000008) #define RESETS_RESET_I2C0_MSB _u(3) @@ -196,7 +175,6 @@ #define RESETS_RESET_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DMA -// Description : None #define RESETS_RESET_DMA_RESET _u(0x1) #define RESETS_RESET_DMA_BITS _u(0x00000004) #define RESETS_RESET_DMA_MSB _u(2) @@ -204,7 +182,6 @@ #define RESETS_RESET_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_BUSCTRL -// Description : None #define RESETS_RESET_BUSCTRL_RESET _u(0x1) #define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) #define RESETS_RESET_BUSCTRL_MSB _u(1) @@ -212,7 +189,6 @@ #define RESETS_RESET_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_ADC -// Description : None #define RESETS_RESET_ADC_RESET _u(0x1) #define RESETS_RESET_ADC_BITS _u(0x00000001) #define RESETS_RESET_ADC_MSB _u(0) @@ -227,7 +203,6 @@ #define RESETS_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_USBCTRL -// Description : None #define RESETS_WDSEL_USBCTRL_RESET _u(0x0) #define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000) #define RESETS_WDSEL_USBCTRL_MSB _u(24) @@ -235,7 +210,6 @@ #define RESETS_WDSEL_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART1 -// Description : None #define RESETS_WDSEL_UART1_RESET _u(0x0) #define RESETS_WDSEL_UART1_BITS _u(0x00800000) #define RESETS_WDSEL_UART1_MSB _u(23) @@ -243,7 +217,6 @@ #define RESETS_WDSEL_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART0 -// Description : None #define RESETS_WDSEL_UART0_RESET _u(0x0) #define RESETS_WDSEL_UART0_BITS _u(0x00400000) #define RESETS_WDSEL_UART0_MSB _u(22) @@ -251,7 +224,6 @@ #define RESETS_WDSEL_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TIMER -// Description : None #define RESETS_WDSEL_TIMER_RESET _u(0x0) #define RESETS_WDSEL_TIMER_BITS _u(0x00200000) #define RESETS_WDSEL_TIMER_MSB _u(21) @@ -259,7 +231,6 @@ #define RESETS_WDSEL_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TBMAN -// Description : None #define RESETS_WDSEL_TBMAN_RESET _u(0x0) #define RESETS_WDSEL_TBMAN_BITS _u(0x00100000) #define RESETS_WDSEL_TBMAN_MSB _u(20) @@ -267,7 +238,6 @@ #define RESETS_WDSEL_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSINFO -// Description : None #define RESETS_WDSEL_SYSINFO_RESET _u(0x0) #define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000) #define RESETS_WDSEL_SYSINFO_MSB _u(19) @@ -275,7 +245,6 @@ #define RESETS_WDSEL_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSCFG -// Description : None #define RESETS_WDSEL_SYSCFG_RESET _u(0x0) #define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000) #define RESETS_WDSEL_SYSCFG_MSB _u(18) @@ -283,7 +252,6 @@ #define RESETS_WDSEL_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI1 -// Description : None #define RESETS_WDSEL_SPI1_RESET _u(0x0) #define RESETS_WDSEL_SPI1_BITS _u(0x00020000) #define RESETS_WDSEL_SPI1_MSB _u(17) @@ -291,7 +259,6 @@ #define RESETS_WDSEL_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI0 -// Description : None #define RESETS_WDSEL_SPI0_RESET _u(0x0) #define RESETS_WDSEL_SPI0_BITS _u(0x00010000) #define RESETS_WDSEL_SPI0_MSB _u(16) @@ -299,7 +266,6 @@ #define RESETS_WDSEL_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_RTC -// Description : None #define RESETS_WDSEL_RTC_RESET _u(0x0) #define RESETS_WDSEL_RTC_BITS _u(0x00008000) #define RESETS_WDSEL_RTC_MSB _u(15) @@ -307,7 +273,6 @@ #define RESETS_WDSEL_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PWM -// Description : None #define RESETS_WDSEL_PWM_RESET _u(0x0) #define RESETS_WDSEL_PWM_BITS _u(0x00004000) #define RESETS_WDSEL_PWM_MSB _u(14) @@ -315,7 +280,6 @@ #define RESETS_WDSEL_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_USB -// Description : None #define RESETS_WDSEL_PLL_USB_RESET _u(0x0) #define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000) #define RESETS_WDSEL_PLL_USB_MSB _u(13) @@ -323,7 +287,6 @@ #define RESETS_WDSEL_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_SYS -// Description : None #define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) #define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000) #define RESETS_WDSEL_PLL_SYS_MSB _u(12) @@ -331,7 +294,6 @@ #define RESETS_WDSEL_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO1 -// Description : None #define RESETS_WDSEL_PIO1_RESET _u(0x0) #define RESETS_WDSEL_PIO1_BITS _u(0x00000800) #define RESETS_WDSEL_PIO1_MSB _u(11) @@ -339,7 +301,6 @@ #define RESETS_WDSEL_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO0 -// Description : None #define RESETS_WDSEL_PIO0_RESET _u(0x0) #define RESETS_WDSEL_PIO0_BITS _u(0x00000400) #define RESETS_WDSEL_PIO0_MSB _u(10) @@ -347,7 +308,6 @@ #define RESETS_WDSEL_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_QSPI -// Description : None #define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) #define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200) #define RESETS_WDSEL_PADS_QSPI_MSB _u(9) @@ -355,7 +315,6 @@ #define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_BANK0 -// Description : None #define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) #define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100) #define RESETS_WDSEL_PADS_BANK0_MSB _u(8) @@ -363,7 +322,6 @@ #define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_JTAG -// Description : None #define RESETS_WDSEL_JTAG_RESET _u(0x0) #define RESETS_WDSEL_JTAG_BITS _u(0x00000080) #define RESETS_WDSEL_JTAG_MSB _u(7) @@ -371,7 +329,6 @@ #define RESETS_WDSEL_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_QSPI -// Description : None #define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) #define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040) #define RESETS_WDSEL_IO_QSPI_MSB _u(6) @@ -379,7 +336,6 @@ #define RESETS_WDSEL_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_BANK0 -// Description : None #define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) #define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020) #define RESETS_WDSEL_IO_BANK0_MSB _u(5) @@ -387,7 +343,6 @@ #define RESETS_WDSEL_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C1 -// Description : None #define RESETS_WDSEL_I2C1_RESET _u(0x0) #define RESETS_WDSEL_I2C1_BITS _u(0x00000010) #define RESETS_WDSEL_I2C1_MSB _u(4) @@ -395,7 +350,6 @@ #define RESETS_WDSEL_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C0 -// Description : None #define RESETS_WDSEL_I2C0_RESET _u(0x0) #define RESETS_WDSEL_I2C0_BITS _u(0x00000008) #define RESETS_WDSEL_I2C0_MSB _u(3) @@ -403,7 +357,6 @@ #define RESETS_WDSEL_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_DMA -// Description : None #define RESETS_WDSEL_DMA_RESET _u(0x0) #define RESETS_WDSEL_DMA_BITS _u(0x00000004) #define RESETS_WDSEL_DMA_MSB _u(2) @@ -411,7 +364,6 @@ #define RESETS_WDSEL_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_BUSCTRL -// Description : None #define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) #define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) #define RESETS_WDSEL_BUSCTRL_MSB _u(1) @@ -419,7 +371,6 @@ #define RESETS_WDSEL_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_ADC -// Description : None #define RESETS_WDSEL_ADC_RESET _u(0x0) #define RESETS_WDSEL_ADC_BITS _u(0x00000001) #define RESETS_WDSEL_ADC_MSB _u(0) @@ -435,7 +386,6 @@ #define RESETS_RESET_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_USBCTRL -// Description : None #define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) #define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000) #define RESETS_RESET_DONE_USBCTRL_MSB _u(24) @@ -443,7 +393,6 @@ #define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART1 -// Description : None #define RESETS_RESET_DONE_UART1_RESET _u(0x0) #define RESETS_RESET_DONE_UART1_BITS _u(0x00800000) #define RESETS_RESET_DONE_UART1_MSB _u(23) @@ -451,7 +400,6 @@ #define RESETS_RESET_DONE_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART0 -// Description : None #define RESETS_RESET_DONE_UART0_RESET _u(0x0) #define RESETS_RESET_DONE_UART0_BITS _u(0x00400000) #define RESETS_RESET_DONE_UART0_MSB _u(22) @@ -459,7 +407,6 @@ #define RESETS_RESET_DONE_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TIMER -// Description : None #define RESETS_RESET_DONE_TIMER_RESET _u(0x0) #define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000) #define RESETS_RESET_DONE_TIMER_MSB _u(21) @@ -467,7 +414,6 @@ #define RESETS_RESET_DONE_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TBMAN -// Description : None #define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) #define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000) #define RESETS_RESET_DONE_TBMAN_MSB _u(20) @@ -475,7 +421,6 @@ #define RESETS_RESET_DONE_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSINFO -// Description : None #define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) #define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000) #define RESETS_RESET_DONE_SYSINFO_MSB _u(19) @@ -483,7 +428,6 @@ #define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSCFG -// Description : None #define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) #define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000) #define RESETS_RESET_DONE_SYSCFG_MSB _u(18) @@ -491,7 +435,6 @@ #define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI1 -// Description : None #define RESETS_RESET_DONE_SPI1_RESET _u(0x0) #define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000) #define RESETS_RESET_DONE_SPI1_MSB _u(17) @@ -499,7 +442,6 @@ #define RESETS_RESET_DONE_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI0 -// Description : None #define RESETS_RESET_DONE_SPI0_RESET _u(0x0) #define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000) #define RESETS_RESET_DONE_SPI0_MSB _u(16) @@ -507,7 +449,6 @@ #define RESETS_RESET_DONE_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_RTC -// Description : None #define RESETS_RESET_DONE_RTC_RESET _u(0x0) #define RESETS_RESET_DONE_RTC_BITS _u(0x00008000) #define RESETS_RESET_DONE_RTC_MSB _u(15) @@ -515,7 +456,6 @@ #define RESETS_RESET_DONE_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PWM -// Description : None #define RESETS_RESET_DONE_PWM_RESET _u(0x0) #define RESETS_RESET_DONE_PWM_BITS _u(0x00004000) #define RESETS_RESET_DONE_PWM_MSB _u(14) @@ -523,7 +463,6 @@ #define RESETS_RESET_DONE_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_USB -// Description : None #define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) #define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000) #define RESETS_RESET_DONE_PLL_USB_MSB _u(13) @@ -531,7 +470,6 @@ #define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_SYS -// Description : None #define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) #define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000) #define RESETS_RESET_DONE_PLL_SYS_MSB _u(12) @@ -539,7 +477,6 @@ #define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO1 -// Description : None #define RESETS_RESET_DONE_PIO1_RESET _u(0x0) #define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800) #define RESETS_RESET_DONE_PIO1_MSB _u(11) @@ -547,7 +484,6 @@ #define RESETS_RESET_DONE_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO0 -// Description : None #define RESETS_RESET_DONE_PIO0_RESET _u(0x0) #define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400) #define RESETS_RESET_DONE_PIO0_MSB _u(10) @@ -555,7 +491,6 @@ #define RESETS_RESET_DONE_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_QSPI -// Description : None #define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) #define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200) #define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9) @@ -563,7 +498,6 @@ #define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_BANK0 -// Description : None #define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) #define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100) #define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8) @@ -571,7 +505,6 @@ #define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_JTAG -// Description : None #define RESETS_RESET_DONE_JTAG_RESET _u(0x0) #define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080) #define RESETS_RESET_DONE_JTAG_MSB _u(7) @@ -579,7 +512,6 @@ #define RESETS_RESET_DONE_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_QSPI -// Description : None #define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) #define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040) #define RESETS_RESET_DONE_IO_QSPI_MSB _u(6) @@ -587,7 +519,6 @@ #define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_BANK0 -// Description : None #define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) #define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020) #define RESETS_RESET_DONE_IO_BANK0_MSB _u(5) @@ -595,7 +526,6 @@ #define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C1 -// Description : None #define RESETS_RESET_DONE_I2C1_RESET _u(0x0) #define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010) #define RESETS_RESET_DONE_I2C1_MSB _u(4) @@ -603,7 +533,6 @@ #define RESETS_RESET_DONE_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C0 -// Description : None #define RESETS_RESET_DONE_I2C0_RESET _u(0x0) #define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008) #define RESETS_RESET_DONE_I2C0_MSB _u(3) @@ -611,7 +540,6 @@ #define RESETS_RESET_DONE_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_DMA -// Description : None #define RESETS_RESET_DONE_DMA_RESET _u(0x0) #define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) #define RESETS_RESET_DONE_DMA_MSB _u(2) @@ -619,7 +547,6 @@ #define RESETS_RESET_DONE_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_BUSCTRL -// Description : None #define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) #define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) #define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) @@ -627,11 +554,11 @@ #define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_ADC -// Description : None #define RESETS_RESET_DONE_ADC_RESET _u(0x0) #define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) #define RESETS_RESET_DONE_ADC_MSB _u(0) #define RESETS_RESET_DONE_ADC_LSB _u(0) #define RESETS_RESET_DONE_ADC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_RESETS_DEFINED +#endif // _HARDWARE_REGS_RESETS_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h index 5501e7ef2..bd4bb9d4a 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/rosc.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/rosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : ROSC // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_ROSC_DEFINED -#define HARDWARE_REGS_ROSC_DEFINED +#ifndef _HARDWARE_REGS_ROSC_H +#define _HARDWARE_REGS_ROSC_H // ============================================================================= // Register : ROSC_CTRL // Description : Ring Oscillator control @@ -27,20 +28,20 @@ // oscillator. // 0xd1e -> DISABLE // 0xfab -> ENABLE -#define ROSC_CTRL_ENABLE_RESET "-" -#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define ROSC_CTRL_ENABLE_MSB _u(23) -#define ROSC_CTRL_ENABLE_LSB _u(12) -#define ROSC_CTRL_ENABLE_ACCESS "RW" +#define ROSC_CTRL_ENABLE_RESET "-" +#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define ROSC_CTRL_ENABLE_MSB _u(23) +#define ROSC_CTRL_ENABLE_LSB _u(12) +#define ROSC_CTRL_ENABLE_ACCESS "RW" #define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : ROSC_CTRL_FREQ_RANGE // Description : Controls the number of delay stages in the ROSC ring // LOW uses stages 0 to 7 -// MEDIUM uses stages 0 to 5 -// HIGH uses stages 0 to 3 -// TOOHIGH uses stages 0 to 1 and should not be used because its +// MEDIUM uses stages 2 to 7 +// HIGH uses stages 4 to 7 +// TOOHIGH uses stages 6 to 7 and should not be used because its // frequency exceeds design specifications // The clock output will not glitch when changing the range up one // step at a time @@ -51,14 +52,14 @@ // 0xfa5 -> MEDIUM // 0xfa7 -> HIGH // 0xfa6 -> TOOHIGH -#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) -#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) -#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) -#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) -#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) -#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) +#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) +#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) +#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) +#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) #define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) // ============================================================================= // Register : ROSC_FREQA @@ -80,11 +81,11 @@ // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQA_PASSWD_RESET _u(0x0000) -#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQA_PASSWD_MSB _u(31) -#define ROSC_FREQA_PASSWD_LSB _u(16) -#define ROSC_FREQA_PASSWD_ACCESS "RW" +#define ROSC_FREQA_PASSWD_RESET _u(0x0000) +#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQA_PASSWD_MSB _u(31) +#define ROSC_FREQA_PASSWD_LSB _u(16) +#define ROSC_FREQA_PASSWD_ACCESS "RW" #define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS3 @@ -129,11 +130,11 @@ // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQB_PASSWD_RESET _u(0x0000) -#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQB_PASSWD_MSB _u(31) -#define ROSC_FREQB_PASSWD_LSB _u(16) -#define ROSC_FREQB_PASSWD_ACCESS "RW" +#define ROSC_FREQB_PASSWD_RESET _u(0x0000) +#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQB_PASSWD_MSB _u(31) +#define ROSC_FREQB_PASSWD_LSB _u(16) +#define ROSC_FREQB_PASSWD_ACCESS "RW" #define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS7 @@ -174,16 +175,16 @@ // On power-up this field is initialised to WAKE // An invalid write will also select WAKE // Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> DORMANT +// 0x636f6d61 -> dormant // 0x77616b65 -> WAKE -#define ROSC_DORMANT_OFFSET _u(0x0000000c) -#define ROSC_DORMANT_BITS _u(0xffffffff) -#define ROSC_DORMANT_RESET "-" -#define ROSC_DORMANT_MSB _u(31) -#define ROSC_DORMANT_LSB _u(0) -#define ROSC_DORMANT_ACCESS "RW" +#define ROSC_DORMANT_OFFSET _u(0x0000000c) +#define ROSC_DORMANT_BITS _u(0xffffffff) +#define ROSC_DORMANT_RESET "-" +#define ROSC_DORMANT_MSB _u(31) +#define ROSC_DORMANT_LSB _u(0) +#define ROSC_DORMANT_ACCESS "RW" #define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) +#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : ROSC_DIV // Description : Controls the output divider @@ -193,12 +194,12 @@ // any other value sets div=31 // this register resets to div=16 // 0xaa0 -> PASS -#define ROSC_DIV_OFFSET _u(0x00000010) -#define ROSC_DIV_BITS _u(0x00000fff) -#define ROSC_DIV_RESET "-" -#define ROSC_DIV_MSB _u(11) -#define ROSC_DIV_LSB _u(0) -#define ROSC_DIV_ACCESS "RW" +#define ROSC_DIV_OFFSET _u(0x00000010) +#define ROSC_DIV_BITS _u(0x00000fff) +#define ROSC_DIV_RESET "-" +#define ROSC_DIV_MSB _u(11) +#define ROSC_DIV_LSB _u(0) +#define ROSC_DIV_ACCESS "RW" #define ROSC_DIV_VALUE_PASS _u(0xaa0) // ============================================================================= // Register : ROSC_PHASE @@ -309,4 +310,5 @@ #define ROSC_COUNT_LSB _u(0) #define ROSC_COUNT_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_ROSC_DEFINED +#endif // _HARDWARE_REGS_ROSC_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/rtc.h b/src/rp2040/hardware_regs/include/hardware/regs/rtc.h index 7d62c9d73..86d519eb0 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/rtc.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/rtc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Register block to control RTC // ============================================================================= -#ifndef HARDWARE_REGS_RTC_DEFINED -#define HARDWARE_REGS_RTC_DEFINED +#ifndef _HARDWARE_REGS_RTC_H +#define _HARDWARE_REGS_RTC_H // ============================================================================= // Register : RTC_CLKDIV_M1 // Description : Divider minus 1 for the 1 second counter. Safe to change the @@ -136,7 +138,6 @@ #define RTC_IRQ_SETUP_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE -// Description : None #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000) #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29) @@ -346,7 +347,6 @@ #define RTC_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTR_RTC -// Description : None #define RTC_INTR_RTC_RESET _u(0x0) #define RTC_INTR_RTC_BITS _u(0x00000001) #define RTC_INTR_RTC_MSB _u(0) @@ -360,7 +360,6 @@ #define RTC_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTE_RTC -// Description : None #define RTC_INTE_RTC_RESET _u(0x0) #define RTC_INTE_RTC_BITS _u(0x00000001) #define RTC_INTE_RTC_MSB _u(0) @@ -374,7 +373,6 @@ #define RTC_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTF_RTC -// Description : None #define RTC_INTF_RTC_RESET _u(0x0) #define RTC_INTF_RTC_BITS _u(0x00000001) #define RTC_INTF_RTC_MSB _u(0) @@ -388,11 +386,11 @@ #define RTC_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTS_RTC -// Description : None #define RTC_INTS_RTC_RESET _u(0x0) #define RTC_INTS_RTC_BITS _u(0x00000001) #define RTC_INTS_RTC_MSB _u(0) #define RTC_INTS_RTC_LSB _u(0) #define RTC_INTS_RTC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_RTC_DEFINED +#endif // _HARDWARE_REGS_RTC_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sio.h b/src/rp2040/hardware_regs/include/hardware/regs/sio.h index 8d4a4ac6b..2d720e927 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/sio.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/sio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +13,8 @@ // Provides core-local and inter-core hardware for the two // processors, with single-cycle access. // ============================================================================= -#ifndef HARDWARE_REGS_SIO_DEFINED -#define HARDWARE_REGS_SIO_DEFINED +#ifndef _HARDWARE_REGS_SIO_H +#define _HARDWARE_REGS_SIO_H // ============================================================================= // Register : SIO_CPUID // Description : Processor core identifier @@ -440,8 +442,8 @@ // Writing an operand (xDIVIDEND, xDIVISOR) will immediately start // a new calculation, no // matter if one is already in progress. -// Writing to a result register will immediately terminate any -// in-progress calculation +// Writing to a result register will immediately terminate any in- +// progress calculation // and set the READY and DIRTY flags. #define SIO_DIV_CSR_READY_RESET _u(0x1) #define SIO_DIV_CSR_READY_BITS _u(0x00000001) @@ -1653,4 +1655,5 @@ #define SIO_SPINLOCK31_LSB _u(0) #define SIO_SPINLOCK31_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_SIO_DEFINED +#endif // _HARDWARE_REGS_SIO_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/spi.h b/src/rp2040/hardware_regs/include/hardware/regs/spi.h index 816e15024..d9d3b14df 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/spi.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/spi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : SPI // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_SPI_DEFINED -#define HARDWARE_REGS_SPI_DEFINED +#ifndef _HARDWARE_REGS_SPI_H +#define _HARDWARE_REGS_SPI_H // ============================================================================= // Register : SPI_SSPCR0 // Description : Control register 0, SSPCR0 on page 3-4 @@ -518,4 +519,5 @@ #define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) #define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_SPI_DEFINED +#endif // _HARDWARE_REGS_SPI_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/ssi.h b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h index 67fddc0a4..7fe6aa6aa 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/ssi.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/ssi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,8 +71,8 @@ // - Serial clock phase – capture on first edge of serial-clock // directly after reset. // ============================================================================= -#ifndef HARDWARE_REGS_SSI_DEFINED -#define HARDWARE_REGS_SSI_DEFINED +#ifndef _HARDWARE_REGS_SSI_H +#define _HARDWARE_REGS_SSI_H // ============================================================================= // Register : SSI_CTRLR0 // Description : Control register 0 @@ -88,16 +90,15 @@ // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SPI_FRF // Description : SPI frame format -// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, -// full-duplex +// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex // 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex // 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex -#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0) -#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000) -#define SSI_CTRLR0_SPI_FRF_MSB _u(22) -#define SSI_CTRLR0_SPI_FRF_LSB _u(21) -#define SSI_CTRLR0_SPI_FRF_ACCESS "RW" -#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0) +#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0) +#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000) +#define SSI_CTRLR0_SPI_FRF_MSB _u(22) +#define SSI_CTRLR0_SPI_FRF_LSB _u(21) +#define SSI_CTRLR0_SPI_FRF_ACCESS "RW" +#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0) #define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1) #define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2) // ----------------------------------------------------------------------------- @@ -140,16 +141,15 @@ // 0x0 -> Both transmit and receive // 0x1 -> Transmit only (not for FRF == 0, standard SPI mode) // 0x2 -> Receive only (not for FRF == 0, standard SPI mode) -// 0x3 -> EEPROM read mode (TX then RX; RX starts after control -// data TX'd) -#define SSI_CTRLR0_TMOD_RESET _u(0x0) -#define SSI_CTRLR0_TMOD_BITS _u(0x00000300) -#define SSI_CTRLR0_TMOD_MSB _u(9) -#define SSI_CTRLR0_TMOD_LSB _u(8) -#define SSI_CTRLR0_TMOD_ACCESS "RW" -#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0) -#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1) -#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2) +// 0x3 -> EEPROM read mode (TX then RX; RX starts after control data TX'd) +#define SSI_CTRLR0_TMOD_RESET _u(0x0) +#define SSI_CTRLR0_TMOD_BITS _u(0x00000300) +#define SSI_CTRLR0_TMOD_MSB _u(9) +#define SSI_CTRLR0_TMOD_LSB _u(8) +#define SSI_CTRLR0_TMOD_ACCESS "RW" +#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0) +#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1) +#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2) #define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SCPOL @@ -758,15 +758,15 @@ // 0x1 -> 4-bit instruction // 0x2 -> 8-bit instruction // 0x3 -> 16-bit instruction -#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0) -#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300) -#define SSI_SPI_CTRLR0_INST_L_MSB _u(9) -#define SSI_SPI_CTRLR0_INST_L_LSB _u(8) -#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" +#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0) +#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300) +#define SSI_SPI_CTRLR0_INST_L_MSB _u(9) +#define SSI_SPI_CTRLR0_INST_L_LSB _u(8) +#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" #define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0) -#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1) -#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2) -#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3) +#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1) +#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2) +#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_ADDR_L // Description : Address length (0b-60b in 4b increments) @@ -779,15 +779,13 @@ // Field : SSI_SPI_CTRLR0_TRANS_TYPE // Description : Address and instruction transfer format // 0x0 -> Command and address both in standard SPI frame format -// 0x1 -> Command in standard SPI format, address in format -// specified by FRF -// 0x2 -> Command and address both in format specified by FRF -// (e.g. Dual-SPI) -#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) -#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) -#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1) -#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0) -#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" +// 0x1 -> Command in standard SPI format, address in format specified by FRF +// 0x2 -> Command and address both in format specified by FRF (e.g. Dual-SPI) +#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) +#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1) +#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0) #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1) #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2) @@ -806,4 +804,5 @@ #define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0) #define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_SSI_DEFINED +#endif // _HARDWARE_REGS_SSI_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h b/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h index 2bf09e26f..96672bb49 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/syscfg.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Register block for various chip control signals // ============================================================================= -#ifndef HARDWARE_REGS_SYSCFG_DEFINED -#define HARDWARE_REGS_SYSCFG_DEFINED +#ifndef _HARDWARE_REGS_SYSCFG_H +#define _HARDWARE_REGS_SYSCFG_H // ============================================================================= // Register : SYSCFG_PROC0_NMI_MASK // Description : Processor core 0 NMI source mask @@ -191,7 +193,6 @@ #define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_ROM -// Description : None #define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080) #define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7) @@ -199,7 +200,6 @@ #define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_USB -// Description : None #define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040) #define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6) @@ -207,7 +207,6 @@ #define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM5 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) #define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) @@ -215,7 +214,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM4 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) #define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) @@ -223,7 +221,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM3 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) #define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) @@ -231,7 +228,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM2 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) #define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) @@ -239,7 +235,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM1 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) #define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) @@ -247,11 +242,11 @@ #define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM0 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) #define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) #define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) #define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_SYSCFG_DEFINED +#endif // _HARDWARE_REGS_SYSCFG_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h index 2a46658e2..e0cf2efab 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/sysinfo.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : SYSINFO // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_SYSINFO_DEFINED -#define HARDWARE_REGS_SYSINFO_DEFINED +#ifndef _HARDWARE_REGS_SYSINFO_H +#define _HARDWARE_REGS_SYSINFO_H // ============================================================================= // Register : SYSINFO_CHIP_ID // Description : JEDEC JEP-106 compliant chip identifier. @@ -19,7 +20,6 @@ #define SYSINFO_CHIP_ID_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_REVISION -// Description : None #define SYSINFO_CHIP_ID_REVISION_RESET "-" #define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) #define SYSINFO_CHIP_ID_REVISION_MSB _u(31) @@ -27,7 +27,6 @@ #define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_PART -// Description : None #define SYSINFO_CHIP_ID_PART_RESET "-" #define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) #define SYSINFO_CHIP_ID_PART_MSB _u(27) @@ -35,7 +34,6 @@ #define SYSINFO_CHIP_ID_PART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_MANUFACTURER -// Description : None #define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" #define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff) #define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) @@ -50,7 +48,6 @@ #define SYSINFO_PLATFORM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_ASIC -// Description : None #define SYSINFO_PLATFORM_ASIC_RESET _u(0x0) #define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) #define SYSINFO_PLATFORM_ASIC_MSB _u(1) @@ -58,7 +55,6 @@ #define SYSINFO_PLATFORM_ASIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_FPGA -// Description : None #define SYSINFO_PLATFORM_FPGA_RESET _u(0x0) #define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) #define SYSINFO_PLATFORM_FPGA_MSB _u(0) @@ -67,11 +63,12 @@ // ============================================================================= // Register : SYSINFO_GITREF_RP2040 // Description : Git hash of the chip source. Used to identify chip version. -#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040) +#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000010) #define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff) #define SYSINFO_GITREF_RP2040_RESET "-" #define SYSINFO_GITREF_RP2040_MSB _u(31) #define SYSINFO_GITREF_RP2040_LSB _u(0) #define SYSINFO_GITREF_RP2040_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_SYSINFO_DEFINED +#endif // _HARDWARE_REGS_SYSINFO_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/tbman.h b/src/rp2040/hardware_regs/include/hardware/regs/tbman.h index 4f8f64132..49b627c84 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/tbman.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/tbman.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +12,8 @@ // Description : Testbench manager. Allows the programmer to know what // platform their software is running on. // ============================================================================= -#ifndef HARDWARE_REGS_TBMAN_DEFINED -#define HARDWARE_REGS_TBMAN_DEFINED +#ifndef _HARDWARE_REGS_TBMAN_H +#define _HARDWARE_REGS_TBMAN_H // ============================================================================= // Register : TBMAN_PLATFORM // Description : Indicates the type of platform in use @@ -35,4 +37,5 @@ #define TBMAN_PLATFORM_ASIC_LSB _u(0) #define TBMAN_PLATFORM_ASIC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_TBMAN_DEFINED +#endif // _HARDWARE_REGS_TBMAN_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/timer.h b/src/rp2040/hardware_regs/include/hardware/regs/timer.h index c3ef0c5a1..7cdcbb304 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/timer.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/timer.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,8 +27,8 @@ // To clear the interrupt write a 1 to the corresponding // alarm_irq // ============================================================================= -#ifndef HARDWARE_REGS_TIMER_DEFINED -#define HARDWARE_REGS_TIMER_DEFINED +#ifndef _HARDWARE_REGS_TIMER_H +#define _HARDWARE_REGS_TIMER_H // ============================================================================= // Register : TIMER_TIMEHW // Description : Write to bits 63:32 of time @@ -184,7 +186,6 @@ #define TIMER_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_3 -// Description : None #define TIMER_INTR_ALARM_3_RESET _u(0x0) #define TIMER_INTR_ALARM_3_BITS _u(0x00000008) #define TIMER_INTR_ALARM_3_MSB _u(3) @@ -192,7 +193,6 @@ #define TIMER_INTR_ALARM_3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_2 -// Description : None #define TIMER_INTR_ALARM_2_RESET _u(0x0) #define TIMER_INTR_ALARM_2_BITS _u(0x00000004) #define TIMER_INTR_ALARM_2_MSB _u(2) @@ -200,7 +200,6 @@ #define TIMER_INTR_ALARM_2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_1 -// Description : None #define TIMER_INTR_ALARM_1_RESET _u(0x0) #define TIMER_INTR_ALARM_1_BITS _u(0x00000002) #define TIMER_INTR_ALARM_1_MSB _u(1) @@ -208,7 +207,6 @@ #define TIMER_INTR_ALARM_1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_0 -// Description : None #define TIMER_INTR_ALARM_0_RESET _u(0x0) #define TIMER_INTR_ALARM_0_BITS _u(0x00000001) #define TIMER_INTR_ALARM_0_MSB _u(0) @@ -222,7 +220,6 @@ #define TIMER_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_3 -// Description : None #define TIMER_INTE_ALARM_3_RESET _u(0x0) #define TIMER_INTE_ALARM_3_BITS _u(0x00000008) #define TIMER_INTE_ALARM_3_MSB _u(3) @@ -230,7 +227,6 @@ #define TIMER_INTE_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_2 -// Description : None #define TIMER_INTE_ALARM_2_RESET _u(0x0) #define TIMER_INTE_ALARM_2_BITS _u(0x00000004) #define TIMER_INTE_ALARM_2_MSB _u(2) @@ -238,7 +234,6 @@ #define TIMER_INTE_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_1 -// Description : None #define TIMER_INTE_ALARM_1_RESET _u(0x0) #define TIMER_INTE_ALARM_1_BITS _u(0x00000002) #define TIMER_INTE_ALARM_1_MSB _u(1) @@ -246,7 +241,6 @@ #define TIMER_INTE_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_0 -// Description : None #define TIMER_INTE_ALARM_0_RESET _u(0x0) #define TIMER_INTE_ALARM_0_BITS _u(0x00000001) #define TIMER_INTE_ALARM_0_MSB _u(0) @@ -260,7 +254,6 @@ #define TIMER_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_3 -// Description : None #define TIMER_INTF_ALARM_3_RESET _u(0x0) #define TIMER_INTF_ALARM_3_BITS _u(0x00000008) #define TIMER_INTF_ALARM_3_MSB _u(3) @@ -268,7 +261,6 @@ #define TIMER_INTF_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_2 -// Description : None #define TIMER_INTF_ALARM_2_RESET _u(0x0) #define TIMER_INTF_ALARM_2_BITS _u(0x00000004) #define TIMER_INTF_ALARM_2_MSB _u(2) @@ -276,7 +268,6 @@ #define TIMER_INTF_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_1 -// Description : None #define TIMER_INTF_ALARM_1_RESET _u(0x0) #define TIMER_INTF_ALARM_1_BITS _u(0x00000002) #define TIMER_INTF_ALARM_1_MSB _u(1) @@ -284,7 +275,6 @@ #define TIMER_INTF_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_0 -// Description : None #define TIMER_INTF_ALARM_0_RESET _u(0x0) #define TIMER_INTF_ALARM_0_BITS _u(0x00000001) #define TIMER_INTF_ALARM_0_MSB _u(0) @@ -298,7 +288,6 @@ #define TIMER_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_3 -// Description : None #define TIMER_INTS_ALARM_3_RESET _u(0x0) #define TIMER_INTS_ALARM_3_BITS _u(0x00000008) #define TIMER_INTS_ALARM_3_MSB _u(3) @@ -306,7 +295,6 @@ #define TIMER_INTS_ALARM_3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_2 -// Description : None #define TIMER_INTS_ALARM_2_RESET _u(0x0) #define TIMER_INTS_ALARM_2_BITS _u(0x00000004) #define TIMER_INTS_ALARM_2_MSB _u(2) @@ -314,7 +302,6 @@ #define TIMER_INTS_ALARM_2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_1 -// Description : None #define TIMER_INTS_ALARM_1_RESET _u(0x0) #define TIMER_INTS_ALARM_1_BITS _u(0x00000002) #define TIMER_INTS_ALARM_1_MSB _u(1) @@ -322,11 +309,11 @@ #define TIMER_INTS_ALARM_1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_0 -// Description : None #define TIMER_INTS_ALARM_0_RESET _u(0x0) #define TIMER_INTS_ALARM_0_BITS _u(0x00000001) #define TIMER_INTS_ALARM_0_MSB _u(0) #define TIMER_INTS_ALARM_0_LSB _u(0) #define TIMER_INTS_ALARM_0_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_TIMER_DEFINED +#endif // _HARDWARE_REGS_TIMER_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/uart.h b/src/rp2040/hardware_regs/include/hardware/regs/uart.h index 409f59821..0f7f17ec0 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/uart.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/uart.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : UART // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_UART_DEFINED -#define HARDWARE_REGS_UART_DEFINED +#ifndef _HARDWARE_REGS_UART_H +#define _HARDWARE_REGS_UART_H // ============================================================================= // Register : UART_UARTDR // Description : Data Register, UARTDR @@ -1145,4 +1146,5 @@ #define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) #define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_UART_DEFINED +#endif // _HARDWARE_REGS_UART_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb.h b/src/rp2040/hardware_regs/include/hardware/regs/usb.h index 552cd11a8..291f65ee7 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/usb.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/usb.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahbl // Description : USB FS/LS controller device registers // ============================================================================= -#ifndef HARDWARE_REGS_USB_DEFINED -#define HARDWARE_REGS_USB_DEFINED +#ifndef _HARDWARE_REGS_USB_H +#define _HARDWARE_REGS_USB_H // ============================================================================= // Register : USB_ADDR_ENDP // Description : Device address and endpoint control @@ -660,7 +662,6 @@ #define USB_SOF_WR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_WR_COUNT -// Description : None #define USB_SOF_WR_COUNT_RESET _u(0x000) #define USB_SOF_WR_COUNT_BITS _u(0x000007ff) #define USB_SOF_WR_COUNT_MSB _u(10) @@ -676,7 +677,6 @@ #define USB_SOF_RD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_RD_COUNT -// Description : None #define USB_SOF_RD_COUNT_RESET _u(0x000) #define USB_SOF_RD_COUNT_BITS _u(0x000007ff) #define USB_SOF_RD_COUNT_MSB _u(10) @@ -1012,7 +1012,7 @@ #define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) #define USB_SIE_STATUS_CONNECTED_MSB _u(16) #define USB_SIE_STATUS_CONNECTED_LSB _u(16) -#define USB_SIE_STATUS_CONNECTED_ACCESS "WC" +#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_RESUME // Description : Host: Device has initiated a remote resume. Device: host has @@ -1037,7 +1037,7 @@ #define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) #define USB_SIE_STATUS_SPEED_MSB _u(9) #define USB_SIE_STATUS_SPEED_LSB _u(8) -#define USB_SIE_STATUS_SPEED_ACCESS "WC" +#define USB_SIE_STATUS_SPEED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_SUSPENDED // Description : Bus in suspended state. Valid for device and host. Host and @@ -1047,7 +1047,7 @@ #define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) #define USB_SIE_STATUS_SUSPENDED_MSB _u(4) #define USB_SIE_STATUS_SUSPENDED_LSB _u(4) -#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" +#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_SIE_STATUS_LINE_STATE // Description : USB bus line state @@ -1072,7 +1072,7 @@ #define USB_INT_EP_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INT_EP_CTRL_INT_EP_ACTIVE -// Description : Host: Enable interrupt endpoint 1 -> 15 +// Description : Host: Enable interrupt endpoint 1 => 15 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) @@ -1090,7 +1090,6 @@ #define USB_BUFF_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_OUT -// Description : None #define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) #define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) @@ -1098,7 +1097,6 @@ #define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_IN -// Description : None #define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) #define USB_BUFF_STATUS_EP15_IN_MSB _u(30) @@ -1106,7 +1104,6 @@ #define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_OUT -// Description : None #define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) #define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) @@ -1114,7 +1111,6 @@ #define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_IN -// Description : None #define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) #define USB_BUFF_STATUS_EP14_IN_MSB _u(28) @@ -1122,7 +1118,6 @@ #define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_OUT -// Description : None #define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) #define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) @@ -1130,7 +1125,6 @@ #define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_IN -// Description : None #define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) #define USB_BUFF_STATUS_EP13_IN_MSB _u(26) @@ -1138,7 +1132,6 @@ #define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_OUT -// Description : None #define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) #define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) @@ -1146,7 +1139,6 @@ #define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_IN -// Description : None #define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) #define USB_BUFF_STATUS_EP12_IN_MSB _u(24) @@ -1154,7 +1146,6 @@ #define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_OUT -// Description : None #define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) #define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) @@ -1162,7 +1153,6 @@ #define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_IN -// Description : None #define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) #define USB_BUFF_STATUS_EP11_IN_MSB _u(22) @@ -1170,7 +1160,6 @@ #define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_OUT -// Description : None #define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) #define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) @@ -1178,7 +1167,6 @@ #define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_IN -// Description : None #define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) #define USB_BUFF_STATUS_EP10_IN_MSB _u(20) @@ -1186,7 +1174,6 @@ #define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_OUT -// Description : None #define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) #define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) @@ -1194,7 +1181,6 @@ #define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_IN -// Description : None #define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) #define USB_BUFF_STATUS_EP9_IN_MSB _u(18) @@ -1202,7 +1188,6 @@ #define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_OUT -// Description : None #define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) #define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) @@ -1210,7 +1195,6 @@ #define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_IN -// Description : None #define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) #define USB_BUFF_STATUS_EP8_IN_MSB _u(16) @@ -1218,7 +1202,6 @@ #define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_OUT -// Description : None #define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) #define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) @@ -1226,7 +1209,6 @@ #define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_IN -// Description : None #define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) #define USB_BUFF_STATUS_EP7_IN_MSB _u(14) @@ -1234,7 +1216,6 @@ #define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_OUT -// Description : None #define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) #define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) @@ -1242,7 +1223,6 @@ #define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_IN -// Description : None #define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) #define USB_BUFF_STATUS_EP6_IN_MSB _u(12) @@ -1250,7 +1230,6 @@ #define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_OUT -// Description : None #define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) #define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) @@ -1258,7 +1237,6 @@ #define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_IN -// Description : None #define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) #define USB_BUFF_STATUS_EP5_IN_MSB _u(10) @@ -1266,7 +1244,6 @@ #define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_OUT -// Description : None #define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) #define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) @@ -1274,7 +1251,6 @@ #define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_IN -// Description : None #define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) #define USB_BUFF_STATUS_EP4_IN_MSB _u(8) @@ -1282,7 +1258,6 @@ #define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_OUT -// Description : None #define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) #define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) @@ -1290,7 +1265,6 @@ #define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_IN -// Description : None #define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) #define USB_BUFF_STATUS_EP3_IN_MSB _u(6) @@ -1298,7 +1272,6 @@ #define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_OUT -// Description : None #define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) #define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) @@ -1306,7 +1279,6 @@ #define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_IN -// Description : None #define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) #define USB_BUFF_STATUS_EP2_IN_MSB _u(4) @@ -1314,7 +1286,6 @@ #define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_OUT -// Description : None #define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) #define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) @@ -1322,7 +1293,6 @@ #define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_IN -// Description : None #define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) #define USB_BUFF_STATUS_EP1_IN_MSB _u(2) @@ -1330,7 +1300,6 @@ #define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_OUT -// Description : None #define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) #define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) @@ -1338,7 +1307,6 @@ #define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_IN -// Description : None #define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) #define USB_BUFF_STATUS_EP0_IN_MSB _u(0) @@ -1355,7 +1323,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) @@ -1363,7 +1330,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) @@ -1371,7 +1337,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) @@ -1379,7 +1344,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) @@ -1387,7 +1351,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) @@ -1395,7 +1358,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) @@ -1403,7 +1365,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) @@ -1411,7 +1372,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) @@ -1419,7 +1379,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) @@ -1427,7 +1386,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) @@ -1435,7 +1393,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) @@ -1443,7 +1400,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) @@ -1451,7 +1407,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) @@ -1459,7 +1414,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) @@ -1467,7 +1421,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) @@ -1475,7 +1428,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) @@ -1483,7 +1435,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) @@ -1491,7 +1442,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) @@ -1499,7 +1449,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) @@ -1507,7 +1456,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) @@ -1515,7 +1463,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) @@ -1523,7 +1470,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) @@ -1531,7 +1477,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) @@ -1539,7 +1484,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) @@ -1547,7 +1491,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) @@ -1555,7 +1498,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) @@ -1563,7 +1505,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) @@ -1571,7 +1512,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) @@ -1579,7 +1519,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) @@ -1587,7 +1526,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) @@ -1595,7 +1533,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) @@ -1603,7 +1540,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) @@ -1621,7 +1557,6 @@ #define USB_EP_ABORT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_OUT -// Description : None #define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) #define USB_EP_ABORT_EP15_OUT_MSB _u(31) @@ -1629,7 +1564,6 @@ #define USB_EP_ABORT_EP15_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_IN -// Description : None #define USB_EP_ABORT_EP15_IN_RESET _u(0x0) #define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) #define USB_EP_ABORT_EP15_IN_MSB _u(30) @@ -1637,7 +1571,6 @@ #define USB_EP_ABORT_EP15_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_OUT -// Description : None #define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) #define USB_EP_ABORT_EP14_OUT_MSB _u(29) @@ -1645,7 +1578,6 @@ #define USB_EP_ABORT_EP14_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_IN -// Description : None #define USB_EP_ABORT_EP14_IN_RESET _u(0x0) #define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) #define USB_EP_ABORT_EP14_IN_MSB _u(28) @@ -1653,7 +1585,6 @@ #define USB_EP_ABORT_EP14_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_OUT -// Description : None #define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) #define USB_EP_ABORT_EP13_OUT_MSB _u(27) @@ -1661,7 +1592,6 @@ #define USB_EP_ABORT_EP13_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_IN -// Description : None #define USB_EP_ABORT_EP13_IN_RESET _u(0x0) #define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) #define USB_EP_ABORT_EP13_IN_MSB _u(26) @@ -1669,7 +1599,6 @@ #define USB_EP_ABORT_EP13_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_OUT -// Description : None #define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) #define USB_EP_ABORT_EP12_OUT_MSB _u(25) @@ -1677,7 +1606,6 @@ #define USB_EP_ABORT_EP12_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_IN -// Description : None #define USB_EP_ABORT_EP12_IN_RESET _u(0x0) #define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) #define USB_EP_ABORT_EP12_IN_MSB _u(24) @@ -1685,7 +1613,6 @@ #define USB_EP_ABORT_EP12_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_OUT -// Description : None #define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) #define USB_EP_ABORT_EP11_OUT_MSB _u(23) @@ -1693,7 +1620,6 @@ #define USB_EP_ABORT_EP11_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_IN -// Description : None #define USB_EP_ABORT_EP11_IN_RESET _u(0x0) #define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) #define USB_EP_ABORT_EP11_IN_MSB _u(22) @@ -1701,7 +1627,6 @@ #define USB_EP_ABORT_EP11_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_OUT -// Description : None #define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) #define USB_EP_ABORT_EP10_OUT_MSB _u(21) @@ -1709,7 +1634,6 @@ #define USB_EP_ABORT_EP10_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_IN -// Description : None #define USB_EP_ABORT_EP10_IN_RESET _u(0x0) #define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) #define USB_EP_ABORT_EP10_IN_MSB _u(20) @@ -1717,7 +1641,6 @@ #define USB_EP_ABORT_EP10_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_OUT -// Description : None #define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) #define USB_EP_ABORT_EP9_OUT_MSB _u(19) @@ -1725,7 +1648,6 @@ #define USB_EP_ABORT_EP9_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_IN -// Description : None #define USB_EP_ABORT_EP9_IN_RESET _u(0x0) #define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) #define USB_EP_ABORT_EP9_IN_MSB _u(18) @@ -1733,7 +1655,6 @@ #define USB_EP_ABORT_EP9_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_OUT -// Description : None #define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) #define USB_EP_ABORT_EP8_OUT_MSB _u(17) @@ -1741,7 +1662,6 @@ #define USB_EP_ABORT_EP8_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_IN -// Description : None #define USB_EP_ABORT_EP8_IN_RESET _u(0x0) #define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) #define USB_EP_ABORT_EP8_IN_MSB _u(16) @@ -1749,7 +1669,6 @@ #define USB_EP_ABORT_EP8_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_OUT -// Description : None #define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) #define USB_EP_ABORT_EP7_OUT_MSB _u(15) @@ -1757,7 +1676,6 @@ #define USB_EP_ABORT_EP7_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_IN -// Description : None #define USB_EP_ABORT_EP7_IN_RESET _u(0x0) #define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) #define USB_EP_ABORT_EP7_IN_MSB _u(14) @@ -1765,7 +1683,6 @@ #define USB_EP_ABORT_EP7_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_OUT -// Description : None #define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) #define USB_EP_ABORT_EP6_OUT_MSB _u(13) @@ -1773,7 +1690,6 @@ #define USB_EP_ABORT_EP6_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_IN -// Description : None #define USB_EP_ABORT_EP6_IN_RESET _u(0x0) #define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) #define USB_EP_ABORT_EP6_IN_MSB _u(12) @@ -1781,7 +1697,6 @@ #define USB_EP_ABORT_EP6_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_OUT -// Description : None #define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) #define USB_EP_ABORT_EP5_OUT_MSB _u(11) @@ -1789,7 +1704,6 @@ #define USB_EP_ABORT_EP5_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_IN -// Description : None #define USB_EP_ABORT_EP5_IN_RESET _u(0x0) #define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) #define USB_EP_ABORT_EP5_IN_MSB _u(10) @@ -1797,7 +1711,6 @@ #define USB_EP_ABORT_EP5_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_OUT -// Description : None #define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) #define USB_EP_ABORT_EP4_OUT_MSB _u(9) @@ -1805,7 +1718,6 @@ #define USB_EP_ABORT_EP4_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_IN -// Description : None #define USB_EP_ABORT_EP4_IN_RESET _u(0x0) #define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) #define USB_EP_ABORT_EP4_IN_MSB _u(8) @@ -1813,7 +1725,6 @@ #define USB_EP_ABORT_EP4_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_OUT -// Description : None #define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) #define USB_EP_ABORT_EP3_OUT_MSB _u(7) @@ -1821,7 +1732,6 @@ #define USB_EP_ABORT_EP3_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_IN -// Description : None #define USB_EP_ABORT_EP3_IN_RESET _u(0x0) #define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) #define USB_EP_ABORT_EP3_IN_MSB _u(6) @@ -1829,7 +1739,6 @@ #define USB_EP_ABORT_EP3_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_OUT -// Description : None #define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) #define USB_EP_ABORT_EP2_OUT_MSB _u(5) @@ -1837,7 +1746,6 @@ #define USB_EP_ABORT_EP2_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_IN -// Description : None #define USB_EP_ABORT_EP2_IN_RESET _u(0x0) #define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) #define USB_EP_ABORT_EP2_IN_MSB _u(4) @@ -1845,7 +1753,6 @@ #define USB_EP_ABORT_EP2_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_OUT -// Description : None #define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) #define USB_EP_ABORT_EP1_OUT_MSB _u(3) @@ -1853,7 +1760,6 @@ #define USB_EP_ABORT_EP1_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_IN -// Description : None #define USB_EP_ABORT_EP1_IN_RESET _u(0x0) #define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) #define USB_EP_ABORT_EP1_IN_MSB _u(2) @@ -1861,7 +1767,6 @@ #define USB_EP_ABORT_EP1_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_OUT -// Description : None #define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) #define USB_EP_ABORT_EP0_OUT_MSB _u(1) @@ -1869,7 +1774,6 @@ #define USB_EP_ABORT_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_IN -// Description : None #define USB_EP_ABORT_EP0_IN_RESET _u(0x0) #define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) #define USB_EP_ABORT_EP0_IN_MSB _u(0) @@ -1885,7 +1789,6 @@ #define USB_EP_ABORT_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_OUT -// Description : None #define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) #define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) @@ -1893,7 +1796,6 @@ #define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_IN -// Description : None #define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) #define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) @@ -1901,7 +1803,6 @@ #define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_OUT -// Description : None #define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) #define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) @@ -1909,7 +1810,6 @@ #define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_IN -// Description : None #define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) #define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) @@ -1917,7 +1817,6 @@ #define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_OUT -// Description : None #define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) #define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) @@ -1925,7 +1824,6 @@ #define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_IN -// Description : None #define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) #define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) @@ -1933,7 +1831,6 @@ #define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_OUT -// Description : None #define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) #define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) @@ -1941,7 +1838,6 @@ #define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_IN -// Description : None #define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) #define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) @@ -1949,7 +1845,6 @@ #define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_OUT -// Description : None #define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) #define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) @@ -1957,7 +1852,6 @@ #define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_IN -// Description : None #define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) #define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) @@ -1965,7 +1859,6 @@ #define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_OUT -// Description : None #define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) #define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) @@ -1973,7 +1866,6 @@ #define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_IN -// Description : None #define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) #define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) @@ -1981,7 +1873,6 @@ #define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_OUT -// Description : None #define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) #define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) @@ -1989,7 +1880,6 @@ #define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_IN -// Description : None #define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) #define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) @@ -1997,7 +1887,6 @@ #define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_OUT -// Description : None #define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) #define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) @@ -2005,7 +1894,6 @@ #define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_IN -// Description : None #define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) #define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) @@ -2013,7 +1901,6 @@ #define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_OUT -// Description : None #define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) #define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) @@ -2021,7 +1908,6 @@ #define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_IN -// Description : None #define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) #define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) @@ -2029,7 +1915,6 @@ #define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_OUT -// Description : None #define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) #define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) @@ -2037,7 +1922,6 @@ #define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_IN -// Description : None #define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) #define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) @@ -2045,7 +1929,6 @@ #define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_OUT -// Description : None #define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) #define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) @@ -2053,7 +1936,6 @@ #define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_IN -// Description : None #define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) #define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) @@ -2061,7 +1943,6 @@ #define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_OUT -// Description : None #define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) #define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) @@ -2069,7 +1950,6 @@ #define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_IN -// Description : None #define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) #define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) @@ -2077,7 +1957,6 @@ #define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_OUT -// Description : None #define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) #define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) @@ -2085,7 +1964,6 @@ #define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_IN -// Description : None #define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) #define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) @@ -2093,7 +1971,6 @@ #define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_OUT -// Description : None #define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) #define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) @@ -2101,7 +1978,6 @@ #define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_IN -// Description : None #define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) #define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) @@ -2109,7 +1985,6 @@ #define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_OUT -// Description : None #define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) #define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) @@ -2117,7 +1992,6 @@ #define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_IN -// Description : None #define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) #define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) @@ -2125,7 +1999,6 @@ #define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_OUT -// Description : None #define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) #define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) @@ -2133,7 +2006,6 @@ #define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_IN -// Description : None #define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) #define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) @@ -2151,7 +2023,6 @@ #define USB_EP_STALL_ARM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_OUT -// Description : None #define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) #define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) #define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) @@ -2159,7 +2030,6 @@ #define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_IN -// Description : None #define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) #define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) #define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) @@ -2198,7 +2068,6 @@ #define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) #define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) @@ -2206,7 +2075,6 @@ #define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) #define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) @@ -2214,7 +2082,6 @@ #define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) #define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) @@ -2222,7 +2089,6 @@ #define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) #define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) @@ -2230,7 +2096,6 @@ #define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) #define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) @@ -2238,7 +2103,6 @@ #define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) #define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) @@ -2246,7 +2110,6 @@ #define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) #define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) @@ -2254,7 +2117,6 @@ #define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) #define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) @@ -2262,7 +2124,6 @@ #define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) #define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) @@ -2270,7 +2131,6 @@ #define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) #define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) @@ -2278,7 +2138,6 @@ #define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) #define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) @@ -2286,7 +2145,6 @@ #define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) #define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) @@ -2294,7 +2152,6 @@ #define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) #define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) @@ -2302,7 +2159,6 @@ #define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) #define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) @@ -2310,7 +2166,6 @@ #define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) #define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) @@ -2318,7 +2173,6 @@ #define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) #define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) @@ -2326,7 +2180,6 @@ #define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) #define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) @@ -2334,7 +2187,6 @@ #define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) #define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) @@ -2342,7 +2194,6 @@ #define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) #define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) @@ -2350,7 +2201,6 @@ #define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) #define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) @@ -2358,7 +2208,6 @@ #define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) #define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) @@ -2366,7 +2215,6 @@ #define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) #define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) @@ -2374,7 +2222,6 @@ #define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) #define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) @@ -2382,7 +2229,6 @@ #define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) #define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) @@ -2390,7 +2236,6 @@ #define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) #define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) @@ -2398,7 +2243,6 @@ #define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) #define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) @@ -2406,7 +2250,6 @@ #define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) #define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) @@ -2414,7 +2257,6 @@ #define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) #define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) @@ -2422,7 +2264,6 @@ #define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) #define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) @@ -2430,7 +2271,6 @@ #define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) #define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) @@ -2438,7 +2278,6 @@ #define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) #define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) @@ -2446,7 +2285,6 @@ #define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) #define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) @@ -2461,7 +2299,6 @@ #define USB_USB_MUXING_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_SOFTCON -// Description : None #define USB_USB_MUXING_SOFTCON_RESET _u(0x0) #define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) #define USB_USB_MUXING_SOFTCON_MSB _u(3) @@ -2469,7 +2306,6 @@ #define USB_USB_MUXING_SOFTCON_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_DIGITAL_PAD -// Description : None #define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) #define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) #define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) @@ -2477,7 +2313,6 @@ #define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_EXTPHY -// Description : None #define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) #define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) #define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) @@ -2485,7 +2320,6 @@ #define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_PHY -// Description : None #define USB_USB_MUXING_TO_PHY_RESET _u(0x0) #define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) #define USB_USB_MUXING_TO_PHY_MSB _u(0) @@ -2495,14 +2329,13 @@ // Register : USB_USB_PWR // Description : Overrides for the power signals in the event that the VBUS // signals are not hooked up to GPIO. Set the value of the -// override and then the override enable to switch over to the +// override and then the override enable so switch over to the // override value. #define USB_USB_PWR_OFFSET _u(0x00000078) #define USB_USB_PWR_BITS _u(0x0000003f) #define USB_USB_PWR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT_EN -// Description : None #define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) #define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) #define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) @@ -2510,7 +2343,6 @@ #define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT -// Description : None #define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) #define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) #define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) @@ -2518,7 +2350,6 @@ #define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN -// Description : None #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) @@ -2526,7 +2357,6 @@ #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT -// Description : None #define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) #define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) #define USB_USB_PWR_VBUS_DETECT_MSB _u(2) @@ -2534,7 +2364,6 @@ #define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN -// Description : None #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) @@ -2542,7 +2371,6 @@ #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN -// Description : None #define USB_USB_PWR_VBUS_EN_RESET _u(0x0) #define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) #define USB_USB_PWR_VBUS_EN_MSB _u(0) @@ -2550,15 +2378,17 @@ #define USB_USB_PWR_VBUS_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT -// Description : This register allows for direct control of the USB phy. Use in -// conjunction with usbphy_direct_override register to enable each -// override bit. +// Description : Note that most functions are driven directly from usb_fsls +// controller. This register allows more detailed control/status +// from the USB PHY. Useful for debug but not expected to be used +// in normal operation +// Use in conjunction with usbphy_direct_override register #define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) #define USB_USBPHY_DIRECT_BITS _u(0x007fff77) #define USB_USBPHY_DIRECT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVV -// Description : DM over voltage +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) #define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) @@ -2566,7 +2396,7 @@ #define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVV -// Description : DP over voltage +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) #define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) @@ -2574,7 +2404,7 @@ #define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVCN -// Description : DM overcurrent +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) #define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) @@ -2582,7 +2412,7 @@ #define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVCN -// Description : DP overcurrent +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) #define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) @@ -2590,7 +2420,8 @@ #define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DM -// Description : DPM pin state +// Description : Status bit from USB PHY +// DPM pin state #define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) #define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) @@ -2598,7 +2429,8 @@ #define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DP -// Description : DPP pin state +// Description : Status bit from USB PHY +// DPP pin state #define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) #define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) @@ -2606,7 +2438,8 @@ #define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DD -// Description : Differential RX +// Description : Status bit from USB PHY +// RX Diff data #define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) #define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) @@ -2614,9 +2447,6 @@ #define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DIFFMODE -// Description : TX_DIFFMODE=0: Single ended mode -// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE -// ignored) #define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) #define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) @@ -2624,8 +2454,6 @@ #define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_FSSLEW -// Description : TX_FSSLEW=0: Low speed slew rate -// TX_FSSLEW=1: Full speed slew rate #define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) #define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) @@ -2633,8 +2461,6 @@ #define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_PD -// Description : TX power down override (if override enable is set). 1 = powered -// down. #define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) #define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) @@ -2642,8 +2468,6 @@ #define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_PD -// Description : RX power down override (if override enable is set). 1 = powered -// down. #define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) #define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) @@ -2651,8 +2475,11 @@ #define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM -// Description : Output data. TX_DIFFMODE=1, Ignored -// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, Ignored +// TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. // DPM=TX_DM #define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) @@ -2661,9 +2488,12 @@ #define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP -// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. -// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP -// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable +// drive. DPP=TX_DP, DPM=~TX_DP +// TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. // DPP=TX_DP #define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) @@ -2672,9 +2502,12 @@ #define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM_OE -// Description : Output enable. If TX_DIFFMODE=1, Ignored. -// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - -// DPM driving +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, Ignored. +// TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM +// driving #define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) #define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) @@ -2682,10 +2515,13 @@ #define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP_OE -// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - -// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving -// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - -// DPP driving +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z +// state; 1 - DPP/DPM driving +// TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP +// driving #define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) #define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) @@ -2693,7 +2529,10 @@ #define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLDN_EN -// Description : DM pull down enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// 1 - Enable Rpd on DPM #define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) @@ -2701,7 +2540,10 @@ #define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_EN -// Description : DM pull up enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// 1 - Enable Rpu on DPM #define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) @@ -2709,8 +2551,8 @@ #define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL -// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - -// Pull = Rpu1 + Rpu2 +// Description : when dm_pullup_en is set high, this enables second resistor. 0 +// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) @@ -2718,7 +2560,10 @@ #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLDN_EN -// Description : DP pull down enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// 1 - Enable Rpd on DPP #define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) @@ -2726,7 +2571,9 @@ #define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_EN -// Description : DP pull up enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller #define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) @@ -2734,8 +2581,8 @@ #define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL -// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - -// Pull = Rpu1 + Rpu2 +// Description : when dp_pullup_en is set high, this enables second resistor. 0 +// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) @@ -2743,13 +2590,11 @@ #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT_OVERRIDE -// Description : Override enable for each control in usbphy_direct #define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) #define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff) #define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) @@ -2757,7 +2602,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) @@ -2765,7 +2609,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) @@ -2773,7 +2616,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) @@ -2781,7 +2623,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) @@ -2789,7 +2630,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) @@ -2797,7 +2639,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) @@ -2805,7 +2648,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) @@ -2813,7 +2657,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) @@ -2821,7 +2666,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) @@ -2829,7 +2675,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) @@ -2837,7 +2684,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) @@ -2845,7 +2693,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) @@ -2853,7 +2700,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) @@ -2861,7 +2707,10 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_TRIM -// Description : Used to adjust trim values of USB phy pull down resistors. +// Description : Note that most functions are driven directly from usb_fsls +// controller. This register allows more detailed control/status +// from the USB PHY. Useful for debug but not expected to be used +// in normal operation #define USB_USBPHY_TRIM_OFFSET _u(0x00000084) #define USB_USBPHY_TRIM_BITS _u(0x00001f1f) #define USB_USBPHY_TRIM_RESET _u(0x00001f1f) @@ -2931,7 +2780,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -2965,7 +2814,7 @@ #define USB_INTR_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTR_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED +// Description : Source: SIE_STATUS.VBUS_DETECT #define USB_INTR_VBUS_DETECT_RESET _u(0x0) #define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTR_VBUS_DETECT_MSB _u(11) @@ -3049,7 +2898,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTR_HOST_RESUME_RESET _u(0x0) #define USB_INTR_HOST_RESUME_BITS _u(0x00000002) #define USB_INTR_HOST_RESUME_MSB _u(1) @@ -3109,7 +2958,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3143,7 +2992,7 @@ #define USB_INTE_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTE_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED +// Description : Source: SIE_STATUS.VBUS_DETECT #define USB_INTE_VBUS_DETECT_RESET _u(0x0) #define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTE_VBUS_DETECT_MSB _u(11) @@ -3227,7 +3076,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTE_HOST_RESUME_RESET _u(0x0) #define USB_INTE_HOST_RESUME_BITS _u(0x00000002) #define USB_INTE_HOST_RESUME_MSB _u(1) @@ -3287,7 +3136,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3321,7 +3170,7 @@ #define USB_INTF_BUS_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_INTF_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED +// Description : Source: SIE_STATUS.VBUS_DETECT #define USB_INTF_VBUS_DETECT_RESET _u(0x0) #define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTF_VBUS_DETECT_MSB _u(11) @@ -3405,7 +3254,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTF_HOST_RESUME_RESET _u(0x0) #define USB_INTF_HOST_RESUME_BITS _u(0x00000002) #define USB_INTF_HOST_RESUME_MSB _u(1) @@ -3465,7 +3314,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3499,7 +3348,7 @@ #define USB_INTS_BUS_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_INTS_VBUS_DETECT -// Description : Source: SIE_STATUS.VBUS_DETECTED +// Description : Source: SIE_STATUS.VBUS_DETECT #define USB_INTS_VBUS_DETECT_RESET _u(0x0) #define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) #define USB_INTS_VBUS_DETECT_MSB _u(11) @@ -3583,7 +3432,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTS_HOST_RESUME_RESET _u(0x0) #define USB_INTS_HOST_RESUME_BITS _u(0x00000002) #define USB_INTS_HOST_RESUME_MSB _u(1) @@ -3600,4 +3449,5 @@ #define USB_INTS_HOST_CONN_DIS_LSB _u(0) #define USB_INTS_HOST_CONN_DIS_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_USB_DEFINED +#endif // _HARDWARE_REGS_USB_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h index fe65ffb1f..d3a5ad32e 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/usb_device_dpram.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahbl // Description : DPRAM layout for USB device. // ============================================================================= -#ifndef HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED -#define HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +#ifndef _HARDWARE_REGS_USB_DEVICE_DPRAM_H +#define _HARDWARE_REGS_USB_DEVICE_DPRAM_H // ============================================================================= // Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW // Description : Bytes 0-3 of the SETUP packet from the host. @@ -19,7 +21,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) @@ -27,7 +28,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) @@ -35,7 +35,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) @@ -49,7 +48,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) @@ -57,7 +55,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) @@ -65,7 +62,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) @@ -105,19 +101,19 @@ #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -146,7 +142,6 @@ #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) @@ -186,19 +181,19 @@ #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -227,7 +222,6 @@ #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) @@ -267,19 +261,19 @@ #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -308,7 +302,6 @@ #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) @@ -348,19 +341,19 @@ #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -389,7 +382,6 @@ #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) @@ -429,19 +421,19 @@ #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -470,7 +462,6 @@ #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) @@ -510,19 +501,19 @@ #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -551,7 +542,6 @@ #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) @@ -591,19 +581,19 @@ #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -632,7 +622,6 @@ #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) @@ -672,19 +661,19 @@ #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -713,7 +702,6 @@ #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) @@ -753,19 +741,19 @@ #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -794,7 +782,6 @@ #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) @@ -834,19 +821,19 @@ #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -875,7 +862,6 @@ #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) @@ -915,19 +901,19 @@ #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -956,7 +942,6 @@ #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) @@ -996,19 +981,19 @@ #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1037,7 +1022,6 @@ #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) @@ -1077,19 +1061,19 @@ #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1118,7 +1102,6 @@ #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) @@ -1158,19 +1141,19 @@ #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1199,7 +1182,6 @@ #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) @@ -1239,19 +1221,19 @@ #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1280,7 +1262,6 @@ #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) @@ -1320,19 +1301,19 @@ #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1361,7 +1342,6 @@ #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) @@ -1401,19 +1381,19 @@ #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1442,7 +1422,6 @@ #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) @@ -1482,19 +1461,19 @@ #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1523,7 +1502,6 @@ #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) @@ -1563,19 +1541,19 @@ #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1604,7 +1582,6 @@ #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) @@ -1644,19 +1621,19 @@ #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1685,7 +1662,6 @@ #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) @@ -1725,19 +1701,19 @@ #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1766,7 +1742,6 @@ #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) @@ -1806,19 +1781,19 @@ #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1847,7 +1822,6 @@ #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) @@ -1887,19 +1861,19 @@ #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1928,7 +1902,6 @@ #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) @@ -1968,19 +1941,19 @@ #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2009,7 +1982,6 @@ #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) @@ -2049,19 +2021,19 @@ #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2090,7 +2062,6 @@ #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) @@ -2130,19 +2101,19 @@ #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2171,7 +2142,6 @@ #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) @@ -2211,19 +2181,19 @@ #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2252,7 +2222,6 @@ #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) @@ -2292,19 +2261,19 @@ #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2333,7 +2302,6 @@ #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) @@ -2373,19 +2341,19 @@ #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2414,7 +2382,6 @@ #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) @@ -2454,19 +2421,19 @@ #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2539,14 +2506,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -2664,8 +2631,7 @@ #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -2674,14 +2640,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -2808,14 +2774,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -2933,8 +2899,7 @@ #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -2943,14 +2908,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3077,14 +3042,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -3202,8 +3167,7 @@ #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -3212,14 +3176,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3346,14 +3310,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -3471,8 +3435,7 @@ #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -3481,14 +3444,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3615,14 +3578,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -3740,8 +3703,7 @@ #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -3750,14 +3712,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3884,14 +3846,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4009,8 +3971,7 @@ #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4019,14 +3980,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4153,14 +4114,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4278,8 +4239,7 @@ #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4288,14 +4248,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4422,14 +4382,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4547,8 +4507,7 @@ #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4557,14 +4516,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4691,14 +4650,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4816,8 +4775,7 @@ #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4826,14 +4784,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4960,14 +4918,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5085,8 +5043,7 @@ #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5095,14 +5052,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -5220,8 +5177,7 @@ #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5230,14 +5186,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5355,8 +5311,7 @@ #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5365,14 +5320,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -5490,8 +5445,7 @@ #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5500,14 +5454,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5625,8 +5579,7 @@ #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5635,14 +5588,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -5760,8 +5713,7 @@ #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5770,14 +5722,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5895,8 +5847,7 @@ #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5905,14 +5856,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6030,8 +5981,7 @@ #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6040,14 +5990,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -6165,8 +6115,7 @@ #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6175,14 +6124,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6300,8 +6249,7 @@ #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6310,14 +6258,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -6435,8 +6383,7 @@ #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6445,14 +6392,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6570,8 +6517,7 @@ #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6580,14 +6526,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -6705,8 +6651,7 @@ #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6715,14 +6660,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6804,4 +6749,5 @@ #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +#endif // _HARDWARE_REGS_USB_DEVICE_DPRAM_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h b/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h index 356ff568a..da61c01f1 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/vreg_and_chip_reset.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +12,8 @@ // Description : control and status for on-chip voltage regulator and chip // level reset subsystem // ============================================================================= -#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED -#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +#ifndef _HARDWARE_REGS_VREG_AND_CHIP_RESET_H +#define _HARDWARE_REGS_VREG_AND_CHIP_RESET_H // ============================================================================= // Register : VREG_AND_CHIP_RESET_VREG // Description : Voltage regulator control and status @@ -148,4 +150,5 @@ #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +#endif // _HARDWARE_REGS_VREG_AND_CHIP_RESET_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h b/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h index 6a9853d40..9c941aede 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/watchdog.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : WATCHDOG // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_WATCHDOG_DEFINED -#define HARDWARE_REGS_WATCHDOG_DEFINED +#ifndef _HARDWARE_REGS_WATCHDOG_H +#define _HARDWARE_REGS_WATCHDOG_H // ============================================================================= // Register : WATCHDOG_CTRL // Description : Watchdog control @@ -89,7 +90,6 @@ #define WATCHDOG_REASON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_FORCE -// Description : None #define WATCHDOG_REASON_FORCE_RESET _u(0x0) #define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) #define WATCHDOG_REASON_FORCE_MSB _u(1) @@ -97,7 +97,6 @@ #define WATCHDOG_REASON_FORCE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_TIMER -// Description : None #define WATCHDOG_REASON_TIMER_RESET _u(0x0) #define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) #define WATCHDOG_REASON_TIMER_MSB _u(0) @@ -223,4 +222,5 @@ #define WATCHDOG_TICK_CYCLES_LSB _u(0) #define WATCHDOG_TICK_CYCLES_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_WATCHDOG_DEFINED +#endif // _HARDWARE_REGS_WATCHDOG_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xip.h b/src/rp2040/hardware_regs/include/hardware/regs/xip.h index 3964f6745..e163f36d5 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/xip.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/xip.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahb // Description : QSPI flash execute-in-place block // ============================================================================= -#ifndef HARDWARE_REGS_XIP_DEFINED -#define HARDWARE_REGS_XIP_DEFINED +#ifndef _HARDWARE_REGS_XIP_H +#define _HARDWARE_REGS_XIP_H // ============================================================================= // Register : XIP_CTRL // Description : Cache control @@ -159,8 +161,8 @@ // a linear data block from flash to the streaming FIFO. // Decrements automatically (1 at a time) as the stream // progresses, and halts on reaching 0. -// Write 0 to halt an in-progress stream, and discard any -// in-flight +// Write 0 to halt an in-progress stream, and discard any in- +// flight // read, so that a new stream can immediately be started (after // draining the FIFO and reinitialising STREAM_ADDR) #define XIP_STREAM_CTR_OFFSET _u(0x00000018) @@ -184,4 +186,5 @@ #define XIP_STREAM_FIFO_LSB _u(0) #define XIP_STREAM_FIFO_ACCESS "RF" // ============================================================================= -#endif // HARDWARE_REGS_XIP_DEFINED +#endif // _HARDWARE_REGS_XIP_H + diff --git a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h index ec84d3d90..8076a99d4 100644 --- a/src/rp2040/hardware_regs/include/hardware/regs/xosc.h +++ b/src/rp2040/hardware_regs/include/hardware/regs/xosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Controls the crystal oscillator // ============================================================================= -#ifndef HARDWARE_REGS_XOSC_DEFINED -#define HARDWARE_REGS_XOSC_DEFINED +#ifndef _HARDWARE_REGS_XOSC_H +#define _HARDWARE_REGS_XOSC_H // ============================================================================= // Register : XOSC_CTRL // Description : Crystal Oscillator Control @@ -22,34 +24,36 @@ // Description : On power-up this field is initialised to DISABLE and the chip // runs from the ROSC. // If the chip has subsequently been programmed to run from the -// XOSC then setting this field to DISABLE may lock-up the chip. -// If this is a concern then run the clk_ref from the ROSC and -// enable the clk_sys RESUS feature. +// XOSC then DISABLE may lock-up the chip. If this is a concern +// then run the clk_ref from the ROSC and enable the clk_sys RESUS +// feature. // The 12-bit code is intended to give some protection against // accidental writes. An invalid setting will enable the // oscillator. // 0xd1e -> DISABLE // 0xfab -> ENABLE -#define XOSC_CTRL_ENABLE_RESET "-" -#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define XOSC_CTRL_ENABLE_MSB _u(23) -#define XOSC_CTRL_ENABLE_LSB _u(12) -#define XOSC_CTRL_ENABLE_ACCESS "RW" +#define XOSC_CTRL_ENABLE_RESET "-" +#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define XOSC_CTRL_ENABLE_MSB _u(23) +#define XOSC_CTRL_ENABLE_LSB _u(12) +#define XOSC_CTRL_ENABLE_ACCESS "RW" #define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : XOSC_CTRL_FREQ_RANGE -// Description : Frequency range. This resets to 0xAA0 and cannot be changed. +// Description : Frequency range. An invalid setting will retain the previous +// value. The actual value being used can be read from +// STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. // 0xaa0 -> 1_15MHZ // 0xaa1 -> RESERVED_1 // 0xaa2 -> RESERVED_2 // 0xaa3 -> RESERVED_3 -#define XOSC_CTRL_FREQ_RANGE_RESET "-" -#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) -#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) -#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) +#define XOSC_CTRL_FREQ_RANGE_RESET "-" +#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) +#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) +#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1) #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2) #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3) @@ -92,12 +96,12 @@ // 0x1 -> RESERVED_1 // 0x2 -> RESERVED_2 // 0x3 -> RESERVED_3 -#define XOSC_STATUS_FREQ_RANGE_RESET "-" -#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) -#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) -#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) -#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" -#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) +#define XOSC_STATUS_FREQ_RANGE_RESET "-" +#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) +#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) +#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) +#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1) #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2) #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3) @@ -107,29 +111,29 @@ // This is used to save power by pausing the XOSC // On power-up this field is initialised to WAKE // An invalid write will also select WAKE -// WARNING: stop the PLLs before selecting dormant mode -// WARNING: setup the irq before selecting dormant mode -// 0x636f6d61 -> DORMANT +// Warning: stop the PLLs before selecting dormant mode +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> dormant // 0x77616b65 -> WAKE -#define XOSC_DORMANT_OFFSET _u(0x00000008) -#define XOSC_DORMANT_BITS _u(0xffffffff) -#define XOSC_DORMANT_RESET "-" -#define XOSC_DORMANT_MSB _u(31) -#define XOSC_DORMANT_LSB _u(0) -#define XOSC_DORMANT_ACCESS "RW" +#define XOSC_DORMANT_OFFSET _u(0x00000008) +#define XOSC_DORMANT_BITS _u(0xffffffff) +#define XOSC_DORMANT_RESET "-" +#define XOSC_DORMANT_MSB _u(31) +#define XOSC_DORMANT_LSB _u(0) +#define XOSC_DORMANT_ACCESS "RW" #define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) +#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : XOSC_STARTUP // Description : Controls the startup delay #define XOSC_STARTUP_OFFSET _u(0x0000000c) #define XOSC_STARTUP_BITS _u(0x00103fff) -#define XOSC_STARTUP_RESET _u(0x000000c4) +#define XOSC_STARTUP_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : XOSC_STARTUP_X4 // Description : Multiplies the startup_delay by 4. This is of little value to // the user given that the delay can be programmed directly. -#define XOSC_STARTUP_X4_RESET _u(0x0) +#define XOSC_STARTUP_X4_RESET "-" #define XOSC_STARTUP_X4_BITS _u(0x00100000) #define XOSC_STARTUP_X4_MSB _u(20) #define XOSC_STARTUP_X4_LSB _u(20) @@ -138,7 +142,7 @@ // Field : XOSC_STARTUP_DELAY // Description : in multiples of 256*xtal_period. The reset value of 0xc4 // corresponds to approx 50 000 cycles. -#define XOSC_STARTUP_DELAY_RESET _u(0x00c4) +#define XOSC_STARTUP_DELAY_RESET "-" #define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) #define XOSC_STARTUP_DELAY_MSB _u(13) #define XOSC_STARTUP_DELAY_LSB _u(0) @@ -157,4 +161,5 @@ #define XOSC_COUNT_LSB _u(0) #define XOSC_COUNT_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_XOSC_DEFINED +#endif // _HARDWARE_REGS_XOSC_H + diff --git a/src/rp2040/hardware_regs/rp2040.svd b/src/rp2040/hardware_regs/rp2040.svd deleted file mode 100644 index afbc2aaab..000000000 --- a/src/rp2040/hardware_regs/rp2040.svd +++ /dev/null @@ -1,46401 +0,0 @@ - - - - Raspberry Pi - RP2040 - 0.1 - - Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz\n - 264KB on-chip SRAM\n - 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels\n - 1 x USB 1.1 controller and PHY, with host and device support\n - 8 x Programmable I/O (PIO) state machines for custom peripheral support\n - Supported input power 1.8-5.5V DC\n - Operating temperature -20C to +85C\n - Drag-and-drop programming using mass storage over USB\n - Low-power sleep and dormant modes\n - Accurate on-chip clock\n - Temperature sensor\n - Accelerated integer and floating-point libraries on-chip - - - Copyright (c) 2020 Raspberry Pi (Trading) Ltd.\n - \n - SPDX-License-Identifier: BSD-3-Clause - - - CM0PLUS - r0p1 - little - true - false - 1 - 2 - false - 26 - - 8 - 32 - - - XIP_CTRL - 1 - QSPI flash execute-in-place block - 0x14000000 - 32 - - 0 - 0x0020 - registers - - - XIP_IRQ - 6 - - - - CTRL - Cache control - 0x0000 - 0x00000003 - - - POWER_DOWN - When 1, the cache memories are powered down. They retain state,\n - but can not be accessed. This reduces static power dissipation.\n - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n - be enabled when powered down.\n - Cache-as-SRAM accesses will produce a bus error response when\n - the cache is powered down. - [3:3] - read-write - - - ERR_BADWRITE - When 1, writes to any alias other than 0x0 (caching, allocating)\n - will produce a bus fault. When 0, these writes are silently ignored.\n - In either case, writes to the 0x0 alias will deallocate on tag match,\n - as usual. - [1:1] - read-write - - - EN - When 1, enable the cache. When the cache is disabled, all XIP accesses\n - will go straight to the flash, without querying the cache. When enabled,\n - cacheable XIP accesses will query the cache, and the flash will\n - not be accessed if the tag matches and the valid bit is set.\n\n - If the cache is enabled, cache-as-SRAM accesses have no effect on the\n - cache data RAM, and will produce a bus error response. - [0:0] - read-write - - - - - FLUSH - Cache Flush control - 0x0004 - 0x00000000 - - - FLUSH - Write 1 to flush the cache. This clears the tag memory, but\n - the data memory retains its contents. (This means cache-as-SRAM\n - contents is not affected by flush or reset.)\n - Reading will hold the bus (stall the processor) until the flush\n - completes. Alternatively STAT can be polled until completion. - [0:0] - read-write - clear - - - - - STAT - Cache Status - 0x0008 - 0x00000002 - - - FIFO_FULL - When 1, indicates the XIP streaming FIFO is completely full.\n - The streaming FIFO is 2 entries deep, so the full and empty\n - flag allow its level to be ascertained. - [2:2] - read-only - - - FIFO_EMPTY - When 1, indicates the XIP streaming FIFO is completely empty. - [1:1] - read-only - - - FLUSH_READY - Reads as 0 while a cache flush is in progress, and 1 otherwise.\n - The cache is flushed whenever the XIP block is reset, and also\n - when requested via the FLUSH register. - [0:0] - read-only - - - - - CTR_HIT - Cache Hit counter\n - A 32 bit saturating counter that increments upon each cache hit,\n - i.e. when an XIP access is serviced directly from cached data.\n - Write any value to clear. - 0x000c - read-write - 0x00000000 - oneToClear - - - CTR_ACC - Cache Access counter\n - A 32 bit saturating counter that increments upon each XIP access,\n - whether the cache is hit or not. This includes noncacheable accesses.\n - Write any value to clear. - 0x0010 - read-write - 0x00000000 - oneToClear - - - STREAM_ADDR - FIFO stream address - 0x0014 - 0x00000000 - - - STREAM_ADDR - The address of the next word to be streamed from flash to the streaming FIFO.\n - Increments automatically after each flash access.\n - Write the initial access address here before starting a streaming read. - [31:2] - read-write - - - - - STREAM_CTR - FIFO stream control - 0x0018 - 0x00000000 - - - STREAM_CTR - Write a nonzero value to start a streaming read. This will then\n - progress in the background, using flash idle cycles to transfer\n - a linear data block from flash to the streaming FIFO.\n - Decrements automatically (1 at a time) as the stream\n - progresses, and halts on reaching 0.\n - Write 0 to halt an in-progress stream, and discard any in-flight\n - read, so that a new stream can immediately be started (after\n - draining the FIFO and reinitialising STREAM_ADDR) - [21:0] - read-write - - - - - STREAM_FIFO - FIFO stream data\n - Streamed data is buffered here, for retrieval by the system DMA.\n - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n - the DMA to bus stalls caused by other XIP traffic. - 0x001c - read-only - 0x00000000 - - - - - XIP_SSI - 1 - DW_apb_ssi has the following features:\n - * APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n - * APB3 and APB4 protocol support.\n - * Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits.\n - * Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices.\n - * Programmable Dual/Quad/Octal SPI support in Master Mode.\n - * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n - * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n - * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n - * DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n - * Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n - * Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus.\n - * Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n - * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n - * Programmable features:\n - - Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - - Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - - Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer.\n - * Configured features:\n - - FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits.\n - - 1 slave select output.\n - - Hardware slave-select - Dedicated hardware slave-select line.\n - - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - - Interrupt polarity - active high interrupt lines.\n - - Serial clock polarity - low serial-clock polarity directly after reset.\n - - Serial clock phase - capture on first edge of serial-clock directly after reset. - 0x18000000 - 32 - - 0 - 0x0100 - registers - - - - CTRLR0 - Control register 0 - 0x0000 - 0x00000000 - - - SSTE - Slave select toggle enable - [24:24] - read-write - - - SPI_FRF - SPI frame format - [22:21] - read-write - - - STD - Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex - 0 - - - DUAL - Dual-SPI frame format; two bits per SCK, half-duplex - 1 - - - QUAD - Quad-SPI frame format; four bits per SCK, half-duplex - 2 - - - - - DFS_32 - Data frame size in 32b transfer mode\n - Value of n -> n+1 clocks per frame. - [20:16] - read-write - - - CFS - Control frame size\n - Value of n -> n+1 clocks per frame. - [15:12] - read-write - - - SRL - Shift register loop (test mode) - [11:11] - read-write - - - SLV_OE - Slave output enable - [10:10] - read-write - - - TMOD - Transfer mode - [9:8] - read-write - - - TX_AND_RX - Both transmit and receive - 0 - - - TX_ONLY - Transmit only (not for FRF == 0, standard SPI mode) - 1 - - - RX_ONLY - Receive only (not for FRF == 0, standard SPI mode) - 2 - - - EEPROM_READ - EEPROM read mode (TX then RX; RX starts after control data TX'd) - 3 - - - - - SCPOL - Serial clock polarity - [7:7] - read-write - - - SCPH - Serial clock phase - [6:6] - read-write - - - FRF - Frame format - [5:4] - read-write - - - DFS - Data frame size - [3:0] - read-write - - - - - CTRLR1 - Master Control register 1 - 0x0004 - 0x00000000 - - - NDF - Number of data frames - [15:0] - read-write - - - - - SSIENR - SSI Enable - 0x0008 - 0x00000000 - - - SSI_EN - SSI enable - [0:0] - read-write - - - - - MWCR - Microwire Control - 0x000c - 0x00000000 - - - MHS - Microwire handshaking - [2:2] - read-write - - - MDD - Microwire control - [1:1] - read-write - - - MWMOD - Microwire transfer mode - [0:0] - read-write - - - - - SER - Slave enable - 0x0010 - 0x00000000 - - - SER - For each bit:\n - 0 -> slave not selected\n - 1 -> slave selected - [0:0] - read-write - - - - - BAUDR - Baud rate - 0x0014 - 0x00000000 - - - SCKDV - SSI clock divider - [15:0] - read-write - - - - - TXFTLR - TX FIFO threshold level - 0x0018 - 0x00000000 - - - TFT - Transmit FIFO threshold - [7:0] - read-write - - - - - RXFTLR - RX FIFO threshold level - 0x001c - 0x00000000 - - - RFT - Receive FIFO threshold - [7:0] - read-write - - - - - TXFLR - TX FIFO level - 0x0020 - 0x00000000 - - - TFTFL - Transmit FIFO level - [7:0] - read-only - - - - - RXFLR - RX FIFO level - 0x0024 - 0x00000000 - - - RXTFL - Receive FIFO level - [7:0] - read-only - - - - - SR - Status register - 0x0028 - 0x00000000 - - - DCOL - Data collision error - [6:6] - read-only - - - TXE - Transmission error - [5:5] - read-only - - - RFF - Receive FIFO full - [4:4] - read-only - - - RFNE - Receive FIFO not empty - [3:3] - read-only - - - TFE - Transmit FIFO empty - [2:2] - read-only - - - TFNF - Transmit FIFO not full - [1:1] - read-only - - - BUSY - SSI busy flag - [0:0] - read-only - - - - - IMR - Interrupt mask - 0x002c - 0x00000000 - - - MSTIM - Multi-master contention interrupt mask - [5:5] - read-write - - - RXFIM - Receive FIFO full interrupt mask - [4:4] - read-write - - - RXOIM - Receive FIFO overflow interrupt mask - [3:3] - read-write - - - RXUIM - Receive FIFO underflow interrupt mask - [2:2] - read-write - - - TXOIM - Transmit FIFO overflow interrupt mask - [1:1] - read-write - - - TXEIM - Transmit FIFO empty interrupt mask - [0:0] - read-write - - - - - ISR - Interrupt status - 0x0030 - 0x00000000 - - - MSTIS - Multi-master contention interrupt status - [5:5] - read-only - - - RXFIS - Receive FIFO full interrupt status - [4:4] - read-only - - - RXOIS - Receive FIFO overflow interrupt status - [3:3] - read-only - - - RXUIS - Receive FIFO underflow interrupt status - [2:2] - read-only - - - TXOIS - Transmit FIFO overflow interrupt status - [1:1] - read-only - - - TXEIS - Transmit FIFO empty interrupt status - [0:0] - read-only - - - - - RISR - Raw interrupt status - 0x0034 - 0x00000000 - - - MSTIR - Multi-master contention raw interrupt status - [5:5] - read-only - - - RXFIR - Receive FIFO full raw interrupt status - [4:4] - read-only - - - RXOIR - Receive FIFO overflow raw interrupt status - [3:3] - read-only - - - RXUIR - Receive FIFO underflow raw interrupt status - [2:2] - read-only - - - TXOIR - Transmit FIFO overflow raw interrupt status - [1:1] - read-only - - - TXEIR - Transmit FIFO empty raw interrupt status - [0:0] - read-only - - - - - TXOICR - TX FIFO overflow interrupt clear - 0x0038 - 0x00000000 - - - TXOICR - Clear-on-read transmit FIFO overflow interrupt - [0:0] - read-only - - - - - RXOICR - RX FIFO overflow interrupt clear - 0x003c - 0x00000000 - - - RXOICR - Clear-on-read receive FIFO overflow interrupt - [0:0] - read-only - - - - - RXUICR - RX FIFO underflow interrupt clear - 0x0040 - 0x00000000 - - - RXUICR - Clear-on-read receive FIFO underflow interrupt - [0:0] - read-only - - - - - MSTICR - Multi-master interrupt clear - 0x0044 - 0x00000000 - - - MSTICR - Clear-on-read multi-master contention interrupt - [0:0] - read-only - - - - - ICR - Interrupt clear - 0x0048 - 0x00000000 - - - ICR - Clear-on-read all active interrupts - [0:0] - read-only - - - - - DMACR - DMA control - 0x004c - 0x00000000 - - - TDMAE - Transmit DMA enable - [1:1] - read-write - - - RDMAE - Receive DMA enable - [0:0] - read-write - - - - - DMATDLR - DMA TX data level - 0x0050 - 0x00000000 - - - DMATDL - Transmit data watermark level - [7:0] - read-write - - - - - DMARDLR - DMA RX data level - 0x0054 - 0x00000000 - - - DMARDL - Receive data watermark level (DMARDLR+1) - [7:0] - read-write - - - - - IDR - Identification register - 0x0058 - 0x51535049 - - - IDCODE - Peripheral dentification code - [31:0] - read-only - - - - - SSI_VERSION_ID - Version ID - 0x005c - 0x3430312a - - - SSI_COMP_VERSION - SNPS component version (format X.YY) - [31:0] - read-only - - - - - DR0 - Data Register 0 (of 36) - 0x0060 - 0x00000000 - - - DR - First data register of 36 - [31:0] - read-write - - - - - RX_SAMPLE_DLY - RX sample delay - 0x00f0 - 0x00000000 - - - RSD - RXD sample delay (in SCLK cycles) - [7:0] - read-write - - - - - SPI_CTRLR0 - SPI control - 0x00f4 - 0x03000000 - - - XIP_CMD - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) - [31:24] - read-write - - - SPI_RXDS_EN - Read data strobe enable - [18:18] - read-write - - - INST_DDR_EN - Instruction DDR transfer enable - [17:17] - read-write - - - SPI_DDR_EN - SPI DDR transfer enable - [16:16] - read-write - - - WAIT_CYCLES - Wait cycles between control frame transmit and data reception (in SCLK cycles) - [15:11] - read-write - - - INST_L - Instruction length (0/4/8/16b) - [9:8] - read-write - - - NONE - No instruction - 0 - - - 4B - 4-bit instruction - 1 - - - 8B - 8-bit instruction - 2 - - - 16B - 16-bit instruction - 3 - - - - - ADDR_L - Address length (0b-60b in 4b increments) - [5:2] - read-write - - - TRANS_TYPE - Address and instruction transfer format - [1:0] - read-write - - - 1C1A - Command and address both in standard SPI frame format - 0 - - - 1C2A - Command in standard SPI format, address in format specified by FRF - 1 - - - 2C2A - Command and address both in format specified by FRF (e.g. Dual-SPI) - 2 - - - - - - - TXD_DRIVE_EDGE - TX drive edge - 0x00f8 - 0x00000000 - - - TDE - TXD drive edge - [7:0] - read-write - - - - - - - SYSINFO - 1 - 0x40000000 - 32 - - 0 - 0x1000 - registers - - - - CHIP_ID - JEDEC JEP-106 compliant chip identifier. - 0x0000 - 0x00000000 - - - REVISION - [31:28] - read-only - - - PART - [27:12] - read-only - - - MANUFACTURER - [11:0] - read-only - - - - - PLATFORM - Platform register. Allows software to know what environment it is running in. - 0x0004 - 0x00000000 - - - ASIC - [1:1] - read-only - - - FPGA - [0:0] - read-only - - - - - GITREF_RP2040 - Git hash of the chip source. Used to identify chip version. - 0x0040 - read-only - 0x00000000 - - - - - SYSCFG - 1 - Register block for various chip control signals - 0x40004000 - 32 - - 0 - 0x1000 - registers - - - - PROC0_NMI_MASK - Processor core 0 NMI source mask\n - Set a bit high to enable NMI from that IRQ - 0x0000 - read-write - 0x00000000 - - - PROC1_NMI_MASK - Processor core 1 NMI source mask\n - Set a bit high to enable NMI from that IRQ - 0x0004 - read-write - 0x00000000 - - - PROC_CONFIG - Configuration for processors - 0x0008 - 0x10000000 - - - PROC1_DAP_INSTID - Configure proc1 DAP instance ID.\n - Recommend that this is NOT changed until you require debug access in multi-chip environment\n - WARNING: do not set to 15 as this is reserved for RescueDP - [31:28] - read-write - - - PROC0_DAP_INSTID - Configure proc0 DAP instance ID.\n - Recommend that this is NOT changed until you require debug access in multi-chip environment\n - WARNING: do not set to 15 as this is reserved for RescueDP - [27:24] - read-write - - - PROC1_HALTED - Indication that proc1 has halted - [1:1] - read-only - - - PROC0_HALTED - Indication that proc0 has halted - [0:0] - read-only - - - - - PROC_IN_SYNC_BYPASS - For each bit, if 1, bypass the input synchronizer between that GPIO\n - and the GPIO input register in the SIO. The input synchronizers should\n - generally be unbypassed, to avoid injecting metastabilities into processors.\n - If you're feeling brave, you can bypass to save two cycles of input\n - latency. This register applies to GPIO 0...29. - 0x000c - 0x00000000 - - - PROC_IN_SYNC_BYPASS - [29:0] - read-write - - - - - PROC_IN_SYNC_BYPASS_HI - For each bit, if 1, bypass the input synchronizer between that GPIO\n - and the GPIO input register in the SIO. The input synchronizers should\n - generally be unbypassed, to avoid injecting metastabilities into processors.\n - If you're feeling brave, you can bypass to save two cycles of input\n - latency. This register applies to GPIO 30...35 (the QSPI IOs). - 0x0010 - 0x00000000 - - - PROC_IN_SYNC_BYPASS_HI - [5:0] - read-write - - - - - DBGFORCE - Directly control the SWD debug port of either processor - 0x0014 - 0x00000066 - - - PROC1_ATTACH - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. - [7:7] - read-write - - - PROC1_SWCLK - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set - [6:6] - read-write - - - PROC1_SWDI - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set - [5:5] - read-write - - - PROC1_SWDO - Observe the value of processor 1 SWDIO output. - [4:4] - read-only - - - PROC0_ATTACH - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. - [3:3] - read-write - - - PROC0_SWCLK - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set - [2:2] - read-write - - - PROC0_SWDI - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set - [1:1] - read-write - - - PROC0_SWDO - Observe the value of processor 0 SWDIO output. - [0:0] - read-only - - - - - MEMPOWERDOWN - Control power downs to memories. Set high to power down memories.\n - Use with extreme caution - 0x0018 - 0x00000000 - - - ROM - [7:7] - read-write - - - USB - [6:6] - read-write - - - SRAM5 - [5:5] - read-write - - - SRAM4 - [4:4] - read-write - - - SRAM3 - [3:3] - read-write - - - SRAM2 - [2:2] - read-write - - - SRAM1 - [1:1] - read-write - - - SRAM0 - [0:0] - read-write - - - - - - - CLOCKS - 1 - 0x40008000 - 32 - - 0 - 0x1000 - registers - - - CLOCKS_IRQ - 17 - - - - CLK_GPOUT0_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0000 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT0_DIV - Clock divisor, can be changed on-the-fly - 0x0004 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT0_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x0008 - read-only - 0x00000001 - - - CLK_GPOUT1_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x000c - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT1_DIV - Clock divisor, can be changed on-the-fly - 0x0010 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT1_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x0014 - read-only - 0x00000001 - - - CLK_GPOUT2_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0018 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT2_DIV - Clock divisor, can be changed on-the-fly - 0x001c - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT2_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x0020 - read-only - 0x00000001 - - - CLK_GPOUT3_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0024 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - DC50 - Enables duty cycle correction for odd divisors - [12:12] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clk_sys - 6 - - - clk_usb - 7 - - - clk_adc - 8 - - - clk_rtc - 9 - - - clk_ref - 10 - - - - - - - CLK_GPOUT3_DIV - Clock divisor, can be changed on-the-fly - 0x0028 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_GPOUT3_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x002c - read-only - 0x00000001 - - - CLK_REF_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0030 - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [6:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [1:0] - read-write - - - rosc_clksrc_ph - 0 - - - clksrc_clk_ref_aux - 1 - - - xosc_clksrc - 2 - - - - - - - CLK_REF_DIV - Clock divisor, can be changed on-the-fly - 0x0034 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_REF_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - 0x0038 - read-only - 0x00000001 - - - CLK_SYS_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x003c - 0x00000000 - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_sys - 0 - - - clksrc_pll_usb - 1 - - - rosc_clksrc - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - SRC - Selects the clock source glitchlessly, can be changed on-the-fly - [0:0] - read-write - - - clk_ref - 0 - - - clksrc_clk_sys_aux - 1 - - - - - - - CLK_SYS_DIV - Clock divisor, can be changed on-the-fly - 0x0040 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_SYS_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. - 0x0044 - read-only - 0x00000001 - - - CLK_PERI_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0048 - 0x00000000 - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clk_sys - 0 - - - clksrc_pll_sys - 1 - - - clksrc_pll_usb - 2 - - - rosc_clksrc_ph - 3 - - - xosc_clksrc - 4 - - - clksrc_gpin0 - 5 - - - clksrc_gpin1 - 6 - - - - - - - CLK_PERI_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x0050 - read-only - 0x00000001 - - - CLK_USB_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0054 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_USB_DIV - Clock divisor, can be changed on-the-fly - 0x0058 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_USB_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x005c - read-only - 0x00000001 - - - CLK_ADC_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0060 - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_ADC_DIV - Clock divisor, can be changed on-the-fly - 0x0064 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [9:8] - read-write - - - - - CLK_ADC_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x0068 - read-only - 0x00000001 - - - CLK_RTC_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x006c - 0x00000000 - - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] - read-write - - - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] - read-write - - - ENABLE - Starts and stops the clock generator cleanly - [11:11] - read-write - - - KILL - Asynchronously kills the clock generator - [10:10] - read-write - - - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [7:5] - read-write - - - clksrc_pll_usb - 0 - - - clksrc_pll_sys - 1 - - - rosc_clksrc_ph - 2 - - - xosc_clksrc - 3 - - - clksrc_gpin0 - 4 - - - clksrc_gpin1 - 5 - - - - - - - CLK_RTC_DIV - Clock divisor, can be changed on-the-fly - 0x0070 - 0x00000100 - - - INT - Integer component of the divisor, 0 -> divide by 2^16 - [31:8] - read-write - - - FRAC - Fractional component of the divisor - [7:0] - read-write - - - - - CLK_RTC_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. - 0x0074 - read-only - 0x00000001 - - - CLK_SYS_RESUS_CTRL - 0x0078 - 0x000000ff - - - CLEAR - For clearing the resus after the fault that triggered it has been corrected - [16:16] - read-write - - - FRCE - Force a resus, for test purposes only - [12:12] - read-write - - - ENABLE - Enable resus - [8:8] - read-write - - - TIMEOUT - This is expressed as a number of clk_ref cycles\n - and must be >= 2x clk_ref_freq/min_clk_tst_freq - [7:0] - read-write - - - - - CLK_SYS_RESUS_STATUS - 0x007c - 0x00000000 - - - RESUSSED - Clock has been resuscitated, correct the error then send ctrl_clear=1 - [0:0] - read-only - - - - - FC0_REF_KHZ - Reference clock frequency in kHz - 0x0080 - 0x00000000 - - - FC0_REF_KHZ - [19:0] - read-write - - - - - FC0_MIN_KHZ - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags - 0x0084 - 0x00000000 - - - FC0_MIN_KHZ - [24:0] - read-write - - - - - FC0_MAX_KHZ - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags - 0x0088 - 0x01ffffff - - - FC0_MAX_KHZ - [24:0] - read-write - - - - - FC0_DELAY - Delays the start of frequency counting to allow the mux to settle\n - Delay is measured in multiples of the reference clock period - 0x008c - 0x00000001 - - - FC0_DELAY - [2:0] - read-write - - - - - FC0_INTERVAL - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n - The default gives a test interval of 250us - 0x0090 - 0x00000008 - - - FC0_INTERVAL - [3:0] - read-write - - - - - FC0_SRC - Clock sent to frequency counter, set to 0 when not required\n - Writing to this register initiates the frequency count - 0x0094 - 0x00000000 - - - FC0_SRC - [7:0] - read-write - - - NULL - 0 - - - pll_sys_clksrc_primary - 1 - - - pll_usb_clksrc_primary - 2 - - - rosc_clksrc - 3 - - - rosc_clksrc_ph - 4 - - - xosc_clksrc - 5 - - - clksrc_gpin0 - 6 - - - clksrc_gpin1 - 7 - - - clk_ref - 8 - - - clk_sys - 9 - - - clk_peri - 10 - - - clk_usb - 11 - - - clk_adc - 12 - - - clk_rtc - 13 - - - - - - - FC0_STATUS - Frequency counter status - 0x0098 - 0x00000000 - - - DIED - Test clock stopped during test - [28:28] - read-only - - - FAST - Test clock faster than expected, only valid when status_done=1 - [24:24] - read-only - - - SLOW - Test clock slower than expected, only valid when status_done=1 - [20:20] - read-only - - - FAIL - Test failed - [16:16] - read-only - - - WAITING - Waiting for test clock to start - [12:12] - read-only - - - RUNNING - Test running - [8:8] - read-only - - - DONE - Test complete - [4:4] - read-only - - - PASS - Test passed - [0:0] - read-only - - - - - FC0_RESULT - Result of frequency measurement, only valid when status_done=1 - 0x009c - 0x00000000 - - - KHZ - [29:5] - read-only - - - FRAC - [4:0] - read-only - - - - - WAKE_EN0 - enable clock in wake mode - 0x00a0 - 0xffffffff - - - clk_sys_sram3 - [31:31] - read-write - - - clk_sys_sram2 - [30:30] - read-write - - - clk_sys_sram1 - [29:29] - read-write - - - clk_sys_sram0 - [28:28] - read-write - - - clk_sys_spi1 - [27:27] - read-write - - - clk_peri_spi1 - [26:26] - read-write - - - clk_sys_spi0 - [25:25] - read-write - - - clk_peri_spi0 - [24:24] - read-write - - - clk_sys_sio - [23:23] - read-write - - - clk_sys_rtc - [22:22] - read-write - - - clk_rtc_rtc - [21:21] - read-write - - - clk_sys_rosc - [20:20] - read-write - - - clk_sys_rom - [19:19] - read-write - - - clk_sys_resets - [18:18] - read-write - - - clk_sys_pwm - [17:17] - read-write - - - clk_sys_psm - [16:16] - read-write - - - clk_sys_pll_usb - [15:15] - read-write - - - clk_sys_pll_sys - [14:14] - read-write - - - clk_sys_pio1 - [13:13] - read-write - - - clk_sys_pio0 - [12:12] - read-write - - - clk_sys_pads - [11:11] - read-write - - - clk_sys_vreg_and_chip_reset - [10:10] - read-write - - - clk_sys_jtag - [9:9] - read-write - - - clk_sys_io - [8:8] - read-write - - - clk_sys_i2c1 - [7:7] - read-write - - - clk_sys_i2c0 - [6:6] - read-write - - - clk_sys_dma - [5:5] - read-write - - - clk_sys_busfabric - [4:4] - read-write - - - clk_sys_busctrl - [3:3] - read-write - - - clk_sys_adc - [2:2] - read-write - - - clk_adc_adc - [1:1] - read-write - - - clk_sys_clocks - [0:0] - read-write - - - - - WAKE_EN1 - enable clock in wake mode - 0x00a4 - 0x00007fff - - - clk_sys_xosc - [14:14] - read-write - - - clk_sys_xip - [13:13] - read-write - - - clk_sys_watchdog - [12:12] - read-write - - - clk_usb_usbctrl - [11:11] - read-write - - - clk_sys_usbctrl - [10:10] - read-write - - - clk_sys_uart1 - [9:9] - read-write - - - clk_peri_uart1 - [8:8] - read-write - - - clk_sys_uart0 - [7:7] - read-write - - - clk_peri_uart0 - [6:6] - read-write - - - clk_sys_timer - [5:5] - read-write - - - clk_sys_tbman - [4:4] - read-write - - - clk_sys_sysinfo - [3:3] - read-write - - - clk_sys_syscfg - [2:2] - read-write - - - clk_sys_sram5 - [1:1] - read-write - - - clk_sys_sram4 - [0:0] - read-write - - - - - SLEEP_EN0 - enable clock in sleep mode - 0x00a8 - 0xffffffff - - - clk_sys_sram3 - [31:31] - read-write - - - clk_sys_sram2 - [30:30] - read-write - - - clk_sys_sram1 - [29:29] - read-write - - - clk_sys_sram0 - [28:28] - read-write - - - clk_sys_spi1 - [27:27] - read-write - - - clk_peri_spi1 - [26:26] - read-write - - - clk_sys_spi0 - [25:25] - read-write - - - clk_peri_spi0 - [24:24] - read-write - - - clk_sys_sio - [23:23] - read-write - - - clk_sys_rtc - [22:22] - read-write - - - clk_rtc_rtc - [21:21] - read-write - - - clk_sys_rosc - [20:20] - read-write - - - clk_sys_rom - [19:19] - read-write - - - clk_sys_resets - [18:18] - read-write - - - clk_sys_pwm - [17:17] - read-write - - - clk_sys_psm - [16:16] - read-write - - - clk_sys_pll_usb - [15:15] - read-write - - - clk_sys_pll_sys - [14:14] - read-write - - - clk_sys_pio1 - [13:13] - read-write - - - clk_sys_pio0 - [12:12] - read-write - - - clk_sys_pads - [11:11] - read-write - - - clk_sys_vreg_and_chip_reset - [10:10] - read-write - - - clk_sys_jtag - [9:9] - read-write - - - clk_sys_io - [8:8] - read-write - - - clk_sys_i2c1 - [7:7] - read-write - - - clk_sys_i2c0 - [6:6] - read-write - - - clk_sys_dma - [5:5] - read-write - - - clk_sys_busfabric - [4:4] - read-write - - - clk_sys_busctrl - [3:3] - read-write - - - clk_sys_adc - [2:2] - read-write - - - clk_adc_adc - [1:1] - read-write - - - clk_sys_clocks - [0:0] - read-write - - - - - SLEEP_EN1 - enable clock in sleep mode - 0x00ac - 0x00007fff - - - clk_sys_xosc - [14:14] - read-write - - - clk_sys_xip - [13:13] - read-write - - - clk_sys_watchdog - [12:12] - read-write - - - clk_usb_usbctrl - [11:11] - read-write - - - clk_sys_usbctrl - [10:10] - read-write - - - clk_sys_uart1 - [9:9] - read-write - - - clk_peri_uart1 - [8:8] - read-write - - - clk_sys_uart0 - [7:7] - read-write - - - clk_peri_uart0 - [6:6] - read-write - - - clk_sys_timer - [5:5] - read-write - - - clk_sys_tbman - [4:4] - read-write - - - clk_sys_sysinfo - [3:3] - read-write - - - clk_sys_syscfg - [2:2] - read-write - - - clk_sys_sram5 - [1:1] - read-write - - - clk_sys_sram4 - [0:0] - read-write - - - - - ENABLED0 - indicates the state of the clock enable - 0x00b0 - 0x00000000 - - - clk_sys_sram3 - [31:31] - read-only - - - clk_sys_sram2 - [30:30] - read-only - - - clk_sys_sram1 - [29:29] - read-only - - - clk_sys_sram0 - [28:28] - read-only - - - clk_sys_spi1 - [27:27] - read-only - - - clk_peri_spi1 - [26:26] - read-only - - - clk_sys_spi0 - [25:25] - read-only - - - clk_peri_spi0 - [24:24] - read-only - - - clk_sys_sio - [23:23] - read-only - - - clk_sys_rtc - [22:22] - read-only - - - clk_rtc_rtc - [21:21] - read-only - - - clk_sys_rosc - [20:20] - read-only - - - clk_sys_rom - [19:19] - read-only - - - clk_sys_resets - [18:18] - read-only - - - clk_sys_pwm - [17:17] - read-only - - - clk_sys_psm - [16:16] - read-only - - - clk_sys_pll_usb - [15:15] - read-only - - - clk_sys_pll_sys - [14:14] - read-only - - - clk_sys_pio1 - [13:13] - read-only - - - clk_sys_pio0 - [12:12] - read-only - - - clk_sys_pads - [11:11] - read-only - - - clk_sys_vreg_and_chip_reset - [10:10] - read-only - - - clk_sys_jtag - [9:9] - read-only - - - clk_sys_io - [8:8] - read-only - - - clk_sys_i2c1 - [7:7] - read-only - - - clk_sys_i2c0 - [6:6] - read-only - - - clk_sys_dma - [5:5] - read-only - - - clk_sys_busfabric - [4:4] - read-only - - - clk_sys_busctrl - [3:3] - read-only - - - clk_sys_adc - [2:2] - read-only - - - clk_adc_adc - [1:1] - read-only - - - clk_sys_clocks - [0:0] - read-only - - - - - ENABLED1 - indicates the state of the clock enable - 0x00b4 - 0x00000000 - - - clk_sys_xosc - [14:14] - read-only - - - clk_sys_xip - [13:13] - read-only - - - clk_sys_watchdog - [12:12] - read-only - - - clk_usb_usbctrl - [11:11] - read-only - - - clk_sys_usbctrl - [10:10] - read-only - - - clk_sys_uart1 - [9:9] - read-only - - - clk_peri_uart1 - [8:8] - read-only - - - clk_sys_uart0 - [7:7] - read-only - - - clk_peri_uart0 - [6:6] - read-only - - - clk_sys_timer - [5:5] - read-only - - - clk_sys_tbman - [4:4] - read-only - - - clk_sys_sysinfo - [3:3] - read-only - - - clk_sys_syscfg - [2:2] - read-only - - - clk_sys_sram5 - [1:1] - read-only - - - clk_sys_sram4 - [0:0] - read-only - - - - - INTR - Raw Interrupts - 0x00b8 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x00bc - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x00c0 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x00c4 - 0x00000000 - - - CLK_SYS_RESUS - [0:0] - read-only - - - - - - - RESETS - 1 - 0x4000c000 - 32 - - 0 - 0x1000 - registers - - - - RESET - Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. - 0x0000 - 0x01ffffff - - - usbctrl - [24:24] - read-write - - - uart1 - [23:23] - read-write - - - uart0 - [22:22] - read-write - - - timer - [21:21] - read-write - - - tbman - [20:20] - read-write - - - sysinfo - [19:19] - read-write - - - syscfg - [18:18] - read-write - - - spi1 - [17:17] - read-write - - - spi0 - [16:16] - read-write - - - rtc - [15:15] - read-write - - - pwm - [14:14] - read-write - - - pll_usb - [13:13] - read-write - - - pll_sys - [12:12] - read-write - - - pio1 - [11:11] - read-write - - - pio0 - [10:10] - read-write - - - pads_qspi - [9:9] - read-write - - - pads_bank0 - [8:8] - read-write - - - jtag - [7:7] - read-write - - - io_qspi - [6:6] - read-write - - - io_bank0 - [5:5] - read-write - - - i2c1 - [4:4] - read-write - - - i2c0 - [3:3] - read-write - - - dma - [2:2] - read-write - - - busctrl - [1:1] - read-write - - - adc - [0:0] - read-write - - - - - WDSEL - Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. - 0x0004 - 0x00000000 - - - usbctrl - [24:24] - read-write - - - uart1 - [23:23] - read-write - - - uart0 - [22:22] - read-write - - - timer - [21:21] - read-write - - - tbman - [20:20] - read-write - - - sysinfo - [19:19] - read-write - - - syscfg - [18:18] - read-write - - - spi1 - [17:17] - read-write - - - spi0 - [16:16] - read-write - - - rtc - [15:15] - read-write - - - pwm - [14:14] - read-write - - - pll_usb - [13:13] - read-write - - - pll_sys - [12:12] - read-write - - - pio1 - [11:11] - read-write - - - pio0 - [10:10] - read-write - - - pads_qspi - [9:9] - read-write - - - pads_bank0 - [8:8] - read-write - - - jtag - [7:7] - read-write - - - io_qspi - [6:6] - read-write - - - io_bank0 - [5:5] - read-write - - - i2c1 - [4:4] - read-write - - - i2c0 - [3:3] - read-write - - - dma - [2:2] - read-write - - - busctrl - [1:1] - read-write - - - adc - [0:0] - read-write - - - - - RESET_DONE - Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. - 0x0008 - 0x00000000 - - - usbctrl - [24:24] - read-only - - - uart1 - [23:23] - read-only - - - uart0 - [22:22] - read-only - - - timer - [21:21] - read-only - - - tbman - [20:20] - read-only - - - sysinfo - [19:19] - read-only - - - syscfg - [18:18] - read-only - - - spi1 - [17:17] - read-only - - - spi0 - [16:16] - read-only - - - rtc - [15:15] - read-only - - - pwm - [14:14] - read-only - - - pll_usb - [13:13] - read-only - - - pll_sys - [12:12] - read-only - - - pio1 - [11:11] - read-only - - - pio0 - [10:10] - read-only - - - pads_qspi - [9:9] - read-only - - - pads_bank0 - [8:8] - read-only - - - jtag - [7:7] - read-only - - - io_qspi - [6:6] - read-only - - - io_bank0 - [5:5] - read-only - - - i2c1 - [4:4] - read-only - - - i2c0 - [3:3] - read-only - - - dma - [2:2] - read-only - - - busctrl - [1:1] - read-only - - - adc - [0:0] - read-only - - - - - - - PSM - 1 - 0x40010000 - 32 - - 0 - 0x1000 - registers - - - - FRCE_ON - Force block out of reset (i.e. power it on) - 0x0000 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write - - - - - FRCE_OFF - Force into reset (i.e. power it off) - 0x0004 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write - - - - - WDSEL - Set to 1 if this peripheral should be reset when the watchdog fires. - 0x0008 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write - - - - - DONE - Indicates the peripheral's registers are ready to access. - 0x000c - 0x00000000 - - - proc1 - [16:16] - read-only - - - proc0 - [15:15] - read-only - - - sio - [14:14] - read-only - - - vreg_and_chip_reset - [13:13] - read-only - - - xip - [12:12] - read-only - - - sram5 - [11:11] - read-only - - - sram4 - [10:10] - read-only - - - sram3 - [9:9] - read-only - - - sram2 - [8:8] - read-only - - - sram1 - [7:7] - read-only - - - sram0 - [6:6] - read-only - - - rom - [5:5] - read-only - - - busfabric - [4:4] - read-only - - - resets - [3:3] - read-only - - - clocks - [2:2] - read-only - - - xosc - [1:1] - read-only - - - rosc - [0:0] - read-only - - - - - - - IO_BANK0 - 1 - 0x40014000 - 32 - - 0 - 0x1000 - registers - - - IO_IRQ_BANK0 - 13 - - - - GPIO0_STATUS - GPIO status - 0x0000 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO0_CTRL - GPIO control including function select and overrides. - 0x0004 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - jtag_tck - 0 - - - spi0_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_0 - 4 - - - sio_0 - 5 - - - pio0_0 - 6 - - - pio1_0 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO1_STATUS - GPIO status - 0x0008 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO1_CTRL - GPIO control including function select and overrides. - 0x000c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - jtag_tms - 0 - - - spi0_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_0 - 4 - - - sio_1 - 5 - - - pio0_1 - 6 - - - pio1_1 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO2_STATUS - GPIO status - 0x0010 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO2_CTRL - GPIO control including function select and overrides. - 0x0014 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - jtag_tdi - 0 - - - spi0_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_1 - 4 - - - sio_2 - 5 - - - pio0_2 - 6 - - - pio1_2 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO3_STATUS - GPIO status - 0x0018 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO3_CTRL - GPIO control including function select and overrides. - 0x001c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - jtag_tdo - 0 - - - spi0_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_1 - 4 - - - sio_3 - 5 - - - pio0_3 - 6 - - - pio1_3 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO4_STATUS - GPIO status - 0x0020 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO4_CTRL - GPIO control including function select and overrides. - 0x0024 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_2 - 4 - - - sio_4 - 5 - - - pio0_4 - 6 - - - pio1_4 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO5_STATUS - GPIO status - 0x0028 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO5_CTRL - GPIO control including function select and overrides. - 0x002c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_2 - 4 - - - sio_5 - 5 - - - pio0_5 - 6 - - - pio1_5 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO6_STATUS - GPIO status - 0x0030 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO6_CTRL - GPIO control including function select and overrides. - 0x0034 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_3 - 4 - - - sio_6 - 5 - - - pio0_6 - 6 - - - pio1_6 - 7 - - - usb_muxing_extphy_softcon - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO7_STATUS - GPIO status - 0x0038 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO7_CTRL - GPIO control including function select and overrides. - 0x003c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_3 - 4 - - - sio_7 - 5 - - - pio0_7 - 6 - - - pio1_7 - 7 - - - usb_muxing_extphy_oe_n - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO8_STATUS - GPIO status - 0x0040 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO8_CTRL - GPIO control including function select and overrides. - 0x0044 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_4 - 4 - - - sio_8 - 5 - - - pio0_8 - 6 - - - pio1_8 - 7 - - - usb_muxing_extphy_rcv - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO9_STATUS - GPIO status - 0x0048 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO9_CTRL - GPIO control including function select and overrides. - 0x004c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_4 - 4 - - - sio_9 - 5 - - - pio0_9 - 6 - - - pio1_9 - 7 - - - usb_muxing_extphy_vp - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO10_STATUS - GPIO status - 0x0050 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO10_CTRL - GPIO control including function select and overrides. - 0x0054 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_5 - 4 - - - sio_10 - 5 - - - pio0_10 - 6 - - - pio1_10 - 7 - - - usb_muxing_extphy_vm - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO11_STATUS - GPIO status - 0x0058 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO11_CTRL - GPIO control including function select and overrides. - 0x005c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_5 - 4 - - - sio_11 - 5 - - - pio0_11 - 6 - - - pio1_11 - 7 - - - usb_muxing_extphy_suspnd - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO12_STATUS - GPIO status - 0x0060 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO12_CTRL - GPIO control including function select and overrides. - 0x0064 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_6 - 4 - - - sio_12 - 5 - - - pio0_12 - 6 - - - pio1_12 - 7 - - - usb_muxing_extphy_speed - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO13_STATUS - GPIO status - 0x0068 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO13_CTRL - GPIO control including function select and overrides. - 0x006c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_6 - 4 - - - sio_13 - 5 - - - pio0_13 - 6 - - - pio1_13 - 7 - - - usb_muxing_extphy_vpo - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO14_STATUS - GPIO status - 0x0070 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO14_CTRL - GPIO control including function select and overrides. - 0x0074 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_7 - 4 - - - sio_14 - 5 - - - pio0_14 - 6 - - - pio1_14 - 7 - - - usb_muxing_extphy_vmo - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO15_STATUS - GPIO status - 0x0078 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO15_CTRL - GPIO control including function select and overrides. - 0x007c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_7 - 4 - - - sio_15 - 5 - - - pio0_15 - 6 - - - pio1_15 - 7 - - - usb_muxing_digital_dp - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO16_STATUS - GPIO status - 0x0080 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO16_CTRL - GPIO control including function select and overrides. - 0x0084 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_0 - 4 - - - sio_16 - 5 - - - pio0_16 - 6 - - - pio1_16 - 7 - - - usb_muxing_digital_dm - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO17_STATUS - GPIO status - 0x0088 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO17_CTRL - GPIO control including function select and overrides. - 0x008c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_0 - 4 - - - sio_17 - 5 - - - pio0_17 - 6 - - - pio1_17 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO18_STATUS - GPIO status - 0x0090 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO18_CTRL - GPIO control including function select and overrides. - 0x0094 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart0_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_1 - 4 - - - sio_18 - 5 - - - pio0_18 - 6 - - - pio1_18 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO19_STATUS - GPIO status - 0x0098 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO19_CTRL - GPIO control including function select and overrides. - 0x009c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart0_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_1 - 4 - - - sio_19 - 5 - - - pio0_19 - 6 - - - pio1_19 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO20_STATUS - GPIO status - 0x00a0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO20_CTRL - GPIO control including function select and overrides. - 0x00a4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_2 - 4 - - - sio_20 - 5 - - - pio0_20 - 6 - - - pio1_20 - 7 - - - clocks_gpin_0 - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO21_STATUS - GPIO status - 0x00a8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO21_CTRL - GPIO control including function select and overrides. - 0x00ac - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_2 - 4 - - - sio_21 - 5 - - - pio0_21 - 6 - - - pio1_21 - 7 - - - clocks_gpout_0 - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO22_STATUS - GPIO status - 0x00b0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO22_CTRL - GPIO control including function select and overrides. - 0x00b4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_3 - 4 - - - sio_22 - 5 - - - pio0_22 - 6 - - - pio1_22 - 7 - - - clocks_gpin_1 - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO23_STATUS - GPIO status - 0x00b8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO23_CTRL - GPIO control including function select and overrides. - 0x00bc - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi0_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_3 - 4 - - - sio_23 - 5 - - - pio0_23 - 6 - - - pio1_23 - 7 - - - clocks_gpout_1 - 8 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO24_STATUS - GPIO status - 0x00c0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO24_CTRL - GPIO control including function select and overrides. - 0x00c4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart1_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_4 - 4 - - - sio_24 - 5 - - - pio0_24 - 6 - - - pio1_24 - 7 - - - clocks_gpout_2 - 8 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO25_STATUS - GPIO status - 0x00c8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO25_CTRL - GPIO control including function select and overrides. - 0x00cc - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart1_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_4 - 4 - - - sio_25 - 5 - - - pio0_25 - 6 - - - pio1_25 - 7 - - - clocks_gpout_3 - 8 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO26_STATUS - GPIO status - 0x00d0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO26_CTRL - GPIO control including function select and overrides. - 0x00d4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_sclk - 1 - - - uart1_cts - 2 - - - i2c1_sda - 3 - - - pwm_a_5 - 4 - - - sio_26 - 5 - - - pio0_26 - 6 - - - pio1_26 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - GPIO27_STATUS - GPIO status - 0x00d8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO27_CTRL - GPIO control including function select and overrides. - 0x00dc - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_tx - 1 - - - uart1_rts - 2 - - - i2c1_scl - 3 - - - pwm_b_5 - 4 - - - sio_27 - 5 - - - pio0_27 - 6 - - - pio1_27 - 7 - - - usb_muxing_overcurr_detect - 9 - - - null - 31 - - - - - - - GPIO28_STATUS - GPIO status - 0x00e0 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO28_CTRL - GPIO control including function select and overrides. - 0x00e4 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_rx - 1 - - - uart0_tx - 2 - - - i2c0_sda - 3 - - - pwm_a_6 - 4 - - - sio_28 - 5 - - - pio0_28 - 6 - - - pio1_28 - 7 - - - usb_muxing_vbus_detect - 9 - - - null - 31 - - - - - - - GPIO29_STATUS - GPIO status - 0x00e8 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO29_CTRL - GPIO control including function select and overrides. - 0x00ec - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - spi1_ss_n - 1 - - - uart0_rx - 2 - - - i2c0_scl - 3 - - - pwm_b_6 - 4 - - - sio_29 - 5 - - - pio0_29 - 6 - - - pio1_29 - 7 - - - usb_muxing_vbus_en - 9 - - - null - 31 - - - - - - - INTR0 - Raw Interrupts - 0x00f0 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO7_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO6_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO5_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO4_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO3_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO2_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO1_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO0_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - INTR1 - Raw Interrupts - 0x00f4 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO15_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO14_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO13_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO12_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO11_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO10_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO9_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO8_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - INTR2 - Raw Interrupts - 0x00f8 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO23_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO22_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO21_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO20_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO19_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO18_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO17_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO16_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - INTR3 - Raw Interrupts - 0x00fc - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO29_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO28_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO27_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO26_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO25_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO24_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE0 - Interrupt Enable for proc0 - 0x0100 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE1 - Interrupt Enable for proc0 - 0x0104 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE2 - Interrupt Enable for proc0 - 0x0108 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTE3 - Interrupt Enable for proc0 - 0x010c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF0 - Interrupt Force for proc0 - 0x0110 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF1 - Interrupt Force for proc0 - 0x0114 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF2 - Interrupt Force for proc0 - 0x0118 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF3 - Interrupt Force for proc0 - 0x011c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS0 - Interrupt status after masking & forcing for proc0 - 0x0120 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS1 - Interrupt status after masking & forcing for proc0 - 0x0124 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS2 - Interrupt status after masking & forcing for proc0 - 0x0128 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTS3 - Interrupt status after masking & forcing for proc0 - 0x012c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE0 - Interrupt Enable for proc1 - 0x0130 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE1 - Interrupt Enable for proc1 - 0x0134 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE2 - Interrupt Enable for proc1 - 0x0138 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTE3 - Interrupt Enable for proc1 - 0x013c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF0 - Interrupt Force for proc1 - 0x0140 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF1 - Interrupt Force for proc1 - 0x0144 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF2 - Interrupt Force for proc1 - 0x0148 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF3 - Interrupt Force for proc1 - 0x014c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS0 - Interrupt status after masking & forcing for proc1 - 0x0150 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS1 - Interrupt status after masking & forcing for proc1 - 0x0154 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS2 - Interrupt status after masking & forcing for proc1 - 0x0158 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTS3 - Interrupt status after masking & forcing for proc1 - 0x015c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE0 - Interrupt Enable for dormant_wake - 0x0160 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE1 - Interrupt Enable for dormant_wake - 0x0164 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE2 - Interrupt Enable for dormant_wake - 0x0168 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTE3 - Interrupt Enable for dormant_wake - 0x016c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF0 - Interrupt Force for dormant_wake - 0x0170 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH - [23:23] - read-write - - - GPIO5_EDGE_LOW - [22:22] - read-write - - - GPIO5_LEVEL_HIGH - [21:21] - read-write - - - GPIO5_LEVEL_LOW - [20:20] - read-write - - - GPIO4_EDGE_HIGH - [19:19] - read-write - - - GPIO4_EDGE_LOW - [18:18] - read-write - - - GPIO4_LEVEL_HIGH - [17:17] - read-write - - - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW - [8:8] - read-write - - - GPIO1_EDGE_HIGH - [7:7] - read-write - - - GPIO1_EDGE_LOW - [6:6] - read-write - - - GPIO1_LEVEL_HIGH - [5:5] - read-write - - - GPIO1_LEVEL_LOW - [4:4] - read-write - - - GPIO0_EDGE_HIGH - [3:3] - read-write - - - GPIO0_EDGE_LOW - [2:2] - read-write - - - GPIO0_LEVEL_HIGH - [1:1] - read-write - - - GPIO0_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF1 - Interrupt Force for dormant_wake - 0x0174 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-write - - - GPIO15_EDGE_LOW - [30:30] - read-write - - - GPIO15_LEVEL_HIGH - [29:29] - read-write - - - GPIO15_LEVEL_LOW - [28:28] - read-write - - - GPIO14_EDGE_HIGH - [27:27] - read-write - - - GPIO14_EDGE_LOW - [26:26] - read-write - - - GPIO14_LEVEL_HIGH - [25:25] - read-write - - - GPIO14_LEVEL_LOW - [24:24] - read-write - - - GPIO13_EDGE_HIGH - [23:23] - read-write - - - GPIO13_EDGE_LOW - [22:22] - read-write - - - GPIO13_LEVEL_HIGH - [21:21] - read-write - - - GPIO13_LEVEL_LOW - [20:20] - read-write - - - GPIO12_EDGE_HIGH - [19:19] - read-write - - - GPIO12_EDGE_LOW - [18:18] - read-write - - - GPIO12_LEVEL_HIGH - [17:17] - read-write - - - GPIO12_LEVEL_LOW - [16:16] - read-write - - - GPIO11_EDGE_HIGH - [15:15] - read-write - - - GPIO11_EDGE_LOW - [14:14] - read-write - - - GPIO11_LEVEL_HIGH - [13:13] - read-write - - - GPIO11_LEVEL_LOW - [12:12] - read-write - - - GPIO10_EDGE_HIGH - [11:11] - read-write - - - GPIO10_EDGE_LOW - [10:10] - read-write - - - GPIO10_LEVEL_HIGH - [9:9] - read-write - - - GPIO10_LEVEL_LOW - [8:8] - read-write - - - GPIO9_EDGE_HIGH - [7:7] - read-write - - - GPIO9_EDGE_LOW - [6:6] - read-write - - - GPIO9_LEVEL_HIGH - [5:5] - read-write - - - GPIO9_LEVEL_LOW - [4:4] - read-write - - - GPIO8_EDGE_HIGH - [3:3] - read-write - - - GPIO8_EDGE_LOW - [2:2] - read-write - - - GPIO8_LEVEL_HIGH - [1:1] - read-write - - - GPIO8_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF2 - Interrupt Force for dormant_wake - 0x0178 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-write - - - GPIO23_EDGE_LOW - [30:30] - read-write - - - GPIO23_LEVEL_HIGH - [29:29] - read-write - - - GPIO23_LEVEL_LOW - [28:28] - read-write - - - GPIO22_EDGE_HIGH - [27:27] - read-write - - - GPIO22_EDGE_LOW - [26:26] - read-write - - - GPIO22_LEVEL_HIGH - [25:25] - read-write - - - GPIO22_LEVEL_LOW - [24:24] - read-write - - - GPIO21_EDGE_HIGH - [23:23] - read-write - - - GPIO21_EDGE_LOW - [22:22] - read-write - - - GPIO21_LEVEL_HIGH - [21:21] - read-write - - - GPIO21_LEVEL_LOW - [20:20] - read-write - - - GPIO20_EDGE_HIGH - [19:19] - read-write - - - GPIO20_EDGE_LOW - [18:18] - read-write - - - GPIO20_LEVEL_HIGH - [17:17] - read-write - - - GPIO20_LEVEL_LOW - [16:16] - read-write - - - GPIO19_EDGE_HIGH - [15:15] - read-write - - - GPIO19_EDGE_LOW - [14:14] - read-write - - - GPIO19_LEVEL_HIGH - [13:13] - read-write - - - GPIO19_LEVEL_LOW - [12:12] - read-write - - - GPIO18_EDGE_HIGH - [11:11] - read-write - - - GPIO18_EDGE_LOW - [10:10] - read-write - - - GPIO18_LEVEL_HIGH - [9:9] - read-write - - - GPIO18_LEVEL_LOW - [8:8] - read-write - - - GPIO17_EDGE_HIGH - [7:7] - read-write - - - GPIO17_EDGE_LOW - [6:6] - read-write - - - GPIO17_LEVEL_HIGH - [5:5] - read-write - - - GPIO17_LEVEL_LOW - [4:4] - read-write - - - GPIO16_EDGE_HIGH - [3:3] - read-write - - - GPIO16_EDGE_LOW - [2:2] - read-write - - - GPIO16_LEVEL_HIGH - [1:1] - read-write - - - GPIO16_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF3 - Interrupt Force for dormant_wake - 0x017c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-write - - - GPIO29_EDGE_LOW - [22:22] - read-write - - - GPIO29_LEVEL_HIGH - [21:21] - read-write - - - GPIO29_LEVEL_LOW - [20:20] - read-write - - - GPIO28_EDGE_HIGH - [19:19] - read-write - - - GPIO28_EDGE_LOW - [18:18] - read-write - - - GPIO28_LEVEL_HIGH - [17:17] - read-write - - - GPIO28_LEVEL_LOW - [16:16] - read-write - - - GPIO27_EDGE_HIGH - [15:15] - read-write - - - GPIO27_EDGE_LOW - [14:14] - read-write - - - GPIO27_LEVEL_HIGH - [13:13] - read-write - - - GPIO27_LEVEL_LOW - [12:12] - read-write - - - GPIO26_EDGE_HIGH - [11:11] - read-write - - - GPIO26_EDGE_LOW - [10:10] - read-write - - - GPIO26_LEVEL_HIGH - [9:9] - read-write - - - GPIO26_LEVEL_LOW - [8:8] - read-write - - - GPIO25_EDGE_HIGH - [7:7] - read-write - - - GPIO25_EDGE_LOW - [6:6] - read-write - - - GPIO25_LEVEL_HIGH - [5:5] - read-write - - - GPIO25_LEVEL_LOW - [4:4] - read-write - - - GPIO24_EDGE_HIGH - [3:3] - read-write - - - GPIO24_EDGE_LOW - [2:2] - read-write - - - GPIO24_LEVEL_HIGH - [1:1] - read-write - - - GPIO24_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS0 - Interrupt status after masking & forcing for dormant_wake - 0x0180 - 0x00000000 - - - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH - [23:23] - read-only - - - GPIO5_EDGE_LOW - [22:22] - read-only - - - GPIO5_LEVEL_HIGH - [21:21] - read-only - - - GPIO5_LEVEL_LOW - [20:20] - read-only - - - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH - [11:11] - read-only - - - GPIO2_EDGE_LOW - [10:10] - read-only - - - GPIO2_LEVEL_HIGH - [9:9] - read-only - - - GPIO2_LEVEL_LOW - [8:8] - read-only - - - GPIO1_EDGE_HIGH - [7:7] - read-only - - - GPIO1_EDGE_LOW - [6:6] - read-only - - - GPIO1_LEVEL_HIGH - [5:5] - read-only - - - GPIO1_LEVEL_LOW - [4:4] - read-only - - - GPIO0_EDGE_HIGH - [3:3] - read-only - - - GPIO0_EDGE_LOW - [2:2] - read-only - - - GPIO0_LEVEL_HIGH - [1:1] - read-only - - - GPIO0_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS1 - Interrupt status after masking & forcing for dormant_wake - 0x0184 - 0x00000000 - - - GPIO15_EDGE_HIGH - [31:31] - read-only - - - GPIO15_EDGE_LOW - [30:30] - read-only - - - GPIO15_LEVEL_HIGH - [29:29] - read-only - - - GPIO15_LEVEL_LOW - [28:28] - read-only - - - GPIO14_EDGE_HIGH - [27:27] - read-only - - - GPIO14_EDGE_LOW - [26:26] - read-only - - - GPIO14_LEVEL_HIGH - [25:25] - read-only - - - GPIO14_LEVEL_LOW - [24:24] - read-only - - - GPIO13_EDGE_HIGH - [23:23] - read-only - - - GPIO13_EDGE_LOW - [22:22] - read-only - - - GPIO13_LEVEL_HIGH - [21:21] - read-only - - - GPIO13_LEVEL_LOW - [20:20] - read-only - - - GPIO12_EDGE_HIGH - [19:19] - read-only - - - GPIO12_EDGE_LOW - [18:18] - read-only - - - GPIO12_LEVEL_HIGH - [17:17] - read-only - - - GPIO12_LEVEL_LOW - [16:16] - read-only - - - GPIO11_EDGE_HIGH - [15:15] - read-only - - - GPIO11_EDGE_LOW - [14:14] - read-only - - - GPIO11_LEVEL_HIGH - [13:13] - read-only - - - GPIO11_LEVEL_LOW - [12:12] - read-only - - - GPIO10_EDGE_HIGH - [11:11] - read-only - - - GPIO10_EDGE_LOW - [10:10] - read-only - - - GPIO10_LEVEL_HIGH - [9:9] - read-only - - - GPIO10_LEVEL_LOW - [8:8] - read-only - - - GPIO9_EDGE_HIGH - [7:7] - read-only - - - GPIO9_EDGE_LOW - [6:6] - read-only - - - GPIO9_LEVEL_HIGH - [5:5] - read-only - - - GPIO9_LEVEL_LOW - [4:4] - read-only - - - GPIO8_EDGE_HIGH - [3:3] - read-only - - - GPIO8_EDGE_LOW - [2:2] - read-only - - - GPIO8_LEVEL_HIGH - [1:1] - read-only - - - GPIO8_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS2 - Interrupt status after masking & forcing for dormant_wake - 0x0188 - 0x00000000 - - - GPIO23_EDGE_HIGH - [31:31] - read-only - - - GPIO23_EDGE_LOW - [30:30] - read-only - - - GPIO23_LEVEL_HIGH - [29:29] - read-only - - - GPIO23_LEVEL_LOW - [28:28] - read-only - - - GPIO22_EDGE_HIGH - [27:27] - read-only - - - GPIO22_EDGE_LOW - [26:26] - read-only - - - GPIO22_LEVEL_HIGH - [25:25] - read-only - - - GPIO22_LEVEL_LOW - [24:24] - read-only - - - GPIO21_EDGE_HIGH - [23:23] - read-only - - - GPIO21_EDGE_LOW - [22:22] - read-only - - - GPIO21_LEVEL_HIGH - [21:21] - read-only - - - GPIO21_LEVEL_LOW - [20:20] - read-only - - - GPIO20_EDGE_HIGH - [19:19] - read-only - - - GPIO20_EDGE_LOW - [18:18] - read-only - - - GPIO20_LEVEL_HIGH - [17:17] - read-only - - - GPIO20_LEVEL_LOW - [16:16] - read-only - - - GPIO19_EDGE_HIGH - [15:15] - read-only - - - GPIO19_EDGE_LOW - [14:14] - read-only - - - GPIO19_LEVEL_HIGH - [13:13] - read-only - - - GPIO19_LEVEL_LOW - [12:12] - read-only - - - GPIO18_EDGE_HIGH - [11:11] - read-only - - - GPIO18_EDGE_LOW - [10:10] - read-only - - - GPIO18_LEVEL_HIGH - [9:9] - read-only - - - GPIO18_LEVEL_LOW - [8:8] - read-only - - - GPIO17_EDGE_HIGH - [7:7] - read-only - - - GPIO17_EDGE_LOW - [6:6] - read-only - - - GPIO17_LEVEL_HIGH - [5:5] - read-only - - - GPIO17_LEVEL_LOW - [4:4] - read-only - - - GPIO16_EDGE_HIGH - [3:3] - read-only - - - GPIO16_EDGE_LOW - [2:2] - read-only - - - GPIO16_LEVEL_HIGH - [1:1] - read-only - - - GPIO16_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTS3 - Interrupt status after masking & forcing for dormant_wake - 0x018c - 0x00000000 - - - GPIO29_EDGE_HIGH - [23:23] - read-only - - - GPIO29_EDGE_LOW - [22:22] - read-only - - - GPIO29_LEVEL_HIGH - [21:21] - read-only - - - GPIO29_LEVEL_LOW - [20:20] - read-only - - - GPIO28_EDGE_HIGH - [19:19] - read-only - - - GPIO28_EDGE_LOW - [18:18] - read-only - - - GPIO28_LEVEL_HIGH - [17:17] - read-only - - - GPIO28_LEVEL_LOW - [16:16] - read-only - - - GPIO27_EDGE_HIGH - [15:15] - read-only - - - GPIO27_EDGE_LOW - [14:14] - read-only - - - GPIO27_LEVEL_HIGH - [13:13] - read-only - - - GPIO27_LEVEL_LOW - [12:12] - read-only - - - GPIO26_EDGE_HIGH - [11:11] - read-only - - - GPIO26_EDGE_LOW - [10:10] - read-only - - - GPIO26_LEVEL_HIGH - [9:9] - read-only - - - GPIO26_LEVEL_LOW - [8:8] - read-only - - - GPIO25_EDGE_HIGH - [7:7] - read-only - - - GPIO25_EDGE_LOW - [6:6] - read-only - - - GPIO25_LEVEL_HIGH - [5:5] - read-only - - - GPIO25_LEVEL_LOW - [4:4] - read-only - - - GPIO24_EDGE_HIGH - [3:3] - read-only - - - GPIO24_EDGE_LOW - [2:2] - read-only - - - GPIO24_LEVEL_HIGH - [1:1] - read-only - - - GPIO24_LEVEL_LOW - [0:0] - read-only - - - - - - - IO_QSPI - 1 - 0x40018000 - 32 - - 0 - 0x1000 - registers - - - IO_IRQ_QSPI - 14 - - - - GPIO_QSPI_SCLK_STATUS - GPIO status - 0x0000 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SCLK_CTRL - GPIO control including function select and overrides. - 0x0004 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - xip_sclk - 0 - - - sio_30 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SS_STATUS - GPIO status - 0x0008 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SS_CTRL - GPIO control including function select and overrides. - 0x000c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - xip_ss_n - 0 - - - sio_31 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD0_STATUS - GPIO status - 0x0010 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD0_CTRL - GPIO control including function select and overrides. - 0x0014 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - xip_sd0 - 0 - - - sio_32 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD1_STATUS - GPIO status - 0x0018 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD1_CTRL - GPIO control including function select and overrides. - 0x001c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - xip_sd1 - 0 - - - sio_33 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD2_STATUS - GPIO status - 0x0020 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD2_CTRL - GPIO control including function select and overrides. - 0x0024 - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - xip_sd2 - 0 - - - sio_34 - 5 - - - null - 31 - - - - - - - GPIO_QSPI_SD3_STATUS - GPIO status - 0x0028 - 0x00000000 - - - IRQTOPROC - interrupt to processors, after override is applied - [26:26] - read-only - - - IRQFROMPAD - interrupt from pad before override is applied - [24:24] - read-only - - - INTOPERI - input signal to peripheral, after override is applied - [19:19] - read-only - - - INFROMPAD - input signal from pad, before override is applied - [17:17] - read-only - - - OETOPAD - output enable to pad after register override is applied - [13:13] - read-only - - - OEFROMPERI - output enable from selected peripheral, before register override is applied - [12:12] - read-only - - - OUTTOPAD - output signal to pad after register override is applied - [9:9] - read-only - - - OUTFROMPERI - output signal from selected peripheral, before register override is applied - [8:8] - read-only - - - - - GPIO_QSPI_SD3_CTRL - GPIO control including function select and overrides. - 0x002c - 0x0000001f - - - IRQOVER - [29:28] - read-write - - - NORMAL - don't invert the interrupt - 0 - - - INVERT - invert the interrupt - 1 - - - LOW - drive interrupt low - 2 - - - HIGH - drive interrupt high - 3 - - - - - INOVER - [17:16] - read-write - - - NORMAL - don't invert the peri input - 0 - - - INVERT - invert the peri input - 1 - - - LOW - drive peri input low - 2 - - - HIGH - drive peri input high - 3 - - - - - OEOVER - [13:12] - read-write - - - NORMAL - drive output enable from peripheral signal selected by funcsel - 0 - - - INVERT - drive output enable from inverse of peripheral signal selected by funcsel - 1 - - - DISABLE - disable output - 2 - - - ENABLE - enable output - 3 - - - - - OUTOVER - [9:8] - read-write - - - NORMAL - drive output from peripheral signal selected by funcsel - 0 - - - INVERT - drive output from inverse of peripheral signal selected by funcsel - 1 - - - LOW - drive output low - 2 - - - HIGH - drive output high - 3 - - - - - FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL - [4:0] - read-write - - - xip_sd3 - 0 - - - sio_35 - 5 - - - null - 31 - - - - - - - INTR - Raw Interrupts - 0x0030 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - oneToClear - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - oneToClear - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - oneToClear - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - oneToClear - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - oneToClear - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - oneToClear - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - oneToClear - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - oneToClear - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - oneToClear - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - oneToClear - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - oneToClear - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - oneToClear - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - PROC0_INTE - Interrupt Enable for proc0 - 0x0034 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTF - Interrupt Force for proc0 - 0x0038 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC0_INTS - Interrupt status after masking & forcing for proc0 - 0x003c - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - PROC1_INTE - Interrupt Enable for proc1 - 0x0040 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTF - Interrupt Force for proc1 - 0x0044 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - PROC1_INTS - Interrupt status after masking & forcing for proc1 - 0x0048 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - DORMANT_WAKE_INTE - Interrupt Enable for dormant_wake - 0x004c - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTF - Interrupt Force for dormant_wake - 0x0050 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-write - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-write - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-write - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-write - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-write - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-write - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-write - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-write - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-write - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-write - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-write - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-write - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-write - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-write - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-write - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-write - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-write - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-write - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-write - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-write - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-write - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-write - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-write - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-write - - - - - DORMANT_WAKE_INTS - Interrupt status after masking & forcing for dormant_wake - 0x0054 - 0x00000000 - - - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] - read-only - - - GPIO_QSPI_SD3_EDGE_LOW - [22:22] - read-only - - - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] - read-only - - - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] - read-only - - - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] - read-only - - - GPIO_QSPI_SD2_EDGE_LOW - [18:18] - read-only - - - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] - read-only - - - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only - - - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] - read-only - - - GPIO_QSPI_SD1_EDGE_LOW - [14:14] - read-only - - - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] - read-only - - - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] - read-only - - - GPIO_QSPI_SD0_EDGE_HIGH - [11:11] - read-only - - - GPIO_QSPI_SD0_EDGE_LOW - [10:10] - read-only - - - GPIO_QSPI_SD0_LEVEL_HIGH - [9:9] - read-only - - - GPIO_QSPI_SD0_LEVEL_LOW - [8:8] - read-only - - - GPIO_QSPI_SS_EDGE_HIGH - [7:7] - read-only - - - GPIO_QSPI_SS_EDGE_LOW - [6:6] - read-only - - - GPIO_QSPI_SS_LEVEL_HIGH - [5:5] - read-only - - - GPIO_QSPI_SS_LEVEL_LOW - [4:4] - read-only - - - GPIO_QSPI_SCLK_EDGE_HIGH - [3:3] - read-only - - - GPIO_QSPI_SCLK_EDGE_LOW - [2:2] - read-only - - - GPIO_QSPI_SCLK_LEVEL_HIGH - [1:1] - read-only - - - GPIO_QSPI_SCLK_LEVEL_LOW - [0:0] - read-only - - - - - - - PADS_BANK0 - 1 - 0x4001c000 - 32 - - 0 - 0x1000 - registers - - - - VOLTAGE_SELECT - Voltage select. Per bank control - 0x0000 - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - - - - - - GPIO0 - Pad control register - 0x0004 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO1 - Pad control register - 0x0008 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO2 - Pad control register - 0x000c - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO3 - Pad control register - 0x0010 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO4 - Pad control register - 0x0014 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO5 - Pad control register - 0x0018 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO6 - Pad control register - 0x001c - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO7 - Pad control register - 0x0020 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO8 - Pad control register - 0x0024 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO9 - Pad control register - 0x0028 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO10 - Pad control register - 0x002c - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO11 - Pad control register - 0x0030 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO12 - Pad control register - 0x0034 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO13 - Pad control register - 0x0038 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO14 - Pad control register - 0x003c - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO15 - Pad control register - 0x0040 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO16 - Pad control register - 0x0044 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO17 - Pad control register - 0x0048 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO18 - Pad control register - 0x004c - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO19 - Pad control register - 0x0050 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO20 - Pad control register - 0x0054 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO21 - Pad control register - 0x0058 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO22 - Pad control register - 0x005c - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO23 - Pad control register - 0x0060 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO24 - Pad control register - 0x0064 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO25 - Pad control register - 0x0068 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO26 - Pad control register - 0x006c - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO27 - Pad control register - 0x0070 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO28 - Pad control register - 0x0074 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO29 - Pad control register - 0x0078 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWCLK - Pad control register - 0x007c - 0x000000da - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - SWD - Pad control register - 0x0080 - 0x0000005a - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - PADS_QSPI - 1 - 0x40020000 - 32 - - 0 - 0x1000 - registers - - - - VOLTAGE_SELECT - Voltage select. Per bank control - 0x0000 - 0x00000000 - - - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - - - - - - GPIO_QSPI_SCLK - Pad control register - 0x0004 - 0x00000056 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD0 - Pad control register - 0x0008 - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD1 - Pad control register - 0x000c - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD2 - Pad control register - 0x0010 - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SD3 - Pad control register - 0x0014 - 0x00000052 - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - GPIO_QSPI_SS - Pad control register - 0x0018 - 0x0000005a - - - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] - read-write - - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - - - PUE - Pull up enable - [3:3] - read-write - - - PDE - Pull down enable - [2:2] - read-write - - - SCHMITT - Enable schmitt trigger - [1:1] - read-write - - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - - - XOSC - 1 - Controls the crystal oscillator - 0x40024000 - 32 - - 0 - 0x1000 - registers - - - - CTRL - Crystal Oscillator Control - 0x0000 - 0x00000000 - - - ENABLE - On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Frequency range. This resets to 0xAA0 and cannot be changed. - [11:0] - read-write - - - 1_15MHZ - 2720 - - - RESERVED_1 - 2721 - - - RESERVED_2 - 2722 - - - RESERVED_3 - 2723 - - - - - - - STATUS - Crystal Oscillator Status - 0x0004 - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT - [24:24] - read-write - oneToClear - - - ENABLED - Oscillator is enabled but not necessarily running and stable, resets to 0 - [12:12] - read-only - - - FREQ_RANGE - The current frequency range setting, always reads 0 - [1:0] - read-only - - - 1_15MHZ - 0 - - - RESERVED_1 - 1 - - - RESERVED_2 - 2 - - - RESERVED_3 - 3 - - - - - - - DORMANT - Crystal Oscillator pause control\n - This is used to save power by pausing the XOSC\n - On power-up this field is initialised to WAKE\n - An invalid write will also select WAKE\n - WARNING: stop the PLLs before selecting dormant mode\n - WARNING: setup the irq before selecting dormant mode - 0x0008 - read-write - 0x00000000 - - - STARTUP - Controls the startup delay - 0x000c - 0x000000c4 - - - X4 - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. - [20:20] - read-write - - - DELAY - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. - [13:0] - read-write - - - - - COUNT - A down counter running at the xosc frequency which counts to zero and stops.\n - To start the counter write a non-zero value.\n - Can be used for short software pauses when setting up time sensitive hardware. - 0x001c - 0x00000000 - - - COUNT - [7:0] - read-write - - - - - - - PLL_SYS - 1 - 0x40028000 - 32 - - 0 - 0x1000 - registers - - - - CS - Control and Status\n - GENERAL CONSTRAINTS:\n - Reference clock frequency min=5MHz, max=800MHz\n - Feedback divider min=16, max=320\n - VCO frequency min=750MHz, max=1600MHz - 0x0000 - 0x00000001 - - - LOCK - PLL is locked - [31:31] - read-only - - - BYPASS - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. - [8:8] - read-write - - - REFDIV - Divides the PLL input reference clock.\n - Behaviour is undefined for div=0.\n - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. - [5:0] - read-write - - - - - PWR - Controls the PLL power modes. - 0x0004 - 0x0000002d - - - VCOPD - PLL VCO powerdown\n - To save power set high when PLL output not required or bypass=1. - [5:5] - read-write - - - POSTDIVPD - PLL post divider powerdown\n - To save power set high when PLL output not required or bypass=1. - [3:3] - read-write - - - DSMPD - PLL DSM powerdown\n - Nothing is achieved by setting this low. - [2:2] - read-write - - - PD - PLL powerdown\n - To save power set high when PLL output not required. - [0:0] - read-write - - - - - FBDIV_INT - Feedback divisor\n - (note: this PLL does not support fractional division) - 0x0008 - 0x00000000 - - - FBDIV_INT - see ctrl reg description for constraints - [11:0] - read-write - - - - - PRIM - Controls the PLL post dividers for the primary output\n - (note: this PLL does not have a secondary output)\n - the primary output is driven from VCO divided by postdiv1*postdiv2 - 0x000c - 0x00077000 - - - POSTDIV1 - divide by 1-7 - [18:16] - read-write - - - POSTDIV2 - divide by 1-7 - [14:12] - read-write - - - - - - - PLL_USB - 0x4002c000 - - - BUSCTRL - 1 - Register block for busfabric control signals and performance counters - 0x40030000 - 32 - - 0 - 0x1000 - registers - - - - BUS_PRIORITY - Set the priority of each master for bus arbitration. - 0x0000 - 0x00000000 - - - DMA_W - 0 - low priority, 1 - high priority - [12:12] - read-write - - - DMA_R - 0 - low priority, 1 - high priority - [8:8] - read-write - - - PROC1 - 0 - low priority, 1 - high priority - [4:4] - read-write - - - PROC0 - 0 - low priority, 1 - high priority - [0:0] - read-write - - - - - BUS_PRIORITY_ACK - Bus priority acknowledge - 0x0004 - 0x00000000 - - - BUS_PRIORITY_ACK - Goes to 1 once all arbiters have registered the new global priority levels.\n - Arbiters update their local priority when servicing a new nonsequential access.\n - In normal circumstances this will happen almost immediately. - [0:0] - read-only - - - - - PERFCTR0 - Bus fabric performance counter 0 - 0x0008 - 0x00000000 - - - PERFCTR0 - Busfabric saturating performance counter 0\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL0 - [23:0] - read-write - oneToClear - - - - - PERFSEL0 - Bus fabric performance event select for PERFCTR0 - 0x000c - 0x0000001f - - - PERFSEL0 - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR1 - Bus fabric performance counter 1 - 0x0010 - 0x00000000 - - - PERFCTR1 - Busfabric saturating performance counter 1\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL1 - [23:0] - read-write - oneToClear - - - - - PERFSEL1 - Bus fabric performance event select for PERFCTR1 - 0x0014 - 0x0000001f - - - PERFSEL1 - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR2 - Bus fabric performance counter 2 - 0x0018 - 0x00000000 - - - PERFCTR2 - Busfabric saturating performance counter 2\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL2 - [23:0] - read-write - oneToClear - - - - - PERFSEL2 - Bus fabric performance event select for PERFCTR2 - 0x001c - 0x0000001f - - - PERFSEL2 - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - PERFCTR3 - Bus fabric performance counter 3 - 0x0020 - 0x00000000 - - - PERFCTR3 - Busfabric saturating performance counter 3\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL3 - [23:0] - read-write - oneToClear - - - - - PERFSEL3 - Bus fabric performance event select for PERFCTR3 - 0x0024 - 0x0000001f - - - PERFSEL3 - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - - - - - - - UART0 - 1 - 0x40034000 - 32 - - 0 - 0x1000 - registers - - - UART0_IRQ - 20 - - - - UARTDR - Data Register, UARTDR - 0x0000 - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. - [11:11] - read-only - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. - [10:10] - read-only - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. - [9:9] - read-only - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. - [8:8] - read-only - - - DATA - Receive (read) data character. Transmit (write) data character. - [7:0] - read-write - - - - - UARTRSR - Receive Status Register/Error Clear Register, UARTRSR/UARTECR - 0x0004 - 0x00000000 - - - OE - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. - [3:3] - read-write - oneToClear - - - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. - [2:2] - read-write - oneToClear - - - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [1:1] - read-write - oneToClear - - - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. - [0:0] - read-write - oneToClear - - - - - UARTFR - Flag Register, UARTFR - 0x0018 - 0x00000090 - - - RI - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. - [8:8] - read-only - - - TXFE - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. - [7:7] - read-only - - - RXFF - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. - [6:6] - read-only - - - TXFF - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. - [5:5] - read-only - - - RXFE - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. - [4:4] - read-only - - - BUSY - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. - [3:3] - read-only - - - DCD - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. - [2:2] - read-only - - - DSR - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. - [1:1] - read-only - - - CTS - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. - [0:0] - read-only - - - - - UARTILPR - IrDA Low-Power Counter Register, UARTILPR - 0x0020 - 0x00000000 - - - ILPDVSR - 8-bit low-power divisor value. These bits are cleared to 0 at reset. - [7:0] - read-write - - - - - UARTIBRD - Integer Baud Rate Register, UARTIBRD - 0x0024 - 0x00000000 - - - BAUD_DIVINT - The integer baud rate divisor. These bits are cleared to 0 on reset. - [15:0] - read-write - - - - - UARTFBRD - Fractional Baud Rate Register, UARTFBRD - 0x0028 - 0x00000000 - - - BAUD_DIVFRAC - The fractional baud rate divisor. These bits are cleared to 0 on reset. - [5:0] - read-write - - - - - UARTLCR_H - Line Control Register, UARTLCR_H - 0x002c - 0x00000000 - - - SPS - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. - [7:7] - read-write - - - WLEN - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. - [6:5] - read-write - - - FEN - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). - [4:4] - read-write - - - STP2 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. - [3:3] - read-write - - - EPS - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. - [2:2] - read-write - - - PEN - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. - [1:1] - read-write - - - BRK - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. - [0:0] - read-write - - - - - UARTCR - Control Register, UARTCR - 0x0030 - 0x00000300 - - - CTSEN - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. - [15:15] - read-write - - - RTSEN - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. - [14:14] - read-write - - - OUT2 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). - [13:13] - read-write - - - OUT1 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). - [12:12] - read-write - - - RTS - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. - [11:11] - read-write - - - DTR - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. - [10:10] - read-write - - - RXE - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. - [9:9] - read-write - - - TXE - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. - [8:8] - read-write - - - LBE - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. - [7:7] - read-write - - - SIRLP - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. - [2:2] - read-write - - - SIREN - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. - [1:1] - read-write - - - UARTEN - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. - [0:0] - read-write - - - - - UARTIFLS - Interrupt FIFO Level Select Register, UARTIFLS - 0x0034 - 0x00000012 - - - RXIFLSEL - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. - [5:3] - read-write - - - TXIFLSEL - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. - [2:0] - read-write - - - - - UARTIMSC - Interrupt Mask Set/Clear Register, UARTIMSC - 0x0038 - 0x00000000 - - - OEIM - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. - [10:10] - read-write - - - BEIM - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. - [9:9] - read-write - - - PEIM - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. - [8:8] - read-write - - - FEIM - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. - [7:7] - read-write - - - RTIM - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. - [6:6] - read-write - - - TXIM - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. - [5:5] - read-write - - - RXIM - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. - [4:4] - read-write - - - DSRMIM - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. - [3:3] - read-write - - - DCDMIM - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. - [2:2] - read-write - - - CTSMIM - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. - [1:1] - read-write - - - RIMIM - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. - [0:0] - read-write - - - - - UARTRIS - Raw Interrupt Status Register, UARTRIS - 0x003c - 0x00000000 - - - OERIS - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BERIS - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PERIS - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FERIS - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTRIS - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a - [6:6] - read-only - - - TXRIS - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXRIS - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRRMIS - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDRMIS - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSRMIS - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIRMIS - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTMIS - Masked Interrupt Status Register, UARTMIS - 0x0040 - 0x00000000 - - - OEMIS - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BEMIS - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PEMIS - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FEMIS - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTMIS - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. - [6:6] - read-only - - - TXMIS - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXMIS - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRMMIS - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only - - - DCDMMIS - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only - - - CTSMMIS - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. - [1:1] - read-only - - - RIMMIS - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. - [0:0] - read-only - - - - - UARTICR - Interrupt Clear Register, UARTICR - 0x0044 - 0x00000000 - - - OEIC - Overrun error interrupt clear. Clears the UARTOEINTR interrupt. - [10:10] - read-write - oneToClear - - - BEIC - Break error interrupt clear. Clears the UARTBEINTR interrupt. - [9:9] - read-write - oneToClear - - - PEIC - Parity error interrupt clear. Clears the UARTPEINTR interrupt. - [8:8] - read-write - oneToClear - - - FEIC - Framing error interrupt clear. Clears the UARTFEINTR interrupt. - [7:7] - read-write - oneToClear - - - RTIC - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. - [6:6] - read-write - oneToClear - - - TXIC - Transmit interrupt clear. Clears the UARTTXINTR interrupt. - [5:5] - read-write - oneToClear - - - RXIC - Receive interrupt clear. Clears the UARTRXINTR interrupt. - [4:4] - read-write - oneToClear - - - DSRMIC - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. - [3:3] - read-write - oneToClear - - - DCDMIC - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. - [2:2] - read-write - oneToClear - - - CTSMIC - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. - [1:1] - read-write - oneToClear - - - RIMIC - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. - [0:0] - read-write - oneToClear - - - - - UARTDMACR - DMA Control Register, UARTDMACR - 0x0048 - 0x00000000 - - - DMAONERR - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - [2:2] - read-write - - - TXDMAE - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - UARTPERIPHID0 - UARTPeriphID0 Register - 0x0fe0 - 0x00000011 - - - PARTNUMBER0 - These bits read back as 0x11 - [7:0] - read-only - - - - - UARTPERIPHID1 - UARTPeriphID1 Register - 0x0fe4 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - UARTPERIPHID2 - UARTPeriphID2 Register - 0x0fe8 - 0x00000034 - - - REVISION - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - UARTPERIPHID3 - UARTPeriphID3 Register - 0x0fec - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - UARTPCELLID0 - UARTPCellID0 Register - 0x0ff0 - 0x0000000d - - - UARTPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - UARTPCELLID1 - UARTPCellID1 Register - 0x0ff4 - 0x000000f0 - - - UARTPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - UARTPCELLID2 - UARTPCellID2 Register - 0x0ff8 - 0x00000005 - - - UARTPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - UARTPCELLID3 - UARTPCellID3 Register - 0x0ffc - 0x000000b1 - - - UARTPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - UART1 - 0x40038000 - - UART1_IRQ - 21 - - - - SPI0 - 1 - 0x4003c000 - 32 - - 0 - 0x1000 - registers - - - SPI0_IRQ - 18 - - - - SSPCR0 - Control register 0, SSPCR0 on page 3-4 - 0x0000 - 0x00000000 - - - SCR - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. - [15:8] - read-write - - - SPH - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [7:7] - read-write - - - SPO - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [6:6] - read-write - - - FRF - Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. - [5:4] - read-write - - - DSS - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. - [3:0] - read-write - - - - - SSPCR1 - Control register 1, SSPCR1 on page 3-5 - 0x0004 - 0x00000000 - - - SOD - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. - [3:3] - read-write - - - MS - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. - [2:2] - read-write - - - SSE - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. - [1:1] - read-write - - - LBM - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. - [0:0] - read-write - - - - - SSPDR - Data register, SSPDR on page 3-6 - 0x0008 - 0x00000000 - - - DATA - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. - [15:0] - read-write - - - - - SSPSR - Status register, SSPSR on page 3-7 - 0x000c - 0x00000003 - - - BSY - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. - [4:4] - read-only - - - RFF - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. - [3:3] - read-only - - - RNE - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. - [2:2] - read-only - - - TNF - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. - [1:1] - read-only - - - TFE - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. - [0:0] - read-only - - - - - SSPCPSR - Clock prescale register, SSPCPSR on page 3-8 - 0x0010 - 0x00000000 - - - CPSDVSR - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. - [7:0] - read-write - - - - - SSPIMSC - Interrupt mask set or clear register, SSPIMSC on page 3-9 - 0x0014 - 0x00000000 - - - TXIM - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. - [3:3] - read-write - - - RXIM - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. - [2:2] - read-write - - - RTIM - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. - [1:1] - read-write - - - RORIM - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. - [0:0] - read-write - - - - - SSPRIS - Raw interrupt status register, SSPRIS on page 3-10 - 0x0018 - 0x00000008 - - - TXRIS - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXRIS - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTRIS - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORRIS - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPMIS - Masked interrupt status register, SSPMIS on page 3-11 - 0x001c - 0x00000000 - - - TXMIS - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - [3:3] - read-only - - - RXMIS - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - [2:2] - read-only - - - RTMIS - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - [1:1] - read-only - - - RORMIS - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt - [0:0] - read-only - - - - - SSPICR - Interrupt clear register, SSPICR on page 3-11 - 0x0020 - 0x00000000 - - - RTIC - Clears the SSPRTINTR interrupt - [1:1] - read-write - oneToClear - - - RORIC - Clears the SSPRORINTR interrupt - [0:0] - read-write - oneToClear - - - - - SSPDMACR - DMA control register, SSPDMACR on page 3-12 - 0x0024 - 0x00000000 - - - TXDMAE - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] - read-write - - - - - SSPPERIPHID0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x0fe0 - 0x00000022 - - - PARTNUMBER0 - These bits read back as 0x22 - [7:0] - read-only - - - - - SSPPERIPHID1 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x0fe4 - 0x00000010 - - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only - - - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - SSPPERIPHID2 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x0fe8 - 0x00000034 - - - REVISION - These bits return the peripheral revision - [7:4] - read-only - - - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only - - - - - SSPPERIPHID3 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0x0fec - 0x00000000 - - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only - - - - - SSPPCELLID0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x0ff0 - 0x0000000d - - - SSPPCELLID0 - These bits read back as 0x0D - [7:0] - read-only - - - - - SSPPCELLID1 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x0ff4 - 0x000000f0 - - - SSPPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only - - - - - SSPPCELLID2 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x0ff8 - 0x00000005 - - - SSPPCELLID2 - These bits read back as 0x05 - [7:0] - read-only - - - - - SSPPCELLID3 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0x0ffc - 0x000000b1 - - - SSPPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only - - - - - - - SPI1 - 0x40040000 - - SPI1_IRQ - 19 - - - - I2C0 - 1 - DW_apb_i2c address block\n\n - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n - IC_ULTRA_FAST_MODE ................ 0x0\n - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n - IC_UFM_SCL_LOW_COUNT .............. 0x0008\n - IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n - IC_TX_TL .......................... 0x0\n - IC_TX_CMD_BLOCK ................... 0x1\n - IC_HAS_DMA ........................ 0x1\n - IC_HAS_ASYNC_FIFO ................. 0x0\n - IC_SMBUS_ARP ...................... 0x0\n - IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n - IC_INTR_IO ........................ 0x1\n - IC_MASTER_MODE .................... 0x1\n - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n - IC_INTR_POL ....................... 0x1\n - IC_OPTIONAL_SAR ................... 0x0\n - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n - IC_DEFAULT_SLAVE_ADDR ............. 0x055\n - IC_DEFAULT_HS_SPKLEN .............. 0x1\n - IC_FS_SCL_HIGH_COUNT .............. 0x0006\n - IC_HS_SCL_LOW_COUNT ............... 0x0008\n - IC_DEVICE_ID_VALUE ................ 0x0\n - IC_10BITADDR_MASTER ............... 0x0\n - IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n - IC_DEFAULT_FS_SPKLEN .............. 0x7\n - IC_ADD_ENCODED_PARAMS ............. 0x0\n - IC_DEFAULT_SDA_HOLD ............... 0x000001\n - IC_DEFAULT_SDA_SETUP .............. 0x64\n - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n - IC_CLOCK_PERIOD ................... 100\n - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n - IC_RESTART_EN ..................... 0x1\n - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n - IC_BUS_CLEAR_FEATURE .............. 0x0\n - IC_CAP_LOADING .................... 100\n - IC_FS_SCL_LOW_COUNT ............... 0x000d\n - APB_DATA_WIDTH .................... 32\n - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n - IC_SLV_DATA_NACK_ONLY ............. 0x1\n - IC_10BITADDR_SLAVE ................ 0x0\n - IC_CLK_TYPE ....................... 0x0\n - IC_SMBUS_UDID_MSB ................. 0x0\n - IC_SMBUS_SUSPEND_ALERT ............ 0x0\n - IC_HS_SCL_HIGH_COUNT .............. 0x0006\n - IC_SLV_RESTART_DET_EN ............. 0x1\n - IC_SMBUS .......................... 0x0\n - IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n - IC_USE_COUNTS ..................... 0x0\n - IC_RX_BUFFER_DEPTH ................ 16\n - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n - IC_RX_FULL_HLD_BUS_EN ............. 0x1\n - IC_SLAVE_DISABLE .................. 0x1\n - IC_RX_TL .......................... 0x0\n - IC_DEVICE_ID ...................... 0x0\n - IC_HC_COUNT_VALUES ................ 0x0\n - I2C_DYNAMIC_TAR_UPDATE ............ 0\n - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n - IC_HS_MASTER_CODE ................. 0x1\n - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n - IC_SS_SCL_HIGH_COUNT .............. 0x0028\n - IC_SS_SCL_LOW_COUNT ............... 0x002f\n - IC_MAX_SPEED_MODE ................. 0x2\n - IC_STAT_FOR_CLK_STRETCH ........... 0x0\n - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n - IC_DEFAULT_UFM_SPKLEN ............. 0x1\n - IC_TX_BUFFER_DEPTH ................ 16 - 0x40044000 - 32 - - 0 - 0x0100 - registers - - - I2C0_IRQ - 23 - - - - IC_CON - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. - 0x0000 - 0x00000065 - - - STOP_DET_IF_MASTER_ACTIVE - Master issues the STOP_DET interrupt irrespective of whether master is active or not - [10:10] - read-only - - - RX_FIFO_FULL_HLD_CTRL - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n - Reset value: 0x0. - [9:9] - read-write - - - DISABLED - Overflow when RX_FIFO is full - 0 - - - ENABLED - Hold bus when RX_FIFO is full - 1 - - - - - TX_EMPTY_CTRL - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0. - [8:8] - read-write - - - DISABLED - Default behaviour of TX_EMPTY interrupt - 0 - - - ENABLED - Controlled generation of TX_EMPTY interrupt - 1 - - - - - STOP_DET_IFADDRESSED - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - [7:7] - read-write - - - DISABLED - slave issues STOP_DET intr always - 0 - - - ENABLED - slave issues STOP_DET intr only if addressed - 1 - - - - - IC_SLAVE_DISABLE - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. - [6:6] - read-write - - - SLAVE_ENABLED - Slave mode is enabled - 0 - - - SLAVE_DISABLED - Slave mode is disabled - 1 - - - - - IC_RESTART_EN - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n - Reset value: ENABLED - [5:5] - read-write - - - DISABLED - Master restart disabled - 0 - - - ENABLED - Master restart enabled - 1 - - - - - IC_10BITADDR_MASTER - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing - [4:4] - read-write - - - ADDR_7BITS - Master 7Bit addressing mode - 0 - - - ADDR_10BITS - Master 10Bit addressing mode - 1 - - - - - IC_10BITADDR_SLAVE - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. - [3:3] - read-write - - - ADDR_7BITS - Slave 7Bit addressing - 0 - - - ADDR_10BITS - Slave 10Bit addressing - 1 - - - - - SPEED - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n - 1: standard mode (100 kbit/s)\n\n - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n - 3: high speed mode (3.4 Mbit/s)\n\n - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 - [2:1] - read-write - - - STANDARD - Standard Speed mode of operation - 1 - - - FAST - Fast or Fast Plus mode of operation - 2 - - - HIGH - High Speed mode of operation - 3 - - - - - MASTER_MODE - This bit controls whether the DW_apb_i2c master is enabled.\n\n - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. - [0:0] - read-write - - - DISABLED - Master mode is disabled - 0 - - - ENABLED - Master mode is enabled - 1 - - - - - - - IC_TAR - I2C Target Address Register\n\n - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. - 0x0004 - 0x00000055 - - - SPECIAL - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 - [11:11] - read-write - - - DISABLED - Disables programming of GENERAL_CALL or START_BYTE transmission - 0 - - - ENABLED - Enables programming of GENERAL_CALL or START_BYTE transmission - 1 - - - - - GC_OR_START - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 - [10:10] - read-write - - - GENERAL_CALL - GENERAL_CALL byte transmission - 0 - - - START_BYTE - START byte transmission - 1 - - - - - IC_TAR - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. - [9:0] - read-write - - - - - IC_SAR - I2C Slave Address Register - 0x0008 - 0x00000055 - - - IC_SAR - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. - [9:0] - read-write - - - - - IC_DATA_CMD - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n - The size of the register changes as follows:\n\n - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. - 0x0010 - 0x00000000 - - - FIRST_DATA_BYTE - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n - Reset value : 0x0\n\n - NOTE: In case of APB_DATA_WIDTH=8,\n\n - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n - 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n - 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. - [11:11] - read-only - - - INACTIVE - Sequential data byte received - 0 - - - ACTIVE - Non sequential data byte received - 1 - - - - - RESTART - This bit controls whether a RESTART is issued before the byte is sent or received.\n\n - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n - Reset value: 0x0 - [10:10] - read-write - clear - - - DISABLE - Don't Issue RESTART before this command - 0 - - - ENABLE - Issue RESTART before this command - 1 - - - - - STOP - This bit controls whether a STOP is issued after the byte is sent or received.\n\n - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 - [9:9] - read-write - clear - - - DISABLE - Don't Issue STOP after this command - 0 - - - ENABLE - Issue STOP after this command - 1 - - - - - CMD - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n - Reset value: 0x0 - [8:8] - read-write - clear - - - WRITE - Master Write Command - 0 - - - READ - Master Read Command - 1 - - - - - DAT - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n - Reset value: 0x0 - [7:0] - read-write - - - - - IC_SS_SCL_HCNT - Standard Speed I2C Clock SCL High Count Register - 0x0014 - 0x00000028 - - - IC_SS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. - [15:0] - read-write - - - - - IC_SS_SCL_LCNT - Standard Speed I2C Clock SCL Low Count Register - 0x0018 - 0x0000002f - - - IC_SS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_HCNT - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - 0x001c - 0x00000006 - - - IC_FS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - [15:0] - read-write - - - - - IC_FS_SCL_LCNT - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - 0x0020 - 0x0000000d - - - IC_FS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. - [15:0] - read-write - - - - - IC_INTR_STAT - I2C Interrupt Status Register\n\n - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - 0x002c - 0x00000000 - - - R_RESTART_DET - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - R_RESTART_DET interrupt is inactive - 0 - - - ACTIVE - R_RESTART_DET interrupt is active - 1 - - - - - R_GEN_CALL - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - R_GEN_CALL interrupt is inactive - 0 - - - ACTIVE - R_GEN_CALL interrupt is active - 1 - - - - - R_START_DET - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - R_START_DET interrupt is inactive - 0 - - - ACTIVE - R_START_DET interrupt is active - 1 - - - - - R_STOP_DET - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n - Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - R_STOP_DET interrupt is inactive - 0 - - - ACTIVE - R_STOP_DET interrupt is active - 1 - - - - - R_ACTIVITY - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - R_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - R_ACTIVITY interrupt is active - 1 - - - - - R_RX_DONE - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - R_RX_DONE interrupt is inactive - 0 - - - ACTIVE - R_RX_DONE interrupt is active - 1 - - - - - R_TX_ABRT - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - R_TX_ABRT interrupt is inactive - 0 - - - ACTIVE - R_TX_ABRT interrupt is active - 1 - - - - - R_RD_REQ - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - R_RD_REQ interrupt is inactive - 0 - - - ACTIVE - R_RD_REQ interrupt is active - 1 - - - - - R_TX_EMPTY - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n - Reset value: 0x0 - [4:4] - read-only - - - INACTIVE - R_TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - R_TX_EMPTY interrupt is active - 1 - - - - - R_TX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - R_TX_OVER interrupt is inactive - 0 - - - ACTIVE - R_TX_OVER interrupt is active - 1 - - - - - R_RX_FULL - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - R_RX_FULL interrupt is inactive - 0 - - - ACTIVE - R_RX_FULL interrupt is active - 1 - - - - - R_RX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - R_RX_OVER interrupt is inactive - 0 - - - ACTIVE - R_RX_OVER interrupt is active - 1 - - - - - R_RX_UNDER - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - - - - - IC_INTR_MASK - I2C Interrupt Mask Register.\n\n - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - 0x0030 - 0x000008ff - - - M_RESTART_DET - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [12:12] - read-write - - - ENABLED - RESTART_DET interrupt is masked - 0 - - - DISABLED - RESTART_DET interrupt is unmasked - 1 - - - - - M_GEN_CALL - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [11:11] - read-write - - - ENABLED - GEN_CALL interrupt is masked - 0 - - - DISABLED - GEN_CALL interrupt is unmasked - 1 - - - - - M_START_DET - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [10:10] - read-write - - - ENABLED - START_DET interrupt is masked - 0 - - - DISABLED - START_DET interrupt is unmasked - 1 - - - - - M_STOP_DET - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [9:9] - read-write - - - ENABLED - STOP_DET interrupt is masked - 0 - - - DISABLED - STOP_DET interrupt is unmasked - 1 - - - - - M_ACTIVITY - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [8:8] - read-write - - - ENABLED - ACTIVITY interrupt is masked - 0 - - - DISABLED - ACTIVITY interrupt is unmasked - 1 - - - - - M_RX_DONE - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [7:7] - read-write - - - ENABLED - RX_DONE interrupt is masked - 0 - - - DISABLED - RX_DONE interrupt is unmasked - 1 - - - - - M_TX_ABRT - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [6:6] - read-write - - - ENABLED - TX_ABORT interrupt is masked - 0 - - - DISABLED - TX_ABORT interrupt is unmasked - 1 - - - - - M_RD_REQ - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [5:5] - read-write - - - ENABLED - RD_REQ interrupt is masked - 0 - - - DISABLED - RD_REQ interrupt is unmasked - 1 - - - - - M_TX_EMPTY - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [4:4] - read-write - - - ENABLED - TX_EMPTY interrupt is masked - 0 - - - DISABLED - TX_EMPTY interrupt is unmasked - 1 - - - - - M_TX_OVER - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [3:3] - read-write - - - ENABLED - TX_OVER interrupt is masked - 0 - - - DISABLED - TX_OVER interrupt is unmasked - 1 - - - - - M_RX_FULL - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [2:2] - read-write - - - ENABLED - RX_FULL interrupt is masked - 0 - - - DISABLED - RX_FULL interrupt is unmasked - 1 - - - - - M_RX_OVER - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [1:1] - read-write - - - ENABLED - RX_OVER interrupt is masked - 0 - - - DISABLED - RX_OVER interrupt is unmasked - 1 - - - - - M_RX_UNDER - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [0:0] - read-write - - - ENABLED - RX_UNDER interrupt is masked - 0 - - - DISABLED - RX_UNDER interrupt is unmasked - 1 - - - - - - - IC_RAW_INTR_STAT - I2C Raw Interrupt Status Register\n\n - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - 0x0034 - 0x00000000 - - - RESTART_DET - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - RESTART_DET interrupt is inactive - 0 - - - ACTIVE - RESTART_DET interrupt is active - 1 - - - - - GEN_CALL - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - GEN_CALL interrupt is inactive - 0 - - - ACTIVE - GEN_CALL interrupt is active - 1 - - - - - START_DET - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - START_DET interrupt is inactive - 0 - - - ACTIVE - START_DET interrupt is active - 1 - - - - - STOP_DET - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n - In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - STOP_DET interrupt is inactive - 0 - - - ACTIVE - STOP_DET interrupt is active - 1 - - - - - ACTIVITY - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - RAW_INTR_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - RAW_INTR_ACTIVITY interrupt is active - 1 - - - - - RX_DONE - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - RX_DONE interrupt is inactive - 0 - - - ACTIVE - RX_DONE interrupt is active - 1 - - - - - TX_ABRT - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - TX_ABRT interrupt is inactive - 0 - - - ACTIVE - TX_ABRT interrupt is active - 1 - - - - - RD_REQ - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - RD_REQ interrupt is inactive - 0 - - - ACTIVE - RD_REQ interrupt is active - 1 - - - - - TX_EMPTY - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n - Reset value: 0x0. - [4:4] - read-only - - - INACTIVE - TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - TX_EMPTY interrupt is active - 1 - - - - - TX_OVER - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Reset value: 0x0 - [3:3] - read-only - - - INACTIVE - TX_OVER interrupt is inactive - 0 - - - ACTIVE - TX_OVER interrupt is active - 1 - - - - - RX_FULL - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - RX_FULL interrupt is inactive - 0 - - - ACTIVE - RX_FULL interrupt is active - 1 - - - - - RX_OVER - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - RX_OVER interrupt is inactive - 0 - - - ACTIVE - RX_OVER interrupt is active - 1 - - - - - RX_UNDER - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - - - - - IC_RX_TL - I2C Receive FIFO Threshold Register - 0x0038 - 0x00000000 - - - RX_TL - Receive FIFO Threshold Level.\n\n - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. - [7:0] - read-write - - - - - IC_TX_TL - I2C Transmit FIFO Threshold Register - 0x003c - 0x00000000 - - - TX_TL - Transmit FIFO Threshold Level.\n\n - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. - [7:0] - read-write - - - - - IC_CLR_INTR - Clear Combined and Individual Interrupt Register - 0x0040 - 0x00000000 - - - CLR_INTR - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_UNDER - Clear RX_UNDER Interrupt Register - 0x0044 - 0x00000000 - - - CLR_RX_UNDER - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_OVER - Clear RX_OVER Interrupt Register - 0x0048 - 0x00000000 - - - CLR_RX_OVER - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_OVER - Clear TX_OVER Interrupt Register - 0x004c - 0x00000000 - - - CLR_TX_OVER - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RD_REQ - Clear RD_REQ Interrupt Register - 0x0050 - 0x00000000 - - - CLR_RD_REQ - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_TX_ABRT - Clear TX_ABRT Interrupt Register - 0x0054 - 0x00000000 - - - CLR_TX_ABRT - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_RX_DONE - Clear RX_DONE Interrupt Register - 0x0058 - 0x00000000 - - - CLR_RX_DONE - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_ACTIVITY - Clear ACTIVITY Interrupt Register - 0x005c - 0x00000000 - - - CLR_ACTIVITY - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_STOP_DET - Clear STOP_DET Interrupt Register - 0x0060 - 0x00000000 - - - CLR_STOP_DET - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_START_DET - Clear START_DET Interrupt Register - 0x0064 - 0x00000000 - - - CLR_START_DET - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_CLR_GEN_CALL - Clear GEN_CALL Interrupt Register - 0x0068 - 0x00000000 - - - CLR_GEN_CALL - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_ENABLE - I2C Enable Register - 0x006c - 0x00000000 - - - TX_CMD_BLOCK - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT - [2:2] - read-write - - - NOT_BLOCKED - Tx Command execution not blocked - 0 - - - BLOCKED - Tx Command execution blocked - 1 - - - - - ABORT - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n - Reset value: 0x0 - [1:1] - read-write - - - DISABLE - ABORT operation not in progress - 0 - - - ENABLED - ABORT operation in progress - 1 - - - - - ENABLE - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n - Reset value: 0x0 - [0:0] - read-write - - - DISABLED - I2C is disabled - 0 - - - ENABLED - I2C is enabled - 1 - - - - - - - IC_STATUS - I2C Status Register\n\n - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - 0x0070 - 0x00000006 - - - SLV_ACTIVITY - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 - [6:6] - read-only - - - IDLE - Slave is idle - 0 - - - ACTIVE - Slave not idle - 1 - - - - - MST_ACTIVITY - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n - Reset value: 0x0 - [5:5] - read-only - - - IDLE - Master is idle - 0 - - - ACTIVE - Master not idle - 1 - - - - - RFF - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 - [4:4] - read-only - - - NOT_FULL - Rx FIFO not full - 0 - - - FULL - Rx FIFO is full - 1 - - - - - RFNE - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 - [3:3] - read-only - - - EMPTY - Rx FIFO is empty - 0 - - - NOT_EMPTY - Rx FIFO not empty - 1 - - - - - TFE - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 - [2:2] - read-only - - - NON_EMPTY - Tx FIFO not empty - 0 - - - EMPTY - Tx FIFO is empty - 1 - - - - - TFNF - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 - [1:1] - read-only - - - FULL - Tx FIFO is full - 0 - - - NOT_FULL - Tx FIFO not full - 1 - - - - - ACTIVITY - I2C Activity Status. Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - I2C is idle - 0 - - - ACTIVE - I2C is active - 1 - - - - - - - IC_TXFLR - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. - 0x0074 - 0x00000000 - - - TXFLR - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n - Reset value: 0x0 - [4:0] - read-only - - - - - IC_RXFLR - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. - 0x0078 - 0x00000000 - - - RXFLR - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n - Reset value: 0x0 - [4:0] - read-only - - - - - IC_SDA_HOLD - I2C SDA Hold Time Length Register\n\n - The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n - The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n - Writes to this register succeed only when IC_ENABLE[0]=0.\n\n - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. - 0x007c - 0x00000001 - - - IC_SDA_RX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n - Reset value: IC_DEFAULT_SDA_HOLD[23:16]. - [23:16] - read-write - - - IC_SDA_TX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n - Reset value: IC_DEFAULT_SDA_HOLD[15:0]. - [15:0] - read-write - - - - - IC_TX_ABRT_SOURCE - I2C Transmit Abort Source Register\n\n - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - 0x0080 - 0x00000000 - - - TX_FLUSH_CNT - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [31:23] - read-only - - - ABRT_USER_ABRT - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [16:16] - read-only - - - ABRT_USER_ABRT_VOID - Transfer abort detected by master- scenario not present - 0 - - - ABRT_USER_ABRT_GENERATED - Transfer abort detected by master - 1 - - - - - ABRT_SLVRD_INTX - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [15:15] - read-only - - - ABRT_SLVRD_INTX_VOID - Slave trying to transmit to remote master in read mode- scenario not present - 0 - - - ABRT_SLVRD_INTX_GENERATED - Slave trying to transmit to remote master in read mode - 1 - - - - - ABRT_SLV_ARBLOST - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [14:14] - read-only - - - ABRT_SLV_ARBLOST_VOID - Slave lost arbitration to remote master- scenario not present - 0 - - - ABRT_SLV_ARBLOST_GENERATED - Slave lost arbitration to remote master - 1 - - - - - ABRT_SLVFLUSH_TXFIFO - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [13:13] - read-only - - - ABRT_SLVFLUSH_TXFIFO_VOID - Slave flushes existing data in TX-FIFO upon getting read command- scenario not present - 0 - - - ABRT_SLVFLUSH_TXFIFO_GENERATED - Slave flushes existing data in TX-FIFO upon getting read command - 1 - - - - - ARB_LOST - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [12:12] - read-only - - - ABRT_LOST_VOID - Master or Slave-Transmitter lost arbitration- scenario not present - 0 - - - ABRT_LOST_GENERATED - Master or Slave-Transmitter lost arbitration - 1 - - - - - ABRT_MASTER_DIS - This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [11:11] - read-only - - - ABRT_MASTER_DIS_VOID - User initiating master operation when MASTER disabled- scenario not present - 0 - - - ABRT_MASTER_DIS_GENERATED - User initiating master operation when MASTER disabled - 1 - - - - - ABRT_10B_RD_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Receiver - [10:10] - read-only - - - ABRT_10B_RD_VOID - Master not trying to read in 10Bit addressing mode when RESTART disabled - 0 - - - ABRT_10B_RD_GENERATED - Master trying to read in 10Bit addressing mode when RESTART disabled - 1 - - - - - ABRT_SBYTE_NORSTRT - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [9:9] - read-only - - - ABRT_SBYTE_NORSTRT_VOID - User trying to send START byte when RESTART disabled- scenario not present - 0 - - - ABRT_SBYTE_NORSTRT_GENERATED - User trying to send START byte when RESTART disabled - 1 - - - - - ABRT_HS_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [8:8] - read-only - - - ABRT_HS_NORSTRT_VOID - User trying to switch Master to HS mode when RESTART disabled- scenario not present - 0 - - - ABRT_HS_NORSTRT_GENERATED - User trying to switch Master to HS mode when RESTART disabled - 1 - - - - - ABRT_SBYTE_ACKDET - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [7:7] - read-only - - - ABRT_SBYTE_ACKDET_VOID - ACK detected for START byte- scenario not present - 0 - - - ABRT_SBYTE_ACKDET_GENERATED - ACK detected for START byte - 1 - - - - - ABRT_HS_ACKDET - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [6:6] - read-only - - - ABRT_HS_ACK_VOID - HS Master code ACKed in HS Mode- scenario not present - 0 - - - ABRT_HS_ACK_GENERATED - HS Master code ACKed in HS Mode - 1 - - - - - ABRT_GCALL_READ - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [5:5] - read-only - - - ABRT_GCALL_READ_VOID - GCALL is followed by read from bus-scenario not present - 0 - - - ABRT_GCALL_READ_GENERATED - GCALL is followed by read from bus - 1 - - - - - ABRT_GCALL_NOACK - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [4:4] - read-only - - - ABRT_GCALL_NOACK_VOID - GCALL not ACKed by any slave-scenario not present - 0 - - - ABRT_GCALL_NOACK_GENERATED - GCALL not ACKed by any slave - 1 - - - - - ABRT_TXDATA_NOACK - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [3:3] - read-only - - - ABRT_TXDATA_NOACK_VOID - Transmitted data non-ACKed by addressed slave-scenario not present - 0 - - - ABRT_TXDATA_NOACK_GENERATED - Transmitted data not ACKed by addressed slave - 1 - - - - - ABRT_10ADDR2_NOACK - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [2:2] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 2 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_10ADDR1_NOACK - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [1:1] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 1 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_7B_ADDR_NOACK - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [0:0] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - This abort is generated because of NOACK for 7-bit address - 1 - - - - - - - IC_SLV_DATA_NACK_ONLY - Generate Slave Data NACK Register\n\n - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. - 0x0084 - 0x00000000 - - - NACK - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 - [0:0] - read-write - - - DISABLED - Slave receiver generates NACK normally - 0 - - - ENABLED - Slave receiver generates NACK upon data reception only - 1 - - - - - - - IC_DMA_CR - DMA Control Register\n\n - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. - 0x0088 - 0x00000000 - - - TDMAE - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 - [1:1] - read-write - - - DISABLED - transmit FIFO DMA channel disabled - 0 - - - ENABLED - Transmit FIFO DMA channel enabled - 1 - - - - - RDMAE - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 - [0:0] - read-write - - - DISABLED - Receive FIFO DMA channel disabled - 0 - - - ENABLED - Receive FIFO DMA channel enabled - 1 - - - - - - - IC_DMA_TDLR - DMA Transmit Data Level Register - 0x008c - 0x00000000 - - - DMATDL - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n - Reset value: 0x0 - [3:0] - read-write - - - - - IC_DMA_RDLR - I2C Receive Data Level Register - 0x0090 - 0x00000000 - - - DMARDL - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n - Reset value: 0x0 - [3:0] - read-write - - - - - IC_SDA_SETUP - I2C SDA Setup Register\n\n - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n - Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n - Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. - 0x0094 - 0x00000064 - - - SDA_SETUP - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. - [7:0] - read-write - - - - - IC_ACK_GENERAL_CALL - I2C ACK General Call Register\n\n - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n - This register is applicable only when the DW_apb_i2c is in slave mode. - 0x0098 - 0x00000001 - - - ACK_GEN_CALL - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). - [0:0] - read-write - - - DISABLED - Generate NACK for a General Call - 0 - - - ENABLED - Generate ACK for a General Call - 1 - - - - - - - IC_ENABLE_STATUS - I2C Enable Status Register\n\n - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n - If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n - Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. - 0x009c - 0x00000000 - - - SLV_RX_DATA_LOST - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - Slave RX Data is not lost - 0 - - - ACTIVE - Slave RX Data is lost - 1 - - - - - SLV_DISABLED_WHILE_BUSY - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n - OR,\n\n - (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - Slave is disabled when it is idle - 0 - - - ACTIVE - Slave is disabled when it is active - 1 - - - - - IC_EN - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n - Reset value: 0x0 - [0:0] - read-only - - - DISABLED - I2C disabled - 0 - - - ENABLED - I2C enabled - 1 - - - - - - - IC_FS_SPKLEN - I2C SS, FS or FM+ spike suppression limit\n\n - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. - 0x00a0 - 0x00000007 - - - IC_FS_SPKLEN - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. - [7:0] - read-write - - - - - IC_CLR_RESTART_DET - Clear RESTART_DET Interrupt Register - 0x00a8 - 0x00000000 - - - CLR_RESTART_DET - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_COMP_PARAM_1 - Component Parameter Register 1\n\n - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - 0x00f4 - 0x00000000 - - - TX_BUFFER_DEPTH - TX Buffer Depth = 16 - [23:16] - read-only - - - RX_BUFFER_DEPTH - RX Buffer Depth = 16 - [15:8] - read-only - - - ADD_ENCODED_PARAMS - Encoded parameters not visible - [7:7] - read-only - - - HAS_DMA - DMA handshaking signals are enabled - [6:6] - read-only - - - INTR_IO - COMBINED Interrupt outputs - [5:5] - read-only - - - HC_COUNT_VALUES - Programmable count values for each mode. - [4:4] - read-only - - - MAX_SPEED_MODE - MAX SPEED MODE = FAST MODE - [3:2] - read-only - - - APB_DATA_WIDTH - APB data bus width is 32 bits - [1:0] - read-only - - - - - IC_COMP_VERSION - I2C Component Version Register - 0x00f8 - 0x3230312a - - - IC_COMP_VERSION - [31:0] - read-only - - - - - IC_COMP_TYPE - I2C Component Type Register - 0x00fc - 0x44570140 - - - IC_COMP_TYPE - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. - [31:0] - read-only - - - - - - - I2C1 - 0x40048000 - - I2C1_IRQ - 24 - - - - ADC - 2 - Control and data interface to SAR ADC - 0x4004c000 - 32 - - 0 - 0x1000 - registers - - - ADC_IRQ_FIFO - 22 - - - - CS - ADC Control and Status - 0x0000 - 0x00000000 - - - RROBIN - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n - The first channel to be sampled will be the one currently indicated by AINSEL.\n - AINSEL will be updated after each conversion with the newly-selected channel. - [20:16] - read-write - - - AINSEL - Select analog mux input. Updated automatically in round-robin mode. - [14:12] - read-write - - - ERR_STICKY - Some past ADC conversion encountered an error. Write 1 to clear. - [10:10] - read-write - oneToClear - - - ERR - The most recent ADC conversion encountered an error; result is undefined or noisy. - [9:9] - read-only - - - READY - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n - 0 whilst conversion in progress. - [8:8] - read-only - - - START_MANY - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. - [3:3] - read-write - - - START_ONCE - Start a single conversion. Self-clearing. Ignored if start_many is asserted. - [2:2] - read-write - clear - - - TS_EN - Power on temperature sensor. 1 - enabled. 0 - disabled. - [1:1] - read-write - - - EN - Power on ADC and enable its clock.\n - 1 - enabled. 0 - disabled. - [0:0] - read-write - - - - - RESULT - Result of most recent ADC conversion - 0x0004 - 0x00000000 - - - RESULT - [11:0] - read-only - - - - - FCS - FIFO control and status - 0x0008 - 0x00000000 - - - THRESH - DREQ/IRQ asserted when level >= threshold - [27:24] - read-write - - - LEVEL - The number of conversion results currently waiting in the FIFO - [19:16] - read-only - - - OVER - 1 if the FIFO has been overflowed. Write 1 to clear. - [11:11] - read-write - oneToClear - - - UNDER - 1 if the FIFO has been underflowed. Write 1 to clear. - [10:10] - read-write - oneToClear - - - FULL - [9:9] - read-only - - - EMPTY - [8:8] - read-only - - - DREQ_EN - If 1: assert DMA requests when FIFO contains data - [3:3] - read-write - - - ERR - If 1: conversion error bit appears in the FIFO alongside the result - [2:2] - read-write - - - SHIFT - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. - [1:1] - read-write - - - EN - If 1: write result to the FIFO after each conversion. - [0:0] - read-write - - - - - FIFO - Conversion result FIFO - 0x000c - 0x00000000 - - - ERR - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. - [15:15] - read-only - - - VAL - [11:0] - read-only - - - - - DIV - Clock divider. If non-zero, CS_START_MANY will start conversions\n - at regular intervals rather than back-to-back.\n - The divider is reset when either of these fields are written.\n - Total period is 1 + INT + FRAC / 256 - 0x0010 - 0x00000000 - - - INT - Integer part of clock divisor. - [23:8] - read-write - - - FRAC - Fractional part of clock divisor. First-order delta-sigma. - [7:0] - read-write - - - - - INTR - Raw Interrupts - 0x0014 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x0018 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x001c - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x0020 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - - - PWM - 1 - Simple PWM - 0x40050000 - 32 - - 0 - 0x1000 - registers - - - PWM_IRQ_WRAP - 4 - - - - CH0_CSR - Control and status register - 0x0000 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH0_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x0004 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH0_CTR - Direct access to the PWM counter - 0x0008 - 0x00000000 - - - CH0_CTR - [15:0] - read-write - - - - - CH0_CC - Counter compare values - 0x000c - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH0_TOP - Counter wrap value - 0x0010 - 0x0000ffff - - - CH0_TOP - [15:0] - read-write - - - - - CH1_CSR - Control and status register - 0x0014 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH1_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x0018 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH1_CTR - Direct access to the PWM counter - 0x001c - 0x00000000 - - - CH1_CTR - [15:0] - read-write - - - - - CH1_CC - Counter compare values - 0x0020 - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH1_TOP - Counter wrap value - 0x0024 - 0x0000ffff - - - CH1_TOP - [15:0] - read-write - - - - - CH2_CSR - Control and status register - 0x0028 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH2_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x002c - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH2_CTR - Direct access to the PWM counter - 0x0030 - 0x00000000 - - - CH2_CTR - [15:0] - read-write - - - - - CH2_CC - Counter compare values - 0x0034 - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH2_TOP - Counter wrap value - 0x0038 - 0x0000ffff - - - CH2_TOP - [15:0] - read-write - - - - - CH3_CSR - Control and status register - 0x003c - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH3_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x0040 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH3_CTR - Direct access to the PWM counter - 0x0044 - 0x00000000 - - - CH3_CTR - [15:0] - read-write - - - - - CH3_CC - Counter compare values - 0x0048 - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH3_TOP - Counter wrap value - 0x004c - 0x0000ffff - - - CH3_TOP - [15:0] - read-write - - - - - CH4_CSR - Control and status register - 0x0050 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH4_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x0054 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH4_CTR - Direct access to the PWM counter - 0x0058 - 0x00000000 - - - CH4_CTR - [15:0] - read-write - - - - - CH4_CC - Counter compare values - 0x005c - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH4_TOP - Counter wrap value - 0x0060 - 0x0000ffff - - - CH4_TOP - [15:0] - read-write - - - - - CH5_CSR - Control and status register - 0x0064 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH5_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x0068 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH5_CTR - Direct access to the PWM counter - 0x006c - 0x00000000 - - - CH5_CTR - [15:0] - read-write - - - - - CH5_CC - Counter compare values - 0x0070 - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH5_TOP - Counter wrap value - 0x0074 - 0x0000ffff - - - CH5_TOP - [15:0] - read-write - - - - - CH6_CSR - Control and status register - 0x0078 - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH6_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x007c - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH6_CTR - Direct access to the PWM counter - 0x0080 - 0x00000000 - - - CH6_CTR - [15:0] - read-write - - - - - CH6_CC - Counter compare values - 0x0084 - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH6_TOP - Counter wrap value - 0x0088 - 0x0000ffff - - - CH6_TOP - [15:0] - read-write - - - - - CH7_CSR - Control and status register - 0x008c - 0x00000000 - - - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] - read-write - clear - - - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] - read-write - clear - - - DIVMODE - [5:4] - read-write - - - div - Free-running counting at rate dictated by fractional divider - 0 - - - level - Fractional divider operation is gated by the PWM B pin. - 1 - - - rise - Counter advances with each rising edge of the PWM B pin. - 2 - - - fall - Counter advances with each falling edge of the PWM B pin. - 3 - - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write - - - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] - read-write - - - EN - Enable the PWM channel. - [0:0] - read-write - - - - - CH7_DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x0090 - 0x00000010 - - - INT - [11:4] - read-write - - - FRAC - [3:0] - read-write - - - - - CH7_CTR - Direct access to the PWM counter - 0x0094 - 0x00000000 - - - CH7_CTR - [15:0] - read-write - - - - - CH7_CC - Counter compare values - 0x0098 - 0x00000000 - - - B - [31:16] - read-write - - - A - [15:0] - read-write - - - - - CH7_TOP - Counter wrap value - 0x009c - 0x0000ffff - - - CH7_TOP - [15:0] - read-write - - - - - EN - This register aliases the CSR_EN bits for all channels.\n - Writing to this register allows multiple channels to be enabled\n - or disabled simultaneously, so they can run in perfect sync.\n - For each channel, there is only one physical EN register bit,\n - which can be accessed through here or CHx_CSR. - 0x00a0 - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0x00a4 - 0x00000000 - - - CH7 - [7:7] - read-write - oneToClear - - - CH6 - [6:6] - read-write - oneToClear - - - CH5 - [5:5] - read-write - oneToClear - - - CH4 - [4:4] - read-write - oneToClear - - - CH3 - [3:3] - read-write - oneToClear - - - CH2 - [2:2] - read-write - oneToClear - - - CH1 - [1:1] - read-write - oneToClear - - - CH0 - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0x00a8 - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x00ac - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x00b0 - 0x00000000 - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - - - TIMER - 1 - Controls time and alarms\n - time is a 64 bit value indicating the time in usec since power-on\n - timeh is the top 32 bits of time & timel is the bottom 32 bits\n - to change time write to timelw before timehw\n - to read time read from timelr before timehr\n - An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n - When an alarm is pending, the corresponding alarm_running signal will be high\n - An alarm can be cancelled before it has finished by clearing the alarm_enable\n - When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n - To clear the interrupt write a 1 to the corresponding alarm_irq - 0x40054000 - 32 - - 0 - 0x1000 - registers - - - TIMER_IRQ_0 - 0 - - - TIMER_IRQ_1 - 1 - - - TIMER_IRQ_2 - 2 - - - TIMER_IRQ_3 - 3 - - - - TIMEHW - Write to bits 63:32 of time\n - always write timelw before timehw - 0x0000 - write-only - 0x00000000 - - - TIMELW - Write to bits 31:0 of time\n - writes do not get copied to time until timehw is written - 0x0004 - write-only - 0x00000000 - - - TIMEHR - Read from bits 63:32 of time\n - always read timelr before timehr - 0x0008 - read-only - 0x00000000 - - - TIMELR - Read from bits 31:0 of time - 0x000c - read-only - 0x00000000 - - - ALARM0 - Arm alarm 0, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x0010 - read-write - 0x00000000 - - - ALARM1 - Arm alarm 1, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x0014 - read-write - 0x00000000 - - - ALARM2 - Arm alarm 2, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x0018 - read-write - 0x00000000 - - - ALARM3 - Arm alarm 3, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x001c - read-write - 0x00000000 - - - ARMED - Indicates the armed/disarmed status of each alarm.\n - A write to the corresponding ALARMx register arms the alarm.\n - Alarms automatically disarm upon firing, but writing ones here\n - will disarm immediately without waiting to fire. - 0x0020 - 0x00000000 - - - ARMED - [3:0] - read-write - oneToClear - - - - - TIMERAWH - Raw read from bits 63:32 of time (no side effects) - 0x0024 - read-only - 0x00000000 - - - TIMERAWL - Raw read from bits 31:0 of time (no side effects) - 0x0028 - read-only - 0x00000000 - - - DBGPAUSE - Set bits high to enable pause when the corresponding debug ports are active - 0x002c - 0x00000007 - - - DBG1 - Pause when processor 1 is in debug mode - [2:2] - read-write - - - DBG0 - Pause when processor 0 is in debug mode - [1:1] - read-write - - - - - PAUSE - Set high to pause the timer - 0x0030 - 0x00000000 - - - PAUSE - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0x0034 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - oneToClear - - - ALARM_2 - [2:2] - read-write - oneToClear - - - ALARM_1 - [1:1] - read-write - oneToClear - - - ALARM_0 - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0x0038 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x003c - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x0040 - 0x00000000 - - - ALARM_3 - [3:3] - read-only - - - ALARM_2 - [2:2] - read-only - - - ALARM_1 - [1:1] - read-only - - - ALARM_0 - [0:0] - read-only - - - - - - - WATCHDOG - 1 - 0x40058000 - 32 - - 0 - 0x1000 - registers - - - - CTRL - Watchdog control\n - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n - The watchdog can be triggered in software. - 0x0000 - 0x07000000 - - - TRIGGER - Trigger a watchdog reset - [31:31] - read-write - clear - - - ENABLE - When not enabled the watchdog timer is paused - [30:30] - read-write - - - PAUSE_DBG1 - Pause the watchdog timer when processor 1 is in debug mode - [26:26] - read-write - - - PAUSE_DBG0 - Pause the watchdog timer when processor 0 is in debug mode - [25:25] - read-write - - - PAUSE_JTAG - Pause the watchdog timer when JTAG is accessing the bus fabric - [24:24] - read-write - - - TIME - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered - [23:0] - read-only - - - - - LOAD - Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). - 0x0004 - 0x00000000 - - - LOAD - [23:0] - write-only - - - - - REASON - Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. - 0x0008 - 0x00000000 - - - FORCE - [1:1] - read-only - - - TIMER - [0:0] - read-only - - - - - SCRATCH0 - Scratch register. Information persists through soft reset of the chip. - 0x000c - read-write - 0x00000000 - - - SCRATCH1 - Scratch register. Information persists through soft reset of the chip. - 0x0010 - read-write - 0x00000000 - - - SCRATCH2 - Scratch register. Information persists through soft reset of the chip. - 0x0014 - read-write - 0x00000000 - - - SCRATCH3 - Scratch register. Information persists through soft reset of the chip. - 0x0018 - read-write - 0x00000000 - - - SCRATCH4 - Scratch register. Information persists through soft reset of the chip. - 0x001c - read-write - 0x00000000 - - - SCRATCH5 - Scratch register. Information persists through soft reset of the chip. - 0x0020 - read-write - 0x00000000 - - - SCRATCH6 - Scratch register. Information persists through soft reset of the chip. - 0x0024 - read-write - 0x00000000 - - - SCRATCH7 - Scratch register. Information persists through soft reset of the chip. - 0x0028 - read-write - 0x00000000 - - - TICK - Controls the tick generator - 0x002c - 0x00000200 - - - COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [19:11] - read-only - - - RUNNING - Is the tick generator running? - [10:10] - read-only - - - ENABLE - start / stop tick generation - [9:9] - read-write - - - CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - - - RTC - 1 - Register block to control RTC - 0x4005c000 - 32 - - 0 - 0x1000 - registers - - - RTC_IRQ - 25 - - - - CLKDIV_M1 - Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. - 0x0000 - 0x00000000 - - - CLKDIV_M1 - [15:0] - read-write - - - - - SETUP_0 - RTC setup register 0 - 0x0004 - 0x00000000 - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - SETUP_1 - RTC setup register 1 - 0x0008 - 0x00000000 - - - DOTW - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - CTRL - RTC Control and status - 0x000c - 0x00000000 - - - FORCE_NOTLEAPYEAR - If set, leapyear is forced off.\n - Useful for years divisible by 100 but not by 400 - [8:8] - read-write - - - LOAD - Load RTC - [4:4] - read-write - clear - - - RTC_ACTIVE - RTC enabled (running) - [1:1] - read-only - - - RTC_ENABLE - Enable RTC - [0:0] - read-write - - - - - IRQ_SETUP_0 - Interrupt setup register 0 - 0x0010 - 0x00000000 - - - MATCH_ACTIVE - [29:29] - read-only - - - MATCH_ENA - Global match enable. Don't change any other value while this one is enabled - [28:28] - read-write - - - YEAR_ENA - Enable year matching - [26:26] - read-write - - - MONTH_ENA - Enable month matching - [25:25] - read-write - - - DAY_ENA - Enable day matching - [24:24] - read-write - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - IRQ_SETUP_1 - Interrupt setup register 1 - 0x0014 - 0x00000000 - - - DOTW_ENA - Enable day of the week matching - [31:31] - read-write - - - HOUR_ENA - Enable hour matching - [30:30] - read-write - - - MIN_ENA - Enable minute matching - [29:29] - read-write - - - SEC_ENA - Enable second matching - [28:28] - read-write - - - DOTW - Day of the week - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - RTC_1 - RTC register 1. - 0x0018 - 0x00000000 - - - YEAR - Year - [23:12] - read-only - - - MONTH - Month (1..12) - [11:8] - read-only - - - DAY - Day of the month (1..31) - [4:0] - read-only - - - - - RTC_0 - RTC register 0\n - Read this before RTC 1! - 0x001c - 0x00000000 - - - DOTW - Day of the week - [26:24] - read-only - - - HOUR - Hours - [20:16] - read-only - - - MIN - Minutes - [13:8] - read-only - - - SEC - Seconds - [5:0] - read-only - - - - - INTR - Raw Interrupts - 0x0020 - 0x00000000 - - - RTC - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x0024 - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x0028 - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x002c - 0x00000000 - - - RTC - [0:0] - read-only - - - - - - - ROSC - 1 - 0x40060000 - 32 - - 0 - 0x1000 - registers - - - - CTRL - Ring Oscillator control - 0x0000 - 0x00000aa0 - - - ENABLE - On power-up this field is initialised to ENABLE\n - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Controls the number of delay stages in the ROSC ring\n - LOW uses stages 0 to 7\n - MEDIUM uses stages 0 to 5\n - HIGH uses stages 0 to 3\n - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n - The clock output will not glitch when changing the range up one step at a time\n - The clock output will glitch when changing the range down\n - Note: the values here are gray coded which is why HIGH comes before TOOHIGH - [11:0] - read-write - - - LOW - 4004 - - - MEDIUM - 4005 - - - HIGH - 4007 - - - TOOHIGH - 4006 - - - - - - - FREQA - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n - The drive strength has 4 levels determined by the number of bits set\n - Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n - 0 bits set is the default drive strength\n - 1 bit set doubles the drive strength\n - 2 bits set triples drive strength\n - 3 bits set quadruples drive strength - 0x0004 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings\n - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS3 - Stage 3 drive strength - [14:12] - read-write - - - DS2 - Stage 2 drive strength - [10:8] - read-write - - - DS1 - Stage 1 drive strength - [6:4] - read-write - - - DS0 - Stage 0 drive strength - [2:0] - read-write - - - - - FREQB - For a detailed description see freqa register - 0x0008 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings\n - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS7 - Stage 7 drive strength - [14:12] - read-write - - - DS6 - Stage 6 drive strength - [10:8] - read-write - - - DS5 - Stage 5 drive strength - [6:4] - read-write - - - DS4 - Stage 4 drive strength - [2:0] - read-write - - - - - DORMANT - Ring Oscillator pause control\n - This is used to save power by pausing the ROSC\n - On power-up this field is initialised to WAKE\n - An invalid write will also select WAKE\n - Warning: setup the irq before selecting dormant mode - 0x000c - read-write - 0x00000000 - - - DIV - Controls the output divider - 0x0010 - 0x00000000 - - - DIV - set to 0xaa0 + div where\n - div = 0 divides by 32\n - div = 1-31 divides by div\n - any other value sets div=31\n - this register resets to div=16 - [11:0] - read-write - - - PASS - 2720 - - - - - - - PHASE - Controls the phase shifted output - 0x0014 - 0x00000008 - - - PASSWD - set to 0xaa\n - any other value enables the output with shift=0 - [11:4] - read-write - - - ENABLE - enable the phase-shifted output\n - this can be changed on-the-fly - [3:3] - read-write - - - FLIP - invert the phase-shifted output\n - this is ignored when div=1 - [2:2] - read-write - - - SHIFT - phase shift the phase-shifted output by SHIFT input clocks\n - this can be changed on-the-fly\n - must be set to 0 before setting div=1 - [1:0] - read-write - - - - - STATUS - Ring Oscillator Status - 0x0018 - 0x00000000 - - - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT - [24:24] - read-write - oneToClear - - - DIV_RUNNING - post-divider is running\n - this resets to 0 but transitions to 1 during chip startup - [16:16] - read-only - - - ENABLED - Oscillator is enabled but not necessarily running and stable\n - this resets to 0 but transitions to 1 during chip startup - [12:12] - read-only - - - - - RANDOMBIT - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency - 0x001c - 0x00000001 - - - RANDOMBIT - [0:0] - read-only - - - - - COUNT - A down counter running at the ROSC frequency which counts to zero and stops.\n - To start the counter write a non-zero value.\n - Can be used for short software pauses when setting up time sensitive hardware. - 0x0020 - 0x00000000 - - - COUNT - [7:0] - read-write - - - - - - - VREG_AND_CHIP_RESET - 1 - control and status for on-chip voltage regulator and chip level reset subsystem - 0x40064000 - 32 - - 0 - 0x1000 - registers - - - - VREG - Voltage regulator control and status - 0x0000 - 0x000000b1 - - - ROK - regulation status\n - 0=not in regulation, 1=in regulation - [12:12] - read-only - - - VSEL - output voltage select\n - 0000 to 0101 - 0.80V\n - 0110 - 0.85V\n - 0111 - 0.90V\n - 1000 - 0.95V\n - 1001 - 1.00V\n - 1010 - 1.05V\n - 1011 - 1.10V (default)\n - 1100 - 1.15V\n - 1101 - 1.20V\n - 1110 - 1.25V\n - 1111 - 1.30V - [7:4] - read-write - - - HIZ - high impedance mode select\n - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - EN - enable\n - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD - brown-out detection control - 0x0004 - 0x00000091 - - - VSEL - threshold select\n - 0000 - 0.473V\n - 0001 - 0.516V\n - 0010 - 0.559V\n - 0011 - 0.602V\n - 0100 - 0.645V\n - 0101 - 0.688V\n - 0110 - 0.731V\n - 0111 - 0.774V\n - 1000 - 0.817V\n - 1001 - 0.860V (default)\n - 1010 - 0.903V\n - 1011 - 0.946V\n - 1100 - 0.989V\n - 1101 - 1.032V\n - 1110 - 1.075V\n - 1111 - 1.118V - [7:4] - read-write - - - EN - enable\n - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - CHIP_RESET - Chip reset control and status - 0x0008 - 0x00000000 - - - PSM_RESTART_FLAG - This is set by psm_restart from the debugger.\n - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. - [24:24] - read-write - oneToClear - - - HAD_PSM_RESTART - Last reset was from the debug port - [20:20] - read-only - - - HAD_RUN - Last reset was from the RUN pin - [16:16] - read-only - - - HAD_POR - Last reset was from the power-on reset or brown-out detection blocks - [8:8] - read-only - - - - - - - TBMAN - 1 - Testbench manager. Allows the programmer to know what platform their software is running on. - 0x4006c000 - 32 - - 0 - 0x1000 - registers - - - - PLATFORM - Indicates the type of platform in use - 0x0000 - 0x00000005 - - - FPGA - Indicates the platform is an FPGA - [1:1] - read-only - - - ASIC - Indicates the platform is an ASIC - [0:0] - read-only - - - - - - - DMA - 1 - DMA with separate read and write masters - 0x50000000 - 32 - - 0 - 0x1000 - registers - - - DMA_IRQ_0 - 11 - - - DMA_IRQ_1 - 12 - - - - CH0_READ_ADDR - DMA Channel 0 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0000 - read-write - 0x00000000 - - - CH0_WRITE_ADDR - DMA Channel 0 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0004 - read-write - 0x00000000 - - - CH0_TRANS_COUNT - DMA Channel 0 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0008 - read-write - 0x00000000 - - - CH0_CTRL_TRIG - DMA Channel 0 Control and Status - 0x000c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH0_AL1_CTRL - Alias for channel 0 CTRL register - 0x0010 - read-write - 0x00000000 - - - CH0_AL1_READ_ADDR - Alias for channel 0 READ_ADDR register - 0x0014 - read-write - 0x00000000 - - - CH0_AL1_WRITE_ADDR - Alias for channel 0 WRITE_ADDR register - 0x0018 - read-write - 0x00000000 - - - CH0_AL1_TRANS_COUNT_TRIG - Alias for channel 0 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x001c - read-write - 0x00000000 - - - CH0_AL2_CTRL - Alias for channel 0 CTRL register - 0x0020 - read-write - 0x00000000 - - - CH0_AL2_TRANS_COUNT - Alias for channel 0 TRANS_COUNT register - 0x0024 - read-write - 0x00000000 - - - CH0_AL2_READ_ADDR - Alias for channel 0 READ_ADDR register - 0x0028 - read-write - 0x00000000 - - - CH0_AL2_WRITE_ADDR_TRIG - Alias for channel 0 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x002c - read-write - 0x00000000 - - - CH0_AL3_CTRL - Alias for channel 0 CTRL register - 0x0030 - read-write - 0x00000000 - - - CH0_AL3_WRITE_ADDR - Alias for channel 0 WRITE_ADDR register - 0x0034 - read-write - 0x00000000 - - - CH0_AL3_TRANS_COUNT - Alias for channel 0 TRANS_COUNT register - 0x0038 - read-write - 0x00000000 - - - CH0_AL3_READ_ADDR_TRIG - Alias for channel 0 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x003c - read-write - 0x00000000 - - - CH1_READ_ADDR - DMA Channel 1 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0040 - read-write - 0x00000000 - - - CH1_WRITE_ADDR - DMA Channel 1 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0044 - read-write - 0x00000000 - - - CH1_TRANS_COUNT - DMA Channel 1 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0048 - read-write - 0x00000000 - - - CH1_CTRL_TRIG - DMA Channel 1 Control and Status - 0x004c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH1_AL1_CTRL - Alias for channel 1 CTRL register - 0x0050 - read-write - 0x00000000 - - - CH1_AL1_READ_ADDR - Alias for channel 1 READ_ADDR register - 0x0054 - read-write - 0x00000000 - - - CH1_AL1_WRITE_ADDR - Alias for channel 1 WRITE_ADDR register - 0x0058 - read-write - 0x00000000 - - - CH1_AL1_TRANS_COUNT_TRIG - Alias for channel 1 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x005c - read-write - 0x00000000 - - - CH1_AL2_CTRL - Alias for channel 1 CTRL register - 0x0060 - read-write - 0x00000000 - - - CH1_AL2_TRANS_COUNT - Alias for channel 1 TRANS_COUNT register - 0x0064 - read-write - 0x00000000 - - - CH1_AL2_READ_ADDR - Alias for channel 1 READ_ADDR register - 0x0068 - read-write - 0x00000000 - - - CH1_AL2_WRITE_ADDR_TRIG - Alias for channel 1 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x006c - read-write - 0x00000000 - - - CH1_AL3_CTRL - Alias for channel 1 CTRL register - 0x0070 - read-write - 0x00000000 - - - CH1_AL3_WRITE_ADDR - Alias for channel 1 WRITE_ADDR register - 0x0074 - read-write - 0x00000000 - - - CH1_AL3_TRANS_COUNT - Alias for channel 1 TRANS_COUNT register - 0x0078 - read-write - 0x00000000 - - - CH1_AL3_READ_ADDR_TRIG - Alias for channel 1 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x007c - read-write - 0x00000000 - - - CH2_READ_ADDR - DMA Channel 2 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0080 - read-write - 0x00000000 - - - CH2_WRITE_ADDR - DMA Channel 2 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0084 - read-write - 0x00000000 - - - CH2_TRANS_COUNT - DMA Channel 2 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0088 - read-write - 0x00000000 - - - CH2_CTRL_TRIG - DMA Channel 2 Control and Status - 0x008c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH2_AL1_CTRL - Alias for channel 2 CTRL register - 0x0090 - read-write - 0x00000000 - - - CH2_AL1_READ_ADDR - Alias for channel 2 READ_ADDR register - 0x0094 - read-write - 0x00000000 - - - CH2_AL1_WRITE_ADDR - Alias for channel 2 WRITE_ADDR register - 0x0098 - read-write - 0x00000000 - - - CH2_AL1_TRANS_COUNT_TRIG - Alias for channel 2 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x009c - read-write - 0x00000000 - - - CH2_AL2_CTRL - Alias for channel 2 CTRL register - 0x00a0 - read-write - 0x00000000 - - - CH2_AL2_TRANS_COUNT - Alias for channel 2 TRANS_COUNT register - 0x00a4 - read-write - 0x00000000 - - - CH2_AL2_READ_ADDR - Alias for channel 2 READ_ADDR register - 0x00a8 - read-write - 0x00000000 - - - CH2_AL2_WRITE_ADDR_TRIG - Alias for channel 2 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x00ac - read-write - 0x00000000 - - - CH2_AL3_CTRL - Alias for channel 2 CTRL register - 0x00b0 - read-write - 0x00000000 - - - CH2_AL3_WRITE_ADDR - Alias for channel 2 WRITE_ADDR register - 0x00b4 - read-write - 0x00000000 - - - CH2_AL3_TRANS_COUNT - Alias for channel 2 TRANS_COUNT register - 0x00b8 - read-write - 0x00000000 - - - CH2_AL3_READ_ADDR_TRIG - Alias for channel 2 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x00bc - read-write - 0x00000000 - - - CH3_READ_ADDR - DMA Channel 3 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x00c0 - read-write - 0x00000000 - - - CH3_WRITE_ADDR - DMA Channel 3 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x00c4 - read-write - 0x00000000 - - - CH3_TRANS_COUNT - DMA Channel 3 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x00c8 - read-write - 0x00000000 - - - CH3_CTRL_TRIG - DMA Channel 3 Control and Status - 0x00cc - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH3_AL1_CTRL - Alias for channel 3 CTRL register - 0x00d0 - read-write - 0x00000000 - - - CH3_AL1_READ_ADDR - Alias for channel 3 READ_ADDR register - 0x00d4 - read-write - 0x00000000 - - - CH3_AL1_WRITE_ADDR - Alias for channel 3 WRITE_ADDR register - 0x00d8 - read-write - 0x00000000 - - - CH3_AL1_TRANS_COUNT_TRIG - Alias for channel 3 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x00dc - read-write - 0x00000000 - - - CH3_AL2_CTRL - Alias for channel 3 CTRL register - 0x00e0 - read-write - 0x00000000 - - - CH3_AL2_TRANS_COUNT - Alias for channel 3 TRANS_COUNT register - 0x00e4 - read-write - 0x00000000 - - - CH3_AL2_READ_ADDR - Alias for channel 3 READ_ADDR register - 0x00e8 - read-write - 0x00000000 - - - CH3_AL2_WRITE_ADDR_TRIG - Alias for channel 3 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x00ec - read-write - 0x00000000 - - - CH3_AL3_CTRL - Alias for channel 3 CTRL register - 0x00f0 - read-write - 0x00000000 - - - CH3_AL3_WRITE_ADDR - Alias for channel 3 WRITE_ADDR register - 0x00f4 - read-write - 0x00000000 - - - CH3_AL3_TRANS_COUNT - Alias for channel 3 TRANS_COUNT register - 0x00f8 - read-write - 0x00000000 - - - CH3_AL3_READ_ADDR_TRIG - Alias for channel 3 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x00fc - read-write - 0x00000000 - - - CH4_READ_ADDR - DMA Channel 4 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0100 - read-write - 0x00000000 - - - CH4_WRITE_ADDR - DMA Channel 4 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0104 - read-write - 0x00000000 - - - CH4_TRANS_COUNT - DMA Channel 4 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0108 - read-write - 0x00000000 - - - CH4_CTRL_TRIG - DMA Channel 4 Control and Status - 0x010c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH4_AL1_CTRL - Alias for channel 4 CTRL register - 0x0110 - read-write - 0x00000000 - - - CH4_AL1_READ_ADDR - Alias for channel 4 READ_ADDR register - 0x0114 - read-write - 0x00000000 - - - CH4_AL1_WRITE_ADDR - Alias for channel 4 WRITE_ADDR register - 0x0118 - read-write - 0x00000000 - - - CH4_AL1_TRANS_COUNT_TRIG - Alias for channel 4 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x011c - read-write - 0x00000000 - - - CH4_AL2_CTRL - Alias for channel 4 CTRL register - 0x0120 - read-write - 0x00000000 - - - CH4_AL2_TRANS_COUNT - Alias for channel 4 TRANS_COUNT register - 0x0124 - read-write - 0x00000000 - - - CH4_AL2_READ_ADDR - Alias for channel 4 READ_ADDR register - 0x0128 - read-write - 0x00000000 - - - CH4_AL2_WRITE_ADDR_TRIG - Alias for channel 4 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x012c - read-write - 0x00000000 - - - CH4_AL3_CTRL - Alias for channel 4 CTRL register - 0x0130 - read-write - 0x00000000 - - - CH4_AL3_WRITE_ADDR - Alias for channel 4 WRITE_ADDR register - 0x0134 - read-write - 0x00000000 - - - CH4_AL3_TRANS_COUNT - Alias for channel 4 TRANS_COUNT register - 0x0138 - read-write - 0x00000000 - - - CH4_AL3_READ_ADDR_TRIG - Alias for channel 4 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x013c - read-write - 0x00000000 - - - CH5_READ_ADDR - DMA Channel 5 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0140 - read-write - 0x00000000 - - - CH5_WRITE_ADDR - DMA Channel 5 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0144 - read-write - 0x00000000 - - - CH5_TRANS_COUNT - DMA Channel 5 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0148 - read-write - 0x00000000 - - - CH5_CTRL_TRIG - DMA Channel 5 Control and Status - 0x014c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH5_AL1_CTRL - Alias for channel 5 CTRL register - 0x0150 - read-write - 0x00000000 - - - CH5_AL1_READ_ADDR - Alias for channel 5 READ_ADDR register - 0x0154 - read-write - 0x00000000 - - - CH5_AL1_WRITE_ADDR - Alias for channel 5 WRITE_ADDR register - 0x0158 - read-write - 0x00000000 - - - CH5_AL1_TRANS_COUNT_TRIG - Alias for channel 5 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x015c - read-write - 0x00000000 - - - CH5_AL2_CTRL - Alias for channel 5 CTRL register - 0x0160 - read-write - 0x00000000 - - - CH5_AL2_TRANS_COUNT - Alias for channel 5 TRANS_COUNT register - 0x0164 - read-write - 0x00000000 - - - CH5_AL2_READ_ADDR - Alias for channel 5 READ_ADDR register - 0x0168 - read-write - 0x00000000 - - - CH5_AL2_WRITE_ADDR_TRIG - Alias for channel 5 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x016c - read-write - 0x00000000 - - - CH5_AL3_CTRL - Alias for channel 5 CTRL register - 0x0170 - read-write - 0x00000000 - - - CH5_AL3_WRITE_ADDR - Alias for channel 5 WRITE_ADDR register - 0x0174 - read-write - 0x00000000 - - - CH5_AL3_TRANS_COUNT - Alias for channel 5 TRANS_COUNT register - 0x0178 - read-write - 0x00000000 - - - CH5_AL3_READ_ADDR_TRIG - Alias for channel 5 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x017c - read-write - 0x00000000 - - - CH6_READ_ADDR - DMA Channel 6 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0180 - read-write - 0x00000000 - - - CH6_WRITE_ADDR - DMA Channel 6 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0184 - read-write - 0x00000000 - - - CH6_TRANS_COUNT - DMA Channel 6 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0188 - read-write - 0x00000000 - - - CH6_CTRL_TRIG - DMA Channel 6 Control and Status - 0x018c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH6_AL1_CTRL - Alias for channel 6 CTRL register - 0x0190 - read-write - 0x00000000 - - - CH6_AL1_READ_ADDR - Alias for channel 6 READ_ADDR register - 0x0194 - read-write - 0x00000000 - - - CH6_AL1_WRITE_ADDR - Alias for channel 6 WRITE_ADDR register - 0x0198 - read-write - 0x00000000 - - - CH6_AL1_TRANS_COUNT_TRIG - Alias for channel 6 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x019c - read-write - 0x00000000 - - - CH6_AL2_CTRL - Alias for channel 6 CTRL register - 0x01a0 - read-write - 0x00000000 - - - CH6_AL2_TRANS_COUNT - Alias for channel 6 TRANS_COUNT register - 0x01a4 - read-write - 0x00000000 - - - CH6_AL2_READ_ADDR - Alias for channel 6 READ_ADDR register - 0x01a8 - read-write - 0x00000000 - - - CH6_AL2_WRITE_ADDR_TRIG - Alias for channel 6 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x01ac - read-write - 0x00000000 - - - CH6_AL3_CTRL - Alias for channel 6 CTRL register - 0x01b0 - read-write - 0x00000000 - - - CH6_AL3_WRITE_ADDR - Alias for channel 6 WRITE_ADDR register - 0x01b4 - read-write - 0x00000000 - - - CH6_AL3_TRANS_COUNT - Alias for channel 6 TRANS_COUNT register - 0x01b8 - read-write - 0x00000000 - - - CH6_AL3_READ_ADDR_TRIG - Alias for channel 6 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x01bc - read-write - 0x00000000 - - - CH7_READ_ADDR - DMA Channel 7 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x01c0 - read-write - 0x00000000 - - - CH7_WRITE_ADDR - DMA Channel 7 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x01c4 - read-write - 0x00000000 - - - CH7_TRANS_COUNT - DMA Channel 7 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x01c8 - read-write - 0x00000000 - - - CH7_CTRL_TRIG - DMA Channel 7 Control and Status - 0x01cc - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH7_AL1_CTRL - Alias for channel 7 CTRL register - 0x01d0 - read-write - 0x00000000 - - - CH7_AL1_READ_ADDR - Alias for channel 7 READ_ADDR register - 0x01d4 - read-write - 0x00000000 - - - CH7_AL1_WRITE_ADDR - Alias for channel 7 WRITE_ADDR register - 0x01d8 - read-write - 0x00000000 - - - CH7_AL1_TRANS_COUNT_TRIG - Alias for channel 7 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x01dc - read-write - 0x00000000 - - - CH7_AL2_CTRL - Alias for channel 7 CTRL register - 0x01e0 - read-write - 0x00000000 - - - CH7_AL2_TRANS_COUNT - Alias for channel 7 TRANS_COUNT register - 0x01e4 - read-write - 0x00000000 - - - CH7_AL2_READ_ADDR - Alias for channel 7 READ_ADDR register - 0x01e8 - read-write - 0x00000000 - - - CH7_AL2_WRITE_ADDR_TRIG - Alias for channel 7 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x01ec - read-write - 0x00000000 - - - CH7_AL3_CTRL - Alias for channel 7 CTRL register - 0x01f0 - read-write - 0x00000000 - - - CH7_AL3_WRITE_ADDR - Alias for channel 7 WRITE_ADDR register - 0x01f4 - read-write - 0x00000000 - - - CH7_AL3_TRANS_COUNT - Alias for channel 7 TRANS_COUNT register - 0x01f8 - read-write - 0x00000000 - - - CH7_AL3_READ_ADDR_TRIG - Alias for channel 7 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x01fc - read-write - 0x00000000 - - - CH8_READ_ADDR - DMA Channel 8 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0200 - read-write - 0x00000000 - - - CH8_WRITE_ADDR - DMA Channel 8 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0204 - read-write - 0x00000000 - - - CH8_TRANS_COUNT - DMA Channel 8 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0208 - read-write - 0x00000000 - - - CH8_CTRL_TRIG - DMA Channel 8 Control and Status - 0x020c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH8_AL1_CTRL - Alias for channel 8 CTRL register - 0x0210 - read-write - 0x00000000 - - - CH8_AL1_READ_ADDR - Alias for channel 8 READ_ADDR register - 0x0214 - read-write - 0x00000000 - - - CH8_AL1_WRITE_ADDR - Alias for channel 8 WRITE_ADDR register - 0x0218 - read-write - 0x00000000 - - - CH8_AL1_TRANS_COUNT_TRIG - Alias for channel 8 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x021c - read-write - 0x00000000 - - - CH8_AL2_CTRL - Alias for channel 8 CTRL register - 0x0220 - read-write - 0x00000000 - - - CH8_AL2_TRANS_COUNT - Alias for channel 8 TRANS_COUNT register - 0x0224 - read-write - 0x00000000 - - - CH8_AL2_READ_ADDR - Alias for channel 8 READ_ADDR register - 0x0228 - read-write - 0x00000000 - - - CH8_AL2_WRITE_ADDR_TRIG - Alias for channel 8 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x022c - read-write - 0x00000000 - - - CH8_AL3_CTRL - Alias for channel 8 CTRL register - 0x0230 - read-write - 0x00000000 - - - CH8_AL3_WRITE_ADDR - Alias for channel 8 WRITE_ADDR register - 0x0234 - read-write - 0x00000000 - - - CH8_AL3_TRANS_COUNT - Alias for channel 8 TRANS_COUNT register - 0x0238 - read-write - 0x00000000 - - - CH8_AL3_READ_ADDR_TRIG - Alias for channel 8 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x023c - read-write - 0x00000000 - - - CH9_READ_ADDR - DMA Channel 9 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0240 - read-write - 0x00000000 - - - CH9_WRITE_ADDR - DMA Channel 9 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0244 - read-write - 0x00000000 - - - CH9_TRANS_COUNT - DMA Channel 9 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0248 - read-write - 0x00000000 - - - CH9_CTRL_TRIG - DMA Channel 9 Control and Status - 0x024c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH9_AL1_CTRL - Alias for channel 9 CTRL register - 0x0250 - read-write - 0x00000000 - - - CH9_AL1_READ_ADDR - Alias for channel 9 READ_ADDR register - 0x0254 - read-write - 0x00000000 - - - CH9_AL1_WRITE_ADDR - Alias for channel 9 WRITE_ADDR register - 0x0258 - read-write - 0x00000000 - - - CH9_AL1_TRANS_COUNT_TRIG - Alias for channel 9 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x025c - read-write - 0x00000000 - - - CH9_AL2_CTRL - Alias for channel 9 CTRL register - 0x0260 - read-write - 0x00000000 - - - CH9_AL2_TRANS_COUNT - Alias for channel 9 TRANS_COUNT register - 0x0264 - read-write - 0x00000000 - - - CH9_AL2_READ_ADDR - Alias for channel 9 READ_ADDR register - 0x0268 - read-write - 0x00000000 - - - CH9_AL2_WRITE_ADDR_TRIG - Alias for channel 9 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x026c - read-write - 0x00000000 - - - CH9_AL3_CTRL - Alias for channel 9 CTRL register - 0x0270 - read-write - 0x00000000 - - - CH9_AL3_WRITE_ADDR - Alias for channel 9 WRITE_ADDR register - 0x0274 - read-write - 0x00000000 - - - CH9_AL3_TRANS_COUNT - Alias for channel 9 TRANS_COUNT register - 0x0278 - read-write - 0x00000000 - - - CH9_AL3_READ_ADDR_TRIG - Alias for channel 9 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x027c - read-write - 0x00000000 - - - CH10_READ_ADDR - DMA Channel 10 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0280 - read-write - 0x00000000 - - - CH10_WRITE_ADDR - DMA Channel 10 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x0284 - read-write - 0x00000000 - - - CH10_TRANS_COUNT - DMA Channel 10 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x0288 - read-write - 0x00000000 - - - CH10_CTRL_TRIG - DMA Channel 10 Control and Status - 0x028c - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH10_AL1_CTRL - Alias for channel 10 CTRL register - 0x0290 - read-write - 0x00000000 - - - CH10_AL1_READ_ADDR - Alias for channel 10 READ_ADDR register - 0x0294 - read-write - 0x00000000 - - - CH10_AL1_WRITE_ADDR - Alias for channel 10 WRITE_ADDR register - 0x0298 - read-write - 0x00000000 - - - CH10_AL1_TRANS_COUNT_TRIG - Alias for channel 10 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x029c - read-write - 0x00000000 - - - CH10_AL2_CTRL - Alias for channel 10 CTRL register - 0x02a0 - read-write - 0x00000000 - - - CH10_AL2_TRANS_COUNT - Alias for channel 10 TRANS_COUNT register - 0x02a4 - read-write - 0x00000000 - - - CH10_AL2_READ_ADDR - Alias for channel 10 READ_ADDR register - 0x02a8 - read-write - 0x00000000 - - - CH10_AL2_WRITE_ADDR_TRIG - Alias for channel 10 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x02ac - read-write - 0x00000000 - - - CH10_AL3_CTRL - Alias for channel 10 CTRL register - 0x02b0 - read-write - 0x00000000 - - - CH10_AL3_WRITE_ADDR - Alias for channel 10 WRITE_ADDR register - 0x02b4 - read-write - 0x00000000 - - - CH10_AL3_TRANS_COUNT - Alias for channel 10 TRANS_COUNT register - 0x02b8 - read-write - 0x00000000 - - - CH10_AL3_READ_ADDR_TRIG - Alias for channel 10 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x02bc - read-write - 0x00000000 - - - CH11_READ_ADDR - DMA Channel 11 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x02c0 - read-write - 0x00000000 - - - CH11_WRITE_ADDR - DMA Channel 11 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x02c4 - read-write - 0x00000000 - - - CH11_TRANS_COUNT - DMA Channel 11 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x02c8 - read-write - 0x00000000 - - - CH11_CTRL_TRIG - DMA Channel 11 Control and Status - 0x02cc - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH11_AL1_CTRL - Alias for channel 11 CTRL register - 0x02d0 - read-write - 0x00000000 - - - CH11_AL1_READ_ADDR - Alias for channel 11 READ_ADDR register - 0x02d4 - read-write - 0x00000000 - - - CH11_AL1_WRITE_ADDR - Alias for channel 11 WRITE_ADDR register - 0x02d8 - read-write - 0x00000000 - - - CH11_AL1_TRANS_COUNT_TRIG - Alias for channel 11 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x02dc - read-write - 0x00000000 - - - CH11_AL2_CTRL - Alias for channel 11 CTRL register - 0x02e0 - read-write - 0x00000000 - - - CH11_AL2_TRANS_COUNT - Alias for channel 11 TRANS_COUNT register - 0x02e4 - read-write - 0x00000000 - - - CH11_AL2_READ_ADDR - Alias for channel 11 READ_ADDR register - 0x02e8 - read-write - 0x00000000 - - - CH11_AL2_WRITE_ADDR_TRIG - Alias for channel 11 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x02ec - read-write - 0x00000000 - - - CH11_AL3_CTRL - Alias for channel 11 CTRL register - 0x02f0 - read-write - 0x00000000 - - - CH11_AL3_WRITE_ADDR - Alias for channel 11 WRITE_ADDR register - 0x02f4 - read-write - 0x00000000 - - - CH11_AL3_TRANS_COUNT - Alias for channel 11 TRANS_COUNT register - 0x02f8 - read-write - 0x00000000 - - - CH11_AL3_READ_ADDR_TRIG - Alias for channel 11 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x02fc - read-write - 0x00000000 - - - INTR - Interrupt Status (raw) - 0x0400 - 0x00000000 - - - INTR - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. - [15:0] - read-write - oneToClear - - - - - INTE0 - Interrupt Enables for IRQ 0 - 0x0404 - 0x00000000 - - - INTE0 - Set bit n to pass interrupts from channel n to DMA IRQ 0. - [15:0] - read-write - - - - - INTF0 - Force Interrupts - 0x0408 - 0x00000000 - - - INTF0 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS0 - Interrupt Status for IRQ 0 - 0x040c - 0x00000000 - - - INTS0 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n - Channel interrupts can be cleared by writing a bit mask here. - [15:0] - read-write - oneToClear - - - - - INTE1 - Interrupt Enables for IRQ 1 - 0x0414 - 0x00000000 - - - INTE1 - Set bit n to pass interrupts from channel n to DMA IRQ 1. - [15:0] - read-write - - - - - INTF1 - Force Interrupts for IRQ 1 - 0x0418 - 0x00000000 - - - INTF1 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write - - - - - INTS1 - Interrupt Status (masked) for IRQ 1 - 0x041c - 0x00000000 - - - INTS1 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n - Channel interrupts can be cleared by writing a bit mask here. - [15:0] - read-write - oneToClear - - - - - TIMER0 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x0420 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER1 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x0424 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER2 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x0428 - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - TIMER3 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x042c - 0x00000000 - - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write - - - - - MULTI_CHAN_TRIGGER - Trigger one or more channels simultaneously - 0x0430 - 0x00000000 - - - MULTI_CHAN_TRIGGER - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. - [15:0] - read-write - clear - - - - - SNIFF_CTRL - Sniffer Control - 0x0434 - 0x00000000 - - - OUT_INV - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [11:11] - read-write - - - OUT_REV - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. - [10:10] - read-write - - - BSWAP - Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. - [9:9] - read-write - - - CALC - [8:5] - read-write - - - CRC32 - Calculate a CRC-32 (IEEE802.3 polynomial) - 0 - - - CRC32R - Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data - 1 - - - CRC16 - Calculate a CRC-16-CCITT - 2 - - - CRC16R - Calculate a CRC-16-CCITT with bit reversed data - 3 - - - EVEN - XOR reduction over all data. == 1 if the total 1 population count is odd. - 14 - - - SUM - Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) - 15 - - - - - DMACH - DMA channel for Sniffer to observe - [4:1] - read-write - - - EN - Enable sniffer - [0:0] - read-write - - - - - SNIFF_DATA - Data accumulator for sniff hardware\n - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. - 0x0438 - read-write - 0x00000000 - - - FIFO_LEVELS - Debug RAF, WAF, TDF levels - 0x0440 - 0x00000000 - - - RAF_LVL - Current Read-Address-FIFO fill level - [23:16] - read-only - - - WAF_LVL - Current Write-Address-FIFO fill level - [15:8] - read-only - - - TDF_LVL - Current Transfer-Data-FIFO fill level - [7:0] - read-only - - - - - CHAN_ABORT - Abort an in-progress transfer sequence on one or more channels - 0x0444 - 0x00000000 - - - CHAN_ABORT - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. - [15:0] - read-write - clear - - - - - N_CHANNELS - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. - 0x0448 - 0x00000000 - - - N_CHANNELS - [4:0] - read-only - - - - - CH0_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0800 - 0x00000000 - - - CH0_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH0_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0804 - read-only - 0x00000000 - - - CH1_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0840 - 0x00000000 - - - CH1_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH1_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0844 - read-only - 0x00000000 - - - CH2_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0880 - 0x00000000 - - - CH2_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH2_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0884 - read-only - 0x00000000 - - - CH3_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x08c0 - 0x00000000 - - - CH3_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH3_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x08c4 - read-only - 0x00000000 - - - CH4_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0900 - 0x00000000 - - - CH4_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH4_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0904 - read-only - 0x00000000 - - - CH5_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0940 - 0x00000000 - - - CH5_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH5_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0944 - read-only - 0x00000000 - - - CH6_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0980 - 0x00000000 - - - CH6_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH6_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0984 - read-only - 0x00000000 - - - CH7_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x09c0 - 0x00000000 - - - CH7_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH7_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x09c4 - read-only - 0x00000000 - - - CH8_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0a00 - 0x00000000 - - - CH8_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH8_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0a04 - read-only - 0x00000000 - - - CH9_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0a40 - 0x00000000 - - - CH9_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH9_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0a44 - read-only - 0x00000000 - - - CH10_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0a80 - 0x00000000 - - - CH10_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH10_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0a84 - read-only - 0x00000000 - - - CH11_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x0ac0 - 0x00000000 - - - CH11_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH11_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x0ac4 - read-only - 0x00000000 - - - - - USBCTRL_DPRAM - 1 - DPRAM layout for USB device. - 0x50100000 - 32 - - 0 - 0x0100 - registers - - - - SETUP_PACKET_LOW - Bytes 0-3 of the SETUP packet from the host. - 0x0000 - 0x00000000 - - - WVALUE - [31:16] - read-write - - - BREQUEST - [15:8] - read-write - - - BMREQUESTTYPE - [7:0] - read-write - - - - - SETUP_PACKET_HIGH - Bytes 4-7 of the setup packet from the host. - 0x0004 - 0x00000000 - - - WLENGTH - [31:16] - read-write - - - WINDEX - [15:0] - read-write - - - - - EP1_IN_CONTROL - 0x0008 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP1_OUT_CONTROL - 0x000c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP2_IN_CONTROL - 0x0010 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP2_OUT_CONTROL - 0x0014 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP3_IN_CONTROL - 0x0018 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP3_OUT_CONTROL - 0x001c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP4_IN_CONTROL - 0x0020 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP4_OUT_CONTROL - 0x0024 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP5_IN_CONTROL - 0x0028 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP5_OUT_CONTROL - 0x002c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP6_IN_CONTROL - 0x0030 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP6_OUT_CONTROL - 0x0034 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP7_IN_CONTROL - 0x0038 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP7_OUT_CONTROL - 0x003c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP8_IN_CONTROL - 0x0040 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP8_OUT_CONTROL - 0x0044 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP9_IN_CONTROL - 0x0048 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP9_OUT_CONTROL - 0x004c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP10_IN_CONTROL - 0x0050 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP10_OUT_CONTROL - 0x0054 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP11_IN_CONTROL - 0x0058 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP11_OUT_CONTROL - 0x005c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP12_IN_CONTROL - 0x0060 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP12_OUT_CONTROL - 0x0064 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP13_IN_CONTROL - 0x0068 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP13_OUT_CONTROL - 0x006c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP14_IN_CONTROL - 0x0070 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP14_OUT_CONTROL - 0x0074 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP15_IN_CONTROL - 0x0078 - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP15_OUT_CONTROL - 0x007c - 0x00000000 - - - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write - - - ENDPOINT_TYPE - [27:26] - read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] - read-write - - - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write - - - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write - - - - - EP0_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x0080 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP0_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x0084 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP1_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x0088 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP1_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x008c - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP2_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x0090 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP2_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x0094 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP3_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x0098 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP3_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x009c - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP4_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00a0 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP4_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00a4 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP5_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00a8 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP5_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00ac - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP6_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00b0 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP6_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00b4 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP7_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00b8 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP7_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00bc - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP8_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00c0 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP8_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00c4 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP9_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00c8 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP9_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00cc - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP10_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00d0 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP10_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00d4 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP11_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00d8 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP11_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00dc - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP12_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00e0 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP12_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00e4 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP13_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00e8 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP13_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00ec - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP14_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00f0 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP14_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00f4 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP15_IN_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00f8 - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - EP15_OUT_BUFFER_CONTROL - Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n - Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. - 0x00fc - 0x00000000 - - - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] - read-write - - - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] - read-write - - - PID_1 - The data pid of buffer 1. - [29:29] - read-write - - - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] - read-write - - - 128 - 0 - - - 256 - 1 - - - 512 - 2 - - - 1024 - 3 - - - - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] - read-write - - - LENGTH_1 - The length of the data in buffer 1. - [25:16] - read-write - - - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] - read-write - - - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] - read-write - - - PID_0 - The data pid of buffer 0. - [13:13] - read-write - - - RESET - Reset the buffer selector to buffer 0. - [12:12] - read-write - - - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write - - - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write - - - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write - - - - - - - USBCTRL_REGS - 1 - USB FS/LS controller device registers - 0x50110000 - 32 - - 0 - 0x1000 - registers - - - USBCTRL_IRQ - 5 - - - - ADDR_ENDP - Device address and endpoint control - 0x0000 - 0x00000000 - - - ENDPOINT - Device endpoint to send data to. Only valid for HOST mode. - [19:16] - read-write - - - ADDRESS - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. - [6:0] - read-write - - - - - ADDR_ENDP1 - Interrupt endpoint 1. Only valid for HOST mode. - 0x0004 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP2 - Interrupt endpoint 2. Only valid for HOST mode. - 0x0008 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP3 - Interrupt endpoint 3. Only valid for HOST mode. - 0x000c - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP4 - Interrupt endpoint 4. Only valid for HOST mode. - 0x0010 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP5 - Interrupt endpoint 5. Only valid for HOST mode. - 0x0014 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP6 - Interrupt endpoint 6. Only valid for HOST mode. - 0x0018 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP7 - Interrupt endpoint 7. Only valid for HOST mode. - 0x001c - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP8 - Interrupt endpoint 8. Only valid for HOST mode. - 0x0020 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP9 - Interrupt endpoint 9. Only valid for HOST mode. - 0x0024 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP10 - Interrupt endpoint 10. Only valid for HOST mode. - 0x0028 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP11 - Interrupt endpoint 11. Only valid for HOST mode. - 0x002c - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP12 - Interrupt endpoint 12. Only valid for HOST mode. - 0x0030 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP13 - Interrupt endpoint 13. Only valid for HOST mode. - 0x0034 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP14 - Interrupt endpoint 14. Only valid for HOST mode. - 0x0038 - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - ADDR_ENDP15 - Interrupt endpoint 15. Only valid for HOST mode. - 0x003c - 0x00000000 - - - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write - - - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write - - - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write - - - ADDRESS - Device address - [6:0] - read-write - - - - - MAIN_CTRL - Main control register - 0x0040 - 0x00000000 - - - SIM_TIMING - Reduced timings for simulation - [31:31] - read-write - - - HOST_NDEVICE - Device mode = 0, Host mode = 1 - [1:1] - read-write - - - CONTROLLER_EN - Enable controller - [0:0] - read-write - - - - - SOF_WR - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. - 0x0044 - 0x00000000 - - - COUNT - [10:0] - write-only - - - - - SOF_RD - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. - 0x0048 - 0x00000000 - - - COUNT - [10:0] - read-only - - - - - SIE_CTRL - SIE control register - 0x004c - 0x00000000 - - - EP0_INT_STALL - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - [31:31] - read-write - - - EP0_DOUBLE_BUF - Device: EP0 single buffered = 0, double buffered = 1 - [30:30] - read-write - - - EP0_INT_1BUF - Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - [29:29] - read-write - - - EP0_INT_2BUF - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 - [28:28] - read-write - - - EP0_INT_NAK - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - [27:27] - read-write - - - DIRECT_EN - Direct bus drive enable - [26:26] - read-write - - - DIRECT_DP - Direct control of DP - [25:25] - read-write - - - DIRECT_DM - Direct control of DM - [24:24] - read-write - - - TRANSCEIVER_PD - Power down bus transceiver - [18:18] - read-write - - - RPU_OPT - Device: Pull-up strength (0=1K2, 1=2k3) - [17:17] - read-write - - - PULLUP_EN - Device: Enable pull up resistor - [16:16] - read-write - - - PULLDOWN_EN - Host: Enable pull down resistors - [15:15] - read-write - - - RESET_BUS - Host: Reset bus - [13:13] - read-write - clear - - - RESUME - Device: Remote wakeup. Device can initiate its own resume after suspend. - [12:12] - read-write - clear - - - VBUS_EN - Host: Enable VBUS - [11:11] - read-write - - - KEEP_ALIVE_EN - Host: Enable keep alive packet (for low speed bus) - [10:10] - read-write - - - SOF_EN - Host: Enable SOF generation (for full speed bus) - [9:9] - read-write - - - SOF_SYNC - Host: Delay packet(s) until after SOF - [8:8] - read-write - - - PREAMBLE_EN - Host: Preable enable for LS device on FS hub - [6:6] - read-write - - - STOP_TRANS - Host: Stop transaction - [4:4] - read-write - clear - - - RECEIVE_DATA - Host: Receive transaction (IN to host) - [3:3] - read-write - - - SEND_DATA - Host: Send transaction (OUT from host) - [2:2] - read-write - - - SEND_SETUP - Host: Send Setup packet - [1:1] - read-write - - - START_TRANS - Host: Start transaction - [0:0] - read-write - clear - - - - - SIE_STATUS - SIE status register - 0x0050 - 0x00000000 - - - DATA_SEQ_ERROR - Data Sequence Error.\n\n - The device can raise a sequence error in the following conditions:\n\n - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n - The host can raise a data sequence error in the following conditions:\n\n - * An IN packet from the device has the wrong data PID - [31:31] - read-write - oneToClear - - - ACK_REC - ACK received. Raised by both host and device. - [30:30] - read-write - oneToClear - - - STALL_REC - Host: STALL received - [29:29] - read-write - oneToClear - - - NAK_REC - Host: NAK received - [28:28] - read-write - oneToClear - - - RX_TIMEOUT - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. - [27:27] - read-write - oneToClear - - - RX_OVERFLOW - RX overflow is raised by the Serial RX engine if the incoming data is too fast. - [26:26] - read-write - oneToClear - - - BIT_STUFF_ERROR - Bit Stuff Error. Raised by the Serial RX engine. - [25:25] - read-write - oneToClear - - - CRC_ERROR - CRC Error. Raised by the Serial RX engine. - [24:24] - read-write - oneToClear - - - BUS_RESET - Device: bus reset received - [19:19] - read-write - oneToClear - - - TRANS_COMPLETE - Transaction complete.\n\n - Raised by device if:\n\n - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n - Raised by host if:\n\n - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set - [18:18] - read-write - oneToClear - - - SETUP_REC - Device: Setup packet received - [17:17] - read-write - oneToClear - - - CONNECTED - Device: connected - [16:16] - read-write - oneToClear - - - RESUME - Host: Device has initiated a remote resume. Device: host has initiated a resume. - [11:11] - read-write - oneToClear - - - VBUS_OVER_CURR - VBUS over current detected - [10:10] - read-only - - - SPEED - Host: device speed. Disconnected = 00, LS = 01, FS = 10 - [9:8] - read-write - oneToClear - - - SUSPENDED - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. - [4:4] - read-write - oneToClear - - - LINE_STATE - USB bus line state - [3:2] - read-only - - - VBUS_DETECTED - Device: VBUS Detected - [0:0] - read-only - - - - - INT_EP_CTRL - interrupt endpoint control register - 0x0054 - 0x00000000 - - - INT_EP_ACTIVE - Host: Enable interrupt endpoint 1 -> 15 - [15:1] - read-write - - - - - BUFF_STATUS - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. - 0x0058 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - BUFF_CPU_SHOULD_HANDLE - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. - 0x005c - 0x00000000 - - - EP15_OUT - [31:31] - read-only - - - EP15_IN - [30:30] - read-only - - - EP14_OUT - [29:29] - read-only - - - EP14_IN - [28:28] - read-only - - - EP13_OUT - [27:27] - read-only - - - EP13_IN - [26:26] - read-only - - - EP12_OUT - [25:25] - read-only - - - EP12_IN - [24:24] - read-only - - - EP11_OUT - [23:23] - read-only - - - EP11_IN - [22:22] - read-only - - - EP10_OUT - [21:21] - read-only - - - EP10_IN - [20:20] - read-only - - - EP9_OUT - [19:19] - read-only - - - EP9_IN - [18:18] - read-only - - - EP8_OUT - [17:17] - read-only - - - EP8_IN - [16:16] - read-only - - - EP7_OUT - [15:15] - read-only - - - EP7_IN - [14:14] - read-only - - - EP6_OUT - [13:13] - read-only - - - EP6_IN - [12:12] - read-only - - - EP5_OUT - [11:11] - read-only - - - EP5_IN - [10:10] - read-only - - - EP4_OUT - [9:9] - read-only - - - EP4_IN - [8:8] - read-only - - - EP3_OUT - [7:7] - read-only - - - EP3_IN - [6:6] - read-only - - - EP2_OUT - [5:5] - read-only - - - EP2_IN - [4:4] - read-only - - - EP1_OUT - [3:3] - read-only - - - EP1_IN - [2:2] - read-only - - - EP0_OUT - [1:1] - read-only - - - EP0_IN - [0:0] - read-only - - - - - EP_ABORT - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. - 0x0060 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - - - EP15_IN - [30:30] - read-write - - - EP14_OUT - [29:29] - read-write - - - EP14_IN - [28:28] - read-write - - - EP13_OUT - [27:27] - read-write - - - EP13_IN - [26:26] - read-write - - - EP12_OUT - [25:25] - read-write - - - EP12_IN - [24:24] - read-write - - - EP11_OUT - [23:23] - read-write - - - EP11_IN - [22:22] - read-write - - - EP10_OUT - [21:21] - read-write - - - EP10_IN - [20:20] - read-write - - - EP9_OUT - [19:19] - read-write - - - EP9_IN - [18:18] - read-write - - - EP8_OUT - [17:17] - read-write - - - EP8_IN - [16:16] - read-write - - - EP7_OUT - [15:15] - read-write - - - EP7_IN - [14:14] - read-write - - - EP6_OUT - [13:13] - read-write - - - EP6_IN - [12:12] - read-write - - - EP5_OUT - [11:11] - read-write - - - EP5_IN - [10:10] - read-write - - - EP4_OUT - [9:9] - read-write - - - EP4_IN - [8:8] - read-write - - - EP3_OUT - [7:7] - read-write - - - EP3_IN - [6:6] - read-write - - - EP2_OUT - [5:5] - read-write - - - EP2_IN - [4:4] - read-write - - - EP1_OUT - [3:3] - read-write - - - EP1_IN - [2:2] - read-write - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - EP_ABORT_DONE - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. - 0x0064 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - EP_STALL_ARM - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. - 0x0068 - 0x00000000 - - - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] - read-write - - - - - NAK_POLL - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. - 0x006c - 0x00100010 - - - DELAY_FS - NAK polling interval for a full speed device - [25:16] - read-write - - - DELAY_LS - NAK polling interval for a low speed device - [9:0] - read-write - - - - - EP_STATUS_STALL_NAK - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. - 0x0070 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear - - - EP8_OUT - [17:17] - read-write - oneToClear - - - EP8_IN - [16:16] - read-write - oneToClear - - - EP7_OUT - [15:15] - read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - - - EP5_IN - [10:10] - read-write - oneToClear - - - EP4_OUT - [9:9] - read-write - oneToClear - - - EP4_IN - [8:8] - read-write - oneToClear - - - EP3_OUT - [7:7] - read-write - oneToClear - - - EP3_IN - [6:6] - read-write - oneToClear - - - EP2_OUT - [5:5] - read-write - oneToClear - - - EP2_IN - [4:4] - read-write - oneToClear - - - EP1_OUT - [3:3] - read-write - oneToClear - - - EP1_IN - [2:2] - read-write - oneToClear - - - EP0_OUT - [1:1] - read-write - oneToClear - - - EP0_IN - [0:0] - read-write - oneToClear - - - - - USB_MUXING - Where to connect the USB controller. Should be to_phy by default. - 0x0074 - 0x00000000 - - - SOFTCON - [3:3] - read-write - - - TO_DIGITAL_PAD - [2:2] - read-write - - - TO_EXTPHY - [1:1] - read-write - - - TO_PHY - [0:0] - read-write - - - - - USB_PWR - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. - 0x0078 - 0x00000000 - - - OVERCURR_DETECT_EN - [5:5] - read-write - - - OVERCURR_DETECT - [4:4] - read-write - - - VBUS_DETECT_OVERRIDE_EN - [3:3] - read-write - - - VBUS_DETECT - [2:2] - read-write - - - VBUS_EN_OVERRIDE_EN - [1:1] - read-write - - - VBUS_EN - [0:0] - read-write - - - - - USBPHY_DIRECT - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. - 0x007c - 0x00000000 - - - DM_OVV - DM over voltage - [22:22] - read-only - - - DP_OVV - DP over voltage - [21:21] - read-only - - - DM_OVCN - DM overcurrent - [20:20] - read-only - - - DP_OVCN - DP overcurrent - [19:19] - read-only - - - RX_DM - DPM pin state - [18:18] - read-only - - - RX_DP - DPP pin state - [17:17] - read-only - - - RX_DD - Differential RX - [16:16] - read-only - - - TX_DIFFMODE - TX_DIFFMODE=0: Single ended mode\n - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) - [15:15] - read-write - - - TX_FSSLEW - TX_FSSLEW=0: Low speed slew rate\n - TX_FSSLEW=1: Full speed slew rate - [14:14] - read-write - - - TX_PD - TX power down override (if override enable is set). 1 = powered down. - [13:13] - read-write - - - RX_PD - RX power down override (if override enable is set). 1 = powered down. - [12:12] - read-write - - - TX_DM - Output data. TX_DIFFMODE=1, Ignored\n - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM - [11:11] - read-write - - - TX_DP - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP - [10:10] - read-write - - - TX_DM_OE - Output enable. If TX_DIFFMODE=1, Ignored.\n - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving - [9:9] - read-write - - - TX_DP_OE - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving - [8:8] - read-write - - - DM_PULLDN_EN - DM pull down enable - [6:6] - read-write - - - DM_PULLUP_EN - DM pull up enable - [5:5] - read-write - - - DM_PULLUP_HISEL - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [4:4] - read-write - - - DP_PULLDN_EN - DP pull down enable - [2:2] - read-write - - - DP_PULLUP_EN - DP pull up enable - [1:1] - read-write - - - DP_PULLUP_HISEL - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [0:0] - read-write - - - - - USBPHY_DIRECT_OVERRIDE - Override enable for each control in usbphy_direct - 0x0080 - 0x00000000 - - - TX_DIFFMODE_OVERRIDE_EN - [15:15] - read-write - - - DM_PULLUP_OVERRIDE_EN - [12:12] - read-write - - - TX_FSSLEW_OVERRIDE_EN - [11:11] - read-write - - - TX_PD_OVERRIDE_EN - [10:10] - read-write - - - RX_PD_OVERRIDE_EN - [9:9] - read-write - - - TX_DM_OVERRIDE_EN - [8:8] - read-write - - - TX_DP_OVERRIDE_EN - [7:7] - read-write - - - TX_DM_OE_OVERRIDE_EN - [6:6] - read-write - - - TX_DP_OE_OVERRIDE_EN - [5:5] - read-write - - - DM_PULLDN_EN_OVERRIDE_EN - [4:4] - read-write - - - DP_PULLDN_EN_OVERRIDE_EN - [3:3] - read-write - - - DP_PULLUP_EN_OVERRIDE_EN - [2:2] - read-write - - - DM_PULLUP_HISEL_OVERRIDE_EN - [1:1] - read-write - - - DP_PULLUP_HISEL_OVERRIDE_EN - [0:0] - read-write - - - - - USBPHY_TRIM - Used to adjust trim values of USB phy pull down resistors. - 0x0084 - 0x00001f1f - - - DM_PULLDN_TRIM - Value to drive to USB PHY\n - DM pulldown resistor trim control\n - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [12:8] - read-write - - - DP_PULLDN_TRIM - Value to drive to USB PHY\n - DP pulldown resistor trim control\n - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [4:0] - read-write - - - - - INTR - Raw Interrupts - 0x008c - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x0090 - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x0094 - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-write - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-write - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-write - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-write - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-write - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-write - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-write - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-write - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-write - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-write - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-write - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-write - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-write - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-write - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-write - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-write - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-write - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-write - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x0098 - 0x00000000 - - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only - - - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only - - - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only - - - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only - - - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only - - - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only - - - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only - - - - - - - PIO0 - 1 - Programmable IO block - 0x50200000 - 32 - - 0 - 0x1000 - registers - - - PIO0_IRQ_0 - 7 - - - PIO0_IRQ_1 - 8 - - - - CTRL - PIO control register - 0x0000 - 0x00000000 - - - CLKDIV_RESTART - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. - [11:8] - read-write - clear - - - SM_RESTART - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. - [7:4] - read-write - clear - - - SM_ENABLE - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. - [3:0] - read-write - - - - - FSTAT - FIFO status register - 0x0004 - 0x0f000f00 - - - TXEMPTY - State machine TX FIFO is empty - [27:24] - read-only - - - TXFULL - State machine TX FIFO is full - [19:16] - read-only - - - RXEMPTY - State machine RX FIFO is empty - [11:8] - read-only - - - RXFULL - State machine RX FIFO is full - [3:0] - read-only - - - - - FDEBUG - FIFO debug register - 0x0008 - 0x00000000 - - - TXSTALL - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. - [27:24] - read-write - oneToClear - - - TXOVER - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. - [19:16] - read-write - oneToClear - - - RXUNDER - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. - [11:8] - read-write - oneToClear - - - RXSTALL - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. - [3:0] - read-write - oneToClear - - - - - FLEVEL - FIFO levels - 0x000c - 0x00000000 - - - RX3 - [31:28] - read-only - - - TX3 - [27:24] - read-only - - - RX2 - [23:20] - read-only - - - TX2 - [19:16] - read-only - - - RX1 - [15:12] - read-only - - - TX1 - [11:8] - read-only - - - RX0 - [7:4] - read-only - - - TX0 - [3:0] - read-only - - - - - TXF0 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x0010 - write-only - 0x00000000 - - - TXF1 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x0014 - write-only - 0x00000000 - - - TXF2 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x0018 - write-only - 0x00000000 - - - TXF3 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x001c - write-only - 0x00000000 - - - RXF0 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x0020 - read-only - 0x00000000 - - - RXF1 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x0024 - read-only - 0x00000000 - - - RXF2 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x0028 - read-only - 0x00000000 - - - RXF3 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x002c - read-only - 0x00000000 - - - IRQ - State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. - 0x0030 - 0x00000000 - - - IRQ - [7:0] - read-write - oneToClear - - - - - IRQ_FORCE - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. - 0x0034 - 0x00000000 - - - IRQ_FORCE - [7:0] - write-only - - - - - INPUT_SYNC_BYPASS - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n - 0 -> input is synchronized (default)\n - 1 -> synchronizer is bypassed\n - If in doubt, leave this register as all zeroes. - 0x0038 - read-write - 0x00000000 - - - DBG_PADOUT - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x003c - read-only - 0x00000000 - - - DBG_PADOE - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x0040 - read-only - 0x00000000 - - - DBG_CFGINFO - The PIO hardware has some free parameters that may vary between chip products.\n - These should be provided in the chip datasheet, but are also exposed here. - 0x0044 - 0x00000000 - - - IMEM_SIZE - The size of the instruction memory, measured in units of one instruction - [21:16] - read-only - - - SM_COUNT - The number of state machines this PIO instance is equipped with. - [11:8] - read-only - - - FIFO_DEPTH - The depth of the state machine TX/RX FIFOs, measured in words.\n - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n - this depth. - [5:0] - read-only - - - - - INSTR_MEM0 - Write-only access to instruction memory location 0 - 0x0048 - 0x00000000 - - - INSTR_MEM0 - [15:0] - write-only - - - - - INSTR_MEM1 - Write-only access to instruction memory location 1 - 0x004c - 0x00000000 - - - INSTR_MEM1 - [15:0] - write-only - - - - - INSTR_MEM2 - Write-only access to instruction memory location 2 - 0x0050 - 0x00000000 - - - INSTR_MEM2 - [15:0] - write-only - - - - - INSTR_MEM3 - Write-only access to instruction memory location 3 - 0x0054 - 0x00000000 - - - INSTR_MEM3 - [15:0] - write-only - - - - - INSTR_MEM4 - Write-only access to instruction memory location 4 - 0x0058 - 0x00000000 - - - INSTR_MEM4 - [15:0] - write-only - - - - - INSTR_MEM5 - Write-only access to instruction memory location 5 - 0x005c - 0x00000000 - - - INSTR_MEM5 - [15:0] - write-only - - - - - INSTR_MEM6 - Write-only access to instruction memory location 6 - 0x0060 - 0x00000000 - - - INSTR_MEM6 - [15:0] - write-only - - - - - INSTR_MEM7 - Write-only access to instruction memory location 7 - 0x0064 - 0x00000000 - - - INSTR_MEM7 - [15:0] - write-only - - - - - INSTR_MEM8 - Write-only access to instruction memory location 8 - 0x0068 - 0x00000000 - - - INSTR_MEM8 - [15:0] - write-only - - - - - INSTR_MEM9 - Write-only access to instruction memory location 9 - 0x006c - 0x00000000 - - - INSTR_MEM9 - [15:0] - write-only - - - - - INSTR_MEM10 - Write-only access to instruction memory location 10 - 0x0070 - 0x00000000 - - - INSTR_MEM10 - [15:0] - write-only - - - - - INSTR_MEM11 - Write-only access to instruction memory location 11 - 0x0074 - 0x00000000 - - - INSTR_MEM11 - [15:0] - write-only - - - - - INSTR_MEM12 - Write-only access to instruction memory location 12 - 0x0078 - 0x00000000 - - - INSTR_MEM12 - [15:0] - write-only - - - - - INSTR_MEM13 - Write-only access to instruction memory location 13 - 0x007c - 0x00000000 - - - INSTR_MEM13 - [15:0] - write-only - - - - - INSTR_MEM14 - Write-only access to instruction memory location 14 - 0x0080 - 0x00000000 - - - INSTR_MEM14 - [15:0] - write-only - - - - - INSTR_MEM15 - Write-only access to instruction memory location 15 - 0x0084 - 0x00000000 - - - INSTR_MEM15 - [15:0] - write-only - - - - - INSTR_MEM16 - Write-only access to instruction memory location 16 - 0x0088 - 0x00000000 - - - INSTR_MEM16 - [15:0] - write-only - - - - - INSTR_MEM17 - Write-only access to instruction memory location 17 - 0x008c - 0x00000000 - - - INSTR_MEM17 - [15:0] - write-only - - - - - INSTR_MEM18 - Write-only access to instruction memory location 18 - 0x0090 - 0x00000000 - - - INSTR_MEM18 - [15:0] - write-only - - - - - INSTR_MEM19 - Write-only access to instruction memory location 19 - 0x0094 - 0x00000000 - - - INSTR_MEM19 - [15:0] - write-only - - - - - INSTR_MEM20 - Write-only access to instruction memory location 20 - 0x0098 - 0x00000000 - - - INSTR_MEM20 - [15:0] - write-only - - - - - INSTR_MEM21 - Write-only access to instruction memory location 21 - 0x009c - 0x00000000 - - - INSTR_MEM21 - [15:0] - write-only - - - - - INSTR_MEM22 - Write-only access to instruction memory location 22 - 0x00a0 - 0x00000000 - - - INSTR_MEM22 - [15:0] - write-only - - - - - INSTR_MEM23 - Write-only access to instruction memory location 23 - 0x00a4 - 0x00000000 - - - INSTR_MEM23 - [15:0] - write-only - - - - - INSTR_MEM24 - Write-only access to instruction memory location 24 - 0x00a8 - 0x00000000 - - - INSTR_MEM24 - [15:0] - write-only - - - - - INSTR_MEM25 - Write-only access to instruction memory location 25 - 0x00ac - 0x00000000 - - - INSTR_MEM25 - [15:0] - write-only - - - - - INSTR_MEM26 - Write-only access to instruction memory location 26 - 0x00b0 - 0x00000000 - - - INSTR_MEM26 - [15:0] - write-only - - - - - INSTR_MEM27 - Write-only access to instruction memory location 27 - 0x00b4 - 0x00000000 - - - INSTR_MEM27 - [15:0] - write-only - - - - - INSTR_MEM28 - Write-only access to instruction memory location 28 - 0x00b8 - 0x00000000 - - - INSTR_MEM28 - [15:0] - write-only - - - - - INSTR_MEM29 - Write-only access to instruction memory location 29 - 0x00bc - 0x00000000 - - - INSTR_MEM29 - [15:0] - write-only - - - - - INSTR_MEM30 - Write-only access to instruction memory location 30 - 0x00c0 - 0x00000000 - - - INSTR_MEM30 - [15:0] - write-only - - - - - INSTR_MEM31 - Write-only access to instruction memory location 31 - 0x00c4 - 0x00000000 - - - INSTR_MEM31 - [15:0] - write-only - - - - - SM0_CLKDIV - Clock divisor register for state machine 0\n - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00c8 - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256).\n - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM0_EXECCTRL - Execution/behavioural settings for state machine 0 - 0x00cc - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable\n - When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n - deassert the latest pin write. This can create useful masking/override behaviour\n - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom.\n - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - All-ones if TX FIFO level < N, otherwise all-zeroes - 0 - - - RXLEVEL - All-ones if RX FIFO level < N, otherwise all-zeroes - 1 - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM0_SHIFTCTRL - Control behaviour of the input/output shift registers for state machine 0 - 0x00d0 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n - TX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n - RX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM0_ADDR - Current instruction address of state machine 0 - 0x00d4 - 0x00000000 - - - SM0_ADDR - [4:0] - read-only - - - - - SM0_INSTR - Read to see the instruction currently addressed by state machine 0's program counter\n - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00d8 - 0x00000000 - - - SM0_INSTR - [15:0] - read-write - - - - - SM0_PINCTRL - State machine pin control - 0x00dc - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM1_CLKDIV - Clock divisor register for state machine 1\n - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00e0 - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256).\n - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM1_EXECCTRL - Execution/behavioural settings for state machine 1 - 0x00e4 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable\n - When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n - deassert the latest pin write. This can create useful masking/override behaviour\n - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom.\n - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - All-ones if TX FIFO level < N, otherwise all-zeroes - 0 - - - RXLEVEL - All-ones if RX FIFO level < N, otherwise all-zeroes - 1 - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM1_SHIFTCTRL - Control behaviour of the input/output shift registers for state machine 1 - 0x00e8 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n - TX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n - RX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM1_ADDR - Current instruction address of state machine 1 - 0x00ec - 0x00000000 - - - SM1_ADDR - [4:0] - read-only - - - - - SM1_INSTR - Read to see the instruction currently addressed by state machine 1's program counter\n - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x00f0 - 0x00000000 - - - SM1_INSTR - [15:0] - read-write - - - - - SM1_PINCTRL - State machine pin control - 0x00f4 - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM2_CLKDIV - Clock divisor register for state machine 2\n - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x00f8 - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256).\n - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM2_EXECCTRL - Execution/behavioural settings for state machine 2 - 0x00fc - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable\n - When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n - deassert the latest pin write. This can create useful masking/override behaviour\n - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom.\n - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - All-ones if TX FIFO level < N, otherwise all-zeroes - 0 - - - RXLEVEL - All-ones if RX FIFO level < N, otherwise all-zeroes - 1 - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM2_SHIFTCTRL - Control behaviour of the input/output shift registers for state machine 2 - 0x0100 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n - TX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n - RX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM2_ADDR - Current instruction address of state machine 2 - 0x0104 - 0x00000000 - - - SM2_ADDR - [4:0] - read-only - - - - - SM2_INSTR - Read to see the instruction currently addressed by state machine 2's program counter\n - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x0108 - 0x00000000 - - - SM2_INSTR - [15:0] - read-write - - - - - SM2_PINCTRL - State machine pin control - 0x010c - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - SM3_CLKDIV - Clock divisor register for state machine 3\n - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x0110 - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256).\n - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM3_EXECCTRL - Execution/behavioural settings for state machine 3 - 0x0114 - 0x0001f000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable\n - When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n - deassert the latest pin write. This can create useful masking/override behaviour\n - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom.\n - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - All-ones if TX FIFO level < N, otherwise all-zeroes - 0 - - - RXLEVEL - All-ones if RX FIFO level < N, otherwise all-zeroes - 1 - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM3_SHIFTCTRL - Control behaviour of the input/output shift registers for state machine 3 - 0x0118 - 0x000c0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n - TX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n - RX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM3_ADDR - Current instruction address of state machine 3 - 0x011c - 0x00000000 - - - SM3_ADDR - [4:0] - read-only - - - - - SM3_INSTR - Read to see the instruction currently addressed by state machine 3's program counter\n - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x0120 - 0x00000000 - - - SM3_INSTR - [15:0] - read-write - - - - - SM3_PINCTRL - State machine pin control - 0x0124 - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - - INTR - Raw Interrupts - 0x0128 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - IRQ0_INTE - Interrupt Enable for irq0 - 0x012c - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ0_INTF - Interrupt Force for irq0 - 0x0130 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ0_INTS - Interrupt status after masking & forcing for irq0 - 0x0134 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - IRQ1_INTE - Interrupt Enable for irq1 - 0x0138 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ1_INTF - Interrupt Force for irq1 - 0x013c - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ1_INTS - Interrupt status after masking & forcing for irq1 - 0x0140 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - - - PIO1 - 0x50300000 - - PIO1_IRQ_0 - 9 - - - PIO1_IRQ_1 - 10 - - - - SIO - 1 - Single-cycle IO block\n - Provides core-local and inter-core hardware for the two processors, with single-cycle access. - 0xd0000000 - 32 - - 0 - 0x0200 - registers - - - SIO_IRQ_PROC0 - 15 - - - SIO_IRQ_PROC1 - 16 - - - - CPUID - Processor core identifier\n - Value is 0 when read from processor core 0, and 1 when read from processor core 1. - 0x0000 - read-only - 0x00000000 - - - GPIO_IN - Input value for GPIO pins - 0x0004 - 0x00000000 - - - GPIO_IN - Input value for GPIO0...29 - [29:0] - read-only - - - - - GPIO_HI_IN - Input value for QSPI pins - 0x0008 - 0x00000000 - - - GPIO_HI_IN - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 - [5:0] - read-only - - - - - GPIO_OUT - GPIO output value - 0x0010 - 0x00000000 - - - GPIO_OUT - Set output level (1/0 -> high/low) for GPIO0...29.\n - Reading back gives the last value written, NOT the input value from the pins.\n - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [29:0] - read-write - - - - - GPIO_OUT_SET - GPIO output value set - 0x0014 - 0x00000000 - - - GPIO_OUT_SET - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` - [29:0] - write-only - - - - - GPIO_OUT_CLR - GPIO output value clear - 0x0018 - 0x00000000 - - - GPIO_OUT_CLR - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` - [29:0] - write-only - - - - - GPIO_OUT_XOR - GPIO output value XOR - 0x001c - 0x00000000 - - - GPIO_OUT_XOR - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` - [29:0] - write-only - - - - - GPIO_OE - GPIO output enable - 0x0020 - 0x00000000 - - - GPIO_OE - Set output enable (1/0 -> output/input) for GPIO0...29.\n - Reading back gives the last value written.\n - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [29:0] - read-write - - - - - GPIO_OE_SET - GPIO output enable set - 0x0024 - 0x00000000 - - - GPIO_OE_SET - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` - [29:0] - write-only - - - - - GPIO_OE_CLR - GPIO output enable clear - 0x0028 - 0x00000000 - - - GPIO_OE_CLR - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` - [29:0] - write-only - - - - - GPIO_OE_XOR - GPIO output enable XOR - 0x002c - 0x00000000 - - - GPIO_OE_XOR - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` - [29:0] - write-only - - - - - GPIO_HI_OUT - QSPI output value - 0x0030 - 0x00000000 - - - GPIO_HI_OUT - Set output level (1/0 -> high/low) for QSPI IO0...5.\n - Reading back gives the last value written, NOT the input value from the pins.\n - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [5:0] - read-write - - - - - GPIO_HI_OUT_SET - QSPI output value set - 0x0034 - 0x00000000 - - - GPIO_HI_OUT_SET - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` - [5:0] - write-only - - - - - GPIO_HI_OUT_CLR - QSPI output value clear - 0x0038 - 0x00000000 - - - GPIO_HI_OUT_CLR - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` - [5:0] - write-only - - - - - GPIO_HI_OUT_XOR - QSPI output value XOR - 0x003c - 0x00000000 - - - GPIO_HI_OUT_XOR - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` - [5:0] - write-only - - - - - GPIO_HI_OE - QSPI output enable - 0x0040 - 0x00000000 - - - GPIO_HI_OE - Set output enable (1/0 -> output/input) for QSPI IO0...5.\n - Reading back gives the last value written.\n - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [5:0] - read-write - - - - - GPIO_HI_OE_SET - QSPI output enable set - 0x0044 - 0x00000000 - - - GPIO_HI_OE_SET - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` - [5:0] - write-only - - - - - GPIO_HI_OE_CLR - QSPI output enable clear - 0x0048 - 0x00000000 - - - GPIO_HI_OE_CLR - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` - [5:0] - write-only - - - - - GPIO_HI_OE_XOR - QSPI output enable XOR - 0x004c - 0x00000000 - - - GPIO_HI_OE_XOR - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` - [5:0] - write-only - - - - - FIFO_ST - Status register for inter-core FIFOs (mailboxes).\n - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. - 0x0050 - 0x00000002 - - - ROE - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. - [3:3] - read-write - oneToClear - - - WOF - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. - [2:2] - read-write - oneToClear - - - RDY - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) - [1:1] - read-only - - - VLD - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) - [0:0] - read-only - - - - - FIFO_WR - Write access to this core's TX FIFO - 0x0054 - write-only - 0x00000000 - - - FIFO_RD - Read access to this core's RX FIFO - 0x0058 - read-only - 0x00000000 - - - SPINLOCK_ST - Spinlock state\n - A bitmap containing the state of all 32 spinlocks (1=locked).\n - Mainly intended for debugging. - 0x005c - read-only - 0x00000000 - - - DIV_UDIVIDEND - Divider unsigned dividend\n - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n - unsigned calculation, and the S alias starts a signed calculation. - 0x0060 - read-write - 0x00000000 - - - DIV_UDIVISOR - Divider unsigned divisor\n - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\n - unsigned calculation, and the S alias starts a signed calculation. - 0x0064 - read-write - 0x00000000 - - - DIV_SDIVIDEND - Divider signed dividend\n - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. - 0x0068 - read-write - 0x00000000 - - - DIV_SDIVISOR - Divider signed divisor\n - The same as UDIVISOR, but starts a signed calculation, rather than unsigned. - 0x006c - read-write - 0x00000000 - - - DIV_QUOTIENT - Divider result quotient\n - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n - This register can be written to directly, for context save/restore purposes. This halts any\n - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n - REMAINDER, QUOTIENT if CSR_DIRTY is used. - 0x0070 - read-write - 0x00000000 - - - DIV_REMAINDER - Divider result remainder\n - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n - For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n - This register can be written to directly, for context save/restore purposes. This halts any\n - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - 0x0074 - read-write - 0x00000000 - - - DIV_CSR - Control and status register for divider. - 0x0078 - 0x00000001 - - - DIRTY - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n - Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n - If the flag is used in this way, it's recommended to either read QUOTIENT only,\n - or REMAINDER and then QUOTIENT, to prevent data loss on context switch. - [1:1] - read-only - - - READY - Reads as 0 when a calculation is in progress, 1 otherwise.\n - Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n - matter if one is already in progress.\n - Writing to a result register will immediately terminate any in-progress calculation\n - and set the READY and DIRTY flags. - [0:0] - read-only - - - - - INTERP0_ACCUM0 - Read/write access to accumulator 0 - 0x0080 - read-write - 0x00000000 - - - INTERP0_ACCUM1 - Read/write access to accumulator 1 - 0x0084 - read-write - 0x00000000 - - - INTERP0_BASE0 - Read/write access to BASE0 register. - 0x0088 - read-write - 0x00000000 - - - INTERP0_BASE1 - Read/write access to BASE1 register. - 0x008c - read-write - 0x00000000 - - - INTERP0_BASE2 - Read/write access to BASE2 register. - 0x0090 - read-write - 0x00000000 - - - INTERP0_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x0094 - read-only - 0x00000000 - - - INTERP0_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x0098 - read-only - 0x00000000 - - - INTERP0_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x009c - read-only - 0x00000000 - - - INTERP0_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0x00a0 - read-only - 0x00000000 - - - INTERP0_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0x00a4 - read-only - 0x00000000 - - - INTERP0_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0x00a8 - read-only - 0x00000000 - - - INTERP0_CTRL_LANE0 - Control register for lane 0 - 0x00ac - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - BLEND - Only present on INTERP0 on each core. If BLEND mode is enabled:\n - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n - by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n - 0 and 255/256ths)\n - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. - [21:21] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP0_CTRL_LANE1 - Control register for lane 1 - 0x00b0 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP0_ACCUM0_ADD - Values written here are atomically added to ACCUM0\n - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0x00b4 - 0x00000000 - - - INTERP0_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP0_ACCUM1_ADD - Values written here are atomically added to ACCUM1\n - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0x00b8 - 0x00000000 - - - INTERP0_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP0_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0x00bc - write-only - 0x00000000 - - - INTERP1_ACCUM0 - Read/write access to accumulator 0 - 0x00c0 - read-write - 0x00000000 - - - INTERP1_ACCUM1 - Read/write access to accumulator 1 - 0x00c4 - read-write - 0x00000000 - - - INTERP1_BASE0 - Read/write access to BASE0 register. - 0x00c8 - read-write - 0x00000000 - - - INTERP1_BASE1 - Read/write access to BASE1 register. - 0x00cc - read-write - 0x00000000 - - - INTERP1_BASE2 - Read/write access to BASE2 register. - 0x00d0 - read-write - 0x00000000 - - - INTERP1_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x00d4 - read-only - 0x00000000 - - - INTERP1_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x00d8 - read-only - 0x00000000 - - - INTERP1_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x00dc - read-only - 0x00000000 - - - INTERP1_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0x00e0 - read-only - 0x00000000 - - - INTERP1_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0x00e4 - read-only - 0x00000000 - - - INTERP1_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0x00e8 - read-only - 0x00000000 - - - INTERP1_CTRL_LANE0 - Control register for lane 0 - 0x00ec - 0x00000000 - - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only - - - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only - - - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only - - - CLAMP - Only present on INTERP1 on each core. If CLAMP mode is enabled:\n - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n - BASE0 and an upper bound of BASE1.\n - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED - [22:22] - read-write - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP1_CTRL_LANE1 - Control register for lane 1 - 0x00f0 - 0x00000000 - - - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] - read-write - - - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write - - - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] - read-write - - - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] - read-write - - - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write - - - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write - - - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write - - - - - INTERP1_ACCUM0_ADD - Values written here are atomically added to ACCUM0\n - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0x00f4 - 0x00000000 - - - INTERP1_ACCUM0_ADD - [23:0] - read-write - - - - - INTERP1_ACCUM1_ADD - Values written here are atomically added to ACCUM1\n - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0x00f8 - 0x00000000 - - - INTERP1_ACCUM1_ADD - [23:0] - read-write - - - - - INTERP1_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0x00fc - write-only - 0x00000000 - - - SPINLOCK0 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0100 - read-write - 0x00000000 - - - SPINLOCK1 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0104 - read-write - 0x00000000 - - - SPINLOCK2 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0108 - read-write - 0x00000000 - - - SPINLOCK3 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x010c - read-write - 0x00000000 - - - SPINLOCK4 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0110 - read-write - 0x00000000 - - - SPINLOCK5 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0114 - read-write - 0x00000000 - - - SPINLOCK6 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0118 - read-write - 0x00000000 - - - SPINLOCK7 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x011c - read-write - 0x00000000 - - - SPINLOCK8 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0120 - read-write - 0x00000000 - - - SPINLOCK9 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0124 - read-write - 0x00000000 - - - SPINLOCK10 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0128 - read-write - 0x00000000 - - - SPINLOCK11 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x012c - read-write - 0x00000000 - - - SPINLOCK12 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0130 - read-write - 0x00000000 - - - SPINLOCK13 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0134 - read-write - 0x00000000 - - - SPINLOCK14 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0138 - read-write - 0x00000000 - - - SPINLOCK15 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x013c - read-write - 0x00000000 - - - SPINLOCK16 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0140 - read-write - 0x00000000 - - - SPINLOCK17 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0144 - read-write - 0x00000000 - - - SPINLOCK18 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0148 - read-write - 0x00000000 - - - SPINLOCK19 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x014c - read-write - 0x00000000 - - - SPINLOCK20 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0150 - read-write - 0x00000000 - - - SPINLOCK21 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0154 - read-write - 0x00000000 - - - SPINLOCK22 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0158 - read-write - 0x00000000 - - - SPINLOCK23 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x015c - read-write - 0x00000000 - - - SPINLOCK24 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0160 - read-write - 0x00000000 - - - SPINLOCK25 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0164 - read-write - 0x00000000 - - - SPINLOCK26 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0168 - read-write - 0x00000000 - - - SPINLOCK27 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x016c - read-write - 0x00000000 - - - SPINLOCK28 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0170 - read-write - 0x00000000 - - - SPINLOCK29 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0174 - read-write - 0x00000000 - - - SPINLOCK30 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x0178 - read-write - 0x00000000 - - - SPINLOCK31 - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x017c - read-write - 0x00000000 - - - - - PPB - 1 - 0xe0000000 - 32 - - 0 - 0x10000 - registers - - - - SYST_CSR - Use the SysTick Control and Status Register to enable the SysTick features. - 0xe010 - 0x00000000 - - - COUNTFLAG - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. - [16:16] - read-only - - - CLKSOURCE - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n - Selects the SysTick timer clock source:\n - 0 = External reference clock.\n - 1 = Processor clock. - [2:2] - read-write - - - TICKINT - Enables SysTick exception request:\n - 0 = Counting down to zero does not assert the SysTick exception request.\n - 1 = Counting down to zero to asserts the SysTick exception request. - [1:1] - read-write - - - ENABLE - Enable SysTick counter:\n - 0 = Counter disabled.\n - 1 = Counter enabled. - [0:0] - read-write - - - - - SYST_RVR - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. - 0xe014 - 0x00000000 - - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0. - [23:0] - read-write - - - - - SYST_CVR - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. - 0xe018 - 0x00000000 - - - CURRENT - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. - [23:0] - read-write - - - - - SYST_CALIB - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. - 0xe01c - 0x00000000 - - - NOREF - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. - [31:31] - read-only - - - SKEW - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). - [30:30] - read-only - - - TENMS - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. - [23:0] - read-only - - - - - NVIC_ISER - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. - 0xe100 - 0x00000000 - - - SETENA - Interrupt set-enable bits.\n - Write:\n - 0 = No effect.\n - 1 = Enable interrupt.\n - Read:\n - 0 = Interrupt disabled.\n - 1 = Interrupt enabled. - [31:0] - read-write - - - - - NVIC_ICER - Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. - 0xe180 - 0x00000000 - - - CLRENA - Interrupt clear-enable bits.\n - Write:\n - 0 = No effect.\n - 1 = Disable interrupt.\n - Read:\n - 0 = Interrupt disabled.\n - 1 = Interrupt enabled. - [31:0] - read-write - - - - - NVIC_ISPR - The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. - 0xe200 - 0x00000000 - - - SETPEND - Interrupt set-pending bits.\n - Write:\n - 0 = No effect.\n - 1 = Changes interrupt state to pending.\n - Read:\n - 0 = Interrupt is not pending.\n - 1 = Interrupt is pending.\n - Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n - An interrupt that is pending has no effect.\n - A disabled interrupt sets the state of that interrupt to pending. - [31:0] - read-write - - - - - NVIC_ICPR - Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. - 0xe280 - 0x00000000 - - - CLRPEND - Interrupt clear-pending bits.\n - Write:\n - 0 = No effect.\n - 1 = Removes pending state and interrupt.\n - Read:\n - 0 = Interrupt is not pending.\n - 1 = Interrupt is pending. - [31:0] - read-write - - - - - NVIC_IPR0 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n - These registers are only word-accessible - 0xe400 - 0x00000000 - - - IP_3 - Priority of interrupt 3 - [31:30] - read-write - - - IP_2 - Priority of interrupt 2 - [23:22] - read-write - - - IP_1 - Priority of interrupt 1 - [15:14] - read-write - - - IP_0 - Priority of interrupt 0 - [7:6] - read-write - - - - - NVIC_IPR1 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xe404 - 0x00000000 - - - IP_7 - Priority of interrupt 7 - [31:30] - read-write - - - IP_6 - Priority of interrupt 6 - [23:22] - read-write - - - IP_5 - Priority of interrupt 5 - [15:14] - read-write - - - IP_4 - Priority of interrupt 4 - [7:6] - read-write - - - - - NVIC_IPR2 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xe408 - 0x00000000 - - - IP_11 - Priority of interrupt 11 - [31:30] - read-write - - - IP_10 - Priority of interrupt 10 - [23:22] - read-write - - - IP_9 - Priority of interrupt 9 - [15:14] - read-write - - - IP_8 - Priority of interrupt 8 - [7:6] - read-write - - - - - NVIC_IPR3 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xe40c - 0x00000000 - - - IP_15 - Priority of interrupt 15 - [31:30] - read-write - - - IP_14 - Priority of interrupt 14 - [23:22] - read-write - - - IP_13 - Priority of interrupt 13 - [15:14] - read-write - - - IP_12 - Priority of interrupt 12 - [7:6] - read-write - - - - - NVIC_IPR4 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xe410 - 0x00000000 - - - IP_19 - Priority of interrupt 19 - [31:30] - read-write - - - IP_18 - Priority of interrupt 18 - [23:22] - read-write - - - IP_17 - Priority of interrupt 17 - [15:14] - read-write - - - IP_16 - Priority of interrupt 16 - [7:6] - read-write - - - - - NVIC_IPR5 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xe414 - 0x00000000 - - - IP_23 - Priority of interrupt 23 - [31:30] - read-write - - - IP_22 - Priority of interrupt 22 - [23:22] - read-write - - - IP_21 - Priority of interrupt 21 - [15:14] - read-write - - - IP_20 - Priority of interrupt 20 - [7:6] - read-write - - - - - NVIC_IPR6 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xe418 - 0x00000000 - - - IP_27 - Priority of interrupt 27 - [31:30] - read-write - - - IP_26 - Priority of interrupt 26 - [23:22] - read-write - - - IP_25 - Priority of interrupt 25 - [15:14] - read-write - - - IP_24 - Priority of interrupt 24 - [7:6] - read-write - - - - - NVIC_IPR7 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xe41c - 0x00000000 - - - IP_31 - Priority of interrupt 31 - [31:30] - read-write - - - IP_30 - Priority of interrupt 30 - [23:22] - read-write - - - IP_29 - Priority of interrupt 29 - [15:14] - read-write - - - IP_28 - Priority of interrupt 28 - [7:6] - read-write - - - - - CPUID - Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. - 0xed00 - 0x410cc601 - - - IMPLEMENTER - Implementor code: 0x41 = ARM - [31:24] - read-only - - - VARIANT - Major revision number n in the rnpm revision status:\n - 0x0 = Revision 0. - [23:20] - read-only - - - ARCHITECTURE - Constant that defines the architecture of the processor:\n - 0xC = ARMv6-M architecture. - [19:16] - read-only - - - PARTNO - Number of processor within family: 0xC60 = Cortex-M0+ - [15:4] - read-only - - - REVISION - Minor revision number m in the rnpm revision status:\n - 0x1 = Patch 1. - [3:0] - read-only - - - - - ICSR - Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. - 0xed04 - 0x00000000 - - - NMIPENDSET - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n - NMI set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes NMI exception state to pending.\n - Read:\n - 0 = NMI exception is not pending.\n - 1 = NMI exception is pending.\n - Because NMI is the highest-priority exception, normally the processor enters the NMI\n - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n - NMI signal is reasserted while the processor is executing that handler. - [31:31] - read-write - - - PENDSVSET - PendSV set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes PendSV exception state to pending.\n - Read:\n - 0 = PendSV exception is not pending.\n - 1 = PendSV exception is pending.\n - Writing 1 to this bit is the only way to set the PendSV exception state to pending. - [28:28] - read-write - - - PENDSVCLR - PendSV clear-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Removes the pending state from the PendSV exception. - [27:27] - read-write - - - PENDSTSET - SysTick exception set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes SysTick exception state to pending.\n - Read:\n - 0 = SysTick exception is not pending.\n - 1 = SysTick exception is pending. - [26:26] - read-write - - - PENDSTCLR - SysTick exception clear-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Removes the pending state from the SysTick exception.\n - This bit is WO. On a register read its value is Unknown. - [25:25] - read-write - - - ISRPREEMPT - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. - [23:23] - read-only - - - ISRPENDING - External interrupt pending flag - [22:22] - read-only - - - VECTPENDING - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. - [20:12] - read-only - - - VECTACTIVE - Active exception number field. Reset clears the VECTACTIVE field. - [8:0] - read-only - - - - - VTOR - The VTOR holds the vector table offset address. - 0xed08 - 0x00000000 - - - TBLOFF - Bits [31:8] of the indicate the vector table offset address. - [31:8] - read-write - - - - - AIRCR - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. - 0xed0c - 0x00000000 - - - VECTKEY - Register key:\n - Reads as Unknown\n - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. - [31:16] - read-write - - - ENDIANESS - Data endianness implemented:\n - 0 = Little-endian. - [15:15] - read-only - - - SYSRESETREQ - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. - [2:2] - read-write - - - VECTCLRACTIVE - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. - [1:1] - read-write - - - - - SCR - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. - 0xed10 - 0x00000000 - - - SEVONPEND - Send Event on Pending bit:\n - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n - processor is not waiting for an event, the event is registered and affects the next WFE.\n - The processor also wakes up on execution of an SEV instruction or an external event. - [4:4] - read-write - - - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode:\n - 0 = Sleep.\n - 1 = Deep sleep. - [2:2] - read-write - - - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n - 0 = Do not sleep when returning to Thread mode.\n - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - [1:1] - read-write - - - - - CCR - The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. - 0xed14 - 0x00000000 - - - STKALIGN - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. - [9:9] - read-only - - - UNALIGN_TRP - Always reads as one, indicates that all unaligned accesses generate a HardFault. - [3:3] - read-only - - - - - SHPR2 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. - 0xed1c - 0x00000000 - - - PRI_11 - Priority of system handler 11, SVCall - [31:30] - read-write - - - - - SHPR3 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. - 0xed20 - 0x00000000 - - - PRI_15 - Priority of system handler 15, SysTick - [31:30] - read-write - - - PRI_14 - Priority of system handler 14, PendSV - [23:22] - read-write - - - - - SHCSR - Use the System Handler Control and State Register to determine or clear the pending status of SVCall. - 0xed24 - 0x00000000 - - - SVCALLPENDED - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. - [15:15] - read-write - - - - - MPU_TYPE - Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. - 0xed90 - 0x00000800 - - - IREGION - Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. - [23:16] - read-only - - - DREGION - Number of regions supported by the MPU. - [15:8] - read-only - - - SEPARATE - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. - [0:0] - read-only - - - - - MPU_CTRL - Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. - 0xed94 - 0x00000000 - - - PRIVDEFENA - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n - covered by any enabled region causes a fault.\n - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. - [2:2] - read-write - - - HFNMIENA - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n - When the MPU is enabled:\n - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n - 1 = the MPU is enabled during HardFault and NMI handlers. - [1:1] - read-write - - - ENABLE - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n - 0 = MPU disabled.\n - 1 = MPU enabled. - [0:0] - read-write - - - - - MPU_RNR - Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. - 0xed98 - 0x00000000 - - - REGION - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n - The MPU supports 8 memory regions, so the permitted values of this field are 0-7. - [3:0] - read-write - - - - - MPU_RBAR - Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. - 0xed9c - 0x00000000 - - - ADDR - Base address of the region. - [31:8] - read-write - - - VALID - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n - Write:\n - 0 = MPU_RNR not changed, and the processor:\n - Updates the base address for the region specified in the MPU_RNR.\n - Ignores the value of the REGION field.\n - 1 = The processor:\n - Updates the value of the MPU_RNR to the value of the REGION field.\n - Updates the base address for the region specified in the REGION field.\n - Always reads as zero. - [4:4] - read-write - - - REGION - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. - [3:0] - read-write - - - - - MPU_RASR - Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. - 0xeda0 - 0x00000000 - - - ATTRS - The MPU Region Attribute field. Use to define the region attribute control.\n - 28 = XN: Instruction access disable bit:\n - 0 = Instruction fetches enabled.\n - 1 = Instruction fetches disabled.\n - 26:24 = AP: Access permission field\n - 18 = S: Shareable bit\n - 17 = C: Cacheable bit\n - 16 = B: Bufferable bit - [31:16] - read-write - - - SRD - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. - [15:8] - read-write - - - SIZE - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes - [5:1] - read-write - - - ENABLE - Enables the region. - [0:0] - read-write - - - - - - - \ No newline at end of file diff --git a/src/rp2040/hardware_structs/BUILD.bazel b/src/rp2040/hardware_structs/BUILD.bazel index a4ddb7bf4..75240454d 100644 --- a/src/rp2040/hardware_structs/BUILD.bazel +++ b/src/rp2040/hardware_structs/BUILD.bazel @@ -1,21 +1,32 @@ -# Always include these libraries through //src/rp2_common/pico_platform:*! +# Always include these libraries through //src/rp2_common:*! # This ensures that you'll get the right headers for the MCU you're targeting. -package(default_visibility = ["//src/rp2_common/pico_platform:__pkg__"]) +package( + default_visibility = [ + "//src/rp2040:__subpackages__", + "//src/rp2_common:__pkg__", + ], +) cc_library( name = "hardware_structs", hdrs = [ "include/hardware/structs/adc.h", "include/hardware/structs/bus_ctrl.h", + "include/hardware/structs/busctrl.h", "include/hardware/structs/clocks.h", "include/hardware/structs/dma.h", + "include/hardware/structs/dma_debug.h", "include/hardware/structs/i2c.h", "include/hardware/structs/interp.h", + "include/hardware/structs/io_bank0.h", + "include/hardware/structs/io_qspi.h", "include/hardware/structs/iobank0.h", "include/hardware/structs/ioqspi.h", + "include/hardware/structs/m0plus.h", "include/hardware/structs/mpu.h", "include/hardware/structs/nvic.h", + "include/hardware/structs/pads_bank0.h", "include/hardware/structs/pads_qspi.h", "include/hardware/structs/padsbank0.h", "include/hardware/structs/pio.h", @@ -30,12 +41,16 @@ cc_library( "include/hardware/structs/spi.h", "include/hardware/structs/ssi.h", "include/hardware/structs/syscfg.h", + "include/hardware/structs/sysinfo.h", "include/hardware/structs/systick.h", + "include/hardware/structs/tbman.h", "include/hardware/structs/timer.h", "include/hardware/structs/uart.h", "include/hardware/structs/usb.h", + "include/hardware/structs/usb_dpram.h", "include/hardware/structs/vreg_and_chip_reset.h", "include/hardware/structs/watchdog.h", + "include/hardware/structs/xip.h", "include/hardware/structs/xip_ctrl.h", "include/hardware/structs/xosc.h", ], diff --git a/src/rp2040/hardware_structs/CMakeLists.txt b/src/rp2040/hardware_structs/CMakeLists.txt index 2e11af269..39432130d 100644 --- a/src/rp2040/hardware_structs/CMakeLists.txt +++ b/src/rp2040/hardware_structs/CMakeLists.txt @@ -1,4 +1,4 @@ add_library(hardware_structs INTERFACE) add_library(hardware_structs_headers INTERFACE) -target_include_directories(hardware_structs_headers INTERFACE include) -pico_mirrored_target_link_libraries(hardware_structs INTERFACE hardware_regs) \ No newline at end of file +target_include_directories(hardware_structs_headers SYSTEM INTERFACE include) +pico_mirrored_target_link_libraries(hardware_structs INTERFACE hardware_regs) diff --git a/src/rp2040/hardware_structs/include/hardware/structs/adc.h b/src/rp2040/hardware_structs/include/hardware/structs/adc.h index 016137cd2..a1b6f34c5 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/adc.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/adc.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_ADC_H #define _HARDWARE_STRUCTS_ADC_H +/** + * \file rp2040/adc.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/adc.h" @@ -18,74 +21,76 @@ // _REG_(x) will link to the corresponding register in hardware/regs/adc.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(ADC_CS_OFFSET) // ADC_CS // ADC Control and Status - // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling - // 0x00007000 [14:12] : AINSEL (0): Select analog mux input - // 0x00000400 [10] : ERR_STICKY (0): Some past ADC conversion encountered an error - // 0x00000200 [9] : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy - // 0x00000100 [8] : READY (0): 1 if the ADC is ready to start a new conversion - // 0x00000008 [3] : START_MANY (0): Continuously perform conversions whilst this bit is 1 - // 0x00000004 [2] : START_ONCE (0): Start a single conversion - // 0x00000002 [1] : TS_EN (0): Power on temperature sensor - // 0x00000001 [0] : EN (0): Power on ADC and enable its clock + // 0x001f0000 [20:16] RROBIN (0x00) Round-robin sampling + // 0x00007000 [14:12] AINSEL (0x0) Select analog mux input + // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error + // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;... + // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion + // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1 + // 0x00000004 [2] START_ONCE (0) Start a single conversion + // 0x00000002 [1] TS_EN (0) Power on temperature sensor + // 0x00000001 [0] EN (0) Power on ADC and enable its clock io_rw_32 cs; - + _REG_(ADC_RESULT_OFFSET) // ADC_RESULT // Result of most recent ADC conversion - // 0x00000fff [11:0] : RESULT (0) + // 0x00000fff [11:0] RESULT (0x000) io_ro_32 result; - + _REG_(ADC_FCS_OFFSET) // ADC_FCS // FIFO control and status - // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold - // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO - // 0x00000800 [11] : OVER (0): 1 if the FIFO has been overflowed - // 0x00000400 [10] : UNDER (0): 1 if the FIFO has been underflowed - // 0x00000200 [9] : FULL (0) - // 0x00000100 [8] : EMPTY (0) - // 0x00000008 [3] : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data - // 0x00000004 [2] : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result - // 0x00000002 [1] : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size - // 0x00000001 [0] : EN (0): If 1: write result to the FIFO after each conversion + // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold + // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO + // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed + // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed + // 0x00000200 [9] FULL (0) + // 0x00000100 [8] EMPTY (0) + // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data + // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside... + // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size + // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion io_rw_32 fcs; - + _REG_(ADC_FIFO_OFFSET) // ADC_FIFO // Conversion result FIFO - // 0x00008000 [15] : ERR (0): 1 if this particular sample experienced a conversion error - // 0x00000fff [11:0] : VAL (0) + // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error + // 0x00000fff [11:0] VAL (-) io_ro_32 fifo; - + _REG_(ADC_DIV_OFFSET) // ADC_DIV // Clock divider - // 0x00ffff00 [23:8] : INT (0): Integer part of clock divisor - // 0x000000ff [7:0] : FRAC (0): Fractional part of clock divisor + // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor + // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor io_rw_32 div; - + _REG_(ADC_INTR_OFFSET) // ADC_INTR // Raw Interrupts - // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level io_ro_32 intr; - + _REG_(ADC_INTE_OFFSET) // ADC_INTE // Interrupt Enable - // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level io_rw_32 inte; - + _REG_(ADC_INTF_OFFSET) // ADC_INTF // Interrupt Force - // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level io_rw_32 intf; - + _REG_(ADC_INTS_OFFSET) // ADC_INTS // Interrupt status after masking & forcing - // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level io_ro_32 ints; } adc_hw_t; #define adc_hw ((adc_hw_t *)ADC_BASE) +static_assert(sizeof (adc_hw_t) == 0x0024, ""); + +#endif // _HARDWARE_STRUCTS_ADC_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h b/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h index d4e819e10..b94a40459 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h @@ -1,77 +1,9 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H -#define _HARDWARE_STRUCTS_BUS_CTRL_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/busctrl.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION - -enum bus_ctrl_perf_counter { - arbiter_rom_perf_event_access = 19, - arbiter_rom_perf_event_access_contested = 18, - arbiter_xip_main_perf_event_access = 17, - arbiter_xip_main_perf_event_access_contested = 16, - arbiter_sram0_perf_event_access = 15, - arbiter_sram0_perf_event_access_contested = 14, - arbiter_sram1_perf_event_access = 13, - arbiter_sram1_perf_event_access_contested = 12, - arbiter_sram2_perf_event_access = 11, - arbiter_sram2_perf_event_access_contested = 10, - arbiter_sram3_perf_event_access = 9, - arbiter_sram3_perf_event_access_contested = 8, - arbiter_sram4_perf_event_access = 7, - arbiter_sram4_perf_event_access_contested = 6, - arbiter_sram5_perf_event_access = 5, - arbiter_sram5_perf_event_access_contested = 4, - arbiter_fastperi_perf_event_access = 3, - arbiter_fastperi_perf_event_access_contested = 2, - arbiter_apb_perf_event_access = 1, - arbiter_apb_perf_event_access_contested = 0 -}; - -typedef struct { - _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 - // Bus fabric performance counter 0 - // 0x00ffffff [23:0] : PERFCTR0 (0): Busfabric saturating performance counter 0 - io_rw_32 value; - - _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 - // Bus fabric performance event select for PERFCTR0 - // 0x0000001f [4:0] : PERFSEL0 (0x1f): Select an event for PERFCTR0 - io_rw_32 sel; -} bus_ctrl_perf_hw_t; - -typedef struct { - _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY - // Set the priority of each master for bus arbitration - // 0x00001000 [12] : DMA_W (0): 0 - low priority, 1 - high priority - // 0x00000100 [8] : DMA_R (0): 0 - low priority, 1 - high priority - // 0x00000010 [4] : PROC1 (0): 0 - low priority, 1 - high priority - // 0x00000001 [0] : PROC0 (0): 0 - low priority, 1 - high priority - io_rw_32 priority; - - _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK - // Bus priority acknowledge - // 0x00000001 [0] : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels - io_ro_32 priority_ack; - - bus_ctrl_perf_hw_t counter[4]; -} bus_ctrl_hw_t; - -#define bus_ctrl_hw ((bus_ctrl_hw_t *)BUSCTRL_BASE) - -#endif +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/busctrl.h" +#define bus_ctrl_hw busctrl_hw \ No newline at end of file diff --git a/src/rp2040/hardware_structs/include/hardware/structs/busctrl.h b/src/rp2040/hardware_structs/include/hardware/structs/busctrl.h new file mode 100644 index 000000000..65893227d --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/busctrl.h @@ -0,0 +1,85 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUSCTRL_H +#define _HARDWARE_STRUCTS_BUSCTRL_H + +/** + * \file rp2040/busctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Bus fabric performance counters on RP2040 (used as typedef \ref bus_ctrl_perf_counter_t) + * \ingroup hardware_busctrl + */ +typedef enum bus_ctrl_perf_counter_rp2040 { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +} bus_ctrl_perf_counter_t; + +typedef struct { + _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 + // Bus fabric performance counter 0 + // 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 + + io_rw_32 value; + + _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 + // Bus fabric performance event select for PERFCTR0 + // 0x0000001f [4:0] PERFSEL0 (0x1f) Select an event for PERFCTR0 + io_rw_32 sel; +} bus_ctrl_perf_hw_t; + +typedef struct { + _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY + // Set the priority of each master for bus arbitration + // 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority + // 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority + // 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority + // 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority + io_rw_32 priority; + + _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK + // Bus priority acknowledge + // 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new... + io_ro_32 priority_ack; + + bus_ctrl_perf_hw_t counter[4]; +} busctrl_hw_t; + +#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE) +static_assert(sizeof (busctrl_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_BUSCTRL_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/clocks.h b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h index 0d27da5f3..bdca7ee08 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/clocks.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/clocks.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_CLOCKS_H #define _HARDWARE_STRUCTS_CLOCKS_H +/** + * \file rp2040/clocks.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/clocks.h" @@ -18,309 +21,484 @@ // _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION -/*! \brief Enumeration identifying a hardware clock +/** \brief Clock numbers on RP2040 (used as typedef \ref clock_num_t) * \ingroup hardware_clocks */ /// \tag::clkenum[] -enum clock_index { - clk_gpout0 = 0, ///< GPIO Muxing 0 - clk_gpout1, ///< GPIO Muxing 1 - clk_gpout2, ///< GPIO Muxing 2 - clk_gpout3, ///< GPIO Muxing 3 - clk_ref, ///< Watchdog and timers reference clock - clk_sys, ///< Processors, bus fabric, memory, memory mapped registers - clk_peri, ///< Peripheral clock for UART and SPI - clk_usb, ///< USB clock - clk_adc, ///< ADC clock - clk_rtc, ///< Real time clock +typedef enum clock_num_rp2040 { + clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source + clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source + clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source + clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source + clk_ref = 4, ///< Select CLK_REF as clock source + clk_sys = 5, ///< Select CLK_SYS as clock source + clk_peri = 6, ///< Select CLK_PERI as clock source + clk_usb = 7, ///< Select CLK_USB as clock source + clk_adc = 8, ///< Select CLK_ADC as clock source + clk_rtc = 9, ///< Select CLK_RTC as clock source CLK_COUNT -}; +} clock_num_t; /// \end::clkenum[] +/** \brief Clock destination numbers on RP2040 (used as typedef \ref clock_dest_num_t) + * \ingroup hardware_clocks + */ +typedef enum clock_dest_num_rp2040 { + CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination + CLK_DEST_ADC_ADC = 1, ///< Select ADC_ADC as clock destination + CLK_DEST_SYS_ADC = 2, ///< Select SYS_ADC as clock destination + CLK_DEST_SYS_BUSCTRL = 3, ///< Select SYS_BUSCTRL as clock destination + CLK_DEST_SYS_BUSFABRIC = 4, ///< Select SYS_BUSFABRIC as clock destination + CLK_DEST_SYS_DMA = 5, ///< Select SYS_DMA as clock destination + CLK_DEST_SYS_I2C0 = 6, ///< Select SYS_I2C0 as clock destination + CLK_DEST_SYS_I2C1 = 7, ///< Select SYS_I2C1 as clock destination + CLK_DEST_SYS_IO = 8, ///< Select SYS_IO as clock destination + CLK_DEST_SYS_JTAG = 9, ///< Select SYS_JTAG as clock destination + CLK_DEST_SYS_VREG_AND_CHIP_RESET = 10, ///< Select SYS_VREG_AND_CHIP_RESET as clock destination + CLK_DEST_SYS_PADS = 11, ///< Select SYS_PADS as clock destination + CLK_DEST_SYS_PIO0 = 12, ///< Select SYS_PIO0 as clock destination + CLK_DEST_SYS_PIO1 = 13, ///< Select SYS_PIO1 as clock destination + CLK_DEST_SYS_PLL_SYS = 14, ///< Select SYS_PLL_SYS as clock destination + CLK_DEST_SYS_PLL_USB = 15, ///< Select SYS_PLL_USB as clock destination + CLK_DEST_SYS_PSM = 16, ///< Select SYS_PSM as clock destination + CLK_DEST_SYS_PWM = 17, ///< Select SYS_PWM as clock destination + CLK_DEST_SYS_RESETS = 18, ///< Select SYS_RESETS as clock destination + CLK_DEST_SYS_ROM = 19, ///< Select SYS_ROM as clock destination + CLK_DEST_SYS_ROSC = 20, ///< Select SYS_ROSC as clock destination + CLK_DEST_RTC_RTC = 21, ///< Select RTC_RTC as clock destination + CLK_DEST_SYS_RTC = 22, ///< Select SYS_RTC as clock destination + CLK_DEST_SYS_SIO = 23, ///< Select SYS_SIO as clock destination + CLK_DEST_PERI_SPI0 = 24, ///< Select PERI_SPI0 as clock destination + CLK_DEST_SYS_SPI0 = 25, ///< Select SYS_SPI0 as clock destination + CLK_DEST_PERI_SPI1 = 26, ///< Select PERI_SPI1 as clock destination + CLK_DEST_SYS_SPI1 = 27, ///< Select SYS_SPI1 as clock destination + CLK_DEST_SYS_SRAM0 = 28, ///< Select SYS_SRAM0 as clock destination + CLK_DEST_SYS_SRAM1 = 29, ///< Select SYS_SRAM1 as clock destination + CLK_DEST_SYS_SRAM2 = 30, ///< Select SYS_SRAM2 as clock destination + CLK_DEST_SYS_SRAM3 = 31, ///< Select SYS_SRAM3 as clock destination + CLK_DEST_SYS_SRAM4 = 32, ///< Select SYS_SRAM4 as clock destination + CLK_DEST_SYS_SRAM5 = 33, ///< Select SYS_SRAM5 as clock destination + CLK_DEST_SYS_SYSCFG = 34, ///< Select SYS_SYSCFG as clock destination + CLK_DEST_SYS_SYSINFO = 35, ///< Select SYS_SYSINFO as clock destination + CLK_DEST_SYS_TBMAN = 36, ///< Select SYS_TBMAN as clock destination + CLK_DEST_SYS_TIMER = 37, ///< Select SYS_TIMER as clock destination + CLK_DEST_PERI_UART0 = 38, ///< Select PERI_UART0 as clock destination + CLK_DEST_SYS_UART0 = 39, ///< Select SYS_UART0 as clock destination + CLK_DEST_PERI_UART1 = 40, ///< Select PERI_UART1 as clock destination + CLK_DEST_SYS_UART1 = 41, ///< Select SYS_UART1 as clock destination + CLK_DEST_SYS_USBCTRL = 42, ///< Select SYS_USBCTRL as clock destination + CLK_DEST_USB_USBCTRL = 43, ///< Select USB_USBCTRL as clock destination + CLK_DEST_SYS_WATCHDOG = 44, ///< Select SYS_WATCHDOG as clock destination + CLK_DEST_SYS_XIP = 45, ///< Select SYS_XIP as clock destination + CLK_DEST_SYS_XOSC = 46, ///< Select SYS_XOSC as clock destination + NUM_CLOCK_DESTINATIONS +} clock_dest_num_t; + /// \tag::clock_hw[] typedef struct { _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL // Clock control, can be changed on-the-fly (except for auxsrc) - // 0x00100000 [20] : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock - // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock - // 0x00001000 [12] : DC50 (0): Enables duty cycle correction for odd divisors - // 0x00000800 [11] : ENABLE (0): Starts and stops the clock generator cleanly - // 0x00000400 [10] : KILL (0): Asynchronously kills the clock generator - // 0x000001e0 [8:5] : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching + // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by... + // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the... + // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors + // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly + // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator + // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching io_rw_32 ctrl; - + _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV // Clock divisor, can be changed on-the-fly - // 0xffffff00 [31:8] : INT (1): Integer component of the divisor, 0 -> divide by 2^16 - // 0x000000ff [7:0] : FRAC (0): Fractional component of the divisor + // 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16 + // 0x000000ff [7:0] FRAC (0x00) Fractional component of the divisor io_rw_32 div; - + _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED // Indicates which SRC is currently selected by the glitchless mux (one-hot) + // 0xffffffff [31:0] CLK_GPOUT0_SELECTED (0x00000001) This slice does not have a glitchless mux (only the... io_ro_32 selected; } clock_hw_t; /// \end::clock_hw[] typedef struct { _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL - // 0x00010000 [16] : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected - // 0x00001000 [12] : FRCE (0): Force a resus, for test purposes only - // 0x00000100 [8] : ENABLE (0): Enable resus - // 0x000000ff [7:0] : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles + // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it... + // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only + // 0x00000100 [8] ENABLE (0) Enable resus + // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles + io_rw_32 ctrl; - + _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS - // 0x00000001 [0] : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1 + // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send... io_ro_32 status; } clock_resus_hw_t; typedef struct { _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ // Reference clock frequency in kHz - // 0x000fffff [19:0] : FC0_REF_KHZ (0) + // 0x000fffff [19:0] FC0_REF_KHZ (0x00000) io_rw_32 ref_khz; - + _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ // Minimum pass frequency in kHz - // 0x01ffffff [24:0] : FC0_MIN_KHZ (0) + // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000) io_rw_32 min_khz; - + _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ // Maximum pass frequency in kHz - // 0x01ffffff [24:0] : FC0_MAX_KHZ (0x1ffffff) + // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff) io_rw_32 max_khz; - + _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY - // Delays the start of frequency counting to allow the mux to settle - // 0x00000007 [2:0] : FC0_DELAY (1) + // Delays the start of frequency counting to allow the mux to settle + + // 0x00000007 [2:0] FC0_DELAY (0x1) io_rw_32 delay; - + _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL // The test interval is 0 - // 0x0000000f [3:0] : FC0_INTERVAL (0x8) + // 0x0000000f [3:0] FC0_INTERVAL (0x8) io_rw_32 interval; - + _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC - // Clock sent to frequency counter, set to 0 when not required - // 0x000000ff [7:0] : FC0_SRC (0) + // Clock sent to frequency counter, set to 0 when not required + + // 0x000000ff [7:0] FC0_SRC (0x00) io_rw_32 src; - + _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS // Frequency counter status - // 0x10000000 [28] : DIED (0): Test clock stopped during test - // 0x01000000 [24] : FAST (0): Test clock faster than expected, only valid when status_done=1 - // 0x00100000 [20] : SLOW (0): Test clock slower than expected, only valid when status_done=1 - // 0x00010000 [16] : FAIL (0): Test failed - // 0x00001000 [12] : WAITING (0): Waiting for test clock to start - // 0x00000100 [8] : RUNNING (0): Test running - // 0x00000010 [4] : DONE (0): Test complete - // 0x00000001 [0] : PASS (0): Test passed + // 0x10000000 [28] DIED (0) Test clock stopped during test + // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1 + // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1 + // 0x00010000 [16] FAIL (0) Test failed + // 0x00001000 [12] WAITING (0) Waiting for test clock to start + // 0x00000100 [8] RUNNING (0) Test running + // 0x00000010 [4] DONE (0) Test complete + // 0x00000001 [0] PASS (0) Test passed io_ro_32 status; - + _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT // Result of frequency measurement, only valid when status_done=1 - // 0x3fffffe0 [29:5] : KHZ (0) - // 0x0000001f [4:0] : FRAC (0) + // 0x3fffffe0 [29:5] KHZ (0x0000000) + // 0x0000001f [4:0] FRAC (0x00) io_ro_32 result; } fc_hw_t; typedef struct { - clock_hw_t clk[CLK_COUNT]; // 10 - + clock_hw_t clk[10]; + clock_resus_hw_t resus; - + fc_hw_t fc0; - - _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 - // enable clock in wake mode - // 0x80000000 [31] : clk_sys_sram3 (1) - // 0x40000000 [30] : clk_sys_sram2 (1) - // 0x20000000 [29] : clk_sys_sram1 (1) - // 0x10000000 [28] : clk_sys_sram0 (1) - // 0x08000000 [27] : clk_sys_spi1 (1) - // 0x04000000 [26] : clk_peri_spi1 (1) - // 0x02000000 [25] : clk_sys_spi0 (1) - // 0x01000000 [24] : clk_peri_spi0 (1) - // 0x00800000 [23] : clk_sys_sio (1) - // 0x00400000 [22] : clk_sys_rtc (1) - // 0x00200000 [21] : clk_rtc_rtc (1) - // 0x00100000 [20] : clk_sys_rosc (1) - // 0x00080000 [19] : clk_sys_rom (1) - // 0x00040000 [18] : clk_sys_resets (1) - // 0x00020000 [17] : clk_sys_pwm (1) - // 0x00010000 [16] : clk_sys_psm (1) - // 0x00008000 [15] : clk_sys_pll_usb (1) - // 0x00004000 [14] : clk_sys_pll_sys (1) - // 0x00002000 [13] : clk_sys_pio1 (1) - // 0x00001000 [12] : clk_sys_pio0 (1) - // 0x00000800 [11] : clk_sys_pads (1) - // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1) - // 0x00000200 [9] : clk_sys_jtag (1) - // 0x00000100 [8] : clk_sys_io (1) - // 0x00000080 [7] : clk_sys_i2c1 (1) - // 0x00000040 [6] : clk_sys_i2c0 (1) - // 0x00000020 [5] : clk_sys_dma (1) - // 0x00000010 [4] : clk_sys_busfabric (1) - // 0x00000008 [3] : clk_sys_busctrl (1) - // 0x00000004 [2] : clk_sys_adc (1) - // 0x00000002 [1] : clk_adc_adc (1) - // 0x00000001 [0] : clk_sys_clocks (1) - io_rw_32 wake_en0; - - _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 - // enable clock in wake mode - // 0x00004000 [14] : clk_sys_xosc (1) - // 0x00002000 [13] : clk_sys_xip (1) - // 0x00001000 [12] : clk_sys_watchdog (1) - // 0x00000800 [11] : clk_usb_usbctrl (1) - // 0x00000400 [10] : clk_sys_usbctrl (1) - // 0x00000200 [9] : clk_sys_uart1 (1) - // 0x00000100 [8] : clk_peri_uart1 (1) - // 0x00000080 [7] : clk_sys_uart0 (1) - // 0x00000040 [6] : clk_peri_uart0 (1) - // 0x00000020 [5] : clk_sys_timer (1) - // 0x00000010 [4] : clk_sys_tbman (1) - // 0x00000008 [3] : clk_sys_sysinfo (1) - // 0x00000004 [2] : clk_sys_syscfg (1) - // 0x00000002 [1] : clk_sys_sram5 (1) - // 0x00000001 [0] : clk_sys_sram4 (1) - io_rw_32 wake_en1; - - _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 - // enable clock in sleep mode - // 0x80000000 [31] : clk_sys_sram3 (1) - // 0x40000000 [30] : clk_sys_sram2 (1) - // 0x20000000 [29] : clk_sys_sram1 (1) - // 0x10000000 [28] : clk_sys_sram0 (1) - // 0x08000000 [27] : clk_sys_spi1 (1) - // 0x04000000 [26] : clk_peri_spi1 (1) - // 0x02000000 [25] : clk_sys_spi0 (1) - // 0x01000000 [24] : clk_peri_spi0 (1) - // 0x00800000 [23] : clk_sys_sio (1) - // 0x00400000 [22] : clk_sys_rtc (1) - // 0x00200000 [21] : clk_rtc_rtc (1) - // 0x00100000 [20] : clk_sys_rosc (1) - // 0x00080000 [19] : clk_sys_rom (1) - // 0x00040000 [18] : clk_sys_resets (1) - // 0x00020000 [17] : clk_sys_pwm (1) - // 0x00010000 [16] : clk_sys_psm (1) - // 0x00008000 [15] : clk_sys_pll_usb (1) - // 0x00004000 [14] : clk_sys_pll_sys (1) - // 0x00002000 [13] : clk_sys_pio1 (1) - // 0x00001000 [12] : clk_sys_pio0 (1) - // 0x00000800 [11] : clk_sys_pads (1) - // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1) - // 0x00000200 [9] : clk_sys_jtag (1) - // 0x00000100 [8] : clk_sys_io (1) - // 0x00000080 [7] : clk_sys_i2c1 (1) - // 0x00000040 [6] : clk_sys_i2c0 (1) - // 0x00000020 [5] : clk_sys_dma (1) - // 0x00000010 [4] : clk_sys_busfabric (1) - // 0x00000008 [3] : clk_sys_busctrl (1) - // 0x00000004 [2] : clk_sys_adc (1) - // 0x00000002 [1] : clk_adc_adc (1) - // 0x00000001 [0] : clk_sys_clocks (1) - io_rw_32 sleep_en0; - - _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 - // enable clock in sleep mode - // 0x00004000 [14] : clk_sys_xosc (1) - // 0x00002000 [13] : clk_sys_xip (1) - // 0x00001000 [12] : clk_sys_watchdog (1) - // 0x00000800 [11] : clk_usb_usbctrl (1) - // 0x00000400 [10] : clk_sys_usbctrl (1) - // 0x00000200 [9] : clk_sys_uart1 (1) - // 0x00000100 [8] : clk_peri_uart1 (1) - // 0x00000080 [7] : clk_sys_uart0 (1) - // 0x00000040 [6] : clk_peri_uart0 (1) - // 0x00000020 [5] : clk_sys_timer (1) - // 0x00000010 [4] : clk_sys_tbman (1) - // 0x00000008 [3] : clk_sys_sysinfo (1) - // 0x00000004 [2] : clk_sys_syscfg (1) - // 0x00000002 [1] : clk_sys_sram5 (1) - // 0x00000001 [0] : clk_sys_sram4 (1) - io_rw_32 sleep_en1; - - _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 - // indicates the state of the clock enable - // 0x80000000 [31] : clk_sys_sram3 (0) - // 0x40000000 [30] : clk_sys_sram2 (0) - // 0x20000000 [29] : clk_sys_sram1 (0) - // 0x10000000 [28] : clk_sys_sram0 (0) - // 0x08000000 [27] : clk_sys_spi1 (0) - // 0x04000000 [26] : clk_peri_spi1 (0) - // 0x02000000 [25] : clk_sys_spi0 (0) - // 0x01000000 [24] : clk_peri_spi0 (0) - // 0x00800000 [23] : clk_sys_sio (0) - // 0x00400000 [22] : clk_sys_rtc (0) - // 0x00200000 [21] : clk_rtc_rtc (0) - // 0x00100000 [20] : clk_sys_rosc (0) - // 0x00080000 [19] : clk_sys_rom (0) - // 0x00040000 [18] : clk_sys_resets (0) - // 0x00020000 [17] : clk_sys_pwm (0) - // 0x00010000 [16] : clk_sys_psm (0) - // 0x00008000 [15] : clk_sys_pll_usb (0) - // 0x00004000 [14] : clk_sys_pll_sys (0) - // 0x00002000 [13] : clk_sys_pio1 (0) - // 0x00001000 [12] : clk_sys_pio0 (0) - // 0x00000800 [11] : clk_sys_pads (0) - // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (0) - // 0x00000200 [9] : clk_sys_jtag (0) - // 0x00000100 [8] : clk_sys_io (0) - // 0x00000080 [7] : clk_sys_i2c1 (0) - // 0x00000040 [6] : clk_sys_i2c0 (0) - // 0x00000020 [5] : clk_sys_dma (0) - // 0x00000010 [4] : clk_sys_busfabric (0) - // 0x00000008 [3] : clk_sys_busctrl (0) - // 0x00000004 [2] : clk_sys_adc (0) - // 0x00000002 [1] : clk_adc_adc (0) - // 0x00000001 [0] : clk_sys_clocks (0) - io_ro_32 enabled0; - - _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 - // indicates the state of the clock enable - // 0x00004000 [14] : clk_sys_xosc (0) - // 0x00002000 [13] : clk_sys_xip (0) - // 0x00001000 [12] : clk_sys_watchdog (0) - // 0x00000800 [11] : clk_usb_usbctrl (0) - // 0x00000400 [10] : clk_sys_usbctrl (0) - // 0x00000200 [9] : clk_sys_uart1 (0) - // 0x00000100 [8] : clk_peri_uart1 (0) - // 0x00000080 [7] : clk_sys_uart0 (0) - // 0x00000040 [6] : clk_peri_uart0 (0) - // 0x00000020 [5] : clk_sys_timer (0) - // 0x00000010 [4] : clk_sys_tbman (0) - // 0x00000008 [3] : clk_sys_sysinfo (0) - // 0x00000004 [2] : clk_sys_syscfg (0) - // 0x00000002 [1] : clk_sys_sram5 (0) - // 0x00000001 [0] : clk_sys_sram4 (0) - io_ro_32 enabled1; - + + union { + struct { + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIOB (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_POWER (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_LDO_POR (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC0 (1) + // 0x00000002 [1] CLK_ADC_ADC0 (1) + // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1) + io_rw_32 wake_en0; + + _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 + // enable clock in wake mode + // 0x00004000 [14] CLK_SYS_XOSC (1) + // 0x00002000 [13] CLK_SYS_XIP (1) + // 0x00001000 [12] CLK_SYS_WATCHDOG (1) + // 0x00000800 [11] CLK_USB_USBCTRL (1) + // 0x00000400 [10] CLK_SYS_USBCTRL (1) + // 0x00000200 [9] CLK_SYS_UART1 (1) + // 0x00000100 [8] CLK_PERI_UART1 (1) + // 0x00000080 [7] CLK_SYS_UART0 (1) + // 0x00000040 [6] CLK_PERI_UART0 (1) + // 0x00000020 [5] CLK_SYS_TIMER (1) + // 0x00000010 [4] CLK_SYS_TBMAN (1) + // 0x00000008 [3] CLK_SYS_SYSINFO (1) + // 0x00000004 [2] CLK_SYS_SYSCFG (1) + // 0x00000002 [1] CLK_SYS_SRAM5 (1) + // 0x00000001 [0] CLK_SYS_SRAM4 (1) + io_rw_32 wake_en1; + }; + // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIO (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_PSM (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC (1) + // 0x00000002 [1] CLK_ADC_ADC (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIOB (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_POWER (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_LDO_POR (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC0 (1) + // 0x00000002 [1] CLK_ADC_ADC0 (1) + // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1) + io_rw_32 sleep_en0; + + _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 + // enable clock in sleep mode + // 0x00004000 [14] CLK_SYS_XOSC (1) + // 0x00002000 [13] CLK_SYS_XIP (1) + // 0x00001000 [12] CLK_SYS_WATCHDOG (1) + // 0x00000800 [11] CLK_USB_USBCTRL (1) + // 0x00000400 [10] CLK_SYS_USBCTRL (1) + // 0x00000200 [9] CLK_SYS_UART1 (1) + // 0x00000100 [8] CLK_PERI_UART1 (1) + // 0x00000080 [7] CLK_SYS_UART0 (1) + // 0x00000040 [6] CLK_PERI_UART0 (1) + // 0x00000020 [5] CLK_SYS_TIMER (1) + // 0x00000010 [4] CLK_SYS_TBMAN (1) + // 0x00000008 [3] CLK_SYS_SYSINFO (1) + // 0x00000004 [2] CLK_SYS_SYSCFG (1) + // 0x00000002 [1] CLK_SYS_SRAM5 (1) + // 0x00000001 [0] CLK_SYS_SRAM4 (1) + io_rw_32 sleep_en1; + }; + // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIO (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_PSM (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC (1) + // 0x00000002 [1] CLK_ADC_ADC (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SRAM3 (0) + // 0x40000000 [30] CLK_SYS_SRAM2 (0) + // 0x20000000 [29] CLK_SYS_SRAM1 (0) + // 0x10000000 [28] CLK_SYS_SRAM0 (0) + // 0x08000000 [27] CLK_SYS_SPI1 (0) + // 0x04000000 [26] CLK_PERI_SPI1 (0) + // 0x02000000 [25] CLK_SYS_SPI0 (0) + // 0x01000000 [24] CLK_PERI_SPI0 (0) + // 0x00800000 [23] CLK_SYS_SIOB (0) + // 0x00400000 [22] CLK_SYS_RTC (0) + // 0x00200000 [21] CLK_RTC_RTC (0) + // 0x00100000 [20] CLK_SYS_ROSC (0) + // 0x00080000 [19] CLK_SYS_ROM (0) + // 0x00040000 [18] CLK_SYS_RESETS (0) + // 0x00020000 [17] CLK_SYS_PWM (0) + // 0x00010000 [16] CLK_SYS_POWER (0) + // 0x00008000 [15] CLK_SYS_PLL_USB (0) + // 0x00004000 [14] CLK_SYS_PLL_SYS (0) + // 0x00002000 [13] CLK_SYS_PIO1 (0) + // 0x00001000 [12] CLK_SYS_PIO0 (0) + // 0x00000800 [11] CLK_SYS_PADS (0) + // 0x00000400 [10] CLK_SYS_LDO_POR (0) + // 0x00000200 [9] CLK_SYS_JTAG (0) + // 0x00000100 [8] CLK_SYS_IO (0) + // 0x00000080 [7] CLK_SYS_I2C1 (0) + // 0x00000040 [6] CLK_SYS_I2C0 (0) + // 0x00000020 [5] CLK_SYS_DMA (0) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (0) + // 0x00000008 [3] CLK_SYS_BUSCTRL (0) + // 0x00000004 [2] CLK_SYS_ADC0 (0) + // 0x00000002 [1] CLK_ADC_ADC0 (0) + // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (0) + io_ro_32 enabled0; + + _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 + // indicates the state of the clock enable + // 0x00004000 [14] CLK_SYS_XOSC (0) + // 0x00002000 [13] CLK_SYS_XIP (0) + // 0x00001000 [12] CLK_SYS_WATCHDOG (0) + // 0x00000800 [11] CLK_USB_USBCTRL (0) + // 0x00000400 [10] CLK_SYS_USBCTRL (0) + // 0x00000200 [9] CLK_SYS_UART1 (0) + // 0x00000100 [8] CLK_PERI_UART1 (0) + // 0x00000080 [7] CLK_SYS_UART0 (0) + // 0x00000040 [6] CLK_PERI_UART0 (0) + // 0x00000020 [5] CLK_SYS_TIMER (0) + // 0x00000010 [4] CLK_SYS_TBMAN (0) + // 0x00000008 [3] CLK_SYS_SYSINFO (0) + // 0x00000004 [2] CLK_SYS_SYSCFG (0) + // 0x00000002 [1] CLK_SYS_SRAM5 (0) + // 0x00000001 [0] CLK_SYS_SRAM4 (0) + io_ro_32 enabled1; + }; + // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes) + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SRAM3 (0) + // 0x40000000 [30] CLK_SYS_SRAM2 (0) + // 0x20000000 [29] CLK_SYS_SRAM1 (0) + // 0x10000000 [28] CLK_SYS_SRAM0 (0) + // 0x08000000 [27] CLK_SYS_SPI1 (0) + // 0x04000000 [26] CLK_PERI_SPI1 (0) + // 0x02000000 [25] CLK_SYS_SPI0 (0) + // 0x01000000 [24] CLK_PERI_SPI0 (0) + // 0x00800000 [23] CLK_SYS_SIO (0) + // 0x00400000 [22] CLK_SYS_RTC (0) + // 0x00200000 [21] CLK_RTC_RTC (0) + // 0x00100000 [20] CLK_SYS_ROSC (0) + // 0x00080000 [19] CLK_SYS_ROM (0) + // 0x00040000 [18] CLK_SYS_RESETS (0) + // 0x00020000 [17] CLK_SYS_PWM (0) + // 0x00010000 [16] CLK_SYS_PSM (0) + // 0x00008000 [15] CLK_SYS_PLL_USB (0) + // 0x00004000 [14] CLK_SYS_PLL_SYS (0) + // 0x00002000 [13] CLK_SYS_PIO1 (0) + // 0x00001000 [12] CLK_SYS_PIO0 (0) + // 0x00000800 [11] CLK_SYS_PADS (0) + // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (0) + // 0x00000200 [9] CLK_SYS_JTAG (0) + // 0x00000100 [8] CLK_SYS_IO (0) + // 0x00000080 [7] CLK_SYS_I2C1 (0) + // 0x00000040 [6] CLK_SYS_I2C0 (0) + // 0x00000020 [5] CLK_SYS_DMA (0) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (0) + // 0x00000008 [3] CLK_SYS_BUSCTRL (0) + // 0x00000004 [2] CLK_SYS_ADC (0) + // 0x00000002 [1] CLK_ADC_ADC (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled[2]; + }; + _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR // Raw Interrupts - // 0x00000001 [0] : CLK_SYS_RESUS (0) + // 0x00000001 [0] CLK_SYS_RESUS (0) io_ro_32 intr; - + _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE // Interrupt Enable - // 0x00000001 [0] : CLK_SYS_RESUS (0) + // 0x00000001 [0] CLK_SYS_RESUS (0) io_rw_32 inte; - + _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF // Interrupt Force - // 0x00000001 [0] : CLK_SYS_RESUS (0) + // 0x00000001 [0] CLK_SYS_RESUS (0) io_rw_32 intf; - + _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS // Interrupt status after masking & forcing - // 0x00000001 [0] : CLK_SYS_RESUS (0) + // 0x00000001 [0] CLK_SYS_RESUS (0) io_ro_32 ints; } clocks_hw_t; #define clocks_hw ((clocks_hw_t *)CLOCKS_BASE) +static_assert(sizeof (clocks_hw_t) == 0x00c8, ""); -static_assert( CLK_COUNT == 10, ""); +#endif // _HARDWARE_STRUCTS_CLOCKS_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/dma.h b/src/rp2040/hardware_structs/include/hardware/structs/dma.h index b5cac77d8..bc83060f7 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/dma.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/dma.h @@ -1,16 +1,20 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_DMA_H #define _HARDWARE_STRUCTS_DMA_H +/** + * \file rp2040/dma.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/dma.h" +#include "hardware/structs/dma_debug.h" // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma // @@ -18,186 +22,218 @@ // _REG_(x) will link to the corresponding register in hardware/regs/dma.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR // DMA Channel 0 Read Address pointer + // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes io_rw_32 read_addr; - + _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR // DMA Channel 0 Write Address pointer + // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes io_rw_32 write_addr; - + _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT // DMA Channel 0 Transfer Count + // 0xffffffff [31:0] CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will... io_rw_32 transfer_count; - + _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG // DMA Channel 0 Control and Status - // 0x80000000 [31] : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags - // 0x40000000 [30] : READ_ERROR (0): If 1, the channel received a read bus error - // 0x20000000 [29] : WRITE_ERROR (0): If 1, the channel received a write bus error - // 0x01000000 [24] : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the... - // 0x00800000 [23] : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each... - // 0x00400000 [22] : BSWAP (0): Apply byte-swap transformation to DMA data - // 0x00200000 [21] : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block - // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal - // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO - // 0x00000400 [10] : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses - // 0x000003c0 [9:6] : RING_SIZE (0): Size of address wrap region - // 0x00000020 [5] : INCR_WRITE (0): If 1, the write address increments with each transfer - // 0x00000010 [4] : INCR_READ (0): If 1, the read address increments with each transfer - // 0x0000000c [3:2] : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word) - // 0x00000002 [1] : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in... - // 0x00000001 [0] : EN (0): DMA Channel Enable + // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags + // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error + // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error + // 0x01000000 [24] BUSY (0) This flag goes high when the channel starts a new... + // 0x00800000 [23] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... + // 0x00400000 [22] BSWAP (0) Apply byte-swap transformation to DMA data + // 0x00200000 [21] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... + // 0x001f8000 [20:15] TREQ_SEL (0x00) Select a Transfer Request signal + // 0x00007800 [14:11] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... + // 0x00000400 [10] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses + // 0x000003c0 [9:6] RING_SIZE (0x0) Size of address wrap region + // 0x00000020 [5] INCR_WRITE (0) If 1, the write address increments with each transfer + // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer + // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) + // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... + // 0x00000001 [0] EN (0) DMA Channel Enable io_rw_32 ctrl_trig; - + _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL1_CTRL (-) io_rw_32 al1_ctrl; - + _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) io_rw_32 al1_read_addr; - + _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) io_rw_32 al1_write_addr; - + _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG - // Alias for channel 0 TRANS_COUNT register + // Alias for channel 0 TRANS_COUNT register + + // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) io_rw_32 al1_transfer_count_trig; - + _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL2_CTRL (-) io_rw_32 al2_ctrl; - + _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) io_rw_32 al2_transfer_count; - + _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) io_rw_32 al2_read_addr; - + _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG - // Alias for channel 0 WRITE_ADDR register + // Alias for channel 0 WRITE_ADDR register + + // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) io_rw_32 al2_write_addr_trig; - + _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL3_CTRL (-) io_rw_32 al3_ctrl; - + _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) io_rw_32 al3_write_addr; - + _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) io_rw_32 al3_transfer_count; - + _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG - // Alias for channel 0 READ_ADDR register + // Alias for channel 0 READ_ADDR register + + // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) io_rw_32 al3_read_addr_trig; } dma_channel_hw_t; typedef struct { - dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12 - - uint32_t _pad0[64]; - _REG_(DMA_INTR_OFFSET) // DMA_INTR // Interrupt Status (raw) - // 0x0000ffff [15:0] : INTR (0): Raw interrupt status for DMA Channels 0 + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 io_rw_32 intr; - + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 // Interrupt Enables for IRQ 0 - // 0x0000ffff [15:0] : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0 - io_rw_32 inte0; - + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte; + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 // Force Interrupts - // 0x0000ffff [15:0] : INTF0 (0): Write 1s to force the corresponding bits in INTE0 - io_rw_32 intf0; - + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 + io_rw_32 intf; + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 // Interrupt Status for IRQ 0 - // 0x0000ffff [15:0] : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted - io_rw_32 ints0; - - uint32_t _pad1; + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints; +} dma_irq_ctrl_hw_t; - _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 - // Interrupt Enables for IRQ 1 - // 0x0000ffff [15:0] : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1 - io_rw_32 inte1; - - _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 - // Force Interrupts for IRQ 1 - // 0x0000ffff [15:0] : INTF1 (0): Write 1s to force the corresponding bits in INTE0 - io_rw_32 intf1; - - _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 - // Interrupt Status (masked) for IRQ 1 - // 0x0000ffff [15:0] : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted - io_rw_32 ints1; - - _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 +typedef struct { + dma_channel_hw_t ch[12]; + + uint32_t _pad0[64]; + + union { + struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte0; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 + io_rw_32 intf0; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints0; + + uint32_t __pad0; + + _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 + // Interrupt Enables for IRQ 1 + // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 + io_rw_32 inte1; + + _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 + // Force Interrupts for IRQ 1 + // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 + io_rw_32 intf1; + + _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 + // Interrupt Status (masked) for IRQ 1 + // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints1; + }; + dma_irq_ctrl_hw_t irq_ctrl[2]; + }; + // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) - // - // Pacing (X/Y) Fractional Timer - // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend - // 0x0000ffff [15:0] : Y (0): Pacing Timer Divisor - io_rw_32 timer[NUM_DMA_TIMERS]; // 4 - + _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 + // Pacing (X/Y) Fractional Timer + + // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend + // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor + io_rw_32 timer[4]; + _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER // Trigger one or more channels simultaneously - // 0x0000ffff [15:0] : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel - io_rw_32 multi_channel_trigger; - + // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel + io_wo_32 multi_channel_trigger; + _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL // Sniffer Control - // 0x00000800 [11] : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read - // 0x00000400 [10] : OUT_REV (0): If set, the result appears bit-reversed when read - // 0x00000200 [9] : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum - // 0x000001e0 [8:5] : CALC (0) - // 0x0000001e [4:1] : DMACH (0): DMA channel for Sniffer to observe - // 0x00000001 [0] : EN (0): Enable sniffer + // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... + // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read + // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... + // 0x000001e0 [8:5] CALC (0x0) + // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe + // 0x00000001 [0] EN (0) Enable sniffer io_rw_32 sniff_ctrl; - + _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA // Data accumulator for sniff hardware + // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... io_rw_32 sniff_data; - - uint32_t _pad2; - + + uint32_t _pad1; + _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS // Debug RAF, WAF, TDF levels - // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level - // 0x0000ff00 [15:8] : WAF_LVL (0): Current Write-Address-FIFO fill level - // 0x000000ff [7:0] : TDF_LVL (0): Current Transfer-Data-FIFO fill level + // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level + // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level + // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level io_ro_32 fifo_levels; - + _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT // Abort an in-progress transfer sequence on one or more channels - // 0x0000ffff [15:0] : CHAN_ABORT (0): Each bit corresponds to a channel - io_rw_32 abort; + // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel + io_wo_32 abort; } dma_hw_t; -typedef struct { - struct dma_debug_hw_channel { - io_rw_32 ctrdeq; - io_ro_32 tcr; - uint32_t pad[14]; - } ch[NUM_DMA_CHANNELS]; -} dma_debug_hw_t; - #define dma_hw ((dma_hw_t *)DMA_BASE) -#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) +static_assert(sizeof (dma_hw_t) == 0x0448, ""); -static_assert( NUM_DMA_TIMERS == 4, ""); -static_assert( NUM_DMA_CHANNELS == 12, ""); +#endif // _HARDWARE_STRUCTS_DMA_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/dma_debug.h b/src/rp2040/hardware_structs/include/hardware/structs/dma_debug.h new file mode 100644 index 000000000..239b8cae8 --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/dma_debug.h @@ -0,0 +1,47 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H +#define _HARDWARE_STRUCTS_DMA_DEBUG_H + +/** + * \file rp2040/dma_debug.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ + // Read: get channel DREQ counter (i + // 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00) + io_rw_32 dbg_ctdreq; + + _REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR + // Read to get channel TRANS_COUNT reload value, i + // 0xffffffff [31:0] CH0_DBG_TCR (0x00000000) + io_ro_32 dbg_tcr; + + uint32_t _pad0[14]; +} dma_debug_channel_hw_t; + +typedef struct { + dma_debug_channel_hw_t ch[12]; +} dma_debug_hw_t; + +#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/i2c.h b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h index 397ad9ac2..2ff099799 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/i2c.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/i2c.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_I2C_H #define _HARDWARE_STRUCTS_I2C_H +/** + * \file rp2040/i2c.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/i2c.h" @@ -18,316 +21,318 @@ // _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON // I2C Control Register - // 0x00000400 [10] : STOP_DET_IF_MASTER_ACTIVE (0): Master issues the STOP_DET interrupt irrespective of whether... - // 0x00000200 [9] : RX_FIFO_FULL_HLD_CTRL (0): This bit controls whether DW_apb_i2c should hold the bus when the Rx... - // 0x00000100 [8] : TX_EMPTY_CTRL (0): This bit controls the generation of the TX_EMPTY interrupt, as described in... - // 0x00000080 [7] : STOP_DET_IFADDRESSED (0): In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is... - // 0x00000040 [6] : IC_SLAVE_DISABLE (1): This bit controls whether I2C has its slave disabled, which means once... - // 0x00000020 [5] : IC_RESTART_EN (1): Determines whether RESTART conditions may be sent when acting as a master - // 0x00000010 [4] : IC_10BITADDR_MASTER (0): Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit... - // 0x00000008 [3] : IC_10BITADDR_SLAVE (0): When acting as a slave, this bit controls whether the DW_apb_i2c... - // 0x00000006 [2:1] : SPEED (0x2): These bits control at which speed the DW_apb_i2c operates; its setting is relevant... - // 0x00000001 [0] : MASTER_MODE (1): This bit controls whether the DW_apb_i2c master is enabled + // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... + // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... + // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... + // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... + // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... + // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... + // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... + // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... + // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... + // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled io_rw_32 con; - + _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR // I2C Target Address Register - // 0x00000800 [11] : SPECIAL (0): This bit indicates whether software performs a Device-ID or General Call or START... - // 0x00000400 [10] : GC_OR_START (0): If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this... - // 0x000003ff [9:0] : IC_TAR (0x55): This is the target address for any master transaction + // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... + // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... + // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction io_rw_32 tar; - + _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR // I2C Slave Address Register - // 0x000003ff [9:0] : IC_SAR (0x55): The IC_SAR holds the slave address when the I2C is operating as a slave + // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... io_rw_32 sar; - + uint32_t _pad0; - + _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD - // I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the... - // 0x00000800 [11] : FIRST_DATA_BYTE (0): Indicates the first data byte received after the address phase for receive... - // 0x00000400 [10] : RESTART (0): This bit controls whether a RESTART is issued before the byte is sent or received - // 0x00000200 [9] : STOP (0): This bit controls whether a STOP is issued after the byte is sent or received - // 0x00000100 [8] : CMD (0): This bit controls whether a read or a write is performed - // 0x000000ff [7:0] : DAT (0): This register contains the data to be transmitted or received on the I2C bus + // I2C Rx/Tx Data Buffer and Command Register + // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... + // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... + // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... + // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed + // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... io_rw_32 data_cmd; - + _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT // Standard Speed I2C Clock SCL High Count Register - // 0x0000ffff [15:0] : IC_SS_SCL_HCNT (0x28): This register must be set before any I2C bus transaction can take place... + // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... io_rw_32 ss_scl_hcnt; - + _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT // Standard Speed I2C Clock SCL Low Count Register - // 0x0000ffff [15:0] : IC_SS_SCL_LCNT (0x2f): This register must be set before any I2C bus transaction can take place... + // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... io_rw_32 ss_scl_lcnt; - + _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - // 0x0000ffff [15:0] : IC_FS_SCL_HCNT (0x6): This register must be set before any I2C bus transaction can take place... + // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... io_rw_32 fs_scl_hcnt; - + _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - // 0x0000ffff [15:0] : IC_FS_SCL_LCNT (0xd): This register must be set before any I2C bus transaction can take place... + // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... io_rw_32 fs_scl_lcnt; - + uint32_t _pad1[2]; - + _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT // I2C Interrupt Status Register - // 0x00001000 [12] : R_RESTART_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit - // 0x00000800 [11] : R_GEN_CALL (0): See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit - // 0x00000400 [10] : R_START_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit - // 0x00000200 [9] : R_STOP_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit - // 0x00000100 [8] : R_ACTIVITY (0): See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit - // 0x00000080 [7] : R_RX_DONE (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit - // 0x00000040 [6] : R_TX_ABRT (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit - // 0x00000020 [5] : R_RD_REQ (0): See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit - // 0x00000010 [4] : R_TX_EMPTY (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit - // 0x00000008 [3] : R_TX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit - // 0x00000004 [2] : R_RX_FULL (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit - // 0x00000002 [1] : R_RX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit - // 0x00000001 [0] : R_RX_UNDER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit + // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit + // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit + // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit + // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit + // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit + // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit + // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit + // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit + // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit + // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit + // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit io_ro_32 intr_stat; - + _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK // I2C Interrupt Mask Register - // 0x00001000 [12] : M_RESTART_DET (0): This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register - // 0x00000800 [11] : M_GEN_CALL (1): This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register - // 0x00000400 [10] : M_START_DET (0): This bit masks the R_START_DET interrupt in IC_INTR_STAT register - // 0x00000200 [9] : M_STOP_DET (0): This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register - // 0x00000100 [8] : M_ACTIVITY (0): This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register - // 0x00000080 [7] : M_RX_DONE (1): This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register - // 0x00000040 [6] : M_TX_ABRT (1): This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register - // 0x00000020 [5] : M_RD_REQ (1): This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register - // 0x00000010 [4] : M_TX_EMPTY (1): This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register - // 0x00000008 [3] : M_TX_OVER (1): This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register - // 0x00000004 [2] : M_RX_FULL (1): This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register - // 0x00000002 [1] : M_RX_OVER (1): This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register - // 0x00000001 [0] : M_RX_UNDER (1): This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register + // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... + // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register + // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register + // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register + // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register + // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register + // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register + // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register + // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register + // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register + // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register + // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register + // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register io_rw_32 intr_mask; - + _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT // I2C Raw Interrupt Status Register - // 0x00001000 [12] : RESTART_DET (0): Indicates whether a RESTART condition has occurred on the I2C interface when... - // 0x00000800 [11] : GEN_CALL (0): Set only when a General Call address is received and it is acknowledged - // 0x00000400 [10] : START_DET (0): Indicates whether a START or RESTART condition has occurred on the I2C interface... - // 0x00000200 [9] : STOP_DET (0): Indicates whether a STOP condition has occurred on the I2C interface regardless... - // 0x00000100 [8] : ACTIVITY (0): This bit captures DW_apb_i2c activity and stays set until it is cleared - // 0x00000080 [7] : RX_DONE (0): When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the... - // 0x00000040 [6] : TX_ABRT (0): This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the... - // 0x00000020 [5] : RD_REQ (0): This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is... - // 0x00000010 [4] : TX_EMPTY (0): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL... - // 0x00000008 [3] : TX_OVER (0): Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the... - // 0x00000004 [2] : RX_FULL (0): Set when the receive buffer reaches or goes above the RX_TL threshold in the... - // 0x00000002 [1] : RX_OVER (0): Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an... - // 0x00000001 [0] : RX_UNDER (0): Set if the processor attempts to read the receive buffer when it is empty by... + // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... + // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... + // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... + // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... + // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... + // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... + // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... + // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... + // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... + // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... + // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... + // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... + // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... io_ro_32 raw_intr_stat; - + _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL // I2C Receive FIFO Threshold Register - // 0x000000ff [7:0] : RX_TL (0): Receive FIFO Threshold Level + // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level io_rw_32 rx_tl; - + _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL // I2C Transmit FIFO Threshold Register - // 0x000000ff [7:0] : TX_TL (0): Transmit FIFO Threshold Level + // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level io_rw_32 tx_tl; - + _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR // Clear Combined and Individual Interrupt Register - // 0x00000001 [0] : CLR_INTR (0): Read this register to clear the combined interrupt, all individual interrupts,... + // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... io_ro_32 clr_intr; - + _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER // Clear RX_UNDER Interrupt Register - // 0x00000001 [0] : CLR_RX_UNDER (0): Read this register to clear the RX_UNDER interrupt (bit 0) of the... + // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... io_ro_32 clr_rx_under; - + _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER // Clear RX_OVER Interrupt Register - // 0x00000001 [0] : CLR_RX_OVER (0): Read this register to clear the RX_OVER interrupt (bit 1) of the... + // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... io_ro_32 clr_rx_over; - + _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER // Clear TX_OVER Interrupt Register - // 0x00000001 [0] : CLR_TX_OVER (0): Read this register to clear the TX_OVER interrupt (bit 3) of the... + // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... io_ro_32 clr_tx_over; - + _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ // Clear RD_REQ Interrupt Register - // 0x00000001 [0] : CLR_RD_REQ (0): Read this register to clear the RD_REQ interrupt (bit 5) of the... + // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... io_ro_32 clr_rd_req; - + _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT // Clear TX_ABRT Interrupt Register - // 0x00000001 [0] : CLR_TX_ABRT (0): Read this register to clear the TX_ABRT interrupt (bit 6) of the... + // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... io_ro_32 clr_tx_abrt; - + _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE // Clear RX_DONE Interrupt Register - // 0x00000001 [0] : CLR_RX_DONE (0): Read this register to clear the RX_DONE interrupt (bit 7) of the... + // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... io_ro_32 clr_rx_done; - + _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY // Clear ACTIVITY Interrupt Register - // 0x00000001 [0] : CLR_ACTIVITY (0): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore + // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... io_ro_32 clr_activity; - + _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET // Clear STOP_DET Interrupt Register - // 0x00000001 [0] : CLR_STOP_DET (0): Read this register to clear the STOP_DET interrupt (bit 9) of the... + // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... io_ro_32 clr_stop_det; - + _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET // Clear START_DET Interrupt Register - // 0x00000001 [0] : CLR_START_DET (0): Read this register to clear the START_DET interrupt (bit 10) of the... + // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... io_ro_32 clr_start_det; - + _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL // Clear GEN_CALL Interrupt Register - // 0x00000001 [0] : CLR_GEN_CALL (0): Read this register to clear the GEN_CALL interrupt (bit 11) of... + // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... io_ro_32 clr_gen_call; - + _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE - // I2C Enable Register - // 0x00000004 [2] : TX_CMD_BLOCK (0): In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx... - // 0x00000002 [1] : ABORT (0): When set, the controller initiates the transfer abort - // 0x00000001 [0] : ENABLE (0): Controls whether the DW_apb_i2c is enabled + // I2C ENABLE Register + // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... + // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort + // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled io_rw_32 enable; - + _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS - // I2C Status Register - // 0x00000040 [6] : SLV_ACTIVITY (0): Slave FSM Activity Status - // 0x00000020 [5] : MST_ACTIVITY (0): Master FSM Activity Status - // 0x00000010 [4] : RFF (0): Receive FIFO Completely Full - // 0x00000008 [3] : RFNE (0): Receive FIFO Not Empty - // 0x00000004 [2] : TFE (1): Transmit FIFO Completely Empty - // 0x00000002 [1] : TFNF (1): Transmit FIFO Not Full - // 0x00000001 [0] : ACTIVITY (0): I2C Activity Status + // I2C STATUS Register + // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status + // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status + // 0x00000010 [4] RFF (0) Receive FIFO Completely Full + // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty + // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty + // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full + // 0x00000001 [0] ACTIVITY (0) I2C Activity Status io_ro_32 status; - + _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR - // I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer - // 0x0000001f [4:0] : TXFLR (0): Transmit FIFO Level + // I2C Transmit FIFO Level Register + // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level io_ro_32 txflr; - + _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR - // I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer - // 0x0000001f [4:0] : RXFLR (0): Receive FIFO Level + // I2C Receive FIFO Level Register + // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level io_ro_32 rxflr; - + _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD // I2C SDA Hold Time Length Register - // 0x00ff0000 [23:16] : IC_SDA_RX_HOLD (0): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c... - // 0x0000ffff [15:0] : IC_SDA_TX_HOLD (1): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c... + // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... + // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... io_rw_32 sda_hold; - + _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE // I2C Transmit Abort Source Register - // 0xff800000 [31:23] : TX_FLUSH_CNT (0): This field indicates the number of Tx FIFO Data Commands which are flushed... - // 0x00010000 [16] : ABRT_USER_ABRT (0): This is a master-mode-only bit - // 0x00008000 [15] : ABRT_SLVRD_INTX (0): 1: When the processor side responds to a slave mode request for data to be... - // 0x00004000 [14] : ABRT_SLV_ARBLOST (0): This field indicates that a Slave has lost the bus while transmitting... - // 0x00002000 [13] : ABRT_SLVFLUSH_TXFIFO (0): This field specifies that the Slave has received a read command and... - // 0x00001000 [12] : ARB_LOST (0): This field specifies that the Master has lost arbitration, or if... - // 0x00000800 [11] : ABRT_MASTER_DIS (0): This field indicates that the User tries to initiate a Master operation... - // 0x00000400 [10] : ABRT_10B_RD_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit... - // 0x00000200 [9] : ABRT_SBYTE_NORSTRT (0): To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed... - // 0x00000100 [8] : ABRT_HS_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit... - // 0x00000080 [7] : ABRT_SBYTE_ACKDET (0): This field indicates that the Master has sent a START Byte and the START... - // 0x00000040 [6] : ABRT_HS_ACKDET (0): This field indicates that the Master is in High Speed mode and the High... - // 0x00000020 [5] : ABRT_GCALL_READ (0): This field indicates that DW_apb_i2c in the master mode has sent a General... - // 0x00000010 [4] : ABRT_GCALL_NOACK (0): This field indicates that DW_apb_i2c in master mode has sent a General... - // 0x00000008 [3] : ABRT_TXDATA_NOACK (0): This field indicates the master-mode only bit - // 0x00000004 [2] : ABRT_10ADDR2_NOACK (0): This field indicates that the Master is in 10-bit address mode and that... - // 0x00000002 [1] : ABRT_10ADDR1_NOACK (0): This field indicates that the Master is in 10-bit address mode and the... - // 0x00000001 [0] : ABRT_7B_ADDR_NOACK (0): This field indicates that the Master is in 7-bit addressing mode and... + // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... + // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit + // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... + // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... + // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... + // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... + // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... + // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... + // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... + // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... + // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... + // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... + // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit + // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... io_ro_32 tx_abrt_source; - + _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY // Generate Slave Data NACK Register - // 0x00000001 [0] : NACK (0): Generate NACK + // 0x00000001 [0] NACK (0) Generate NACK io_rw_32 slv_data_nack_only; - + _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR // DMA Control Register - // 0x00000002 [1] : TDMAE (0): Transmit DMA Enable - // 0x00000001 [0] : RDMAE (0): Receive DMA Enable + // 0x00000002 [1] TDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RDMAE (0) Receive DMA Enable io_rw_32 dma_cr; - + _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR // DMA Transmit Data Level Register - // 0x0000000f [3:0] : DMATDL (0): Transmit Data Level + // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level io_rw_32 dma_tdlr; - + _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR - // I2C Receive Data Level Register - // 0x0000000f [3:0] : DMARDL (0): Receive Data Level + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level io_rw_32 dma_rdlr; - + _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP // I2C SDA Setup Register - // 0x000000ff [7:0] : SDA_SETUP (0x64): SDA Setup + // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup io_rw_32 sda_setup; - + _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL // I2C ACK General Call Register - // 0x00000001 [0] : ACK_GEN_CALL (1): ACK General Call + // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call io_rw_32 ack_general_call; - + _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS // I2C Enable Status Register - // 0x00000004 [2] : SLV_RX_DATA_LOST (0): Slave Received Data Lost - // 0x00000002 [1] : SLV_DISABLED_WHILE_BUSY (0): Slave Disabled While Busy (Transmit, Receive) - // 0x00000001 [0] : IC_EN (0): ic_en Status + // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost + // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) + // 0x00000001 [0] IC_EN (0) ic_en Status io_ro_32 enable_status; - + _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN // I2C SS, FS or FM+ spike suppression limit - // 0x000000ff [7:0] : IC_FS_SPKLEN (0x7): This register must be set before any I2C bus transaction can take place to... + // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... io_rw_32 fs_spklen; - + uint32_t _pad2; - + _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET // Clear RESTART_DET Interrupt Register - // 0x00000001 [0] : CLR_RESTART_DET (0): Read this register to clear the RESTART_DET interrupt (bit 12) of... + // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... io_ro_32 clr_restart_det; - + uint32_t _pad3[18]; - + _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 // Component Parameter Register 1 - // 0x00ff0000 [23:16] : TX_BUFFER_DEPTH (0): TX Buffer Depth = 16 - // 0x0000ff00 [15:8] : RX_BUFFER_DEPTH (0): RX Buffer Depth = 16 - // 0x00000080 [7] : ADD_ENCODED_PARAMS (0): Encoded parameters not visible - // 0x00000040 [6] : HAS_DMA (0): DMA handshaking signals are enabled - // 0x00000020 [5] : INTR_IO (0): COMBINED Interrupt outputs - // 0x00000010 [4] : HC_COUNT_VALUES (0): Programmable count values for each mode - // 0x0000000c [3:2] : MAX_SPEED_MODE (0): MAX SPEED MODE = FAST MODE - // 0x00000003 [1:0] : APB_DATA_WIDTH (0): APB data bus width is 32 bits + // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 + // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 + // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible + // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled + // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs + // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode + // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE + // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits io_ro_32 comp_param_1; - + _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION // I2C Component Version Register - // 0xffffffff [31:0] : IC_COMP_VERSION (0x3230312a) + // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) io_ro_32 comp_version; - + _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE // I2C Component Type Register - // 0xffffffff [31:0] : IC_COMP_TYPE (0x44570140): Designware Component Type number = 0x44_57_01_40 + // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 io_ro_32 comp_type; } i2c_hw_t; #define i2c0_hw ((i2c_hw_t *)I2C0_BASE) #define i2c1_hw ((i2c_hw_t *)I2C1_BASE) +static_assert(sizeof (i2c_hw_t) == 0x0100, ""); + +#endif // _HARDWARE_STRUCTS_I2C_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/interp.h b/src/rp2040/hardware_structs/include/hardware/structs/interp.h index e96caab2f..abc06843a 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/interp.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/interp.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_INTERP_H #define _HARDWARE_STRUCTS_INTERP_H +/** + * \file rp2040/interp.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/sio.h" @@ -18,65 +21,66 @@ // _REG_(x) will link to the corresponding register in hardware/regs/sio.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { - _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) - // + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 // Read/write access to accumulator 0 + // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) io_rw_32 accum[2]; - - _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) - // + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 // Read/write access to BASE0 register + // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) io_rw_32 base[3]; - - _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) - // + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) + // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) io_ro_32 pop[3]; - - _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) - // + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 // Read LANE0 result, without altering any internal state (PEEK) + // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) io_ro_32 peek[3]; - - _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) - // + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 // Control register for lane 0 - // 0x02000000 [25] : OVERF (0): Set if either OVERF0 or OVERF1 is set - // 0x01000000 [24] : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set - // 0x00800000 [23] : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set - // 0x00200000 [21] : BLEND (0): Only present on INTERP0 on each core - // 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus - // 0x00040000 [18] : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result - // 0x00020000 [17] : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP - // 0x00010000 [16] : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware - // 0x00008000 [15] : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - // 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive) - // 0x000003e0 [9:5] : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive) - // 0x0000001f [4:0] : SHIFT (0): Logical right-shift applied to accumulator before masking + // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core + // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... + // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... + // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... + // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... + // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... + // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking io_rw_32 ctrl[2]; - - _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) - // + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD // Values written here are atomically added to ACCUM0 - // 0x00ffffff [23:0] : INTERP0_ACCUM0_ADD (0) + // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) io_rw_32 add_raw[2]; - + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 - // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) io_wo_32 base01; } interp_hw_t; #define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +static_assert(sizeof (interp_hw_t) == 0x0040, ""); #define interp0_hw (&interp_hw_array[0]) #define interp1_hw (&interp_hw_array[1]) -#endif +#endif // _HARDWARE_STRUCTS_INTERP_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/io_bank0.h b/src/rp2040/hardware_structs/include/hardware/structs/io_bank0.h new file mode 100644 index 000000000..6c09bb043 --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/io_bank0.h @@ -0,0 +1,236 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_BANK0_H +#define _HARDWARE_STRUCTS_IO_BANK0_H + +/** + * \file rp2040/io_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief GPIO pin function selectors on RP2040 (used as typedef \ref gpio_function_t) + * \ingroup hardware_gpio + */ +typedef enum gpio_function_rp2040 { + GPIO_FUNC_XIP = 0, ///< Select XIP as GPIO pin function + GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function + GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function + GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function + GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function + GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function + GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function + GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function + GPIO_FUNC_GPCK = 8, ///< Select GPCK as GPIO pin function + GPIO_FUNC_USB = 9, ///< Select USB as GPIO pin function + GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function +} gpio_function_t; + +typedef struct { + _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS + // GPIO status + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied + // 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register... + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + // 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register... + io_ro_32 status; + + _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x00003000 [13:12] OEOVER (0x0) + // 0x00000300 [9:8] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_bank0_status_ctrl_hw_t; + +typedef struct { + // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 inte[4]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intf[4]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_ro_32 ints[4]; +} io_bank0_irq_ctrl_hw_t; + +/// \tag::io_bank0_hw[] +typedef struct { + io_bank0_status_ctrl_hw_t io[30]; + + // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) + _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 + // Raw Interrupts + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intr[4]; + + union { + struct { + io_bank0_irq_ctrl_hw_t proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t proc1_irq_ctrl; + io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_bank0_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_bank0_hw_t; +/// \end::io_bank0_hw[] + +#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE) +static_assert(sizeof (io_bank0_hw_t) == 0x0190, ""); + +#endif // _HARDWARE_STRUCTS_IO_BANK0_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/io_qspi.h b/src/rp2040/hardware_structs/include/hardware/structs/io_qspi.h new file mode 100644 index 000000000..4dca02f5c --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/io_qspi.h @@ -0,0 +1,189 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_QSPI_H +#define _HARDWARE_STRUCTS_IO_QSPI_H + +/** + * \file rp2040/io_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief QSPI pin function selectors on RP2040 (used as typedef \ref gpio_function1_t) + */ +typedef enum gpio_function1_rp2040 { + GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function + GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function + GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function +} gpio_function1_t; + +typedef struct { + _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS + // GPIO status + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied + // 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register... + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + // 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register... + io_ro_32 status; + + _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x00003000 [13:12] OEOVER (0x0) + // 0x00000300 [9:8] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_qspi_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE + // Interrupt Enable for proc0 + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 inte; + + _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF + // Interrupt Force for proc0 + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intf; + + _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS + // Interrupt status after masking & forcing for proc0 + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_ro_32 ints; +} io_qspi_irq_ctrl_hw_t; + +typedef struct { + io_qspi_status_ctrl_hw_t io[6]; + + _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR + // Raw Interrupts + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intr; + + union { + struct { + io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; + io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; + io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_qspi_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_qspi_hw_t; + +#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) +static_assert(sizeof (io_qspi_hw_t) == 0x0058, ""); + +#endif // _HARDWARE_STRUCTS_IO_QSPI_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h b/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h index 04b3f4d71..2dc31e38d 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/iobank0.h @@ -1,216 +1,9 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _HARDWARE_STRUCTS_IOBANK0_H -#define _HARDWARE_STRUCTS_IOBANK0_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/io_bank0.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION - -typedef struct { - _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS - // GPIO status - // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied - // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied - // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied - // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied - // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied - // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied - // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied - // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied - io_ro_32 status; - - _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL - // GPIO control including function select and overrides - // 0x30000000 [29:28] : IRQOVER (0) - // 0x00030000 [17:16] : INOVER (0) - // 0x00003000 [13:12] : OEOVER (0) - // 0x00000300 [9:8] : OUTOVER (0) - // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table - io_rw_32 ctrl; -} iobank0_status_ctrl_hw_t; - -typedef struct { - _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 - // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) - // - // Interrupt Enable for proc0 - // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] : GPIO7_EDGE_LOW (0) - // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] : GPIO6_EDGE_LOW (0) - // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO5_EDGE_LOW (0) - // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO4_EDGE_LOW (0) - // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO3_EDGE_LOW (0) - // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO2_EDGE_LOW (0) - // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO1_EDGE_LOW (0) - // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO0_EDGE_LOW (0) - // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) - io_rw_32 inte[4]; - - _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 - // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) - // - // Interrupt Force for proc0 - // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] : GPIO7_EDGE_LOW (0) - // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] : GPIO6_EDGE_LOW (0) - // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO5_EDGE_LOW (0) - // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO4_EDGE_LOW (0) - // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO3_EDGE_LOW (0) - // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO2_EDGE_LOW (0) - // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO1_EDGE_LOW (0) - // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO0_EDGE_LOW (0) - // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) - io_rw_32 intf[4]; - - _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 - // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) - // - // Interrupt status after masking & forcing for proc0 - // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] : GPIO7_EDGE_LOW (0) - // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] : GPIO6_EDGE_LOW (0) - // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO5_EDGE_LOW (0) - // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO4_EDGE_LOW (0) - // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO3_EDGE_LOW (0) - // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO2_EDGE_LOW (0) - // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO1_EDGE_LOW (0) - // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO0_EDGE_LOW (0) - // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) - io_ro_32 ints[4]; -} io_irq_ctrl_hw_t; - -/// \tag::iobank0_hw[] -typedef struct { - iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30 - - _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 - // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) - // - // Raw Interrupts - // 0x80000000 [31] : GPIO7_EDGE_HIGH (0) - // 0x40000000 [30] : GPIO7_EDGE_LOW (0) - // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0) - // 0x10000000 [28] : GPIO7_LEVEL_LOW (0) - // 0x08000000 [27] : GPIO6_EDGE_HIGH (0) - // 0x04000000 [26] : GPIO6_EDGE_LOW (0) - // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0) - // 0x01000000 [24] : GPIO6_LEVEL_LOW (0) - // 0x00800000 [23] : GPIO5_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO5_EDGE_LOW (0) - // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO5_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO4_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO4_EDGE_LOW (0) - // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO4_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO3_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO3_EDGE_LOW (0) - // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO3_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO2_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO2_EDGE_LOW (0) - // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO2_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO1_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO1_EDGE_LOW (0) - // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO1_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO0_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO0_EDGE_LOW (0) - // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO0_LEVEL_LOW (0) - io_rw_32 intr[4]; - - io_irq_ctrl_hw_t proc0_irq_ctrl; - - io_irq_ctrl_hw_t proc1_irq_ctrl; - - io_irq_ctrl_hw_t dormant_wake_irq_ctrl; -} iobank0_hw_t; - -#define iobank0_hw ((iobank0_hw_t *)IO_BANK0_BASE) -/// \end::iobank0_hw[] - -static_assert( NUM_BANK0_GPIOS == 30, ""); - -#endif +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_bank0.h" +#define iobank0_hw io_bank0_hw \ No newline at end of file diff --git a/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h b/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h index 70ba09e35..20cc74c79 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h @@ -1,174 +1,9 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _HARDWARE_STRUCTS_IOQSPI_H -#define _HARDWARE_STRUCTS_IOQSPI_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/io_qspi.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION - -typedef struct { - _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS - // GPIO status - // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied - // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied - // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied - // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied - // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied - // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied - // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied - // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied - io_ro_32 status; - - _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL - // GPIO control including function select and overrides - // 0x30000000 [29:28] : IRQOVER (0) - // 0x00030000 [17:16] : INOVER (0) - // 0x00003000 [13:12] : OEOVER (0) - // 0x00000300 [9:8] : OUTOVER (0) - // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table - io_rw_32 ctrl; -} ioqspi_status_ctrl_hw_t; - -typedef struct { - _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE - // Interrupt Enable for proc0 - // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_rw_32 inte; - - _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF - // Interrupt Force for proc0 - // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_rw_32 intf; - - _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS - // Interrupt status after masking & forcing for proc0 - // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_ro_32 ints; -} io_qspi_ctrl_hw_t; - -typedef struct { - ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6 - - _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR - // Raw Interrupts - // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0) - // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0) - // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0) - // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0) - // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0) - // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0) - // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0) - // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0) - // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0) - // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0) - // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0) - // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0) - // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0) - // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0) - // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0) - // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0) - // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0) - // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0) - // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0) - // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0) - // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0) - // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0) - // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0) - // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0) - io_rw_32 intr; - - io_qspi_ctrl_hw_t proc0_qspi_ctrl; - - io_qspi_ctrl_hw_t proc1_qspi_ctrl; - - io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl; -} ioqspi_hw_t; - -#define ioqspi_hw ((ioqspi_hw_t *)IO_QSPI_BASE) - -static_assert( NUM_QSPI_GPIOS == 6, ""); - -#endif +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_qspi.h" +#define ioqspi_hw io_qspi_hw \ No newline at end of file diff --git a/src/rp2040/hardware_structs/include/hardware/structs/m0plus.h b/src/rp2040/hardware_structs/include/hardware/structs/m0plus.h new file mode 100644 index 000000000..6d30edec0 --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/m0plus.h @@ -0,0 +1,197 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M0PLUS_H +#define _HARDWARE_STRUCTS_M0PLUS_H + +/** + * \file rp2040/m0plus.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + uint32_t _pad0[14340]; + + _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 syst_csr; + + _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 syst_rvr; + + _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 syst_cvr; + + _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 syst_calib; + + uint32_t _pad1[56]; + + _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER + // Interrupt Set-Enable Register + // 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits + io_rw_32 nvic_iser; + + uint32_t _pad2[31]; + + _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER + // Interrupt Clear-Enable Register + // 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits + io_rw_32 nvic_icer; + + uint32_t _pad3[31]; + + _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR + // Interrupt Set-Pending Register + // 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits + io_rw_32 nvic_ispr; + + uint32_t _pad4[31]; + + _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR + // Interrupt Clear-Pending Register + // 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits + io_rw_32 nvic_icpr; + + uint32_t _pad5[95]; + + // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 + // Interrupt Priority Register 0 + // 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3 + // 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2 + // 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1 + // 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0 + io_rw_32 nvic_ipr[8]; + + uint32_t _pad6[568]; + + _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID + // CPUID Base Register + // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM + // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: + + // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: + + // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+ + // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: + + io_ro_32 cpuid; + + _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR + // Interrupt Control and State Register + // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI + // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit + // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit + // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit + // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit + // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted + // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag + // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority... + // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field + io_rw_32 icsr; + + _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR + // Vector Table Offset Register + // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address + io_rw_32 vtor; + + _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR + // Configuration and Control Register + // 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on... + // 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned... + io_ro_32 ccr; + + uint32_t _pad7; + + // (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes) + _REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2 + // System Handler Priority Register 2 + // 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall + io_rw_32 shpr[2]; + + _REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR + // System Handler Control and State Register + // 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending + io_rw_32 shcsr; + + uint32_t _pad8[26]; + + _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE + // MPU Type Register + // 0x00ff0000 [23:16] IREGION (0x00) Instruction region + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps + io_ro_32 mpu_type; + + _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL + // MPU Control Register + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... + // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 mpu_ctrl; + + _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR + // MPU Region Number Register + // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... + io_rw_32 mpu_rnr; + + _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR + // MPU Region Base Address Register + // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region + // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... + // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... + io_rw_32 mpu_rbar; + + _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR + // MPU Region Attribute and Size Register + // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field + // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable + // 0x0000003e [5:1] SIZE (0x00) Indicates the region size + // 0x00000001 [0] ENABLE (0) Enables the region + io_rw_32 mpu_rasr; +} m0plus_hw_t; + +#define ppb_hw ((m0plus_hw_t *)PPB_BASE) +static_assert(sizeof (m0plus_hw_t) == 0xeda4, ""); + +#endif // _HARDWARE_STRUCTS_M0PLUS_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/mpu.h b/src/rp2040/hardware_structs/include/hardware/structs/mpu.h index 09fb644b7..766f4d589 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/mpu.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/mpu.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_MPU_H #define _HARDWARE_STRUCTS_MPU_H +/** + * \file rp2040/mpu.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" @@ -18,44 +21,46 @@ // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE - // Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports - // 0x00ff0000 [23:16] : IREGION (0): Instruction region - // 0x0000ff00 [15:8] : DREGION (0x8): Number of regions supported by the MPU - // 0x00000001 [0] : SEPARATE (0): Indicates support for separate instruction and data address maps + // MPU Type Register + // 0x00ff0000 [23:16] IREGION (0x00) Instruction region + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps io_ro_32 type; - + _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL - // Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled... - // 0x00000004 [2] : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for... - // 0x00000002 [1] : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs - // 0x00000001 [0] : ENABLE (0): Enables the MPU + // MPU Control Register + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... + // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs + // 0x00000001 [0] ENABLE (0) Enables the MPU io_rw_32 ctrl; - + _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR - // Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR - // 0x0000000f [3:0] : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers + // MPU Region Number Register + // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... io_rw_32 rnr; - + _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR - // Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR - // 0xffffff00 [31:8] : ADDR (0): Base address of the region - // 0x00000010 [4] : VALID (0): On writes, indicates whether the write must update the base address of the region... - // 0x0000000f [3:0] : REGION (0): On writes, specifies the number of the region whose base address to update provided... + // MPU Region Base Address Register + // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region + // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... + // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... io_rw_32 rbar; - + _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR - // Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region... - // 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field - // 0x0000ff00 [15:8] : SRD (0): Subregion Disable - // 0x0000003e [5:1] : SIZE (0): Indicates the region size - // 0x00000001 [0] : ENABLE (0): Enables the region + // MPU Region Attribute and Size Register + // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field + // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable + // 0x0000003e [5:1] SIZE (0x00) Indicates the region size + // 0x00000001 [0] ENABLE (0) Enables the region io_rw_32 rasr; } mpu_hw_t; #define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) +static_assert(sizeof (mpu_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_MPU_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/nvic.h b/src/rp2040/hardware_structs/include/hardware/structs/nvic.h index 47bc3076c..d09ebd19e 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/nvic.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/nvic.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_NVIC_H #define _HARDWARE_STRUCTS_NVIC_H +/** + * \file rp2040/nvic.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" @@ -18,48 +21,49 @@ // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER - // Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled - // 0xffffffff [31:0] : SETENA (0): Interrupt set-enable bits + // Interrupt Set-Enable Register + // 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits io_rw_32 iser; - + uint32_t _pad0[31]; - + _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER - // Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled - // 0xffffffff [31:0] : CLRENA (0): Interrupt clear-enable bits + // Interrupt Clear-Enable Register + // 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits io_rw_32 icer; - + uint32_t _pad1[31]; - + _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR - // The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending - // 0xffffffff [31:0] : SETPEND (0): Interrupt set-pending bits + // Interrupt Set-Pending Register + // 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits io_rw_32 ispr; - + uint32_t _pad2[31]; - + _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR - // Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending - // 0xffffffff [31:0] : CLRPEND (0): Interrupt clear-pending bits + // Interrupt Clear-Pending Register + // 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits io_rw_32 icpr; - + uint32_t _pad3[95]; - - _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 + // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes) - // - // Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts - // 0xc0000000 [31:30] : IP_3 (0): Priority of interrupt 3 - // 0x00c00000 [23:22] : IP_2 (0): Priority of interrupt 2 - // 0x0000c000 [15:14] : IP_1 (0): Priority of interrupt 1 - // 0x000000c0 [7:6] : IP_0 (0): Priority of interrupt 0 + _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 + // Interrupt Priority Register 0 + // 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3 + // 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2 + // 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1 + // 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0 io_rw_32 ipr[8]; } nvic_hw_t; #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) +static_assert(sizeof (nvic_hw_t) == 0x0320, ""); + +#endif // _HARDWARE_STRUCTS_NVIC_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pads_bank0.h b/src/rp2040/hardware_structs/include/hardware/structs/pads_bank0.h new file mode 100644 index 000000000..f00c70afc --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/pads_bank0.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H +#define _HARDWARE_STRUCTS_PADS_BANK0_H + +/** + * \file rp2040/pads_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) + _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 + // Pad control register + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (1) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[30]; +} pads_bank0_hw_t; + +#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) +static_assert(sizeof (pads_bank0_hw_t) == 0x007c, ""); + +#endif // _HARDWARE_STRUCTS_PADS_BANK0_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h b/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h index 5c9d90fba..66b6c1a1b 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_PADS_QSPI_H #define _HARDWARE_STRUCTS_PADS_QSPI_H +/** + * \file rp2040/pads_qspi.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/pads_qspi.h" @@ -18,30 +21,29 @@ // _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT // Voltage select - // 0x00000001 [0] : VOLTAGE_SELECT (0) + // 0x00000001 [0] VOLTAGE_SELECT (0) io_rw_32 voltage_select; - - _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK + // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) - // + _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK // Pad control register - // 0x00000080 [7] : OD (0): Output disable - // 0x00000040 [6] : IE (1): Input enable - // 0x00000030 [5:4] : DRIVE (1): Drive strength - // 0x00000008 [3] : PUE (0): Pull up enable - // 0x00000004 [2] : PDE (1): Pull down enable - // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger - // 0x00000001 [0] : SLEWFAST (0): Slew rate control - io_rw_32 io[NUM_QSPI_GPIOS]; // 6 + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (1) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[6]; } pads_qspi_hw_t; #define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE) +static_assert(sizeof (pads_qspi_hw_t) == 0x001c, ""); -static_assert( NUM_QSPI_GPIOS == 6, ""); +#endif // _HARDWARE_STRUCTS_PADS_QSPI_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h b/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h index fbb60525a..cb14e792b 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h @@ -1,47 +1,9 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _HARDWARE_STRUCTS_PADSBANK0_H -#define _HARDWARE_STRUCTS_PADSBANK0_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/pads_bank0.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0 -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION - -typedef struct { - _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT - // Voltage select - // 0x00000001 [0] : VOLTAGE_SELECT (0) - io_rw_32 voltage_select; - - _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 - // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) - // - // Pad control register - // 0x00000080 [7] : OD (0): Output disable - // 0x00000040 [6] : IE (1): Input enable - // 0x00000030 [5:4] : DRIVE (1): Drive strength - // 0x00000008 [3] : PUE (0): Pull up enable - // 0x00000004 [2] : PDE (1): Pull down enable - // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger - // 0x00000001 [0] : SLEWFAST (0): Slew rate control - io_rw_32 io[NUM_BANK0_GPIOS]; // 30 -} padsbank0_hw_t; - -#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE) - -static_assert( NUM_BANK0_GPIOS == 30, ""); - -#endif +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/pads_bank0.h" +#define padsbank0_hw pads_bank0_hw \ No newline at end of file diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pio.h b/src/rp2040/hardware_structs/include/hardware/structs/pio.h index 6a3126a0e..bceb14a71 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/pio.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/pio.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_PIO_H #define _HARDWARE_STRUCTS_PIO_H +/** + * \file rp2040/pio.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/pio.h" @@ -18,267 +21,323 @@ // _REG_(x) will link to the corresponding register in hardware/regs/pio.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION -typedef struct pio_sm_hw { +typedef struct { _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV - // Clock divisor register for state machine 0 - // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256) - // 0x0000ff00 [15:8] : FRAC (0): Fractional part of clock divisor + // Clock divisor register for state machine 0 + + // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) + // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor io_rw_32 clkdiv; - + _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL // Execution/behavioural settings for state machine 0 - // 0x80000000 [31] : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine - // 0x40000000 [30] : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,... - // 0x20000000 [29] : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values - // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN - // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable - // 0x00040000 [18] : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable - // 0x00020000 [17] : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins - // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom - // 0x00000f80 [11:7] : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address - // 0x00000010 [4] : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction - // 0x0000000f [3:0] : STATUS_N (0): Comparison level for the MOV x, STATUS instruction + // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... + // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... + // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... + // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN + // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable + // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + + // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins + // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom + // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address + // 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction + // 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction io_rw_32 execctrl; - + _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL // Control behaviour of the input/output shift registers for state machine 0 - // 0x80000000 [31] : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep - // 0x40000000 [30] : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep - // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL... - // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH... - // 0x00080000 [19] : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right - // 0x00040000 [18] : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left) - // 0x00020000 [17] : AUTOPULL (0): Pull automatically when the output shift register is emptied, i - // 0x00010000 [16] : AUTOPUSH (0): Push automatically when the input shift register is filled, i + // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... + // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... + // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... + // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... + // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right + // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) + // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i + // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i io_rw_32 shiftctrl; - + _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR // Current instruction address of state machine 0 - // 0x0000001f [4:0] : SM0_ADDR (0) + // 0x0000001f [4:0] SM0_ADDR (0x00) io_ro_32 addr; - + _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR - // Read to see the instruction currently addressed by state machine 0's program counter - // 0x0000ffff [15:0] : SM0_INSTR (0) + // Read to see the instruction currently addressed by state machine 0's program counter + + // 0x0000ffff [15:0] SM0_INSTR (-) io_rw_32 instr; - + _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL // State machine pin control - // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used... - // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET - // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction - // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus - // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation - // 0x000003e0 [9:5] : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction - // 0x0000001f [4:0] : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV... + // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... + // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET + // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... + // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... + // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... + // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... + // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... io_rw_32 pinctrl; } pio_sm_hw_t; +typedef struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints; +} pio_irq_ctrl_hw_t; + typedef struct { _REG_(PIO_CTRL_OFFSET) // PIO_CTRL // PIO control register - // 0x00000f00 [11:8] : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0 - // 0x000000f0 [7:4] : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult... - // 0x0000000f [3:0] : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits + // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... + // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... + // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... io_rw_32 ctrl; - + _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT // FIFO status register - // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty - // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full - // 0x00000f00 [11:8] : RXEMPTY (0xf): State machine RX FIFO is empty - // 0x0000000f [3:0] : RXFULL (0): State machine RX FIFO is full + // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty + // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full + // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty + // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full io_ro_32 fstat; - + _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG // FIFO debug register - // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with... - // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i - // 0x00000f00 [11:8] : RXUNDER (0): RX FIFO underflow (i - // 0x0000000f [3:0] : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with... + // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... + // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i + // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i + // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... io_rw_32 fdebug; - + _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL // FIFO levels - // 0xf0000000 [31:28] : RX3 (0) - // 0x0f000000 [27:24] : TX3 (0) - // 0x00f00000 [23:20] : RX2 (0) - // 0x000f0000 [19:16] : TX2 (0) - // 0x0000f000 [15:12] : RX1 (0) - // 0x00000f00 [11:8] : TX1 (0) - // 0x000000f0 [7:4] : RX0 (0) - // 0x0000000f [3:0] : TX0 (0) + // 0xf0000000 [31:28] RX3 (0x0) + // 0x0f000000 [27:24] TX3 (0x0) + // 0x00f00000 [23:20] RX2 (0x0) + // 0x000f0000 [19:16] TX2 (0x0) + // 0x0000f000 [15:12] RX1 (0x0) + // 0x00000f00 [11:8] TX1 (0x0) + // 0x000000f0 [7:4] RX0 (0x0) + // 0x0000000f [3:0] TX0 (0x0) io_ro_32 flevel; - - _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 + // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) - // + _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 // Direct write access to the TX FIFO for this state machine - io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4 - - _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 + // 0xffffffff [31:0] TXF0 (0x00000000) + io_wo_32 txf[4]; + // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) - // + _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 // Direct read access to the RX FIFO for this state machine - io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4 - + // 0xffffffff [31:0] RXF0 (-) + io_ro_32 rxf[4]; + _REG_(PIO_IRQ_OFFSET) // PIO_IRQ // State machine IRQ flags register - // 0x000000ff [7:0] : IRQ (0) + // 0x000000ff [7:0] IRQ (0x00) io_rw_32 irq; - + _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ - // 0x000000ff [7:0] : IRQ_FORCE (0) + // 0x000000ff [7:0] IRQ_FORCE (0x00) io_wo_32 irq_force; - + _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities + // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) io_rw_32 input_sync_bypass; - + _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT // Read to sample the pad output values PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOUT (0x00000000) io_ro_32 dbg_padout; - + _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOE (0x00000000) io_ro_32 dbg_padoe; - + _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO // The PIO hardware has some free parameters that may vary between chip products - // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction - // 0x00000f00 [11:8] : SM_COUNT (0): The number of state machines this PIO instance is equipped with - // 0x0000003f [5:0] : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words + // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... + // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with + // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words io_ro_32 dbg_cfginfo; - - _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 + // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) - // + _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 // Write-only access to instruction memory location 0 - // 0x0000ffff [15:0] : INSTR_MEM0 (0) - io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32 - - pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4 - + // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) + io_wo_32 instr_mem[32]; + + pio_sm_hw_t sm[4]; + _REG_(PIO_INTR_OFFSET) // PIO_INTR // Raw Interrupts - // 0x00000800 [11] : SM3 (0) - // 0x00000400 [10] : SM2 (0) - // 0x00000200 [9] : SM1 (0) - // 0x00000100 [8] : SM0 (0) - // 0x00000080 [7] : SM3_TXNFULL (0) - // 0x00000040 [6] : SM2_TXNFULL (0) - // 0x00000020 [5] : SM1_TXNFULL (0) - // 0x00000010 [4] : SM0_TXNFULL (0) - // 0x00000008 [3] : SM3_RXNEMPTY (0) - // 0x00000004 [2] : SM2_RXNEMPTY (0) - // 0x00000002 [1] : SM1_RXNEMPTY (0) - // 0x00000001 [0] : SM0_RXNEMPTY (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) io_ro_32 intr; - - _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE - // Interrupt Enable for irq0 - // 0x00000800 [11] : SM3 (0) - // 0x00000400 [10] : SM2 (0) - // 0x00000200 [9] : SM1 (0) - // 0x00000100 [8] : SM0 (0) - // 0x00000080 [7] : SM3_TXNFULL (0) - // 0x00000040 [6] : SM2_TXNFULL (0) - // 0x00000020 [5] : SM1_TXNFULL (0) - // 0x00000010 [4] : SM0_TXNFULL (0) - // 0x00000008 [3] : SM3_RXNEMPTY (0) - // 0x00000004 [2] : SM2_RXNEMPTY (0) - // 0x00000002 [1] : SM1_RXNEMPTY (0) - // 0x00000001 [0] : SM0_RXNEMPTY (0) - io_rw_32 inte0; - - _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF - // Interrupt Force for irq0 - // 0x00000800 [11] : SM3 (0) - // 0x00000400 [10] : SM2 (0) - // 0x00000200 [9] : SM1 (0) - // 0x00000100 [8] : SM0 (0) - // 0x00000080 [7] : SM3_TXNFULL (0) - // 0x00000040 [6] : SM2_TXNFULL (0) - // 0x00000020 [5] : SM1_TXNFULL (0) - // 0x00000010 [4] : SM0_TXNFULL (0) - // 0x00000008 [3] : SM3_RXNEMPTY (0) - // 0x00000004 [2] : SM2_RXNEMPTY (0) - // 0x00000002 [1] : SM1_RXNEMPTY (0) - // 0x00000001 [0] : SM0_RXNEMPTY (0) - io_rw_32 intf0; - - _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS - // Interrupt status after masking & forcing for irq0 - // 0x00000800 [11] : SM3 (0) - // 0x00000400 [10] : SM2 (0) - // 0x00000200 [9] : SM1 (0) - // 0x00000100 [8] : SM0 (0) - // 0x00000080 [7] : SM3_TXNFULL (0) - // 0x00000040 [6] : SM2_TXNFULL (0) - // 0x00000020 [5] : SM1_TXNFULL (0) - // 0x00000010 [4] : SM0_TXNFULL (0) - // 0x00000008 [3] : SM3_RXNEMPTY (0) - // 0x00000004 [2] : SM2_RXNEMPTY (0) - // 0x00000002 [1] : SM1_RXNEMPTY (0) - // 0x00000001 [0] : SM0_RXNEMPTY (0) - io_ro_32 ints0; - - _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE - // Interrupt Enable for irq1 - // 0x00000800 [11] : SM3 (0) - // 0x00000400 [10] : SM2 (0) - // 0x00000200 [9] : SM1 (0) - // 0x00000100 [8] : SM0 (0) - // 0x00000080 [7] : SM3_TXNFULL (0) - // 0x00000040 [6] : SM2_TXNFULL (0) - // 0x00000020 [5] : SM1_TXNFULL (0) - // 0x00000010 [4] : SM0_TXNFULL (0) - // 0x00000008 [3] : SM3_RXNEMPTY (0) - // 0x00000004 [2] : SM2_RXNEMPTY (0) - // 0x00000002 [1] : SM1_RXNEMPTY (0) - // 0x00000001 [0] : SM0_RXNEMPTY (0) - io_rw_32 inte1; - - _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF - // Interrupt Force for irq1 - // 0x00000800 [11] : SM3 (0) - // 0x00000400 [10] : SM2 (0) - // 0x00000200 [9] : SM1 (0) - // 0x00000100 [8] : SM0 (0) - // 0x00000080 [7] : SM3_TXNFULL (0) - // 0x00000040 [6] : SM2_TXNFULL (0) - // 0x00000020 [5] : SM1_TXNFULL (0) - // 0x00000010 [4] : SM0_TXNFULL (0) - // 0x00000008 [3] : SM3_RXNEMPTY (0) - // 0x00000004 [2] : SM2_RXNEMPTY (0) - // 0x00000002 [1] : SM1_RXNEMPTY (0) - // 0x00000001 [0] : SM0_RXNEMPTY (0) - io_rw_32 intf1; - - _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS - // Interrupt status after masking & forcing for irq1 - // 0x00000800 [11] : SM3 (0) - // 0x00000400 [10] : SM2 (0) - // 0x00000200 [9] : SM1 (0) - // 0x00000100 [8] : SM0 (0) - // 0x00000080 [7] : SM3_TXNFULL (0) - // 0x00000040 [6] : SM2_TXNFULL (0) - // 0x00000020 [5] : SM1_TXNFULL (0) - // 0x00000010 [4] : SM0_TXNFULL (0) - // 0x00000008 [3] : SM3_RXNEMPTY (0) - // 0x00000004 [2] : SM2_RXNEMPTY (0) - // 0x00000002 [1] : SM1_RXNEMPTY (0) - // 0x00000001 [0] : SM0_RXNEMPTY (0) - io_ro_32 ints1; + + union { + struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte0; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf0; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints0; + + _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte1; + + _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf1; + + _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints1; + }; + pio_irq_ctrl_hw_t irq_ctrl[2]; + }; } pio_hw_t; #define pio0_hw ((pio_hw_t *)PIO0_BASE) #define pio1_hw ((pio_hw_t *)PIO1_BASE) +static_assert(sizeof (pio_hw_t) == 0x0144, ""); -static_assert( NUM_PIO_STATE_MACHINES == 4, ""); -static_assert( PIO_INSTRUCTION_COUNT == 32, ""); +#endif // _HARDWARE_STRUCTS_PIO_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pll.h b/src/rp2040/hardware_structs/include/hardware/structs/pll.h index 5633ad9d9..7d3ccc82b 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/pll.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/pll.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_PLL_H #define _HARDWARE_STRUCTS_PLL_H +/** + * \file rp2040/pll.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/pll.h" @@ -18,39 +21,41 @@ // _REG_(x) will link to the corresponding register in hardware/regs/pll.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION /// \tag::pll_hw[] typedef struct { _REG_(PLL_CS_OFFSET) // PLL_CS // Control and Status - // 0x80000000 [31] : LOCK (0): PLL is locked - // 0x00000100 [8] : BYPASS (0): Passes the reference clock to the output instead of the divided VCO - // 0x0000003f [5:0] : REFDIV (1): Divides the PLL input reference clock + // 0x80000000 [31] LOCK (0) PLL is locked + // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the... + // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock io_rw_32 cs; - + _REG_(PLL_PWR_OFFSET) // PLL_PWR // Controls the PLL power modes - // 0x00000020 [5] : VCOPD (1): PLL VCO powerdown - // 0x00000008 [3] : POSTDIVPD (1): PLL post divider powerdown - // 0x00000004 [2] : DSMPD (1): PLL DSM powerdown - // 0x00000001 [0] : PD (1): PLL powerdown + // 0x00000020 [5] VCOPD (1) PLL VCO powerdown + + // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown + + // 0x00000004 [2] DSMPD (1) PLL DSM powerdown + + // 0x00000001 [0] PD (1) PLL powerdown + io_rw_32 pwr; - + _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT // Feedback divisor - // 0x00000fff [11:0] : FBDIV_INT (0): see ctrl reg description for constraints + // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints io_rw_32 fbdiv_int; - + _REG_(PLL_PRIM_OFFSET) // PLL_PRIM // Controls the PLL post dividers for the primary output - // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7 - // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7 + // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7 + // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7 io_rw_32 prim; } pll_hw_t; +/// \end::pll_hw[] #define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) #define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) -/// \end::pll_hw[] +static_assert(sizeof (pll_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_PLL_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/psm.h b/src/rp2040/hardware_structs/include/hardware/structs/psm.h index 3b9e65e4d..74ccaf32a 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/psm.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/psm.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_PSM_H #define _HARDWARE_STRUCTS_PSM_H +/** + * \file rp2040/psm.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/psm.h" @@ -18,94 +21,96 @@ // _REG_(x) will link to the corresponding register in hardware/regs/psm.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON // Force block out of reset (i - // 0x00010000 [16] : proc1 (0) - // 0x00008000 [15] : proc0 (0) - // 0x00004000 [14] : sio (0) - // 0x00002000 [13] : vreg_and_chip_reset (0) - // 0x00001000 [12] : xip (0) - // 0x00000800 [11] : sram5 (0) - // 0x00000400 [10] : sram4 (0) - // 0x00000200 [9] : sram3 (0) - // 0x00000100 [8] : sram2 (0) - // 0x00000080 [7] : sram1 (0) - // 0x00000040 [6] : sram0 (0) - // 0x00000020 [5] : rom (0) - // 0x00000010 [4] : busfabric (0) - // 0x00000008 [3] : resets (0) - // 0x00000004 [2] : clocks (0) - // 0x00000002 [1] : xosc (0) - // 0x00000001 [0] : rosc (0) + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) io_rw_32 frce_on; - + _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF // Force into reset (i - // 0x00010000 [16] : proc1 (0) - // 0x00008000 [15] : proc0 (0) - // 0x00004000 [14] : sio (0) - // 0x00002000 [13] : vreg_and_chip_reset (0) - // 0x00001000 [12] : xip (0) - // 0x00000800 [11] : sram5 (0) - // 0x00000400 [10] : sram4 (0) - // 0x00000200 [9] : sram3 (0) - // 0x00000100 [8] : sram2 (0) - // 0x00000080 [7] : sram1 (0) - // 0x00000040 [6] : sram0 (0) - // 0x00000020 [5] : rom (0) - // 0x00000010 [4] : busfabric (0) - // 0x00000008 [3] : resets (0) - // 0x00000004 [2] : clocks (0) - // 0x00000002 [1] : xosc (0) - // 0x00000001 [0] : rosc (0) + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) io_rw_32 frce_off; - + _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL // Set to 1 if this peripheral should be reset when the watchdog fires - // 0x00010000 [16] : proc1 (0) - // 0x00008000 [15] : proc0 (0) - // 0x00004000 [14] : sio (0) - // 0x00002000 [13] : vreg_and_chip_reset (0) - // 0x00001000 [12] : xip (0) - // 0x00000800 [11] : sram5 (0) - // 0x00000400 [10] : sram4 (0) - // 0x00000200 [9] : sram3 (0) - // 0x00000100 [8] : sram2 (0) - // 0x00000080 [7] : sram1 (0) - // 0x00000040 [6] : sram0 (0) - // 0x00000020 [5] : rom (0) - // 0x00000010 [4] : busfabric (0) - // 0x00000008 [3] : resets (0) - // 0x00000004 [2] : clocks (0) - // 0x00000002 [1] : xosc (0) - // 0x00000001 [0] : rosc (0) + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) io_rw_32 wdsel; - + _REG_(PSM_DONE_OFFSET) // PSM_DONE // Indicates the peripheral's registers are ready to access - // 0x00010000 [16] : proc1 (0) - // 0x00008000 [15] : proc0 (0) - // 0x00004000 [14] : sio (0) - // 0x00002000 [13] : vreg_and_chip_reset (0) - // 0x00001000 [12] : xip (0) - // 0x00000800 [11] : sram5 (0) - // 0x00000400 [10] : sram4 (0) - // 0x00000200 [9] : sram3 (0) - // 0x00000100 [8] : sram2 (0) - // 0x00000080 [7] : sram1 (0) - // 0x00000040 [6] : sram0 (0) - // 0x00000020 [5] : rom (0) - // 0x00000010 [4] : busfabric (0) - // 0x00000008 [3] : resets (0) - // 0x00000004 [2] : clocks (0) - // 0x00000002 [1] : xosc (0) - // 0x00000001 [0] : rosc (0) + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) io_ro_32 done; } psm_hw_t; #define psm_hw ((psm_hw_t *)PSM_BASE) +static_assert(sizeof (psm_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_PSM_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/pwm.h b/src/rp2040/hardware_structs/include/hardware/structs/pwm.h index f62c6d773..3eedee4d9 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/pwm.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/pwm.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_PWM_H #define _HARDWARE_STRUCTS_PWM_H +/** + * \file rp2040/pwm.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/pwm.h" @@ -18,109 +21,152 @@ // _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION -typedef struct pwm_slice_hw { +typedef struct { _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR // Control and status register - // 0x00000080 [7] : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running - // 0x00000040 [6] : PH_RET (0): Retard the phase of the counter by 1 count, while it is running - // 0x00000030 [5:4] : DIVMODE (0) - // 0x00000008 [3] : B_INV (0): Invert output B - // 0x00000004 [2] : A_INV (0): Invert output A - // 0x00000002 [1] : PH_CORRECT (0): 1: Enable phase-correct modulation - // 0x00000001 [0] : EN (0): Enable the PWM channel + // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running + // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running + // 0x00000030 [5:4] DIVMODE (0x0) + // 0x00000008 [3] B_INV (0) Invert output B + // 0x00000004 [2] A_INV (0) Invert output A + // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation + // 0x00000001 [0] EN (0) Enable the PWM channel io_rw_32 csr; - + _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV // INT and FRAC form a fixed-point fractional number - // 0x00000ff0 [11:4] : INT (1) - // 0x0000000f [3:0] : FRAC (0) + // 0x00000ff0 [11:4] INT (0x01) + // 0x0000000f [3:0] FRAC (0x0) io_rw_32 div; - + _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR // Direct access to the PWM counter - // 0x0000ffff [15:0] : CH0_CTR (0) + // 0x0000ffff [15:0] CH0_CTR (0x0000) io_rw_32 ctr; - + _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC // Counter compare values - // 0xffff0000 [31:16] : B (0) - // 0x0000ffff [15:0] : A (0) + // 0xffff0000 [31:16] B (0x0000) + // 0x0000ffff [15:0] A (0x0000) io_rw_32 cc; - + _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP // Counter wrap value - // 0x0000ffff [15:0] : CH0_TOP (0xffff) + // 0x0000ffff [15:0] CH0_TOP (0xffff) io_rw_32 top; } pwm_slice_hw_t; typedef struct { - pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8 - - _REG_(PWM_EN_OFFSET) // PWM_EN - // This register aliases the CSR_EN bits for all channels - // 0x00000080 [7] : CH7 (0) - // 0x00000040 [6] : CH6 (0) - // 0x00000020 [5] : CH5 (0) - // 0x00000010 [4] : CH4 (0) - // 0x00000008 [3] : CH3 (0) - // 0x00000004 [2] : CH2 (0) - // 0x00000002 [1] : CH1 (0) - // 0x00000001 [0] : CH0 (0) - io_rw_32 en; - - _REG_(PWM_INTR_OFFSET) // PWM_INTR - // Raw Interrupts - // 0x00000080 [7] : CH7 (0) - // 0x00000040 [6] : CH6 (0) - // 0x00000020 [5] : CH5 (0) - // 0x00000010 [4] : CH4 (0) - // 0x00000008 [3] : CH3 (0) - // 0x00000004 [2] : CH2 (0) - // 0x00000002 [1] : CH1 (0) - // 0x00000001 [0] : CH0 (0) - io_rw_32 intr; - _REG_(PWM_INTE_OFFSET) // PWM_INTE // Interrupt Enable - // 0x00000080 [7] : CH7 (0) - // 0x00000040 [6] : CH6 (0) - // 0x00000020 [5] : CH5 (0) - // 0x00000010 [4] : CH4 (0) - // 0x00000008 [3] : CH3 (0) - // 0x00000004 [2] : CH2 (0) - // 0x00000002 [1] : CH1 (0) - // 0x00000001 [0] : CH0 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) io_rw_32 inte; - + _REG_(PWM_INTF_OFFSET) // PWM_INTF // Interrupt Force - // 0x00000080 [7] : CH7 (0) - // 0x00000040 [6] : CH6 (0) - // 0x00000020 [5] : CH5 (0) - // 0x00000010 [4] : CH4 (0) - // 0x00000008 [3] : CH3 (0) - // 0x00000004 [2] : CH2 (0) - // 0x00000002 [1] : CH1 (0) - // 0x00000001 [0] : CH0 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) io_rw_32 intf; - + _REG_(PWM_INTS_OFFSET) // PWM_INTS // Interrupt status after masking & forcing - // 0x00000080 [7] : CH7 (0) - // 0x00000040 [6] : CH6 (0) - // 0x00000020 [5] : CH5 (0) - // 0x00000010 [4] : CH4 (0) - // 0x00000008 [3] : CH3 (0) - // 0x00000004 [2] : CH2 (0) - // 0x00000002 [1] : CH1 (0) - // 0x00000001 [0] : CH0 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) io_ro_32 ints; +} pwm_irq_ctrl_hw_t; + +typedef struct { + pwm_slice_hw_t slice[8]; + + _REG_(PWM_EN_OFFSET) // PWM_EN + // This register aliases the CSR_EN bits for all channels + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 en; + + _REG_(PWM_INTR_OFFSET) // PWM_INTR + // Raw Interrupts + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intr; + + union { + struct { + _REG_(PWM_INTE_OFFSET) // PWM_INTE + // Interrupt Enable + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_INTF_OFFSET) // PWM_INTF + // Interrupt Force + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_INTS_OFFSET) // PWM_INTS + // Interrupt status after masking & forcing + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints; + }; + pwm_irq_ctrl_hw_t irq_ctrl[1]; + }; } pwm_hw_t; #define pwm_hw ((pwm_hw_t *)PWM_BASE) +static_assert(sizeof (pwm_hw_t) == 0x00b4, ""); -static_assert( NUM_PWM_SLICES == 8, ""); +#endif // _HARDWARE_STRUCTS_PWM_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/resets.h b/src/rp2040/hardware_structs/include/hardware/structs/resets.h index c27337cbf..ca3a62970 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/resets.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/resets.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_RESETS_H #define _HARDWARE_STRUCTS_RESETS_H +/** + * \file rp2040/resets.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/resets.h" @@ -18,99 +21,133 @@ // _REG_(x) will link to the corresponding register in hardware/regs/resets.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Resettable component numbers on RP2040 (used as typedef \ref reset_num_t) + * \ingroup hardware_resets + */ +typedef enum reset_num_rp2040 { + RESET_ADC = 0, ///< Select ADC to be reset + RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset + RESET_DMA = 2, ///< Select DMA to be reset + RESET_I2C0 = 3, ///< Select I2C0 to be reset + RESET_I2C1 = 4, ///< Select I2C1 to be reset + RESET_IO_BANK0 = 5, ///< Select IO_BANK0 to be reset + RESET_IO_QSPI = 6, ///< Select IO_QSPI to be reset + RESET_JTAG = 7, ///< Select JTAG to be reset + RESET_PADS_BANK0 = 8, ///< Select PADS_BANK0 to be reset + RESET_PADS_QSPI = 9, ///< Select PADS_QSPI to be reset + RESET_PIO0 = 10, ///< Select PIO0 to be reset + RESET_PIO1 = 11, ///< Select PIO1 to be reset + RESET_PLL_SYS = 12, ///< Select PLL_SYS to be reset + RESET_PLL_USB = 13, ///< Select PLL_USB to be reset + RESET_PWM = 14, ///< Select PWM to be reset + RESET_RTC = 15, ///< Select RTC to be reset + RESET_SPI0 = 16, ///< Select SPI0 to be reset + RESET_SPI1 = 17, ///< Select SPI1 to be reset + RESET_SYSCFG = 18, ///< Select SYSCFG to be reset + RESET_SYSINFO = 19, ///< Select SYSINFO to be reset + RESET_TBMAN = 20, ///< Select TBMAN to be reset + RESET_TIMER = 21, ///< Select TIMER to be reset + RESET_UART0 = 22, ///< Select UART0 to be reset + RESET_UART1 = 23, ///< Select UART1 to be reset + RESET_USBCTRL = 24, ///< Select USBCTRL to be reset + RESET_COUNT +} reset_num_t; /// \tag::resets_hw[] typedef struct { _REG_(RESETS_RESET_OFFSET) // RESETS_RESET - // Reset control - // 0x01000000 [24] : usbctrl (1) - // 0x00800000 [23] : uart1 (1) - // 0x00400000 [22] : uart0 (1) - // 0x00200000 [21] : timer (1) - // 0x00100000 [20] : tbman (1) - // 0x00080000 [19] : sysinfo (1) - // 0x00040000 [18] : syscfg (1) - // 0x00020000 [17] : spi1 (1) - // 0x00010000 [16] : spi0 (1) - // 0x00008000 [15] : rtc (1) - // 0x00004000 [14] : pwm (1) - // 0x00002000 [13] : pll_usb (1) - // 0x00001000 [12] : pll_sys (1) - // 0x00000800 [11] : pio1 (1) - // 0x00000400 [10] : pio0 (1) - // 0x00000200 [9] : pads_qspi (1) - // 0x00000100 [8] : pads_bank0 (1) - // 0x00000080 [7] : jtag (1) - // 0x00000040 [6] : io_qspi (1) - // 0x00000020 [5] : io_bank0 (1) - // 0x00000010 [4] : i2c1 (1) - // 0x00000008 [3] : i2c0 (1) - // 0x00000004 [2] : dma (1) - // 0x00000002 [1] : busctrl (1) - // 0x00000001 [0] : adc (1) + // Reset control. + // 0x01000000 [24] USBCTRL (1) + // 0x00800000 [23] UART1 (1) + // 0x00400000 [22] UART0 (1) + // 0x00200000 [21] TIMER (1) + // 0x00100000 [20] TBMAN (1) + // 0x00080000 [19] SYSINFO (1) + // 0x00040000 [18] SYSCFG (1) + // 0x00020000 [17] SPI1 (1) + // 0x00010000 [16] SPI0 (1) + // 0x00008000 [15] RTC (1) + // 0x00004000 [14] PWM (1) + // 0x00002000 [13] PLL_USB (1) + // 0x00001000 [12] PLL_SYS (1) + // 0x00000800 [11] PIO1 (1) + // 0x00000400 [10] PIO0 (1) + // 0x00000200 [9] PADS_QSPI (1) + // 0x00000100 [8] PADS_BANK0 (1) + // 0x00000080 [7] JTAG (1) + // 0x00000040 [6] IO_QSPI (1) + // 0x00000020 [5] IO_BANK0 (1) + // 0x00000010 [4] I2C1 (1) + // 0x00000008 [3] I2C0 (1) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] BUSCTRL (1) + // 0x00000001 [0] ADC (1) io_rw_32 reset; - + _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL - // Watchdog select - // 0x01000000 [24] : usbctrl (0) - // 0x00800000 [23] : uart1 (0) - // 0x00400000 [22] : uart0 (0) - // 0x00200000 [21] : timer (0) - // 0x00100000 [20] : tbman (0) - // 0x00080000 [19] : sysinfo (0) - // 0x00040000 [18] : syscfg (0) - // 0x00020000 [17] : spi1 (0) - // 0x00010000 [16] : spi0 (0) - // 0x00008000 [15] : rtc (0) - // 0x00004000 [14] : pwm (0) - // 0x00002000 [13] : pll_usb (0) - // 0x00001000 [12] : pll_sys (0) - // 0x00000800 [11] : pio1 (0) - // 0x00000400 [10] : pio0 (0) - // 0x00000200 [9] : pads_qspi (0) - // 0x00000100 [8] : pads_bank0 (0) - // 0x00000080 [7] : jtag (0) - // 0x00000040 [6] : io_qspi (0) - // 0x00000020 [5] : io_bank0 (0) - // 0x00000010 [4] : i2c1 (0) - // 0x00000008 [3] : i2c0 (0) - // 0x00000004 [2] : dma (0) - // 0x00000002 [1] : busctrl (0) - // 0x00000001 [0] : adc (0) + // Watchdog select. + // 0x01000000 [24] USBCTRL (0) + // 0x00800000 [23] UART1 (0) + // 0x00400000 [22] UART0 (0) + // 0x00200000 [21] TIMER (0) + // 0x00100000 [20] TBMAN (0) + // 0x00080000 [19] SYSINFO (0) + // 0x00040000 [18] SYSCFG (0) + // 0x00020000 [17] SPI1 (0) + // 0x00010000 [16] SPI0 (0) + // 0x00008000 [15] RTC (0) + // 0x00004000 [14] PWM (0) + // 0x00002000 [13] PLL_USB (0) + // 0x00001000 [12] PLL_SYS (0) + // 0x00000800 [11] PIO1 (0) + // 0x00000400 [10] PIO0 (0) + // 0x00000200 [9] PADS_QSPI (0) + // 0x00000100 [8] PADS_BANK0 (0) + // 0x00000080 [7] JTAG (0) + // 0x00000040 [6] IO_QSPI (0) + // 0x00000020 [5] IO_BANK0 (0) + // 0x00000010 [4] I2C1 (0) + // 0x00000008 [3] I2C0 (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) io_rw_32 wdsel; - + _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE - // Reset done - // 0x01000000 [24] : usbctrl (0) - // 0x00800000 [23] : uart1 (0) - // 0x00400000 [22] : uart0 (0) - // 0x00200000 [21] : timer (0) - // 0x00100000 [20] : tbman (0) - // 0x00080000 [19] : sysinfo (0) - // 0x00040000 [18] : syscfg (0) - // 0x00020000 [17] : spi1 (0) - // 0x00010000 [16] : spi0 (0) - // 0x00008000 [15] : rtc (0) - // 0x00004000 [14] : pwm (0) - // 0x00002000 [13] : pll_usb (0) - // 0x00001000 [12] : pll_sys (0) - // 0x00000800 [11] : pio1 (0) - // 0x00000400 [10] : pio0 (0) - // 0x00000200 [9] : pads_qspi (0) - // 0x00000100 [8] : pads_bank0 (0) - // 0x00000080 [7] : jtag (0) - // 0x00000040 [6] : io_qspi (0) - // 0x00000020 [5] : io_bank0 (0) - // 0x00000010 [4] : i2c1 (0) - // 0x00000008 [3] : i2c0 (0) - // 0x00000004 [2] : dma (0) - // 0x00000002 [1] : busctrl (0) - // 0x00000001 [0] : adc (0) + // Reset done. + // 0x01000000 [24] USBCTRL (0) + // 0x00800000 [23] UART1 (0) + // 0x00400000 [22] UART0 (0) + // 0x00200000 [21] TIMER (0) + // 0x00100000 [20] TBMAN (0) + // 0x00080000 [19] SYSINFO (0) + // 0x00040000 [18] SYSCFG (0) + // 0x00020000 [17] SPI1 (0) + // 0x00010000 [16] SPI0 (0) + // 0x00008000 [15] RTC (0) + // 0x00004000 [14] PWM (0) + // 0x00002000 [13] PLL_USB (0) + // 0x00001000 [12] PLL_SYS (0) + // 0x00000800 [11] PIO1 (0) + // 0x00000400 [10] PIO0 (0) + // 0x00000200 [9] PADS_QSPI (0) + // 0x00000100 [8] PADS_BANK0 (0) + // 0x00000080 [7] JTAG (0) + // 0x00000040 [6] IO_QSPI (0) + // 0x00000020 [5] IO_BANK0 (0) + // 0x00000010 [4] I2C1 (0) + // 0x00000008 [3] I2C0 (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) io_ro_32 reset_done; } resets_hw_t; +/// \end::resets_hw[] #define resets_hw ((resets_hw_t *)RESETS_BASE) -/// \end::resets_hw[] +static_assert(sizeof (resets_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_RESETS_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/rosc.h b/src/rp2040/hardware_structs/include/hardware/structs/rosc.h index 86fa04230..2bc82007b 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/rosc.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/rosc.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_ROSC_H #define _HARDWARE_STRUCTS_ROSC_H +/** + * \file rp2040/rosc.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/rosc.h" @@ -18,69 +21,72 @@ // _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL // Ring Oscillator control - // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE - // 0x00000fff [11:0] : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE + + // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring + io_rw_32 ctrl; - + _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA - // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings - // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength - // 0x00000700 [10:8] : DS2 (0): Stage 2 drive strength - // 0x00000070 [6:4] : DS1 (0): Stage 1 drive strength - // 0x00000007 [2:0] : DS0 (0): Stage 0 drive strength + // Ring Oscillator frequency control A + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength + // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength + // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength + // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength io_rw_32 freqa; - + _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB - // For a detailed description see freqa register - // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings - // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength - // 0x00000700 [10:8] : DS6 (0): Stage 6 drive strength - // 0x00000070 [6:4] : DS5 (0): Stage 5 drive strength - // 0x00000007 [2:0] : DS4 (0): Stage 4 drive strength + // Ring Oscillator frequency control B + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength + // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength + // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength + // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength io_rw_32 freqb; - + _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT // Ring Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC + io_rw_32 dormant; - + _REG_(ROSC_DIV_OFFSET) // ROSC_DIV // Controls the output divider - // 0x00000fff [11:0] : DIV (0): set to 0xaa0 + div where + // 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where + io_rw_32 div; - + _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE // Controls the phase shifted output - // 0x00000ff0 [11:4] : PASSWD (0): set to 0xaa - // 0x00000008 [3] : ENABLE (1): enable the phase-shifted output - // 0x00000004 [2] : FLIP (0): invert the phase-shifted output - // 0x00000003 [1:0] : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks + // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa + + // 0x00000008 [3] ENABLE (1) enable the phase-shifted output + + // 0x00000004 [2] FLIP (0) invert the phase-shifted output + + // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks + io_rw_32 phase; - + _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS // Ring Oscillator Status - // 0x80000000 [31] : STABLE (0): Oscillator is running and stable - // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or... - // 0x00010000 [16] : DIV_RUNNING (0): post-divider is running - // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00010000 [16] DIV_RUNNING (-) post-divider is running + + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable + io_rw_32 status; - + _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT - // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or... - // 0x00000001 [0] : RANDOMBIT (1) + // Returns a 1 bit random value + // 0x00000001 [0] RANDOMBIT (1) io_ro_32 randombit; - + _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT - // A down counter running at the ROSC frequency which counts to zero and stops - // 0x000000ff [7:0] : COUNT (0) + // A down counter running at the ROSC frequency which counts to zero and stops. + // 0x000000ff [7:0] COUNT (0x00) io_rw_32 count; } rosc_hw_t; #define rosc_hw ((rosc_hw_t *)ROSC_BASE) +static_assert(sizeof (rosc_hw_t) == 0x0024, ""); + +#endif // _HARDWARE_STRUCTS_ROSC_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/rtc.h b/src/rp2040/hardware_structs/include/hardware/structs/rtc.h index ccdb32614..6f35b682a 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/rtc.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/rtc.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_RTC_H #define _HARDWARE_STRUCTS_RTC_H +/** + * \file rp2040/rtc.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/rtc.h" @@ -18,97 +21,99 @@ // _REG_(x) will link to the corresponding register in hardware/regs/rtc.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1 // Divider minus 1 for the 1 second counter - // 0x0000ffff [15:0] : CLKDIV_M1 (0) + // 0x0000ffff [15:0] CLKDIV_M1 (0x0000) io_rw_32 clkdiv_m1; - + _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0 // RTC setup register 0 - // 0x00fff000 [23:12] : YEAR (0): Year - // 0x00000f00 [11:8] : MONTH (0): Month (1 - // 0x0000001f [4:0] : DAY (0): Day of the month (1 + // 0x00fff000 [23:12] YEAR (0x000) Year + // 0x00000f00 [11:8] MONTH (0x0) Month (1 + // 0x0000001f [4:0] DAY (0x00) Day of the month (1 io_rw_32 setup_0; - + _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1 // RTC setup register 1 - // 0x07000000 [26:24] : DOTW (0): Day of the week: 1-Monday - // 0x001f0000 [20:16] : HOUR (0): Hours - // 0x00003f00 [13:8] : MIN (0): Minutes - // 0x0000003f [5:0] : SEC (0): Seconds + // 0x07000000 [26:24] DOTW (0x0) Day of the week: 1-Monday + // 0x001f0000 [20:16] HOUR (0x00) Hours + // 0x00003f00 [13:8] MIN (0x00) Minutes + // 0x0000003f [5:0] SEC (0x00) Seconds io_rw_32 setup_1; - + _REG_(RTC_CTRL_OFFSET) // RTC_CTRL // RTC Control and status - // 0x00000100 [8] : FORCE_NOTLEAPYEAR (0): If set, leapyear is forced off - // 0x00000010 [4] : LOAD (0): Load RTC - // 0x00000002 [1] : RTC_ACTIVE (0): RTC enabled (running) - // 0x00000001 [0] : RTC_ENABLE (0): Enable RTC + // 0x00000100 [8] FORCE_NOTLEAPYEAR (0) If set, leapyear is forced off + // 0x00000010 [4] LOAD (0) Load RTC + // 0x00000002 [1] RTC_ACTIVE (-) RTC enabled (running) + // 0x00000001 [0] RTC_ENABLE (0) Enable RTC io_rw_32 ctrl; - + _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0 // Interrupt setup register 0 - // 0x20000000 [29] : MATCH_ACTIVE (0) - // 0x10000000 [28] : MATCH_ENA (0): Global match enable - // 0x04000000 [26] : YEAR_ENA (0): Enable year matching - // 0x02000000 [25] : MONTH_ENA (0): Enable month matching - // 0x01000000 [24] : DAY_ENA (0): Enable day matching - // 0x00fff000 [23:12] : YEAR (0): Year - // 0x00000f00 [11:8] : MONTH (0): Month (1 - // 0x0000001f [4:0] : DAY (0): Day of the month (1 + // 0x20000000 [29] MATCH_ACTIVE (-) + // 0x10000000 [28] MATCH_ENA (0) Global match enable + // 0x04000000 [26] YEAR_ENA (0) Enable year matching + // 0x02000000 [25] MONTH_ENA (0) Enable month matching + // 0x01000000 [24] DAY_ENA (0) Enable day matching + // 0x00fff000 [23:12] YEAR (0x000) Year + // 0x00000f00 [11:8] MONTH (0x0) Month (1 + // 0x0000001f [4:0] DAY (0x00) Day of the month (1 io_rw_32 irq_setup_0; - + _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1 // Interrupt setup register 1 - // 0x80000000 [31] : DOTW_ENA (0): Enable day of the week matching - // 0x40000000 [30] : HOUR_ENA (0): Enable hour matching - // 0x20000000 [29] : MIN_ENA (0): Enable minute matching - // 0x10000000 [28] : SEC_ENA (0): Enable second matching - // 0x07000000 [26:24] : DOTW (0): Day of the week - // 0x001f0000 [20:16] : HOUR (0): Hours - // 0x00003f00 [13:8] : MIN (0): Minutes - // 0x0000003f [5:0] : SEC (0): Seconds + // 0x80000000 [31] DOTW_ENA (0) Enable day of the week matching + // 0x40000000 [30] HOUR_ENA (0) Enable hour matching + // 0x20000000 [29] MIN_ENA (0) Enable minute matching + // 0x10000000 [28] SEC_ENA (0) Enable second matching + // 0x07000000 [26:24] DOTW (0x0) Day of the week + // 0x001f0000 [20:16] HOUR (0x00) Hours + // 0x00003f00 [13:8] MIN (0x00) Minutes + // 0x0000003f [5:0] SEC (0x00) Seconds io_rw_32 irq_setup_1; - + _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1 // RTC register 1 - // 0x00fff000 [23:12] : YEAR (0): Year - // 0x00000f00 [11:8] : MONTH (0): Month (1 - // 0x0000001f [4:0] : DAY (0): Day of the month (1 + // 0x00fff000 [23:12] YEAR (-) Year + // 0x00000f00 [11:8] MONTH (-) Month (1 + // 0x0000001f [4:0] DAY (-) Day of the month (1 io_ro_32 rtc_1; - + _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0 - // RTC register 0 - // 0x07000000 [26:24] : DOTW (0): Day of the week - // 0x001f0000 [20:16] : HOUR (0): Hours - // 0x00003f00 [13:8] : MIN (0): Minutes - // 0x0000003f [5:0] : SEC (0): Seconds + // RTC register 0 + + // 0x07000000 [26:24] DOTW (-) Day of the week + // 0x001f0000 [20:16] HOUR (-) Hours + // 0x00003f00 [13:8] MIN (-) Minutes + // 0x0000003f [5:0] SEC (-) Seconds io_ro_32 rtc_0; - + _REG_(RTC_INTR_OFFSET) // RTC_INTR // Raw Interrupts - // 0x00000001 [0] : RTC (0) + // 0x00000001 [0] RTC (0) io_ro_32 intr; - + _REG_(RTC_INTE_OFFSET) // RTC_INTE // Interrupt Enable - // 0x00000001 [0] : RTC (0) + // 0x00000001 [0] RTC (0) io_rw_32 inte; - + _REG_(RTC_INTF_OFFSET) // RTC_INTF // Interrupt Force - // 0x00000001 [0] : RTC (0) + // 0x00000001 [0] RTC (0) io_rw_32 intf; - + _REG_(RTC_INTS_OFFSET) // RTC_INTS // Interrupt status after masking & forcing - // 0x00000001 [0] : RTC (0) + // 0x00000001 [0] RTC (0) io_ro_32 ints; } rtc_hw_t; #define rtc_hw ((rtc_hw_t *)RTC_BASE) +static_assert(sizeof (rtc_hw_t) == 0x0030, ""); + +#endif // _HARDWARE_STRUCTS_RTC_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/scb.h b/src/rp2040/hardware_structs/include/hardware/structs/scb.h index 321441428..d4af74800 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/scb.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/scb.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_SCB_H #define _HARDWARE_STRUCTS_SCB_H +/** + * \file rp2040/scb.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" @@ -18,52 +21,54 @@ // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID - // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor... - // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM - // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status: - // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor: - // 0x0000fff0 [15:4] : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+ - // 0x0000000f [3:0] : REVISION (1): Minor revision number m in the rnpm revision status: + // CPUID Base Register + // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM + // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: + + // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: + + // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+ + // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: + io_ro_32 cpuid; - + _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR - // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending... - // 0x80000000 [31] : NMIPENDSET (0): Setting this bit will activate an NMI - // 0x10000000 [28] : PENDSVSET (0): PendSV set-pending bit - // 0x08000000 [27] : PENDSVCLR (0): PendSV clear-pending bit - // 0x04000000 [26] : PENDSTSET (0): SysTick exception set-pending bit - // 0x02000000 [25] : PENDSTCLR (0): SysTick exception clear-pending bit - // 0x00800000 [23] : ISRPREEMPT (0): The system can only access this bit when the core is halted - // 0x00400000 [22] : ISRPENDING (0): External interrupt pending flag - // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =... - // 0x000001ff [8:0] : VECTACTIVE (0): Active exception number field + // Interrupt Control and State Register + // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI + // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit + // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit + // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit + // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit + // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted + // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag + // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority... + // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field io_rw_32 icsr; - + _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR - // The VTOR holds the vector table offset address - // 0xffffff00 [31:8] : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address + // Vector Table Offset Register + // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address io_rw_32 vtor; - + _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR - // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state... - // 0xffff0000 [31:16] : VECTKEY (0): Register key: - // 0x00008000 [15] : ENDIANESS (0): Data endianness implemented: - // 0x00000004 [2] : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be... - // 0x00000002 [1] : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... io_rw_32 aircr; - + _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR // System Control Register - // 0x00000010 [4] : SEVONPEND (0): Send Event on Pending bit: - // 0x00000004 [2] : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode: - // 0x00000002 [1] : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode: + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... io_rw_32 scr; -} armv6m_scb_t; +} armv6m_scb_hw_t; + +#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET)) +static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, ""); -#define scb_hw ((armv6m_scb_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET)) +#endif // _HARDWARE_STRUCTS_SCB_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/sio.h b/src/rp2040/hardware_structs/include/hardware/structs/sio.h index 251dd30bb..412a7d868 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/sio.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/sio.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_SIO_H #define _HARDWARE_STRUCTS_SIO_H +/** + * \file rp2040/sio.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/sio.h" #include "hardware/structs/interp.h" @@ -19,158 +22,179 @@ // _REG_(x) will link to the corresponding register in hardware/regs/sio.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + typedef struct { _REG_(SIO_CPUID_OFFSET) // SIO_CPUID // Processor core identifier + // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... io_ro_32 cpuid; - + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN // Input value for GPIO pins - // 0x3fffffff [29:0] : GPIO_IN (0): Input value for GPIO0 + // 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0 io_ro_32 gpio_in; - + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN // Input value for QSPI pins - // 0x0000003f [5:0] : GPIO_HI_IN (0): Input value on QSPI IO in order 0 + // 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0 io_ro_32 gpio_hi_in; - + uint32_t _pad0; - + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT // GPIO output value - // 0x3fffffff [29:0] : GPIO_OUT (0): Set output level (1/0 -> high/low) for GPIO0 + // 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 io_rw_32 gpio_out; - + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET // GPIO output value set - // 0x3fffffff [29:0] : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i + // 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i io_wo_32 gpio_set; - + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR // GPIO output value clear - // 0x3fffffff [29:0] : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i + // 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i io_wo_32 gpio_clr; - + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR // GPIO output value XOR - // 0x3fffffff [29:0] : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i + // 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i io_wo_32 gpio_togl; - + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE // GPIO output enable - // 0x3fffffff [29:0] : GPIO_OE (0): Set output enable (1/0 -> output/input) for GPIO0 + // 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 io_rw_32 gpio_oe; - + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET // GPIO output enable set - // 0x3fffffff [29:0] : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i + // 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i io_wo_32 gpio_oe_set; - + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR // GPIO output enable clear - // 0x3fffffff [29:0] : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i + // 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i io_wo_32 gpio_oe_clr; - + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR // GPIO output enable XOR - // 0x3fffffff [29:0] : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i + // 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i io_wo_32 gpio_oe_togl; - + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT // QSPI output value - // 0x0000003f [5:0] : GPIO_HI_OUT (0): Set output level (1/0 -> high/low) for QSPI IO0 + // 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0 io_rw_32 gpio_hi_out; - + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET // QSPI output value set - // 0x0000003f [5:0] : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i + // 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i io_wo_32 gpio_hi_set; - + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR // QSPI output value clear - // 0x0000003f [5:0] : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i + // 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i io_wo_32 gpio_hi_clr; - + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR // QSPI output value XOR - // 0x0000003f [5:0] : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i + // 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i io_wo_32 gpio_hi_togl; - + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE // QSPI output enable - // 0x0000003f [5:0] : GPIO_HI_OE (0): Set output enable (1/0 -> output/input) for QSPI IO0 + // 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0 io_rw_32 gpio_hi_oe; - + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET // QSPI output enable set - // 0x0000003f [5:0] : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i + // 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_set; - + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR // QSPI output enable clear - // 0x0000003f [5:0] : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i + // 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_clr; - + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR // QSPI output enable XOR - // 0x0000003f [5:0] : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i + // 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i io_wo_32 gpio_hi_oe_togl; - + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST - // Status register for inter-core FIFOs (mailboxes) - // 0x00000008 [3] : ROE (0): Sticky flag indicating the RX FIFO was read when empty - // 0x00000004 [2] : WOF (0): Sticky flag indicating the TX FIFO was written when full - // 0x00000002 [1] : RDY (1): Value is 1 if this core's TX FIFO is not full (i - // 0x00000001 [0] : VLD (0): Value is 1 if this core's RX FIFO is not empty (i + // Status register for inter-core FIFOs (mailboxes). + // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i io_rw_32 fifo_st; - + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR // Write access to this core's TX FIFO + // 0xffffffff [31:0] FIFO_WR (0x00000000) io_wo_32 fifo_wr; - + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD // Read access to this core's RX FIFO + // 0xffffffff [31:0] FIFO_RD (-) io_ro_32 fifo_rd; - + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST // Spinlock state + // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) io_ro_32 spinlock_st; - + _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND // Divider unsigned dividend + // 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000) io_rw_32 div_udividend; - + _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR // Divider unsigned divisor + // 0xffffffff [31:0] DIV_UDIVISOR (0x00000000) io_rw_32 div_udivisor; - + _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND // Divider signed dividend + // 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000) io_rw_32 div_sdividend; - + _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR // Divider signed divisor + // 0xffffffff [31:0] DIV_SDIVISOR (0x00000000) io_rw_32 div_sdivisor; - + _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT // Divider result quotient + // 0xffffffff [31:0] DIV_QUOTIENT (0x00000000) io_rw_32 div_quotient; - + _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER // Divider result remainder + // 0xffffffff [31:0] DIV_REMAINDER (0x00000000) io_rw_32 div_remainder; - + _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR // Control and status register for divider - // 0x00000002 [1] : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read - // 0x00000001 [0] : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise + // 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0... + // 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise io_ro_32 div_csr; + uint32_t _pad1; + interp_hw_t interp[2]; + + // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) + _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 + // Spinlock register 0 + // 0xffffffff [31:0] SPINLOCK0 (0x00000000) + io_rw_32 spinlock[32]; } sio_hw_t; #define sio_hw ((sio_hw_t *)SIO_BASE) +static_assert(sizeof (sio_hw_t) == 0x0180, ""); + +#endif // _HARDWARE_STRUCTS_SIO_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/spi.h b/src/rp2040/hardware_structs/include/hardware/structs/spi.h index 08243c09f..7d1956e91 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/spi.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/spi.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_SPI_H #define _HARDWARE_STRUCTS_SPI_H +/** + * \file rp2040/spi.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/spi.h" @@ -18,83 +21,85 @@ // _REG_(x) will link to the corresponding register in hardware/regs/spi.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 // Control register 0, SSPCR0 on page 3-4 - // 0x0000ff00 [15:8] : SCR (0): Serial clock rate - // 0x00000080 [7] : SPH (0): SSPCLKOUT phase, applicable to Motorola SPI frame format only - // 0x00000040 [6] : SPO (0): SSPCLKOUT polarity, applicable to Motorola SPI frame format only - // 0x00000030 [5:4] : FRF (0): Frame format: 00 Motorola SPI frame format - // 0x0000000f [3:0] : DSS (0): Data Size Select: 0000 Reserved, undefined operation + // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate + // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only + // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format + // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation io_rw_32 cr0; - + _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 // Control register 1, SSPCR1 on page 3-5 - // 0x00000008 [3] : SOD (0): Slave-mode output disable - // 0x00000004 [2] : MS (0): Master or slave mode select - // 0x00000002 [1] : SSE (0): Synchronous serial port enable: 0 SSP operation disabled - // 0x00000001 [0] : LBM (0): Loop back mode: 0 Normal serial port operation enabled + // 0x00000008 [3] SOD (0) Slave-mode output disable + // 0x00000004 [2] MS (0) Master or slave mode select + // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled + // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled io_rw_32 cr1; - + _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR // Data register, SSPDR on page 3-6 - // 0x0000ffff [15:0] : DATA (0): Transmit/Receive FIFO: Read Receive FIFO + // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO io_rw_32 dr; - + _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR // Status register, SSPSR on page 3-7 - // 0x00000010 [4] : BSY (0): PrimeCell SSP busy flag, RO: 0 SSP is idle - // 0x00000008 [3] : RFF (0): Receive FIFO full, RO: 0 Receive FIFO is not full - // 0x00000004 [2] : RNE (0): Receive FIFO not empty, RO: 0 Receive FIFO is empty - // 0x00000002 [1] : TNF (1): Transmit FIFO not full, RO: 0 Transmit FIFO is full - // 0x00000001 [0] : TFE (1): Transmit FIFO empty, RO: 0 Transmit FIFO is not empty + // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle + // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full + // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty + // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full + // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty io_ro_32 sr; - + _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR // Clock prescale register, SSPCPSR on page 3-8 - // 0x000000ff [7:0] : CPSDVSR (0): Clock prescale divisor + // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor io_rw_32 cpsr; - + _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC // Interrupt mask set or clear register, SSPIMSC on page 3-9 - // 0x00000008 [3] : TXIM (0): Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked - // 0x00000004 [2] : RXIM (0): Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked - // 0x00000002 [1] : RTIM (0): Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout... - // 0x00000001 [0] : RORIM (0): Receive overrun interrupt mask: 0 Receive FIFO written to while full condition... + // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty... + // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or... + // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty... + // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written... io_rw_32 imsc; - + _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS // Raw interrupt status register, SSPRIS on page 3-10 - // 0x00000008 [3] : TXRIS (1): Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt - // 0x00000004 [2] : RXRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt - // 0x00000002 [1] : RTRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt - // 0x00000001 [0] : RORRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the... + // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the... io_ro_32 ris; - + _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS // Masked interrupt status register, SSPMIS on page 3-11 - // 0x00000008 [3] : TXMIS (0): Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt - // 0x00000004 [2] : RXMIS (0): Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt - // 0x00000002 [1] : RTMIS (0): Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt - // 0x00000001 [0] : RORMIS (0): Gives the receive over run masked interrupt status, after masking, of the... + // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after... + // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after... + // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after... + // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,... io_ro_32 mis; - + _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR // Interrupt clear register, SSPICR on page 3-11 - // 0x00000002 [1] : RTIC (0): Clears the SSPRTINTR interrupt - // 0x00000001 [0] : RORIC (0): Clears the SSPRORINTR interrupt + // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt + // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt io_rw_32 icr; - + _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR // DMA control register, SSPDMACR on page 3-12 - // 0x00000002 [1] : TXDMAE (0): Transmit DMA Enable - // 0x00000001 [0] : RXDMAE (0): Receive DMA Enable + // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RXDMAE (0) Receive DMA Enable io_rw_32 dmacr; } spi_hw_t; #define spi0_hw ((spi_hw_t *)SPI0_BASE) #define spi1_hw ((spi_hw_t *)SPI1_BASE) +static_assert(sizeof (spi_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SPI_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/ssi.h b/src/rp2040/hardware_structs/include/hardware/structs/ssi.h index 639bd64f9..9d5fdace6 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/ssi.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/ssi.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_SSI_H #define _HARDWARE_STRUCTS_SSI_H +/** + * \file rp2040/ssi.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/ssi.h" @@ -18,193 +21,195 @@ // _REG_(x) will link to the corresponding register in hardware/regs/ssi.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0 // Control register 0 - // 0x01000000 [24] : SSTE (0): Slave select toggle enable - // 0x00600000 [22:21] : SPI_FRF (0): SPI frame format - // 0x001f0000 [20:16] : DFS_32 (0): Data frame size in 32b transfer mode - // 0x0000f000 [15:12] : CFS (0): Control frame size - // 0x00000800 [11] : SRL (0): Shift register loop (test mode) - // 0x00000400 [10] : SLV_OE (0): Slave output enable - // 0x00000300 [9:8] : TMOD (0): Transfer mode - // 0x00000080 [7] : SCPOL (0): Serial clock polarity - // 0x00000040 [6] : SCPH (0): Serial clock phase - // 0x00000030 [5:4] : FRF (0): Frame format - // 0x0000000f [3:0] : DFS (0): Data frame size + // 0x01000000 [24] SSTE (0) Slave select toggle enable + // 0x00600000 [22:21] SPI_FRF (0x0) SPI frame format + // 0x001f0000 [20:16] DFS_32 (0x00) Data frame size in 32b transfer mode + + // 0x0000f000 [15:12] CFS (0x0) Control frame size + + // 0x00000800 [11] SRL (0) Shift register loop (test mode) + // 0x00000400 [10] SLV_OE (0) Slave output enable + // 0x00000300 [9:8] TMOD (0x0) Transfer mode + // 0x00000080 [7] SCPOL (0) Serial clock polarity + // 0x00000040 [6] SCPH (0) Serial clock phase + // 0x00000030 [5:4] FRF (0x0) Frame format + // 0x0000000f [3:0] DFS (0x0) Data frame size io_rw_32 ctrlr0; - + _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1 // Master Control register 1 - // 0x0000ffff [15:0] : NDF (0): Number of data frames + // 0x0000ffff [15:0] NDF (0x0000) Number of data frames io_rw_32 ctrlr1; - + _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR // SSI Enable - // 0x00000001 [0] : SSI_EN (0): SSI enable + // 0x00000001 [0] SSI_EN (0) SSI enable io_rw_32 ssienr; - + _REG_(SSI_MWCR_OFFSET) // SSI_MWCR // Microwire Control - // 0x00000004 [2] : MHS (0): Microwire handshaking - // 0x00000002 [1] : MDD (0): Microwire control - // 0x00000001 [0] : MWMOD (0): Microwire transfer mode + // 0x00000004 [2] MHS (0) Microwire handshaking + // 0x00000002 [1] MDD (0) Microwire control + // 0x00000001 [0] MWMOD (0) Microwire transfer mode io_rw_32 mwcr; - + _REG_(SSI_SER_OFFSET) // SSI_SER // Slave enable - // 0x00000001 [0] : SER (0): For each bit: + // 0x00000001 [0] SER (0) For each bit: + io_rw_32 ser; - + _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR // Baud rate - // 0x0000ffff [15:0] : SCKDV (0): SSI clock divider + // 0x0000ffff [15:0] SCKDV (0x0000) SSI clock divider io_rw_32 baudr; - + _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR // TX FIFO threshold level - // 0x000000ff [7:0] : TFT (0): Transmit FIFO threshold + // 0x000000ff [7:0] TFT (0x00) Transmit FIFO threshold io_rw_32 txftlr; - + _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR // RX FIFO threshold level - // 0x000000ff [7:0] : RFT (0): Receive FIFO threshold + // 0x000000ff [7:0] RFT (0x00) Receive FIFO threshold io_rw_32 rxftlr; - + _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR // TX FIFO level - // 0x000000ff [7:0] : TFTFL (0): Transmit FIFO level + // 0x000000ff [7:0] TFTFL (0x00) Transmit FIFO level io_ro_32 txflr; - + _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR // RX FIFO level - // 0x000000ff [7:0] : RXTFL (0): Receive FIFO level + // 0x000000ff [7:0] RXTFL (0x00) Receive FIFO level io_ro_32 rxflr; - + _REG_(SSI_SR_OFFSET) // SSI_SR // Status register - // 0x00000040 [6] : DCOL (0): Data collision error - // 0x00000020 [5] : TXE (0): Transmission error - // 0x00000010 [4] : RFF (0): Receive FIFO full - // 0x00000008 [3] : RFNE (0): Receive FIFO not empty - // 0x00000004 [2] : TFE (0): Transmit FIFO empty - // 0x00000002 [1] : TFNF (0): Transmit FIFO not full - // 0x00000001 [0] : BUSY (0): SSI busy flag + // 0x00000040 [6] DCOL (0) Data collision error + // 0x00000020 [5] TXE (0) Transmission error + // 0x00000010 [4] RFF (0) Receive FIFO full + // 0x00000008 [3] RFNE (0) Receive FIFO not empty + // 0x00000004 [2] TFE (0) Transmit FIFO empty + // 0x00000002 [1] TFNF (0) Transmit FIFO not full + // 0x00000001 [0] BUSY (0) SSI busy flag io_ro_32 sr; - + _REG_(SSI_IMR_OFFSET) // SSI_IMR // Interrupt mask - // 0x00000020 [5] : MSTIM (0): Multi-master contention interrupt mask - // 0x00000010 [4] : RXFIM (0): Receive FIFO full interrupt mask - // 0x00000008 [3] : RXOIM (0): Receive FIFO overflow interrupt mask - // 0x00000004 [2] : RXUIM (0): Receive FIFO underflow interrupt mask - // 0x00000002 [1] : TXOIM (0): Transmit FIFO overflow interrupt mask - // 0x00000001 [0] : TXEIM (0): Transmit FIFO empty interrupt mask + // 0x00000020 [5] MSTIM (0) Multi-master contention interrupt mask + // 0x00000010 [4] RXFIM (0) Receive FIFO full interrupt mask + // 0x00000008 [3] RXOIM (0) Receive FIFO overflow interrupt mask + // 0x00000004 [2] RXUIM (0) Receive FIFO underflow interrupt mask + // 0x00000002 [1] TXOIM (0) Transmit FIFO overflow interrupt mask + // 0x00000001 [0] TXEIM (0) Transmit FIFO empty interrupt mask io_rw_32 imr; - + _REG_(SSI_ISR_OFFSET) // SSI_ISR // Interrupt status - // 0x00000020 [5] : MSTIS (0): Multi-master contention interrupt status - // 0x00000010 [4] : RXFIS (0): Receive FIFO full interrupt status - // 0x00000008 [3] : RXOIS (0): Receive FIFO overflow interrupt status - // 0x00000004 [2] : RXUIS (0): Receive FIFO underflow interrupt status - // 0x00000002 [1] : TXOIS (0): Transmit FIFO overflow interrupt status - // 0x00000001 [0] : TXEIS (0): Transmit FIFO empty interrupt status + // 0x00000020 [5] MSTIS (0) Multi-master contention interrupt status + // 0x00000010 [4] RXFIS (0) Receive FIFO full interrupt status + // 0x00000008 [3] RXOIS (0) Receive FIFO overflow interrupt status + // 0x00000004 [2] RXUIS (0) Receive FIFO underflow interrupt status + // 0x00000002 [1] TXOIS (0) Transmit FIFO overflow interrupt status + // 0x00000001 [0] TXEIS (0) Transmit FIFO empty interrupt status io_ro_32 isr; - + _REG_(SSI_RISR_OFFSET) // SSI_RISR // Raw interrupt status - // 0x00000020 [5] : MSTIR (0): Multi-master contention raw interrupt status - // 0x00000010 [4] : RXFIR (0): Receive FIFO full raw interrupt status - // 0x00000008 [3] : RXOIR (0): Receive FIFO overflow raw interrupt status - // 0x00000004 [2] : RXUIR (0): Receive FIFO underflow raw interrupt status - // 0x00000002 [1] : TXOIR (0): Transmit FIFO overflow raw interrupt status - // 0x00000001 [0] : TXEIR (0): Transmit FIFO empty raw interrupt status + // 0x00000020 [5] MSTIR (0) Multi-master contention raw interrupt status + // 0x00000010 [4] RXFIR (0) Receive FIFO full raw interrupt status + // 0x00000008 [3] RXOIR (0) Receive FIFO overflow raw interrupt status + // 0x00000004 [2] RXUIR (0) Receive FIFO underflow raw interrupt status + // 0x00000002 [1] TXOIR (0) Transmit FIFO overflow raw interrupt status + // 0x00000001 [0] TXEIR (0) Transmit FIFO empty raw interrupt status io_ro_32 risr; - + _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR // TX FIFO overflow interrupt clear - // 0x00000001 [0] : TXOICR (0): Clear-on-read transmit FIFO overflow interrupt + // 0x00000001 [0] TXOICR (0) Clear-on-read transmit FIFO overflow interrupt io_ro_32 txoicr; - + _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR // RX FIFO overflow interrupt clear - // 0x00000001 [0] : RXOICR (0): Clear-on-read receive FIFO overflow interrupt + // 0x00000001 [0] RXOICR (0) Clear-on-read receive FIFO overflow interrupt io_ro_32 rxoicr; - + _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR // RX FIFO underflow interrupt clear - // 0x00000001 [0] : RXUICR (0): Clear-on-read receive FIFO underflow interrupt + // 0x00000001 [0] RXUICR (0) Clear-on-read receive FIFO underflow interrupt io_ro_32 rxuicr; - + _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR // Multi-master interrupt clear - // 0x00000001 [0] : MSTICR (0): Clear-on-read multi-master contention interrupt + // 0x00000001 [0] MSTICR (0) Clear-on-read multi-master contention interrupt io_ro_32 msticr; - + _REG_(SSI_ICR_OFFSET) // SSI_ICR // Interrupt clear - // 0x00000001 [0] : ICR (0): Clear-on-read all active interrupts + // 0x00000001 [0] ICR (0) Clear-on-read all active interrupts io_ro_32 icr; - + _REG_(SSI_DMACR_OFFSET) // SSI_DMACR // DMA control - // 0x00000002 [1] : TDMAE (0): Transmit DMA enable - // 0x00000001 [0] : RDMAE (0): Receive DMA enable + // 0x00000002 [1] TDMAE (0) Transmit DMA enable + // 0x00000001 [0] RDMAE (0) Receive DMA enable io_rw_32 dmacr; - + _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR // DMA TX data level - // 0x000000ff [7:0] : DMATDL (0): Transmit data watermark level + // 0x000000ff [7:0] DMATDL (0x00) Transmit data watermark level io_rw_32 dmatdlr; - + _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR // DMA RX data level - // 0x000000ff [7:0] : DMARDL (0): Receive data watermark level (DMARDLR+1) + // 0x000000ff [7:0] DMARDL (0x00) Receive data watermark level (DMARDLR+1) io_rw_32 dmardlr; - + _REG_(SSI_IDR_OFFSET) // SSI_IDR // Identification register - // 0xffffffff [31:0] : IDCODE (0x51535049): Peripheral dentification code + // 0xffffffff [31:0] IDCODE (0x51535049) Peripheral dentification code io_ro_32 idr; - + _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID // Version ID - // 0xffffffff [31:0] : SSI_COMP_VERSION (0x3430312a): SNPS component version (format X + // 0xffffffff [31:0] SSI_COMP_VERSION (0x3430312a) SNPS component version (format X io_ro_32 ssi_version_id; - + _REG_(SSI_DR0_OFFSET) // SSI_DR0 // Data Register 0 (of 36) - // 0xffffffff [31:0] : DR (0): First data register of 36 + // 0xffffffff [31:0] DR (0x00000000) First data register of 36 io_rw_32 dr0; - + uint32_t _pad0[35]; - + _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY // RX sample delay - // 0x000000ff [7:0] : RSD (0): RXD sample delay (in SCLK cycles) + // 0x000000ff [7:0] RSD (0x00) RXD sample delay (in SCLK cycles) io_rw_32 rx_sample_dly; - + _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0 // SPI control - // 0xff000000 [31:24] : XIP_CMD (0x3): SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) - // 0x00040000 [18] : SPI_RXDS_EN (0): Read data strobe enable - // 0x00020000 [17] : INST_DDR_EN (0): Instruction DDR transfer enable - // 0x00010000 [16] : SPI_DDR_EN (0): SPI DDR transfer enable - // 0x0000f800 [15:11] : WAIT_CYCLES (0): Wait cycles between control frame transmit and data reception (in SCLK cycles) - // 0x00000300 [9:8] : INST_L (0): Instruction length (0/4/8/16b) - // 0x0000003c [5:2] : ADDR_L (0): Address length (0b-60b in 4b increments) - // 0x00000003 [1:0] : TRANS_TYPE (0): Address and instruction transfer format + // 0xff000000 [31:24] XIP_CMD (0x03) SPI Command to send in XIP mode (INST_L = 8-bit) or to... + // 0x00040000 [18] SPI_RXDS_EN (0) Read data strobe enable + // 0x00020000 [17] INST_DDR_EN (0) Instruction DDR transfer enable + // 0x00010000 [16] SPI_DDR_EN (0) SPI DDR transfer enable + // 0x0000f800 [15:11] WAIT_CYCLES (0x00) Wait cycles between control frame transmit and data... + // 0x00000300 [9:8] INST_L (0x0) Instruction length (0/4/8/16b) + // 0x0000003c [5:2] ADDR_L (0x0) Address length (0b-60b in 4b increments) + // 0x00000003 [1:0] TRANS_TYPE (0x0) Address and instruction transfer format io_rw_32 spi_ctrlr0; - + _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE // TX drive edge - // 0x000000ff [7:0] : TDE (0): TXD drive edge + // 0x000000ff [7:0] TDE (0x00) TXD drive edge io_rw_32 txd_drive_edge; } ssi_hw_t; #define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE) +static_assert(sizeof (ssi_hw_t) == 0x00fc, ""); + +#endif // _HARDWARE_STRUCTS_SSI_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h b/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h index e89052109..1d63dc75f 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/syscfg.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_SYSCFG_H #define _HARDWARE_STRUCTS_SYSCFG_H +/** + * \file rp2040/syscfg.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/syscfg.h" @@ -18,60 +21,64 @@ // _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK // Processor core 0 NMI source mask + // 0xffffffff [31:0] PROC0_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ io_rw_32 proc0_nmi_mask; - + _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK // Processor core 1 NMI source mask + // 0xffffffff [31:0] PROC1_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ io_rw_32 proc1_nmi_mask; - + _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG // Configuration for processors - // 0xf0000000 [31:28] : PROC1_DAP_INSTID (1): Configure proc1 DAP instance ID - // 0x0f000000 [27:24] : PROC0_DAP_INSTID (0): Configure proc0 DAP instance ID - // 0x00000002 [1] : PROC1_HALTED (0): Indication that proc1 has halted - // 0x00000001 [0] : PROC0_HALTED (0): Indication that proc0 has halted + // 0xf0000000 [31:28] PROC1_DAP_INSTID (0x1) Configure proc1 DAP instance ID + // 0x0f000000 [27:24] PROC0_DAP_INSTID (0x0) Configure proc0 DAP instance ID + // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted + // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted io_rw_32 proc_config; - + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS - // For each bit, if 1, bypass the input synchronizer between that GPIO - // 0x3fffffff [29:0] : PROC_IN_SYNC_BYPASS (0) + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0x3fffffff [29:0] PROC_IN_SYNC_BYPASS (0x00000000) io_rw_32 proc_in_sync_bypass; - + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI - // For each bit, if 1, bypass the input synchronizer between that GPIO - // 0x0000003f [5:0] : PROC_IN_SYNC_BYPASS_HI (0) + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0x0000003f [5:0] PROC_IN_SYNC_BYPASS_HI (0x00) io_rw_32 proc_in_sync_bypass_hi; - + _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE // Directly control the SWD debug port of either processor - // 0x00000080 [7] : PROC1_ATTACH (0): Attach processor 1 debug port to syscfg controls, and disconnect it from... - // 0x00000040 [6] : PROC1_SWCLK (1): Directly drive processor 1 SWCLK, if PROC1_ATTACH is set - // 0x00000020 [5] : PROC1_SWDI (1): Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set - // 0x00000010 [4] : PROC1_SWDO (0): Observe the value of processor 1 SWDIO output - // 0x00000008 [3] : PROC0_ATTACH (0): Attach processor 0 debug port to syscfg controls, and disconnect it from... - // 0x00000004 [2] : PROC0_SWCLK (1): Directly drive processor 0 SWCLK, if PROC0_ATTACH is set - // 0x00000002 [1] : PROC0_SWDI (1): Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set - // 0x00000001 [0] : PROC0_SWDO (0): Observe the value of processor 0 SWDIO output + // 0x00000080 [7] PROC1_ATTACH (0) Attach processor 1 debug port to syscfg controls, and... + // 0x00000040 [6] PROC1_SWCLK (1) Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + // 0x00000020 [5] PROC1_SWDI (1) Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + // 0x00000010 [4] PROC1_SWDO (-) Observe the value of processor 1 SWDIO output + // 0x00000008 [3] PROC0_ATTACH (0) Attach processor 0 debug port to syscfg controls, and... + // 0x00000004 [2] PROC0_SWCLK (1) Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + // 0x00000002 [1] PROC0_SWDI (1) Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + // 0x00000001 [0] PROC0_SWDO (-) Observe the value of processor 0 SWDIO output io_rw_32 dbgforce; - + _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN // Control power downs to memories - // 0x00000080 [7] : ROM (0) - // 0x00000040 [6] : USB (0) - // 0x00000020 [5] : SRAM5 (0) - // 0x00000010 [4] : SRAM4 (0) - // 0x00000008 [3] : SRAM3 (0) - // 0x00000004 [2] : SRAM2 (0) - // 0x00000002 [1] : SRAM1 (0) - // 0x00000001 [0] : SRAM0 (0) + // 0x00000080 [7] ROM (0) + // 0x00000040 [6] USB (0) + // 0x00000020 [5] SRAM5 (0) + // 0x00000010 [4] SRAM4 (0) + // 0x00000008 [3] SRAM3 (0) + // 0x00000004 [2] SRAM2 (0) + // 0x00000002 [1] SRAM1 (0) + // 0x00000001 [0] SRAM0 (0) io_rw_32 mempowerdown; } syscfg_hw_t; #define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) +static_assert(sizeof (syscfg_hw_t) == 0x001c, ""); + +#endif // _HARDWARE_STRUCTS_SYSCFG_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/sysinfo.h b/src/rp2040/hardware_structs/include/hardware/structs/sysinfo.h new file mode 100644 index 000000000..6c0502f6e --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/sysinfo.h @@ -0,0 +1,52 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSINFO_H +#define _HARDWARE_STRUCTS_SYSINFO_H + +/** + * \file rp2040/sysinfo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sysinfo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sysinfo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID + // JEDEC JEP-106 compliant chip identifier + // 0xf0000000 [31:28] REVISION (-) + // 0x0ffff000 [27:12] PART (-) + // 0x00000fff [11:0] MANUFACTURER (-) + io_ro_32 chip_id; + + _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM + // Platform register + // 0x00000002 [1] ASIC (0) + // 0x00000001 [0] FPGA (0) + io_ro_32 platform; + + uint32_t _pad0[2]; + + _REG_(SYSINFO_GITREF_RP2040_OFFSET) // SYSINFO_GITREF_RP2040 + // Git hash of the chip source + // 0xffffffff [31:0] GITREF_RP2040 (-) + io_ro_32 gitref_rp2040; +} sysinfo_hw_t; + +#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) +static_assert(sizeof (sysinfo_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_SYSINFO_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/systick.h b/src/rp2040/hardware_structs/include/hardware/structs/systick.h index b57a74026..ee878719b 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/systick.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/systick.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_SYSTICK_H #define _HARDWARE_STRUCTS_SYSTICK_H +/** + * \file rp2040/systick.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/m0plus.h" @@ -18,35 +21,37 @@ // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR - // Use the SysTick Control and Status Register to enable the SysTick features - // 0x00010000 [16] : COUNTFLAG (0): Returns 1 if timer counted to 0 since last time this was read - // 0x00000004 [2] : CLKSOURCE (0): SysTick clock source - // 0x00000002 [1] : TICKINT (0): Enables SysTick exception request: - // 0x00000001 [0] : ENABLE (0): Enable SysTick counter: + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + io_rw_32 csr; - + _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR - // Use the SysTick Reload Value Register to specify the start value to load into the current value register when the... - // 0x00ffffff [23:0] : RELOAD (0): Value to load into the SysTick Current Value Register when the counter reaches 0 + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... io_rw_32 rvr; - + _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR - // Use the SysTick Current Value Register to find the current value in the register - // 0x00ffffff [23:0] : CURRENT (0): Reads return the current value of the SysTick counter + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter io_rw_32 cvr; - + _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB - // Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply - // 0x80000000 [31] : NOREF (0): If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the... - // 0x40000000 [30] : SKEW (0): If reads as 1, the calibration value for 10ms is inexact (due to clock frequency) - // 0x00ffffff [23:0] : TENMS (0): An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock... + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... io_ro_32 calib; } systick_hw_t; #define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET)) +static_assert(sizeof (systick_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_SYSTICK_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/tbman.h b/src/rp2040/hardware_structs/include/hardware/structs/tbman.h new file mode 100644 index 000000000..78a5f3b22 --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/tbman.h @@ -0,0 +1,38 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TBMAN_H +#define _HARDWARE_STRUCTS_TBMAN_H + +/** + * \file rp2040/tbman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/tbman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_tbman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM + // Indicates the type of platform in use + // 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA + // 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC + io_ro_32 platform; +} tbman_hw_t; + +#define tbman_hw ((tbman_hw_t *)TBMAN_BASE) +static_assert(sizeof (tbman_hw_t) == 0x0004, ""); + +#endif // _HARDWARE_STRUCTS_TBMAN_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/timer.h b/src/rp2040/hardware_structs/include/hardware/structs/timer.h index 7622f131e..1b059ad56 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/timer.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/timer.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_TIMER_H #define _HARDWARE_STRUCTS_TIMER_H +/** + * \file rp2040/timer.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/timer.h" @@ -18,90 +21,96 @@ // _REG_(x) will link to the corresponding register in hardware/regs/timer.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW - // Write to bits 63:32 of time + // Write to bits 63:32 of time + + // 0xffffffff [31:0] TIMEHW (0x00000000) io_wo_32 timehw; - + _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW - // Write to bits 31:0 of time + // Write to bits 31:0 of time + + // 0xffffffff [31:0] TIMELW (0x00000000) io_wo_32 timelw; - + _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR - // Read from bits 63:32 of time + // Read from bits 63:32 of time + + // 0xffffffff [31:0] TIMEHR (0x00000000) io_ro_32 timehr; - + _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR // Read from bits 31:0 of time + // 0xffffffff [31:0] TIMELR (0x00000000) io_ro_32 timelr; - - _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 + // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) - // + _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 // Arm alarm 0, and configure the time it will fire - io_rw_32 alarm[NUM_TIMERS]; // 4 - + // 0xffffffff [31:0] ALARM0 (0x00000000) + io_rw_32 alarm[4]; + _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED // Indicates the armed/disarmed status of each alarm - // 0x0000000f [3:0] : ARMED (0) + // 0x0000000f [3:0] ARMED (0x0) io_rw_32 armed; - + _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH // Raw read from bits 63:32 of time (no side effects) + // 0xffffffff [31:0] TIMERAWH (0x00000000) io_ro_32 timerawh; - + _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL // Raw read from bits 31:0 of time (no side effects) + // 0xffffffff [31:0] TIMERAWL (0x00000000) io_ro_32 timerawl; - + _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE // Set bits high to enable pause when the corresponding debug ports are active - // 0x00000004 [2] : DBG1 (1): Pause when processor 1 is in debug mode - // 0x00000002 [1] : DBG0 (1): Pause when processor 0 is in debug mode + // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode + // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode io_rw_32 dbgpause; - + _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE // Set high to pause the timer - // 0x00000001 [0] : PAUSE (0) + // 0x00000001 [0] PAUSE (0) io_rw_32 pause; - + _REG_(TIMER_INTR_OFFSET) // TIMER_INTR // Raw Interrupts - // 0x00000008 [3] : ALARM_3 (0) - // 0x00000004 [2] : ALARM_2 (0) - // 0x00000002 [1] : ALARM_1 (0) - // 0x00000001 [0] : ALARM_0 (0) + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) io_rw_32 intr; - + _REG_(TIMER_INTE_OFFSET) // TIMER_INTE // Interrupt Enable - // 0x00000008 [3] : ALARM_3 (0) - // 0x00000004 [2] : ALARM_2 (0) - // 0x00000002 [1] : ALARM_1 (0) - // 0x00000001 [0] : ALARM_0 (0) + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) io_rw_32 inte; - + _REG_(TIMER_INTF_OFFSET) // TIMER_INTF // Interrupt Force - // 0x00000008 [3] : ALARM_3 (0) - // 0x00000004 [2] : ALARM_2 (0) - // 0x00000002 [1] : ALARM_1 (0) - // 0x00000001 [0] : ALARM_0 (0) + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) io_rw_32 intf; - + _REG_(TIMER_INTS_OFFSET) // TIMER_INTS // Interrupt status after masking & forcing - // 0x00000008 [3] : ALARM_3 (0) - // 0x00000004 [2] : ALARM_2 (0) - // 0x00000002 [1] : ALARM_1 (0) - // 0x00000001 [0] : ALARM_0 (0) + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) io_ro_32 ints; } timer_hw_t; #define timer_hw ((timer_hw_t *)TIMER_BASE) +static_assert(sizeof (timer_hw_t) == 0x0044, ""); -static_assert( NUM_TIMERS == 4, ""); +#endif // _HARDWARE_STRUCTS_TIMER_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/uart.h b/src/rp2040/hardware_structs/include/hardware/structs/uart.h index 4912824bb..db0b4be40 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/uart.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/uart.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_UART_H #define _HARDWARE_STRUCTS_UART_H +/** + * \file rp2040/uart.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/uart.h" @@ -18,160 +21,162 @@ // _REG_(x) will link to the corresponding register in hardware/regs/uart.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(UART_UARTDR_OFFSET) // UART_UARTDR // Data Register, UARTDR - // 0x00000800 [11] : OE (0): Overrun error - // 0x00000400 [10] : BE (0): Break error - // 0x00000200 [9] : PE (0): Parity error - // 0x00000100 [8] : FE (0): Framing error - // 0x000000ff [7:0] : DATA (0): Receive (read) data character + // 0x00000800 [11] OE (-) Overrun error + // 0x00000400 [10] BE (-) Break error + // 0x00000200 [9] PE (-) Parity error + // 0x00000100 [8] FE (-) Framing error + // 0x000000ff [7:0] DATA (-) Receive (read) data character io_rw_32 dr; - + _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR // Receive Status Register/Error Clear Register, UARTRSR/UARTECR - // 0x00000008 [3] : OE (0): Overrun error - // 0x00000004 [2] : BE (0): Break error - // 0x00000002 [1] : PE (0): Parity error - // 0x00000001 [0] : FE (0): Framing error + // 0x00000008 [3] OE (0) Overrun error + // 0x00000004 [2] BE (0) Break error + // 0x00000002 [1] PE (0) Parity error + // 0x00000001 [0] FE (0) Framing error io_rw_32 rsr; - + uint32_t _pad0[4]; - + _REG_(UART_UARTFR_OFFSET) // UART_UARTFR // Flag Register, UARTFR - // 0x00000100 [8] : RI (0): Ring indicator - // 0x00000080 [7] : TXFE (1): Transmit FIFO empty - // 0x00000040 [6] : RXFF (0): Receive FIFO full - // 0x00000020 [5] : TXFF (0): Transmit FIFO full - // 0x00000010 [4] : RXFE (1): Receive FIFO empty - // 0x00000008 [3] : BUSY (0): UART busy - // 0x00000004 [2] : DCD (0): Data carrier detect - // 0x00000002 [1] : DSR (0): Data set ready - // 0x00000001 [0] : CTS (0): Clear to send + // 0x00000100 [8] RI (-) Ring indicator + // 0x00000080 [7] TXFE (1) Transmit FIFO empty + // 0x00000040 [6] RXFF (0) Receive FIFO full + // 0x00000020 [5] TXFF (0) Transmit FIFO full + // 0x00000010 [4] RXFE (1) Receive FIFO empty + // 0x00000008 [3] BUSY (0) UART busy + // 0x00000004 [2] DCD (-) Data carrier detect + // 0x00000002 [1] DSR (-) Data set ready + // 0x00000001 [0] CTS (-) Clear to send io_ro_32 fr; - + uint32_t _pad1; - + _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR // IrDA Low-Power Counter Register, UARTILPR - // 0x000000ff [7:0] : ILPDVSR (0): 8-bit low-power divisor value + // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value io_rw_32 ilpr; - + _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD // Integer Baud Rate Register, UARTIBRD - // 0x0000ffff [15:0] : BAUD_DIVINT (0): The integer baud rate divisor + // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor io_rw_32 ibrd; - + _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD // Fractional Baud Rate Register, UARTFBRD - // 0x0000003f [5:0] : BAUD_DIVFRAC (0): The fractional baud rate divisor + // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor io_rw_32 fbrd; - + _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H // Line Control Register, UARTLCR_H - // 0x00000080 [7] : SPS (0): Stick parity select - // 0x00000060 [6:5] : WLEN (0): Word length - // 0x00000010 [4] : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become... - // 0x00000008 [3] : STP2 (0): Two stop bits select - // 0x00000004 [2] : EPS (0): Even parity select - // 0x00000002 [1] : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =... - // 0x00000001 [0] : BRK (0): Send break + // 0x00000080 [7] SPS (0) Stick parity select + // 0x00000060 [6:5] WLEN (0x0) Word length + // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)... + // 0x00000008 [3] STP2 (0) Two stop bits select + // 0x00000004 [2] EPS (0) Even parity select + // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit... + // 0x00000001 [0] BRK (0) Send break io_rw_32 lcr_h; - + _REG_(UART_UARTCR_OFFSET) // UART_UARTCR // Control Register, UARTCR - // 0x00008000 [15] : CTSEN (0): CTS hardware flow control enable - // 0x00004000 [14] : RTSEN (0): RTS hardware flow control enable - // 0x00002000 [13] : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output - // 0x00001000 [12] : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output - // 0x00000800 [11] : RTS (0): Request to send - // 0x00000400 [10] : DTR (0): Data transmit ready - // 0x00000200 [9] : RXE (1): Receive enable - // 0x00000100 [8] : TXE (1): Transmit enable - // 0x00000080 [7] : LBE (0): Loopback enable - // 0x00000004 [2] : SIRLP (0): SIR low-power IrDA mode - // 0x00000002 [1] : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled - // 0x00000001 [0] : UARTEN (0): UART enable: 0 = UART is disabled + // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable + // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable + // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)... + // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)... + // 0x00000800 [11] RTS (0) Request to send + // 0x00000400 [10] DTR (0) Data transmit ready + // 0x00000200 [9] RXE (1) Receive enable + // 0x00000100 [8] TXE (1) Transmit enable + // 0x00000080 [7] LBE (0) Loopback enable + // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode + // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled + // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled io_rw_32 cr; - + _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS // Interrupt FIFO Level Select Register, UARTIFLS - // 0x00000038 [5:3] : RXIFLSEL (0x2): Receive interrupt FIFO level select - // 0x00000007 [2:0] : TXIFLSEL (0x2): Transmit interrupt FIFO level select + // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select + // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select io_rw_32 ifls; - + _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC // Interrupt Mask Set/Clear Register, UARTIMSC - // 0x00000400 [10] : OEIM (0): Overrun error interrupt mask - // 0x00000200 [9] : BEIM (0): Break error interrupt mask - // 0x00000100 [8] : PEIM (0): Parity error interrupt mask - // 0x00000080 [7] : FEIM (0): Framing error interrupt mask - // 0x00000040 [6] : RTIM (0): Receive timeout interrupt mask - // 0x00000020 [5] : TXIM (0): Transmit interrupt mask - // 0x00000010 [4] : RXIM (0): Receive interrupt mask - // 0x00000008 [3] : DSRMIM (0): nUARTDSR modem interrupt mask - // 0x00000004 [2] : DCDMIM (0): nUARTDCD modem interrupt mask - // 0x00000002 [1] : CTSMIM (0): nUARTCTS modem interrupt mask - // 0x00000001 [0] : RIMIM (0): nUARTRI modem interrupt mask + // 0x00000400 [10] OEIM (0) Overrun error interrupt mask + // 0x00000200 [9] BEIM (0) Break error interrupt mask + // 0x00000100 [8] PEIM (0) Parity error interrupt mask + // 0x00000080 [7] FEIM (0) Framing error interrupt mask + // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask + // 0x00000020 [5] TXIM (0) Transmit interrupt mask + // 0x00000010 [4] RXIM (0) Receive interrupt mask + // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask + // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask + // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask + // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask io_rw_32 imsc; - + _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS // Raw Interrupt Status Register, UARTRIS - // 0x00000400 [10] : OERIS (0): Overrun error interrupt status - // 0x00000200 [9] : BERIS (0): Break error interrupt status - // 0x00000100 [8] : PERIS (0): Parity error interrupt status - // 0x00000080 [7] : FERIS (0): Framing error interrupt status - // 0x00000040 [6] : RTRIS (0): Receive timeout interrupt status - // 0x00000020 [5] : TXRIS (0): Transmit interrupt status - // 0x00000010 [4] : RXRIS (0): Receive interrupt status - // 0x00000008 [3] : DSRRMIS (0): nUARTDSR modem interrupt status - // 0x00000004 [2] : DCDRMIS (0): nUARTDCD modem interrupt status - // 0x00000002 [1] : CTSRMIS (0): nUARTCTS modem interrupt status - // 0x00000001 [0] : RIRMIS (0): nUARTRI modem interrupt status + // 0x00000400 [10] OERIS (0) Overrun error interrupt status + // 0x00000200 [9] BERIS (0) Break error interrupt status + // 0x00000100 [8] PERIS (0) Parity error interrupt status + // 0x00000080 [7] FERIS (0) Framing error interrupt status + // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status + // 0x00000020 [5] TXRIS (0) Transmit interrupt status + // 0x00000010 [4] RXRIS (0) Receive interrupt status + // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status + // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status + // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status + // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status io_ro_32 ris; - + _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS // Masked Interrupt Status Register, UARTMIS - // 0x00000400 [10] : OEMIS (0): Overrun error masked interrupt status - // 0x00000200 [9] : BEMIS (0): Break error masked interrupt status - // 0x00000100 [8] : PEMIS (0): Parity error masked interrupt status - // 0x00000080 [7] : FEMIS (0): Framing error masked interrupt status - // 0x00000040 [6] : RTMIS (0): Receive timeout masked interrupt status - // 0x00000020 [5] : TXMIS (0): Transmit masked interrupt status - // 0x00000010 [4] : RXMIS (0): Receive masked interrupt status - // 0x00000008 [3] : DSRMMIS (0): nUARTDSR modem masked interrupt status - // 0x00000004 [2] : DCDMMIS (0): nUARTDCD modem masked interrupt status - // 0x00000002 [1] : CTSMMIS (0): nUARTCTS modem masked interrupt status - // 0x00000001 [0] : RIMMIS (0): nUARTRI modem masked interrupt status + // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status + // 0x00000200 [9] BEMIS (0) Break error masked interrupt status + // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status + // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status + // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status + // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status + // 0x00000010 [4] RXMIS (0) Receive masked interrupt status + // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status + // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status + // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status + // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status io_ro_32 mis; - + _REG_(UART_UARTICR_OFFSET) // UART_UARTICR // Interrupt Clear Register, UARTICR - // 0x00000400 [10] : OEIC (0): Overrun error interrupt clear - // 0x00000200 [9] : BEIC (0): Break error interrupt clear - // 0x00000100 [8] : PEIC (0): Parity error interrupt clear - // 0x00000080 [7] : FEIC (0): Framing error interrupt clear - // 0x00000040 [6] : RTIC (0): Receive timeout interrupt clear - // 0x00000020 [5] : TXIC (0): Transmit interrupt clear - // 0x00000010 [4] : RXIC (0): Receive interrupt clear - // 0x00000008 [3] : DSRMIC (0): nUARTDSR modem interrupt clear - // 0x00000004 [2] : DCDMIC (0): nUARTDCD modem interrupt clear - // 0x00000002 [1] : CTSMIC (0): nUARTCTS modem interrupt clear - // 0x00000001 [0] : RIMIC (0): nUARTRI modem interrupt clear + // 0x00000400 [10] OEIC (-) Overrun error interrupt clear + // 0x00000200 [9] BEIC (-) Break error interrupt clear + // 0x00000100 [8] PEIC (-) Parity error interrupt clear + // 0x00000080 [7] FEIC (-) Framing error interrupt clear + // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear + // 0x00000020 [5] TXIC (-) Transmit interrupt clear + // 0x00000010 [4] RXIC (-) Receive interrupt clear + // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear + // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear + // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear + // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear io_rw_32 icr; - + _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR // DMA Control Register, UARTDMACR - // 0x00000004 [2] : DMAONERR (0): DMA on error - // 0x00000002 [1] : TXDMAE (0): Transmit DMA enable - // 0x00000001 [0] : RXDMAE (0): Receive DMA enable + // 0x00000004 [2] DMAONERR (0) DMA on error + // 0x00000002 [1] TXDMAE (0) Transmit DMA enable + // 0x00000001 [0] RXDMAE (0) Receive DMA enable io_rw_32 dmacr; } uart_hw_t; #define uart0_hw ((uart_hw_t *)UART0_BASE) #define uart1_hw ((uart_hw_t *)UART1_BASE) +static_assert(sizeof (uart_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_UART_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/usb.h b/src/rp2040/hardware_structs/include/hardware/structs/usb.h index d5d74df04..399845f17 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/usb.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/usb.h @@ -1,16 +1,20 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_USB_H #define _HARDWARE_STRUCTS_USB_H +/** + * \file rp2040/usb.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/usb.h" +#include "hardware/structs/usb_dpram.h" // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb // @@ -18,561 +22,455 @@ // _REG_(x) will link to the corresponding register in hardware/regs/usb.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION - -// 0-15 -#define USB_NUM_ENDPOINTS 16 - -// allow user to restrict number of endpoints available to save RAN -#ifndef USB_MAX_ENDPOINTS -#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS -#endif - -// 1-15 -#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) - -// Endpoint buffer control bits -#define USB_BUF_CTRL_FULL 0x00008000u -#define USB_BUF_CTRL_LAST 0x00004000u -#define USB_BUF_CTRL_DATA0_PID 0x00000000u -#define USB_BUF_CTRL_DATA1_PID 0x00002000u -#define USB_BUF_CTRL_SEL 0x00001000u -#define USB_BUF_CTRL_STALL 0x00000800u -#define USB_BUF_CTRL_AVAIL 0x00000400u -#define USB_BUF_CTRL_LEN_MASK 0x000003FFu -#define USB_BUF_CTRL_LEN_LSB 0 - -// ep_inout_ctrl bits -#define EP_CTRL_ENABLE_BITS (1u << 31u) -#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) -#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) -#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) -#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) -#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) -#define EP_CTRL_BUFFER_TYPE_LSB 26u -#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u - -#define USB_DPRAM_SIZE 4096u - -// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb -// Allow user to claim some of the USB RAM for themselves -#ifndef USB_DPRAM_MAX -#define USB_DPRAM_MAX USB_DPRAM_SIZE -#endif - -// Define maximum packet sizes -#define USB_MAX_ISO_PACKET_SIZE 1023 -#define USB_MAX_PACKET_SIZE 64 - -typedef struct { - // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses - volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets - - // Starts at ep1 - struct usb_device_dpram_ep_ctrl { - io_rw_32 in; - io_rw_32 out; - } ep_ctrl[USB_NUM_ENDPOINTS - 1]; - - // Starts at ep0 - struct usb_device_dpram_ep_buf_ctrl { - io_rw_32 in; - io_rw_32 out; - } ep_buf_ctrl[USB_NUM_ENDPOINTS]; - - // EP0 buffers are fixed. Assumes single buffered mode for EP0 - uint8_t ep0_buf_a[0x40]; - uint8_t ep0_buf_b[0x40]; - - // Rest of DPRAM can be carved up as needed - uint8_t epx_data[USB_DPRAM_MAX - 0x180]; -} usb_device_dpram_t; - -static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); -static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); - -typedef struct { - // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses - volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets - - // Interrupt endpoint control 1 -> 15 - struct usb_host_dpram_ep_ctrl { - io_rw_32 ctrl; - io_rw_32 spare; - } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; - - io_rw_32 epx_buf_ctrl; - io_rw_32 _spare0; - - // Interrupt endpoint buffer control - struct usb_host_dpram_ep_buf_ctrl { - io_rw_32 ctrl; - io_rw_32 spare; - } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; - - io_rw_32 epx_ctrl; - - uint8_t _spare1[124]; - - // Should start at 0x180 - uint8_t epx_data[USB_DPRAM_MAX - 0x180]; -} usb_host_dpram_t; - -static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); -static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP // Device address and endpoint control - // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to - // 0x0000007f [6:0] : ADDRESS (0): In device mode, the address that the device should respond to + // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to + // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to io_rw_32 dev_addr_ctrl; - - _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 + // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) - // + _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 // Interrupt endpoint 1 - // 0x04000000 [26] : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub) - // 0x02000000 [25] : INTEP_DIR (0): Direction of the interrupt endpoint - // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint - // 0x0000007f [6:0] : ADDRESS (0): Device address - io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15 - + // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on... + // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint + // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint + // 0x0000007f [6:0] ADDRESS (0x00) Device address + io_rw_32 int_ep_addr_ctrl[15]; + _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL // Main control register - // 0x80000000 [31] : SIM_TIMING (0): Reduced timings for simulation - // 0x00000002 [1] : HOST_NDEVICE (0): Device mode = 0, Host mode = 1 - // 0x00000001 [0] : CONTROLLER_EN (0): Enable controller + // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation + // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1 + // 0x00000001 [0] CONTROLLER_EN (0) Enable controller io_rw_32 main_ctrl; - + _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR // Set the SOF (Start of Frame) frame number in the host controller - // 0x000007ff [10:0] : COUNT (0) - io_wo_32 sof_rw; - + // 0x000007ff [10:0] COUNT (0x000) + io_wo_32 sof_wr; + _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD // Read the last SOF (Start of Frame) frame number seen - // 0x000007ff [10:0] : COUNT (0) + // 0x000007ff [10:0] COUNT (0x000) io_ro_32 sof_rd; - + _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL // SIE control register - // 0x80000000 [31] : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - // 0x40000000 [30] : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1 - // 0x20000000 [29] : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - // 0x10000000 [28] : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 - // 0x08000000 [27] : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - // 0x04000000 [26] : DIRECT_EN (0): Direct bus drive enable - // 0x02000000 [25] : DIRECT_DP (0): Direct control of DP - // 0x01000000 [24] : DIRECT_DM (0): Direct control of DM - // 0x00040000 [18] : TRANSCEIVER_PD (0): Power down bus transceiver - // 0x00020000 [17] : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3) - // 0x00010000 [16] : PULLUP_EN (0): Device: Enable pull up resistor - // 0x00008000 [15] : PULLDOWN_EN (0): Host: Enable pull down resistors - // 0x00002000 [13] : RESET_BUS (0): Host: Reset bus - // 0x00001000 [12] : RESUME (0): Device: Remote wakeup - // 0x00000800 [11] : VBUS_EN (0): Host: Enable VBUS - // 0x00000400 [10] : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus) - // 0x00000200 [9] : SOF_EN (0): Host: Enable SOF generation (for full speed bus) - // 0x00000100 [8] : SOF_SYNC (0): Host: Delay packet(s) until after SOF - // 0x00000040 [6] : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub - // 0x00000010 [4] : STOP_TRANS (0): Host: Stop transaction - // 0x00000008 [3] : RECEIVE_DATA (0): Host: Receive transaction (IN to host) - // 0x00000004 [2] : SEND_DATA (0): Host: Send transaction (OUT from host) - // 0x00000002 [1] : SEND_SETUP (0): Host: Send Setup packet - // 0x00000001 [0] : START_TRANS (0): Host: Start transaction + // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1 + // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers... + // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable + // 0x02000000 [25] DIRECT_DP (0) Direct control of DP + // 0x01000000 [24] DIRECT_DM (0) Direct control of DM + // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver + // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3) + // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor + // 0x00008000 [15] PULLDOWN_EN (0) Host: Enable pull down resistors + // 0x00002000 [13] RESET_BUS (0) Host: Reset bus + // 0x00001000 [12] RESUME (0) Device: Remote wakeup + // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS + // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus) + // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus) + // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF + // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub + // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction + // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host) + // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host) + // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet + // 0x00000001 [0] START_TRANS (0) Host: Start transaction io_rw_32 sie_ctrl; - + _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS // SIE status register - // 0x80000000 [31] : DATA_SEQ_ERROR (0): Data Sequence Error - // 0x40000000 [30] : ACK_REC (0): ACK received - // 0x20000000 [29] : STALL_REC (0): Host: STALL received - // 0x10000000 [28] : NAK_REC (0): Host: NAK received - // 0x08000000 [27] : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in... - // 0x04000000 [26] : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast - // 0x02000000 [25] : BIT_STUFF_ERROR (0): Bit Stuff Error - // 0x01000000 [24] : CRC_ERROR (0): CRC Error - // 0x00080000 [19] : BUS_RESET (0): Device: bus reset received - // 0x00040000 [18] : TRANS_COMPLETE (0): Transaction complete - // 0x00020000 [17] : SETUP_REC (0): Device: Setup packet received - // 0x00010000 [16] : CONNECTED (0): Device: connected - // 0x00000800 [11] : RESUME (0): Host: Device has initiated a remote resume - // 0x00000400 [10] : VBUS_OVER_CURR (0): VBUS over current detected - // 0x00000300 [9:8] : SPEED (0): Host: device speed - // 0x00000010 [4] : SUSPENDED (0): Bus in suspended state - // 0x0000000c [3:2] : LINE_STATE (0): USB bus line state - // 0x00000001 [0] : VBUS_DETECTED (0): Device: VBUS Detected + // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error + // 0x40000000 [30] ACK_REC (0) ACK received + // 0x20000000 [29] STALL_REC (0) Host: STALL received + // 0x10000000 [28] NAK_REC (0) Host: NAK received + // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an... + // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the... + // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error + // 0x01000000 [24] CRC_ERROR (0) CRC Error + // 0x00080000 [19] BUS_RESET (0) Device: bus reset received + // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete + // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received + // 0x00010000 [16] CONNECTED (0) Device: connected + // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume + // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected + // 0x00000300 [9:8] SPEED (0x0) Host: device speed + // 0x00000010 [4] SUSPENDED (0) Bus in suspended state + // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state + // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected io_rw_32 sie_status; - + _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL // interrupt endpoint control register - // 0x0000fffe [15:1] : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15 + // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 => 15 io_rw_32 int_ep_ctrl; - + _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS // Buffer status register - // 0x80000000 [31] : EP15_OUT (0) - // 0x40000000 [30] : EP15_IN (0) - // 0x20000000 [29] : EP14_OUT (0) - // 0x10000000 [28] : EP14_IN (0) - // 0x08000000 [27] : EP13_OUT (0) - // 0x04000000 [26] : EP13_IN (0) - // 0x02000000 [25] : EP12_OUT (0) - // 0x01000000 [24] : EP12_IN (0) - // 0x00800000 [23] : EP11_OUT (0) - // 0x00400000 [22] : EP11_IN (0) - // 0x00200000 [21] : EP10_OUT (0) - // 0x00100000 [20] : EP10_IN (0) - // 0x00080000 [19] : EP9_OUT (0) - // 0x00040000 [18] : EP9_IN (0) - // 0x00020000 [17] : EP8_OUT (0) - // 0x00010000 [16] : EP8_IN (0) - // 0x00008000 [15] : EP7_OUT (0) - // 0x00004000 [14] : EP7_IN (0) - // 0x00002000 [13] : EP6_OUT (0) - // 0x00001000 [12] : EP6_IN (0) - // 0x00000800 [11] : EP5_OUT (0) - // 0x00000400 [10] : EP5_IN (0) - // 0x00000200 [9] : EP4_OUT (0) - // 0x00000100 [8] : EP4_IN (0) - // 0x00000080 [7] : EP3_OUT (0) - // 0x00000040 [6] : EP3_IN (0) - // 0x00000020 [5] : EP2_OUT (0) - // 0x00000010 [4] : EP2_IN (0) - // 0x00000008 [3] : EP1_OUT (0) - // 0x00000004 [2] : EP1_IN (0) - // 0x00000002 [1] : EP0_OUT (0) - // 0x00000001 [0] : EP0_IN (0) + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) io_rw_32 buf_status; - + _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE // Which of the double buffers should be handled - // 0x80000000 [31] : EP15_OUT (0) - // 0x40000000 [30] : EP15_IN (0) - // 0x20000000 [29] : EP14_OUT (0) - // 0x10000000 [28] : EP14_IN (0) - // 0x08000000 [27] : EP13_OUT (0) - // 0x04000000 [26] : EP13_IN (0) - // 0x02000000 [25] : EP12_OUT (0) - // 0x01000000 [24] : EP12_IN (0) - // 0x00800000 [23] : EP11_OUT (0) - // 0x00400000 [22] : EP11_IN (0) - // 0x00200000 [21] : EP10_OUT (0) - // 0x00100000 [20] : EP10_IN (0) - // 0x00080000 [19] : EP9_OUT (0) - // 0x00040000 [18] : EP9_IN (0) - // 0x00020000 [17] : EP8_OUT (0) - // 0x00010000 [16] : EP8_IN (0) - // 0x00008000 [15] : EP7_OUT (0) - // 0x00004000 [14] : EP7_IN (0) - // 0x00002000 [13] : EP6_OUT (0) - // 0x00001000 [12] : EP6_IN (0) - // 0x00000800 [11] : EP5_OUT (0) - // 0x00000400 [10] : EP5_IN (0) - // 0x00000200 [9] : EP4_OUT (0) - // 0x00000100 [8] : EP4_IN (0) - // 0x00000080 [7] : EP3_OUT (0) - // 0x00000040 [6] : EP3_IN (0) - // 0x00000020 [5] : EP2_OUT (0) - // 0x00000010 [4] : EP2_IN (0) - // 0x00000008 [3] : EP1_OUT (0) - // 0x00000004 [2] : EP1_IN (0) - // 0x00000002 [1] : EP0_OUT (0) - // 0x00000001 [0] : EP0_IN (0) + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) io_ro_32 buf_cpu_should_handle; - + _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT - // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer - // 0x80000000 [31] : EP15_OUT (0) - // 0x40000000 [30] : EP15_IN (0) - // 0x20000000 [29] : EP14_OUT (0) - // 0x10000000 [28] : EP14_IN (0) - // 0x08000000 [27] : EP13_OUT (0) - // 0x04000000 [26] : EP13_IN (0) - // 0x02000000 [25] : EP12_OUT (0) - // 0x01000000 [24] : EP12_IN (0) - // 0x00800000 [23] : EP11_OUT (0) - // 0x00400000 [22] : EP11_IN (0) - // 0x00200000 [21] : EP10_OUT (0) - // 0x00100000 [20] : EP10_IN (0) - // 0x00080000 [19] : EP9_OUT (0) - // 0x00040000 [18] : EP9_IN (0) - // 0x00020000 [17] : EP8_OUT (0) - // 0x00010000 [16] : EP8_IN (0) - // 0x00008000 [15] : EP7_OUT (0) - // 0x00004000 [14] : EP7_IN (0) - // 0x00002000 [13] : EP6_OUT (0) - // 0x00001000 [12] : EP6_IN (0) - // 0x00000800 [11] : EP5_OUT (0) - // 0x00000400 [10] : EP5_IN (0) - // 0x00000200 [9] : EP4_OUT (0) - // 0x00000100 [8] : EP4_IN (0) - // 0x00000080 [7] : EP3_OUT (0) - // 0x00000040 [6] : EP3_IN (0) - // 0x00000020 [5] : EP2_OUT (0) - // 0x00000010 [4] : EP2_IN (0) - // 0x00000008 [3] : EP1_OUT (0) - // 0x00000004 [2] : EP1_IN (0) - // 0x00000002 [1] : EP0_OUT (0) - // 0x00000001 [0] : EP0_IN (0) + // Device only: Can be set to ignore the buffer control register for this endpoint in case you... + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) io_rw_32 abort; - + _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE // Device only: Used in conjunction with `EP_ABORT` - // 0x80000000 [31] : EP15_OUT (0) - // 0x40000000 [30] : EP15_IN (0) - // 0x20000000 [29] : EP14_OUT (0) - // 0x10000000 [28] : EP14_IN (0) - // 0x08000000 [27] : EP13_OUT (0) - // 0x04000000 [26] : EP13_IN (0) - // 0x02000000 [25] : EP12_OUT (0) - // 0x01000000 [24] : EP12_IN (0) - // 0x00800000 [23] : EP11_OUT (0) - // 0x00400000 [22] : EP11_IN (0) - // 0x00200000 [21] : EP10_OUT (0) - // 0x00100000 [20] : EP10_IN (0) - // 0x00080000 [19] : EP9_OUT (0) - // 0x00040000 [18] : EP9_IN (0) - // 0x00020000 [17] : EP8_OUT (0) - // 0x00010000 [16] : EP8_IN (0) - // 0x00008000 [15] : EP7_OUT (0) - // 0x00004000 [14] : EP7_IN (0) - // 0x00002000 [13] : EP6_OUT (0) - // 0x00001000 [12] : EP6_IN (0) - // 0x00000800 [11] : EP5_OUT (0) - // 0x00000400 [10] : EP5_IN (0) - // 0x00000200 [9] : EP4_OUT (0) - // 0x00000100 [8] : EP4_IN (0) - // 0x00000080 [7] : EP3_OUT (0) - // 0x00000040 [6] : EP3_IN (0) - // 0x00000020 [5] : EP2_OUT (0) - // 0x00000010 [4] : EP2_IN (0) - // 0x00000008 [3] : EP1_OUT (0) - // 0x00000004 [2] : EP1_IN (0) - // 0x00000002 [1] : EP0_OUT (0) - // 0x00000001 [0] : EP0_IN (0) + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) io_rw_32 abort_done; - + _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM - // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0 - // 0x00000002 [1] : EP0_OUT (0) - // 0x00000001 [0] : EP0_IN (0) + // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register... + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) io_rw_32 ep_stall_arm; - + _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL // Used by the host controller - // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device - // 0x000003ff [9:0] : DELAY_LS (0x10): NAK polling interval for a low speed device + // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device + // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device io_rw_32 nak_poll; - + _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set - // 0x80000000 [31] : EP15_OUT (0) - // 0x40000000 [30] : EP15_IN (0) - // 0x20000000 [29] : EP14_OUT (0) - // 0x10000000 [28] : EP14_IN (0) - // 0x08000000 [27] : EP13_OUT (0) - // 0x04000000 [26] : EP13_IN (0) - // 0x02000000 [25] : EP12_OUT (0) - // 0x01000000 [24] : EP12_IN (0) - // 0x00800000 [23] : EP11_OUT (0) - // 0x00400000 [22] : EP11_IN (0) - // 0x00200000 [21] : EP10_OUT (0) - // 0x00100000 [20] : EP10_IN (0) - // 0x00080000 [19] : EP9_OUT (0) - // 0x00040000 [18] : EP9_IN (0) - // 0x00020000 [17] : EP8_OUT (0) - // 0x00010000 [16] : EP8_IN (0) - // 0x00008000 [15] : EP7_OUT (0) - // 0x00004000 [14] : EP7_IN (0) - // 0x00002000 [13] : EP6_OUT (0) - // 0x00001000 [12] : EP6_IN (0) - // 0x00000800 [11] : EP5_OUT (0) - // 0x00000400 [10] : EP5_IN (0) - // 0x00000200 [9] : EP4_OUT (0) - // 0x00000100 [8] : EP4_IN (0) - // 0x00000080 [7] : EP3_OUT (0) - // 0x00000040 [6] : EP3_IN (0) - // 0x00000020 [5] : EP2_OUT (0) - // 0x00000010 [4] : EP2_IN (0) - // 0x00000008 [3] : EP1_OUT (0) - // 0x00000004 [2] : EP1_IN (0) - // 0x00000002 [1] : EP0_OUT (0) - // 0x00000001 [0] : EP0_IN (0) + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) io_rw_32 ep_nak_stall_status; - + _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING // Where to connect the USB controller - // 0x00000008 [3] : SOFTCON (0) - // 0x00000004 [2] : TO_DIGITAL_PAD (0) - // 0x00000002 [1] : TO_EXTPHY (0) - // 0x00000001 [0] : TO_PHY (0) + // 0x00000008 [3] SOFTCON (0) + // 0x00000004 [2] TO_DIGITAL_PAD (0) + // 0x00000002 [1] TO_EXTPHY (0) + // 0x00000001 [0] TO_PHY (0) io_rw_32 muxing; - + _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO - // 0x00000020 [5] : OVERCURR_DETECT_EN (0) - // 0x00000010 [4] : OVERCURR_DETECT (0) - // 0x00000008 [3] : VBUS_DETECT_OVERRIDE_EN (0) - // 0x00000004 [2] : VBUS_DETECT (0) - // 0x00000002 [1] : VBUS_EN_OVERRIDE_EN (0) - // 0x00000001 [0] : VBUS_EN (0) + // 0x00000020 [5] OVERCURR_DETECT_EN (0) + // 0x00000010 [4] OVERCURR_DETECT (0) + // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0) + // 0x00000004 [2] VBUS_DETECT (0) + // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0) + // 0x00000001 [0] VBUS_EN (0) io_rw_32 pwr; - + _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT - // This register allows for direct control of the USB phy - // 0x00400000 [22] : DM_OVV (0): DM over voltage - // 0x00200000 [21] : DP_OVV (0): DP over voltage - // 0x00100000 [20] : DM_OVCN (0): DM overcurrent - // 0x00080000 [19] : DP_OVCN (0): DP overcurrent - // 0x00040000 [18] : RX_DM (0): DPM pin state - // 0x00020000 [17] : RX_DP (0): DPP pin state - // 0x00010000 [16] : RX_DD (0): Differential RX - // 0x00008000 [15] : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode - // 0x00004000 [14] : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate - // 0x00002000 [13] : TX_PD (0): TX power down override (if override enable is set) - // 0x00001000 [12] : RX_PD (0): RX power down override (if override enable is set) - // 0x00000800 [11] : TX_DM (0): Output data - // 0x00000400 [10] : TX_DP (0): Output data - // 0x00000200 [9] : TX_DM_OE (0): Output enable - // 0x00000100 [8] : TX_DP_OE (0): Output enable - // 0x00000040 [6] : DM_PULLDN_EN (0): DM pull down enable - // 0x00000020 [5] : DM_PULLUP_EN (0): DM pull up enable - // 0x00000010 [4] : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor - // 0x00000004 [2] : DP_PULLDN_EN (0): DP pull down enable - // 0x00000002 [1] : DP_PULLUP_EN (0): DP pull up enable - // 0x00000001 [0] : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor + // Note that most functions are driven directly from usb_fsls controller + // 0x00400000 [22] DM_OVV (0) Status bit from USB PHY + // 0x00200000 [21] DP_OVV (0) Status bit from USB PHY + // 0x00100000 [20] DM_OVCN (0) Status bit from USB PHY + // 0x00080000 [19] DP_OVCN (0) Status bit from USB PHY + // 0x00040000 [18] RX_DM (0) Status bit from USB PHY + + // 0x00020000 [17] RX_DP (0) Status bit from USB PHY + + // 0x00010000 [16] RX_DD (0) Status bit from USB PHY + + // 0x00008000 [15] TX_DIFFMODE (0) + // 0x00004000 [14] TX_FSSLEW (0) + // 0x00002000 [13] TX_PD (0) + // 0x00001000 [12] RX_PD (0) + // 0x00000800 [11] TX_DM (0) Value to drive to USB PHY when override enable is set... + // 0x00000400 [10] TX_DP (0) Value to drive to USB PHY when override enable is set... + // 0x00000200 [9] TX_DM_OE (0) Value to drive to USB PHY when override enable is set... + // 0x00000100 [8] TX_DP_OE (0) Value to drive to USB PHY when override enable is set... + // 0x00000040 [6] DM_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000020 [5] DM_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000010 [4] DM_PULLUP_HISEL (0) when dm_pullup_en is set high, this enables second resistor + // 0x00000004 [2] DP_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000002 [1] DP_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000001 [0] DP_PULLUP_HISEL (0) when dp_pullup_en is set high, this enables second resistor io_rw_32 phy_direct; - + _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE - // Override enable for each control in usbphy_direct - // 0x00008000 [15] : TX_DIFFMODE_OVERRIDE_EN (0) - // 0x00001000 [12] : DM_PULLUP_OVERRIDE_EN (0) - // 0x00000800 [11] : TX_FSSLEW_OVERRIDE_EN (0) - // 0x00000400 [10] : TX_PD_OVERRIDE_EN (0) - // 0x00000200 [9] : RX_PD_OVERRIDE_EN (0) - // 0x00000100 [8] : TX_DM_OVERRIDE_EN (0) - // 0x00000080 [7] : TX_DP_OVERRIDE_EN (0) - // 0x00000040 [6] : TX_DM_OE_OVERRIDE_EN (0) - // 0x00000020 [5] : TX_DP_OE_OVERRIDE_EN (0) - // 0x00000010 [4] : DM_PULLDN_EN_OVERRIDE_EN (0) - // 0x00000008 [3] : DP_PULLDN_EN_OVERRIDE_EN (0) - // 0x00000004 [2] : DP_PULLUP_EN_OVERRIDE_EN (0) - // 0x00000002 [1] : DM_PULLUP_HISEL_OVERRIDE_EN (0) - // 0x00000001 [0] : DP_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) + // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) + // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) + // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) + // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) + // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) io_rw_32 phy_direct_override; - + _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM - // Used to adjust trim values of USB phy pull down resistors - // 0x00001f00 [12:8] : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY - // 0x0000001f [4:0] : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY + // Note that most functions are driven directly from usb_fsls controller + // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + io_rw_32 phy_trim; - + uint32_t _pad0; - + _REG_(USB_INTR_OFFSET) // USB_INTR // Raw Interrupts - // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] : SETUP_REQ (0): Device - // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host - // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes - // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes - // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS - // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS - // 0x00000400 [10] : STALL (0): Source: SIE_STATUS - // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS - // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS - // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS - // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS - // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS - // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS - // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host - // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i io_ro_32 intr; - + _REG_(USB_INTE_OFFSET) // USB_INTE // Interrupt Enable - // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] : SETUP_REQ (0): Device - // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host - // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes - // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes - // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS - // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS - // 0x00000400 [10] : STALL (0): Source: SIE_STATUS - // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS - // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS - // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS - // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS - // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS - // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS - // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host - // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i io_rw_32 inte; - + _REG_(USB_INTF_OFFSET) // USB_INTF // Interrupt Force - // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] : SETUP_REQ (0): Device - // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host - // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes - // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes - // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS - // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS - // 0x00000400 [10] : STALL (0): Source: SIE_STATUS - // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS - // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS - // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS - // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS - // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS - // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS - // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host - // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i io_rw_32 intf; - + _REG_(USB_INTS_OFFSET) // USB_INTS // Interrupt status after masking & forcing - // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set - // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set - // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet - // 0x00010000 [16] : SETUP_REQ (0): Device - // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host - // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes - // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes - // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS - // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS - // 0x00000400 [10] : STALL (0): Source: SIE_STATUS - // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS - // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS - // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS - // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS - // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS - // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set - // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS - // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame) - // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host - // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i io_ro_32 ints; } usb_hw_t; #define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) +static_assert(sizeof (usb_hw_t) == 0x009c, ""); -#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) -#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) - -static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); +#endif // _HARDWARE_STRUCTS_USB_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/usb_dpram.h b/src/rp2040/hardware_structs/include/hardware/structs/usb_dpram.h new file mode 100644 index 000000000..aaa4ec58b --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/usb_dpram.h @@ -0,0 +1,128 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H +#define _HARDWARE_STRUCTS_USB_DPRAM_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +// 0-15 +#define USB_NUM_ENDPOINTS 16 + +// allow user to restrict number of endpoints available to save RAN +#ifndef USB_MAX_ENDPOINTS +#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS +#endif + +// 1-15 +#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) + +// Endpoint buffer control bits +#define USB_BUF_CTRL_FULL 0x00008000u +#define USB_BUF_CTRL_LAST 0x00004000u +#define USB_BUF_CTRL_DATA0_PID 0x00000000u +#define USB_BUF_CTRL_DATA1_PID 0x00002000u +#define USB_BUF_CTRL_SEL 0x00001000u +#define USB_BUF_CTRL_STALL 0x00000800u +#define USB_BUF_CTRL_AVAIL 0x00000400u +#define USB_BUF_CTRL_LEN_MASK 0x000003FFu +#define USB_BUF_CTRL_LEN_LSB 0 + +// ep_inout_ctrl bits +#define EP_CTRL_ENABLE_BITS (1u << 31u) +#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) +#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) +#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) +#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) +#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) +#define EP_CTRL_BUFFER_TYPE_LSB 26u +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u + +#define USB_DPRAM_SIZE 4096u + +// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb +// Allow user to claim some of the USB RAM for themselves +#ifndef USB_DPRAM_MAX +#define USB_DPRAM_MAX USB_DPRAM_SIZE +#endif + +// Define maximum packet sizes +#define USB_MAX_ISO_PACKET_SIZE 1023 +#define USB_MAX_PACKET_SIZE 64 + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Starts at ep1 + struct usb_device_dpram_ep_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_ctrl[USB_NUM_ENDPOINTS - 1]; + + // Starts at ep0 + struct usb_device_dpram_ep_buf_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_buf_ctrl[USB_NUM_ENDPOINTS]; + + // EP0 buffers are fixed. Assumes single buffered mode for EP0 + uint8_t ep0_buf_a[0x40]; + uint8_t ep0_buf_b[0x40]; + + // Rest of DPRAM can be carved up as needed + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_device_dpram_t; + +static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Interrupt endpoint control 1 -> 15 + struct usb_host_dpram_ep_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_buf_ctrl; + io_rw_32 _spare0; + + // Interrupt endpoint buffer control + struct usb_host_dpram_ep_buf_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_ctrl; + + uint8_t _spare1[124]; + + // Should start at 0x180 + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_host_dpram_t; + +static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); + +#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) +#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) + +static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); + +#endif // _HARDWARE_STRUCTS_USB_DPRAM_H \ No newline at end of file diff --git a/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h b/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h index edfc498f1..0f16a0a04 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/vreg_and_chip_reset.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H #define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H +/** + * \file rp2040/vreg_and_chip_reset.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/vreg_and_chip_reset.h" @@ -18,32 +21,34 @@ // _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG // Voltage regulator control and status - // 0x00001000 [12] : ROK (0): regulation status - // 0x000000f0 [7:4] : VSEL (0xb): output voltage select - // 0x00000002 [1] : HIZ (0): high impedance mode select - // 0x00000001 [0] : EN (1): enable + // 0x00001000 [12] ROK (0) regulation status + + // 0x000000f0 [7:4] VSEL (0xb) output voltage select + + // 0x00000002 [1] HIZ (0) high impedance mode select + + // 0x00000001 [0] EN (1) enable + io_rw_32 vreg; - + _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD // brown-out detection control - // 0x000000f0 [7:4] : VSEL (0x9): threshold select - // 0x00000001 [0] : EN (1): enable + // 0x000000f0 [7:4] VSEL (0x9) threshold select + + // 0x00000001 [0] EN (1) enable + io_rw_32 bod; - + _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET // Chip reset control and status - // 0x01000000 [24] : PSM_RESTART_FLAG (0): This is set by psm_restart from the debugger - // 0x00100000 [20] : HAD_PSM_RESTART (0): Last reset was from the debug port - // 0x00010000 [16] : HAD_RUN (0): Last reset was from the RUN pin - // 0x00000100 [8] : HAD_POR (0): Last reset was from the power-on reset or brown-out detection blocks + // 0x01000000 [24] PSM_RESTART_FLAG (0) This is set by psm_restart from the debugger + // 0x00100000 [20] HAD_PSM_RESTART (0) Last reset was from the debug port + // 0x00010000 [16] HAD_RUN (0) Last reset was from the RUN pin + // 0x00000100 [8] HAD_POR (0) Last reset was from the power-on reset or brown-out... io_rw_32 chip_reset; } vreg_and_chip_reset_hw_t; #define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *)VREG_AND_CHIP_RESET_BASE) +static_assert(sizeof (vreg_and_chip_reset_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h b/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h index 5071cf5a0..7667aa499 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/watchdog.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_WATCHDOG_H #define _HARDWARE_STRUCTS_WATCHDOG_H +/** + * \file rp2040/watchdog.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/watchdog.h" @@ -18,45 +21,47 @@ // _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION typedef struct { _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL // Watchdog control - // 0x80000000 [31] : TRIGGER (0): Trigger a watchdog reset - // 0x40000000 [30] : ENABLE (0): When not enabled the watchdog timer is paused - // 0x04000000 [26] : PAUSE_DBG1 (1): Pause the watchdog timer when processor 1 is in debug mode - // 0x02000000 [25] : PAUSE_DBG0 (1): Pause the watchdog timer when processor 0 is in debug mode - // 0x01000000 [24] : PAUSE_JTAG (1): Pause the watchdog timer when JTAG is accessing the bus fabric - // 0x00ffffff [23:0] : TIME (0): Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will... + // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset + // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused + // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode + // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode + // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric + // 0x00ffffff [23:0] TIME (0x000000) Indicates the number of ticks / 2 (see errata RP2040-E1)... io_rw_32 ctrl; - + _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD - // Load the watchdog timer - // 0x00ffffff [23:0] : LOAD (0) + // Load the watchdog timer. + // 0x00ffffff [23:0] LOAD (0x000000) io_wo_32 load; - + _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON - // Logs the reason for the last reset - // 0x00000002 [1] : FORCE (0) - // 0x00000001 [0] : TIMER (0) + // Logs the reason for the last reset. + // 0x00000002 [1] FORCE (0) + // 0x00000001 [0] TIMER (0) io_ro_32 reason; - - _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 + // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) - // + _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) io_rw_32 scratch[8]; - + _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK // Controls the tick generator - // 0x000ff800 [19:11] : COUNT (0): Count down timer: the remaining number clk_tick cycles before the next tick is generated - // 0x00000400 [10] : RUNNING (0): Is the tick generator running? - // 0x00000200 [9] : ENABLE (1): start / stop tick generation - // 0x000001ff [8:0] : CYCLES (0): Total number of clk_tick cycles before the next tick + // 0x000ff800 [19:11] COUNT (-) Count down timer: the remaining number clk_tick cycles... + // 0x00000400 [10] RUNNING (-) Is the tick generator running? + // 0x00000200 [9] ENABLE (1) start / stop tick generation + // 0x000001ff [8:0] CYCLES (0x000) Total number of clk_tick cycles before the next tick io_rw_32 tick; } watchdog_hw_t; #define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) +static_assert(sizeof (watchdog_hw_t) == 0x0030, ""); + +#endif // _HARDWARE_STRUCTS_WATCHDOG_H -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/xip.h b/src/rp2040/hardware_structs/include/hardware/structs/xip.h new file mode 100644 index 000000000..332e8ccf1 --- /dev/null +++ b/src/rp2040/hardware_structs/include/hardware/structs/xip.h @@ -0,0 +1,76 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_H +#define _HARDWARE_STRUCTS_XIP_H + +/** + * \file rp2040/xip.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_CTRL_OFFSET) // XIP_CTRL + // Cache control + // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down + // 0x00000002 [1] ERR_BADWRITE (1) When 1, writes to any alias other than 0x0 (caching,... + // 0x00000001 [0] EN (1) When 1, enable the cache + io_rw_32 ctrl; + + _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH + // Cache Flush control + // 0x00000001 [0] FLUSH (0) Write 1 to flush the cache + io_wo_32 flush; + + _REG_(XIP_STAT_OFFSET) // XIP_STAT + // Cache Status + // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full + // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty + // 0x00000001 [0] FLUSH_READY (0) Reads as 0 while a cache flush is in progress, and 1 otherwise + io_ro_32 stat; + + _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT + // Cache Hit counter + // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_hit; + + _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC + // Cache Access counter + // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_acc; + + _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR + // FIFO stream address + // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... + io_rw_32 stream_addr; + + _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR + // FIFO stream control + // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read + io_rw_32 stream_ctr; + + _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO + // FIFO stream data + // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA + io_ro_32 stream_fifo; +} xip_ctrl_hw_t; + +#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) +static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_XIP_H + diff --git a/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h b/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h index 84e92b447..c31569b60 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/xip_ctrl.h @@ -1,72 +1,11 @@ -// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT - -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H -#define _HARDWARE_STRUCTS_XIP_CTRL_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/xip.h" - -// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip -// -// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) -// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. -// -// Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION - -typedef struct { - _REG_(XIP_CTRL_OFFSET) // XIP_CTRL - // Cache control - // 0x00000008 [3] : POWER_DOWN (0): When 1, the cache memories are powered down - // 0x00000002 [1] : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating) - // 0x00000001 [0] : EN (1): When 1, enable the cache - io_rw_32 ctrl; - - _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH - // Cache Flush control - // 0x00000001 [0] : FLUSH (0): Write 1 to flush the cache - io_rw_32 flush; - - _REG_(XIP_STAT_OFFSET) // XIP_STAT - // Cache Status - // 0x00000004 [2] : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full - // 0x00000002 [1] : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty - // 0x00000001 [0] : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise - io_ro_32 stat; - - _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT - // Cache Hit counter - io_rw_32 ctr_hit; - - _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC - // Cache Access counter - io_rw_32 ctr_acc; - - _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR - // FIFO stream address - // 0xfffffffc [31:2] : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO - io_rw_32 stream_addr; - - _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR - // FIFO stream control - // 0x003fffff [21:0] : STREAM_CTR (0): Write a nonzero value to start a streaming read - io_rw_32 stream_ctr; - - _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO - // FIFO stream data - io_ro_32 stream_fifo; -} xip_ctrl_hw_t; - -#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) - +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/xip.h" #define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS #define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS #define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS - -#endif diff --git a/src/rp2040/hardware_structs/include/hardware/structs/xosc.h b/src/rp2040/hardware_structs/include/hardware/structs/xosc.h index d327aa970..ee5a234f6 100644 --- a/src/rp2040/hardware_structs/include/hardware/structs/xosc.h +++ b/src/rp2040/hardware_structs/include/hardware/structs/xosc.h @@ -1,14 +1,17 @@ // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT -/* - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef _HARDWARE_STRUCTS_XOSC_H #define _HARDWARE_STRUCTS_XOSC_H +/** + * \file rp2040/xosc.h + */ + #include "hardware/address_mapped.h" #include "hardware/regs/xosc.h" @@ -18,43 +21,46 @@ // _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. // // Bit-field descriptions are of the form: -// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION /// \tag::xosc_hw[] typedef struct { _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL // Crystal Oscillator Control - // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC - // 0x00000fff [11:0] : FREQ_RANGE (0): Frequency range + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the... + // 0x00000fff [11:0] FREQ_RANGE (-) Frequency range io_rw_32 ctrl; - + _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS // Crystal Oscillator Status - // 0x80000000 [31] : STABLE (0): Oscillator is running and stable - // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT - // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0 - // 0x00000003 [1:0] : FREQ_RANGE (0): The current frequency range setting, always reads 0 + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and... + // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting, always reads 0 io_rw_32 status; - + _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT // Crystal Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC + io_rw_32 dormant; - + _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP // Controls the startup delay - // 0x00100000 [20] : X4 (0): Multiplies the startup_delay by 4 - // 0x00003fff [13:0] : DELAY (0xc4): in multiples of 256*xtal_period + // 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4 + // 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period io_rw_32 startup; - + uint32_t _pad0[3]; - + _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT - // A down counter running at the xosc frequency which counts to zero and stops - // 0x000000ff [7:0] : COUNT (0) + // A down counter running at the XOSC frequency which counts to zero and stops. + // 0x000000ff [7:0] COUNT (0x00) io_rw_32 count; } xosc_hw_t; +/// \end::xosc_hw[] #define xosc_hw ((xosc_hw_t *)XOSC_BASE) -/// \end::xosc_hw[] +static_assert(sizeof (xosc_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_XOSC_H -#endif diff --git a/src/rp2040/pico_platform/BUILD.bazel b/src/rp2040/pico_platform/BUILD.bazel new file mode 100644 index 000000000..bc860f1f4 --- /dev/null +++ b/src/rp2040/pico_platform/BUILD.bazel @@ -0,0 +1,52 @@ +package( + default_visibility = [ + "//src/rp2040:__subpackages__", + "//src/rp2_common:__pkg__", + ], +) + +cc_library( + name = "pico_platform_internal", + hdrs = [ + "include/pico/asm_helper.S", + "include/pico/platform.h", + "include/pico/platform/cpu_regs.h", + ], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:rp2040"], + + # Be extra careful about who references this for now; if users depend on + # this but not `pico_platform` they'll end up with undefined symbols. + # It's generally safe for anything that circularly depends on + # //src/rp2_common:pico_platform to be added to this allowlist because + # that implicitly means the transitive dependencies of pico_platform will + # get linked in. + visibility = [ + "//src/rp2_common:__pkg__", + ], + deps = [ + "//src/rp2040/hardware_regs", + "//src/rp2040/hardware_regs:platform_defs", + "//src/rp2_common/pico_platform_compiler", + "//src/rp2_common/pico_platform_panic:pico_platform_panic_headers", + "//src/rp2_common/pico_platform_sections", + ], +) + +cc_library( + name = "pico_platform", + srcs = ["platform.c"], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:rp2040"], + deps = [ + ":pico_platform_internal", + "//src/common/pico_base_headers", + "//src/rp2040/hardware_regs", + "//src/rp2040/hardware_regs:platform_defs", + "//src/rp2_common/hardware_base", + "//src/rp2_common/pico_platform_compiler", + "//src/rp2_common/pico_platform_panic", + "//src/rp2_common/pico_platform_sections", + "//src/rp2_common/pico_standard_link", + ], +) diff --git a/src/rp2_common/pico_platform/CMakeLists.txt b/src/rp2040/pico_platform/CMakeLists.txt similarity index 50% rename from src/rp2_common/pico_platform/CMakeLists.txt rename to src/rp2040/pico_platform/CMakeLists.txt index 8a6f1d24d..f7c607a4f 100644 --- a/src/rp2_common/pico_platform/CMakeLists.txt +++ b/src/rp2040/pico_platform/CMakeLists.txt @@ -1,23 +1,26 @@ -if (NOT TARGET pico_platform_headers) - add_library(pico_platform_headers INTERFACE) +if (NOT TARGET pico_platform) + pico_add_library(pico_platform) + + target_sources(pico_platform INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/platform.c + ) target_compile_definitions(pico_platform_headers INTERFACE PICO_NO_HARDWARE=0 PICO_ON_DEVICE=1 PICO_BUILD=1 + PICO_RP2040=1 + PICO_32BIT=1 ) - target_include_directories(pico_platform_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_platform_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(pico_platform_headers INTERFACE hardware_regs) -endif() - -if (NOT TARGET pico_platform) - pico_add_impl_library(pico_platform) - target_sources(pico_platform INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/platform.c) - - target_link_libraries(pico_platform INTERFACE pico_platform_headers) + pico_mirrored_target_link_libraries(pico_platform INTERFACE + pico_platform_compiler + pico_platform_panic + pico_platform_sections + ) endif() function(pico_add_platform_library TARGET) diff --git a/src/rp2_common/pico_platform/include/pico/asm_helper.S b/src/rp2040/pico_platform/include/pico/asm_helper.S similarity index 83% rename from src/rp2_common/pico_platform/include/pico/asm_helper.S rename to src/rp2040/pico_platform/include/pico/asm_helper.S index 23a925838..aff1fc9ae 100644 --- a/src/rp2_common/pico_platform/include/pico/asm_helper.S +++ b/src/rp2040/pico_platform/include/pico/asm_helper.S @@ -23,6 +23,13 @@ \x: .endm +.macro weak_func x +.weak \x +.type \x,%function +.thumb_func +\x: +.endm + .macro regular_func_with_section x .section .text.\x regular_func \x @@ -33,9 +40,13 @@ regular_func \x regular_func WRAPPER_FUNC_NAME(\x) .endm +.macro weak_wrapper_func x +weak_func WRAPPER_FUNC_NAME(\x) +.endm + +# backwards compatibility .macro __pre_init func, priority_string .section .preinit_array.\priority_string -.align 2 +.p2align 2 .word \func .endm - diff --git a/src/rp2040/pico_platform/include/pico/platform.h b/src/rp2040/pico_platform/include/pico/platform.h new file mode 100644 index 000000000..c28e2591d --- /dev/null +++ b/src/rp2040/pico_platform/include/pico/platform.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** \file platform.h + * \defgroup pico_platform pico_platform + * + * \brief Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture + * to provide a common abstraction over low level compiler / platform specifics + * + * This header may be included by assembly code + */ + +#ifndef _PICO_PLATFORM_H +#define _PICO_PLATFORM_H + +#ifndef _PICO_H +#error pico/platform.h should not be included directly; include pico.h instead +#endif + +#include "pico/platform/compiler.h" +#include "pico/platform/sections.h" +#include "pico/platform/panic.h" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/sio.h" + +// PICO_CONFIG: PICO_STACK_SIZE, Minimum amount of stack space reserved in the linker script for each core. See also PICO_CORE1_STACK_SIZE, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_STACK_SIZE +#define PICO_STACK_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_HEAP_SIZE, Minimum amount of heap space reserved by the linker script, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_HEAP_SIZE +#define PICO_HEAP_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform +#ifndef PICO_NO_RAM_VECTOR_TABLE +#define PICO_NO_RAM_VECTOR_TABLE 0 +#endif + +// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B0_SUPPORTED +#define PICO_RP2040_B0_SUPPORTED 1 +#endif + +// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_FLOAT_SUPPORT_ROM_V1 +#define PICO_FLOAT_SUPPORT_ROM_V1 1 +#endif + +// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 +#define PICO_DOUBLE_SUPPORT_ROM_V1 1 +#endif + +// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B1_SUPPORTED +#define PICO_RP2040_B1_SUPPORTED 1 +#endif + +// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2040_B2_SUPPORTED +#define PICO_RP2040_B2_SUPPORTED 1 +#endif + +// PICO_CONFIG: PICO_RP2350_A2_SUPPORTED, Whether to include any specific software support for RP2350 A2 revision, type=bool, default=1, advanced=true, group=pico_platform +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#ifndef PICO_RAM_VECTOR_TABLE_SIZE +#define PICO_RAM_VECTOR_TABLE_SIZE (VTABLE_FIRST_IRQ + NUM_IRQS) +#endif + +#ifndef __ASSEMBLER__ + +/*! \brief No-op function for the body of tight loops + * \ingroup pico_platform + * + * No-op function intended to be called by any tight hardware polling loop. Using this ubiquitously + * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup + * debugging might be added + */ +static __force_inline void tight_loop_contents(void) {} + +/*! \brief Helper method to busy-wait for at least the given number of cycles + * \ingroup pico_platform + * + * This method is useful for introducing very short delays. + * + * This method busy-waits in a tight loop for the given number of system clock cycles. The total wait time is only accurate to within 2 cycles, + * and this method uses a loop counter rather than a hardware timer, so the method will always take longer than expected if an + * interrupt is handled on the calling core during the busy-wait; you can of course disable interrupts to prevent this. + * + * You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert an actual + * time duration to a number of cycles. + * + * \param minimum_cycles the minimum number of system clock cycles to delay for + */ +static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) { + pico_default_asm_volatile( + "1: subs %0, #3\n" + "bcs 1b\n" + : "+l" (minimum_cycles) : : "cc", "memory" + ); +} + +// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=1, advanced=true, group=pico_runtime +#ifndef PICO_NO_FPGA_CHECK +#define PICO_NO_FPGA_CHECK 1 +#endif + +#if PICO_NO_FPGA_CHECK +static inline bool running_on_fpga(void) {return false;} +#else +bool running_on_fpga(void); +#endif + +/*! \brief Execute a breakpoint instruction + * \ingroup pico_platform + */ +static __force_inline void __breakpoint(void) { + pico_default_asm_volatile ("bkpt #0" : : : "memory"); +} + +/*! \brief Get the current core number + * \ingroup pico_platform + * + * \return The core number the call was made from + */ +__force_inline static uint get_core_num(void) { + return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); +} + +/*! \brief Get the current exception level on this core + * \ingroup pico_platform + * + * On Cortex-M this is the exception number defined in the architecture + * reference, which is equal to VTABLE_FIRST_IRQ + irq num if inside an + * interrupt handler. (VTABLE_FIRST_IRQ is defined in platform_defs.h). + * + * On Hazard3, this function returns VTABLE_FIRST_IRQ + irq num if inside of + * an external IRQ handler (or a fault from such a handler), and 0 otherwise, + * generally aligning with the Cortex-M values. + * + * \return the exception number if the CPU is handling an exception, or 0 otherwise + */ +static __force_inline uint __get_current_exception(void) { + uint exception; + pico_default_asm_volatile ( "mrs %0, ipsr" : "=l" (exception)); + return exception; +} + +#define host_safe_hw_ptr(x) ((uintptr_t)(x)) +#define native_safe_hw_ptr(x) host_safe_hw_ptr(x) + +/*! \brief Returns the RP2040 chip revision number + * \ingroup pico_platform + * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2) + */ +uint8_t rp2040_chip_version(void); + +/*! \brief Returns the RP2040 rom version number + * \ingroup pico_platform + * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2) + */ +static inline uint8_t rp2040_rom_version(void) { + GCC_Pragma("GCC diagnostic push") + GCC_Pragma("GCC diagnostic ignored \"-Warray-bounds\"") + return *(uint8_t*)0x13; + GCC_Pragma("GCC diagnostic pop") +} + +/*! \brief Multiply two integers using an assembly `MUL` instruction + * \ingroup pico_platform + * + * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler + * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation. + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ +__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) { +#ifdef __riscv +__asm ("mul %0, %0, %1" : "+l" (a) : "l" (b) : ); +#else +pico_default_asm ("muls %0, %1" : "+l" (a) : "l" (b) : "cc"); +#endif +return a; +} + +/*! \brief multiply two integer values using the fastest method possible + * \ingroup pico_platform + * + * Efficiently multiplies value a by possibly constant value b. + * + * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default + * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable + * and will be used + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ +#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ + (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ + (a)*(b)) + +#endif // __ASSEMBLER__ + +#endif \ No newline at end of file diff --git a/src/rp2040/pico_platform/include/pico/platform/cpu_regs.h b/src/rp2040/pico_platform/include/pico/platform/cpu_regs.h new file mode 100644 index 000000000..21ff95af3 --- /dev/null +++ b/src/rp2040/pico_platform/include/pico/platform/cpu_regs.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** \file platform.h + * \defgroup pico_platform pico_platform + * + * \brief Macros and definitions for accessing the CPU registers + * + * This header may be included by assembly code + */ + +#ifndef _PICO_PLATFORM_CPU_REGS_H +#define _PICO_PLATFORM_CPU_REGS_H + +#include "hardware/regs/m0plus.h" +#define ARM_CPU_PREFIXED(x) M0PLUS_ ## x + +#ifndef __ASSEMBLER__ +#include "hardware/structs/m0plus.h" +#define arm_cpu_hw m0plus_hw +#include "hardware/structs/nvic.h" +#include "hardware/structs/scb.h" +#endif + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_platform/platform.c b/src/rp2040/pico_platform/platform.c similarity index 95% rename from src/rp2_common/pico_platform/platform.c rename to src/rp2040/pico_platform/platform.c index 46e3c88f4..9b0016535 100644 --- a/src/rp2_common/pico_platform/platform.c +++ b/src/rp2040/pico_platform/platform.c @@ -19,7 +19,7 @@ // Inline stub provided in header if this code is unused (so folding can be // done in each TU instead of relying on LTO) bool running_on_fpga(void) { - return !!((*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS); + return (*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS; } #endif diff --git a/src/rp2350-arm-s.cmake b/src/rp2350-arm-s.cmake new file mode 100644 index 000000000..4941a1c3e --- /dev/null +++ b/src/rp2350-arm-s.cmake @@ -0,0 +1,22 @@ +# include everything needed to build against rp2350 + +set(PICO_RP2040 "0" CACHE INTERNAL "") +set(PICO_RP2350 "1" CACHE INTERNAL "") +set(PICO_RISCV "0" CACHE INTERNAL "") +set(PICO_ARM "1" CACHE INTERNAL "") +set(RP2_VARIANT_DIR ${CMAKE_CURRENT_LIST_DIR}/rp2350) +set(PICO_PIO_VERSION "1" CACHE INTERNAL "") +set(PICO_CMSIS_DEVICE "RP2350" CACHE INTERNAL "") +set(PICO_DEFAULT_FLASH_SIZE_BYTES "4 * 1024 * 1024") + +pico_add_doxygen_pre_define("PICO_RP2040=0") +pico_add_doxygen_pre_define("PICO_RP2350=1") +pico_add_doxygen_pre_define("NUM_DOORBELLS=1") # we have functions that are gated by this +pico_add_doxygen_enabled_section(rp2350_specific) + +# for now we are building RISC-V into RP2350 docs, so document these too +pico_add_doxygen(rp2_common/hardware_riscv) +pico_add_doxygen(rp2_common/hardware_hazard3) + +include(cmake/rp2_common.cmake) + diff --git a/src/rp2350-riscv.cmake b/src/rp2350-riscv.cmake new file mode 100644 index 000000000..f62f6e4be --- /dev/null +++ b/src/rp2350-riscv.cmake @@ -0,0 +1,18 @@ +# include everything needed to build against rp2350-riscv + +set(PICO_RP2040 "0" CACHE INTERNAL "") +set(PICO_RP2350 "1" CACHE INTERNAL "") +set(PICO_RISCV "1" CACHE INTERNAL "") +set(PICO_ARM "0" CACHE INTERNAL "") +set(RP2_VARIANT_DIR ${CMAKE_CURRENT_LIST_DIR}/rp2350) +set(PICO_PIO_VERSION "1" CACHE INTERNAL "") +set(PICO_DEFAULT_FLASH_SIZE_BYTES "4 * 1024 * 1024") +# for TinyUSB +set(NO_WARN_RWX_SEGMENTS_SUPPORTED "0" CACHE INTERNAL "") + +pico_add_doxygen_pre_define("PICO_RP2040=0") +pico_add_doxygen_pre_define("PICO_RP2350=1") +pico_add_doxygen_enabled_section(rp2350_specific) + +include(cmake/rp2_common.cmake) + diff --git a/src/rp2350/README.md b/src/rp2350/README.md new file mode 100644 index 000000000..7a710171d --- /dev/null +++ b/src/rp2350/README.md @@ -0,0 +1,6 @@ +This directory contains files specific to the RP2350 hardware. It is only used when building for RP2350 platforms, i.e. +`PICO_PLATFORM=rp2350-arm-s` or `PICO_PLATFORM=rp235-riscv` + +`hardware_regs` contains low level hardware register #defines autogenerated from the RP2350 chip definition itself. + +`hardware_structs` contains C structures for accessing memory mapped registers diff --git a/src/rp2350/boot_stage2/BUILD.bazel b/src/rp2350/boot_stage2/BUILD.bazel new file mode 100644 index 000000000..e831c638c --- /dev/null +++ b/src/rp2350/boot_stage2/BUILD.bazel @@ -0,0 +1,146 @@ +# Always include these libraries through //src/rp2_common:*! +# This ensures that you'll get the right headers for the MCU you're targeting. + +load("@bazel_skylib//rules:copy_file.bzl", "copy_file") +load("@bazel_skylib//rules:run_binary.bzl", "run_binary") +load("@rules_python//python:defs.bzl", "py_binary") +load("//bazel/toolchain:objcopy.bzl", "objcopy_to_bin") +load("//bazel/util:multiple_choice_flag.bzl", "declare_flag_choices", "flag_choice") +load("//bazel/util:transition.bzl", "rp2040_bootloader_binary") + +# There's a lot of implementation details in here that shouldn't be considered +# stable, so allowlist visibility to just the public-facing pieces. +package(default_visibility = ["//visibility:private"]) + +# Known choices for boot2: +BOOT2_CHOICES = [ + "boot2_at25sf128a", + "boot2_generic_03h", + "boot2_is25lp080", + "boot2_usb_blinky", + "boot2_w25q080", + "boot2_w25x10cl", + "compile_time_choice", +] + +BOOT2_CHOICE_FILES = [c + ".S" for c in BOOT2_CHOICES] + +BOOT2_CHOICE_FILE_MAP = {c: [c + ".S"] for c in BOOT2_CHOICES} + +BOOT2_CHOICE_DEFINE_MAP = {c: ['PICO_BUILD_BOOT_STAGE2_NAME=\\"{}\\"'.format(c)] for c in BOOT2_CHOICES} + +# Define shouldn't be set for compile_time_choice. +BOOT2_CHOICE_DEFINE_MAP["compile_time_choice"] = [] + +cc_library( + name = "config", + hdrs = [ + "asminclude/boot2_helpers/exit_from_boot2.S", + "asminclude/boot2_helpers/read_flash_sreg.S", + "asminclude/boot2_helpers/wait_qmi_ready.S", + "include/boot_stage2/config.h", + ] + BOOT2_CHOICE_FILES, + defines = select(flag_choice( + "//bazel/config:PICO_DEFAULT_BOOT_STAGE2", + ":__pkg__", + BOOT2_CHOICE_DEFINE_MAP, + )), + includes = [ + "asminclude", + "include", + ], + target_compatible_with = ["//bazel/constraint:rp2350"], + visibility = ["//visibility:public"], +) + +# Creates a config_setting for each known boot2 option with the name: +# PICO_DEFAULT_BOOT_STAGE2_[choice] +declare_flag_choices( + "//bazel/config:PICO_DEFAULT_BOOT_STAGE2", + BOOT2_CHOICES, +) + +filegroup( + name = "build_selected_boot2", + srcs = select(flag_choice( + "//bazel/config:PICO_DEFAULT_BOOT_STAGE2", + ":__pkg__", + BOOT2_CHOICE_FILE_MAP, + )), + visibility = ["//src/rp2_common:__pkg__"], +) + +cc_binary( + name = "boot_stage2_elf_actual", + srcs = ["//bazel/config:PICO_DEFAULT_BOOT_STAGE2_FILE"], + copts = ["-fPIC"], + # Incompatible with section garbage collection. + features = ["-gc_sections"], + linkopts = [ + "-Wl,--no-gc-sections", + "-nostartfiles", + "-Wl,--entry=_stage2_boot", + "-T$(location boot_stage2.ld)", + ], + # this does nothing if someone passes --custom_malloc, so the + # rp2040_bootloader_binary transition forcibly clobbers --custom_malloc. + malloc = "//bazel:empty_cc_lib", + tags = ["manual"], # Only build as an explicit dependency. + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + "boot_stage2.ld", + ":config", + "//src/common/pico_base_headers", + "//src/rp2_common:pico_platform_internal", + ], +) + +# Always build the bootloader with the bootloader-specific platform. +rp2040_bootloader_binary( + name = "boot_stage2_elf", + src = "boot_stage2_elf_actual", +) + +objcopy_to_bin( + name = "boot_stage2_bin", + src = ":boot_stage2_elf", + out = "boot_stage2.bin", + target_compatible_with = ["//bazel/constraint:rp2350"], +) + +# WORKAROUND: Python rules always require a .py extension. +copy_file( + name = "copy_tool_to_py", + src = "pad_checksum", + out = "pad_checksum_tool.py", + target_compatible_with = ["//bazel/constraint:host"], +) + +py_binary( + name = "pad_checksum_tool", + srcs = ["pad_checksum_tool.py"], + target_compatible_with = ["//bazel/constraint:host"], +) + +run_binary( + name = "boot_stage2_padded", + srcs = [":boot_stage2_bin"], + outs = ["boot_stage2.S"], + args = [ + "-s 0xffffffff", + "$(location boot_stage2_bin)", + "$(location boot_stage2.S)", + ], + target_compatible_with = ["//bazel/constraint:rp2350"], + tool = ":pad_checksum_tool", +) + +cc_library( + name = "boot_stage2", + srcs = [":boot_stage2_padded"], + target_compatible_with = ["//bazel/constraint:rp2350"], + visibility = ["//src/rp2_common:__pkg__"], + # This isn't referenced as a symbol, so alwayslink is required to ensure + # it doesn't get dropped before the linker script can find it. + alwayslink = True, +) diff --git a/src/rp2350/boot_stage2/CMakeLists.txt b/src/rp2350/boot_stage2/CMakeLists.txt new file mode 100644 index 000000000..bf41eb233 --- /dev/null +++ b/src/rp2350/boot_stage2/CMakeLists.txt @@ -0,0 +1,107 @@ +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, type=string, group=build +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the latter is set to src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, type=string, default=compile_time_choice, group=build + +if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) + set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) + message("Using PICO_DEFAULT_BOOT_STAGE2_FILE from environment ('${PICO_DEFAULT_BOOT_STAGE2_FILE}')") +elseif (PICO_DEFAULT_BOOT_STAGE2_FILE) + # explicitly set, so cache it + set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot stage 2 source file" FORCE) +endif() + +set(PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME compile_time_choice) # local var +if (NOT PICO_DEFAULT_BOOT_STAGE2_FILE) + if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2}) + set(PICO_DEFAULT_BOOT_STAGE2 $ENV{PICO_DEFAULT_BOOT_STAGE2}) + message("Using PICO_DEFAULT_BOOT_STAGE2 from environment ('${PICO_DEFAULT_BOOT_STAGE2}')") + endif() + if (NOT DEFINED PICO_DEFAULT_BOOT_STAGE2) + set(PICO_DEFAULT_BOOT_STAGE2 ${PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME}) + endif() + set(PICO_DEFAULT_BOOT_STAGE2 "${PICO_DEFAULT_BOOT_STAGE2}" CACHE STRING "boot stage 2 short name" FORCE) + set(PICO_DEFAULT_BOOT_STAGE2_FILE "${CMAKE_CURRENT_LIST_DIR}/${PICO_DEFAULT_BOOT_STAGE2}.S") +endif() + +if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE}) + message(FATAL_ERROR "Specified boot stage 2 source '${PICO_DEFAULT_BOOT_STAGE2_FILE}' does not exist.") +endif() +pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE) + +# needed by function below +set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") + +pico_add_library(boot_stage2_headers) +target_include_directories(boot_stage2_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +# by convention the first source file name without extension is used for the binary info name +function(pico_define_boot_stage2 NAME SOURCES) + add_executable(${NAME} + ${SOURCES} + ) + + # todo bit of an abstraction failure - revisit for Clang support anyway + if (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${NAME} PRIVATE "-nostdlib") + else () + target_link_options(${NAME} PRIVATE "--specs=nosys.specs") + target_link_options(${NAME} PRIVATE "-nostartfiles") + endif () + + # boot2_helpers include dir + target_include_directories(${NAME} PRIVATE ${PICO_BOOT_STAGE2_DIR}/asminclude) + + target_link_libraries(${NAME} hardware_regs boot_stage2_headers) + target_link_options(${NAME} PRIVATE "LINKER:--script=${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld") + set_target_properties(${NAME} PROPERTIES LINK_DEPENDS ${PICO_BOOT_STAGE2_DIR}/boot_stage2.ld) + + pico_add_dis_output(${NAME}) + pico_add_map_output(${NAME}) + + set(ORIGINAL_BIN ${CMAKE_CURRENT_BINARY_DIR}/${NAME}.bin) + set(PADDED_CHECKSUMMED_ASM ${CMAKE_CURRENT_BINARY_DIR}/${NAME}_padded_checksummed.S) + + find_package (Python3 REQUIRED COMPONENTS Interpreter) + + add_custom_target(${NAME}_bin DEPENDS ${ORIGINAL_BIN}) + add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${ORIGINAL_BIN}) + + add_custom_target(${NAME}_padded_checksummed_asm DEPENDS ${PADDED_CHECKSUMMED_ASM}) + add_custom_command(OUTPUT ${PADDED_CHECKSUMMED_ASM} DEPENDS ${ORIGINAL_BIN} + COMMAND ${Python3_EXECUTABLE} ${PICO_BOOT_STAGE2_DIR}/pad_checksum -s 0xffffffff -a $ ${ORIGINAL_BIN} ${PADDED_CHECKSUMMED_ASM} + ) + + add_library(${NAME}_library INTERFACE) + add_dependencies(${NAME}_library ${NAME}_padded_checksummed_asm) + # not strictly (or indeed actually) a link library, but this avoids dependency cycle + target_link_libraries(${NAME}_library INTERFACE ${PADDED_CHECKSUMMED_ASM}) + target_link_libraries(${NAME}_library INTERFACE boot_stage2_headers) + + list(GET SOURCES 0 FIRST_SOURCE) + get_filename_component(BOOT_STAGE2_BI_NAME ${FIRST_SOURCE} NAME_WE) + + # we only set the PICO_BUILD_STAGE2_NAME if it isn't 'compile_time_choice' + if (NOT BOOT_STAGE2_BI_NAME STREQUAL PICO_BOOT_STAGE2_COMPILE_TIME_CHOICE_NAME) + target_compile_definitions(${NAME} INTERFACE + -DPICO_BUILD_BOOT_STAGE2_NAME="${BOOT_STAGE2_BI_NAME}") + target_compile_definitions(${NAME}_library INTERFACE + -DPICO_BUILD_BOOT_STAGE2_NAME="${BOOT_STAGE2_BI_NAME}") + endif() +endfunction() + +macro(pico_set_boot_stage2 TARGET NAME) + get_target_property(target_type ${TARGET} TYPE) + if ("EXECUTABLE" STREQUAL "${target_type}") + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BOOT_STAGE2 "${NAME}") + else() + message(FATAL_ERROR "boot stage 2 implementation must be set on executable not library") + endif() +endmacro() + +pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE}) + +# Create a new boot stage 2 target using the default implementation for the current build (PICO_BOARD derived) +function(pico_clone_default_boot_stage2 NAME) + pico_define_boot_stage2(${NAME} ${PICO_DEFAULT_BOOT_STAGE2_FILE}) +endfunction() + +pico_promote_common_scope_vars() diff --git a/src/rp2350/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S b/src/rp2350/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S new file mode 100644 index 000000000..cadcd0132 --- /dev/null +++ b/src/rp2350/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2 +#define _BOOT2_HELPER_EXIT_FROM_BOOT2 + +// Always return through saved ra/lr. On RP2350, boot2 is not responsible for entering +// the flash image. It's just a relocatable function that sets up QMI and flash +// for the best possible XIP. + +#ifdef __riscv + jr t0 +#else + pop {pc} +#endif + +#endif diff --git a/src/rp2350/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S b/src/rp2350/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S new file mode 100644 index 000000000..8a6903867 --- /dev/null +++ b/src/rp2350/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT2_HELPER_READ_FLASH_SREG +#define _BOOT2_HELPER_READ_FLASH_SREG + +#include "boot2_helpers/wait_qmi_ready.S" + +// Pass status read cmd into r0/a0. +// Returns status value in r0/a0. + +.global read_flash_sreg +.type read_flash_sreg,%function +#ifdef __riscv +read_flash_sreg: + // wait_qmi_ready does not clobber t1, so use this rather than stack. + mv t1, ra + sw a0, QMI_DIRECT_TX_OFFSET(a3) + // Dummy byte: + sw a0, QMI_DIRECT_TX_OFFSET(a3) + + jal wait_qmi_ready + // Discard first byte, return second + lw a0, QMI_DIRECT_RX_OFFSET(a3) + lw a0, QMI_DIRECT_RX_OFFSET(a3) + jr t1 + +#else + +.thumb_func +read_flash_sreg: + push {lr} + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + // Dummy byte: + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + + bl wait_qmi_ready + // Discard first byte, return second + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] + + pop {pc} + +#endif + +#endif diff --git a/src/rp2350/boot_stage2/asminclude/boot2_helpers/wait_qmi_ready.S b/src/rp2350/boot_stage2/asminclude/boot2_helpers/wait_qmi_ready.S new file mode 100644 index 000000000..cf191807f --- /dev/null +++ b/src/rp2350/boot_stage2/asminclude/boot2_helpers/wait_qmi_ready.S @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT2_HELPER_WAIT_SSI_READY +#define _BOOT2_HELPER_WAIT_SSI_READY + +// Wait for QMI direct mode to go idle. Clobbers r0/a0 (Arm/RISC-V) + +#ifdef __riscv + +wait_qmi_ready: +1: + lw a0, QMI_DIRECT_CSR_OFFSET(a3) + andi a0, a0, QMI_DIRECT_CSR_BUSY_BITS + bnez a0, 1b + + ret + +#else + +wait_qmi_ready: +1: + ldr r0, [r3, #QMI_DIRECT_CSR_OFFSET] + lsrs r0, r0, #QMI_DIRECT_CSR_BUSY_LSB + 1 + bcs 1b + + bx lr + +#endif + +#endif diff --git a/src/rp2_common/boot_stage2/boot2_at25sf128a.S b/src/rp2350/boot_stage2/boot2_at25sf128a.S similarity index 96% rename from src/rp2_common/boot_stage2/boot2_at25sf128a.S rename to src/rp2350/boot_stage2/boot2_at25sf128a.S index f013ea997..8682badea 100644 --- a/src/rp2_common/boot_stage2/boot2_at25sf128a.S +++ b/src/rp2350/boot_stage2/boot2_at25sf128a.S @@ -30,6 +30,8 @@ #include "hardware/regs/ssi.h" #include "hardware/regs/pads_qspi.h" +// todo port to QMI + // ---------------------------------------------------------------------------- // Config section // ---------------------------------------------------------------------------- @@ -90,11 +92,7 @@ pico_default_asm_setup .section .text -// The exit point is passed in lr. If entered from bootrom, this will be the -// flash address immediately following this second stage (0x10000100). -// Otherwise it will be a return address -- second stage being called as a -// function by user code, after copying out of XIP region. r3 holds SSI base, -// r0...2 used as temporaries. Other GPRs not used. +// On RP2350 boot stage2 is always called as a regular function, and should return normally regular_func _stage2_boot push {lr} diff --git a/src/rp2350/boot_stage2/boot2_generic_03h.S b/src/rp2350/boot_stage2/boot2_generic_03h.S new file mode 100644 index 000000000..4e14a4c7b --- /dev/null +++ b/src/rp2350/boot_stage2/boot2_generic_03h.S @@ -0,0 +1,121 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Anything which responds to 03h serial read command +// +// Details: * Configure SSI to translate each APB read into a 03h command +// * 8 command clocks, 24 address clocks and 32 data clocks +// * This enables you to boot from almost anything: you can pretty +// much solder a potato to your PCB, or a piece of cheese +// * The tradeoff is performance around 3x worse than QSPI XIP +// +// Building: * This code must be position-independent, and use stack only +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/qmi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 4 +#endif +#if (PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB) & ~QMI_M0_TIMING_CLKDIV_BITS +#error "CLKDIV greater than maximum" +#endif + +// RX sampling delay is measured in units of one half clock cycle. + +#ifndef PICO_FLASH_SPI_RXDELAY +#define PICO_FLASH_SPI_RXDELAY 1 +#endif +#if (PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB) & ~QMI_M0_TIMING_RXDELAY_BITS +#error "RX delay greater than maximum" +#endif + +#define CMD_READ 0x03 + +// ---------------------------------------------------------------------------- +// Register initialisation values -- same in Arm/RISC-V code. +// ---------------------------------------------------------------------------- + +// The QMI is automatically configured for 03h XIP straight out of reset, +// but this code can't assume it's still in that state. Set up memory +// window 0 for 03h serial reads. + +// Setup timing parameters: short sequential-access cooldown, configured +// CLKDIV and RXDELAY, and no constraints on CS max assertion, CS min +// deassertion, or page boundary burst breaks. + +#define INIT_M0_TIMING (\ + 1 << QMI_M0_TIMING_COOLDOWN_LSB |\ + PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB |\ + PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB |\ +0) + +// Set command constants +#define INIT_M0_RCMD (\ + CMD_READ << QMI_M0_RCMD_PREFIX_LSB |\ +0) + +// Set read format to all-serial with a command prefix +#define INIT_M0_RFMT (\ + QMI_M0_RFMT_PREFIX_WIDTH_VALUE_S << QMI_M0_RFMT_PREFIX_WIDTH_LSB |\ + QMI_M0_RFMT_ADDR_WIDTH_VALUE_S << QMI_M0_RFMT_ADDR_WIDTH_LSB |\ + QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_S << QMI_M0_RFMT_SUFFIX_WIDTH_LSB |\ + QMI_M0_RFMT_DUMMY_WIDTH_VALUE_S << QMI_M0_RFMT_DUMMY_WIDTH_LSB |\ + QMI_M0_RFMT_DATA_WIDTH_VALUE_S << QMI_M0_RFMT_DATA_WIDTH_LSB |\ + QMI_M0_RFMT_PREFIX_LEN_VALUE_8 << QMI_M0_RFMT_PREFIX_LEN_LSB |\ +0) + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +pico_default_asm_setup + +.section .text + +// On RP2350 boot stage2 is always called as a regular function, and should return normally +regular_func _stage2_boot +#ifdef __riscv + mv t0, ra + li a3, XIP_QMI_BASE + li a0, INIT_M0_TIMING + sw a0, QMI_M0_TIMING_OFFSET(a3) + li a0, INIT_M0_RCMD + sw a0, QMI_M0_RCMD_OFFSET(a3) + li a0, INIT_M0_RFMT + sw a0, QMI_M0_RFMT_OFFSET(a3) +#else + push {lr} + ldr r3, =XIP_QMI_BASE + ldr r0, =INIT_M0_TIMING + str r0, [r3, #QMI_M0_TIMING_OFFSET] + ldr r0, =INIT_M0_RCMD + str r0, [r3, #QMI_M0_RCMD_OFFSET] + ldr r0, =INIT_M0_RFMT + str r0, [r3, #QMI_M0_RFMT_OFFSET] +#endif + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +#ifndef __riscv +.global literals +literals: +.ltorg +#endif diff --git a/src/rp2_common/boot_stage2/boot2_is25lp080.S b/src/rp2350/boot_stage2/boot2_is25lp080.S similarity index 98% rename from src/rp2_common/boot_stage2/boot2_is25lp080.S rename to src/rp2350/boot_stage2/boot2_is25lp080.S index 80b7a74a3..e5cc2d4f4 100644 --- a/src/rp2_common/boot_stage2/boot2_is25lp080.S +++ b/src/rp2350/boot_stage2/boot2_is25lp080.S @@ -31,6 +31,8 @@ #include "hardware/regs/addressmap.h" #include "hardware/regs/ssi.h" +// todo port to QMI + // ---------------------------------------------------------------------------- // Config section // ---------------------------------------------------------------------------- @@ -82,7 +84,8 @@ pico_default_asm_setup -.section .text +.section text +// On RP2350 boot stage2 is always called as a regular function, and should return normally regular_func _stage2_boot push {lr} diff --git a/src/rp2350/boot_stage2/boot2_usb_blinky.S b/src/rp2350/boot_stage2/boot2_usb_blinky.S new file mode 100644 index 000000000..4d280e087 --- /dev/null +++ b/src/rp2350/boot_stage2/boot2_usb_blinky.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" + +// Stub second stage which calls into USB bootcode, with parameters. +// USB boot takes two parameters: +// - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all +// - A mask of interfaces to disable. Bit 0 disables MSC, bit 1 disables PICOBoot +// The bootrom passes 0 for both of these parameters, but user code (or this +// second stage) can pass anything. + +#define USB_BOOT_MSD_AND_PICOBOOT 0x0 +#define USB_BOOT_MSD_ONLY 0x2 +#define USB_BOOT_PICOBOOT_ONLY 0x1 + +// Config +#define ACTIVITY_LED 0 +#define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT + +pico_default_asm_setup + +.section .text + +// On RP2350 boot stage2 is always called as a regular function, and should return normally +regular_func _stage2_boot + movs r7, #0x14 // Pointer to _well_known pointer table in ROM + ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table + ldrh r7, [r7, #4] // Offset 4 is 16 bit pointer to table lookup routine + ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot + blx r7 + cmp r0, #0 + beq dead + + mov r7, r0 + ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use + movs r1, #BOOT_MODE + blx r7 + +dead: + wfi + b dead + +.global literals +literals: +.ltorg + +.end diff --git a/src/rp2350/boot_stage2/boot2_w25q080.S b/src/rp2350/boot_stage2/boot2_w25q080.S new file mode 100644 index 000000000..9d37e5f5a --- /dev/null +++ b/src/rp2350/boot_stage2/boot2_w25q080.S @@ -0,0 +1,343 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2022 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// +// Device: Winbond W25Q080 +// Also supports W25Q16JV (which has some different SR instructions) +// Also supports AT25SF081 +// Also supports S25FL132K0 +// +// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode +// +// Details: * Check status register 2 to determine if QSPI mode is enabled, +// and perform an SR2 programming cycle if necessary. +// * Use SSI to perform a dummy 0xEB read command, with the mode +// continuation bits set, so that the flash will not require +// 0xEB instruction prefix on subsequent reads. +// * Configure SSI to write address, mode bits, but no instruction. +// SSI + flash are now jointly in a state where continuous reads +// can take place. +// * Jump to exit pointer passed in via lr. Bootrom passes null, +// in which case this code uses a default 256 byte flash offset +// +// Building: * This code must be position-independent, and use stack only +// * The code will be padded to a size of 256 bytes, including a +// 4-byte checksum. Therefore code size cannot exceed 252 bytes. +// ---------------------------------------------------------------------------- + +#include "pico/asm_helper.S" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/pads_qspi.h" +#include "hardware/regs/qmi.h" + +// ---------------------------------------------------------------------------- +// Config section +// ---------------------------------------------------------------------------- +// It should be possible to support most flash devices by modifying this section + +// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV. +// This must be a positive integer. +// The bootrom is very conservative with SPI frequency, but here we should be +// as aggressive as possible. + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif +#if (PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB) & ~QMI_M0_TIMING_CLKDIV_BITS +#error "CLKDIV greater than maximum" +#endif + +// RX sampling delay is measured in units of one half clock cycle. + +#ifndef PICO_FLASH_SPI_RXDELAY +#define PICO_FLASH_SPI_RXDELAY 2 +#endif +#if (PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB) & ~QMI_M0_TIMING_RXDELAY_BITS +#error "RX delay greater than maximum" +#endif + +// Define interface width: single/dual/quad IO +#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD + +// For W25Q080 this is the "Read data fast quad IO" instruction: +#define CMD_READ 0xeb + +// "Mode bits" are 8 special bits sent immediately after +// the address bits in a "Read Data Fast Quad I/O" command sequence. +// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the +// next read does not require the 0xeb instruction prefix. +#define MODE_CONTINUOUS_READ 0xa0 + +// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles +// are required. +#define WAIT_CYCLES 4 + +// If defined, we will read status reg, compare to SREG_DATA, and overwrite +// with our value if the SR doesn't match. +// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to +// SR2 (31h cmd) as the latter command isn't supported by WX25Q080. +// This isn't great because it will remove block protections. +// A better solution is to use a volatile SR write if your device supports it. +#define PROGRAM_STATUS_REG + +#define CMD_WRITE_ENABLE 0x06 +#define CMD_READ_STATUS 0x05 +#define CMD_READ_STATUS2 0x35 +#define CMD_WRITE_STATUS 0x01 +#define SREG_DATA 0x02 // Enable quad-SPI mode + +// ---------------------------------------------------------------------------- +// Register initialisation values -- same in Arm/RISC-V code. +// ---------------------------------------------------------------------------- + +// SCLK: 8mA drive, no slew limiting, input buffer disabled +#define INIT_PAD_SCLK (\ + 2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | \ + PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS | \ +0) + +// Need to use direct serial mode to send SR commands. Choose a +// conservative direct-mode divisor (5 MHz at 150 MHz clk_sys) +// since the XIP-mode divisor may be unsafe without an RX delay. +#define INIT_DIRECT_CSR (\ + 30 << QMI_DIRECT_CSR_CLKDIV_LSB | \ + QMI_DIRECT_CSR_EN_BITS | \ + QMI_DIRECT_CSR_AUTO_CS0N_BITS | \ +0) + +// Setup timing parameters: short sequential-access cooldown, configured +// CLKDIV and RXDELAY, and no constraints on CS max assertion, CS min +// deassertion, or page boundary burst breaks. +#define INIT_M0_TIMING (\ + 1 << QMI_M0_TIMING_COOLDOWN_LSB |\ + PICO_FLASH_SPI_RXDELAY << QMI_M0_TIMING_RXDELAY_LSB |\ + PICO_FLASH_SPI_CLKDIV << QMI_M0_TIMING_CLKDIV_LSB |\ +0) + +// Set command constants (e.g. EBh + A0h) +#define INIT_M0_RCMD (\ + CMD_READ << QMI_M0_RCMD_PREFIX_LSB |\ + MODE_CONTINUOUS_READ << QMI_M0_RCMD_SUFFIX_LSB |\ +0) + +// Set read format (serial command prefix, everything else quad) +// Initial dummy transfer has a serial EBh prefix, and has XIP mode bits +// set after the address. Subsequent transfers don't need the prefix, as long +// as the mode bits are set correctly. +#define INIT_M0_RFMT (\ + QMI_M0_RFMT_PREFIX_WIDTH_VALUE_S << QMI_M0_RFMT_PREFIX_WIDTH_LSB |\ + QMI_M0_RFMT_ADDR_WIDTH_VALUE_Q << QMI_M0_RFMT_ADDR_WIDTH_LSB |\ + QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_Q << QMI_M0_RFMT_SUFFIX_WIDTH_LSB |\ + QMI_M0_RFMT_DUMMY_WIDTH_VALUE_Q << QMI_M0_RFMT_DUMMY_WIDTH_LSB |\ + QMI_M0_RFMT_DATA_WIDTH_VALUE_Q << QMI_M0_RFMT_DATA_WIDTH_LSB |\ + QMI_M0_RFMT_PREFIX_LEN_VALUE_8 << QMI_M0_RFMT_PREFIX_LEN_LSB |\ + QMI_M0_RFMT_SUFFIX_LEN_VALUE_8 << QMI_M0_RFMT_SUFFIX_LEN_LSB |\ + WAIT_CYCLES << QMI_M0_RFMT_DUMMY_LEN_LSB |\ +0) + +// ---------------------------------------------------------------------------- +// Start of 2nd Stage Boot Code +// ---------------------------------------------------------------------------- + +pico_default_asm_setup +.section .text + +// ---------------------------------------------------------------------------- +// RISC-V implementation + +#ifdef __riscv + +// On RP2350 boot stage2 is always called as a regular function, and should return normally +regular_func _stage2_boot + mv t0, ra +_pad_config: + li a3, PADS_QSPI_BASE + li a0, INIT_PAD_SCLK + sw a0, PADS_QSPI_GPIO_QSPI_SCLK_OFFSET(a3) + // SDx: disable input Schmitt to reduce delay + li a3, PADS_QSPI_BASE + REG_ALIAS_CLR_BITS + li a0, PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS + sw a0, PADS_QSPI_GPIO_QSPI_SD0_OFFSET(a3) + sw a0, PADS_QSPI_GPIO_QSPI_SD1_OFFSET(a3) + sw a0, PADS_QSPI_GPIO_QSPI_SD2_OFFSET(a3) + sw a0, PADS_QSPI_GPIO_QSPI_SD3_OFFSET(a3) + + li a3, XIP_QMI_BASE + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: + li a1, INIT_DIRECT_CSR + sw a1, QMI_DIRECT_CSR_OFFSET(a3) + // Wait for cooldown on last XIP transfer to expire, by polling BUSY +1: + lw a1, QMI_DIRECT_CSR_OFFSET(a3) + andi a1, a1, QMI_DIRECT_CSR_BUSY_BITS + bnez a1, 1b + + // Check whether SR needs updating + li a0, CMD_READ_STATUS2 + jal read_flash_sreg + addi a0, a0, -SREG_DATA + beqz a0, _skip_sreg_programming + + // Send write enable command, discard RX + li a0, CMD_WRITE_ENABLE + sw a0, QMI_DIRECT_TX_OFFSET(a3) + jal wait_qmi_ready + lw a0, QMI_DIRECT_RX_OFFSET(a3) + + // Send status write command followed by data bytes + li a0, CMD_WRITE_STATUS + sw a0, QMI_DIRECT_TX_OFFSET(a3) + sw zero, QMI_DIRECT_TX_OFFSET(a3) + li a0, SREG_DATA + sw a0, QMI_DIRECT_TX_OFFSET(a3) + jal wait_qmi_ready + lw a0, QMI_DIRECT_RX_OFFSET(a3) + lw a0, QMI_DIRECT_RX_OFFSET(a3) + lw a0, QMI_DIRECT_RX_OFFSET(a3) + + // Poll status register for write completion +1: + li a0, CMD_READ_STATUS + jal read_flash_sreg + andi a0, a0, 0x1 + bnez a0, 1b + +_skip_sreg_programming: + // Disable direct mode + andi a1, a1, ~QMI_DIRECT_CSR_EN_BITS + sw a1, QMI_DIRECT_CSR_OFFSET(a3) +#endif + +_qmi_config: + li a0, INIT_M0_TIMING + sw a0, QMI_M0_TIMING_OFFSET(a3) + li a0, INIT_M0_RCMD + sw a0, QMI_M0_RCMD_OFFSET(a3) + li a0, INIT_M0_RFMT + sw a0, QMI_M0_RFMT_OFFSET(a3) + + // Dummy transfer + li a1, XIP_NOCACHE_NOALLOC_BASE + lw a1, (a1) + + // Set prefix length to 0, as flash no longer expects to see commands + bclri a0, a0, QMI_M0_RFMT_PREFIX_LEN_LSB + sw a0, QMI_M0_RFMT_OFFSET(a3) + +// ---------------------------------------------------------------------------- +// Arm implementation + +#else + +// On RP2350 boot stage2 is always called as a regular function, and should return normally +regular_func _stage2_boot + push {lr} +_pad_config: + ldr r3, =PADS_QSPI_BASE + movs r0, INIT_PAD_SCLK + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET] + // SDx: disable input Schmitt to reduce delay + adds r3, #REG_ALIAS_CLR_BITS + movs r0, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET] + str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET] + + adds r3, (XIP_QMI_BASE - (PADS_QSPI_BASE + REG_ALIAS_CLR_BITS)) + +// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode +// (i.e. turn WPn and HOLDn into IO2/IO3) +#ifdef PROGRAM_STATUS_REG +program_sregs: + + // Need to use direct serial mode to send SR commands. Choose a + // conservative direct-mode divisor (5 MHz at 150 MHz clk_sys) + // since the XIP-mode divisor may be unsafe without an RX delay. + ldr r1, =INIT_DIRECT_CSR + str r1, [r3, #QMI_DIRECT_CSR_OFFSET] + // Need to poll for the cooldown on the last XIP transfer to expire + // (via direct-mode BUSY flag) before it is safe to perform the first + // direct-mode operation +1: + ldr r0, [r3, #QMI_DIRECT_CSR_OFFSET] + tst r0, #QMI_DIRECT_CSR_BUSY_BITS + bne 1b + + // Check whether SR needs updating + movs r0, #CMD_READ_STATUS2 + bl read_flash_sreg + cmp r0, #SREG_DATA + beq _skip_sreg_programming + + // Send write enable command, discard RX + movs r0, #CMD_WRITE_ENABLE + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + bl wait_qmi_ready + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] + + // Send status write command followed by data bytes + movs r0, #CMD_WRITE_STATUS + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + movs r0, #0 + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + movs r0, #SREG_DATA + str r0, [r3, #QMI_DIRECT_TX_OFFSET] + bl wait_qmi_ready + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] + ldr r0, [r3, #QMI_DIRECT_RX_OFFSET] + + // Poll status register for write completion +1: + movs r0, #CMD_READ_STATUS + bl read_flash_sreg + lsrs r0, #1 + bcs 1b + +_skip_sreg_programming: + // Disable direct mode + bics r1, #QMI_DIRECT_CSR_EN_BITS + str r1, [r3, #QMI_DIRECT_CSR_OFFSET] + +#endif + +_qmi_config: + ldr r0, =INIT_M0_TIMING + str r0, [r3, #QMI_M0_TIMING_OFFSET] + ldr r0, =INIT_M0_RCMD + str r0, [r3, #QMI_M0_RCMD_OFFSET] + ldr r0, =INIT_M0_RFMT + str r0, [r3, #QMI_M0_RFMT_OFFSET] + + // Dummy transfer + mov r1, #XIP_NOCACHE_NOALLOC_BASE + ldrb r1, [r1] + + // Set prefix length to 0, as flash no longer expects to see commands + bic r0, #QMI_M0_RFMT_PREFIX_LEN_BITS + str r0, [r3, #QMI_M0_RFMT_OFFSET] + +#endif + +// ---------------------------------------------------------------------------- + +// Pull in standard exit routine +#include "boot2_helpers/exit_from_boot2.S" + +// Common functions +#include "boot2_helpers/wait_qmi_ready.S" +#ifdef PROGRAM_STATUS_REG +#include "boot2_helpers/read_flash_sreg.S" +#endif + +#ifndef __riscv +.global literals +literals: +.ltorg +#endif diff --git a/src/rp2_common/boot_stage2/boot2_w25x10cl.S b/src/rp2350/boot_stage2/boot2_w25x10cl.S similarity index 98% rename from src/rp2_common/boot_stage2/boot2_w25x10cl.S rename to src/rp2350/boot_stage2/boot2_w25x10cl.S index 89d2cd10e..6cdf1ec26 100644 --- a/src/rp2_common/boot_stage2/boot2_w25x10cl.S +++ b/src/rp2350/boot_stage2/boot2_w25x10cl.S @@ -42,6 +42,8 @@ pico_default_asm_setup +// todo port to QMI + // ---------------------------------------------------------------------------- // The "System Control Block" is a set of internal Cortex-M0+ control registers // that are memory mapped and accessed like any other H/W register. They have @@ -75,8 +77,7 @@ pico_default_asm_setup .section .text -// This code will get copied to 0x20000000 and then executed - +// On RP2350 boot stage2 is always called as a regular function, and should return normally regular_func _stage2_boot push {lr} ldr r3, =XIP_SSI_BASE // Use as base address where possible diff --git a/src/rp2350/boot_stage2/boot_stage2.ld b/src/rp2350/boot_stage2/boot_stage2.ld new file mode 100644 index 000000000..0162414a8 --- /dev/null +++ b/src/rp2350/boot_stage2/boot_stage2.ld @@ -0,0 +1,13 @@ +MEMORY { + /* We are loaded to the top 256 bytes of SRAM, which is above the bootrom + stack. Note 4 bytes occupied by checksum. */ + SRAM(rx) : ORIGIN = 0x20081f00, LENGTH = 252 +} + +SECTIONS { + . = ORIGIN(SRAM); + .text : { + *(.entry) + *(.text) + } >SRAM +} diff --git a/src/rp2350/boot_stage2/compile_time_choice.S b/src/rp2350/boot_stage2/compile_time_choice.S new file mode 100644 index 000000000..5aa2b96cd --- /dev/null +++ b/src/rp2350/boot_stage2/compile_time_choice.S @@ -0,0 +1,19 @@ +// ---------------------------------------------------------------------------- +// Second stage boot code +// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------- +// +// This implementation uses the PICO_BOOT_STAGE2_CHOOSE_ preprocessor defines to pick +// amongst a menu of known boot stage 2 implementations, allowing the board +// configuration header to be able to specify the boot stage 2 + +#include "boot_stage2/config.h" + +#ifdef PICO_BUILD_BOOT_STAGE2_NAME + // boot stage 2 is configured by cmake, so use the name specified there + #error PICO_BUILD_BOOT_STAGE2_NAME should not be defined for compile_time_choice builds +#else + // boot stage 2 is selected by board config header, and PICO_BOOT_STAGE2_ASM is set in boot_stage2/config.h + #include PICO_BOOT_STAGE2_ASM +#endif diff --git a/src/rp2350/boot_stage2/doc.h b/src/rp2350/boot_stage2/doc.h new file mode 100644 index 000000000..483dd682f --- /dev/null +++ b/src/rp2350/boot_stage2/doc.h @@ -0,0 +1,4 @@ +/** + * \defgroup boot_stage2 boot_stage2 + * \brief Second stage boot loaders responsible for setting up external flash + */ diff --git a/src/rp2350/boot_stage2/include/boot_stage2/config.h b/src/rp2350/boot_stage2/include/boot_stage2/config.h new file mode 100644 index 000000000..61f9b9b53 --- /dev/null +++ b/src/rp2350/boot_stage2/include/boot_stage2/config.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT_STAGE2_CONFIG_H_ +#define _BOOT_STAGE2_CONFIG_H_ + +// NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY + +#include "pico/config.h" + +// PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, Name of the boot stage 2 if selected in the build system, group=boot_stage2 +#ifdef PICO_BUILD_BOOT_STAGE2_NAME + #define _BOOT_STAGE2_SELECTED +#else + // check that multiple boot stage 2 options haven't been set... + +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_IS25LP080, Select boot2_is25lp080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_IS25LP080 + #define PICO_BOOT_STAGE2_CHOOSE_IS25LP080 0 +#elif PICO_BOOT_STAGE2_CHOOSE_IS25LP080 + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25Q080, Select boot2_w25q080 as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_W25Q080 + #define PICO_BOOT_STAGE2_CHOOSE_W25Q080 0 +#elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_W25X10CL, Select boot2_w25x10cl as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_W25X10CL + #define PICO_BOOT_STAGE2_CHOOSE_W25X10CL 0 +#elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_AT25SF128A, Select boot2_at25sf128a as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=0, group=boot_stage2 +#ifndef PICO_BOOT_STAGE2_CHOOSE_AT25SF128A + #define PICO_BOOT_STAGE2_CHOOSE_AT25SF128A 0 +#elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif + +// PICO_CONFIG: PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H, Select boot2_generic_03h as the boot stage 2 when no boot stage 2 selection is made by the CMake build, type=bool, default=1, group=boot_stage2 +#if defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) && PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H + #ifdef _BOOT_STAGE2_SELECTED + #error multiple boot stage 2 options chosen + #endif + #define _BOOT_STAGE2_SELECTED +#endif + +#endif // PICO_BUILD_BOOT_STAGE2_NAME + +#ifdef PICO_BUILD_BOOT_STAGE2_NAME + // boot stage 2 is configured by cmake, so use the name specified there + #define PICO_BOOT_STAGE2_NAME PICO_BUILD_BOOT_STAGE2_NAME +#else + // boot stage 2 is selected by board config header, so we have to do some work + #if PICO_BOOT_STAGE2_CHOOSE_IS25LP080 + #error "IS25LP080 boot2 is broken (FIXME)" + #define _BOOT_STAGE2 boot2_is25lp080 + #elif PICO_BOOT_STAGE2_CHOOSE_W25Q080 + #define _BOOT_STAGE2 boot2_w25q080 + #elif PICO_BOOT_STAGE2_CHOOSE_W25X10CL + #error "W25X10CL boot2 is broken (FIXME)" + #define _BOOT_STAGE2 boot2_w25x10cl + #elif PICO_BOOT_STAGE2_CHOOSE_AT25SF128A + #error "AT25SF128A boot2 is broken (FIXME)" + #define _BOOT_STAGE2 boot2_at25sf128a + #elif !defined(PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H) || PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H + #undef PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H + #define PICO_BOOT_STAGE2_CHOOSE_GENERIC_03H 1 + #define _BOOT_STAGE2 boot2_generic_03h + #else + #error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro + #endif + // we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion + #define _PICO__STRING(x) #x + #define _PICO__XSTRING(x) _PICO__STRING(x) + #define _PICO__CONCAT1(x, y) x ## y + #define PICO_BOOT_STAGE2_NAME _PICO__XSTRING(_BOOT_STAGE2) + #define PICO_BOOT_STAGE2_ASM _PICO__XSTRING(_PICO__CONCAT1(_BOOT_STAGE2,.S)) +#endif +#endif diff --git a/src/rp2350/boot_stage2/pad_checksum b/src/rp2350/boot_stage2/pad_checksum new file mode 100755 index 000000000..2cbe1ade2 --- /dev/null +++ b/src/rp2350/boot_stage2/pad_checksum @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 + +import argparse +import sys + + +def any_int(x): + try: + return int(x, 0) + except: + raise argparse.ArgumentTypeError("expected an integer, not '{!r}'".format(x)) + + +def bitrev(x, width): + return int("{:0{w}b}".format(x, w=width)[::-1], 2) + + +parser = argparse.ArgumentParser() +parser.add_argument("ifile", help="Input file (binary)") +parser.add_argument("ofile", help="Output file (assembly)") +parser.add_argument("-p", "--pad", help="Padded size (bytes), including 4-byte checksum, default 256", + type=any_int, default=256) +parser.add_argument("-s", "--seed", help="Checksum seed value, default 0", + type=any_int, default=0) +parser.add_argument("-a", "--arch", default="arm", choices=["arm", "riscv"]) +args = parser.parse_args() + +try: + idata = open(args.ifile, "rb").read() +except: + sys.exit("Could not open input file '{}'".format(args.ifile)) + +if len(idata) > args.pad: + sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad)) + +odata = idata + bytes(args.pad - len(idata)) + +# No CRC, as "boot2" is entered by crt0 rather than the bootrom. The bootrom +# can optionally perform a SHA-256 hash check of the entire image, and will +# always at least check for a metadata block which is a valid IMAGE_DEF, so +# the boot2 CRC is redundant. + +# try: +with open(args.ofile, "w") as ofile: + ofile.write("// Padded and checksummed version of: {}\n\n".format(args.ifile)) + if args.arch == "arm": + ofile.write(".cpu cortex-m0plus\n") + ofile.write(".thumb\n\n") + ofile.write(".section .boot2, \"ax\"\n\n") + ofile.write(".global __boot2_entry_point\n") + ofile.write("__boot2_entry_point:\n") + for offs in range(0, len(odata), 16): + chunk = odata[offs:min(offs + 16, len(odata))] + ofile.write(".byte {}\n".format(", ".join("0x{:02x}".format(b) for b in chunk))) +# except: + # sys.exit("Could not open output file '{}'".format(args.ofile)) diff --git a/src/rp2350/hardware_regs/BUILD.bazel b/src/rp2350/hardware_regs/BUILD.bazel new file mode 100644 index 000000000..b665bbbe3 --- /dev/null +++ b/src/rp2350/hardware_regs/BUILD.bazel @@ -0,0 +1,94 @@ +# Always include these libraries through //src/rp2_common:*! +# This ensures that you'll get the right headers for the MCU you're targeting. + +package( + default_visibility = [ + "//src/rp2350:__subpackages__", + "//src/rp2_common:__pkg__", + ], +) + +cc_library( + name = "platform_defs", + hdrs = [ + "include/hardware/platform_defs.h", + ], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:rp2350"], +) + +# Picotool needs this, so we can't strictly constrain compatibility. +cc_library( + name = "otp_data", + hdrs = [ + "include/hardware/regs/otp_data.h", + ], + includes = ["include"], + tags = ["manual"], + visibility = ["@picotool//:__subpackages__"], +) + +filegroup( + name = "otp_data_header", + srcs = ["include/hardware/regs/otp_data.h"], + tags = ["manual"], + visibility = ["@picotool//:__subpackages__"], +) + +cc_library( + name = "hardware_regs", + hdrs = [ + "include/hardware/platform_defs.h", + "include/hardware/regs/accessctrl.h", + "include/hardware/regs/adc.h", + "include/hardware/regs/addressmap.h", + "include/hardware/regs/bootram.h", + "include/hardware/regs/busctrl.h", + "include/hardware/regs/clocks.h", + "include/hardware/regs/coresight_trace.h", + "include/hardware/regs/dma.h", + "include/hardware/regs/dreq.h", + "include/hardware/regs/glitch_detector.h", + "include/hardware/regs/hstx_ctrl.h", + "include/hardware/regs/hstx_fifo.h", + "include/hardware/regs/i2c.h", + "include/hardware/regs/intctrl.h", + "include/hardware/regs/io_bank0.h", + "include/hardware/regs/io_qspi.h", + "include/hardware/regs/m33.h", + "include/hardware/regs/m33_eppb.h", + "include/hardware/regs/otp.h", + "include/hardware/regs/otp_data.h", + "include/hardware/regs/pads_bank0.h", + "include/hardware/regs/pads_qspi.h", + "include/hardware/regs/pio.h", + "include/hardware/regs/pll.h", + "include/hardware/regs/powman.h", + "include/hardware/regs/psm.h", + "include/hardware/regs/pwm.h", + "include/hardware/regs/qmi.h", + "include/hardware/regs/resets.h", + "include/hardware/regs/riscv_dm.h", + "include/hardware/regs/rosc.h", + "include/hardware/regs/rp_ap.h", + "include/hardware/regs/rvcsr.h", + "include/hardware/regs/sha256.h", + "include/hardware/regs/sio.h", + "include/hardware/regs/spi.h", + "include/hardware/regs/syscfg.h", + "include/hardware/regs/sysinfo.h", + "include/hardware/regs/tbman.h", + "include/hardware/regs/ticks.h", + "include/hardware/regs/timer.h", + "include/hardware/regs/trng.h", + "include/hardware/regs/uart.h", + "include/hardware/regs/usb.h", + "include/hardware/regs/usb_device_dpram.h", + "include/hardware/regs/watchdog.h", + "include/hardware/regs/xip.h", + "include/hardware/regs/xip_aux.h", + "include/hardware/regs/xosc.h", + ], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:rp2350"], +) diff --git a/src/rp2350/hardware_regs/CMakeLists.txt b/src/rp2350/hardware_regs/CMakeLists.txt new file mode 100644 index 000000000..082d44a7e --- /dev/null +++ b/src/rp2350/hardware_regs/CMakeLists.txt @@ -0,0 +1,4 @@ +add_library(hardware_regs INTERFACE) +add_library(hardware_regs_headers INTERFACE) +target_include_directories(hardware_regs_headers SYSTEM INTERFACE include) +pico_mirrored_target_link_libraries(hardware_regs INTERFACE hardware_base) diff --git a/src/rp2350/hardware_regs/RP2350.svd b/src/rp2350/hardware_regs/RP2350.svd new file mode 100644 index 000000000..aa2c36213 --- /dev/null +++ b/src/rp2350/hardware_regs/RP2350.svd @@ -0,0 +1,105849 @@ + + + + Raspberry Pi + RP2350 + RP + 0.1 + + Dual Cortex-M33 or Hazard3 processors at 150MHz + 520kB on-chip SRAM, in 10 independent banks + Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD + 8kB of one-time-programmable storage (OTP) + Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus + Additional 16MB flash/PSRAM accessible via optional second chip-select + On-chip switched-mode power supply to generate core voltage + Low-quiescent-current LDO mode can be enabled for sleep states + 2x on-chip PLLs for internal or external clock generation + GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) + Security features: + Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP + Protected OTP storage for optional boot decryption key + Global bus filtering based on Arm or RISC-V security/privilege levels + Peripherals, GPIOs and DMA channels individually assignable to security domains + Hardware mitigations for fault injection attacks + Hardware SHA-256 accelerator + Peripherals: + 2x UARTs + 2x SPI controllers + 2x I2C controllers + 24x PWM channels + USB 1.1 controller and PHY, with host and device support + 12x PIO state machines + 1x HSTX peripheral + + 32 + 32 + 0xffffffff + 0x00000000 + read-write + + Copyright (c) 2024 Raspberry Pi Ltd. + + SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r1p0 + little + true + true + 8 + 4 + 1 + 1 + false + 52 + + 8 + + + RESETS + 0x40020000 + + 0 + 12 + registers + + + + RESET + 0x00000000 + 0x1fffffff + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + WDSEL + 0x00000004 + 0x00000000 + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + RESET_DONE + 0x00000008 + 0x00000000 + + + USBCTRL + [28:28] + read-only + + + UART1 + [27:27] + read-only + + + UART0 + [26:26] + read-only + + + TRNG + [25:25] + read-only + + + TIMER1 + [24:24] + read-only + + + TIMER0 + [23:23] + read-only + + + TBMAN + [22:22] + read-only + + + SYSINFO + [21:21] + read-only + + + SYSCFG + [20:20] + read-only + + + SPI1 + [19:19] + read-only + + + SPI0 + [18:18] + read-only + + + SHA256 + [17:17] + read-only + + + PWM + [16:16] + read-only + + + PLL_USB + [15:15] + read-only + + + PLL_SYS + [14:14] + read-only + + + PIO2 + [13:13] + read-only + + + PIO1 + [12:12] + read-only + + + PIO0 + [11:11] + read-only + + + PADS_QSPI + [10:10] + read-only + + + PADS_BANK0 + [9:9] + read-only + + + JTAG + [8:8] + read-only + + + IO_QSPI + [7:7] + read-only + + + IO_BANK0 + [6:6] + read-only + + + I2C1 + [5:5] + read-only + + + I2C0 + [4:4] + read-only + + + HSTX + [3:3] + read-only + + + DMA + [2:2] + read-only + + + BUSCTRL + [1:1] + read-only + + + ADC + [0:0] + read-only + + + + + + + PSM + 0x40018000 + + 0 + 16 + registers + + + + FRCE_ON + 0x00000000 + Force block out of reset (i.e. power it on) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + FRCE_OFF + 0x00000004 + Force into reset (i.e. power it off) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + WDSEL + 0x00000008 + Set to 1 if the watchdog should reset this + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + DONE + 0x0000000c + Is the subsystem ready? + 0x00000000 + + + PROC1 + [24:24] + read-only + + + PROC0 + [23:23] + read-only + + + ACCESSCTRL + [22:22] + read-only + + + SIO + [21:21] + read-only + + + XIP + [20:20] + read-only + + + SRAM9 + [19:19] + read-only + + + SRAM8 + [18:18] + read-only + + + SRAM7 + [17:17] + read-only + + + SRAM6 + [16:16] + read-only + + + SRAM5 + [15:15] + read-only + + + SRAM4 + [14:14] + read-only + + + SRAM3 + [13:13] + read-only + + + SRAM2 + [12:12] + read-only + + + SRAM1 + [11:11] + read-only + + + SRAM0 + [10:10] + read-only + + + BOOTRAM + [9:9] + read-only + + + ROM + [8:8] + read-only + + + BUSFABRIC + [7:7] + read-only + + + PSM_READY + [6:6] + read-only + + + CLOCKS + [5:5] + read-only + + + RESETS + [4:4] + read-only + + + XOSC + [3:3] + read-only + + + ROSC + [2:2] + read-only + + + OTP + [1:1] + read-only + + + PROC_COLD + [0:0] + read-only + + + + + + + CLOCKS + 0x40010000 + + 0 + 212 + registers + + + CLOCKS_IRQ + 30 + + + + CLK_GPOUT0_CTRL + 0x00000000 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT0_DIV + 0x00000004 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT0_SELECTED + 0x00000008 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT0_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT1_CTRL + 0x0000000c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT1_DIV + 0x00000010 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT1_SELECTED + 0x00000014 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT1_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT2_CTRL + 0x00000018 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT2_DIV + 0x0000001c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT2_SELECTED + 0x00000020 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT2_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT3_CTRL + 0x00000024 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT3_DIV + 0x00000028 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT3_SELECTED + 0x0000002c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT3_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_REF_CTRL + 0x00000030 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [6:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb_primary_ref_opcg + 3 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [1:0] + read-write + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + lposc_clksrc + 3 + + + + + + + CLK_REF_DIV + 0x00000034 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [23:16] + read-write + + + + + CLK_REF_SELECTED + 0x00000038 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_REF_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [3:0] + read-only + + + + + CLK_SYS_CTRL + 0x0000003c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [0:0] + read-write + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + + + + + CLK_SYS_DIV + 0x00000040 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_SYS_SELECTED + 0x00000044 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_SYS_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [1:0] + read-only + + + + + CLK_PERI_CTRL + 0x00000048 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + + + + + CLK_PERI_DIV + 0x0000004c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_PERI_SELECTED + 0x00000050 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_PERI_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_HSTX_CTRL + 0x00000054 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + clksrc_gpin0 + 3 + + + clksrc_gpin1 + 4 + + + + + + + CLK_HSTX_DIV + 0x00000058 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_HSTX_SELECTED + 0x0000005c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_HSTX_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_USB_CTRL + 0x00000060 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_USB_DIV + 0x00000064 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_USB_SELECTED + 0x00000068 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_USB_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_ADC_CTRL + 0x0000006c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_ADC_DIV + 0x00000070 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_ADC_SELECTED + 0x00000074 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_ADC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + DFTCLK_XOSC_CTRL + 0x00000078 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary + 1 + + + clksrc_gpin0 + 2 + + + + + + + DFTCLK_ROSC_CTRL + 0x0000007c + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_sys_primary_rosc + 1 + + + clksrc_gpin1 + 2 + + + + + + + DFTCLK_LPOSC_CTRL + 0x00000080 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary_lposc + 1 + + + clksrc_gpin1 + 2 + + + + + + + CLK_SYS_RESUS_CTRL + 0x00000084 + 0x000000ff + + + CLEAR + For clearing the resus after the fault that triggered it has been corrected + [16:16] + read-write + + + FRCE + Force a resus, for test purposes only + [12:12] + read-write + + + ENABLE + Enable resus + [8:8] + read-write + + + TIMEOUT + This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq + [7:0] + read-write + + + + + CLK_SYS_RESUS_STATUS + 0x00000088 + 0x00000000 + + + RESUSSED + Clock has been resuscitated, correct the error then send ctrl_clear=1 + [0:0] + read-only + + + + + FC0_REF_KHZ + 0x0000008c + Reference clock frequency in kHz + 0x00000000 + + + FC0_REF_KHZ + [19:0] + read-write + + + + + FC0_MIN_KHZ + 0x00000090 + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + 0x00000000 + + + FC0_MIN_KHZ + [24:0] + read-write + + + + + FC0_MAX_KHZ + 0x00000094 + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + 0x01ffffff + + + FC0_MAX_KHZ + [24:0] + read-write + + + + + FC0_DELAY + 0x00000098 + Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period + 0x00000001 + + + FC0_DELAY + [2:0] + read-write + + + + + FC0_INTERVAL + 0x0000009c + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us + 0x00000008 + + + FC0_INTERVAL + [3:0] + read-write + + + + + FC0_SRC + 0x000000a0 + Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count + 0x00000000 + + + FC0_SRC + [7:0] + read-write + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_hstx + 13 + + + lposc_clksrc + 14 + + + otp_clk2fc + 15 + + + pll_usb_clksrc_primary_dft + 16 + + + + + + + FC0_STATUS + 0x000000a4 + Frequency counter status + 0x00000000 + + + DIED + Test clock stopped during test + [28:28] + read-only + + + FAST + Test clock faster than expected, only valid when status_done=1 + [24:24] + read-only + + + SLOW + Test clock slower than expected, only valid when status_done=1 + [20:20] + read-only + + + FAIL + Test failed + [16:16] + read-only + + + WAITING + Waiting for test clock to start + [12:12] + read-only + + + RUNNING + Test running + [8:8] + read-only + + + DONE + Test complete + [4:4] + read-only + + + PASS + Test passed + [0:0] + read-only + + + + + FC0_RESULT + 0x000000a8 + Result of frequency measurement, only valid when status_done=1 + 0x00000000 + + + KHZ + [29:5] + read-only + + + FRAC + [4:0] + read-only + + + + + WAKE_EN0 + 0x000000ac + enable clock in wake mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + WAKE_EN1 + 0x000000b0 + enable clock in wake mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + SLEEP_EN0 + 0x000000b4 + enable clock in sleep mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + SLEEP_EN1 + 0x000000b8 + enable clock in sleep mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + ENABLED0 + 0x000000bc + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_SIO + [31:31] + read-only + + + CLK_SYS_SHA256 + [30:30] + read-only + + + CLK_SYS_PSM + [29:29] + read-only + + + CLK_SYS_ROSC + [28:28] + read-only + + + CLK_SYS_ROM + [27:27] + read-only + + + CLK_SYS_RESETS + [26:26] + read-only + + + CLK_SYS_PWM + [25:25] + read-only + + + CLK_SYS_POWMAN + [24:24] + read-only + + + CLK_REF_POWMAN + [23:23] + read-only + + + CLK_SYS_PLL_USB + [22:22] + read-only + + + CLK_SYS_PLL_SYS + [21:21] + read-only + + + CLK_SYS_PIO2 + [20:20] + read-only + + + CLK_SYS_PIO1 + [19:19] + read-only + + + CLK_SYS_PIO0 + [18:18] + read-only + + + CLK_SYS_PADS + [17:17] + read-only + + + CLK_SYS_OTP + [16:16] + read-only + + + CLK_REF_OTP + [15:15] + read-only + + + CLK_SYS_JTAG + [14:14] + read-only + + + CLK_SYS_IO + [13:13] + read-only + + + CLK_SYS_I2C1 + [12:12] + read-only + + + CLK_SYS_I2C0 + [11:11] + read-only + + + CLK_SYS_HSTX + [10:10] + read-only + + + CLK_HSTX + [9:9] + read-only + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-only + + + CLK_SYS_DMA + [7:7] + read-only + + + CLK_SYS_BUSFABRIC + [6:6] + read-only + + + CLK_SYS_BUSCTRL + [5:5] + read-only + + + CLK_SYS_BOOTRAM + [4:4] + read-only + + + CLK_SYS_ADC + [3:3] + read-only + + + CLK_ADC + [2:2] + read-only + + + CLK_SYS_ACCESSCTRL + [1:1] + read-only + + + CLK_SYS_CLOCKS + [0:0] + read-only + + + + + ENABLED1 + 0x000000c0 + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_XOSC + [30:30] + read-only + + + CLK_SYS_XIP + [29:29] + read-only + + + CLK_SYS_WATCHDOG + [28:28] + read-only + + + CLK_USB + [27:27] + read-only + + + CLK_SYS_USBCTRL + [26:26] + read-only + + + CLK_SYS_UART1 + [25:25] + read-only + + + CLK_PERI_UART1 + [24:24] + read-only + + + CLK_SYS_UART0 + [23:23] + read-only + + + CLK_PERI_UART0 + [22:22] + read-only + + + CLK_SYS_TRNG + [21:21] + read-only + + + CLK_SYS_TIMER1 + [20:20] + read-only + + + CLK_SYS_TIMER0 + [19:19] + read-only + + + CLK_SYS_TICKS + [18:18] + read-only + + + CLK_REF_TICKS + [17:17] + read-only + + + CLK_SYS_TBMAN + [16:16] + read-only + + + CLK_SYS_SYSINFO + [15:15] + read-only + + + CLK_SYS_SYSCFG + [14:14] + read-only + + + CLK_SYS_SRAM9 + [13:13] + read-only + + + CLK_SYS_SRAM8 + [12:12] + read-only + + + CLK_SYS_SRAM7 + [11:11] + read-only + + + CLK_SYS_SRAM6 + [10:10] + read-only + + + CLK_SYS_SRAM5 + [9:9] + read-only + + + CLK_SYS_SRAM4 + [8:8] + read-only + + + CLK_SYS_SRAM3 + [7:7] + read-only + + + CLK_SYS_SRAM2 + [6:6] + read-only + + + CLK_SYS_SRAM1 + [5:5] + read-only + + + CLK_SYS_SRAM0 + [4:4] + read-only + + + CLK_SYS_SPI1 + [3:3] + read-only + + + CLK_PERI_SPI1 + [2:2] + read-only + + + CLK_SYS_SPI0 + [1:1] + read-only + + + CLK_PERI_SPI0 + [0:0] + read-only + + + + + INTR + 0x000000c4 + Raw Interrupts + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + INTE + 0x000000c8 + Interrupt Enable + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTF + 0x000000cc + Interrupt Force + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTS + 0x000000d0 + Interrupt status after masking & forcing + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + + + TICKS + 0x40108000 + + 0 + 72 + registers + + + + PROC0_CTRL + 0x00000000 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC0_CYCLES + 0x00000004 + 0x00000000 + + + PROC0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC0_COUNT + 0x00000008 + 0x00000000 + + + PROC0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + PROC1_CTRL + 0x0000000c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC1_CYCLES + 0x00000010 + 0x00000000 + + + PROC1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC1_COUNT + 0x00000014 + 0x00000000 + + + PROC1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER0_CTRL + 0x00000018 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER0_CYCLES + 0x0000001c + 0x00000000 + + + TIMER0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER0_COUNT + 0x00000020 + 0x00000000 + + + TIMER0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER1_CTRL + 0x00000024 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER1_CYCLES + 0x00000028 + 0x00000000 + + + TIMER1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER1_COUNT + 0x0000002c + 0x00000000 + + + TIMER1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + WATCHDOG_CTRL + 0x00000030 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + WATCHDOG_CYCLES + 0x00000034 + 0x00000000 + + + WATCHDOG_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + WATCHDOG_COUNT + 0x00000038 + 0x00000000 + + + WATCHDOG_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + RISCV_CTRL + 0x0000003c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + RISCV_CYCLES + 0x00000040 + 0x00000000 + + + RISCV_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + RISCV_COUNT + 0x00000044 + 0x00000000 + + + RISCV_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + + + PADS_BANK0 + 0x40038000 + + 0 + 204 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO0 + 0x00000004 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO1 + 0x00000008 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO2 + 0x0000000c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO3 + 0x00000010 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO4 + 0x00000014 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO5 + 0x00000018 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO6 + 0x0000001c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO7 + 0x00000020 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO8 + 0x00000024 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO9 + 0x00000028 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO10 + 0x0000002c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO11 + 0x00000030 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO12 + 0x00000034 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO13 + 0x00000038 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO14 + 0x0000003c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO15 + 0x00000040 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO16 + 0x00000044 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO17 + 0x00000048 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO18 + 0x0000004c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO19 + 0x00000050 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO20 + 0x00000054 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO21 + 0x00000058 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO22 + 0x0000005c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO23 + 0x00000060 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO24 + 0x00000064 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO25 + 0x00000068 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO26 + 0x0000006c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO27 + 0x00000070 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO28 + 0x00000074 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO29 + 0x00000078 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO30 + 0x0000007c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO31 + 0x00000080 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO32 + 0x00000084 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO33 + 0x00000088 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO34 + 0x0000008c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO35 + 0x00000090 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO36 + 0x00000094 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO37 + 0x00000098 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO38 + 0x0000009c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO39 + 0x000000a0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO40 + 0x000000a4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO41 + 0x000000a8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO42 + 0x000000ac + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO43 + 0x000000b0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO44 + 0x000000b4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO45 + 0x000000b8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO46 + 0x000000bc + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO47 + 0x000000c0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWCLK + 0x000000c4 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWD + 0x000000c8 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + PADS_QSPI + 0x40040000 + + 0 + 28 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO_QSPI_SCLK + 0x00000004 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD0 + 0x00000008 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD1 + 0x0000000c + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD2 + 0x00000010 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD3 + 0x00000014 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SS + 0x00000018 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + IO_QSPI + 0x40030000 + + 0 + 576 + registers + + + IO_IRQ_QSPI + 23 + + + IO_IRQ_QSPI_NS + 24 + + + + USBPHY_DP_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DP_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_56 + 5 + + + null + 31 + + + + + + + USBPHY_DM_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DM_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_57 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SCLK_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SCLK_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sclk + 0 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_58 + 5 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SS_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SS_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_ss_n_0 + 0 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_59 + 5 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD0_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD0_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd0 + 0 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_60 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD1_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD1_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd1 + 0 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_61 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD2_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD2_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd2 + 0 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_62 + 5 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD3_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD3_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd3 + 0 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_63 + 5 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE + 0x00000200 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE + 0x00000204 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE + 0x00000208 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE + 0x0000020c + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE + 0x00000210 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE + 0x00000214 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + INTR + 0x00000218 + Raw Interrupts + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + oneToClear + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + oneToClear + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + oneToClear + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + oneToClear + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE + 0x0000021c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF + 0x00000220 + Interrupt Force for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS + 0x00000224 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE + 0x00000228 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF + 0x0000022c + Interrupt Force for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS + 0x00000230 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE + 0x00000234 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF + 0x00000238 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS + 0x0000023c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + + + IO_BANK0 + 0x40028000 + + 0 + 800 + registers + + + IO_IRQ_BANK0 + 21 + + + IO_IRQ_BANK0_NS + 22 + + + + GPIO0_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO0_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tck + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_0 + 5 + + + pio0_0 + 6 + + + pio1_0 + 7 + + + pio2_0 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO1_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO1_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tms + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_1 + 5 + + + pio0_1 + 6 + + + pio1_1 + 7 + + + pio2_1 + 8 + + + coresight_traceclk + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO2_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO2_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdi + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_2 + 5 + + + pio0_2 + 6 + + + pio1_2 + 7 + + + pio2_2 + 8 + + + coresight_tracedata_0 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO3_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO3_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdo + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_3 + 5 + + + pio0_3 + 6 + + + pio1_3 + 7 + + + pio2_3 + 8 + + + coresight_tracedata_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO4_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO4_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_4 + 5 + + + pio0_4 + 6 + + + pio1_4 + 7 + + + pio2_4 + 8 + + + coresight_tracedata_2 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO5_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO5_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_5 + 5 + + + pio0_5 + 6 + + + pio1_5 + 7 + + + pio2_5 + 8 + + + coresight_tracedata_3 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO6_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO6_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_6 + 5 + + + pio0_6 + 6 + + + pio1_6 + 7 + + + pio2_6 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO7_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO7_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_7 + 5 + + + pio0_7 + 6 + + + pio1_7 + 7 + + + pio2_7 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO8_STATUS + 0x00000040 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO8_CTRL + 0x00000044 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_8 + 5 + + + pio0_8 + 6 + + + pio1_8 + 7 + + + pio2_8 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO9_STATUS + 0x00000048 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO9_CTRL + 0x0000004c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_9 + 5 + + + pio0_9 + 6 + + + pio1_9 + 7 + + + pio2_9 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO10_STATUS + 0x00000050 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO10_CTRL + 0x00000054 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_10 + 5 + + + pio0_10 + 6 + + + pio1_10 + 7 + + + pio2_10 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO11_STATUS + 0x00000058 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO11_CTRL + 0x0000005c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_11 + 5 + + + pio0_11 + 6 + + + pio1_11 + 7 + + + pio2_11 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO12_STATUS + 0x00000060 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO12_CTRL + 0x00000064 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_0 + 0 + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_12 + 5 + + + pio0_12 + 6 + + + pio1_12 + 7 + + + pio2_12 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO13_STATUS + 0x00000068 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO13_CTRL + 0x0000006c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_1 + 0 + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_13 + 5 + + + pio0_13 + 6 + + + pio1_13 + 7 + + + pio2_13 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO14_STATUS + 0x00000070 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO14_CTRL + 0x00000074 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_2 + 0 + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_14 + 5 + + + pio0_14 + 6 + + + pio1_14 + 7 + + + pio2_14 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO15_STATUS + 0x00000078 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO15_CTRL + 0x0000007c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_3 + 0 + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_15 + 5 + + + pio0_15 + 6 + + + pio1_15 + 7 + + + pio2_15 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO16_STATUS + 0x00000080 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO16_CTRL + 0x00000084 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_4 + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_16 + 5 + + + pio0_16 + 6 + + + pio1_16 + 7 + + + pio2_16 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO17_STATUS + 0x00000088 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO17_CTRL + 0x0000008c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_5 + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_17 + 5 + + + pio0_17 + 6 + + + pio1_17 + 7 + + + pio2_17 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO18_STATUS + 0x00000090 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO18_CTRL + 0x00000094 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_6 + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_18 + 5 + + + pio0_18 + 6 + + + pio1_18 + 7 + + + pio2_18 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO19_STATUS + 0x00000098 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO19_CTRL + 0x0000009c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_7 + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_19 + 5 + + + pio0_19 + 6 + + + pio1_19 + 7 + + + pio2_19 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO20_STATUS + 0x000000a0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO20_CTRL + 0x000000a4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_20 + 5 + + + pio0_20 + 6 + + + pio1_20 + 7 + + + pio2_20 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO21_STATUS + 0x000000a8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO21_CTRL + 0x000000ac + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_21 + 5 + + + pio0_21 + 6 + + + pio1_21 + 7 + + + pio2_21 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO22_STATUS + 0x000000b0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO22_CTRL + 0x000000b4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_22 + 5 + + + pio0_22 + 6 + + + pio1_22 + 7 + + + pio2_22 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO23_STATUS + 0x000000b8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO23_CTRL + 0x000000bc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_23 + 5 + + + pio0_23 + 6 + + + pio1_23 + 7 + + + pio2_23 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO24_STATUS + 0x000000c0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO24_CTRL + 0x000000c4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_24 + 5 + + + pio0_24 + 6 + + + pio1_24 + 7 + + + pio2_24 + 8 + + + clocks_gpout_2 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO25_STATUS + 0x000000c8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO25_CTRL + 0x000000cc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_25 + 5 + + + pio0_25 + 6 + + + pio1_25 + 7 + + + pio2_25 + 8 + + + clocks_gpout_3 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO26_STATUS + 0x000000d0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO26_CTRL + 0x000000d4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_26 + 5 + + + pio0_26 + 6 + + + pio1_26 + 7 + + + pio2_26 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO27_STATUS + 0x000000d8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO27_CTRL + 0x000000dc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_27 + 5 + + + pio0_27 + 6 + + + pio1_27 + 7 + + + pio2_27 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO28_STATUS + 0x000000e0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO28_CTRL + 0x000000e4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_28 + 5 + + + pio0_28 + 6 + + + pio1_28 + 7 + + + pio2_28 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO29_STATUS + 0x000000e8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO29_CTRL + 0x000000ec + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_29 + 5 + + + pio0_29 + 6 + + + pio1_29 + 7 + + + pio2_29 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO30_STATUS + 0x000000f0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO30_CTRL + 0x000000f4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_30 + 5 + + + pio0_30 + 6 + + + pio1_30 + 7 + + + pio2_30 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO31_STATUS + 0x000000f8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO31_CTRL + 0x000000fc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_31 + 5 + + + pio0_31 + 6 + + + pio1_31 + 7 + + + pio2_31 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO32_STATUS + 0x00000100 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO32_CTRL + 0x00000104 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_32 + 5 + + + pio0_32 + 6 + + + pio1_32 + 7 + + + pio2_32 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO33_STATUS + 0x00000108 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO33_CTRL + 0x0000010c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_33 + 5 + + + pio0_33 + 6 + + + pio1_33 + 7 + + + pio2_33 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO34_STATUS + 0x00000110 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO34_CTRL + 0x00000114 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_34 + 5 + + + pio0_34 + 6 + + + pio1_34 + 7 + + + pio2_34 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO35_STATUS + 0x00000118 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO35_CTRL + 0x0000011c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_35 + 5 + + + pio0_35 + 6 + + + pio1_35 + 7 + + + pio2_35 + 8 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO36_STATUS + 0x00000120 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO36_CTRL + 0x00000124 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_36 + 5 + + + pio0_36 + 6 + + + pio1_36 + 7 + + + pio2_36 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO37_STATUS + 0x00000128 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO37_CTRL + 0x0000012c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_37 + 5 + + + pio0_37 + 6 + + + pio1_37 + 7 + + + pio2_37 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO38_STATUS + 0x00000130 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO38_CTRL + 0x00000134 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_38 + 5 + + + pio0_38 + 6 + + + pio1_38 + 7 + + + pio2_38 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO39_STATUS + 0x00000138 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO39_CTRL + 0x0000013c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_39 + 5 + + + pio0_39 + 6 + + + pio1_39 + 7 + + + pio2_39 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO40_STATUS + 0x00000140 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO40_CTRL + 0x00000144 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_40 + 5 + + + pio0_40 + 6 + + + pio1_40 + 7 + + + pio2_40 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO41_STATUS + 0x00000148 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO41_CTRL + 0x0000014c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_41 + 5 + + + pio0_41 + 6 + + + pio1_41 + 7 + + + pio2_41 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO42_STATUS + 0x00000150 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO42_CTRL + 0x00000154 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_42 + 5 + + + pio0_42 + 6 + + + pio1_42 + 7 + + + pio2_42 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO43_STATUS + 0x00000158 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO43_CTRL + 0x0000015c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_43 + 5 + + + pio0_43 + 6 + + + pio1_43 + 7 + + + pio2_43 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO44_STATUS + 0x00000160 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO44_CTRL + 0x00000164 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_44 + 5 + + + pio0_44 + 6 + + + pio1_44 + 7 + + + pio2_44 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO45_STATUS + 0x00000168 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO45_CTRL + 0x0000016c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_45 + 5 + + + pio0_45 + 6 + + + pio1_45 + 7 + + + pio2_45 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO46_STATUS + 0x00000170 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO46_CTRL + 0x00000174 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_46 + 5 + + + pio0_46 + 6 + + + pio1_46 + 7 + + + pio2_46 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO47_STATUS + 0x00000178 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO47_CTRL + 0x0000017c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_47 + 5 + + + pio0_47 + 6 + + + pio1_47 + 7 + + + pio2_47 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE0 + 0x00000200 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_SECURE1 + 0x00000204 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE0 + 0x00000208 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE1 + 0x0000020c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE0 + 0x00000210 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE1 + 0x00000214 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE0 + 0x00000218 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE1 + 0x0000021c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE0 + 0x00000220 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE1 + 0x00000224 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + 0x00000228 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE1 + 0x0000022c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + INTR0 + 0x00000230 + Raw Interrupts + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO7_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO6_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO3_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO2_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO1_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO0_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + INTR1 + 0x00000234 + Raw Interrupts + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO15_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO14_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO13_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO12_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO11_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO10_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO9_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO8_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + INTR2 + 0x00000238 + Raw Interrupts + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO23_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO22_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO21_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO20_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO19_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO18_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO17_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO16_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + INTR3 + 0x0000023c + Raw Interrupts + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO31_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO30_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO29_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO28_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO27_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO26_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO25_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO24_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + INTR4 + 0x00000240 + Raw Interrupts + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO39_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO38_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO37_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO36_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO35_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO34_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO33_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO32_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + INTR5 + 0x00000244 + Raw Interrupts + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO47_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO46_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO45_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO44_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO43_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO42_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO41_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO40_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE0 + 0x00000248 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE1 + 0x0000024c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE2 + 0x00000250 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE3 + 0x00000254 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE4 + 0x00000258 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE5 + 0x0000025c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF0 + 0x00000260 + Interrupt Force for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF1 + 0x00000264 + Interrupt Force for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF2 + 0x00000268 + Interrupt Force for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF3 + 0x0000026c + Interrupt Force for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF4 + 0x00000270 + Interrupt Force for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF5 + 0x00000274 + Interrupt Force for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS0 + 0x00000278 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS1 + 0x0000027c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS2 + 0x00000280 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS3 + 0x00000284 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS4 + 0x00000288 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS5 + 0x0000028c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE0 + 0x00000290 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE1 + 0x00000294 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE2 + 0x00000298 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE3 + 0x0000029c + Interrupt Enable for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE4 + 0x000002a0 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE5 + 0x000002a4 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF0 + 0x000002a8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF1 + 0x000002ac + Interrupt Force for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF2 + 0x000002b0 + Interrupt Force for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF3 + 0x000002b4 + Interrupt Force for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF4 + 0x000002b8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF5 + 0x000002bc + Interrupt Force for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS0 + 0x000002c0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS1 + 0x000002c4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS2 + 0x000002c8 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS3 + 0x000002cc + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS4 + 0x000002d0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS5 + 0x000002d4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE0 + 0x000002d8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE1 + 0x000002dc + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE2 + 0x000002e0 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE3 + 0x000002e4 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE4 + 0x000002e8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE5 + 0x000002ec + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF0 + 0x000002f0 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF1 + 0x000002f4 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF2 + 0x000002f8 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF3 + 0x000002fc + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF4 + 0x00000300 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF5 + 0x00000304 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS0 + 0x00000308 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS1 + 0x0000030c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS2 + 0x00000310 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS3 + 0x00000314 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS4 + 0x00000318 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS5 + 0x0000031c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + + + SYSINFO + 0x40000000 + + 0 + 24 + registers + + + + CHIP_ID + 0x00000000 + JEDEC JEP-106 compliant chip identifier. + 0x00000001 + + + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:1] + read-only + + + STOP_BIT + [0:0] + read-only + + + + + PACKAGE_SEL + 0x00000004 + 0x00000000 + + + PACKAGE_SEL + [0:0] + read-only + + + + + PLATFORM + 0x00000008 + Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. + 0x00000000 + + + GATESIM + [4:4] + read-only + + + BATCHSIM + [3:3] + read-only + + + HDLSIM + [2:2] + read-only + + + ASIC + [1:1] + read-only + + + FPGA + [0:0] + read-only + + + + + GITREF_RP2350 + 0x00000014 + Git hash of the chip source. Used to identify chip version. + 0x00000000 + + + GITREF_RP2350 + [31:0] + read-only + + + + + + + SHA256 + SHA-256 hash function implementation + 0x400f8000 + + 0 + 40 + registers + + + + CSR + 0x00000000 + Control and status register + 0x00001206 + + + BSWAP + Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. + + This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. + + However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. + + This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. + [12:12] + read-write + + + DMA_SIZE + Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. + + The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. + [9:8] + read-write + + + 8bit + 0 + + + 16bit + 1 + + + 32bit + 2 + + + + + ERR_WDATA_NOT_RDY + Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. + [4:4] + read-write + oneToClear + + + SUM_VLD + If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. + + Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. + [2:2] + read-only + + + WDATA_RDY + If 1, the SHA-256 core is ready to accept more data through the WDATA register. + + After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. + [1:1] + read-only + + + START + Write 1 to prepare the SHA-256 core for a new checksum. + + The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. + + START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. + [0:0] + write-only + + + + + WDATA + 0x00000004 + Write data register + 0x00000000 + + + WDATA + After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. + + Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. + + After this, WDATA_RDY will return high, and more data can be written (if any). + + This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. + [31:0] + write-only + + + + + SUM0 + 0x00000008 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM0 + [31:0] + read-only + + + + + SUM1 + 0x0000000c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM1 + [31:0] + read-only + + + + + SUM2 + 0x00000010 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM2 + [31:0] + read-only + + + + + SUM3 + 0x00000014 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM3 + [31:0] + read-only + + + + + SUM4 + 0x00000018 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM4 + [31:0] + read-only + + + + + SUM5 + 0x0000001c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM5 + [31:0] + read-only + + + + + SUM6 + 0x00000020 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM6 + [31:0] + read-only + + + + + SUM7 + 0x00000024 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM7 + [31:0] + read-only + + + + + + + HSTX_FIFO + FIFO status and write access for HSTX + 0x50600000 + + 0 + 8 + registers + + + + STAT + 0x00000000 + FIFO status + 0x00000000 + + + WOF + FIFO was written when full. Write 1 to clear. + [10:10] + read-write + oneToClear + + + EMPTY + [9:9] + read-only + + + FULL + [8:8] + read-only + + + LEVEL + [7:0] + read-only + + + + + FIFO + 0x00000004 + Write access to FIFO + 0x00000000 + + + FIFO + [31:0] + write-only + + + + + + + HSTX_CTRL + Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. + 0x400c0000 + + 0 + 44 + registers + + + + CSR + 0x00000000 + 0x10050600 + + + CLKDIV + Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. + + For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). + + A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. + [31:28] + read-write + + + CLKPHASE + Set the initial phase of the generated clock. + + A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: + + * The clock will be initially low + + * The first rising edge will be 0.5 clk_hstx cycles after asserting first data + + * The first falling edge will be 1.5 clk_hstx cycles after asserting first data + + This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. + + When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. + + Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. + [27:24] + read-write + + + N_SHIFTS + Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) + + A register value of 0 means shift 32 times. + [20:16] + read-write + + + SHIFT + How many bits to right-rotate the shift register by each cycle. + + The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. + [12:8] + read-write + + + COUPLED_SEL + Select which PIO to use for coupled mode operation. + [6:5] + read-write + + + COUPLED_MODE + Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. + + When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. + + The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. + + For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. + [4:4] + read-write + + + EXPAND_EN + Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. + + Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. + [1:1] + read-write + + + EN + When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. + + When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. + + Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. + [0:0] + read-write + + + + + BIT0 + 0x00000004 + Data control register for output bit 0 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT1 + 0x00000008 + Data control register for output bit 1 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT2 + 0x0000000c + Data control register for output bit 2 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT3 + 0x00000010 + Data control register for output bit 3 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT4 + 0x00000014 + Data control register for output bit 4 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT5 + 0x00000018 + Data control register for output bit 5 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT6 + 0x0000001c + Data control register for output bit 6 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT7 + 0x00000020 + Data control register for output bit 7 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + EXPAND_SHIFT + 0x00000024 + Configure the optional shifter inside the command expander + 0x01000100 + + + ENC_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. + [28:24] + read-write + + + ENC_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). + [20:16] + read-write + + + RAW_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. + [12:8] + read-write + + + RAW_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. + [4:0] + read-write + + + + + EXPAND_TMDS + 0x00000028 + Configure the optional TMDS encoder inside the command expander + 0x00000000 + + + L2_NBITS + Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [23:21] + read-write + + + L2_ROT + Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. + [20:16] + read-write + + + L1_NBITS + Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [15:13] + read-write + + + L1_ROT + Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. + [12:8] + read-write + + + L0_NBITS + Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [7:5] + read-write + + + L0_ROT + Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. + [4:0] + read-write + + + + + + + EPPB + Cortex-M33 EPPB vendor register block for RP2350 + 0xe0080000 + + 0 + 12 + registers + + + + NMI_MASK0 + 0x00000000 + NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK0 + [31:0] + read-write + + + + + NMI_MASK1 + 0x00000004 + NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK1 + [19:0] + read-write + + + + + SLEEPCTRL + 0x00000008 + Nonstandard sleep control register + 0x00000002 + + + WICENACK + Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. + [2:2] + read-only + + + WICENREQ + Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. + [1:1] + read-write + + + LIGHT_SLEEP + By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. + + Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. + [0:0] + read-write + + + + + + + PPB + TEAL registers accessible through the debug interface + 0xe0000000 + + 0 + 274432 + registers + + + + ITM_STIM0 + 0x00000000 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM1 + 0x00000004 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM2 + 0x00000008 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM3 + 0x0000000c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM4 + 0x00000010 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM5 + 0x00000014 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM6 + 0x00000018 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM7 + 0x0000001c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM8 + 0x00000020 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM9 + 0x00000024 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM10 + 0x00000028 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM11 + 0x0000002c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM12 + 0x00000030 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM13 + 0x00000034 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM14 + 0x00000038 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM15 + 0x0000003c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM16 + 0x00000040 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM17 + 0x00000044 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM18 + 0x00000048 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM19 + 0x0000004c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM20 + 0x00000050 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM21 + 0x00000054 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM22 + 0x00000058 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM23 + 0x0000005c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM24 + 0x00000060 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM25 + 0x00000064 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM26 + 0x00000068 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM27 + 0x0000006c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM28 + 0x00000070 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM29 + 0x00000074 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM30 + 0x00000078 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM31 + 0x0000007c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_TER0 + 0x00000e00 + Provide an individual enable bit for each ITM_STIM register + 0x00000000 + + + STIMENA + For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled + [31:0] + read-write + + + + + ITM_TPR + 0x00000e40 + Controls which stimulus ports can be accessed by unprivileged code + 0x00000000 + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports + [3:0] + read-write + + + + + ITM_TCR + 0x00000e80 + Configures and controls transfers through the ITM interface + 0x00000000 + + + BUSY + Indicates whether the ITM is currently processing events + [23:23] + read-only + + + TRACEBUSID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field + [22:16] + read-write + + + GTSFREQ + Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps + [11:10] + read-write + + + TSPRESCALE + Local timestamp prescaler, used with the trace packet reference clock + [9:8] + read-write + + + STALLENA + Stall the PE to guarantee delivery of Data Trace packets. + [5:5] + read-write + + + SWOENA + Enables asynchronous clocking of the timestamp counter + [4:4] + read-write + + + TXENA + Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU + [3:3] + read-write + + + SYNCENA + Enables Synchronization packet transmission for a synchronous TPIU + [2:2] + read-write + + + TSENA + Enables Local timestamp generation + [1:1] + read-write + + + ITMENA + Enables the ITM + [0:0] + read-write + + + + + INT_ATREADY + 0x00000ef0 + Integration Mode: Read ATB Ready + 0x00000000 + + + AFVALID + A read of this bit returns the value of AFVALID + [1:1] + read-only + + + ATREADY + A read of this bit returns the value of ATREADY + [0:0] + read-only + + + + + INT_ATVALID + 0x00000ef8 + Integration Mode: Write ATB Valid + 0x00000000 + + + AFREADY + A write to this bit gives the value of AFREADY + [1:1] + read-write + + + ATREADY + A write to this bit gives the value of ATVALID + [0:0] + read-write + + + + + ITM_ITCTRL + 0x00000f00 + Integration Mode Control Register + 0x00000000 + + + IME + Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. + [0:0] + read-write + + + + + ITM_DEVARCH + 0x00000fbc + Provides CoreSight discovery information for the ITM + 0x47701a01 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + ITM_DEVTYPE + 0x00000fcc + Provides CoreSight discovery information for the ITM + 0x00000043 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + ITM_PIDR4 + 0x00000fd0 + Provides CoreSight discovery information for the ITM + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR5 + 0x00000fd4 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR5 + [31:0] + read-write + + + + + ITM_PIDR6 + 0x00000fd8 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR6 + [31:0] + read-write + + + + + ITM_PIDR7 + 0x00000fdc + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR7 + [31:0] + read-write + + + + + ITM_PIDR0 + 0x00000fe0 + Provides CoreSight discovery information for the ITM + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_PIDR1 + 0x00000fe4 + Provides CoreSight discovery information for the ITM + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR2 + 0x00000fe8 + Provides CoreSight discovery information for the ITM + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + ITM_PIDR3 + 0x00000fec + Provides CoreSight discovery information for the ITM + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR0 + 0x00000ff0 + Provides CoreSight discovery information for the ITM + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR1 + 0x00000ff4 + Provides CoreSight discovery information for the ITM + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR2 + 0x00000ff8 + Provides CoreSight discovery information for the ITM + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR3 + 0x00000ffc + Provides CoreSight discovery information for the ITM + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CTRL + 0x00001000 + Provides configuration and status information for the DWT unit, and used to control features of the unit + 0x73741824 + + + NUMCOMP + Number of DWT comparators implemented + [31:28] + read-only + + + NOTRCPKT + Indicates whether the implementation does not support trace + [27:27] + read-only + + + NOEXTTRIG + Reserved, RAZ + [26:26] + read-only + + + NOCYCCNT + Indicates whether the implementation does not include a cycle counter + [25:25] + read-only + + + NOPRFCNT + Indicates whether the implementation does not include the profiling counters + [24:24] + read-only + + + CYCDISS + Controls whether the cycle counter is disabled in Secure state + [23:23] + read-write + + + CYCEVTENA + Enables Event Counter packet generation on POSTCNT underflow + [22:22] + read-write + + + FOLDEVTENA + Enables DWT_FOLDCNT counter + [21:21] + read-write + + + LSUEVTENA + Enables DWT_LSUCNT counter + [20:20] + read-write + + + SLEEPEVTENA + Enable DWT_SLEEPCNT counter + [19:19] + read-write + + + EXCEVTENA + Enables DWT_EXCCNT counter + [18:18] + read-write + + + CPIEVTENA + Enables DWT_CPICNT counter + [17:17] + read-write + + + EXTTRCENA + Enables generation of Exception Trace packets + [16:16] + read-write + + + PCSAMPLENA + Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation + [12:12] + read-write + + + SYNCTAP + Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate + [11:10] + read-write + + + CYCTAP + Selects the position of the POSTCNT tap on the CYCCNT counter + [9:9] + read-write + + + POSTINIT + Initial value for the POSTCNT counter + [8:5] + read-write + + + POSTPRESET + Reload value for the POSTCNT counter + [4:1] + read-write + + + CYCCNTENA + Enables CYCCNT + [0:0] + read-write + + + + + DWT_CYCCNT + 0x00001004 + Shows or sets the value of the processor cycle counter, CYCCNT + 0x00000000 + + + CYCCNT + Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero + [31:0] + read-write + + + + + DWT_EXCCNT + 0x0000100c + Counts the total cycles spent in exception processing + 0x00000000 + + + EXCCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_LSUCNT + 0x00001014 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + LSUCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_FOLDCNT + 0x00001018 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + FOLDCNT + Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one + [7:0] + read-write + + + + + DWT_COMP0 + 0x00001020 + Provides a reference value for use by watchpoint comparator 0 + 0x00000000 + + + DWT_COMP0 + [31:0] + read-write + + + + + DWT_FUNCTION0 + 0x00001028 + Controls the operation of watchpoint comparator 0 + 0x58000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP1 + 0x00001030 + Provides a reference value for use by watchpoint comparator 1 + 0x00000000 + + + DWT_COMP1 + [31:0] + read-write + + + + + DWT_FUNCTION1 + 0x00001038 + Controls the operation of watchpoint comparator 1 + 0x89000828 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP2 + 0x00001040 + Provides a reference value for use by watchpoint comparator 2 + 0x00000000 + + + DWT_COMP2 + [31:0] + read-write + + + + + DWT_FUNCTION2 + 0x00001048 + Controls the operation of watchpoint comparator 2 + 0x50000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP3 + 0x00001050 + Provides a reference value for use by watchpoint comparator 3 + 0x00000000 + + + DWT_COMP3 + [31:0] + read-write + + + + + DWT_FUNCTION3 + 0x00001058 + Controls the operation of watchpoint comparator 3 + 0x20000800 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_DEVARCH + 0x00001fbc + Provides CoreSight discovery information for the DWT + 0x47701a02 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DWT_DEVTYPE + 0x00001fcc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + DWT_PIDR4 + 0x00001fd0 + Provides CoreSight discovery information for the DWT + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR5 + 0x00001fd4 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR5 + [31:0] + read-write + + + + + DWT_PIDR6 + 0x00001fd8 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR6 + [31:0] + read-write + + + + + DWT_PIDR7 + 0x00001fdc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR7 + [31:0] + read-write + + + + + DWT_PIDR0 + 0x00001fe0 + Provides CoreSight discovery information for the DWT + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_PIDR1 + 0x00001fe4 + Provides CoreSight discovery information for the DWT + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR2 + 0x00001fe8 + Provides CoreSight discovery information for the DWT + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DWT_PIDR3 + 0x00001fec + Provides CoreSight discovery information for the DWT + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR0 + 0x00001ff0 + Provides CoreSight discovery information for the DWT + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR1 + 0x00001ff4 + Provides CoreSight discovery information for the DWT + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR2 + 0x00001ff8 + Provides CoreSight discovery information for the DWT + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR3 + 0x00001ffc + Provides CoreSight discovery information for the DWT + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CTRL + 0x00002000 + Provides FPB implementation information, and the global enable for the FPB unit + 0x60005580 + + + REV + Flash Patch and Breakpoint Unit architecture revision + [31:28] + read-only + + + NUM_CODE_14_12_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [14:12] + read-only + + + NUM_LIT + Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 + [11:8] + read-only + + + NUM_CODE_7_4_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [7:4] + read-only + + + KEY + Writes to the FP_CTRL are ignored unless KEY is concurrently written to one + [1:1] + read-write + + + ENABLE + Enables the FPB + [0:0] + read-write + + + + + FP_REMAP + 0x00002004 + Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap + 0x00000000 + + + RMPSPT + Indicates whether the FPB unit supports the Flash Patch remap function + [29:29] + read-only + + + REMAP + Holds the bits[28:5] of the Flash Patch remap address + [28:5] + read-only + + + + + FP_COMP0 + 0x00002008 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP1 + 0x0000200c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP2 + 0x00002010 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP3 + 0x00002014 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP4 + 0x00002018 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP5 + 0x0000201c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP6 + 0x00002020 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP7 + 0x00002024 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_DEVARCH + 0x00002fbc + Provides CoreSight discovery information for the FPB + 0x47701a03 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + FP_DEVTYPE + 0x00002fcc + Provides CoreSight discovery information for the FPB + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + FP_PIDR4 + 0x00002fd0 + Provides CoreSight discovery information for the FP + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR5 + 0x00002fd4 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR5 + [31:0] + read-write + + + + + FP_PIDR6 + 0x00002fd8 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR6 + [31:0] + read-write + + + + + FP_PIDR7 + 0x00002fdc + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR7 + [31:0] + read-write + + + + + FP_PIDR0 + 0x00002fe0 + Provides CoreSight discovery information for the FP + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_PIDR1 + 0x00002fe4 + Provides CoreSight discovery information for the FP + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR2 + 0x00002fe8 + Provides CoreSight discovery information for the FP + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + FP_PIDR3 + 0x00002fec + Provides CoreSight discovery information for the FP + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR0 + 0x00002ff0 + Provides CoreSight discovery information for the FP + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR1 + 0x00002ff4 + Provides CoreSight discovery information for the FP + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR2 + 0x00002ff8 + Provides CoreSight discovery information for the FP + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR3 + 0x00002ffc + Provides CoreSight discovery information for the FP + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ICTR + 0x0000e004 + Provides information about the interrupt controller + 0x00000001 + + + INTLINESNUM + Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM + [3:0] + read-only + + + + + ACTLR + 0x0000e008 + Provides IMPLEMENTATION DEFINED configuration and control options + 0x00000000 + + + EXTEXCLALL + External Exclusives Allowed with no MPU + [29:29] + read-write + + + DISITMATBFLUSH + Disable ATB Flush + [12:12] + read-write + + + FPEXCODIS + Disable FPU exception outputs + [10:10] + read-write + + + DISOOFP + Disable out-of-order FP instruction completion + [9:9] + read-write + + + DISFOLD + Disable dual-issue. + [2:2] + read-write + + + DISMCYCINT + Disable dual-issue. + [0:0] + read-write + + + + + SYST_CSR + 0x0000e010 + Use the SysTick Control and Status Register to enable the SysTick features. + 0x00000000 + + + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only + + + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock. + [2:2] + read-write + + + TICKINT + Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request. + [1:1] + read-write + + + ENABLE + Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled. + [0:0] + read-write + + + + + SYST_RVR + 0x0000e014 + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0x00000000 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] + read-write + + + + + SYST_CVR + 0x0000e018 + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0x00000000 + + + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] + read-write + + + + + SYST_CALIB + 0x0000e01c + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0x00000000 + + + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only + + + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only + + + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + + NVIC_ISER0 + 0x0000e100 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISER1 + 0x0000e104 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER0 + 0x0000e180 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER1 + 0x0000e184 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISPR0 + 0x0000e200 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ISPR1 + 0x0000e204 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR0 + 0x0000e280 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR1 + 0x0000e284 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_IABR0 + 0x0000e300 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IABR1 + 0x0000e304 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS0 + 0x0000e380 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS1 + 0x0000e384 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IPR0 + 0x0000e400 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR1 + 0x0000e404 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR2 + 0x0000e408 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR3 + 0x0000e40c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR4 + 0x0000e410 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR5 + 0x0000e414 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR6 + 0x0000e418 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR7 + 0x0000e41c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR8 + 0x0000e420 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR9 + 0x0000e424 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR10 + 0x0000e428 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR11 + 0x0000e42c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR12 + 0x0000e430 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR13 + 0x0000e434 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR14 + 0x0000e438 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR15 + 0x0000e43c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + CPUID + 0x0000ed00 + Provides identification information for the PE, including an implementer code for the device and a device ID number + 0x411fd210 + + + IMPLEMENTER + This field must hold an implementer code that has been assigned by ARM + [31:24] + read-only + + + VARIANT + IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product + [23:20] + read-only + + + ARCHITECTURE + Defines the Architecture implemented by the PE + [19:16] + read-only + + + PARTNO + IMPLEMENTATION DEFINED primary part number for the device + [15:4] + read-only + + + REVISION + IMPLEMENTATION DEFINED revision number for the device + [3:0] + read-only + + + + + ICSR + 0x0000ed04 + Controls and provides status information for NMI, PendSV, SysTick and interrupts + 0x00000000 + + + PENDNMISET + Indicates whether the NMI exception is pending + [31:31] + read-only + + + PENDNMICLR + Allows the NMI exception pend state to be cleared + [30:30] + read-write + + + PENDSVSET + Indicates whether the PendSV `FTSSS exception is pending + [28:28] + read-only + + + PENDSVCLR + Allows the PendSV exception pend state to be cleared `FTSSS + [27:27] + read-write + + + PENDSTSET + Indicates whether the SysTick `FTSSS exception is pending + [26:26] + read-only + + + PENDSTCLR + Allows the SysTick exception pend state to be cleared `FTSSS + [25:25] + read-write + + + STTNS + Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure + [24:24] + read-write + + + ISRPREEMPT + Indicates whether a pending exception will be serviced on exit from debug halt state + [23:23] + read-only + + + ISRPENDING + Indicates whether an external interrupt, generated by the NVIC, is pending + [22:22] + read-only + + + VECTPENDING + The exception number of the highest priority pending and enabled interrupt + [20:12] + read-only + + + RETTOBASE + In Handler mode, indicates whether there is more than one active exception + [11:11] + read-only + + + VECTACTIVE + The exception number of the current executing exception + [8:0] + read-only + + + + + VTOR + 0x0000ed08 + The VTOR indicates the offset of the vector table base address from memory address 0x00000000. + 0x00000000 + + + TBLOFF + Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. + [31:7] + read-write + + + + + AIRCR + 0x0000ed0c + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0x00000000 + + + VECTKEY + Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] + read-write + + + ENDIANESS + Data endianness implemented: + 0 = Little-endian. + [15:15] + read-only + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. + 0 Priority ranges of Secure and Non-secure exceptions are identical. + 1 Non-secure exceptions are de-prioritized. + [14:14] + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. + 0 BusFault, HardFault, and NMI are Secure. + 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + [13:13] + read-write + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en + [10:8] + read-write + + + SYSRESETREQS + System reset request, Secure state only. + 0 SYSRESETREQ functionality is available to both Security states. + 1 SYSRESETREQ functionality is only available to Secure state. + [3:3] + read-write + + + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + [2:2] + read-write + + + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + [1:1] + read-write + + + + + SCR + 0x0000ed10 + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0x00000000 + + + SEVONPEND + Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] + read-write + + + SLEEPDEEPS + 0 SLEEPDEEP is available to both security states + 1 SLEEPDEEP is only available to Secure state + [3:3] + read-write + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] + read-write + + + + + CCR + 0x0000ed14 + Sets or returns configuration and control data + 0x00000201 + + + BP + Enables program flow prediction `FTSSS + [18:18] + read-only + + + IC + This is a global enable bit for instruction caches in the selected Security state + [17:17] + read-only + + + DC + Enables data caching of all data accesses to Normal memory `FTSSS + [16:16] + read-only + + + STKOFHFNMIGN + Controls the effect of a stack limit violation while executing at a requested priority less than 0 + [10:10] + read-write + + + RES1 + Reserved, RES1 + [9:9] + read-only + + + BFHFNMIGN + Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 + [8:8] + read-write + + + DIV_0_TRP + Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero + [4:4] + read-write + + + UNALIGN_TRP + Controls the trapping of unaligned word or halfword accesses + [3:3] + read-write + + + USERSETMPEND + Determines whether unprivileged accesses are permitted to pend interrupts via the STIR + [1:1] + read-write + + + RES1_1 + Reserved, RES1 + [0:0] + read-only + + + + + SHPR1 + 0x0000ed18 + Sets or returns priority for system handlers 4 - 7 + 0x00000000 + + + PRI_7_3 + Priority of system handler 7, SecureFault + [31:29] + read-write + + + PRI_6_3 + Priority of system handler 6, SecureFault + [23:21] + read-write + + + PRI_5_3 + Priority of system handler 5, SecureFault + [15:13] + read-write + + + PRI_4_3 + Priority of system handler 4, SecureFault + [7:5] + read-write + + + + + SHPR2 + 0x0000ed1c + Sets or returns priority for system handlers 8 - 11 + 0x00000000 + + + PRI_11_3 + Priority of system handler 11, SecureFault + [31:29] + read-write + + + PRI_10 + Reserved, RES0 + [23:16] + read-only + + + PRI_9 + Reserved, RES0 + [15:8] + read-only + + + PRI_8 + Reserved, RES0 + [7:0] + read-only + + + + + SHPR3 + 0x0000ed20 + Sets or returns priority for system handlers 12 - 15 + 0x00000000 + + + PRI_15_3 + Priority of system handler 15, SecureFault + [31:29] + read-write + + + PRI_14_3 + Priority of system handler 14, SecureFault + [23:21] + read-write + + + PRI_13 + Reserved, RES0 + [15:8] + read-only + + + PRI_12_3 + Priority of system handler 12, SecureFault + [7:5] + read-write + + + + + SHCSR + 0x0000ed24 + Provides access to the active and pending status of system exceptions + 0x00000000 + + + HARDFAULTPENDED + `IAAMO the pending state of the HardFault exception `CTTSSS + [21:21] + read-write + + + SECUREFAULTPENDED + `IAAMO the pending state of the SecureFault exception + [20:20] + read-write + + + SECUREFAULTENA + `DW the SecureFault exception is enabled + [19:19] + read-write + + + USGFAULTENA + `DW the UsageFault exception is enabled `FTSSS + [18:18] + read-write + + + BUSFAULTENA + `DW the BusFault exception is enabled + [17:17] + read-write + + + MEMFAULTENA + `DW the MemManage exception is enabled `FTSSS + [16:16] + read-write + + + SVCALLPENDED + `IAAMO the pending state of the SVCall exception `FTSSS + [15:15] + read-write + + + BUSFAULTPENDED + `IAAMO the pending state of the BusFault exception + [14:14] + read-write + + + MEMFAULTPENDED + `IAAMO the pending state of the MemManage exception `FTSSS + [13:13] + read-write + + + USGFAULTPENDED + The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS + [12:12] + read-write + + + SYSTICKACT + `IAAMO the active state of the SysTick exception `FTSSS + [11:11] + read-write + + + PENDSVACT + `IAAMO the active state of the PendSV exception `FTSSS + [10:10] + read-write + + + MONITORACT + `IAAMO the active state of the DebugMonitor exception + [8:8] + read-write + + + SVCALLACT + `IAAMO the active state of the SVCall exception `FTSSS + [7:7] + read-write + + + NMIACT + `IAAMO the active state of the NMI exception + [5:5] + read-write + + + SECUREFAULTACT + `IAAMO the active state of the SecureFault exception + [4:4] + read-write + + + USGFAULTACT + `IAAMO the active state of the UsageFault exception `FTSSS + [3:3] + read-write + + + HARDFAULTACT + Indicates and allows limited modification of the active state of the HardFault exception `FTSSS + [2:2] + read-write + + + BUSFAULTACT + `IAAMO the active state of the BusFault exception + [1:1] + read-write + + + MEMFAULTACT + `IAAMO the active state of the MemManage exception `FTSSS + [0:0] + read-write + + + + + CFSR + 0x0000ed28 + Contains the three Configurable Fault Status Registers. + + 31:16 UFSR: Provides information on UsageFault exceptions + + 15:8 BFSR: Provides information on BusFault exceptions + + 7:0 MMFSR: Provides information on MemManage exceptions + 0x00000000 + + + UFSR_DIVBYZERO + Sticky flag indicating whether an integer division by zero error has occurred + [25:25] + read-write + + + UFSR_UNALIGNED + Sticky flag indicating whether an unaligned access error has occurred + [24:24] + read-write + + + UFSR_STKOF + Sticky flag indicating whether a stack overflow error has occurred + [20:20] + read-write + + + UFSR_NOCP + Sticky flag indicating whether a coprocessor disabled or not present error has occurred + [19:19] + read-write + + + UFSR_INVPC + Sticky flag indicating whether an integrity check error has occurred + [18:18] + read-write + + + UFSR_INVSTATE + Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred + [17:17] + read-write + + + UFSR_UNDEFINSTR + Sticky flag indicating whether an undefined instruction error has occurred + [16:16] + read-write + + + BFSR_BFARVALID + Indicates validity of the contents of the BFAR register + [15:15] + read-write + + + BFSR_LSPERR + Records whether a BusFault occurred during FP lazy state preservation + [13:13] + read-write + + + BFSR_STKERR + Records whether a derived BusFault occurred during exception entry stacking + [12:12] + read-write + + + BFSR_UNSTKERR + Records whether a derived BusFault occurred during exception return unstacking + [11:11] + read-write + + + BFSR_IMPRECISERR + Records whether an imprecise data access error has occurred + [10:10] + read-write + + + BFSR_PRECISERR + Records whether a precise data access error has occurred + [9:9] + read-write + + + BFSR_IBUSERR + Records whether a BusFault on an instruction prefetch has occurred + [8:8] + read-write + + + MMFSR + Provides information on MemManage exceptions + [7:0] + read-write + + + + + HFSR + 0x0000ed2c + Shows the cause of any HardFaults + 0x00000000 + + + DEBUGEVT + Indicates when a Debug event has occurred + [31:31] + read-write + + + FORCED + Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled + [30:30] + read-write + + + VECTTBL + Indicates when a fault has occurred because of a vector table read error on exception processing + [1:1] + read-write + + + + + DFSR + 0x0000ed30 + Shows which debug event occurred + 0x00000000 + + + EXTERNAL + Sticky flag indicating whether an External debug request debug event has occurred + [4:4] + read-write + + + VCATCH + Sticky flag indicating whether a Vector catch debug event has occurred + [3:3] + read-write + + + DWTTRAP + Sticky flag indicating whether a Watchpoint debug event has occurred + [2:2] + read-write + + + BKPT + Sticky flag indicating whether a Breakpoint debug event has occurred + [1:1] + read-write + + + HALTED + Sticky flag indicating that a Halt request debug event or Step debug event has occurred + [0:0] + read-write + + + + + MMFAR + 0x0000ed34 + Shows the address of the memory location that caused an MPU fault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + BFAR + 0x0000ed38 + Shows the address associated with a precise data access BusFault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + ID_PFR0 + 0x0000ed40 + Gives top-level information about the instruction set supported by the PE + 0x00000030 + + + STATE1 + T32 instruction set support + [7:4] + read-only + + + STATE0 + A32 instruction set support + [3:0] + read-only + + + + + ID_PFR1 + 0x0000ed44 + Gives information about the programmers' model and Extensions support + 0x00000520 + + + MPROGMOD + Identifies support for the M-Profile programmers' model support + [11:8] + read-only + + + SECURITY + Identifies whether the Security Extension is implemented + [7:4] + read-only + + + + + ID_DFR0 + 0x0000ed48 + Provides top level information about the debug system + 0x00200000 + + + MPROFDBG + Indicates the supported M-profile debug architecture + [23:20] + read-only + + + + + ID_AFR0 + 0x0000ed4c + Provides information about the IMPLEMENTATION DEFINED features of the PE + 0x00000000 + + + IMPDEF3 + IMPLEMENTATION DEFINED meaning + [15:12] + read-only + + + IMPDEF2 + IMPLEMENTATION DEFINED meaning + [11:8] + read-only + + + IMPDEF1 + IMPLEMENTATION DEFINED meaning + [7:4] + read-only + + + IMPDEF0 + IMPLEMENTATION DEFINED meaning + [3:0] + read-only + + + + + ID_MMFR0 + 0x0000ed50 + Provides information about the implemented memory model and memory management support + 0x00101f40 + + + AUXREG + Indicates support for Auxiliary Control Registers + [23:20] + read-only + + + TCM + Indicates support for tightly coupled memories (TCMs) + [19:16] + read-only + + + SHARELVL + Indicates the number of shareability levels implemented + [15:12] + read-only + + + OUTERSHR + Indicates the outermost shareability domain implemented + [11:8] + read-only + + + PMSA + Indicates support for the protected memory system architecture (PMSA) + [7:4] + read-only + + + + + ID_MMFR1 + 0x0000ed54 + Provides information about the implemented memory model and memory management support + 0x00000000 + + + ID_MMFR1 + [31:0] + read-write + + + + + ID_MMFR2 + 0x0000ed58 + Provides information about the implemented memory model and memory management support + 0x01000000 + + + WFISTALL + Indicates the support for Wait For Interrupt (WFI) stalling + [27:24] + read-only + + + + + ID_MMFR3 + 0x0000ed5c + Provides information about the implemented memory model and memory management support + 0x00000000 + + + BPMAINT + Indicates the supported branch predictor maintenance + [11:8] + read-only + + + CMAINTSW + Indicates the supported cache maintenance operations by set/way + [7:4] + read-only + + + CMAINTVA + Indicates the supported cache maintenance operations by address + [3:0] + read-only + + + + + ID_ISAR0 + 0x0000ed60 + Provides information about the instruction set implemented by the PE + 0x08092300 + + + DIVIDE + Indicates the supported Divide instructions + [27:24] + read-only + + + DEBUG + Indicates the implemented Debug instructions + [23:20] + read-only + + + COPROC + Indicates the supported Coprocessor instructions + [19:16] + read-only + + + CMPBRANCH + Indicates the supported combined Compare and Branch instructions + [15:12] + read-only + + + BITFIELD + Indicates the supported bit field instructions + [11:8] + read-only + + + BITCOUNT + Indicates the supported bit count instructions + [7:4] + read-only + + + + + ID_ISAR1 + 0x0000ed64 + Provides information about the instruction set implemented by the PE + 0x05725000 + + + INTERWORK + Indicates the implemented Interworking instructions + [27:24] + read-only + + + IMMEDIATE + Indicates the implemented for data-processing instructions with long immediates + [23:20] + read-only + + + IFTHEN + Indicates the implemented If-Then instructions + [19:16] + read-only + + + EXTEND + Indicates the implemented Extend instructions + [15:12] + read-only + + + + + ID_ISAR2 + 0x0000ed68 + Provides information about the instruction set implemented by the PE + 0x30173426 + + + REVERSAL + Indicates the implemented Reversal instructions + [31:28] + read-only + + + MULTU + Indicates the implemented advanced unsigned Multiply instructions + [23:20] + read-only + + + MULTS + Indicates the implemented advanced signed Multiply instructions + [19:16] + read-only + + + MULT + Indicates the implemented additional Multiply instructions + [15:12] + read-only + + + MULTIACCESSINT + Indicates the support for interruptible multi-access instructions + [11:8] + read-only + + + MEMHINT + Indicates the implemented Memory Hint instructions + [7:4] + read-only + + + LOADSTORE + Indicates the implemented additional load/store instructions + [3:0] + read-only + + + + + ID_ISAR3 + 0x0000ed6c + Provides information about the instruction set implemented by the PE + 0x07895729 + + + TRUENOP + Indicates the implemented true NOP instructions + [27:24] + read-only + + + T32COPY + Indicates the support for T32 non flag-setting MOV instructions + [23:20] + read-only + + + TABBRANCH + Indicates the implemented Table Branch instructions + [19:16] + read-only + + + SYNCHPRIM + Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions + [15:12] + read-only + + + SVC + Indicates the implemented SVC instructions + [11:8] + read-only + + + SIMD + Indicates the implemented SIMD instructions + [7:4] + read-only + + + SATURATE + Indicates the implemented saturating instructions + [3:0] + read-only + + + + + ID_ISAR4 + 0x0000ed70 + Provides information about the instruction set implemented by the PE + 0x01310132 + + + PSR_M + Indicates the implemented M profile instructions to modify the PSRs + [27:24] + read-only + + + SYNCPRIM_FRAC + Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions + [23:20] + read-only + + + BARRIER + Indicates the implemented Barrier instructions + [19:16] + read-only + + + WRITEBACK + Indicates the support for writeback addressing modes + [11:8] + read-only + + + WITHSHIFTS + Indicates the support for writeback addressing modes + [7:4] + read-only + + + UNPRIV + Indicates the implemented unprivileged instructions + [3:0] + read-only + + + + + ID_ISAR5 + 0x0000ed74 + Provides information about the instruction set implemented by the PE + 0x00000000 + + + ID_ISAR5 + [31:0] + read-write + + + + + CTR + 0x0000ed7c + Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. + 0x8000c000 + + + RES1 + Reserved, RES1 + [31:31] + read-only + + + CWG + Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified + [27:24] + read-only + + + ERG + Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions + [23:20] + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE + [19:16] + read-only + + + RES1_1 + Reserved, RES1 + [15:14] + read-only + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE + [3:0] + read-only + + + + + CPACR + 0x0000ed88 + Specifies the access privileges for coprocessors and the FP Extension + 0x00000000 + + + CP11 + The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN + [23:22] + read-write + + + CP10 + Defines the access rights for the floating-point functionality + [21:20] + read-write + + + CP7 + Controls access privileges for coprocessor 7 + [15:14] + read-write + + + CP6 + Controls access privileges for coprocessor 6 + [13:12] + read-write + + + CP5 + Controls access privileges for coprocessor 5 + [11:10] + read-write + + + CP4 + Controls access privileges for coprocessor 4 + [9:8] + read-write + + + CP3 + Controls access privileges for coprocessor 3 + [7:6] + read-write + + + CP2 + Controls access privileges for coprocessor 2 + [5:4] + read-write + + + CP1 + Controls access privileges for coprocessor 1 + [3:2] + read-write + + + CP0 + Controls access privileges for coprocessor 0 + [1:0] + read-write + + + + + NSACR + 0x0000ed8c + Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + 0x00000000 + + + CP11 + Enables Non-secure access to the Floating-point Extension + [11:11] + read-write + + + CP10 + Enables Non-secure access to the Floating-point Extension + [10:10] + read-write + + + CP7 + Enables Non-secure access to coprocessor CP7 + [7:7] + read-write + + + CP6 + Enables Non-secure access to coprocessor CP6 + [6:6] + read-write + + + CP5 + Enables Non-secure access to coprocessor CP5 + [5:5] + read-write + + + CP4 + Enables Non-secure access to coprocessor CP4 + [4:4] + read-write + + + CP3 + Enables Non-secure access to coprocessor CP3 + [3:3] + read-write + + + CP2 + Enables Non-secure access to coprocessor CP2 + [2:2] + read-write + + + CP1 + Enables Non-secure access to coprocessor CP1 + [1:1] + read-write + + + CP0 + Enables Non-secure access to coprocessor CP0 + [0:0] + read-write + + + + + MPU_TYPE + 0x0000ed90 + The MPU Type Register indicates how many regions the MPU `FTSSS supports + 0x00000800 + + + DREGION + Number of regions supported by the MPU + [15:8] + read-only + + + SEPARATE + Indicates support for separate instructions and data address regions + [0:0] + read-only + + + + + MPU_CTRL + 0x0000ed94 + Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + 0x00000000 + + + PRIVDEFENA + Controls whether the default memory map is enabled for privileged software + [2:2] + read-write + + + HFNMIENA + Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + [1:1] + read-write + + + ENABLE + Enables the MPU + [0:0] + read-write + + + + + MPU_RNR + 0x0000ed98 + Selects the region currently accessed by MPU_RBAR and MPU_RLAR + 0x00000000 + + + REGION + Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + [2:0] + read-write + + + + + MPU_RBAR + 0x0000ed9c + Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR + 0x0000eda0 + Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A1 + 0x0000eda4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A1 + 0x0000eda8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A2 + 0x0000edac + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A2 + 0x0000edb0 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A3 + 0x0000edb4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A3 + 0x0000edb8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_MAIR0 + 0x0000edc0 + Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR3 + Memory attribute encoding for MPU regions with an AttrIndex of 3 + [31:24] + read-write + + + ATTR2 + Memory attribute encoding for MPU regions with an AttrIndex of 2 + [23:16] + read-write + + + ATTR1 + Memory attribute encoding for MPU regions with an AttrIndex of 1 + [15:8] + read-write + + + ATTR0 + Memory attribute encoding for MPU regions with an AttrIndex of 0 + [7:0] + read-write + + + + + MPU_MAIR1 + 0x0000edc4 + Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR7 + Memory attribute encoding for MPU regions with an AttrIndex of 7 + [31:24] + read-write + + + ATTR6 + Memory attribute encoding for MPU regions with an AttrIndex of 6 + [23:16] + read-write + + + ATTR5 + Memory attribute encoding for MPU regions with an AttrIndex of 5 + [15:8] + read-write + + + ATTR4 + Memory attribute encoding for MPU regions with an AttrIndex of 4 + [7:0] + read-write + + + + + SAU_CTRL + 0x0000edd0 + Allows enabling of the Security Attribution Unit + 0x00000000 + + + ALLNS + When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure + [1:1] + read-write + + + ENABLE + Enables the SAU + [0:0] + read-write + + + + + SAU_TYPE + 0x0000edd4 + Indicates the number of regions implemented by the Security Attribution Unit + 0x00000008 + + + SREGION + The number of implemented SAU regions + [7:0] + read-only + + + + + SAU_RNR + 0x0000edd8 + Selects the region currently accessed by SAU_RBAR and SAU_RLAR + 0x00000000 + + + REGION + Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + [7:0] + read-write + + + + + SAU_RBAR + 0x0000eddc + Provides indirect read and write access to the base address of the currently selected SAU region + 0x00000000 + + + BADDR + Holds bits [31:5] of the base address for the selected SAU region + [31:5] + read-write + + + + + SAU_RLAR + 0x0000ede0 + Provides indirect read and write access to the limit address of the currently selected SAU region + 0x00000000 + + + LADDR + Holds bits [31:5] of the limit address for the selected SAU region + [31:5] + read-write + + + NSC + Controls whether Non-secure state is permitted to execute an SG instruction from this region + [1:1] + read-write + + + ENABLE + SAU region enable + [0:0] + read-write + + + + + SFSR + 0x0000ede4 + Provides information about any security related faults + 0x00000000 + + + LSERR + Sticky flag indicating that an error occurred during lazy state activation or deactivation + [7:7] + read-write + + + SFARVALID + This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault + [6:6] + read-write + + + LSPERR + Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state + [5:5] + read-write + + + INVTRAN + Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory + [4:4] + read-write + + + AUVIOL + Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR + [3:3] + read-write + + + INVER + This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state + [2:2] + read-write + + + INVIS + This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation + [1:1] + read-write + + + INVEP + This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set + [0:0] + read-write + + + + + SFAR + 0x0000ede8 + Shows the address of the memory location that caused a Security violation + 0x00000000 + + + ADDRESS + The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state + [31:0] + read-write + + + + + DHCSR + 0x0000edf0 + Controls halting debug + 0x00000000 + + + S_RESTART_ST + Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request + [26:26] + read-only + + + S_RESET_ST + Indicates whether the PE has been reset since the last read of the DHCSR + [25:25] + read-only + + + S_RETIRE_ST + Set to 1 every time the PE retires one of more instructions + [24:24] + read-only + + + S_SDE + Indicates whether Secure invasive debug is allowed + [20:20] + read-only + + + S_LOCKUP + Indicates whether the PE is in Lockup state + [19:19] + read-only + + + S_SLEEP + Indicates whether the PE is sleeping + [18:18] + read-only + + + S_HALT + Indicates whether the PE is in Debug state + [17:17] + read-only + + + S_REGRDY + Handshake flag to transfers through the DCRDR + [16:16] + read-only + + + C_SNAPSTALL + Allow imprecise entry to Debug state + [5:5] + read-write + + + C_MASKINTS + When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts + [3:3] + read-write + + + C_STEP + Enable single instruction step + [2:2] + read-write + + + C_HALT + PE enter Debug state halt request + [1:1] + read-write + + + C_DEBUGEN + Enable Halting debug + [0:0] + read-write + + + + + DCRSR + 0x0000edf4 + With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer + 0x00000000 + + + REGWNR + Specifies the access type for the transfer + [16:16] + read-write + + + REGSEL + Specifies the general-purpose register, special-purpose register, or FP register to transfer + [6:0] + read-write + + + + + DCRDR + 0x0000edf8 + With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE + 0x00000000 + + + DBGTMP + Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers + [31:0] + read-write + + + + + DEMCR + 0x0000edfc + Manages vector catch behavior and DebugMonitor handling when debugging + 0x00000000 + + + TRCENA + Global enable for all DWT and ITM features + [24:24] + read-write + + + SDME + Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state + [20:20] + read-only + + + MON_REQ + DebugMonitor semaphore bit + [19:19] + read-write + + + MON_STEP + Enable DebugMonitor stepping + [18:18] + read-write + + + MON_PEND + Sets or clears the pending state of the DebugMonitor exception + [17:17] + read-write + + + MON_EN + Enable the DebugMonitor exception + [16:16] + read-write + + + VC_SFERR + SecureFault exception halting debug vector catch enable + [11:11] + read-write + + + VC_HARDERR + HardFault exception halting debug vector catch enable + [10:10] + read-write + + + VC_INTERR + Enable halting debug vector catch for faults during exception entry and return + [9:9] + read-write + + + VC_BUSERR + BusFault exception halting debug vector catch enable + [8:8] + read-write + + + VC_STATERR + Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception + [7:7] + read-write + + + VC_CHKERR + Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error + [6:6] + read-write + + + VC_NOCPERR + Enable halting debug trap on a UsageFault caused by an access to a coprocessor + [5:5] + read-write + + + VC_MMERR + Enable halting debug trap on a MemManage exception + [4:4] + read-write + + + VC_CORERESET + Enable Reset Vector Catch. This causes a warm reset to halt a running system + [0:0] + read-write + + + + + DSCSR + 0x0000ee08 + Provides control and status information for Secure debug + 0x00000000 + + + CDSKEY + Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero + [17:17] + read-write + + + CDS + This field indicates the current Security state of the processor + [16:16] + read-write + + + SBRSEL + If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger + [1:1] + read-write + + + SBRSELEN + Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger + [0:0] + read-write + + + + + STIR + 0x0000ef00 + Provides a mechanism for software to generate an interrupt + 0x00000000 + + + INTID + Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) + [8:0] + read-write + + + + + FPCCR + 0x0000ef34 + Holds control data for the Floating-point extension + 0x20000472 + + + ASPEN + When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 + [31:31] + read-write + + + LSPEN + Enables lazy context save of floating-point state + [30:30] + read-write + + + LSPENS + This bit controls whether the LSPEN bit is writeable from the Non-secure state + [29:29] + read-write + + + CLRONRET + Clear floating-point caller saved registers on exception return + [28:28] + read-write + + + CLRONRETS + This bit controls whether the CLRONRET bit is writeable from the Non-secure state + [27:27] + read-write + + + TS + Treat floating-point registers as Secure enable + [26:26] + read-write + + + UFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending + [10:10] + read-write + + + SPLIMVIOL + This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior + [9:9] + read-write + + + MONRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending + [8:8] + read-write + + + SFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state + [7:7] + read-write + + + BFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending + [6:6] + read-write + + + MMRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending + [5:5] + read-write + + + HFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending + [4:4] + read-write + + + THREAD + Indicates the PE mode when it allocated the floating-point stack frame + [3:3] + read-write + + + S + Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed + [2:2] + read-write + + + USER + Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame + [1:1] + read-write + + + LSPACT + Indicates whether lazy preservation of the floating-point state is active + [0:0] + read-write + + + + + FPCAR + 0x0000ef38 + Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + 0x00000000 + + + ADDRESS + The location of the unpopulated floating-point register space allocated on an exception stack frame + [31:3] + read-write + + + + + FPDSCR + 0x0000ef3c + Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context + 0x00000000 + + + AHP + Default value for FPSCR.AHP + [26:26] + read-write + + + DN + Default value for FPSCR.DN + [25:25] + read-write + + + FZ + Default value for FPSCR.FZ + [24:24] + read-write + + + RMODE + Default value for FPSCR.RMode + [23:22] + read-write + + + + + MVFR0 + 0x0000ef40 + Describes the features provided by the Floating-point Extension + 0x60540601 + + + FPROUND + Indicates the rounding modes supported by the FP Extension + [31:28] + read-only + + + FPSQRT + Indicates the support for FP square root operations + [23:20] + read-only + + + FPDIVIDE + Indicates the support for FP divide operations + [19:16] + read-only + + + FPDP + Indicates support for FP double-precision operations + [11:8] + read-only + + + FPSP + Indicates support for FP single-precision operations + [7:4] + read-only + + + SIMDREG + Indicates size of FP register file + [3:0] + read-only + + + + + MVFR1 + 0x0000ef44 + Describes the features provided by the Floating-point Extension + 0x85000089 + + + FMAC + Indicates whether the FP Extension implements the fused multiply accumulate instructions + [31:28] + read-only + + + FPHP + Indicates whether the FP Extension implements half-precision FP conversion instructions + [27:24] + read-only + + + FPDNAN + Indicates whether the FP hardware implementation supports NaN propagation + [7:4] + read-only + + + FPFTZ + Indicates whether subnormals are always flushed-to-zero + [3:0] + read-only + + + + + MVFR2 + 0x0000ef48 + Describes the features provided by the Floating-point Extension + 0x00000060 + + + FPMISC + Indicates support for miscellaneous FP features + [7:4] + read-only + + + + + DDEVARCH + 0x0000efbc + Provides CoreSight discovery information for the SCS + 0x47702a04 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DDEVTYPE + 0x0000efcc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + CoreSight major type + [3:0] + read-only + + + + + DPIDR4 + 0x0000efd0 + Provides CoreSight discovery information for the SCS + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR5 + 0x0000efd4 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR5 + [31:0] + read-write + + + + + DPIDR6 + 0x0000efd8 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR6 + [31:0] + read-write + + + + + DPIDR7 + 0x0000efdc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR7 + [31:0] + read-write + + + + + DPIDR0 + 0x0000efe0 + Provides CoreSight discovery information for the SCS + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DPIDR1 + 0x0000efe4 + Provides CoreSight discovery information for the SCS + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR2 + 0x0000efe8 + Provides CoreSight discovery information for the SCS + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DPIDR3 + 0x0000efec + Provides CoreSight discovery information for the SCS + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR0 + 0x0000eff0 + Provides CoreSight discovery information for the SCS + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR1 + 0x0000eff4 + Provides CoreSight discovery information for the SCS + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR2 + 0x0000eff8 + Provides CoreSight discovery information for the SCS + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR3 + 0x0000effc + Provides CoreSight discovery information for the SCS + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + TRCPRGCTLR + 0x00041004 + Programming Control Register + 0x00000000 + + + EN + Trace Unit Enable + [0:0] + read-write + + + + + TRCSTATR + 0x0004100c + The TRCSTATR indicates the ETM-Teal status + 0x00000000 + + + PMSTABLE + Indicates whether the ETM-Teal registers are stable and can be read + [1:1] + read-only + + + IDLE + Indicates that the trace unit is inactive + [0:0] + read-only + + + + + TRCCONFIGR + 0x00041010 + The TRCCONFIGR sets the basic tracing options for the trace unit + 0x00000000 + + + RS + Return stack enable + [12:12] + read-write + + + TS + Global timestamp tracing + [11:11] + read-write + + + COND + Conditional instruction tracing + [10:5] + read-write + + + CCI + Cycle counting in instruction trace + [4:4] + read-write + + + BB + Branch broadcast mode + [3:3] + read-write + + + + + TRCEVENTCTL0R + 0x00041020 + The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. + 0x00000000 + + + TYPE1 + Selects the resource type for event 1 + [15:15] + read-write + + + SEL1 + Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] + [10:8] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [2:0] + read-write + + + + + TRCEVENTCTL1R + 0x00041024 + The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + 0x00000000 + + + LPOVERRIDE + Low power state behavior override + [12:12] + read-write + + + ATB + ATB enabled + [11:11] + read-write + + + INSTEN1 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [1:1] + read-write + + + INSTEN0 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [0:0] + read-write + + + + + TRCSTALLCTLR + 0x0004102c + The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow + 0x00000000 + + + INSTPRIORITY + Reserved, RES0 + [10:10] + read-only + + + ISTALL + Stall processor based on instruction trace buffer space + [8:8] + read-write + + + LEVEL + Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow + [3:2] + read-write + + + + + TRCTSCTLR + 0x00041030 + The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream + 0x00000000 + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCSYNCPR + 0x00041034 + The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two + 0x0000000a + + + PERIOD + Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes + [4:0] + read-only + + + + + TRCCCCTLR + 0x00041038 + The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets + 0x00000000 + + + THRESHOLD + Instruction trace cycle count threshold + [11:0] + read-write + + + + + TRCVICTLR + 0x00041080 + The TRCVICTLR controls instruction trace filtering + 0x00000000 + + + EXLEVEL_S3 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [19:19] + read-write + + + EXLEVEL_S0 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [16:16] + read-write + + + TRCERR + Selects whether a system error exception must always be traced + [11:11] + read-write + + + TRCRESET + Selects whether a reset exception must always be traced + [10:10] + read-write + + + SSSTATUS + Indicates the current status of the start/stop logic + [9:9] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCCNTRLDVR0 + 0x00041140 + The TRCCNTRLDVR defines the reload value for the reduced function counter + 0x00000000 + + + VALUE + Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs + [15:0] + read-write + + + + + TRCIDR8 + 0x00041180 + TRCIDR8 + 0x00000000 + + + MAXSPEC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR9 + 0x00041184 + TRCIDR9 + 0x00000000 + + + NUMP0KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR10 + 0x00041188 + TRCIDR10 + 0x00000000 + + + NUMP1KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR11 + 0x0004118c + TRCIDR11 + 0x00000000 + + + NUMP1SPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR12 + 0x00041190 + TRCIDR12 + 0x00000001 + + + NUMCONDKEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR13 + 0x00041194 + TRCIDR13 + 0x00000000 + + + NUMCONDSPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIMSPEC + 0x000411c0 + The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided + 0x00000000 + + + SUPPORT + Reserved, RES0 + [3:0] + read-only + + + + + TRCIDR0 + 0x000411e0 + TRCIDR0 + 0x280006e1 + + + COMMOPT + reads as `ImpDef + [29:29] + read-only + + + TSSIZE + reads as `ImpDef + [28:24] + read-only + + + TRCEXDATA + reads as `ImpDef + [17:17] + read-only + + + QSUPP + reads as `ImpDef + [16:15] + read-only + + + QFILT + reads as `ImpDef + [14:14] + read-only + + + CONDTYPE + reads as `ImpDef + [13:12] + read-only + + + NUMEVENT + reads as `ImpDef + [11:10] + read-only + + + RETSTACK + reads as `ImpDef + [9:9] + read-only + + + TRCCCI + reads as `ImpDef + [7:7] + read-only + + + TRCCOND + reads as `ImpDef + [6:6] + read-only + + + TRCBB + reads as `ImpDef + [5:5] + read-only + + + TRCDATA + reads as `ImpDef + [4:3] + read-only + + + INSTP0 + reads as `ImpDef + [2:1] + read-only + + + RES1 + Reserved, RES1 + [0:0] + read-only + + + + + TRCIDR1 + 0x000411e4 + TRCIDR1 + 0x4100f421 + + + DESIGNER + reads as `ImpDef + [31:24] + read-only + + + RES1 + Reserved, RES1 + [15:12] + read-only + + + TRCARCHMAJ + reads as 0b0100 + [11:8] + read-only + + + TRCARCHMIN + reads as 0b0000 + [7:4] + read-only + + + REVISION + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR2 + 0x000411e8 + TRCIDR2 + 0x00000004 + + + CCSIZE + reads as `ImpDef + [28:25] + read-only + + + DVSIZE + reads as `ImpDef + [24:20] + read-only + + + DASIZE + reads as `ImpDef + [19:15] + read-only + + + VMIDSIZE + reads as `ImpDef + [14:10] + read-only + + + CIDSIZE + reads as `ImpDef + [9:5] + read-only + + + IASIZE + reads as `ImpDef + [4:0] + read-only + + + + + TRCIDR3 + 0x000411ec + TRCIDR3 + 0x0f090004 + + + NOOVERFLOW + reads as `ImpDef + [31:31] + read-only + + + NUMPROC + reads as `ImpDef + [30:28] + read-only + + + SYSSTALL + reads as `ImpDef + [27:27] + read-only + + + STALLCTL + reads as `ImpDef + [26:26] + read-only + + + SYNCPR + reads as `ImpDef + [25:25] + read-only + + + TRCERR + reads as `ImpDef + [24:24] + read-only + + + EXLEVEL_NS + reads as `ImpDef + [23:20] + read-only + + + EXLEVEL_S + reads as `ImpDef + [19:16] + read-only + + + CCITMIN + reads as `ImpDef + [11:0] + read-only + + + + + TRCIDR4 + 0x000411f0 + TRCIDR4 + 0x00114000 + + + NUMVMIDC + reads as `ImpDef + [31:28] + read-only + + + NUMCIDC + reads as `ImpDef + [27:24] + read-only + + + NUMSSCC + reads as `ImpDef + [23:20] + read-only + + + NUMRSPAIR + reads as `ImpDef + [19:16] + read-only + + + NUMPC + reads as `ImpDef + [15:12] + read-only + + + SUPPDAC + reads as `ImpDef + [8:8] + read-only + + + NUMDVC + reads as `ImpDef + [7:4] + read-only + + + NUMACPAIRS + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR5 + 0x000411f4 + TRCIDR5 + 0x90c70004 + + + REDFUNCNTR + reads as `ImpDef + [31:31] + read-only + + + NUMCNTR + reads as `ImpDef + [30:28] + read-only + + + NUMSEQSTATE + reads as `ImpDef + [27:25] + read-only + + + LPOVERRIDE + reads as `ImpDef + [23:23] + read-only + + + ATBTRIG + reads as `ImpDef + [22:22] + read-only + + + TRACEIDSIZE + reads as 0x07 + [21:16] + read-only + + + NUMEXTINSEL + reads as `ImpDef + [11:9] + read-only + + + NUMEXTIN + reads as `ImpDef + [8:0] + read-only + + + + + TRCIDR6 + 0x000411f8 + TRCIDR6 + 0x00000000 + + + TRCIDR6 + [31:0] + read-write + + + + + TRCIDR7 + 0x000411fc + TRCIDR7 + 0x00000000 + + + TRCIDR7 + [31:0] + read-write + + + + + TRCRSCTLR2 + 0x00041208 + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCRSCTLR3 + 0x0004120c + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCSSCSR + 0x000412a0 + Controls the corresponding single-shot comparator resource + 0x00000000 + + + STATUS + Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched + [31:31] + read-write + + + PC + Reserved, RES1 + [3:3] + read-only + + + DV + Reserved, RES0 + [2:2] + read-only + + + DA + Reserved, RES0 + [1:1] + read-only + + + INST + Reserved, RES0 + [0:0] + read-only + + + + + TRCSSPCICR + 0x000412c0 + Selects the PE comparator inputs for Single-shot control + 0x00000000 + + + PC + Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control + [3:0] + read-write + + + + + TRCPDCR + 0x00041310 + Requests the system to provide power to the trace unit + 0x00000000 + + + PU + Powerup request bit: + [3:3] + read-write + + + + + TRCPDSR + 0x00041314 + Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status + 0x00000003 + + + OSLK + OS Lock status bit: + [5:5] + read-only + + + STICKYPD + Sticky powerdown status bit. Indicates whether the trace register state is valid: + [1:1] + read-only + + + POWER + Power status bit: + [0:0] + read-only + + + + + TRCITATBIDR + 0x00041ee4 + Trace Integration ATB Identification Register + 0x00000000 + + + ID + Trace ID + [6:0] + read-write + + + + + TRCITIATBINR + 0x00041ef4 + Trace Integration Instruction ATB In Register + 0x00000000 + + + AFVALIDM + Integration Mode instruction AFVALIDM in + [1:1] + read-write + + + ATREADYM + Integration Mode instruction ATREADYM in + [0:0] + read-write + + + + + TRCITIATBOUTR + 0x00041efc + Trace Integration Instruction ATB Out Register + 0x00000000 + + + AFREADY + Integration Mode instruction AFREADY out + [1:1] + read-write + + + ATVALID + Integration Mode instruction ATVALID out + [0:0] + read-write + + + + + TRCCLAIMSET + 0x00041fa0 + Claim Tag Set Register + 0x0000000f + + + SET3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + SET2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + SET1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + SET0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCCLAIMCLR + 0x00041fa4 + Claim Tag Clear Register + 0x00000000 + + + CLR3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + CLR2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + CLR1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + CLR0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCAUTHSTATUS + 0x00041fb8 + Returns the level of tracing that the trace unit can support + 0x00000000 + + + SNID + Indicates whether the system enables the trace unit to support Secure non-invasive debug: + [7:6] + read-only + + + SID + Indicates whether the trace unit supports Secure invasive debug: + [5:4] + read-only + + + NSNID + Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: + [3:2] + read-only + + + NSID + Indicates whether the trace unit supports Non-secure invasive debug: + [1:0] + read-only + + + + + TRCDEVARCH + 0x00041fbc + TRCDEVARCH + 0x47724a13 + + + ARCHITECT + reads as 0b01000111011 + [31:21] + read-only + + + PRESENT + reads as 0b1 + [20:20] + read-only + + + REVISION + reads as 0b0000 + [19:16] + read-only + + + ARCHID + reads as 0b0100101000010011 + [15:0] + read-only + + + + + TRCDEVID + 0x00041fc8 + TRCDEVID + 0x00000000 + + + TRCDEVID + [31:0] + read-write + + + + + TRCDEVTYPE + 0x00041fcc + TRCDEVTYPE + 0x00000013 + + + SUB + reads as 0b0001 + [7:4] + read-only + + + MAJOR + reads as 0b0011 + [3:0] + read-only + + + + + TRCPIDR4 + 0x00041fd0 + TRCPIDR4 + 0x00000004 + + + SIZE + reads as `ImpDef + [7:4] + read-only + + + DES_2 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR5 + 0x00041fd4 + TRCPIDR5 + 0x00000000 + + + TRCPIDR5 + [31:0] + read-write + + + + + TRCPIDR6 + 0x00041fd8 + TRCPIDR6 + 0x00000000 + + + TRCPIDR6 + [31:0] + read-write + + + + + TRCPIDR7 + 0x00041fdc + TRCPIDR7 + 0x00000000 + + + TRCPIDR7 + [31:0] + read-write + + + + + TRCPIDR0 + 0x00041fe0 + TRCPIDR0 + 0x00000021 + + + PART_0 + reads as `ImpDef + [7:0] + read-only + + + + + TRCPIDR1 + 0x00041fe4 + TRCPIDR1 + 0x000000bd + + + DES_0 + reads as `ImpDef + [7:4] + read-only + + + PART_0 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR2 + 0x00041fe8 + TRCPIDR2 + 0x0000002b + + + REVISION + reads as `ImpDef + [7:4] + read-only + + + JEDEC + reads as 0b1 + [3:3] + read-only + + + DES_0 + reads as `ImpDef + [2:0] + read-only + + + + + TRCPIDR3 + 0x00041fec + TRCPIDR3 + 0x00000000 + + + REVAND + reads as `ImpDef + [7:4] + read-only + + + CMOD + reads as `ImpDef + [3:0] + read-only + + + + + TRCCIDR0 + 0x00041ff0 + TRCCIDR0 + 0x0000000d + + + PRMBL_0 + reads as 0b00001101 + [7:0] + read-only + + + + + TRCCIDR1 + 0x00041ff4 + TRCCIDR1 + 0x00000090 + + + CLASS + reads as 0b1001 + [7:4] + read-only + + + PRMBL_1 + reads as 0b0000 + [3:0] + read-only + + + + + TRCCIDR2 + 0x00041ff8 + TRCCIDR2 + 0x00000005 + + + PRMBL_2 + reads as 0b00000101 + [7:0] + read-only + + + + + TRCCIDR3 + 0x00041ffc + TRCCIDR3 + 0x000000b1 + + + PRMBL_3 + reads as 0b10110001 + [7:0] + read-only + + + + + CTICONTROL + 0x00042000 + CTI Control Register + 0x00000000 + + + GLBEN + Enables or disables the CTI + [0:0] + read-write + + + + + CTIINTACK + 0x00042010 + CTI Interrupt Acknowledge Register + 0x00000000 + + + INTACK + Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. + [7:0] + read-write + + + + + CTIAPPSET + 0x00042014 + CTI Application Trigger Set Register + 0x00000000 + + + APPSET + Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel + [3:0] + read-write + + + + + CTIAPPCLEAR + 0x00042018 + CTI Application Trigger Clear Register + 0x00000000 + + + APPCLEAR + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIAPPPULSE + 0x0004201c + CTI Application Pulse Register + 0x00000000 + + + APPULSE + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIINEN0 + 0x00042020 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN1 + 0x00042024 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN2 + 0x00042028 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN3 + 0x0004202c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN4 + 0x00042030 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN5 + 0x00042034 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN6 + 0x00042038 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN7 + 0x0004203c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIOUTEN0 + 0x000420a0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN1 + 0x000420a4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN2 + 0x000420a8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN3 + 0x000420ac + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN4 + 0x000420b0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN5 + 0x000420b4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN6 + 0x000420b8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN7 + 0x000420bc + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTITRIGINSTATUS + 0x00042130 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINSTATUS + Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. + [7:0] + read-only + + + + + CTITRIGOUTSTATUS + 0x00042134 + CTI Trigger In Status Register + 0x00000000 + + + TRIGOUTSTATUS + Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. + [7:0] + read-only + + + + + CTICHINSTATUS + 0x00042138 + CTI Channel In Status Register + 0x00000000 + + + CTICHOUTSTATUS + Shows the status of the ctichout outputs. There is one bit of the field for each channel output + [3:0] + read-only + + + + + CTIGATE + 0x00042140 + Enable CTI Channel Gate register + 0x0000000f + + + CTIGATEEN3 + Enable ctichout3. Set to 0 to disable channel propagation. + [3:3] + read-write + + + CTIGATEEN2 + Enable ctichout2. Set to 0 to disable channel propagation. + [2:2] + read-write + + + CTIGATEEN1 + Enable ctichout1. Set to 0 to disable channel propagation. + [1:1] + read-write + + + CTIGATEEN0 + Enable ctichout0. Set to 0 to disable channel propagation. + [0:0] + read-write + + + + + ASICCTL + 0x00042144 + External Multiplexer Control register + 0x00000000 + + + ASICCTL + [31:0] + read-write + + + + + ITCHOUT + 0x00042ee4 + Integration Test Channel Output register + 0x00000000 + + + CTCHOUT + Sets the value of the ctichout outputs + [3:0] + read-write + + + + + ITTRIGOUT + 0x00042ee8 + Integration Test Trigger Output register + 0x00000000 + + + CTTRIGOUT + Sets the value of the ctitrigout outputs + [7:0] + read-write + + + + + ITCHIN + 0x00042ef4 + Integration Test Channel Input register + 0x00000000 + + + CTCHIN + Reads the value of the ctichin inputs. + [3:0] + read-only + + + + + ITCTRL + 0x00042f00 + Integration Mode Control register + 0x00000000 + + + IME + Integration Mode Enable + [0:0] + read-write + + + + + DEVARCH + 0x00042fbc + Device Architecture register + 0x47701a14 + + + ARCHITECT + Indicates the component architect + [31:21] + read-only + + + PRESENT + Indicates whether the DEVARCH register is present + [20:20] + read-only + + + REVISION + Indicates the architecture revision + [19:16] + read-only + + + ARCHID + Indicates the component + [15:0] + read-only + + + + + DEVID + 0x00042fc8 + Device Configuration register + 0x00040800 + + + NUMCH + Number of ECT channels available + [19:16] + read-only + + + NUMTRIG + Number of ECT triggers available. + [15:8] + read-only + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. + [4:0] + read-only + + + + + DEVTYPE + 0x00042fcc + Device Type Identifier register + 0x00000014 + + + SUB + Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. + [7:4] + read-only + + + MAJOR + Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. + [3:0] + read-only + + + + + PIDR4 + 0x00042fd0 + CoreSight Peripheral ID4 + 0x00000004 + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory + [7:4] + read-only + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [3:0] + read-only + + + + + PIDR5 + 0x00042fd4 + CoreSight Peripheral ID5 + 0x00000000 + + + PIDR5 + [31:0] + read-write + + + + + PIDR6 + 0x00042fd8 + CoreSight Peripheral ID6 + 0x00000000 + + + PIDR6 + [31:0] + read-write + + + + + PIDR7 + 0x00042fdc + CoreSight Peripheral ID7 + 0x00000000 + + + PIDR7 + [31:0] + read-write + + + + + PIDR0 + 0x00042fe0 + CoreSight Peripheral ID0 + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + [7:0] + read-only + + + + + PIDR1 + 0x00042fe4 + CoreSight Peripheral ID1 + 0x000000bd + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [7:4] + read-only + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + [3:0] + read-only + + + + + PIDR2 + 0x00042fe8 + CoreSight Peripheral ID2 + 0x0000000b + + + REVISION + This device is at r1p0 + [7:4] + read-only + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + [3:3] + read-only + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [2:0] + read-only + + + + + PIDR3 + 0x00042fec + CoreSight Peripheral ID3 + 0x00000000 + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + [7:4] + read-only + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. + [3:0] + read-only + + + + + CIDR0 + 0x00042ff0 + CoreSight Component ID0 + 0x0000000d + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code + [7:0] + read-only + + + + + CIDR1 + 0x00042ff4 + CoreSight Component ID1 + 0x00000090 + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. + [7:4] + read-only + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + [3:0] + read-only + + + + + CIDR2 + 0x00042ff8 + CoreSight Component ID2 + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + [7:0] + read-only + + + + + CIDR3 + 0x00042ffc + CoreSight Component ID3 + 0x000000b1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + [7:0] + read-only + + + + + + + PPB_NS + 0xe0020000 + + + QMI + QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. + 0x400d0000 + + 0 + 84 + registers + + + + DIRECT_CSR + 0x00000000 + Control and status for direct serial mode + + Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. + 0x01800000 + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) + [31:30] + read-write + + + CLKDIV + Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. + [29:22] + read-write + + + RXLEVEL + Current level of DIRECT_RX FIFO + [20:18] + read-only + + + RXFULL + When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. + [17:17] + read-only + + + RXEMPTY + When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. + [16:16] + read-only + + + TXLEVEL + Current level of DIRECT_TX FIFO + [14:12] + read-only + + + TXEMPTY + When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. + [11:11] + read-only + + + TXFULL + When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. + [10:10] + read-only + + + AUTO_CS1N + When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. + [7:7] + read-write + + + AUTO_CS0N + When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. + [6:6] + read-write + + + ASSERT_CS1N + When 1, assert (i.e. drive low) the CS1n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [3:3] + read-write + + + ASSERT_CS0N + When 1, assert (i.e. drive low) the CS0n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [2:2] + read-write + + + BUSY + Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. + + The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. + + (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) + [1:1] + read-only + + + EN + Enable direct mode. + + In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. + + Memory-mapped accesses will generate bus errors when direct serial mode is enabled. + [0:0] + read-write + + + + + DIRECT_TX + 0x00000004 + Transmit FIFO for direct mode + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + DIRECT_RX + 0x00000008 + Receive FIFO for direct mode + 0x00000000 + + + DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + M0_TIMING + 0x0000000c + Timing configuration register for memory address window 0. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M0_RFMT + 0x00000010 + Read transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_RCMD + 0x00000014 + Command constants used for reads from memory address window 0. + + The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M0_WFMT + 0x00000018 + Write transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_WCMD + 0x0000001c + Command constants used for writes to memory address window 0. + + The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_TIMING + 0x00000020 + Timing configuration register for memory address window 1. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M1_RFMT + 0x00000024 + Read transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_RCMD + 0x00000028 + Command constants used for reads from memory address window 1. + + The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_WFMT + 0x0000002c + Write transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_WCMD + 0x00000030 + Command constants used for writes to memory address window 1. + + The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + ATRANS0 + 0x00000034 + Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS1 + 0x00000038 + Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS2 + 0x0000003c + Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS3 + 0x00000040 + Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS4 + 0x00000044 + Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS5 + 0x00000048 + Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS6 + 0x0000004c + Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS7 + 0x00000050 + Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + + + XIP_CTRL + QSPI flash execute-in-place block + 0x400c8000 + + 0 + 32 + registers + + + + CTRL + 0x00000000 + Cache control register. Read-only from a Non-secure context. + 0x00000083 + + + WRITABLE_M1 + If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [11:11] + read-write + + + WRITABLE_M0 + If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [10:10] + read-write + + + SPLIT_WAYS + When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. + + This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. + + A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. + [9:9] + read-write + + + MAINT_NONSEC + When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. + + Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. + + Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. + [8:8] + read-write + + + NO_UNTRANSLATED_NONSEC + When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [7:7] + read-write + + + NO_UNTRANSLATED_SEC + When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [6:6] + read-write + + + NO_UNCACHED_NONSEC + When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [5:5] + read-write + + + NO_UNCACHED_SEC + When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [4:4] + read-write + + + POWER_DOWN + When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. + [3:3] + read-write + + + EN_NONSECURE + When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + [1:1] + read-write + + + EN_SECURE + When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + + There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. + [0:0] + read-write + + + + + STAT + 0x00000008 + 0x00000002 + + + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. + [2:2] + read-only + + + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. + [1:1] + read-only + + + + + CTR_HIT + 0x0000000c + Cache Hit counter + 0x00000000 + + + CTR_HIT + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + CTR_ACC + 0x00000010 + Cache Access counter + 0x00000000 + + + CTR_ACC + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + STREAM_ADDR + 0x00000014 + FIFO stream address + 0x00000000 + + + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + + STREAM_CTR + 0x00000018 + FIFO stream control + 0x00000000 + + + STREAM_CTR + Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + + STREAM_FIFO + 0x0000001c + FIFO stream data + 0x00000000 + + + STREAM_FIFO + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + [31:0] + read-only + modify + + + + + + + XIP_AUX + Auxiliary DMA access to XIP FIFOs, via fast AHB bus access + 0x50500000 + + 0 + 12 + registers + + + + STREAM + 0x00000000 + Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + 0x00000000 + + + STREAM + [31:0] + read-only + modify + + + + + QMI_DIRECT_TX + 0x00000004 + Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + QMI_DIRECT_RX + 0x00000008 + Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + 0x00000000 + + + QMI_DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + + + SYSCFG + Register block for various chip control signals + 0x40008000 + + 0 + 24 + registers + + + + PROC_CONFIG + 0x00000000 + Configuration for processors + 0x00000000 + + + PROC1_HALTED + Indication that proc1 has halted + [1:1] + read-only + + + PROC0_HALTED + Indication that proc0 has halted + [0:0] + read-only + + + + + PROC_IN_SYNC_BYPASS + 0x00000004 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...31. + 0x00000000 + + + GPIO + [31:0] + read-write + + + + + PROC_IN_SYNC_BYPASS_HI + 0x00000008 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + DBGFORCE + 0x0000000c + Directly control the chip SWD debug port + 0x00000006 + + + ATTACH + Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. + [3:3] + read-write + + + SWCLK + Directly drive SWCLK, if ATTACH is set + [2:2] + read-write + + + SWDI + Directly drive SWDIO input, if ATTACH is set + [1:1] + read-write + + + SWDO + Observe the value of SWDIO output. + [0:0] + read-only + + + + + MEMPOWERDOWN + 0x00000010 + Control PD pins to memories. + Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible + Use with caution + 0x00000000 + + + BOOTRAM + [12:12] + read-write + + + ROM + [11:11] + read-write + + + USB + [10:10] + read-write + + + SRAM9 + [9:9] + read-write + + + SRAM8 + [8:8] + read-write + + + SRAM7 + [7:7] + read-write + + + SRAM6 + [6:6] + read-write + + + SRAM5 + [5:5] + read-write + + + SRAM4 + [4:4] + read-write + + + SRAM3 + [3:3] + read-write + + + SRAM2 + [2:2] + read-write + + + SRAM1 + [1:1] + read-write + + + SRAM0 + [0:0] + read-write + + + + + AUXCTRL + 0x00000014 + Auxiliary system control register + 0x00000000 + + + AUXCTRL + * Bits 7:2: Reserved + + * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. + + * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. + [7:0] + read-write + + + + + + + XOSC + Controls the crystal oscillator + 0x40048000 + + 0 + 20 + registers + + + + CTRL + 0x00000000 + Crystal Oscillator Control + 0x00000000 + + + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE + [11:0] + read-write + + + 1_15MHZ + 2720 + + + 10_30MHZ + 2721 + + + 25_60MHZ + 2722 + + + 40_100MHZ + 2723 + + + + + + + STATUS + 0x00000004 + Crystal Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting + [1:0] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + + + DORMANT + 0x00000008 + Crystal Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: stop the PLLs before selecting dormant mode + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + STARTUP + 0x0000000c + Controls the startup delay + 0x00000000 + + + X4 + Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write + + + + + COUNT + 0x00000010 + A down counter running at the xosc frequency which counts to zero and stops. + Can be used for short software pauses when setting up time sensitive hardware. + To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. + Minimum count value is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + PLL_SYS + 0x40050000 + + 0 + 32 + registers + + + PLL_SYS_IRQ + 42 + + + + CS + 0x00000000 + Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz + 0x00000001 + + + LOCK + PLL is locked + [31:31] + read-only + + + LOCK_N + PLL is not locked + Ideally this is cleared when PLL lock is seen and this should never normally be set + [30:30] + read-write + oneToClear + + + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] + read-write + + + REFDIV + Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] + read-write + + + + + PWR + 0x00000004 + Controls the PLL power modes. + 0x0000002d + + + VCOPD + PLL VCO powerdown + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown + To save power set high when PLL output not required or bypass=1. + [3:3] + read-write + + + DSMPD + PLL DSM powerdown + Nothing is achieved by setting this low. + [2:2] + read-write + + + PD + PLL powerdown + To save power set high when PLL output not required. + [0:0] + read-write + + + + + FBDIV_INT + 0x00000008 + Feedback divisor + (note: this PLL does not support fractional division) + 0x00000000 + + + FBDIV_INT + see ctrl reg description for constraints + [11:0] + read-write + + + + + PRIM + 0x0000000c + Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 + 0x00077000 + + + POSTDIV1 + divide by 1-7 + [18:16] + read-write + + + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + INTR + 0x00000010 + Raw Interrupts + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000014 + Interrupt Enable + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTF + 0x00000018 + Interrupt Force + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTS + 0x0000001c + Interrupt status after masking & forcing + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-only + + + + + + + PLL_USB + 0x40058000 + + PLL_USB_IRQ + 43 + + + + ACCESSCTRL + Hardware access control registers + 0x40060000 + + 0 + 236 + registers + + + + LOCK + 0x00000000 + Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. + + LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL + + Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. + 0x00000004 + + + DEBUG + [3:3] + read-write + + + DMA + [2:2] + read-only + + + CORE1 + [1:1] + read-write + + + CORE0 + [0:0] + read-write + + + + + FORCE_CORE_NS + 0x00000004 + Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. + + Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. + 0x00000000 + + + CORE1 + [1:1] + read-write + + + + + CFGRESET + 0x00000008 + Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. + + This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. + + Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. + 0x00000000 + + + CFGRESET + [0:0] + write-only + + + + + GPIO_NSMASK0 + 0x0000000c + Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. + + 0 -> Secure access only + + 1 -> Secure + Non-secure access + 0x00000000 + + + GPIO_NSMASK0 + [31:0] + read-write + + + + + GPIO_NSMASK1 + 0x00000010 + Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + ROM + 0x00000014 + Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_MAIN + 0x00000018 + Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_MAIN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM0 + 0x0000001c + Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM1 + 0x00000020 + Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM2 + 0x00000024 + Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM3 + 0x00000028 + Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM3 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM3 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM4 + 0x0000002c + Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM4 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM4 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM5 + 0x00000030 + Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM5 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM5 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM6 + 0x00000034 + Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM6 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM6 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM7 + 0x00000038 + Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM7 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM7 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM8 + 0x0000003c + Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM8 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM8 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM9 + 0x00000040 + Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM9 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM9 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + DMA + 0x00000044 + Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, DMA can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, DMA can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + USBCTRL + 0x00000048 + Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, USBCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, USBCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO0 + 0x0000004c + Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO1 + 0x00000050 + Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO2 + 0x00000054 + Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_TRACE + 0x00000058 + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_PERIPH + 0x0000005c + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSINFO + 0x00000060 + Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSINFO can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSINFO can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RESETS + 0x00000064 + Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RESETS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RESETS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK0 + 0x00000068 + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK1 + 0x0000006c + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_BANK0 + 0x00000070 + Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_QSPI + 0x00000074 + Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_QSPI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + BUSCTRL + 0x00000078 + Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, BUSCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ADC0 + 0x0000007c + Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ADC0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ADC0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + HSTX + 0x00000080 + Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, HSTX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, HSTX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C0 + 0x00000084 + Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C1 + 0x00000088 + Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PWM + 0x0000008c + Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PWM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PWM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI0 + 0x00000090 + Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI1 + 0x00000094 + Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER0 + 0x00000098 + Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER1 + 0x0000009c + Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART0 + 0x000000a0 + Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART1 + 0x000000a4 + Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + OTP + 0x000000a8 + Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, OTP can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, OTP can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TBMAN + 0x000000ac + Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TBMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TBMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + POWMAN + 0x000000b0 + Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, POWMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, POWMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TRNG + 0x000000b4 + Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TRNG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TRNG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SHA256 + 0x000000b8 + Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SHA256 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SHA256 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSCFG + 0x000000bc + Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSCFG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSCFG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CLOCKS + 0x000000c0 + Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CLOCKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CLOCKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XOSC + 0x000000c4 + Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XOSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XOSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ROSC + 0x000000c8 + Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_SYS + 0x000000cc + Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_SYS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_USB + 0x000000d0 + Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_USB can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_USB can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TICKS + 0x000000d4 + Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TICKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TICKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + WATCHDOG + 0x000000d8 + Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, WATCHDOG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RSM + 0x000000dc + Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RSM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RSM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_CTRL + 0x000000e0 + Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_CTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_QMI + 0x000000e4 + Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_QMI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_AUX + 0x000000e8 + Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_AUX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + + + UART0 + 0x40070000 + + 0 + 4096 + registers + + + UART0_IRQ + 33 + + + + UARTDR + 0x00000000 + Data Register, UARTDR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] + read-only + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] + read-only + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] + read-only + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] + read-only + + + DATA + Receive (read) data character. Transmit (write) data character. + [7:0] + read-write + modify + + + + + UARTRSR + 0x00000004 + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + [3:3] + read-write + oneToClear + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + [2:2] + read-write + oneToClear + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [1:1] + read-write + oneToClear + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [0:0] + read-write + oneToClear + + + + + UARTFR + 0x00000018 + Flag Register, UARTFR + 0x00000090 + + + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] + read-only + + + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] + read-only + + + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] + read-only + + + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] + read-only + + + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + [3:3] + read-only + + + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + [2:2] + read-only + + + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + [1:1] + read-only + + + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + [0:0] + read-only + + + + + UARTILPR + 0x00000020 + IrDA Low-Power Counter Register, UARTILPR + 0x00000000 + + + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] + read-write + + + + + UARTIBRD + 0x00000024 + Integer Baud Rate Register, UARTIBRD + 0x00000000 + + + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] + read-write + + + + + UARTFBRD + 0x00000028 + Fractional Baud Rate Register, UARTFBRD + 0x00000000 + + + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write + + + + + UARTLCR_H + 0x0000002c + Line Control Register, UARTLCR_H + 0x00000000 + + + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write + + + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + + + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write + + + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write + + + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write + + + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write + + + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write + + + + + UARTCR + 0x00000030 + Control Register, UARTCR + 0x00000300 + + + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write + + + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write + + + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + [10:10] + read-write + + + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + [9:9] + read-write + + + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + [8:8] + read-write + + + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + [7:7] + read-write + + + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] + read-write + + + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] + read-write + + + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] + read-write + + + + + UARTIFLS + 0x00000034 + Interrupt FIFO Level Select Register, UARTIFLS + 0x00000012 + + + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] + read-write + + + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] + read-write + + + + + UARTIMSC + 0x00000038 + Interrupt Mask Set/Clear Register, UARTIMSC + 0x00000000 + + + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + [10:10] + read-write + + + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] + read-write + + + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] + read-write + + + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write + + + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] + read-write + + + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] + read-write + + + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] + read-write + + + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] + read-write + + + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] + read-write + + + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] + read-write + + + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] + read-write + + + + + UARTRIS + 0x0000003c + Raw Interrupt Status Register, UARTRIS + 0x00000000 + + + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + [6:6] + read-only + + + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTMIS + 0x00000040 + Masked Interrupt Status Register, UARTMIS + 0x00000000 + + + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + 0x00000044 + Interrupt Clear Register, UARTICR + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + [10:10] + read-write + oneToClear + + + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. + [9:9] + read-write + oneToClear + + + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + [8:8] + read-write + oneToClear + + + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + [7:7] + read-write + oneToClear + + + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + [6:6] + read-write + oneToClear + + + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + [5:5] + read-write + oneToClear + + + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. + [4:4] + read-write + oneToClear + + + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + [3:3] + read-write + oneToClear + + + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + [2:2] + read-write + oneToClear + + + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + [1:1] + read-write + oneToClear + + + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + [0:0] + read-write + oneToClear + + + + + UARTDMACR + 0x00000048 + DMA Control Register, UARTDMACR + 0x00000000 + + + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write + + + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + UARTPERIPHID0 + 0x00000fe0 + UARTPeriphID0 Register + 0x00000011 + + + PARTNUMBER0 + These bits read back as 0x11 + [7:0] + read-only + + + + + UARTPERIPHID1 + 0x00000fe4 + UARTPeriphID1 Register + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + UARTPERIPHID2 + 0x00000fe8 + UARTPeriphID2 Register + 0x00000034 + + + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + UARTPERIPHID3 + 0x00000fec + UARTPeriphID3 Register + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + UARTPCELLID0 + 0x00000ff0 + UARTPCellID0 Register + 0x0000000d + + + UARTPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + UARTPCELLID1 + 0x00000ff4 + UARTPCellID1 Register + 0x000000f0 + + + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + UARTPCELLID2 + 0x00000ff8 + UARTPCellID2 Register + 0x00000005 + + + UARTPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + UARTPCELLID3 + 0x00000ffc + UARTPCellID3 Register + 0x000000b1 + + + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + UART1 + 0x40078000 + + UART1_IRQ + 34 + + + + ROSC + 0x400e8000 + + 0 + 40 + registers + + + + CTRL + 0x00000000 + Ring Oscillator control + 0x00000aa0 + + + ENABLE + On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 2 to 7 + HIGH uses stages 4 to 7 + TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + + + + + FREQA + 0x00000004 + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS3 + Stage 3 drive strength + [14:12] + read-write + + + DS2 + Stage 2 drive strength + [10:8] + read-write + + + DS1_RANDOM + Randomises the stage 1 drive strength + [7:7] + read-write + + + DS1 + Stage 1 drive strength + [6:4] + read-write + + + DS0_RANDOM + Randomises the stage 0 drive strength + [3:3] + read-write + + + DS0 + Stage 0 drive strength + [2:0] + read-write + + + + + FREQB + 0x00000008 + For a detailed description see freqa register + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write + + + + + RANDOM + 0x0000000c + Loads a value to the LFSR randomiser + 0x3f04b16d + + + SEED + [31:0] + read-write + + + + + DORMANT + 0x00000010 + Ring Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + DIV + 0x00000014 + Controls the output divider + 0x00000000 + + + DIV + set to 0xaa00 + div where + div = 0 divides by 128 + div = 1-127 divides by div + any other value sets div=128 + this register resets to div=32 + [15:0] + read-write + + + PASS + 43520 + + + + + + + PHASE + 0x00000018 + Controls the phase shifted output + 0x00000008 + + + PASSWD + set to 0xaa + any other value enables the output with shift=0 + [11:4] + read-write + + + ENABLE + enable the phase-shifted output + this can be changed on-the-fly + [3:3] + read-write + + + FLIP + invert the phase-shifted output + this is ignored when div=1 + [2:2] + read-write + + + SHIFT + phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1 + [1:0] + read-write + + + + + STATUS + 0x0000001c + Ring Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + [24:24] + read-write + oneToClear + + + DIV_RUNNING + post-divider is running + this resets to 0 but transitions to 1 during chip startup + [16:16] + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup + [12:12] + read-only + + + + + RANDOMBIT + 0x00000020 + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x00000001 + + + RANDOMBIT + [0:0] + read-only + + + + + COUNT + 0x00000024 + A down counter running at the ROSC frequency which counts to zero and stops. + To start the counter write a non-zero value. + Can be used for short software pauses when setting up time sensitive hardware. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + POWMAN + Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use + 0x40100000 + + 0 + 240 + registers + + + POWMAN_IRQ_POW + 44 + + + POWMAN_IRQ_TIMER + 45 + + + + BADPASSWD + 0x00000000 + Indicates a bad password has been used + 0x00000000 + + + BADPASSWD + [0:0] + read-write + oneToClear + + + + + VREG_CTRL + 0x00000004 + Voltage Regulator Control + 0x00008050 + + + RST_N + returns the regulator to its startup settings + 0 - reset + 1 - not reset (default) + [15:15] + read-write + + + UNLOCK + unlocks the VREG control interface after power up + 0 - Locked (default) + 1 - Unlocked + It cannot be relocked when it is unlocked. + [13:13] + read-write + + + ISOLATE + isolates the VREG control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + DISABLE_VOLTAGE_LIMIT + 0=not disabled, 1=enabled + [8:8] + read-write + + + HT_TH + high temperature protection threshold + regulator power transistors are disabled when junction temperature exceeds threshold + 000 - 100C + 001 - 105C + 010 - 110C + 011 - 115C + 100 - 120C + 101 - 125C + 110 - 135C + 111 - 150C + [6:4] + read-write + + + + + VREG_STS + 0x00000008 + Voltage Regulator Status + 0x00000000 + + + VOUT_OK + output regulation status + 0=not in regulation, 1=in regulation + [4:4] + read-only + + + STARTUP + startup status + 0=startup complete, 1=starting up + [0:0] + read-only + + + + + VREG + 0x0000000c + Voltage Regulator Settings + 0x000000b0 + + + UPDATE_IN_PROGRESS + regulator state is being updated + writes to the vreg register will be ignored when this field is set + [15:15] + read-only + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_ENTRY + 0x00000010 + Voltage Regulator Low Power Entry Settings + 0x000000b4 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_EXIT + 0x00000014 + Voltage Regulator Low Power Exit Settings + 0x000000b0 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + BOD_CTRL + 0x00000018 + Brown-out Detection Control + 0x00000000 + + + ISOLATE + isolates the brown-out detection control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + + + BOD + 0x0000001c + Brown-out Detection Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_ENTRY + 0x00000020 + Brown-out Detection Low Power Entry Settings + 0x000000b0 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_EXIT + 0x00000024 + Brown-out Detection Low Power Exit Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + LPOSC + 0x00000028 + Low power oscillator control register. + 0x00000203 + + + TRIM + Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% + [9:4] + read-write + + + MODE + This feature has been removed + [1:0] + read-write + + + + + CHIP_RESET + 0x0000002c + Chip reset control and status + 0x00000000 + + + HAD_WATCHDOG_RESET_RSM + Last reset was a watchdog timeout which was configured to reset the power-on state machine + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [28:28] + read-only + + + HAD_HZD_SYS_RESET_REQ + Last reset was a system reset from the hazard debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [27:27] + read-only + + + HAD_GLITCH_DETECT + Last reset was due to a power supply glitch + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [26:26] + read-only + + + HAD_SWCORE_PD + Last reset was a switched core powerdown + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [25:25] + read-only + + + HAD_WATCHDOG_RESET_SWCORE + Last reset was a watchdog timeout which was configured to reset the switched-core + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [24:24] + read-only + + + HAD_WATCHDOG_RESET_POWMAN + Last reset was a watchdog timeout which was configured to reset the power manager + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [23:23] + read-only + + + HAD_WATCHDOG_RESET_POWMAN_ASYNC + Last reset was a watchdog timeout which was configured to reset the power manager asynchronously + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [22:22] + read-only + + + HAD_RESCUE + Last reset was a rescue reset from the debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no, it sets this flag + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [21:21] + read-only + + + HAD_DP_RESET_REQ + Last reset was an reset request from the arm debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [19:19] + read-only + + + HAD_RUN_LOW + Last reset was from the RUN pin + This resets: + double_tap flag no + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [18:18] + read-only + + + HAD_BOR + Last reset was from the brown-out detection block + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [17:17] + read-only + + + HAD_POR + Last reset was from the power-on reset + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [16:16] + read-only + + + RESCUE_FLAG + This is set by a rescue reset from the RP-AP. + Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. + The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. + [4:4] + read-write + oneToClear + + + DOUBLE_TAP + This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. + [0:0] + read-write + + + + + WDSEL + 0x00000030 + Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). + Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. + 0x00000000 + + + RESET_RSM + If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a reset from a glitch detector + [12:12] + read-write + + + RESET_SWCORE + If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain + [8:8] + read-write + + + RESET_POWMAN + If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain + and run the full power-on state machine (PSM) sequence + This relies on clk_ref running. Use reset_powman_async if that may not be true + [4:4] + read-write + + + RESET_POWMAN_ASYNC + If set to 1, a watchdog reset will restore powman defaults, reset the timer, + reset the switched core domain and run the full power-on state machine (PSM) sequence + This does not rely on clk_ref running + [0:0] + read-write + + + + + SEQ_CFG + 0x00000034 + For configuration of the power sequencer + Writes are ignored while POWMAN_STATE_CHANGING=1 + 0x001011f0 + + + USING_FAST_POWCK + 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) + 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) + [20:20] + read-only + + + USING_BOD_LP + Indicates the brown-out detector (BOD) mode + 0 = BOD high power mode which is the default + 1 = BOD low power mode + [17:17] + read-only + + + USING_VREG_LP + Indicates the voltage regulator (VREG) mode + 0 = VREG high power mode which is the default + 1 = VREG low power mode + [16:16] + read-only + + + USE_FAST_POWCK + selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. + 0 always run the POWMAN clock from the slow clock (lposc) + 1 run the POWMAN clock from the fast clock when available + This setting takes effect when a power up sequence is next run + [12:12] + read-write + + + RUN_LPOSC_IN_LP + Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer + This setting takes effect when the swcore is next powered down + [8:8] + read-write + + + USE_BOD_HP + Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [7:7] + read-write + + + USE_BOD_LP + Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [6:6] + read-write + + + USE_VREG_HP + Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [5:5] + read-write + + + USE_VREG_LP + Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [4:4] + read-write + + + HW_PWRUP_SRAM0 + Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [1:1] + read-write + + + HW_PWRUP_SRAM1 + Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [0:0] + read-write + + + + + STATE + 0x00000038 + This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. + To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states + defined in the datasheet: + bit 3 = SWCORE + bit 2 = XIP cache + bit 1 = SRAM0 + bit 0 = SRAM1 + 0 = powered up + 1 = powered down + When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. + 0x0000000f + + + CHANGING + [13:13] + read-only + + + WAITING + [12:12] + read-only + + + BAD_HW_REQ + Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) + [11:11] + read-only + + + BAD_SW_REQ + Bad software initiated state request. No action taken. + [10:10] + read-only + + + PWRUP_WHILE_WAITING + Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. + [9:9] + read-write + oneToClear + + + REQ_IGNORED + [8:8] + read-write + oneToClear + + + REQ + [7:4] + read-write + + + CURRENT + [3:0] + read-only + + + + + POW_FASTDIV + 0x0000003c + 0x00000040 + + + POW_FASTDIV + divides the POWMAN clock to provide a tick for the delay module and state machines + when clk_pow is running from the slow clock it is not divided + when clk_pow is running from the fast clock it is divided by tick_div + [10:0] + read-write + + + + + POW_DELAY + 0x00000040 + power state machine delays + 0x00002011 + + + SRAM_STEP + timing between the sram0 and sram1 power state machine steps + measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit + [15:8] + read-write + + + XIP_STEP + timing between the xip power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [7:4] + read-write + + + SWCORE_STEP + timing between the swcore power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [3:0] + read-write + + + + + EXT_CTRL0 + 0x00000044 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_CTRL1 + 0x00000048 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_TIME_REF + 0x0000004c + Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. + 0x00000000 + + + DRIVE_LPCK + Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 + [4:4] + read-write + + + SOURCE_SEL + 0 -> gpio12 + 1 -> gpio20 + 2 -> gpio14 + 3 -> gpio22 + [1:0] + read-write + + + + + LPOSC_FREQ_KHZ_INT + 0x00000050 + Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. + 0x00000020 + + + LPOSC_FREQ_KHZ_INT + Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [5:0] + read-write + + + + + LPOSC_FREQ_KHZ_FRAC + 0x00000054 + Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. + 0x0000c49c + + + LPOSC_FREQ_KHZ_FRAC + Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_INT + 0x00000058 + Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. + 0x00002ee0 + + + XOSC_FREQ_KHZ_INT + Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_FRAC + 0x0000005c + Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. + 0x00000000 + + + XOSC_FREQ_KHZ_FRAC + Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + SET_TIME_63TO48 + 0x00000060 + 0x00000000 + + + SET_TIME_63TO48 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_47TO32 + 0x00000064 + 0x00000000 + + + SET_TIME_47TO32 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_31TO16 + 0x00000068 + 0x00000000 + + + SET_TIME_31TO16 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_15TO0 + 0x0000006c + 0x00000000 + + + SET_TIME_15TO0 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + READ_TIME_UPPER + 0x00000070 + 0x00000000 + + + READ_TIME_UPPER + For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. + [31:0] + read-only + + + + + READ_TIME_LOWER + 0x00000074 + 0x00000000 + + + READ_TIME_LOWER + For reading bits 31:0 of the timer. + [31:0] + read-only + + + + + ALARM_TIME_63TO48 + 0x00000078 + 0x00000000 + + + ALARM_TIME_63TO48 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_47TO32 + 0x0000007c + 0x00000000 + + + ALARM_TIME_47TO32 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_31TO16 + 0x00000080 + 0x00000000 + + + ALARM_TIME_31TO16 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_15TO0 + 0x00000084 + 0x00000000 + + + ALARM_TIME_15TO0 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + TIMER + 0x00000088 + 0x00000000 + + + USING_GPIO_1HZ + Timer is synchronised to a 1hz gpio source + [19:19] + read-only + + + USING_GPIO_1KHZ + Timer is running from a 1khz gpio source + [18:18] + read-only + + + USING_LPOSC + Timer is running from lposc + [17:17] + read-only + + + USING_XOSC + Timer is running from xosc + [16:16] + read-only + + + USE_GPIO_1HZ + Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. + [13:13] + read-write + + + USE_GPIO_1KHZ + switch to gpio as the source of the 1kHz timer tick + [10:10] + write-only + + + USE_XOSC + switch to xosc as the source of the 1kHz timer tick + [9:9] + write-only + + + USE_LPOSC + Switch to lposc as the source of the 1kHz timer tick + [8:8] + write-only + + + ALARM + Alarm has fired. Write to 1 to clear the alarm. + [6:6] + read-write + oneToClear + + + PWRUP_ON_ALARM + Alarm wakes the chip from low power mode + [5:5] + read-write + + + ALARM_ENAB + Enables the alarm. The alarm must be disabled while writing the alarm time. + [4:4] + read-write + + + CLEAR + Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. + [2:2] + write-only + + + RUN + Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. + + Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. + + Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 + [1:1] + read-write + + + NONSEC_WRITE + Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. + [0:0] + read-write + + + + + PWRUP0 + 0x0000008c + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP1 + 0x00000090 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP2 + 0x00000094 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP3 + 0x00000098 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + CURRENT_PWRUP_REQ + 0x0000009c + Indicates current powerup request state + pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + CURRENT_PWRUP_REQ + [6:0] + read-only + + + + + LAST_SWCORE_PWRUP + 0x000000a0 + Indicates which pwrup source triggered the last switched-core power up + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + LAST_SWCORE_PWRUP + [6:0] + read-only + + + + + DBG_PWRCFG + 0x000000a4 + 0x00000000 + + + IGNORE + Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req + [0:0] + read-write + + + + + BOOTDIS + 0x000000a8 + Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the OTP BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. + [1:1] + read-write + + + NOW + When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + DBGCONFIG + 0x000000ac + 0x00000000 + + + DP_INSTID + Configure DP instance ID for SWD multidrop selection. + Recommend that this is NOT changed until you require debug access in multi-chip environment + [3:0] + read-write + + + + + SCRATCH0 + 0x000000b0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x000000b4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x000000b8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x000000bc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x000000c0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x000000c4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x000000c8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x000000cc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + BOOT0 + 0x000000d0 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT0 + [31:0] + read-write + + + + + BOOT1 + 0x000000d4 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT1 + [31:0] + read-write + + + + + BOOT2 + 0x000000d8 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT2 + [31:0] + read-write + + + + + BOOT3 + 0x000000dc + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT3 + [31:0] + read-write + + + + + INTR + 0x000000e0 + Raw Interrupts + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-write + oneToClear + + + + + INTE + 0x000000e4 + Interrupt Enable + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTF + 0x000000e8 + Interrupt Force + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTS + 0x000000ec + Interrupt status after masking & forcing + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-only + + + + + + + WATCHDOG + 0x400d8000 + + 0 + 44 + registers + + + + CTRL + 0x00000000 + Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + 0x07000000 + + + TRIGGER + Trigger a watchdog reset + [31:31] + write-only + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] + read-write + + + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] + read-write + + + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write + + + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write + + + TIME + Indicates the time in usec before a watchdog reset will be triggered + [23:0] + read-only + + + + + LOAD + 0x00000004 + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. + 0x00000000 + + + LOAD + [23:0] + write-only + + + + + REASON + 0x00000008 + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + + Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. + 0x00000000 + + + FORCE + [1:1] + read-only + + + TIMER + [0:0] + read-only + + + + + SCRATCH0 + 0x0000000c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x00000010 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x00000014 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x00000018 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x0000001c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x00000020 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x00000024 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x00000028 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + + + DMA + DMA with separate read and write masters + 0x50000000 + + 0 + 3016 + registers + + + DMA_IRQ_0 + 10 + + + DMA_IRQ_1 + 11 + + + DMA_IRQ_2 + 12 + + + DMA_IRQ_3 + 13 + + + + CH0_READ_ADDR + 0x00000000 + DMA Channel 0 Read Address pointer + 0x00000000 + + + CH0_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH0_WRITE_ADDR + 0x00000004 + DMA Channel 0 Write Address pointer + 0x00000000 + + + CH0_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH0_TRANS_COUNT + 0x00000008 + DMA Channel 0 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH0_CTRL_TRIG + 0x0000000c + DMA Channel 0 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH0_AL1_CTRL + 0x00000010 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL1_CTRL + [31:0] + read-write + + + + + CH0_AL1_READ_ADDR + 0x00000014 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL1_READ_ADDR + [31:0] + read-write + + + + + CH0_AL1_WRITE_ADDR + 0x00000018 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL1_TRANS_COUNT_TRIG + 0x0000001c + Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH0_AL2_CTRL + 0x00000020 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL2_CTRL + [31:0] + read-write + + + + + CH0_AL2_TRANS_COUNT + 0x00000024 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL2_READ_ADDR + 0x00000028 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL2_READ_ADDR + [31:0] + read-write + + + + + CH0_AL2_WRITE_ADDR_TRIG + 0x0000002c + Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH0_AL3_CTRL + 0x00000030 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL3_CTRL + [31:0] + read-write + + + + + CH0_AL3_WRITE_ADDR + 0x00000034 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL3_TRANS_COUNT + 0x00000038 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL3_READ_ADDR_TRIG + 0x0000003c + Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH1_READ_ADDR + 0x00000040 + DMA Channel 1 Read Address pointer + 0x00000000 + + + CH1_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH1_WRITE_ADDR + 0x00000044 + DMA Channel 1 Write Address pointer + 0x00000000 + + + CH1_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH1_TRANS_COUNT + 0x00000048 + DMA Channel 1 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH1_CTRL_TRIG + 0x0000004c + DMA Channel 1 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH1_AL1_CTRL + 0x00000050 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL1_CTRL + [31:0] + read-write + + + + + CH1_AL1_READ_ADDR + 0x00000054 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL1_READ_ADDR + [31:0] + read-write + + + + + CH1_AL1_WRITE_ADDR + 0x00000058 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL1_TRANS_COUNT_TRIG + 0x0000005c + Alias for channel 1 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH1_AL2_CTRL + 0x00000060 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL2_CTRL + [31:0] + read-write + + + + + CH1_AL2_TRANS_COUNT + 0x00000064 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL2_READ_ADDR + 0x00000068 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL2_READ_ADDR + [31:0] + read-write + + + + + CH1_AL2_WRITE_ADDR_TRIG + 0x0000006c + Alias for channel 1 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH1_AL3_CTRL + 0x00000070 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL3_CTRL + [31:0] + read-write + + + + + CH1_AL3_WRITE_ADDR + 0x00000074 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL3_TRANS_COUNT + 0x00000078 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL3_READ_ADDR_TRIG + 0x0000007c + Alias for channel 1 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH2_READ_ADDR + 0x00000080 + DMA Channel 2 Read Address pointer + 0x00000000 + + + CH2_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH2_WRITE_ADDR + 0x00000084 + DMA Channel 2 Write Address pointer + 0x00000000 + + + CH2_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH2_TRANS_COUNT + 0x00000088 + DMA Channel 2 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH2_CTRL_TRIG + 0x0000008c + DMA Channel 2 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH2_AL1_CTRL + 0x00000090 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL1_CTRL + [31:0] + read-write + + + + + CH2_AL1_READ_ADDR + 0x00000094 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL1_READ_ADDR + [31:0] + read-write + + + + + CH2_AL1_WRITE_ADDR + 0x00000098 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL1_TRANS_COUNT_TRIG + 0x0000009c + Alias for channel 2 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH2_AL2_CTRL + 0x000000a0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL2_CTRL + [31:0] + read-write + + + + + CH2_AL2_TRANS_COUNT + 0x000000a4 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL2_READ_ADDR + 0x000000a8 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL2_READ_ADDR + [31:0] + read-write + + + + + CH2_AL2_WRITE_ADDR_TRIG + 0x000000ac + Alias for channel 2 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH2_AL3_CTRL + 0x000000b0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL3_CTRL + [31:0] + read-write + + + + + CH2_AL3_WRITE_ADDR + 0x000000b4 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL3_TRANS_COUNT + 0x000000b8 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL3_READ_ADDR_TRIG + 0x000000bc + Alias for channel 2 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH3_READ_ADDR + 0x000000c0 + DMA Channel 3 Read Address pointer + 0x00000000 + + + CH3_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH3_WRITE_ADDR + 0x000000c4 + DMA Channel 3 Write Address pointer + 0x00000000 + + + CH3_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH3_TRANS_COUNT + 0x000000c8 + DMA Channel 3 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH3_CTRL_TRIG + 0x000000cc + DMA Channel 3 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH3_AL1_CTRL + 0x000000d0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL1_CTRL + [31:0] + read-write + + + + + CH3_AL1_READ_ADDR + 0x000000d4 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL1_READ_ADDR + [31:0] + read-write + + + + + CH3_AL1_WRITE_ADDR + 0x000000d8 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL1_TRANS_COUNT_TRIG + 0x000000dc + Alias for channel 3 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH3_AL2_CTRL + 0x000000e0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL2_CTRL + [31:0] + read-write + + + + + CH3_AL2_TRANS_COUNT + 0x000000e4 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL2_READ_ADDR + 0x000000e8 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL2_READ_ADDR + [31:0] + read-write + + + + + CH3_AL2_WRITE_ADDR_TRIG + 0x000000ec + Alias for channel 3 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH3_AL3_CTRL + 0x000000f0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL3_CTRL + [31:0] + read-write + + + + + CH3_AL3_WRITE_ADDR + 0x000000f4 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL3_TRANS_COUNT + 0x000000f8 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL3_READ_ADDR_TRIG + 0x000000fc + Alias for channel 3 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH4_READ_ADDR + 0x00000100 + DMA Channel 4 Read Address pointer + 0x00000000 + + + CH4_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH4_WRITE_ADDR + 0x00000104 + DMA Channel 4 Write Address pointer + 0x00000000 + + + CH4_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH4_TRANS_COUNT + 0x00000108 + DMA Channel 4 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH4_CTRL_TRIG + 0x0000010c + DMA Channel 4 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH4_AL1_CTRL + 0x00000110 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL1_CTRL + [31:0] + read-write + + + + + CH4_AL1_READ_ADDR + 0x00000114 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL1_READ_ADDR + [31:0] + read-write + + + + + CH4_AL1_WRITE_ADDR + 0x00000118 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL1_TRANS_COUNT_TRIG + 0x0000011c + Alias for channel 4 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH4_AL2_CTRL + 0x00000120 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL2_CTRL + [31:0] + read-write + + + + + CH4_AL2_TRANS_COUNT + 0x00000124 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL2_READ_ADDR + 0x00000128 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL2_READ_ADDR + [31:0] + read-write + + + + + CH4_AL2_WRITE_ADDR_TRIG + 0x0000012c + Alias for channel 4 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH4_AL3_CTRL + 0x00000130 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL3_CTRL + [31:0] + read-write + + + + + CH4_AL3_WRITE_ADDR + 0x00000134 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL3_TRANS_COUNT + 0x00000138 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL3_READ_ADDR_TRIG + 0x0000013c + Alias for channel 4 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH5_READ_ADDR + 0x00000140 + DMA Channel 5 Read Address pointer + 0x00000000 + + + CH5_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH5_WRITE_ADDR + 0x00000144 + DMA Channel 5 Write Address pointer + 0x00000000 + + + CH5_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH5_TRANS_COUNT + 0x00000148 + DMA Channel 5 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH5_CTRL_TRIG + 0x0000014c + DMA Channel 5 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH5_AL1_CTRL + 0x00000150 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL1_CTRL + [31:0] + read-write + + + + + CH5_AL1_READ_ADDR + 0x00000154 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL1_READ_ADDR + [31:0] + read-write + + + + + CH5_AL1_WRITE_ADDR + 0x00000158 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL1_TRANS_COUNT_TRIG + 0x0000015c + Alias for channel 5 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH5_AL2_CTRL + 0x00000160 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL2_CTRL + [31:0] + read-write + + + + + CH5_AL2_TRANS_COUNT + 0x00000164 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL2_READ_ADDR + 0x00000168 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL2_READ_ADDR + [31:0] + read-write + + + + + CH5_AL2_WRITE_ADDR_TRIG + 0x0000016c + Alias for channel 5 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH5_AL3_CTRL + 0x00000170 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL3_CTRL + [31:0] + read-write + + + + + CH5_AL3_WRITE_ADDR + 0x00000174 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL3_TRANS_COUNT + 0x00000178 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL3_READ_ADDR_TRIG + 0x0000017c + Alias for channel 5 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH6_READ_ADDR + 0x00000180 + DMA Channel 6 Read Address pointer + 0x00000000 + + + CH6_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH6_WRITE_ADDR + 0x00000184 + DMA Channel 6 Write Address pointer + 0x00000000 + + + CH6_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH6_TRANS_COUNT + 0x00000188 + DMA Channel 6 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH6_CTRL_TRIG + 0x0000018c + DMA Channel 6 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH6_AL1_CTRL + 0x00000190 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL1_CTRL + [31:0] + read-write + + + + + CH6_AL1_READ_ADDR + 0x00000194 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL1_READ_ADDR + [31:0] + read-write + + + + + CH6_AL1_WRITE_ADDR + 0x00000198 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL1_TRANS_COUNT_TRIG + 0x0000019c + Alias for channel 6 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH6_AL2_CTRL + 0x000001a0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL2_CTRL + [31:0] + read-write + + + + + CH6_AL2_TRANS_COUNT + 0x000001a4 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL2_READ_ADDR + 0x000001a8 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL2_READ_ADDR + [31:0] + read-write + + + + + CH6_AL2_WRITE_ADDR_TRIG + 0x000001ac + Alias for channel 6 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH6_AL3_CTRL + 0x000001b0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL3_CTRL + [31:0] + read-write + + + + + CH6_AL3_WRITE_ADDR + 0x000001b4 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL3_TRANS_COUNT + 0x000001b8 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL3_READ_ADDR_TRIG + 0x000001bc + Alias for channel 6 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH7_READ_ADDR + 0x000001c0 + DMA Channel 7 Read Address pointer + 0x00000000 + + + CH7_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH7_WRITE_ADDR + 0x000001c4 + DMA Channel 7 Write Address pointer + 0x00000000 + + + CH7_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH7_TRANS_COUNT + 0x000001c8 + DMA Channel 7 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH7_CTRL_TRIG + 0x000001cc + DMA Channel 7 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH7_AL1_CTRL + 0x000001d0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL1_CTRL + [31:0] + read-write + + + + + CH7_AL1_READ_ADDR + 0x000001d4 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL1_READ_ADDR + [31:0] + read-write + + + + + CH7_AL1_WRITE_ADDR + 0x000001d8 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL1_TRANS_COUNT_TRIG + 0x000001dc + Alias for channel 7 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH7_AL2_CTRL + 0x000001e0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL2_CTRL + [31:0] + read-write + + + + + CH7_AL2_TRANS_COUNT + 0x000001e4 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL2_READ_ADDR + 0x000001e8 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL2_READ_ADDR + [31:0] + read-write + + + + + CH7_AL2_WRITE_ADDR_TRIG + 0x000001ec + Alias for channel 7 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH7_AL3_CTRL + 0x000001f0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL3_CTRL + [31:0] + read-write + + + + + CH7_AL3_WRITE_ADDR + 0x000001f4 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL3_TRANS_COUNT + 0x000001f8 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL3_READ_ADDR_TRIG + 0x000001fc + Alias for channel 7 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH8_READ_ADDR + 0x00000200 + DMA Channel 8 Read Address pointer + 0x00000000 + + + CH8_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH8_WRITE_ADDR + 0x00000204 + DMA Channel 8 Write Address pointer + 0x00000000 + + + CH8_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH8_TRANS_COUNT + 0x00000208 + DMA Channel 8 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH8_CTRL_TRIG + 0x0000020c + DMA Channel 8 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH8_AL1_CTRL + 0x00000210 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL1_CTRL + [31:0] + read-write + + + + + CH8_AL1_READ_ADDR + 0x00000214 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL1_READ_ADDR + [31:0] + read-write + + + + + CH8_AL1_WRITE_ADDR + 0x00000218 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL1_TRANS_COUNT_TRIG + 0x0000021c + Alias for channel 8 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH8_AL2_CTRL + 0x00000220 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL2_CTRL + [31:0] + read-write + + + + + CH8_AL2_TRANS_COUNT + 0x00000224 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL2_READ_ADDR + 0x00000228 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL2_READ_ADDR + [31:0] + read-write + + + + + CH8_AL2_WRITE_ADDR_TRIG + 0x0000022c + Alias for channel 8 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH8_AL3_CTRL + 0x00000230 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL3_CTRL + [31:0] + read-write + + + + + CH8_AL3_WRITE_ADDR + 0x00000234 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL3_TRANS_COUNT + 0x00000238 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL3_READ_ADDR_TRIG + 0x0000023c + Alias for channel 8 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH9_READ_ADDR + 0x00000240 + DMA Channel 9 Read Address pointer + 0x00000000 + + + CH9_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH9_WRITE_ADDR + 0x00000244 + DMA Channel 9 Write Address pointer + 0x00000000 + + + CH9_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH9_TRANS_COUNT + 0x00000248 + DMA Channel 9 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH9_CTRL_TRIG + 0x0000024c + DMA Channel 9 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH9_AL1_CTRL + 0x00000250 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL1_CTRL + [31:0] + read-write + + + + + CH9_AL1_READ_ADDR + 0x00000254 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL1_READ_ADDR + [31:0] + read-write + + + + + CH9_AL1_WRITE_ADDR + 0x00000258 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL1_TRANS_COUNT_TRIG + 0x0000025c + Alias for channel 9 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH9_AL2_CTRL + 0x00000260 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL2_CTRL + [31:0] + read-write + + + + + CH9_AL2_TRANS_COUNT + 0x00000264 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL2_READ_ADDR + 0x00000268 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL2_READ_ADDR + [31:0] + read-write + + + + + CH9_AL2_WRITE_ADDR_TRIG + 0x0000026c + Alias for channel 9 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH9_AL3_CTRL + 0x00000270 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL3_CTRL + [31:0] + read-write + + + + + CH9_AL3_WRITE_ADDR + 0x00000274 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL3_TRANS_COUNT + 0x00000278 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL3_READ_ADDR_TRIG + 0x0000027c + Alias for channel 9 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH10_READ_ADDR + 0x00000280 + DMA Channel 10 Read Address pointer + 0x00000000 + + + CH10_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH10_WRITE_ADDR + 0x00000284 + DMA Channel 10 Write Address pointer + 0x00000000 + + + CH10_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH10_TRANS_COUNT + 0x00000288 + DMA Channel 10 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH10_CTRL_TRIG + 0x0000028c + DMA Channel 10 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH10_AL1_CTRL + 0x00000290 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL1_CTRL + [31:0] + read-write + + + + + CH10_AL1_READ_ADDR + 0x00000294 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL1_READ_ADDR + [31:0] + read-write + + + + + CH10_AL1_WRITE_ADDR + 0x00000298 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL1_TRANS_COUNT_TRIG + 0x0000029c + Alias for channel 10 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH10_AL2_CTRL + 0x000002a0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL2_CTRL + [31:0] + read-write + + + + + CH10_AL2_TRANS_COUNT + 0x000002a4 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL2_READ_ADDR + 0x000002a8 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL2_READ_ADDR + [31:0] + read-write + + + + + CH10_AL2_WRITE_ADDR_TRIG + 0x000002ac + Alias for channel 10 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH10_AL3_CTRL + 0x000002b0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL3_CTRL + [31:0] + read-write + + + + + CH10_AL3_WRITE_ADDR + 0x000002b4 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL3_TRANS_COUNT + 0x000002b8 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL3_READ_ADDR_TRIG + 0x000002bc + Alias for channel 10 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH11_READ_ADDR + 0x000002c0 + DMA Channel 11 Read Address pointer + 0x00000000 + + + CH11_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH11_WRITE_ADDR + 0x000002c4 + DMA Channel 11 Write Address pointer + 0x00000000 + + + CH11_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH11_TRANS_COUNT + 0x000002c8 + DMA Channel 11 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH11_CTRL_TRIG + 0x000002cc + DMA Channel 11 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH11_AL1_CTRL + 0x000002d0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL1_CTRL + [31:0] + read-write + + + + + CH11_AL1_READ_ADDR + 0x000002d4 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL1_READ_ADDR + [31:0] + read-write + + + + + CH11_AL1_WRITE_ADDR + 0x000002d8 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL1_TRANS_COUNT_TRIG + 0x000002dc + Alias for channel 11 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH11_AL2_CTRL + 0x000002e0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL2_CTRL + [31:0] + read-write + + + + + CH11_AL2_TRANS_COUNT + 0x000002e4 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL2_READ_ADDR + 0x000002e8 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL2_READ_ADDR + [31:0] + read-write + + + + + CH11_AL2_WRITE_ADDR_TRIG + 0x000002ec + Alias for channel 11 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH11_AL3_CTRL + 0x000002f0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL3_CTRL + [31:0] + read-write + + + + + CH11_AL3_WRITE_ADDR + 0x000002f4 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL3_TRANS_COUNT + 0x000002f8 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL3_READ_ADDR_TRIG + 0x000002fc + Alias for channel 11 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH12_READ_ADDR + 0x00000300 + DMA Channel 12 Read Address pointer + 0x00000000 + + + CH12_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH12_WRITE_ADDR + 0x00000304 + DMA Channel 12 Write Address pointer + 0x00000000 + + + CH12_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH12_TRANS_COUNT + 0x00000308 + DMA Channel 12 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH12_CTRL_TRIG + 0x0000030c + DMA Channel 12 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH12_AL1_CTRL + 0x00000310 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL1_CTRL + [31:0] + read-write + + + + + CH12_AL1_READ_ADDR + 0x00000314 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL1_READ_ADDR + [31:0] + read-write + + + + + CH12_AL1_WRITE_ADDR + 0x00000318 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL1_TRANS_COUNT_TRIG + 0x0000031c + Alias for channel 12 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH12_AL2_CTRL + 0x00000320 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL2_CTRL + [31:0] + read-write + + + + + CH12_AL2_TRANS_COUNT + 0x00000324 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL2_READ_ADDR + 0x00000328 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL2_READ_ADDR + [31:0] + read-write + + + + + CH12_AL2_WRITE_ADDR_TRIG + 0x0000032c + Alias for channel 12 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH12_AL3_CTRL + 0x00000330 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL3_CTRL + [31:0] + read-write + + + + + CH12_AL3_WRITE_ADDR + 0x00000334 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL3_TRANS_COUNT + 0x00000338 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL3_READ_ADDR_TRIG + 0x0000033c + Alias for channel 12 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH13_READ_ADDR + 0x00000340 + DMA Channel 13 Read Address pointer + 0x00000000 + + + CH13_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH13_WRITE_ADDR + 0x00000344 + DMA Channel 13 Write Address pointer + 0x00000000 + + + CH13_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH13_TRANS_COUNT + 0x00000348 + DMA Channel 13 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH13_CTRL_TRIG + 0x0000034c + DMA Channel 13 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH13_AL1_CTRL + 0x00000350 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL1_CTRL + [31:0] + read-write + + + + + CH13_AL1_READ_ADDR + 0x00000354 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL1_READ_ADDR + [31:0] + read-write + + + + + CH13_AL1_WRITE_ADDR + 0x00000358 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL1_TRANS_COUNT_TRIG + 0x0000035c + Alias for channel 13 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH13_AL2_CTRL + 0x00000360 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL2_CTRL + [31:0] + read-write + + + + + CH13_AL2_TRANS_COUNT + 0x00000364 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL2_READ_ADDR + 0x00000368 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL2_READ_ADDR + [31:0] + read-write + + + + + CH13_AL2_WRITE_ADDR_TRIG + 0x0000036c + Alias for channel 13 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH13_AL3_CTRL + 0x00000370 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL3_CTRL + [31:0] + read-write + + + + + CH13_AL3_WRITE_ADDR + 0x00000374 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL3_TRANS_COUNT + 0x00000378 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL3_READ_ADDR_TRIG + 0x0000037c + Alias for channel 13 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH14_READ_ADDR + 0x00000380 + DMA Channel 14 Read Address pointer + 0x00000000 + + + CH14_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH14_WRITE_ADDR + 0x00000384 + DMA Channel 14 Write Address pointer + 0x00000000 + + + CH14_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH14_TRANS_COUNT + 0x00000388 + DMA Channel 14 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH14_CTRL_TRIG + 0x0000038c + DMA Channel 14 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH14_AL1_CTRL + 0x00000390 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL1_CTRL + [31:0] + read-write + + + + + CH14_AL1_READ_ADDR + 0x00000394 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL1_READ_ADDR + [31:0] + read-write + + + + + CH14_AL1_WRITE_ADDR + 0x00000398 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL1_TRANS_COUNT_TRIG + 0x0000039c + Alias for channel 14 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH14_AL2_CTRL + 0x000003a0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL2_CTRL + [31:0] + read-write + + + + + CH14_AL2_TRANS_COUNT + 0x000003a4 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL2_READ_ADDR + 0x000003a8 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL2_READ_ADDR + [31:0] + read-write + + + + + CH14_AL2_WRITE_ADDR_TRIG + 0x000003ac + Alias for channel 14 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH14_AL3_CTRL + 0x000003b0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL3_CTRL + [31:0] + read-write + + + + + CH14_AL3_WRITE_ADDR + 0x000003b4 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL3_TRANS_COUNT + 0x000003b8 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL3_READ_ADDR_TRIG + 0x000003bc + Alias for channel 14 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH15_READ_ADDR + 0x000003c0 + DMA Channel 15 Read Address pointer + 0x00000000 + + + CH15_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH15_WRITE_ADDR + 0x000003c4 + DMA Channel 15 Write Address pointer + 0x00000000 + + + CH15_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH15_TRANS_COUNT + 0x000003c8 + DMA Channel 15 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH15_CTRL_TRIG + 0x000003cc + DMA Channel 15 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH15_AL1_CTRL + 0x000003d0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL1_CTRL + [31:0] + read-write + + + + + CH15_AL1_READ_ADDR + 0x000003d4 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL1_READ_ADDR + [31:0] + read-write + + + + + CH15_AL1_WRITE_ADDR + 0x000003d8 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL1_TRANS_COUNT_TRIG + 0x000003dc + Alias for channel 15 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH15_AL2_CTRL + 0x000003e0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL2_CTRL + [31:0] + read-write + + + + + CH15_AL2_TRANS_COUNT + 0x000003e4 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL2_READ_ADDR + 0x000003e8 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL2_READ_ADDR + [31:0] + read-write + + + + + CH15_AL2_WRITE_ADDR_TRIG + 0x000003ec + Alias for channel 15 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH15_AL3_CTRL + 0x000003f0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL3_CTRL + [31:0] + read-write + + + + + CH15_AL3_WRITE_ADDR + 0x000003f4 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL3_TRANS_COUNT + 0x000003f8 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL3_READ_ADDR_TRIG + 0x000003fc + Alias for channel 15 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + INTR + 0x00000400 + Interrupt Status (raw) + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE0 + 0x00000404 + Interrupt Enables for IRQ 0 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. + [15:0] + read-write + + + + + INTF0 + 0x00000408 + Force Interrupts + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + 0x0000040c + Interrupt Status for IRQ 0 + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR1 + 0x00000410 + Interrupt Status (raw) + 0x00000000 + + + INTR1 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE1 + 0x00000414 + Interrupt Enables for IRQ 1 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. + [15:0] + read-write + + + + + INTF1 + 0x00000418 + Force Interrupts + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. + [15:0] + read-write + + + + + INTS1 + 0x0000041c + Interrupt Status for IRQ 1 + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR2 + 0x00000420 + Interrupt Status (raw) + 0x00000000 + + + INTR2 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE2 + 0x00000424 + Interrupt Enables for IRQ 2 + 0x00000000 + + + INTE2 + Set bit n to pass interrupts from channel n to DMA IRQ 2. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. + [15:0] + read-write + + + + + INTF2 + 0x00000428 + Force Interrupts + 0x00000000 + + + INTF2 + Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. + [15:0] + read-write + + + + + INTS2 + 0x0000042c + Interrupt Status for IRQ 2 + 0x00000000 + + + INTS2 + Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR3 + 0x00000430 + Interrupt Status (raw) + 0x00000000 + + + INTR3 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE3 + 0x00000434 + Interrupt Enables for IRQ 3 + 0x00000000 + + + INTE3 + Set bit n to pass interrupts from channel n to DMA IRQ 3. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. + [15:0] + read-write + + + + + INTF3 + 0x00000438 + Force Interrupts + 0x00000000 + + + INTF3 + Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. + [15:0] + read-write + + + + + INTS3 + 0x0000043c + Interrupt Status for IRQ 3 + 0x00000000 + + + INTS3 + Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + TIMER0 + 0x00000440 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + 0x00000444 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + 0x00000448 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + 0x0000044c + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + 0x00000450 + Trigger one or more channels simultaneously + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + write-only + + + + + SNIFF_CTRL + 0x00000454 + Sniffer Control + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + 0 + Calculate a CRC-32 (IEEE802.3 polynomial) + + + CRC32R + 1 + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + + + CRC16 + 2 + Calculate a CRC-16-CCITT + + + CRC16R + 3 + Calculate a CRC-16-CCITT with bit reversed data + + + EVEN + 14 + XOR reduction over all data. == 1 if the total 1 population count is odd. + + + SUM + 15 + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + 0x00000458 + Data accumulator for sniff hardware + 0x00000000 + + + SNIFF_DATA + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + [31:0] + read-write + + + + + FIFO_LEVELS + 0x00000460 + Debug RAF, WAF, TDF levels + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + 0x00000464 + Abort an in-progress transfer sequence on one or more channels + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + write-only + + + + + N_CHANNELS + 0x00000468 + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + SECCFG_CH0 + 0x00000480 + Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH1 + 0x00000484 + Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH2 + 0x00000488 + Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH3 + 0x0000048c + Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH4 + 0x00000490 + Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH5 + 0x00000494 + Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH6 + 0x00000498 + Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH7 + 0x0000049c + Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH8 + 0x000004a0 + Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH9 + 0x000004a4 + Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH10 + 0x000004a8 + Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH11 + 0x000004ac + Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH12 + 0x000004b0 + Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH13 + 0x000004b4 + Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH14 + 0x000004b8 + Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH15 + 0x000004bc + Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_IRQ0 + 0x000004c0 + Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ1 + 0x000004c4 + Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ2 + 0x000004c8 + Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ3 + 0x000004cc + Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_MISC + 0x000004d0 + Miscellaneous security configuration + 0x000003ff + + + TIMER3_S + If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. + [9:9] + read-write + + + TIMER3_P + If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. + [8:8] + read-write + + + TIMER2_S + If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. + [7:7] + read-write + + + TIMER2_P + If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. + [6:6] + read-write + + + TIMER1_S + If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. + [5:5] + read-write + + + TIMER1_P + If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. + [4:4] + read-write + + + TIMER0_S + If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. + [3:3] + read-write + + + TIMER0_P + If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. + [2:2] + read-write + + + SNIFF_S + If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. + + If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. + [1:1] + read-write + + + SNIFF_P + If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. + + If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. + [0:0] + read-write + + + + + MPU_CTRL + 0x00000500 + Control register for DMA MPU. Accessible only from a Privileged context. + 0x00000000 + + + NS_HIDE_ADDR + By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. + [3:3] + read-write + + + S + Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) + [2:2] + read-write + + + P + Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) + [1:1] + read-write + + + + + MPU_BAR0 + 0x00000504 + Base address register for MPU region 0. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR0 + 0x00000508 + Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR1 + 0x0000050c + Base address register for MPU region 1. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR1 + 0x00000510 + Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR2 + 0x00000514 + Base address register for MPU region 2. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR2 + 0x00000518 + Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR3 + 0x0000051c + Base address register for MPU region 3. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR3 + 0x00000520 + Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR4 + 0x00000524 + Base address register for MPU region 4. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR4 + 0x00000528 + Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR5 + 0x0000052c + Base address register for MPU region 5. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR5 + 0x00000530 + Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR6 + 0x00000534 + Base address register for MPU region 6. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR6 + 0x00000538 + Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR7 + 0x0000053c + Base address register for MPU region 7. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR7 + 0x00000540 + Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + CH0_DBG_CTDREQ + 0x00000800 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + 0x00000804 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH0_DBG_TCR + [31:0] + read-only + + + + + CH1_DBG_CTDREQ + 0x00000840 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + 0x00000844 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH1_DBG_TCR + [31:0] + read-only + + + + + CH2_DBG_CTDREQ + 0x00000880 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + 0x00000884 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH2_DBG_TCR + [31:0] + read-only + + + + + CH3_DBG_CTDREQ + 0x000008c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + 0x000008c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH3_DBG_TCR + [31:0] + read-only + + + + + CH4_DBG_CTDREQ + 0x00000900 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + 0x00000904 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH4_DBG_TCR + [31:0] + read-only + + + + + CH5_DBG_CTDREQ + 0x00000940 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + 0x00000944 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH5_DBG_TCR + [31:0] + read-only + + + + + CH6_DBG_CTDREQ + 0x00000980 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + 0x00000984 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH6_DBG_TCR + [31:0] + read-only + + + + + CH7_DBG_CTDREQ + 0x000009c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + 0x000009c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH7_DBG_TCR + [31:0] + read-only + + + + + CH8_DBG_CTDREQ + 0x00000a00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + 0x00000a04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH8_DBG_TCR + [31:0] + read-only + + + + + CH9_DBG_CTDREQ + 0x00000a40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + 0x00000a44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH9_DBG_TCR + [31:0] + read-only + + + + + CH10_DBG_CTDREQ + 0x00000a80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + 0x00000a84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH10_DBG_TCR + [31:0] + read-only + + + + + CH11_DBG_CTDREQ + 0x00000ac0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + 0x00000ac4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH11_DBG_TCR + [31:0] + read-only + + + + + CH12_DBG_CTDREQ + 0x00000b00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH12_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH12_DBG_TCR + 0x00000b04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH12_DBG_TCR + [31:0] + read-only + + + + + CH13_DBG_CTDREQ + 0x00000b40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH13_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH13_DBG_TCR + 0x00000b44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH13_DBG_TCR + [31:0] + read-only + + + + + CH14_DBG_CTDREQ + 0x00000b80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH14_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH14_DBG_TCR + 0x00000b84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH14_DBG_TCR + [31:0] + read-only + + + + + CH15_DBG_CTDREQ + 0x00000bc0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH15_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH15_DBG_TCR + 0x00000bc4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH15_DBG_TCR + [31:0] + read-only + + + + + + + TIMER0 + Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing + 0x400b0000 + + 0 + 76 + registers + + + TIMER0_IRQ_0 + 0 + + + TIMER0_IRQ_1 + 1 + + + TIMER0_IRQ_2 + 2 + + + TIMER0_IRQ_3 + 3 + + + + TIMEHW + 0x00000000 + Write to bits 63:32 of time always write timelw before timehw + 0x00000000 + + + TIMEHW + [31:0] + write-only + + + + + TIMELW + 0x00000004 + Write to bits 31:0 of time writes do not get copied to time until timehw is written + 0x00000000 + + + TIMELW + [31:0] + write-only + + + + + TIMEHR + 0x00000008 + Read from bits 63:32 of time always read timelr before timehr + 0x00000000 + + + TIMEHR + [31:0] + read-only + + + + + TIMELR + 0x0000000c + Read from bits 31:0 of time + 0x00000000 + + + TIMELR + [31:0] + read-only + modify + + + + + ALARM0 + 0x00000010 + Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM0 + [31:0] + read-write + + + + + ALARM1 + 0x00000014 + Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM1 + [31:0] + read-write + + + + + ALARM2 + 0x00000018 + Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM2 + [31:0] + read-write + + + + + ALARM3 + 0x0000001c + Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM3 + [31:0] + read-write + + + + + ARMED + 0x00000020 + Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + 0x00000024 + Raw read from bits 63:32 of time (no side effects) + 0x00000000 + + + TIMERAWH + [31:0] + read-only + + + + + TIMERAWL + 0x00000028 + Raw read from bits 31:0 of time (no side effects) + 0x00000000 + + + TIMERAWL + [31:0] + read-only + + + + + DBGPAUSE + 0x0000002c + Set bits high to enable pause when the corresponding debug ports are active + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + 0x00000030 + Set high to pause the timer + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + LOCKED + 0x00000034 + Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + 0x00000000 + + + LOCKED + [0:0] + read-write + + + + + SOURCE + 0x00000038 + Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. + 0x00000000 + + + CLK_SYS + [0:0] + read-write + + + TICK + 0 + + + CLK_SYS + 1 + + + + + + + INTR + 0x0000003c + Raw Interrupts + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000040 + Interrupt Enable + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + 0x00000044 + Interrupt Force + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + 0x00000048 + Interrupt status after masking & forcing + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + TIMER1 + 0x400b8000 + + TIMER1_IRQ_0 + 4 + + + TIMER1_IRQ_1 + 5 + + + TIMER1_IRQ_2 + 6 + + + TIMER1_IRQ_3 + 7 + + + + PWM + Simple PWM + 0x400a8000 + + 0 + 272 + registers + + + PWM_IRQ_WRAP_0 + 8 + + + PWM_IRQ_WRAP_1 + 9 + + + + CH0_CSR + 0x00000000 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH0_DIV + 0x00000004 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH0_CTR + 0x00000008 + Direct access to the PWM counter + 0x00000000 + + + CH0_CTR + [15:0] + read-write + + + + + CH0_CC + 0x0000000c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH0_TOP + 0x00000010 + Counter wrap value + 0x0000ffff + + + CH0_TOP + [15:0] + read-write + + + + + CH1_CSR + 0x00000014 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH1_DIV + 0x00000018 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH1_CTR + 0x0000001c + Direct access to the PWM counter + 0x00000000 + + + CH1_CTR + [15:0] + read-write + + + + + CH1_CC + 0x00000020 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH1_TOP + 0x00000024 + Counter wrap value + 0x0000ffff + + + CH1_TOP + [15:0] + read-write + + + + + CH2_CSR + 0x00000028 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH2_DIV + 0x0000002c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH2_CTR + 0x00000030 + Direct access to the PWM counter + 0x00000000 + + + CH2_CTR + [15:0] + read-write + + + + + CH2_CC + 0x00000034 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH2_TOP + 0x00000038 + Counter wrap value + 0x0000ffff + + + CH2_TOP + [15:0] + read-write + + + + + CH3_CSR + 0x0000003c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH3_DIV + 0x00000040 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH3_CTR + 0x00000044 + Direct access to the PWM counter + 0x00000000 + + + CH3_CTR + [15:0] + read-write + + + + + CH3_CC + 0x00000048 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH3_TOP + 0x0000004c + Counter wrap value + 0x0000ffff + + + CH3_TOP + [15:0] + read-write + + + + + CH4_CSR + 0x00000050 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH4_DIV + 0x00000054 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH4_CTR + 0x00000058 + Direct access to the PWM counter + 0x00000000 + + + CH4_CTR + [15:0] + read-write + + + + + CH4_CC + 0x0000005c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH4_TOP + 0x00000060 + Counter wrap value + 0x0000ffff + + + CH4_TOP + [15:0] + read-write + + + + + CH5_CSR + 0x00000064 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH5_DIV + 0x00000068 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH5_CTR + 0x0000006c + Direct access to the PWM counter + 0x00000000 + + + CH5_CTR + [15:0] + read-write + + + + + CH5_CC + 0x00000070 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH5_TOP + 0x00000074 + Counter wrap value + 0x0000ffff + + + CH5_TOP + [15:0] + read-write + + + + + CH6_CSR + 0x00000078 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH6_DIV + 0x0000007c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH6_CTR + 0x00000080 + Direct access to the PWM counter + 0x00000000 + + + CH6_CTR + [15:0] + read-write + + + + + CH6_CC + 0x00000084 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH6_TOP + 0x00000088 + Counter wrap value + 0x0000ffff + + + CH6_TOP + [15:0] + read-write + + + + + CH7_CSR + 0x0000008c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH7_DIV + 0x00000090 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH7_CTR + 0x00000094 + Direct access to the PWM counter + 0x00000000 + + + CH7_CTR + [15:0] + read-write + + + + + CH7_CC + 0x00000098 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH7_TOP + 0x0000009c + Counter wrap value + 0x0000ffff + + + CH7_TOP + [15:0] + read-write + + + + + CH8_CSR + 0x000000a0 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH8_DIV + 0x000000a4 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH8_CTR + 0x000000a8 + Direct access to the PWM counter + 0x00000000 + + + CH8_CTR + [15:0] + read-write + + + + + CH8_CC + 0x000000ac + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH8_TOP + 0x000000b0 + Counter wrap value + 0x0000ffff + + + CH8_TOP + [15:0] + read-write + + + + + CH9_CSR + 0x000000b4 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH9_DIV + 0x000000b8 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH9_CTR + 0x000000bc + Direct access to the PWM counter + 0x00000000 + + + CH9_CTR + [15:0] + read-write + + + + + CH9_CC + 0x000000c0 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH9_TOP + 0x000000c4 + Counter wrap value + 0x0000ffff + + + CH9_TOP + [15:0] + read-write + + + + + CH10_CSR + 0x000000c8 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH10_DIV + 0x000000cc + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH10_CTR + 0x000000d0 + Direct access to the PWM counter + 0x00000000 + + + CH10_CTR + [15:0] + read-write + + + + + CH10_CC + 0x000000d4 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH10_TOP + 0x000000d8 + Counter wrap value + 0x0000ffff + + + CH10_TOP + [15:0] + read-write + + + + + CH11_CSR + 0x000000dc + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH11_DIV + 0x000000e0 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH11_CTR + 0x000000e4 + Direct access to the PWM counter + 0x00000000 + + + CH11_CTR + [15:0] + read-write + + + + + CH11_CC + 0x000000e8 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH11_TOP + 0x000000ec + Counter wrap value + 0x0000ffff + + + CH11_TOP + [15:0] + read-write + + + + + EN + 0x000000f0 + This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + 0x000000f4 + Raw Interrupts + 0x00000000 + + + CH11 + [11:11] + read-write + oneToClear + + + CH10 + [10:10] + read-write + oneToClear + + + CH9 + [9:9] + read-write + oneToClear + + + CH8 + [8:8] + read-write + oneToClear + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + IRQ0_INTE + 0x000000f8 + Interrupt Enable for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTF + 0x000000fc + Interrupt Force for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000100 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + IRQ1_INTE + 0x00000104 + Interrupt Enable for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000108 + Interrupt Force for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTS + 0x0000010c + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + ADC + Control and data interface to SAR ADC + 0x400a0000 + + 0 + 36 + registers + + + ADC_IRQ_FIFO + 35 + + + + CS + 0x00000000 + ADC Control and Status + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel. + [24:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order + [15:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + write-only + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock. + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + 0x00000004 + Result of most recent ADC conversion + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + 0x00000008 + FIFO control and status + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + 0x0000000c + Conversion result FIFO + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + modify + + + VAL + [11:0] + read-only + modify + + + + + DIV + 0x00000010 + Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + 0x00000014 + Raw Interrupts + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + 0x00000018 + Interrupt Enable + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + 0x0000001c + Interrupt Force + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + 0x00000020 + Interrupt status after masking & forcing + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + I2C0 + DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 + 0x40090000 + + 0 + 256 + registers + + + I2C0_IRQ + 36 + + + + IC_CON + 0x00000000 + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + 0 + Overflow when RX_FIFO is full + + + ENABLED + 1 + Hold bus when RX_FIFO is full + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + 0 + Default behaviour of TX_EMPTY interrupt + + + ENABLED + 1 + Controlled generation of TX_EMPTY interrupt + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + 0 + slave issues STOP_DET intr always + + + ENABLED + 1 + slave issues STOP_DET intr only if addressed + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + 0 + Slave mode is enabled + + + SLAVE_DISABLED + 1 + Slave mode is disabled + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + 0 + Master restart disabled + + + ENABLED + 1 + Master restart enabled + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + 0 + Master 7Bit addressing mode + + + ADDR_10BITS + 1 + Master 10Bit addressing mode + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + 0 + Slave 7Bit addressing + + + ADDR_10BITS + 1 + Slave 10Bit addressing + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + 1 + Standard Speed mode of operation + + + FAST + 2 + Fast or Fast Plus mode of operation + + + HIGH + 3 + High Speed mode of operation + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + 0 + Master mode is disabled + + + ENABLED + 1 + Master mode is enabled + + + + + + + IC_TAR + 0x00000004 + I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + 0 + Disables programming of GENERAL_CALL or START_BYTE transmission + + + ENABLED + 1 + Enables programming of GENERAL_CALL or START_BYTE transmission + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + 0 + GENERAL_CALL byte transmission + + + START_BYTE + 1 + START byte transmission + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + 0x00000008 + I2C Slave Address Register + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + 0x00000010 + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + 0 + Sequential data byte received + + + ACTIVE + 1 + Non sequential data byte received + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0 + [10:10] + write-only + + + DISABLE + 0 + Don't Issue RESTART before this command + + + ENABLE + 1 + Issue RESTART before this command + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + write-only + + + DISABLE + 0 + Don't Issue STOP after this command + + + ENABLE + 1 + Issue STOP after this command + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0 + [8:8] + write-only + + + WRITE + 0 + Master Write Command + + + READ + 1 + Master Read Command + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + 0x00000014 + Standard Speed I2C Clock SCL High Count Register + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + 0x00000018 + Standard Speed I2C Clock SCL Low Count Register + 0x0000002f + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + 0x0000001c + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + 0x00000020 + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x0000000d + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + 0x0000002c + I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + R_RESTART_DET interrupt is inactive + + + ACTIVE + 1 + R_RESTART_DET interrupt is active + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + R_GEN_CALL interrupt is inactive + + + ACTIVE + 1 + R_GEN_CALL interrupt is active + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + R_START_DET interrupt is inactive + + + ACTIVE + 1 + R_START_DET interrupt is active + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + R_STOP_DET interrupt is inactive + + + ACTIVE + 1 + R_STOP_DET interrupt is active + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + R_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + R_ACTIVITY interrupt is active + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + R_RX_DONE interrupt is inactive + + + ACTIVE + 1 + R_RX_DONE interrupt is active + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + R_TX_ABRT interrupt is inactive + + + ACTIVE + 1 + R_TX_ABRT interrupt is active + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + R_RD_REQ interrupt is inactive + + + ACTIVE + 1 + R_RD_REQ interrupt is active + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + 0 + R_TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + R_TX_EMPTY interrupt is active + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + R_TX_OVER interrupt is inactive + + + ACTIVE + 1 + R_TX_OVER interrupt is active + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + R_RX_FULL interrupt is inactive + + + ACTIVE + 1 + R_RX_FULL interrupt is active + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + R_RX_OVER interrupt is inactive + + + ACTIVE + 1 + R_RX_OVER interrupt is active + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_INTR_MASK + 0x00000030 + I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x000008ff + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + 0 + RESTART_DET interrupt is masked + + + DISABLED + 1 + RESTART_DET interrupt is unmasked + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + 0 + GEN_CALL interrupt is masked + + + DISABLED + 1 + GEN_CALL interrupt is unmasked + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + 0 + START_DET interrupt is masked + + + DISABLED + 1 + START_DET interrupt is unmasked + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + 0 + STOP_DET interrupt is masked + + + DISABLED + 1 + STOP_DET interrupt is unmasked + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + 0 + ACTIVITY interrupt is masked + + + DISABLED + 1 + ACTIVITY interrupt is unmasked + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + 0 + RX_DONE interrupt is masked + + + DISABLED + 1 + RX_DONE interrupt is unmasked + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + 0 + TX_ABORT interrupt is masked + + + DISABLED + 1 + TX_ABORT interrupt is unmasked + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + 0 + RD_REQ interrupt is masked + + + DISABLED + 1 + RD_REQ interrupt is unmasked + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + 0 + TX_EMPTY interrupt is masked + + + DISABLED + 1 + TX_EMPTY interrupt is unmasked + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + 0 + TX_OVER interrupt is masked + + + DISABLED + 1 + TX_OVER interrupt is unmasked + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + 0 + RX_FULL interrupt is masked + + + DISABLED + 1 + RX_FULL interrupt is unmasked + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + 0 + RX_OVER interrupt is masked + + + DISABLED + 1 + RX_OVER interrupt is unmasked + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + 0 + RX_UNDER interrupt is masked + + + DISABLED + 1 + RX_UNDER interrupt is unmasked + + + + + + + IC_RAW_INTR_STAT + 0x00000034 + I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + RESTART_DET interrupt is inactive + + + ACTIVE + 1 + RESTART_DET interrupt is active + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + GEN_CALL interrupt is inactive + + + ACTIVE + 1 + GEN_CALL interrupt is active + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + START_DET interrupt is inactive + + + ACTIVE + 1 + START_DET interrupt is active + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + STOP_DET interrupt is inactive + + + ACTIVE + 1 + STOP_DET interrupt is active + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + RAW_INTR_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + RAW_INTR_ACTIVITY interrupt is active + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + RX_DONE interrupt is inactive + + + ACTIVE + 1 + RX_DONE interrupt is active + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + TX_ABRT interrupt is inactive + + + ACTIVE + 1 + TX_ABRT interrupt is active + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + RD_REQ interrupt is inactive + + + ACTIVE + 1 + RD_REQ interrupt is active + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + 0 + TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + TX_EMPTY interrupt is active + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + TX_OVER interrupt is inactive + + + ACTIVE + 1 + TX_OVER interrupt is active + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + RX_FULL interrupt is inactive + + + ACTIVE + 1 + RX_FULL interrupt is active + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + RX_OVER interrupt is inactive + + + ACTIVE + 1 + RX_OVER interrupt is active + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_RX_TL + 0x00000038 + I2C Receive FIFO Threshold Register + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + 0x0000003c + I2C Transmit FIFO Threshold Register + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + 0x00000040 + Clear Combined and Individual Interrupt Register + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + 0x00000044 + Clear RX_UNDER Interrupt Register + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + 0x00000048 + Clear RX_OVER Interrupt Register + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + 0x0000004c + Clear TX_OVER Interrupt Register + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + 0x00000050 + Clear RD_REQ Interrupt Register + 0x00000000 + + + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_ABRT + 0x00000054 + Clear TX_ABRT Interrupt Register + 0x00000000 + + + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_DONE + 0x00000058 + Clear RX_DONE Interrupt Register + 0x00000000 + + + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_ACTIVITY + 0x0000005c + Clear ACTIVITY Interrupt Register + 0x00000000 + + + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + 0x00000060 + Clear STOP_DET Interrupt Register + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + 0x00000064 + Clear START_DET Interrupt Register + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + 0x00000068 + Clear GEN_CALL Interrupt Register + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + 0x0000006c + I2C Enable Register + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] + read-write + + + NOT_BLOCKED + 0 + Tx Command execution not blocked + + + BLOCKED + 1 + Tx Command execution blocked + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + 0 + ABORT operation not in progress + + + ENABLED + 1 + ABORT operation in progress + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + I2C is disabled + + + ENABLED + 1 + I2C is enabled + + + + + + + IC_STATUS + 0x00000070 + I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + 0 + Slave is idle + + + ACTIVE + 1 + Slave not idle + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0 + [5:5] + read-only + + + IDLE + 0 + Master is idle + + + ACTIVE + 1 + Master not idle + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + 0 + Rx FIFO not full + + + FULL + 1 + Rx FIFO is full + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + 0 + Rx FIFO is empty + + + NOT_EMPTY + 1 + Rx FIFO not empty + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + 0 + Tx FIFO not empty + + + EMPTY + 1 + Tx FIFO is empty + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + 0 + Tx FIFO is full + + + NOT_FULL + 1 + Tx FIFO not full + + + + + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + I2C is idle + + + ACTIVE + 1 + I2C is active + + + + + + + IC_TXFLR + 0x00000074 + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x00000000 + + + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_RXFLR + 0x00000078 + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x00000000 + + + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_SDA_HOLD + 0x0000007c + I2C SDA Hold Time Length Register + + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE[0]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x00000001 + + + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] + read-write + + + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + [15:0] + read-write + + + + + IC_TX_ABRT_SOURCE + 0x00000080 + I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x00000000 + + + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only + + + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + 0 + Transfer abort detected by master- scenario not present + + + ABRT_USER_ABRT_GENERATED + 1 + Transfer abort detected by master + + + + + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + 0 + Slave trying to transmit to remote master in read mode- scenario not present + + + ABRT_SLVRD_INTX_GENERATED + 1 + Slave trying to transmit to remote master in read mode + + + + + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + 0 + Slave lost arbitration to remote master- scenario not present + + + ABRT_SLV_ARBLOST_GENERATED + 1 + Slave lost arbitration to remote master + + + + + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + 0 + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + 1 + Slave flushes existing data in TX-FIFO upon getting read command + + + + + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + 0 + Master or Slave-Transmitter lost arbitration- scenario not present + + + ABRT_LOST_GENERATED + 1 + Master or Slave-Transmitter lost arbitration + + + + + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [11:11] + read-only + + + ABRT_MASTER_DIS_VOID + 0 + User initiating master operation when MASTER disabled- scenario not present + + + ABRT_MASTER_DIS_GENERATED + 1 + User initiating master operation when MASTER disabled + + + + + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver + [10:10] + read-only + + + ABRT_10B_RD_VOID + 0 + Master not trying to read in 10Bit addressing mode when RESTART disabled + + + ABRT_10B_RD_GENERATED + 1 + Master trying to read in 10Bit addressing mode when RESTART disabled + + + + + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [9:9] + read-only + + + ABRT_SBYTE_NORSTRT_VOID + 0 + User trying to send START byte when RESTART disabled- scenario not present + + + ABRT_SBYTE_NORSTRT_GENERATED + 1 + User trying to send START byte when RESTART disabled + + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + + + ABRT_HS_NORSTRT_VOID + 0 + User trying to switch Master to HS mode when RESTART disabled- scenario not present + + + ABRT_HS_NORSTRT_GENERATED + 1 + User trying to switch Master to HS mode when RESTART disabled + + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [7:7] + read-only + + + ABRT_SBYTE_ACKDET_VOID + 0 + ACK detected for START byte- scenario not present + + + ABRT_SBYTE_ACKDET_GENERATED + 1 + ACK detected for START byte + + + + + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [6:6] + read-only + + + ABRT_HS_ACK_VOID + 0 + HS Master code ACKed in HS Mode- scenario not present + + + ABRT_HS_ACK_GENERATED + 1 + HS Master code ACKed in HS Mode + + + + + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [5:5] + read-only + + + ABRT_GCALL_READ_VOID + 0 + GCALL is followed by read from bus-scenario not present + + + ABRT_GCALL_READ_GENERATED + 1 + GCALL is followed by read from bus + + + + + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [4:4] + read-only + + + ABRT_GCALL_NOACK_VOID + 0 + GCALL not ACKed by any slave-scenario not present + + + ABRT_GCALL_NOACK_GENERATED + 1 + GCALL not ACKed by any slave + + + + + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + 0 + Transmitted data non-ACKed by addressed slave-scenario not present + + + ABRT_TXDATA_NOACK_GENERATED + 1 + Transmitted data not ACKed by addressed slave + + + + + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 2 of 10Bit Address not ACKed by any slave + + + + + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 1 of 10Bit Address not ACKed by any slave + + + + + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + This abort is generated because of NOACK for 7-bit address + + + + + + + IC_SLV_DATA_NACK_ONLY + 0x00000084 + Generate Slave Data NACK Register + + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. + + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x00000000 + + + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Slave receiver generates NACK normally + + + ENABLED + 1 + Slave receiver generates NACK upon data reception only + + + + + + + IC_DMA_CR + 0x00000088 + DMA Control Register + + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x00000000 + + + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] + read-write + + + DISABLED + 0 + transmit FIFO DMA channel disabled + + + ENABLED + 1 + Transmit FIFO DMA channel enabled + + + + + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Receive FIFO DMA channel disabled + + + ENABLED + 1 + Receive FIFO DMA channel enabled + + + + + + + IC_DMA_TDLR + 0x0000008c + DMA Transmit Data Level Register + 0x00000000 + + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_DMA_RDLR + 0x00000090 + I2C Receive Data Level Register + 0x00000000 + + + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_SDA_SETUP + 0x00000094 + I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE[0] = 0. + + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x00000064 + + + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] + read-write + + + + + IC_ACK_GENERAL_CALL + 0x00000098 + I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x00000001 + + + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] + read-write + + + DISABLED + 0 + Generate NACK for a General Call + + + ENABLED + 1 + Generate ACK for a General Call + + + + + + + IC_ENABLE_STATUS + 0x0000009c + I2C Enable Status Register + + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. + + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. + + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. + + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x00000000 + + + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + Slave RX Data is not lost + + + ACTIVE + 1 + Slave RX Data is lost + + + + + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + Slave is disabled when it is idle + + + ACTIVE + 1 + Slave is disabled when it is active + + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0 + [0:0] + read-only + + + DISABLED + 0 + I2C disabled + + + ENABLED + 1 + I2C enabled + + + + + + + IC_FS_SPKLEN + 0x000000a0 + I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0x00000007 + + + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] + read-write + + + + + IC_CLR_RESTART_DET + 0x000000a8 + Clear RESTART_DET Interrupt Register + 0x00000000 + + + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_COMP_PARAM_1 + 0x000000f4 + Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0x00000000 + + + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only + + + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + 0x000000f8 + I2C Component Version Register + 0x3230312a + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + 0x000000fc + I2C Component Type Register + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + + + + I2C1 + 0x40098000 + + I2C1_IRQ + 37 + + + + SPI0 + 0x40080000 + + 0 + 4096 + registers + + + SPI0_IRQ + 31 + + + + SSPCR0 + 0x00000000 + Control register 0, SSPCR0 on page 3-4 + 0x00000000 + + + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] + read-write + + + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] + read-write + + + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] + read-write + + + FRF + Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. + [5:4] + read-write + + + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] + read-write + + + + + SSPCR1 + 0x00000004 + Control register 1, SSPCR1 on page 3-5 + 0x00000000 + + + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] + read-write + + + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] + read-write + + + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] + read-write + + + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] + read-write + + + + + SSPDR + 0x00000008 + Data register, SSPDR on page 3-6 + 0x00000000 + + + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + modify + + + + + SSPSR + 0x0000000c + Status register, SSPSR on page 3-7 + 0x00000003 + + + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only + + + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only + + + + + SSPCPSR + 0x00000010 + Clock prescale register, SSPCPSR on page 3-8 + 0x00000000 + + + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + SSPIMSC + 0x00000014 + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x00000000 + + + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] + read-write + + + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] + read-write + + + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] + read-write + + + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] + read-write + + + + + SSPRIS + 0x00000018 + Raw interrupt status register, SSPRIS on page 3-10 + 0x00000008 + + + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPMIS + 0x0000001c + Masked interrupt status register, SSPMIS on page 3-11 + 0x00000000 + + + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPICR + 0x00000020 + Interrupt clear register, SSPICR on page 3-11 + 0x00000000 + + + RTIC + Clears the SSPRTINTR interrupt + [1:1] + read-write + oneToClear + + + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + 0x00000024 + DMA control register, SSPDMACR on page 3-12 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + SSPPERIPHID0 + 0x00000fe0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000022 + + + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only + + + + + SSPPERIPHID1 + 0x00000fe4 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + SSPPERIPHID2 + 0x00000fe8 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + 0x00000fec + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + SSPPCELLID0 + 0x00000ff0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0000000d + + + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + SSPPCELLID1 + 0x00000ff4 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000f0 + + + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + SSPPCELLID2 + 0x00000ff8 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x00000005 + + + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + SSPPCELLID3 + 0x00000ffc + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000b1 + + + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + SPI1 + 0x40088000 + + SPI1_IRQ + 32 + + + + PIO0 + Programmable IO block + 0x50200000 + + 0 + 392 + registers + + + PIO0_IRQ_0 + 15 + + + PIO0_IRQ_1 + 16 + + + + CTRL + 0x00000000 + PIO control register + 0x00000000 + + + NEXTPREV_CLKDIV_RESTART + Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + [26:26] + write-only + + + NEXTPREV_SM_DISABLE + Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + [25:25] + write-only + + + NEXTPREV_SM_ENABLE + Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + + If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. + [24:24] + write-only + + + NEXT_PIO_MASK + A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [23:20] + write-only + + + PREV_PIO_MASK + A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [19:16] + write-only + + + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + write-only + + + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. + + The contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + write-only + + + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] + read-write + + + + + FSTAT + 0x00000004 + FIFO status register + 0x0f000f00 + + + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only + + + TXFULL + State machine TX FIFO is full + [19:16] + read-only + + + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only + + + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + + FDEBUG + 0x00000008 + FIFO debug register + 0x00000000 + + + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] + read-write + oneToClear + + + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] + read-write + oneToClear + + + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] + read-write + oneToClear + + + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] + read-write + oneToClear + + + + + FLEVEL + 0x0000000c + FIFO levels + 0x00000000 + + + RX3 + [31:28] + read-only + + + TX3 + [27:24] + read-only + + + RX2 + [23:20] + read-only + + + TX2 + [19:16] + read-only + + + RX1 + [15:12] + read-only + + + TX1 + [11:8] + read-only + + + RX0 + [7:4] + read-only + + + TX0 + [3:0] + read-only + + + + + TXF0 + 0x00000010 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF0 + [31:0] + write-only + + + + + TXF1 + 0x00000014 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF1 + [31:0] + write-only + + + + + TXF2 + 0x00000018 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF2 + [31:0] + write-only + + + + + TXF3 + 0x0000001c + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF3 + [31:0] + write-only + + + + + RXF0 + 0x00000020 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF0 + [31:0] + read-only + modify + + + + + RXF1 + 0x00000024 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF1 + [31:0] + read-only + modify + + + + + RXF2 + 0x00000028 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF2 + [31:0] + read-only + modify + + + + + RXF3 + 0x0000002c + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF3 + [31:0] + read-only + modify + + + + + IRQ + 0x00000030 + State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x00000000 + + + IRQ + [7:0] + read-write + oneToClear + + + + + IRQ_FORCE + 0x00000034 + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x00000000 + + + IRQ_FORCE + [7:0] + write-only + + + + + INPUT_SYNC_BYPASS + 0x00000038 + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + 0x00000000 + + + INPUT_SYNC_BYPASS + [31:0] + read-write + + + + + DBG_PADOUT + 0x0000003c + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOUT + [31:0] + read-only + + + + + DBG_PADOE + 0x00000040 + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOE + [31:0] + read-only + + + + + DBG_CFGINFO + 0x00000044 + The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + 0x10000000 + + + VERSION + Version of the core PIO hardware. + [31:28] + read-only + + + v0 + 0 + Version 0 (RP2040) + + + v1 + 1 + Version 1 (RP2350) + + + + + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only + + + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only + + + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. + [5:0] + read-only + + + + + INSTR_MEM0 + 0x00000048 + Write-only access to instruction memory location 0 + 0x00000000 + + + INSTR_MEM0 + [15:0] + write-only + + + + + INSTR_MEM1 + 0x0000004c + Write-only access to instruction memory location 1 + 0x00000000 + + + INSTR_MEM1 + [15:0] + write-only + + + + + INSTR_MEM2 + 0x00000050 + Write-only access to instruction memory location 2 + 0x00000000 + + + INSTR_MEM2 + [15:0] + write-only + + + + + INSTR_MEM3 + 0x00000054 + Write-only access to instruction memory location 3 + 0x00000000 + + + INSTR_MEM3 + [15:0] + write-only + + + + + INSTR_MEM4 + 0x00000058 + Write-only access to instruction memory location 4 + 0x00000000 + + + INSTR_MEM4 + [15:0] + write-only + + + + + INSTR_MEM5 + 0x0000005c + Write-only access to instruction memory location 5 + 0x00000000 + + + INSTR_MEM5 + [15:0] + write-only + + + + + INSTR_MEM6 + 0x00000060 + Write-only access to instruction memory location 6 + 0x00000000 + + + INSTR_MEM6 + [15:0] + write-only + + + + + INSTR_MEM7 + 0x00000064 + Write-only access to instruction memory location 7 + 0x00000000 + + + INSTR_MEM7 + [15:0] + write-only + + + + + INSTR_MEM8 + 0x00000068 + Write-only access to instruction memory location 8 + 0x00000000 + + + INSTR_MEM8 + [15:0] + write-only + + + + + INSTR_MEM9 + 0x0000006c + Write-only access to instruction memory location 9 + 0x00000000 + + + INSTR_MEM9 + [15:0] + write-only + + + + + INSTR_MEM10 + 0x00000070 + Write-only access to instruction memory location 10 + 0x00000000 + + + INSTR_MEM10 + [15:0] + write-only + + + + + INSTR_MEM11 + 0x00000074 + Write-only access to instruction memory location 11 + 0x00000000 + + + INSTR_MEM11 + [15:0] + write-only + + + + + INSTR_MEM12 + 0x00000078 + Write-only access to instruction memory location 12 + 0x00000000 + + + INSTR_MEM12 + [15:0] + write-only + + + + + INSTR_MEM13 + 0x0000007c + Write-only access to instruction memory location 13 + 0x00000000 + + + INSTR_MEM13 + [15:0] + write-only + + + + + INSTR_MEM14 + 0x00000080 + Write-only access to instruction memory location 14 + 0x00000000 + + + INSTR_MEM14 + [15:0] + write-only + + + + + INSTR_MEM15 + 0x00000084 + Write-only access to instruction memory location 15 + 0x00000000 + + + INSTR_MEM15 + [15:0] + write-only + + + + + INSTR_MEM16 + 0x00000088 + Write-only access to instruction memory location 16 + 0x00000000 + + + INSTR_MEM16 + [15:0] + write-only + + + + + INSTR_MEM17 + 0x0000008c + Write-only access to instruction memory location 17 + 0x00000000 + + + INSTR_MEM17 + [15:0] + write-only + + + + + INSTR_MEM18 + 0x00000090 + Write-only access to instruction memory location 18 + 0x00000000 + + + INSTR_MEM18 + [15:0] + write-only + + + + + INSTR_MEM19 + 0x00000094 + Write-only access to instruction memory location 19 + 0x00000000 + + + INSTR_MEM19 + [15:0] + write-only + + + + + INSTR_MEM20 + 0x00000098 + Write-only access to instruction memory location 20 + 0x00000000 + + + INSTR_MEM20 + [15:0] + write-only + + + + + INSTR_MEM21 + 0x0000009c + Write-only access to instruction memory location 21 + 0x00000000 + + + INSTR_MEM21 + [15:0] + write-only + + + + + INSTR_MEM22 + 0x000000a0 + Write-only access to instruction memory location 22 + 0x00000000 + + + INSTR_MEM22 + [15:0] + write-only + + + + + INSTR_MEM23 + 0x000000a4 + Write-only access to instruction memory location 23 + 0x00000000 + + + INSTR_MEM23 + [15:0] + write-only + + + + + INSTR_MEM24 + 0x000000a8 + Write-only access to instruction memory location 24 + 0x00000000 + + + INSTR_MEM24 + [15:0] + write-only + + + + + INSTR_MEM25 + 0x000000ac + Write-only access to instruction memory location 25 + 0x00000000 + + + INSTR_MEM25 + [15:0] + write-only + + + + + INSTR_MEM26 + 0x000000b0 + Write-only access to instruction memory location 26 + 0x00000000 + + + INSTR_MEM26 + [15:0] + write-only + + + + + INSTR_MEM27 + 0x000000b4 + Write-only access to instruction memory location 27 + 0x00000000 + + + INSTR_MEM27 + [15:0] + write-only + + + + + INSTR_MEM28 + 0x000000b8 + Write-only access to instruction memory location 28 + 0x00000000 + + + INSTR_MEM28 + [15:0] + write-only + + + + + INSTR_MEM29 + 0x000000bc + Write-only access to instruction memory location 29 + 0x00000000 + + + INSTR_MEM29 + [15:0] + write-only + + + + + INSTR_MEM30 + 0x000000c0 + Write-only access to instruction memory location 30 + 0x00000000 + + + INSTR_MEM30 + [15:0] + write-only + + + + + INSTR_MEM31 + 0x000000c4 + Write-only access to instruction memory location 31 + 0x00000000 + + + INSTR_MEM31 + [15:0] + write-only + + + + + SM0_CLKDIV + 0x000000c8 + Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM0_EXECCTRL + 0x000000cc + Execution/behavioural settings for state machine 0 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM0_SHIFTCTRL + 0x000000d0 + Control behaviour of the input/output shift registers for state machine 0 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM0_ADDR + 0x000000d4 + Current instruction address of state machine 0 + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM0_INSTR + 0x000000d8 + Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM0_PINCTRL + 0x000000dc + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM1_CLKDIV + 0x000000e0 + Clock divisor register for state machine 1 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM1_EXECCTRL + 0x000000e4 + Execution/behavioural settings for state machine 1 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM1_SHIFTCTRL + 0x000000e8 + Control behaviour of the input/output shift registers for state machine 1 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM1_ADDR + 0x000000ec + Current instruction address of state machine 1 + 0x00000000 + + + SM1_ADDR + [4:0] + read-only + + + + + SM1_INSTR + 0x000000f0 + Read to see the instruction currently addressed by state machine 1's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM1_INSTR + [15:0] + read-write + + + + + SM1_PINCTRL + 0x000000f4 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM2_CLKDIV + 0x000000f8 + Clock divisor register for state machine 2 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM2_EXECCTRL + 0x000000fc + Execution/behavioural settings for state machine 2 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM2_SHIFTCTRL + 0x00000100 + Control behaviour of the input/output shift registers for state machine 2 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM2_ADDR + 0x00000104 + Current instruction address of state machine 2 + 0x00000000 + + + SM2_ADDR + [4:0] + read-only + + + + + SM2_INSTR + 0x00000108 + Read to see the instruction currently addressed by state machine 2's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM2_INSTR + [15:0] + read-write + + + + + SM2_PINCTRL + 0x0000010c + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM3_CLKDIV + 0x00000110 + Clock divisor register for state machine 3 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM3_EXECCTRL + 0x00000114 + Execution/behavioural settings for state machine 3 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM3_SHIFTCTRL + 0x00000118 + Control behaviour of the input/output shift registers for state machine 3 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM3_ADDR + 0x0000011c + Current instruction address of state machine 3 + 0x00000000 + + + SM3_ADDR + [4:0] + read-only + + + + + SM3_INSTR + 0x00000120 + Read to see the instruction currently addressed by state machine 3's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM3_INSTR + [15:0] + read-write + + + + + SM3_PINCTRL + 0x00000124 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + RXF0_PUTGET0 + 0x00000128 + Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET0 + [31:0] + read-write + + + + + RXF0_PUTGET1 + 0x0000012c + Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET1 + [31:0] + read-write + + + + + RXF0_PUTGET2 + 0x00000130 + Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET2 + [31:0] + read-write + + + + + RXF0_PUTGET3 + 0x00000134 + Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET3 + [31:0] + read-write + + + + + RXF1_PUTGET0 + 0x00000138 + Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET0 + [31:0] + read-write + + + + + RXF1_PUTGET1 + 0x0000013c + Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET1 + [31:0] + read-write + + + + + RXF1_PUTGET2 + 0x00000140 + Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET2 + [31:0] + read-write + + + + + RXF1_PUTGET3 + 0x00000144 + Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET3 + [31:0] + read-write + + + + + RXF2_PUTGET0 + 0x00000148 + Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET0 + [31:0] + read-write + + + + + RXF2_PUTGET1 + 0x0000014c + Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET1 + [31:0] + read-write + + + + + RXF2_PUTGET2 + 0x00000150 + Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET2 + [31:0] + read-write + + + + + RXF2_PUTGET3 + 0x00000154 + Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET3 + [31:0] + read-write + + + + + RXF3_PUTGET0 + 0x00000158 + Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET0 + [31:0] + read-write + + + + + RXF3_PUTGET1 + 0x0000015c + Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET1 + [31:0] + read-write + + + + + RXF3_PUTGET2 + 0x00000160 + Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET2 + [31:0] + read-write + + + + + RXF3_PUTGET3 + 0x00000164 + Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET3 + [31:0] + read-write + + + + + GPIOBASE + 0x00000168 + Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. + + Only the values 0 and 16 are supported (only bit 4 is writable). + 0x00000000 + + + GPIOBASE + [4:4] + read-write + + + + + INTR + 0x0000016c + Raw Interrupts + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ0_INTE + 0x00000170 + Interrupt Enable for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTF + 0x00000174 + Interrupt Force for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000178 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ1_INTE + 0x0000017c + Interrupt Enable for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000180 + Interrupt Force for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTS + 0x00000184 + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 17 + + + PIO1_IRQ_1 + 18 + + + + PIO2 + 0x50400000 + + PIO2_IRQ_0 + 19 + + + PIO2_IRQ_1 + 20 + + + + BUSCTRL + Register block for busfabric control signals and performance counters + 0x40068000 + + 0 + 44 + registers + + + + BUS_PRIORITY + 0x00000000 + Set the priority of each master for bus arbitration. + 0x00000000 + + + DMA_W + 0 - low priority, 1 - high priority + [12:12] + read-write + + + DMA_R + 0 - low priority, 1 - high priority + [8:8] + read-write + + + PROC1 + 0 - low priority, 1 - high priority + [4:4] + read-write + + + PROC0 + 0 - low priority, 1 - high priority + [0:0] + read-write + + + + + BUS_PRIORITY_ACK + 0x00000004 + Bus priority acknowledge + 0x00000000 + + + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + + PERFCTR_EN + 0x00000008 + Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. + + The performance counters are initially disabled, to save energy. + 0x00000000 + + + PERFCTR_EN + [0:0] + read-write + + + + + PERFCTR0 + 0x0000000c + Bus fabric performance counter 0 + 0x00000000 + + + PERFCTR0 + Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] + read-write + oneToClear + + + + + PERFSEL0 + 0x00000010 + Bus fabric performance event select for PERFCTR0 + 0x0000001f + + + PERFSEL0 + Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR1 + 0x00000014 + Bus fabric performance counter 1 + 0x00000000 + + + PERFCTR1 + Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] + read-write + oneToClear + + + + + PERFSEL1 + 0x00000018 + Bus fabric performance event select for PERFCTR1 + 0x0000001f + + + PERFSEL1 + Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR2 + 0x0000001c + Bus fabric performance counter 2 + 0x00000000 + + + PERFCTR2 + Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] + read-write + oneToClear + + + + + PERFSEL2 + 0x00000020 + Bus fabric performance event select for PERFCTR2 + 0x0000001f + + + PERFSEL2 + Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR3 + 0x00000024 + Bus fabric performance counter 3 + 0x00000000 + + + PERFCTR3 + Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + + PERFSEL3 + 0x00000028 + Bus fabric performance event select for PERFCTR3 + 0x0000001f + + + PERFSEL3 + Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + + + SIO + Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xd0000000 + + 0 + 488 + registers + + + SIO_IRQ_FIFO + 25 + + + SIO_IRQ_BELL + 26 + + + SIO_IRQ_FIFO_NS + 27 + + + SIO_IRQ_BELL_NS + 28 + + + SIO_IRQ_MTIMECMP + 29 + + + + CPUID + 0x00000000 + Processor core identifier + 0x00000000 + + + CPUID + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + [31:0] + read-only + + + + + GPIO_IN + 0x00000004 + Input value for GPIO0...31. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + GPIO_IN + [31:0] + read-only + + + + + GPIO_HI_IN + 0x00000008 + Input value on GPIO32...47, QSPI IOs and USB pins + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + QSPI_SD + Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-only + + + QSPI_CSN + Input value on QSPI CSn pin + [27:27] + read-only + + + QSPI_SCK + Input value on QSPI SCK pin + [26:26] + read-only + + + USB_DM + Input value on USB D- pin + [25:25] + read-only + + + USB_DP + Input value on USB D+ pin + [24:24] + read-only + + + GPIO + Input value on GPIO32...47 + [15:0] + read-only + + + + + GPIO_OUT + 0x00000010 + GPIO0...31 output value + 0x00000000 + + + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. + + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OUT + 0x00000014 + Output value for GPIO32...47, QSPI IOs and USB pins. + + Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output value for USB D- pin + [25:25] + read-write + + + USB_DP + Output value for USB D+ pin + [24:24] + read-write + + + GPIO + Output value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OUT_SET + 0x00000018 + GPIO0...31 output value set + 0x00000000 + + + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_SET + 0x0000001c + Output value set for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_CLR + 0x00000020 + GPIO0...31 output value clear + 0x00000000 + + + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_CLR + 0x00000024 + Output value clear for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_XOR + 0x00000028 + GPIO0...31 output value XOR + 0x00000000 + + + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_XOR + 0x0000002c + Output value XOR for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE + 0x00000030 + GPIO0...31 output enable + 0x00000000 + + + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. + + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OE + 0x00000034 + Output enable value for GPIO32...47, QSPI IOs and USB pins. + + Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output enable value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output enable value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output enable value for USB D- pin + [25:25] + read-write + + + USB_DP + Output enable value for USB D+ pin + [24:24] + read-write + + + GPIO + Output enable value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OE_SET + 0x00000038 + GPIO0...31 output enable set + 0x00000000 + + + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_SET + 0x0000003c + Output enable set for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_CLR + 0x00000040 + GPIO0...31 output enable clear + 0x00000000 + + + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_CLR + 0x00000044 + Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_XOR + 0x00000048 + GPIO0...31 output enable XOR + 0x00000000 + + + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_XOR + 0x0000004c + Output enable XOR for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + FIFO_ST + 0x00000050 + Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x00000002 + + + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] + read-write + oneToClear + + + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] + read-write + oneToClear + + + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only + + + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + + FIFO_WR + 0x00000054 + Write access to this core's TX FIFO + 0x00000000 + + + FIFO_WR + [31:0] + write-only + + + + + FIFO_RD + 0x00000058 + Read access to this core's RX FIFO + 0x00000000 + + + FIFO_RD + [31:0] + read-only + modify + + + + + SPINLOCK_ST + 0x0000005c + Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + 0x00000000 + + + SPINLOCK_ST + [31:0] + read-only + + + + + INTERP0_ACCUM0 + 0x00000080 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP0_ACCUM0 + [31:0] + read-write + + + + + INTERP0_ACCUM1 + 0x00000084 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP0_ACCUM1 + [31:0] + read-write + + + + + INTERP0_BASE0 + 0x00000088 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP0_BASE0 + [31:0] + read-write + + + + + INTERP0_BASE1 + 0x0000008c + Read/write access to BASE1 register. + 0x00000000 + + + INTERP0_BASE1 + [31:0] + read-write + + + + + INTERP0_BASE2 + 0x00000090 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP0_BASE2 + [31:0] + read-write + + + + + INTERP0_POP_LANE0 + 0x00000094 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE0 + [31:0] + read-only + + + + + INTERP0_POP_LANE1 + 0x00000098 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE1 + [31:0] + read-only + + + + + INTERP0_POP_FULL + 0x0000009c + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_FULL + [31:0] + read-only + + + + + INTERP0_PEEK_LANE0 + 0x000000a0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP0_PEEK_LANE1 + 0x000000a4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP0_PEEK_FULL + 0x000000a8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_FULL + [31:0] + read-only + + + + + INTERP0_CTRL_LANE0 + 0x000000ac + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + [21:21] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_CTRL_LANE1 + 0x000000b0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_ACCUM0_ADD + 0x000000b4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP0_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP0_ACCUM1_ADD + 0x000000b8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP0_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP0_BASE_1AND0 + 0x000000bc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP0_BASE_1AND0 + [31:0] + write-only + + + + + INTERP1_ACCUM0 + 0x000000c0 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP1_ACCUM0 + [31:0] + read-write + + + + + INTERP1_ACCUM1 + 0x000000c4 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP1_ACCUM1 + [31:0] + read-write + + + + + INTERP1_BASE0 + 0x000000c8 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP1_BASE0 + [31:0] + read-write + + + + + INTERP1_BASE1 + 0x000000cc + Read/write access to BASE1 register. + 0x00000000 + + + INTERP1_BASE1 + [31:0] + read-write + + + + + INTERP1_BASE2 + 0x000000d0 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP1_BASE2 + [31:0] + read-write + + + + + INTERP1_POP_LANE0 + 0x000000d4 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE0 + [31:0] + read-only + + + + + INTERP1_POP_LANE1 + 0x000000d8 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE1 + [31:0] + read-only + + + + + INTERP1_POP_FULL + 0x000000dc + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_FULL + [31:0] + read-only + + + + + INTERP1_PEEK_LANE0 + 0x000000e0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP1_PEEK_LANE1 + 0x000000e4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP1_PEEK_FULL + 0x000000e8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_FULL + [31:0] + read-only + + + + + INTERP1_CTRL_LANE0 + 0x000000ec + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_CTRL_LANE1 + 0x000000f0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_ACCUM0_ADD + 0x000000f4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP1_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP1_ACCUM1_ADD + 0x000000f8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP1_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP1_BASE_1AND0 + 0x000000fc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP1_BASE_1AND0 + [31:0] + write-only + + + + + SPINLOCK0 + 0x00000100 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK0 + [31:0] + read-write + modify + + + + + SPINLOCK1 + 0x00000104 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK1 + [31:0] + read-write + modify + + + + + SPINLOCK2 + 0x00000108 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK2 + [31:0] + read-write + modify + + + + + SPINLOCK3 + 0x0000010c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK3 + [31:0] + read-write + modify + + + + + SPINLOCK4 + 0x00000110 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK4 + [31:0] + read-write + modify + + + + + SPINLOCK5 + 0x00000114 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK5 + [31:0] + read-write + modify + + + + + SPINLOCK6 + 0x00000118 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK6 + [31:0] + read-write + modify + + + + + SPINLOCK7 + 0x0000011c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK7 + [31:0] + read-write + modify + + + + + SPINLOCK8 + 0x00000120 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK8 + [31:0] + read-write + modify + + + + + SPINLOCK9 + 0x00000124 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK9 + [31:0] + read-write + modify + + + + + SPINLOCK10 + 0x00000128 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK10 + [31:0] + read-write + modify + + + + + SPINLOCK11 + 0x0000012c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK11 + [31:0] + read-write + modify + + + + + SPINLOCK12 + 0x00000130 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK12 + [31:0] + read-write + modify + + + + + SPINLOCK13 + 0x00000134 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK13 + [31:0] + read-write + modify + + + + + SPINLOCK14 + 0x00000138 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK14 + [31:0] + read-write + modify + + + + + SPINLOCK15 + 0x0000013c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK15 + [31:0] + read-write + modify + + + + + SPINLOCK16 + 0x00000140 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK16 + [31:0] + read-write + modify + + + + + SPINLOCK17 + 0x00000144 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK17 + [31:0] + read-write + modify + + + + + SPINLOCK18 + 0x00000148 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK18 + [31:0] + read-write + modify + + + + + SPINLOCK19 + 0x0000014c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK19 + [31:0] + read-write + modify + + + + + SPINLOCK20 + 0x00000150 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK20 + [31:0] + read-write + modify + + + + + SPINLOCK21 + 0x00000154 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK21 + [31:0] + read-write + modify + + + + + SPINLOCK22 + 0x00000158 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK22 + [31:0] + read-write + modify + + + + + SPINLOCK23 + 0x0000015c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK23 + [31:0] + read-write + modify + + + + + SPINLOCK24 + 0x00000160 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK24 + [31:0] + read-write + modify + + + + + SPINLOCK25 + 0x00000164 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK25 + [31:0] + read-write + modify + + + + + SPINLOCK26 + 0x00000168 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK26 + [31:0] + read-write + modify + + + + + SPINLOCK27 + 0x0000016c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK27 + [31:0] + read-write + modify + + + + + SPINLOCK28 + 0x00000170 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK28 + [31:0] + read-write + modify + + + + + SPINLOCK29 + 0x00000174 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK29 + [31:0] + read-write + modify + + + + + SPINLOCK30 + 0x00000178 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK30 + [31:0] + read-write + modify + + + + + SPINLOCK31 + 0x0000017c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK31 + [31:0] + read-write + modify + + + + + DOORBELL_OUT_SET + 0x00000180 + Trigger a doorbell interrupt on the opposite core. + + Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. + + Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_SET + [7:0] + read-write + + + + + DOORBELL_OUT_CLR + 0x00000184 + Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. + + Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. + + Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_CLR + [7:0] + read-write + oneToClear + + + + + DOORBELL_IN_SET + 0x00000188 + Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_SET + [7:0] + read-write + + + + + DOORBELL_IN_CLR + 0x0000018c + Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. + + Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_CLR + [7:0] + read-write + oneToClear + + + + + PERI_NONSEC + 0x00000190 + Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. + + This register is per-core, and is only present on the Secure SIO. + + Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. + 0x00000000 + + + TMDS + IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [5:5] + read-write + + + INTERP1 + If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [1:1] + read-write + + + INTERP0 + If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [0:0] + read-write + + + + + RISCV_SOFTIRQ + 0x000001a0 + Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. + + Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. + + It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. + 0x00000000 + + + CORE1_CLR + Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. + [9:9] + read-write + + + CORE0_CLR + Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. + [8:8] + read-write + + + CORE1_SET + Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. + [1:1] + read-write + + + CORE0_SET + Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. + [0:0] + read-write + + + + + MTIME_CTRL + 0x000001a4 + Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. + + Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. + 0x0000000d + + + DBGPAUSE_CORE1 + If 1, the timer pauses when core 1 is in the debug halt state. + [3:3] + read-write + + + DBGPAUSE_CORE0 + If 1, the timer pauses when core 0 is in the debug halt state. + [2:2] + read-write + + + FULLSPEED + If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. + [1:1] + read-write + + + EN + Timer enable bit. When 0, the timer will not increment automatically. + [0:0] + read-write + + + + + MTIME + 0x000001b0 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIME + [31:0] + read-write + + + + + MTIMEH + 0x000001b4 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIMEH + [31:0] + read-write + + + + + MTIMECMP + 0x000001b8 + Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMP + [31:0] + read-write + + + + + MTIMECMPH + 0x000001bc + High half of RISC-V Machine-mode timer comparator. This register is core-local. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMPH + [31:0] + read-write + + + + + TMDS_CTRL + 0x000001c0 + Control register for TMDS encoder. + 0x00000000 + + + CLEAR_BALANCE + Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. + [28:28] + write-only + + + PIX2_NOSHIFT + When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. + + This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. + [27:27] + read-write + + + PIX_SHIFT + Shift applied to the colour data register with each read of a POP alias register. + + Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. + + Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) + [26:24] + read-write + + + 0 + 0 + Do not shift the colour data register. + + + 1 + 1 + Shift the colour data register by 1 bit + + + 2 + 2 + Shift the colour data register by 2 bits + + + 4 + 3 + Shift the colour data register by 4 bits + + + 8 + 4 + Shift the colour data register by 8 bits + + + 16 + 5 + Shift the colour data register by 16 bits + + + + + INTERLEAVE + Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. + + When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. + + When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. + [23:23] + read-write + + + L2_NBITS + Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [20:18] + read-write + + + L1_NBITS + Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [17:15] + read-write + + + L0_NBITS + Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [14:12] + read-write + + + L2_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. + [11:8] + read-write + + + L1_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. + [7:4] + read-write + + + L0_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. + [3:0] + read-write + + + + + TMDS_WDATA + 0x000001c4 + Write-only access to the TMDS colour data register. + 0x00000000 + + + TMDS_WDATA + [31:0] + write-only + + + + + TMDS_PEEK_SINGLE + 0x000001c8 + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). + + The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. + 0x00000000 + + + TMDS_PEEK_SINGLE + [31:0] + read-only + modify + + + + + TMDS_POP_SINGLE + 0x000001cc + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. + + The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. + 0x00000000 + + + TMDS_POP_SINGLE + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L0 + 0x000001d0 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L0 + 0x000001d4 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L1 + 0x000001d8 + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L1 + 0x000001dc + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L2 + 0x000001e0 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L2 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L2 + 0x000001e4 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L2 + [31:0] + read-only + modify + + + + + + + SIO_NS + 0xd0020000 + + + BOOTRAM + Additional registers mapped adjacent to the bootram, for use by the bootrom. + 0x400e0000 + + 0 + 2092 + registers + + + + WRITE_ONCE0 + 0x00000800 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE0 + [31:0] + read-write + + + + + WRITE_ONCE1 + 0x00000804 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE1 + [31:0] + read-write + + + + + BOOTLOCK_STAT + 0x00000808 + Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. + 0x000000ff + + + BOOTLOCK_STAT + [7:0] + read-write + + + + + BOOTLOCK0 + 0x0000080c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK0 + [31:0] + read-write + + + + + BOOTLOCK1 + 0x00000810 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK1 + [31:0] + read-write + + + + + BOOTLOCK2 + 0x00000814 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK2 + [31:0] + read-write + + + + + BOOTLOCK3 + 0x00000818 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK3 + [31:0] + read-write + + + + + BOOTLOCK4 + 0x0000081c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK4 + [31:0] + read-write + + + + + BOOTLOCK5 + 0x00000820 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK5 + [31:0] + read-write + + + + + BOOTLOCK6 + 0x00000824 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK6 + [31:0] + read-write + + + + + BOOTLOCK7 + 0x00000828 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK7 + [31:0] + read-write + + + + + + + CORESIGHT_TRACE + Coresight block - RP specific registers + 0x50700000 + + 0 + 8 + registers + + + + CTRL_STATUS + 0x00000000 + Control and status register + 0x00000001 + + + TRACE_CAPTURE_FIFO_OVERFLOW + This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. + [1:1] + read-write + + + TRACE_CAPTURE_FIFO_FLUSH + Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. + + Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. + + Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. + [0:0] + read-write + + + + + TRACE_CAPTURE_FIFO + 0x00000004 + FIFO for trace data captured from the TPIU + 0x00000000 + + + RDATA + Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. + + Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: + + * TPIU TRACECTL output is low (normal trace data) + + * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) + + These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices + + The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. + [31:0] + read-only + modify + + + + + + + USB + USB FS/LS controller device registers + 0x50110000 + + 0 + 280 + registers + + + USBCTRL_IRQ + 14 + + + + ADDR_ENDP + 0x00000000 + Device address and endpoint control + 0x00000000 + + + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] + read-write + + + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] + read-write + + + + + ADDR_ENDP1 + 0x00000004 + Interrupt endpoint 1. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP2 + 0x00000008 + Interrupt endpoint 2. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP3 + 0x0000000c + Interrupt endpoint 3. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP4 + 0x00000010 + Interrupt endpoint 4. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP5 + 0x00000014 + Interrupt endpoint 5. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP6 + 0x00000018 + Interrupt endpoint 6. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP7 + 0x0000001c + Interrupt endpoint 7. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP8 + 0x00000020 + Interrupt endpoint 8. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP9 + 0x00000024 + Interrupt endpoint 9. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP10 + 0x00000028 + Interrupt endpoint 10. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP11 + 0x0000002c + Interrupt endpoint 11. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP12 + 0x00000030 + Interrupt endpoint 12. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP13 + 0x00000034 + Interrupt endpoint 13. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP14 + 0x00000038 + Interrupt endpoint 14. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP15 + 0x0000003c + Interrupt endpoint 15. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + MAIN_CTRL + 0x00000040 + Main control register + 0x00000004 + + + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write + + + PHY_ISO + Isolates USB phy after controller power-up + Remove isolation once software has configured the controller + Not isolated = 0, Isolated = 1 + [2:2] + read-write + + + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write + + + CONTROLLER_EN + Enable controller + [0:0] + read-write + + + + + SOF_WR + 0x00000044 + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x00000000 + + + COUNT + [10:0] + write-only + + + + + SOF_RD + 0x00000048 + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x00000000 + + + COUNT + [10:0] + read-only + + + + + SIE_CTRL + 0x0000004c + SIE control register + 0x00008000 + + + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] + read-write + + + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] + read-write + + + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] + read-write + + + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] + read-write + + + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] + read-write + + + DIRECT_EN + Direct bus drive enable + [26:26] + read-write + + + DIRECT_DP + Direct control of DP + [25:25] + read-write + + + DIRECT_DM + Direct control of DM + [24:24] + read-write + + + EP0_STOP_ON_SHORT_PACKET + Device: Stop EP0 on a short packet. + [19:19] + read-write + + + TRANSCEIVER_PD + Power down bus transceiver + [18:18] + read-write + + + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] + read-write + + + PULLUP_EN + Device: Enable pull up resistor + [16:16] + read-write + + + PULLDOWN_EN + Host: Enable pull down resistors + [15:15] + read-write + + + RESET_BUS + Host: Reset bus + [13:13] + write-only + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. + [12:12] + write-only + + + VBUS_EN + Host: Enable VBUS + [11:11] + read-write + + + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) + [10:10] + read-write + + + SOF_EN + Host: Enable SOF generation (for full speed bus) + [9:9] + read-write + + + SOF_SYNC + Host: Delay packet(s) until after SOF + [8:8] + read-write + + + PREAMBLE_EN + Host: Preable enable for LS device on FS hub + [6:6] + read-write + + + STOP_TRANS + Host: Stop transaction + [4:4] + write-only + + + RECEIVE_DATA + Host: Receive transaction (IN to host) + [3:3] + read-write + + + SEND_DATA + Host: Send transaction (OUT from host) + [2:2] + read-write + + + SEND_SETUP + Host: Send Setup packet + [1:1] + read-write + + + START_TRANS + Host: Start transaction + [0:0] + write-only + + + + + SIE_STATUS + 0x00000050 + SIE status register + 0x00000000 + + + DATA_SEQ_ERROR + Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear + + + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear + + + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear + + + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear + + + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear + + + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear + + + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear + + + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + ENDPOINT_ERROR + An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. + [23:23] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received + [19:19] + read-write + oneToClear + + + TRANS_COMPLETE + Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + [18:18] + read-write + oneToClear + + + SETUP_REC + Device: Setup packet received + [17:17] + read-write + oneToClear + + + CONNECTED + Device: connected + [16:16] + read-only + + + RX_SHORT_PACKET + Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. + [12:12] + read-write + oneToClear + + + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] + read-write + oneToClear + + + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only + + + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-only + + + SUSPENDED + Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] + read-write + oneToClear + + + LINE_STATE + USB bus line state + [3:2] + read-only + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + 0x00000054 + interrupt endpoint control register + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 -> 15 + [15:1] + read-write + + + + + BUFF_STATUS + 0x00000058 + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + BUFF_CPU_SHOULD_HANDLE + 0x0000005c + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x00000000 + + + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT + [19:19] + read-only + + + EP9_IN + [18:18] + read-only + + + EP8_OUT + [17:17] + read-only + + + EP8_IN + [16:16] + read-only + + + EP7_OUT + [15:15] + read-only + + + EP7_IN + [14:14] + read-only + + + EP6_OUT + [13:13] + read-only + + + EP6_IN + [12:12] + read-only + + + EP5_OUT + [11:11] + read-only + + + EP5_IN + [10:10] + read-only + + + EP4_OUT + [9:9] + read-only + + + EP4_IN + [8:8] + read-only + + + EP3_OUT + [7:7] + read-only + + + EP3_IN + [6:6] + read-only + + + EP2_OUT + [5:5] + read-only + + + EP2_IN + [4:4] + read-only + + + EP1_OUT + [3:3] + read-only + + + EP1_IN + [2:2] + read-only + + + EP0_OUT + [1:1] + read-only + + + EP0_IN + [0:0] + read-only + + + + + EP_ABORT + 0x00000060 + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] + read-write + + + EP11_OUT + [23:23] + read-write + + + EP11_IN + [22:22] + read-write + + + EP10_OUT + [21:21] + read-write + + + EP10_IN + [20:20] + read-write + + + EP9_OUT + [19:19] + read-write + + + EP9_IN + [18:18] + read-write + + + EP8_OUT + [17:17] + read-write + + + EP8_IN + [16:16] + read-write + + + EP7_OUT + [15:15] + read-write + + + EP7_IN + [14:14] + read-write + + + EP6_OUT + [13:13] + read-write + + + EP6_IN + [12:12] + read-write + + + EP5_OUT + [11:11] + read-write + + + EP5_IN + [10:10] + read-write + + + EP4_OUT + [9:9] + read-write + + + EP4_IN + [8:8] + read-write + + + EP3_OUT + [7:7] + read-write + + + EP3_IN + [6:6] + read-write + + + EP2_OUT + [5:5] + read-write + + + EP2_IN + [4:4] + read-write + + + EP1_OUT + [3:3] + read-write + + + EP1_IN + [2:2] + read-write + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + EP_ABORT_DONE + 0x00000064 + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + EP_STALL_ARM + 0x00000068 + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + 0x0000006c + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x00100010 + + + RETRY_COUNT_HI + Bits 9:6 of nak_retry count + [31:28] + read-only + + + EPX_STOPPED_ON_NAK + EPX polling has stopped because a nak was received + [27:27] + read-write + oneToClear + + + STOP_EPX_ON_NAK + Stop polling epx when a nak is received + [26:26] + read-write + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + RETRY_COUNT_LO + Bits 5:0 of nak_retry_count + [15:10] + read-only + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + 0x00000070 + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + 0x00000074 + Where to connect the USB controller. Should be to_phy by default. + 0x00000001 + + + SWAP_DPDM + Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. + This is done at a low level so overrides all other controls. + [31:31] + read-write + + + USBPHY_AS_GPIO + Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. + [4:4] + read-write + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + 0x00000078 + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT + [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + 0x0000007c + This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + 0x00000000 + + + RX_DM_OVERRIDE + Override rx_dm value into controller + [25:25] + read-write + + + RX_DP_OVERRIDE + Override rx_dp value into controller + [24:24] + read-write + + + RX_DD_OVERRIDE + Override rx_dd value into controller + [23:23] + read-write + + + DM_OVV + DM over voltage + [22:22] + read-only + + + DP_OVV + DP over voltage + [21:21] + read-only + + + DM_OVCN + DM overcurrent + [20:20] + read-only + + + DP_OVCN + DP overcurrent + [19:19] + read-only + + + RX_DM + DPM pin state + [18:18] + read-only + + + RX_DP + DPP pin state + [17:17] + read-only + + + RX_DD + Differential RX + [16:16] + read-only + + + TX_DIFFMODE + TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + [15:15] + read-write + + + TX_FSSLEW + TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate + [14:14] + read-write + + + TX_PD + TX power down override (if override enable is set). 1 = powered down. + [13:13] + read-write + + + RX_PD + RX power down override (if override enable is set). 1 = powered down. + [12:12] + read-write + + + TX_DM + Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write + + + TX_DP + Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + DM pull down enable + [6:6] + read-write + + + DM_PULLUP_EN + DM pull up enable + [5:5] + read-write + + + DM_PULLUP_HISEL + Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + DP pull down enable + [2:2] + read-write + + + DP_PULLUP_EN + DP pull up enable + [1:1] + read-write + + + DP_PULLUP_HISEL + Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + + + USBPHY_DIRECT_OVERRIDE + 0x00000080 + Override enable for each control in usbphy_direct + 0x00000000 + + + RX_DM_OVERRIDE_EN + [18:18] + read-write + + + RX_DP_OVERRIDE_EN + [17:17] + read-write + + + RX_DD_OVERRIDE_EN + [16:16] + read-write + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + + + + USBPHY_TRIM + 0x00000084 + Used to adjust trim values of USB phy pull down resistors. + 0x00001f1f + + + DM_PULLDN_TRIM + Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write + + + + + LINESTATE_TUNING + 0x00000088 + Used for debug only. + 0x000000f8 + + + SPARE_FIX + [11:8] + read-write + + + DEV_LS_WAKE_FIX + Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer + [7:7] + read-write + + + DEV_RX_ERR_QUIESCE + Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. + [6:6] + read-write + + + SIE_RX_CHATTER_SE0_FIX + RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as + 8 consecutive idle bits. + [5:5] + read-write + + + SIE_RX_BITSTUFF_FIX + RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to + avoid a hang during certain packet phases. + [4:4] + read-write + + + DEV_BUFF_CONTROL_DOUBLE_READ_FIX + Device - the controller FSM performs two reads of the buffer status memory address to + avoid sampling metastable data. An enabled buffer is only used if both reads match. + [3:3] + read-write + + + MULTI_HUB_FIX + Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. + [2:2] + read-write + + + LINESTATE_DELAY + Device/Host - add an extra 1-bit debounce of linestate sampling. + [1:1] + read-write + + + RCV_DELAY + Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. + [0:0] + read-write + + + + + INTR + 0x0000008c + Raw Interrupts + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + INTE + 0x00000090 + Interrupt Enable + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTF + 0x00000094 + Interrupt Force + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTS + 0x00000098 + Interrupt status after masking & forcing + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + SOF_TIMESTAMP_RAW + 0x00000100 + Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. + 0x00000000 + + + SOF_TIMESTAMP_RAW + [20:0] + read-only + + + + + SOF_TIMESTAMP_LAST + 0x00000104 + Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. + 0x00000000 + + + SOF_TIMESTAMP_LAST + [20:0] + read-only + + + + + SM_STATE + 0x00000108 + 0x00000000 + + + RX_DASM + [11:8] + read-only + + + BC_STATE + [7:5] + read-only + + + STATE + [4:0] + read-only + + + + + EP_TX_ERROR + 0x0000010c + TX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15 + [31:30] + read-write + oneToClear + + + EP14 + [29:28] + read-write + oneToClear + + + EP13 + [27:26] + read-write + oneToClear + + + EP12 + [25:24] + read-write + oneToClear + + + EP11 + [23:22] + read-write + oneToClear + + + EP10 + [21:20] + read-write + oneToClear + + + EP9 + [19:18] + read-write + oneToClear + + + EP8 + [17:16] + read-write + oneToClear + + + EP7 + [15:14] + read-write + oneToClear + + + EP6 + [13:12] + read-write + oneToClear + + + EP5 + [11:10] + read-write + oneToClear + + + EP4 + [9:8] + read-write + oneToClear + + + EP3 + [7:6] + read-write + oneToClear + + + EP2 + [5:4] + read-write + oneToClear + + + EP1 + [3:2] + read-write + oneToClear + + + EP0 + [1:0] + read-write + oneToClear + + + + + EP_RX_ERROR + 0x00000110 + RX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15_SEQ + [31:31] + read-write + oneToClear + + + EP15_TRANSACTION + [30:30] + read-write + oneToClear + + + EP14_SEQ + [29:29] + read-write + oneToClear + + + EP14_TRANSACTION + [28:28] + read-write + oneToClear + + + EP13_SEQ + [27:27] + read-write + oneToClear + + + EP13_TRANSACTION + [26:26] + read-write + oneToClear + + + EP12_SEQ + [25:25] + read-write + oneToClear + + + EP12_TRANSACTION + [24:24] + read-write + oneToClear + + + EP11_SEQ + [23:23] + read-write + oneToClear + + + EP11_TRANSACTION + [22:22] + read-write + oneToClear + + + EP10_SEQ + [21:21] + read-write + oneToClear + + + EP10_TRANSACTION + [20:20] + read-write + oneToClear + + + EP9_SEQ + [19:19] + read-write + oneToClear + + + EP9_TRANSACTION + [18:18] + read-write + oneToClear + + + EP8_SEQ + [17:17] + read-write + oneToClear + + + EP8_TRANSACTION + [16:16] + read-write + oneToClear + + + EP7_SEQ + [15:15] + read-write + oneToClear + + + EP7_TRANSACTION + [14:14] + read-write + oneToClear + + + EP6_SEQ + [13:13] + read-write + oneToClear + + + EP6_TRANSACTION + [12:12] + read-write + oneToClear + + + EP5_SEQ + [11:11] + read-write + oneToClear + + + EP5_TRANSACTION + [10:10] + read-write + oneToClear + + + EP4_SEQ + [9:9] + read-write + oneToClear + + + EP4_TRANSACTION + [8:8] + read-write + oneToClear + + + EP3_SEQ + [7:7] + read-write + oneToClear + + + EP3_TRANSACTION + [6:6] + read-write + oneToClear + + + EP2_SEQ + [5:5] + read-write + oneToClear + + + EP2_TRANSACTION + [4:4] + read-write + oneToClear + + + EP1_SEQ + [3:3] + read-write + oneToClear + + + EP1_TRANSACTION + [2:2] + read-write + oneToClear + + + EP0_SEQ + [1:1] + read-write + oneToClear + + + EP0_TRANSACTION + [0:0] + read-write + oneToClear + + + + + DEV_SM_WATCHDOG + 0x00000114 + Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. + Set limit while enable is low and then set the enable. + 0x00000000 + + + FIRED + [20:20] + read-write + oneToClear + + + RESET + Set to 1 to forcibly reset the device state machine on watchdog expiry + [19:19] + read-write + + + ENABLE + [18:18] + read-write + + + LIMIT + [17:0] + read-write + + + + + + + TRNG + ARM TrustZone RNG register block + 0x400f0000 + + 0 + 492 + registers + + + TRNG_IRQ + 39 + + + + RNG_IMR + 0x00000100 + Interrupt masking. + 0x0000000f + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [3:3] + read-write + + + CRNGT_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [2:2] + read-write + + + AUTOCORR_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [1:1] + read-write + + + EHR_VALID_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [0:0] + read-write + + + + + RNG_ISR + 0x00000104 + RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. + [3:3] + read-only + + + CRNGT_ERR + 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. + [2:2] + read-only + + + AUTOCORR_ERR + 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. + [1:1] + read-only + + + EHR_VALID + 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. + [0:0] + read-only + + + + + RNG_ICR + 0x00000108 + Interrupt/status bit clear Register. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [3:3] + read-write + + + CRNGT_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [2:2] + read-write + + + AUTOCORR_ERR + Cannot be cleared by SW! Only RNG reset clears this bit. + [1:1] + read-write + + + EHR_VALID + Write 1'b1 - clear corresponding bit in RNG_ISR. + [0:0] + read-write + + + + + TRNG_CONFIG + 0x0000010c + Selecting the inverter-chain length. + 0x00000000 + + + RESERVED + RESERVED + [31:2] + read-only + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). + [1:0] + read-write + + + + + TRNG_VALID + 0x00000110 + 192 bit collection indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + EHR_VALID + 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. + [0:0] + read-only + + + + + EHR_DATA0 + 0x00000114 + RNG collected bits. + 0x00000000 + + + EHR_DATA0 + Bits [31:0] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA1 + 0x00000118 + RNG collected bits. + 0x00000000 + + + EHR_DATA1 + Bits [63:32] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA2 + 0x0000011c + RNG collected bits. + 0x00000000 + + + EHR_DATA2 + Bits [95:64] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA3 + 0x00000120 + RNG collected bits. + 0x00000000 + + + EHR_DATA3 + Bits [127:96] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA4 + 0x00000124 + RNG collected bits. + 0x00000000 + + + EHR_DATA4 + Bits [159:128] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA5 + 0x00000128 + RNG collected bits. + 0x00000000 + + + EHR_DATA5 + Bits [191:160] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + RND_SOURCE_ENABLE + 0x0000012c + Enable signal for the random source. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RND_SRC_EN + * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled + [0:0] + read-write + + + + + SAMPLE_CNT1 + 0x00000130 + Counts clocks between sampling of random bit. + 0x0000ffff + + + SAMPLE_CNTR1 + Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen + [31:0] + read-write + + + + + AUTOCORR_STATISTIC + 0x00000134 + Statistic about Autocorrelation test activations. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [21:14] + read-write + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [13:0] + read-write + + + + + TRNG_DEBUG_CONTROL + 0x00000138 + Debug register. + 0x00000000 + + + AUTO_CORRELATE_BYPASS + When set, the autocorrelation test in the TRNG module is bypassed. + [3:3] + read-write + + + TRNG_CRNGT_BYPASS + When set, the CRNGT test in the RNG is bypassed. + [2:2] + read-write + + + VNC_BYPASS + When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). + [1:1] + read-write + + + RESERVED + N/A + [0:0] + read-only + + + + + TRNG_SW_RESET + 0x00000140 + Generate internal SW reset within the RNG block. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_SW_RESET + Writing 1'b1 to this register causes an internal RNG reset. + [0:0] + read-write + + + + + RNG_DEBUG_EN_INPUT + 0x000001b4 + Enable the RNG debug mode + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RNG_DEBUG_EN + * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled + [0:0] + read-write + + + + + TRNG_BUSY + 0x000001b8 + RNG Busy indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_BUSY + Reflects rng_busy status. + [0:0] + read-only + + + + + RST_BITS_COUNTER + 0x000001bc + Reset the counter of collected bits in the RNG. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RST_BITS_COUNTER + Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. + [0:0] + read-write + + + + + RNG_VERSION + 0x000001c0 + Displays the version settings of the TRNG. + 0x00000000 + + + RESERVED + RESERVED + [31:8] + read-only + + + RNG_USE_5_SBOXES + * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES + [7:7] + read-only + + + RESEEDING_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [6:6] + read-only + + + KAT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [5:5] + read-only + + + PRNG_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [4:4] + read-only + + + TRNG_TESTS_BYPASS_EN + * 1'b1 - Exists. *1'b0 - Does not exist + [3:3] + read-only + + + AUTOCORR_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [2:2] + read-only + + + CRNGT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [1:1] + read-only + + + EHR_WIDTH_192 + * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR + [0:0] + read-only + + + + + RNG_BIST_CNTR_0 + 0x000001e0 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_1 + 0x000001e4 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_2 + 0x000001e8 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + + + GLITCH_DETECTOR + Glitch detector controls + 0x40158000 + + 0 + 24 + registers + + + + ARM + 0x00000000 + Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. + + Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + + This register is Secure read/write only. + 0x00005bad + + + ARM + [15:0] + read-write + + + no + 23469 + Do not force the glitch detectors to be armed + + + yes + 0 + Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) + + + + + + + DISARM + 0x00000004 + 0x00000000 + + + DISARM + Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. + + This register is Secure read/write only. + [15:0] + read-write + + + no + 0 + Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) + + + yes + 56495 + Disarm the glitch detectors + + + + + + + SENSITIVITY + 0x00000008 + Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. + + This register is Secure read/write only. + 0x00000000 + + + DEFAULT + [31:24] + read-write + + + yes + 0 + Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) + + + no + 222 + Do not use the default sensitivity configured in OTP. Instead use the value from this register. + + + + + DET3_INV + Must be the inverse of DET3, else the default value is used. + [15:14] + read-write + + + DET2_INV + Must be the inverse of DET2, else the default value is used. + [13:12] + read-write + + + DET1_INV + Must be the inverse of DET1, else the default value is used. + [11:10] + read-write + + + DET0_INV + Must be the inverse of DET0, else the default value is used. + [9:8] + read-write + + + DET3 + Set sensitivity for detector 3. Higher values are more sensitive. + [7:6] + read-write + + + DET2 + Set sensitivity for detector 2. Higher values are more sensitive. + [5:4] + read-write + + + DET1 + Set sensitivity for detector 1. Higher values are more sensitive. + [3:2] + read-write + + + DET0 + Set sensitivity for detector 0. Higher values are more sensitive. + [1:0] + read-write + + + + + LOCK + 0x0000000c + 0x00000000 + + + LOCK + Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. + [7:0] + read-write + + + + + TRIG_STATUS + 0x00000010 + Set when a detector output triggers. Write-1-clear. + + (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) + + This register is Secure read/write only. + 0x00000000 + + + DET3 + [3:3] + read-write + oneToClear + + + DET2 + [2:2] + read-write + oneToClear + + + DET1 + [1:1] + read-write + oneToClear + + + DET0 + [0:0] + read-write + oneToClear + + + + + TRIG_FORCE + 0x00000014 + Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. + + If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. + + This register is Secure read/write only. + 0x00000000 + + + TRIG_FORCE + [3:0] + write-only + + + + + + + OTP + SNPS OTP control IF (SBPI and RPi wrapper control) + 0x40120000 + + 0 + 372 + registers + + + OTP_IRQ + 38 + + + + SW_LOCK0 + 0x00000000 + Software lock register for page 0. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK1 + 0x00000004 + Software lock register for page 1. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK2 + 0x00000008 + Software lock register for page 2. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK3 + 0x0000000c + Software lock register for page 3. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK4 + 0x00000010 + Software lock register for page 4. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK5 + 0x00000014 + Software lock register for page 5. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK6 + 0x00000018 + Software lock register for page 6. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK7 + 0x0000001c + Software lock register for page 7. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK8 + 0x00000020 + Software lock register for page 8. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK9 + 0x00000024 + Software lock register for page 9. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK10 + 0x00000028 + Software lock register for page 10. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK11 + 0x0000002c + Software lock register for page 11. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK12 + 0x00000030 + Software lock register for page 12. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK13 + 0x00000034 + Software lock register for page 13. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK14 + 0x00000038 + Software lock register for page 14. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK15 + 0x0000003c + Software lock register for page 15. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK16 + 0x00000040 + Software lock register for page 16. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK17 + 0x00000044 + Software lock register for page 17. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK18 + 0x00000048 + Software lock register for page 18. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK19 + 0x0000004c + Software lock register for page 19. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK20 + 0x00000050 + Software lock register for page 20. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK21 + 0x00000054 + Software lock register for page 21. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK22 + 0x00000058 + Software lock register for page 22. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK23 + 0x0000005c + Software lock register for page 23. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK24 + 0x00000060 + Software lock register for page 24. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK25 + 0x00000064 + Software lock register for page 25. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK26 + 0x00000068 + Software lock register for page 26. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK27 + 0x0000006c + Software lock register for page 27. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK28 + 0x00000070 + Software lock register for page 28. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK29 + 0x00000074 + Software lock register for page 29. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK30 + 0x00000078 + Software lock register for page 30. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK31 + 0x0000007c + Software lock register for page 31. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK32 + 0x00000080 + Software lock register for page 32. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK33 + 0x00000084 + Software lock register for page 33. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK34 + 0x00000088 + Software lock register for page 34. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK35 + 0x0000008c + Software lock register for page 35. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK36 + 0x00000090 + Software lock register for page 36. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK37 + 0x00000094 + Software lock register for page 37. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK38 + 0x00000098 + Software lock register for page 38. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK39 + 0x0000009c + Software lock register for page 39. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK40 + 0x000000a0 + Software lock register for page 40. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK41 + 0x000000a4 + Software lock register for page 41. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK42 + 0x000000a8 + Software lock register for page 42. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK43 + 0x000000ac + Software lock register for page 43. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK44 + 0x000000b0 + Software lock register for page 44. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK45 + 0x000000b4 + Software lock register for page 45. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK46 + 0x000000b8 + Software lock register for page 46. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK47 + 0x000000bc + Software lock register for page 47. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK48 + 0x000000c0 + Software lock register for page 48. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK49 + 0x000000c4 + Software lock register for page 49. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK50 + 0x000000c8 + Software lock register for page 50. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK51 + 0x000000cc + Software lock register for page 51. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK52 + 0x000000d0 + Software lock register for page 52. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK53 + 0x000000d4 + Software lock register for page 53. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK54 + 0x000000d8 + Software lock register for page 54. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK55 + 0x000000dc + Software lock register for page 55. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK56 + 0x000000e0 + Software lock register for page 56. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK57 + 0x000000e4 + Software lock register for page 57. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK58 + 0x000000e8 + Software lock register for page 58. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK59 + 0x000000ec + Software lock register for page 59. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK60 + 0x000000f0 + Software lock register for page 60. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK61 + 0x000000f4 + Software lock register for page 61. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK62 + 0x000000f8 + Software lock register for page 62. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK63 + 0x000000fc + Software lock register for page 63. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SBPI_INSTR + 0x00000100 + Dispatch instructions to the SBPI interface, used for programming the OTP fuses. + 0x00000000 + + + EXEC + Execute instruction + [30:30] + write-only + + + IS_WR + Payload type is write + [29:29] + read-write + + + HAS_PAYLOAD + Instruction has payload (data to be written or to be read) + [28:28] + read-write + + + PAYLOAD_SIZE_M1 + Instruction payload size in bytes minus 1 + [27:24] + read-write + + + TARGET + Instruction target, it can be PMC (0x3a) or DAP (0x02) + [23:16] + read-write + + + CMD + [15:8] + read-write + + + SHORT_WDATA + wdata to be used only when payload_size_m1=0 + [7:0] + read-write + + + + + SBPI_WDATA_0 + 0x00000104 + SBPI write payload bytes 3..0 + 0x00000000 + + + SBPI_WDATA_0 + [31:0] + read-write + + + + + SBPI_WDATA_1 + 0x00000108 + SBPI write payload bytes 7..4 + 0x00000000 + + + SBPI_WDATA_1 + [31:0] + read-write + + + + + SBPI_WDATA_2 + 0x0000010c + SBPI write payload bytes 11..8 + 0x00000000 + + + SBPI_WDATA_2 + [31:0] + read-write + + + + + SBPI_WDATA_3 + 0x00000110 + SBPI write payload bytes 15..12 + 0x00000000 + + + SBPI_WDATA_3 + [31:0] + read-write + + + + + SBPI_RDATA_0 + 0x00000114 + Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_0 + [31:0] + read-only + modify + + + + + SBPI_RDATA_1 + 0x00000118 + Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_1 + [31:0] + read-only + modify + + + + + SBPI_RDATA_2 + 0x0000011c + Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_2 + [31:0] + read-only + modify + + + + + SBPI_RDATA_3 + 0x00000120 + Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_3 + [31:0] + read-only + modify + + + + + SBPI_STATUS + 0x00000124 + 0x00000000 + + + MISO + SBPI MISO (master in - slave out): response from SBPI + [23:16] + read-only + + + FLAG + SBPI flag + [12:12] + read-only + + + INSTR_MISS + Last instruction missed (dropped), as the previous has not finished running + [8:8] + read-write + oneToClear + + + INSTR_DONE + Last instruction done + [4:4] + read-write + oneToClear + + + RDATA_VLD + Read command has returned data + [0:0] + read-write + oneToClear + + + + + USR + 0x00000128 + Controls for APB data read interface (USER interface) + 0x00000001 + + + PD + Power-down; 1 disables current reference. Must be 0 to read data from the OTP. + [4:4] + read-write + + + DCTRL + 1 enables USER interface; 0 disables USER interface (enables SBPI). + + This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. + [0:0] + read-write + + + + + DBG + 0x0000012c + Debug for OTP power-on state machine + 0x00000000 + + + CUSTOMER_RMA_FLAG + The chip is in RMA mode + [12:12] + read-only + + + PSM_STATE + Monitor the PSM FSM's state + [7:4] + read-only + + + ROSC_UP + Ring oscillator is up and running + [3:3] + read-only + + + ROSC_UP_SEEN + Ring oscillator was seen up and running + [2:2] + read-write + oneToClear + + + BOOT_DONE + PSM boot done status flag + [1:1] + read-only + + + PSM_DONE + PSM done status flag + [0:0] + read-only + + + + + BIST + 0x00000134 + During BIST, count address locations that have at least one leaky bit + 0x0fff0000 + + + CNT_FAIL + Flag if the count of address locations with at least one leaky bit exceeds cnt_max + [30:30] + read-only + + + CNT_CLR + Clear counter before use + [29:29] + write-only + + + CNT_ENA + Enable the counter before the BIST function is initiated + [28:28] + read-write + + + CNT_MAX + The cnt_fail flag will be set if the number of leaky locations exceeds this number + [27:16] + read-write + + + CNT + Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. + [12:0] + read-only + + + + + CRT_KEY_W0 + 0x00000138 + Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W0 + [31:0] + write-only + + + + + CRT_KEY_W1 + 0x0000013c + Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W1 + [31:0] + write-only + + + + + CRT_KEY_W2 + 0x00000140 + Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W2 + [31:0] + write-only + + + + + CRT_KEY_W3 + 0x00000144 + Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W3 + [31:0] + write-only + + + + + CRITICAL + 0x00000148 + Quickly check values of critical flags read during boot up + 0x00000000 + + + RISCV_DISABLE + [17:17] + read-only + + + ARM_DISABLE + [16:16] + read-only + + + GLITCH_DETECTOR_SENS + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + [4:4] + read-only + + + DEFAULT_ARCHSEL + [3:3] + read-only + + + DEBUG_DISABLE + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + [1:1] + read-only + + + SECURE_BOOT_ENABLE + [0:0] + read-only + + + + + KEY_VALID + 0x0000014c + Which keys were valid (enrolled) at boot time + 0x00000000 + + + KEY_VALID + [7:0] + read-only + + + + + DEBUGEN + 0x00000150 + Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + + Specifically: + + - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. + + - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. + + - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. + 0x00000000 + + + MISC + Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. + + These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [8:8] + read-write + + + PROC1_SECURE + Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). + + Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + [3:3] + read-write + + + PROC1 + Enable core 1's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [2:2] + read-write + + + PROC0_SECURE + Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). + + Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [1:1] + read-write + + + PROC0 + Enable core 0's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [0:0] + read-write + + + + + DEBUGEN_LOCK + 0x00000154 + Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. + 0x00000000 + + + MISC + Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. + [8:8] + read-write + + + PROC1_SECURE + Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. + [3:3] + read-write + + + PROC1 + Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. + [2:2] + read-write + + + PROC0_SECURE + Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. + [1:1] + read-write + + + PROC0 + Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. + [0:0] + read-write + + + + + ARCHSEL + 0x00000158 + Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. + + This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). + + Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. + + Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. + 0x00000000 + + + CORE1 + Select architecture for core 1. + [1:1] + read-write + + + arm + 0 + Switch core 1 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 1 to RISC-V (Hazard3) + + + + + CORE0 + Select architecture for core 0. + [0:0] + read-write + + + arm + 0 + Switch core 0 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 0 to RISC-V (Hazard3) + + + + + + + ARCHSEL_STATUS + 0x0000015c + Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. + 0x00000000 + + + CORE1 + Current architecture for core 0. Updated on processor warm reset. + [1:1] + read-only + + + arm + 0 + Core 1 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 1 is currently RISC-V (Hazard3) + + + + + CORE0 + Current architecture for core 0. Updated on processor warm reset. + [0:0] + read-only + + + arm + 0 + Core 0 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 0 is currently RISC-V (Hazard3) + + + + + + + BOOTDIS + 0x00000160 + Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the power manager BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. + [1:1] + read-write + + + NOW + When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + INTR + 0x00000164 + Raw Interrupts + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + oneToClear + + + APB_RD_SEC_FAIL + [3:3] + read-write + oneToClear + + + APB_DCTRL_FAIL + [2:2] + read-write + oneToClear + + + SBPI_WR_FAIL + [1:1] + read-write + oneToClear + + + SBPI_FLAG_N + [0:0] + read-only + + + + + INTE + 0x00000168 + Interrupt Enable + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTF + 0x0000016c + Interrupt Force + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTS + 0x00000170 + Interrupt status after masking & forcing + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-only + + + APB_RD_SEC_FAIL + [3:3] + read-only + + + APB_DCTRL_FAIL + [2:2] + read-only + + + SBPI_WR_FAIL + [1:1] + read-only + + + SBPI_FLAG_N + [0:0] + read-only + + + + + + + OTP_DATA + Predefined OTP data layout for RP2350 + 0x40130000 + + 0 + 7920 + registers + + + + CHIPID0 + 0x0000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 16 + 0x0000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + 0x0002 + Bits 31:16 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + 0x0004 + Bits 47:32 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + 0x0006 + Bits 63:48 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + 0x0008 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 16 + 0x0000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + 0x000a + Bits 31:16 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + 0x000c + Bits 47:32 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + 0x000e + Bits 63:48 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + 0x0010 + Bits 79:64 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + 0x0012 + Bits 95:80 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + 0x0014 + Bits 111:96 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + 0x0016 + Bits 127:112 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + 0x0020 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 16 + 0x0000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + 0x0022 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 16 + 0x0000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + 0x0030 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 16 + 0x0000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + 0x006c + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 16 + 0x0000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + 0x006e + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 16 + 0x0000 + + + INFO_CRC1 + [15:0] + read-only + + + + + FLASH_DEVINFO + 0x00a8 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 16 + 0x0000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x00aa + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 16 + 0x0000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x00ac + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 16 + 0x0000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x00ae + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 16 + 0x0000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x00b0 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 16 + 0x0000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x00b8 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 16 + 0x0000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x00bc + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 16 + 0x0000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + 0x00be + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 16 + 0x0000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + 0x00c0 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + 0x00c2 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + 0x0100 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + 0x0102 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + 0x0104 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + 0x0106 + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + 0x0108 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + 0x010a + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + 0x010c + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + 0x010e + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + 0x0110 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + 0x0112 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + 0x0114 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + 0x0116 + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + 0x0118 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + 0x011a + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + 0x011c + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + 0x011e + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + 0x0120 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + 0x0122 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + 0x0124 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + 0x0126 + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + 0x0128 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + 0x012a + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + 0x012c + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + 0x012e + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + 0x0130 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + 0x0132 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + 0x0134 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + 0x0136 + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + 0x0138 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + 0x013a + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + 0x013c + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + 0x013e + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + 0x0140 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + 0x0142 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + 0x0144 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + 0x0146 + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + 0x0148 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + 0x014a + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + 0x014c + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + 0x014e + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + 0x0150 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + 0x0152 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + 0x0154 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + 0x0156 + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + 0x0158 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + 0x015a + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + 0x015c + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + 0x015e + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + 0x0160 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + 0x0162 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + 0x0164 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + 0x0166 + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + 0x0168 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + 0x016a + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + 0x016c + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + 0x016e + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + 0x0170 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + 0x0172 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + 0x0174 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + 0x0176 + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + 0x0178 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + 0x017a + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + 0x017c + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + 0x017e + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + 0x1e90 + Bits 15:0 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + 0x1e92 + Bits 31:16 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + 0x1e94 + Bits 47:32 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + 0x1e96 + Bits 63:48 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + 0x1e98 + Bits 79:64 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + 0x1e9a + Bits 95:80 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + 0x1e9c + Bits 111:96 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + 0x1e9e + Bits 127:112 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + 0x1ea0 + Bits 15:0 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + 0x1ea2 + Bits 31:16 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + 0x1ea4 + Bits 47:32 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + 0x1ea6 + Bits 63:48 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + 0x1ea8 + Bits 79:64 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + 0x1eaa + Bits 95:80 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + 0x1eac + Bits 111:96 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + 0x1eae + Bits 127:112 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + 0x1eb0 + Bits 15:0 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + 0x1eb2 + Bits 31:16 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + 0x1eb4 + Bits 47:32 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + 0x1eb6 + Bits 63:48 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + 0x1eb8 + Bits 79:64 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + 0x1eba + Bits 95:80 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + 0x1ebc + Bits 111:96 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + 0x1ebe + Bits 127:112 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + 0x1ec0 + Bits 15:0 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + 0x1ec2 + Bits 31:16 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + 0x1ec4 + Bits 47:32 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + 0x1ec6 + Bits 63:48 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + 0x1ec8 + Bits 79:64 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + 0x1eca + Bits 95:80 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + 0x1ecc + Bits 111:96 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + 0x1ece + Bits 127:112 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + 0x1ed0 + Bits 15:0 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + 0x1ed2 + Bits 31:16 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + 0x1ed4 + Bits 47:32 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + 0x1ed6 + Bits 63:48 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + 0x1ed8 + Bits 79:64 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + 0x1eda + Bits 95:80 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + 0x1edc + Bits 111:96 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + 0x1ede + Bits 127:112 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + 0x1ee0 + Bits 15:0 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + 0x1ee2 + Bits 31:16 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + 0x1ee4 + Bits 47:32 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + 0x1ee6 + Bits 63:48 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + 0x1ee8 + Bits 79:64 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + 0x1eea + Bits 95:80 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + 0x1eec + Bits 111:96 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + 0x1eee + Bits 127:112 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_7 + [15:0] + read-only + + + + + + + OTP_DATA_RAW + Predefined OTP data layout for RP2350 + 0x40134000 + + 0 + 16384 + registers + + + + CHIPID0 + 0x00000000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 0x00000000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + 0x00000004 + Bits 31:16 of public device ID (ECC) + 0x00000000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + 0x00000008 + Bits 47:32 of public device ID (ECC) + 0x00000000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + 0x0000000c + Bits 63:48 of public device ID (ECC) + 0x00000000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + 0x00000010 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 0x00000000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + 0x00000014 + Bits 31:16 of private per-device random number (ECC) + 0x00000000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + 0x00000018 + Bits 47:32 of private per-device random number (ECC) + 0x00000000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + 0x0000001c + Bits 63:48 of private per-device random number (ECC) + 0x00000000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + 0x00000020 + Bits 79:64 of private per-device random number (ECC) + 0x00000000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + 0x00000024 + Bits 95:80 of private per-device random number (ECC) + 0x00000000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + 0x00000028 + Bits 111:96 of private per-device random number (ECC) + 0x00000000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + 0x0000002c + Bits 127:112 of private per-device random number (ECC) + 0x00000000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + 0x00000040 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 0x00000000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + 0x00000044 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 0x00000000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + 0x00000060 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 0x00000000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + 0x000000d8 + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 0x00000000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + 0x000000dc + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 0x00000000 + + + INFO_CRC1 + [15:0] + read-only + + + + + CRIT0 + 0x000000e0 + Page 0 critical boot flags (RBIT-8) + 0x00000000 + + + RISCV_DISABLE + Permanently disable RISC-V processors (Hazard3) + [1:1] + read-only + + + ARM_DISABLE + Permanently disable ARM processors (Cortex-M33) + [0:0] + read-only + + + + + CRIT0_R1 + 0x000000e4 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R1 + [23:0] + read-only + + + + + CRIT0_R2 + 0x000000e8 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R2 + [23:0] + read-only + + + + + CRIT0_R3 + 0x000000ec + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R3 + [23:0] + read-only + + + + + CRIT0_R4 + 0x000000f0 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R4 + [23:0] + read-only + + + + + CRIT0_R5 + 0x000000f4 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R5 + [23:0] + read-only + + + + + CRIT0_R6 + 0x000000f8 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R6 + [23:0] + read-only + + + + + CRIT0_R7 + 0x000000fc + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R7 + [23:0] + read-only + + + + + CRIT1 + 0x00000100 + Page 1 critical boot flags (RBIT-8) + 0x00000000 + + + GLITCH_DETECTOR_SENS + Increase the sensitivity of the glitch detectors from their default. + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. + [4:4] + read-only + + + BOOT_ARCH + Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. + [3:3] + read-only + + + DEBUG_DISABLE + Disable all debug access + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + Disable Secure debug access + [1:1] + read-only + + + SECURE_BOOT_ENABLE + Enable boot signature enforcement, and permanently disable the RISC-V cores. + [0:0] + read-only + + + + + CRIT1_R1 + 0x00000104 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R1 + [23:0] + read-only + + + + + CRIT1_R2 + 0x00000108 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R2 + [23:0] + read-only + + + + + CRIT1_R3 + 0x0000010c + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R3 + [23:0] + read-only + + + + + CRIT1_R4 + 0x00000110 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R4 + [23:0] + read-only + + + + + CRIT1_R5 + 0x00000114 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R5 + [23:0] + read-only + + + + + CRIT1_R6 + 0x00000118 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R6 + [23:0] + read-only + + + + + CRIT1_R7 + 0x0000011c + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R7 + [23:0] + read-only + + + + + BOOT_FLAGS0 + 0x00000120 + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x00000000 + + + DISABLE_SRAM_WINDOW_BOOT + [21:21] + read-only + + + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY + Disable all access to XIP after entering an SRAM binary. + + Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. + [20:20] + read-only + + + DISABLE_BOOTSEL_UART_BOOT + [19:19] + read-only + + + DISABLE_BOOTSEL_USB_PICOBOOT_IFC + [18:18] + read-only + + + DISABLE_BOOTSEL_USB_MSD_IFC + [17:17] + read-only + + + DISABLE_WATCHDOG_SCRATCH + [16:16] + read-only + + + DISABLE_POWER_SCRATCH + [15:15] + read-only + + + ENABLE_OTP_BOOT + Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. + + The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. + + Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. + [14:14] + read-only + + + DISABLE_OTP_BOOT + Takes precedence over ENABLE_OTP_BOOT. + [13:13] + read-only + + + DISABLE_FLASH_BOOT + [12:12] + read-only + + + ROLLBACK_REQUIRED + Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. + [11:11] + read-only + + + HASHED_PARTITION_TABLE + Require a partition table to be hashed (if not signed) + [10:10] + read-only + + + SECURE_PARTITION_TABLE + Require a partition table to be signed + [9:9] + read-only + + + DISABLE_AUTO_SWITCH_ARCH + Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled + [8:8] + read-only + + + SINGLE_FLASH_BINARY + Restrict flash boot path to use of a single binary at the start of flash + [7:7] + read-only + + + OVERRIDE_FLASH_PARTITION_SLOT_SIZE + Override the limit for default flash metadata scanning. + + The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit + [6:6] + read-only + + + FLASH_DEVINFO_ENABLE + Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. + [5:5] + read-only + + + FAST_SIGCHECK_ROSC_DIV + Enable quartering of ROSC divisor during signature check, to reduce secure boot time + [4:4] + read-only + + + FLASH_IO_VOLTAGE_1V8 + If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. + + If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) + [3:3] + read-only + + + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG + Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. + + Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. + + If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. + [2:2] + read-only + + + ENABLE_BOOTSEL_LED + Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid + [1:1] + read-only + + + DISABLE_BOOTSEL_EXEC2 + [0:0] + read-only + + + + + BOOT_FLAGS0_R1 + 0x00000124 + Redundant copy of BOOT_FLAGS0 + 0x00000000 + + + BOOT_FLAGS0_R1 + [23:0] + read-only + + + + + BOOT_FLAGS0_R2 + 0x00000128 + Redundant copy of BOOT_FLAGS0 + 0x00000000 + + + BOOT_FLAGS0_R2 + [23:0] + read-only + + + + + BOOT_FLAGS1 + 0x0000012c + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x00000000 + + + DOUBLE_TAP + Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. + + This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. + [19:19] + read-only + + + DOUBLE_TAP_DELAY + Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. + + For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. + + 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. + [18:16] + read-only + + + KEY_INVALID + Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. + [11:8] + read-only + + + KEY_VALID + Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. + + Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. + + Do not enable secure boot without first installing a valid key. This will render your device unbootable. + [3:0] + read-only + + + + + BOOT_FLAGS1_R1 + 0x00000130 + Redundant copy of BOOT_FLAGS1 + 0x00000000 + + + BOOT_FLAGS1_R1 + [23:0] + read-only + + + + + BOOT_FLAGS1_R2 + 0x00000134 + Redundant copy of BOOT_FLAGS1 + 0x00000000 + + + BOOT_FLAGS1_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0 + 0x00000138 + Default boot version thermometer counter, bits 23:0 (RBIT-3) + 0x00000000 + + + DEFAULT_BOOT_VERSION0 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R1 + 0x0000013c + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R2 + 0x00000140 + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1 + 0x00000144 + Default boot version thermometer counter, bits 47:24 (RBIT-3) + 0x00000000 + + + DEFAULT_BOOT_VERSION1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R1 + 0x00000148 + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R2 + 0x0000014c + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R2 + [23:0] + read-only + + + + + FLASH_DEVINFO + 0x00000150 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 0x00000000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x00000154 + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 0x00000000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x00000158 + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 0x00000000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x0000015c + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 0x00000000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x00000160 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 0x00000000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_BOOT_FLAGS + 0x00000164 + USB boot specific feature flags (RBIT-3) + 0x00000000 + + + DP_DM_SWAP + Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). + [23:23] + read-only + + + WHITE_LABEL_ADDR_VALID + valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) + [22:22] + read-only + + + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID + valid flag for the USB_WHITE_LABEL_ADDR field + [15:15] + read-only + + + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID + valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) + [14:14] + read-only + + + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) + [13:13] + read-only + + + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) + [12:12] + read-only + + + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID + valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) + [11:11] + read-only + + + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID + valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) + [10:10] + read-only + + + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID + valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) + [9:9] + read-only + + + WL_VOLUME_LABEL_STRDEF_VALID + valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) + [8:8] + read-only + + + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID + valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) + [7:7] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID + valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) + [6:6] + read-only + + + WL_USB_DEVICE_PRODUCT_STRDEF_VALID + valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) + [5:5] + read-only + + + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID + valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) + [4:4] + read-only + + + WL_USB_DEVICE_LANG_ID_VALUE_VALID + valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) + [3:3] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID + valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) + [2:2] + read-only + + + WL_USB_DEVICE_PID_VALUE_VALID + valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) + [1:1] + read-only + + + WL_USB_DEVICE_VID_VALUE_VALID + valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) + [0:0] + read-only + + + + + USB_BOOT_FLAGS_R1 + 0x00000168 + Redundant copy of USB_BOOT_FLAGS + 0x00000000 + + + USB_BOOT_FLAGS_R1 + [23:0] + read-only + + + + + USB_BOOT_FLAGS_R2 + 0x0000016c + Redundant copy of USB_BOOT_FLAGS + 0x00000000 + + + USB_BOOT_FLAGS_R2 + [23:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x00000170 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 0x00000000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x00000178 + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 0x00000000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + 0x0000017c + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 0x00000000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + 0x00000180 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x00000000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + 0x00000184 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x00000000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + 0x00000200 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + 0x00000204 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + 0x00000208 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + 0x0000020c + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + 0x00000210 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + 0x00000214 + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + 0x00000218 + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + 0x0000021c + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + 0x00000220 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + 0x00000224 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + 0x00000228 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + 0x0000022c + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + 0x00000230 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + 0x00000234 + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + 0x00000238 + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + 0x0000023c + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + 0x00000240 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + 0x00000244 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + 0x00000248 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + 0x0000024c + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + 0x00000250 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + 0x00000254 + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + 0x00000258 + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + 0x0000025c + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + 0x00000260 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + 0x00000264 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + 0x00000268 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + 0x0000026c + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + 0x00000270 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + 0x00000274 + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + 0x00000278 + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + 0x0000027c + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + 0x00000280 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + 0x00000284 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + 0x00000288 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + 0x0000028c + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + 0x00000290 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + 0x00000294 + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + 0x00000298 + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + 0x0000029c + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + 0x000002a0 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + 0x000002a4 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + 0x000002a8 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + 0x000002ac + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + 0x000002b0 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + 0x000002b4 + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + 0x000002b8 + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + 0x000002bc + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + 0x000002c0 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + 0x000002c4 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + 0x000002c8 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + 0x000002cc + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + 0x000002d0 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + 0x000002d4 + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + 0x000002d8 + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + 0x000002dc + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + 0x000002e0 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + 0x000002e4 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + 0x000002e8 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + 0x000002ec + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + 0x000002f0 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + 0x000002f4 + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + 0x000002f8 + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + 0x000002fc + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + 0x00003d20 + Bits 15:0 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + 0x00003d24 + Bits 31:16 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + 0x00003d28 + Bits 47:32 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + 0x00003d2c + Bits 63:48 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + 0x00003d30 + Bits 79:64 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + 0x00003d34 + Bits 95:80 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + 0x00003d38 + Bits 111:96 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + 0x00003d3c + Bits 127:112 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + 0x00003d40 + Bits 15:0 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + 0x00003d44 + Bits 31:16 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + 0x00003d48 + Bits 47:32 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + 0x00003d4c + Bits 63:48 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + 0x00003d50 + Bits 79:64 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + 0x00003d54 + Bits 95:80 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + 0x00003d58 + Bits 111:96 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + 0x00003d5c + Bits 127:112 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + 0x00003d60 + Bits 15:0 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + 0x00003d64 + Bits 31:16 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + 0x00003d68 + Bits 47:32 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + 0x00003d6c + Bits 63:48 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + 0x00003d70 + Bits 79:64 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + 0x00003d74 + Bits 95:80 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + 0x00003d78 + Bits 111:96 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + 0x00003d7c + Bits 127:112 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + 0x00003d80 + Bits 15:0 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + 0x00003d84 + Bits 31:16 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + 0x00003d88 + Bits 47:32 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + 0x00003d8c + Bits 63:48 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + 0x00003d90 + Bits 79:64 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + 0x00003d94 + Bits 95:80 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + 0x00003d98 + Bits 111:96 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + 0x00003d9c + Bits 127:112 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + 0x00003da0 + Bits 15:0 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + 0x00003da4 + Bits 31:16 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + 0x00003da8 + Bits 47:32 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + 0x00003dac + Bits 63:48 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + 0x00003db0 + Bits 79:64 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + 0x00003db4 + Bits 95:80 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + 0x00003db8 + Bits 111:96 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + 0x00003dbc + Bits 127:112 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + 0x00003dc0 + Bits 15:0 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + 0x00003dc4 + Bits 31:16 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + 0x00003dc8 + Bits 47:32 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + 0x00003dcc + Bits 63:48 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + 0x00003dd0 + Bits 79:64 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + 0x00003dd4 + Bits 95:80 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + 0x00003dd8 + Bits 111:96 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + 0x00003ddc + Bits 127:112 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_7 + [15:0] + read-only + + + + + KEY1_VALID + 0x00003de4 + Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY2_VALID + 0x00003de8 + Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY3_VALID + 0x00003dec + Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY4_VALID + 0x00003df0 + Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY5_VALID + 0x00003df4 + Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY6_VALID + 0x00003df8 + Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + PAGE0_LOCK0 + 0x00003e00 + Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE0_LOCK1 + 0x00003e04 + Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE1_LOCK0 + 0x00003e08 + Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE1_LOCK1 + 0x00003e0c + Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE2_LOCK0 + 0x00003e10 + Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE2_LOCK1 + 0x00003e14 + Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE3_LOCK0 + 0x00003e18 + Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE3_LOCK1 + 0x00003e1c + Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE4_LOCK0 + 0x00003e20 + Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE4_LOCK1 + 0x00003e24 + Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE5_LOCK0 + 0x00003e28 + Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE5_LOCK1 + 0x00003e2c + Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE6_LOCK0 + 0x00003e30 + Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE6_LOCK1 + 0x00003e34 + Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE7_LOCK0 + 0x00003e38 + Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE7_LOCK1 + 0x00003e3c + Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE8_LOCK0 + 0x00003e40 + Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE8_LOCK1 + 0x00003e44 + Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE9_LOCK0 + 0x00003e48 + Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE9_LOCK1 + 0x00003e4c + Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE10_LOCK0 + 0x00003e50 + Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE10_LOCK1 + 0x00003e54 + Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE11_LOCK0 + 0x00003e58 + Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE11_LOCK1 + 0x00003e5c + Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE12_LOCK0 + 0x00003e60 + Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE12_LOCK1 + 0x00003e64 + Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE13_LOCK0 + 0x00003e68 + Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE13_LOCK1 + 0x00003e6c + Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE14_LOCK0 + 0x00003e70 + Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE14_LOCK1 + 0x00003e74 + Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE15_LOCK0 + 0x00003e78 + Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE15_LOCK1 + 0x00003e7c + Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE16_LOCK0 + 0x00003e80 + Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE16_LOCK1 + 0x00003e84 + Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE17_LOCK0 + 0x00003e88 + Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE17_LOCK1 + 0x00003e8c + Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE18_LOCK0 + 0x00003e90 + Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE18_LOCK1 + 0x00003e94 + Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE19_LOCK0 + 0x00003e98 + Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE19_LOCK1 + 0x00003e9c + Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE20_LOCK0 + 0x00003ea0 + Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE20_LOCK1 + 0x00003ea4 + Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE21_LOCK0 + 0x00003ea8 + Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE21_LOCK1 + 0x00003eac + Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE22_LOCK0 + 0x00003eb0 + Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE22_LOCK1 + 0x00003eb4 + Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE23_LOCK0 + 0x00003eb8 + Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE23_LOCK1 + 0x00003ebc + Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE24_LOCK0 + 0x00003ec0 + Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE24_LOCK1 + 0x00003ec4 + Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE25_LOCK0 + 0x00003ec8 + Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE25_LOCK1 + 0x00003ecc + Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE26_LOCK0 + 0x00003ed0 + Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE26_LOCK1 + 0x00003ed4 + Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE27_LOCK0 + 0x00003ed8 + Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE27_LOCK1 + 0x00003edc + Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE28_LOCK0 + 0x00003ee0 + Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE28_LOCK1 + 0x00003ee4 + Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE29_LOCK0 + 0x00003ee8 + Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE29_LOCK1 + 0x00003eec + Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE30_LOCK0 + 0x00003ef0 + Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE30_LOCK1 + 0x00003ef4 + Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE31_LOCK0 + 0x00003ef8 + Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE31_LOCK1 + 0x00003efc + Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE32_LOCK0 + 0x00003f00 + Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE32_LOCK1 + 0x00003f04 + Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE33_LOCK0 + 0x00003f08 + Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE33_LOCK1 + 0x00003f0c + Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE34_LOCK0 + 0x00003f10 + Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE34_LOCK1 + 0x00003f14 + Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE35_LOCK0 + 0x00003f18 + Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE35_LOCK1 + 0x00003f1c + Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE36_LOCK0 + 0x00003f20 + Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE36_LOCK1 + 0x00003f24 + Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE37_LOCK0 + 0x00003f28 + Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE37_LOCK1 + 0x00003f2c + Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE38_LOCK0 + 0x00003f30 + Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE38_LOCK1 + 0x00003f34 + Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE39_LOCK0 + 0x00003f38 + Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE39_LOCK1 + 0x00003f3c + Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE40_LOCK0 + 0x00003f40 + Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE40_LOCK1 + 0x00003f44 + Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE41_LOCK0 + 0x00003f48 + Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE41_LOCK1 + 0x00003f4c + Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE42_LOCK0 + 0x00003f50 + Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE42_LOCK1 + 0x00003f54 + Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE43_LOCK0 + 0x00003f58 + Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE43_LOCK1 + 0x00003f5c + Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE44_LOCK0 + 0x00003f60 + Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE44_LOCK1 + 0x00003f64 + Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE45_LOCK0 + 0x00003f68 + Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE45_LOCK1 + 0x00003f6c + Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE46_LOCK0 + 0x00003f70 + Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE46_LOCK1 + 0x00003f74 + Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE47_LOCK0 + 0x00003f78 + Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE47_LOCK1 + 0x00003f7c + Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE48_LOCK0 + 0x00003f80 + Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE48_LOCK1 + 0x00003f84 + Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE49_LOCK0 + 0x00003f88 + Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE49_LOCK1 + 0x00003f8c + Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE50_LOCK0 + 0x00003f90 + Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE50_LOCK1 + 0x00003f94 + Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE51_LOCK0 + 0x00003f98 + Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE51_LOCK1 + 0x00003f9c + Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE52_LOCK0 + 0x00003fa0 + Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE52_LOCK1 + 0x00003fa4 + Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE53_LOCK0 + 0x00003fa8 + Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE53_LOCK1 + 0x00003fac + Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE54_LOCK0 + 0x00003fb0 + Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE54_LOCK1 + 0x00003fb4 + Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE55_LOCK0 + 0x00003fb8 + Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE55_LOCK1 + 0x00003fbc + Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE56_LOCK0 + 0x00003fc0 + Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE56_LOCK1 + 0x00003fc4 + Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE57_LOCK0 + 0x00003fc8 + Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE57_LOCK1 + 0x00003fcc + Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE58_LOCK0 + 0x00003fd0 + Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE58_LOCK1 + 0x00003fd4 + Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE59_LOCK0 + 0x00003fd8 + Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE59_LOCK1 + 0x00003fdc + Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE60_LOCK0 + 0x00003fe0 + Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE60_LOCK1 + 0x00003fe4 + Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE61_LOCK0 + 0x00003fe8 + Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE61_LOCK1 + 0x00003fec + Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE62_LOCK0 + 0x00003ff0 + Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE62_LOCK1 + 0x00003ff4 + Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE63_LOCK0 + 0x00003ff8 + Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + RMA + Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. + [7:7] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE63_LOCK1 + 0x00003ffc + Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + + + TBMAN + For managing simulation testbenches + 0x40160000 + + 0 + 4 + registers + + + + PLATFORM + 0x00000000 + Indicates the type of platform in use + 0x00000001 + + + HDLSIM + Indicates the platform is a simulation + [2:2] + read-only + + + FPGA + Indicates the platform is an FPGA + [1:1] + read-only + + + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + USB_DPRAM + DPRAM layout for USB device. + 0x50100000 + + 0 + 256 + registers + + + + SETUP_PACKET_LOW + 0x00000000 + Bytes 0-3 of the SETUP packet from the host. + 0x00000000 + + + WVALUE + [31:16] + read-write + + + BREQUEST + [15:8] + read-write + + + BMREQUESTTYPE + [7:0] + read-write + + + + + SETUP_PACKET_HIGH + 0x00000004 + Bytes 4-7 of the setup packet from the host. + 0x00000000 + + + WLENGTH + [31:16] + read-write + + + WINDEX + [15:0] + read-write + + + + + EP1_IN_CONTROL + 0x00000008 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP1_OUT_CONTROL + 0x0000000c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_IN_CONTROL + 0x00000010 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_OUT_CONTROL + 0x00000014 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_IN_CONTROL + 0x00000018 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_OUT_CONTROL + 0x0000001c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_IN_CONTROL + 0x00000020 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_OUT_CONTROL + 0x00000024 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_IN_CONTROL + 0x00000028 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_OUT_CONTROL + 0x0000002c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_IN_CONTROL + 0x00000030 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_OUT_CONTROL + 0x00000034 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_IN_CONTROL + 0x00000038 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_OUT_CONTROL + 0x0000003c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_IN_CONTROL + 0x00000040 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_OUT_CONTROL + 0x00000044 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_IN_CONTROL + 0x00000048 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_OUT_CONTROL + 0x0000004c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_IN_CONTROL + 0x00000050 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_OUT_CONTROL + 0x00000054 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_IN_CONTROL + 0x00000058 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_OUT_CONTROL + 0x0000005c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_IN_CONTROL + 0x00000060 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_OUT_CONTROL + 0x00000064 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_IN_CONTROL + 0x00000068 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_OUT_CONTROL + 0x0000006c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_IN_CONTROL + 0x00000070 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_OUT_CONTROL + 0x00000074 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_IN_CONTROL + 0x00000078 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_OUT_CONTROL + 0x0000007c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP0_IN_BUFFER_CONTROL + 0x00000080 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP0_OUT_BUFFER_CONTROL + 0x00000084 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_IN_BUFFER_CONTROL + 0x00000088 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_OUT_BUFFER_CONTROL + 0x0000008c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_IN_BUFFER_CONTROL + 0x00000090 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_OUT_BUFFER_CONTROL + 0x00000094 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_IN_BUFFER_CONTROL + 0x00000098 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_OUT_BUFFER_CONTROL + 0x0000009c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_IN_BUFFER_CONTROL + 0x000000a0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_OUT_BUFFER_CONTROL + 0x000000a4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_IN_BUFFER_CONTROL + 0x000000a8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_OUT_BUFFER_CONTROL + 0x000000ac + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_IN_BUFFER_CONTROL + 0x000000b0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_OUT_BUFFER_CONTROL + 0x000000b4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_IN_BUFFER_CONTROL + 0x000000b8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_OUT_BUFFER_CONTROL + 0x000000bc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_IN_BUFFER_CONTROL + 0x000000c0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_OUT_BUFFER_CONTROL + 0x000000c4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_IN_BUFFER_CONTROL + 0x000000c8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_OUT_BUFFER_CONTROL + 0x000000cc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_IN_BUFFER_CONTROL + 0x000000d0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_OUT_BUFFER_CONTROL + 0x000000d4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_IN_BUFFER_CONTROL + 0x000000d8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_OUT_BUFFER_CONTROL + 0x000000dc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_IN_BUFFER_CONTROL + 0x000000e0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_OUT_BUFFER_CONTROL + 0x000000e4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_IN_BUFFER_CONTROL + 0x000000e8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_OUT_BUFFER_CONTROL + 0x000000ec + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_IN_BUFFER_CONTROL + 0x000000f0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_OUT_BUFFER_CONTROL + 0x000000f4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_IN_BUFFER_CONTROL + 0x000000f8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_OUT_BUFFER_CONTROL + 0x000000fc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + + + diff --git a/src/rp2350/hardware_regs/include/hardware/platform_defs.h b/src/rp2350/hardware_regs/include/hardware/platform_defs.h new file mode 100644 index 000000000..8ea4fadfb --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/platform_defs.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLATFORM_DEFS_H +#define _HARDWARE_PLATFORM_DEFS_H + +// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__ + +#ifndef _u +#ifdef __ASSEMBLER__ +#define _u(x) x +#else +#define _u(x) x ## u +#endif +#endif + +#define NUM_CORES _u(2) +#define NUM_DMA_CHANNELS _u(16) +#define NUM_DMA_TIMERS _u(4) +#define NUM_DMA_MPU_REGIONS _u(8) +#define NUM_DMA_IRQS _u(4) +#define NUM_IRQS _u(52) +#define NUM_USER_IRQS _u(6) +#define NUM_PIOS _u(3) +#define NUM_PIO_STATE_MACHINES _u(4) +#define NUM_PIO_IRQS _u(2) +#define NUM_PWM_SLICES _u(12) +#define NUM_PWM_IRQS _u(2) +#define NUM_SPIN_LOCKS _u(32) +#define NUM_UARTS _u(2) +#define NUM_I2CS _u(2) +#define NUM_SPIS _u(2) +#define NUM_GENERIC_TIMERS _u(2) +#define NUM_ALARMS _u(4) +#if PICO_RP2350A +#define NUM_ADC_CHANNELS _u(5) +#define ADC_BASE_PIN _u(26) +#else +#define NUM_ADC_CHANNELS _u(9) +#define ADC_BASE_PIN _u(40) +#endif +#define NUM_RESETS _u(28) +#define NUM_DOORBELLS _u(8) + +#if PICO_RP2350A +#define NUM_BANK0_GPIOS _u(30) +#else +#define NUM_BANK0_GPIOS _u(48) +#endif +#define NUM_QSPI_GPIOS _u(6) + +#define NUM_OTP_PAGES _u(64) +#define NUM_OTP_PAGE_ROWS _u(64) +#define NUM_OTP_ROWS (NUM_OTP_PAGES * NUM_OTP_PAGE_ROWS) + +#define PIO_INSTRUCTION_COUNT _u(32) + +#define NUM_MPU_REGIONS _u(8) +#define NUM_SAU_REGIONS _u(8) +#define NUM_BOOT_LOCKS _u(8) + +#define BOOTRAM_SIZE _u(0x400) +#define USBCTRL_DPRAM_SIZE _u(4096) + +#ifndef __riscv +#define HAS_GPIO_COPROCESSOR 1 +#define HAS_DOUBLE_COPROCESSOR 1 +#define HAS_REDUNDANCY_COPROCESSOR 1 +#endif +#define HAS_POWMAN_TIMER 1 +#define HAS_RP2350_TRNG 1 +#define HAS_HSTX 1 + +// PICO_CONFIG: XOSC_HZ, The crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base +// NOTE: The system and USB clocks are generated from the frequency using two PLLs. +// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to +// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h +// Please see the comments there about calculating the new PLL setting values. +#ifndef XOSC_HZ +#ifdef XOSC_KHZ +#define XOSC_HZ ((XOSC_KHZ) * _u(1000)) +#elif defined(XOSC_MHZ) +#define XOSC_HZ ((XOSC_MHZ) * _u(1000000)) +#else +#define XOSC_HZ _u(12000000) +#endif +#endif + +// PICO_CONFIG: SYS_CLK_HZ, The system operating frequency in Hz, type=int, default=150000000, advanced=true, group=hardware_base +#ifndef SYS_CLK_HZ +#ifdef SYS_CLK_KHZ +#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000)) +#elif defined(SYS_CLK_MHZ) +#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000)) +#else +#define SYS_CLK_HZ _u(150000000) +#endif +#endif + +// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base +#ifndef USB_CLK_HZ +#ifdef USB_CLK_KHZ +#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000)) +#elif defined(USB_CLK_MHZ) +#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000)) +#else +#define USB_CLK_HZ _u(48000000) +#endif +#endif + +// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz. +#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0) +#define XOSC_KHZ (XOSC_HZ / 1000) +#endif + +// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0) +#define XOSC_MHZ (XOSC_KHZ / 1000) +#endif + +// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0) +#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000) +#endif + +// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0) +#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000) +#endif + +// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0) +#define USB_CLK_KHZ (USB_CLK_HZ / 1000) +#endif + +// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0) +#define USB_CLK_MHZ (USB_CLK_KHZ / 1000) +#endif + +#define ACCESSCTRL_PASSWORD_BITS _u(0xacce0000) +#define POWMAN_PASSWORD_BITS _u(0x5afe0000) + +#ifdef __riscv +// Note the soft-table dispatch code is between the hard and soft vector +// tables, as it's inlined into the last slot of the hard table: +#if defined(__riscv_c) || defined(__riscv_zca) +// RISC-V with compressed instructions: NOTE that this is dependent on the size of the code in crt0_riscv.S +#define VTABLE_FIRST_IRQ 0x34 +#else +// RISC-V without compressed instructions: +#define VTABLE_FIRST_IRQ 0x48 +#endif +#else +// Armv8-M: +#define VTABLE_FIRST_IRQ 16 +#endif +#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS) + +#endif diff --git a/src/rp2350/hardware_regs/include/hardware/regs/accessctrl.h b/src/rp2350/hardware_regs/include/hardware/regs/accessctrl.h new file mode 100644 index 000000000..2b8c4ca1f --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/accessctrl.h @@ -0,0 +1,4953 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ACCESSCTRL +// Version : 1 +// Bus type : apb +// Description : Hardware access control registers +// ============================================================================= +#ifndef _HARDWARE_REGS_ACCESSCTRL_H +#define _HARDWARE_REGS_ACCESSCTRL_H +// ============================================================================= +// Register : ACCESSCTRL_LOCK +// Description : Once a LOCK bit is written to 1, ACCESSCTRL silently ignores +// writes from that master. LOCK is writable only by a Secure, +// Privileged processor or debugger. +// +// LOCK bits are only writable when their value is zero. Once set, +// they can never be cleared, except by a full reset of ACCESSCTRL +// +// Setting the LOCK bit does not affect whether an access raises a +// bus error. Unprivileged writes, or writes from the DMA, will +// continue to raise bus errors. All other accesses will continue +// not to. +#define ACCESSCTRL_LOCK_OFFSET _u(0x00000000) +#define ACCESSCTRL_LOCK_BITS _u(0x0000000f) +#define ACCESSCTRL_LOCK_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_DEBUG +#define ACCESSCTRL_LOCK_DEBUG_RESET _u(0x0) +#define ACCESSCTRL_LOCK_DEBUG_BITS _u(0x00000008) +#define ACCESSCTRL_LOCK_DEBUG_MSB _u(3) +#define ACCESSCTRL_LOCK_DEBUG_LSB _u(3) +#define ACCESSCTRL_LOCK_DEBUG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_DMA +#define ACCESSCTRL_LOCK_DMA_RESET _u(0x1) +#define ACCESSCTRL_LOCK_DMA_BITS _u(0x00000004) +#define ACCESSCTRL_LOCK_DMA_MSB _u(2) +#define ACCESSCTRL_LOCK_DMA_LSB _u(2) +#define ACCESSCTRL_LOCK_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_CORE1 +#define ACCESSCTRL_LOCK_CORE1_RESET _u(0x0) +#define ACCESSCTRL_LOCK_CORE1_BITS _u(0x00000002) +#define ACCESSCTRL_LOCK_CORE1_MSB _u(1) +#define ACCESSCTRL_LOCK_CORE1_LSB _u(1) +#define ACCESSCTRL_LOCK_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_CORE0 +#define ACCESSCTRL_LOCK_CORE0_RESET _u(0x0) +#define ACCESSCTRL_LOCK_CORE0_BITS _u(0x00000001) +#define ACCESSCTRL_LOCK_CORE0_MSB _u(0) +#define ACCESSCTRL_LOCK_CORE0_LSB _u(0) +#define ACCESSCTRL_LOCK_CORE0_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_FORCE_CORE_NS +// Description : Force core 1's bus accesses to always be Non-secure, no matter +// the core's internal state. +// +// Useful for schemes where one core is designated as the Non- +// secure core, since some peripherals may filter individual +// registers internally based on security state but not on master +// ID. +#define ACCESSCTRL_FORCE_CORE_NS_OFFSET _u(0x00000004) +#define ACCESSCTRL_FORCE_CORE_NS_BITS _u(0x00000002) +#define ACCESSCTRL_FORCE_CORE_NS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_FORCE_CORE_NS_CORE1 +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_RESET _u(0x0) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_BITS _u(0x00000002) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_MSB _u(1) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_LSB _u(1) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CFGRESET +// Description : Write 1 to reset all ACCESSCTRL configuration, except for the +// LOCK and FORCE_CORE_NS registers. +// +// This bit is used in the RP2350 bootrom to quickly restore +// ACCESSCTRL to a known state during the boot path. +// +// Note that, like all registers in ACCESSCTRL, this register is +// not writable when the writer's corresponding LOCK bit is set, +// therefore a master which has been locked out of ACCESSCTRL can +// not use the CFGRESET register to disturb its contents. +#define ACCESSCTRL_CFGRESET_OFFSET _u(0x00000008) +#define ACCESSCTRL_CFGRESET_BITS _u(0x00000001) +#define ACCESSCTRL_CFGRESET_RESET _u(0x00000000) +#define ACCESSCTRL_CFGRESET_MSB _u(0) +#define ACCESSCTRL_CFGRESET_LSB _u(0) +#define ACCESSCTRL_CFGRESET_ACCESS "SC" +// ============================================================================= +// Register : ACCESSCTRL_GPIO_NSMASK0 +// Description : Control whether GPIO0...31 are accessible to Non-secure code. +// Writable only by a Secure, Privileged processor or debugger. +// +// 0 -> Secure access only +// +// 1 -> Secure + Non-secure access +#define ACCESSCTRL_GPIO_NSMASK0_OFFSET _u(0x0000000c) +#define ACCESSCTRL_GPIO_NSMASK0_BITS _u(0xffffffff) +#define ACCESSCTRL_GPIO_NSMASK0_RESET _u(0x00000000) +#define ACCESSCTRL_GPIO_NSMASK0_MSB _u(31) +#define ACCESSCTRL_GPIO_NSMASK0_LSB _u(0) +#define ACCESSCTRL_GPIO_NSMASK0_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_GPIO_NSMASK1 +// Description : Control whether GPIO32..47 are accessible to Non-secure code, +// and whether QSPI and USB bitbang are accessible through the +// Non-secure SIO. Writable only by a Secure, Privileged processor +// or debugger. +#define ACCESSCTRL_GPIO_NSMASK1_OFFSET _u(0x00000010) +#define ACCESSCTRL_GPIO_NSMASK1_BITS _u(0xff00ffff) +#define ACCESSCTRL_GPIO_NSMASK1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_SD +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_BITS _u(0xf0000000) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_MSB _u(31) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_LSB _u(28) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_BITS _u(0x08000000) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_MSB _u(27) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_LSB _u(27) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_BITS _u(0x04000000) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_MSB _u(26) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_LSB _u(26) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_USB_DM +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_BITS _u(0x02000000) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_MSB _u(25) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_LSB _u(25) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_USB_DP +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_BITS _u(0x01000000) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_MSB _u(24) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_LSB _u(24) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_GPIO +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_RESET _u(0x0000) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_BITS _u(0x0000ffff) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_MSB _u(15) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_LSB _u(0) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_ROM +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// ROM, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_ROM_OFFSET _u(0x00000014) +#define ACCESSCTRL_ROM_BITS _u(0x000000ff) +#define ACCESSCTRL_ROM_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_DBG +// Description : If 1, ROM can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_ROM_DBG_RESET _u(0x1) +#define ACCESSCTRL_ROM_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_ROM_DBG_MSB _u(7) +#define ACCESSCTRL_ROM_DBG_LSB _u(7) +#define ACCESSCTRL_ROM_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_DMA +// Description : If 1, ROM can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROM_DMA_RESET _u(0x1) +#define ACCESSCTRL_ROM_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_ROM_DMA_MSB _u(6) +#define ACCESSCTRL_ROM_DMA_LSB _u(6) +#define ACCESSCTRL_ROM_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_CORE1 +// Description : If 1, ROM can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROM_CORE1_RESET _u(0x1) +#define ACCESSCTRL_ROM_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_ROM_CORE1_MSB _u(5) +#define ACCESSCTRL_ROM_CORE1_LSB _u(5) +#define ACCESSCTRL_ROM_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_CORE0 +// Description : If 1, ROM can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROM_CORE0_RESET _u(0x1) +#define ACCESSCTRL_ROM_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_ROM_CORE0_MSB _u(4) +#define ACCESSCTRL_ROM_CORE0_LSB _u(4) +#define ACCESSCTRL_ROM_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_SP +// Description : If 1, ROM can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_ROM_SP_RESET _u(0x1) +#define ACCESSCTRL_ROM_SP_BITS _u(0x00000008) +#define ACCESSCTRL_ROM_SP_MSB _u(3) +#define ACCESSCTRL_ROM_SP_LSB _u(3) +#define ACCESSCTRL_ROM_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_SU +// Description : If 1, and SP is also set, ROM can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_ROM_SU_RESET _u(0x1) +#define ACCESSCTRL_ROM_SU_BITS _u(0x00000004) +#define ACCESSCTRL_ROM_SU_MSB _u(2) +#define ACCESSCTRL_ROM_SU_LSB _u(2) +#define ACCESSCTRL_ROM_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_NSP +// Description : If 1, ROM can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_ROM_NSP_RESET _u(0x1) +#define ACCESSCTRL_ROM_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_ROM_NSP_MSB _u(1) +#define ACCESSCTRL_ROM_NSP_LSB _u(1) +#define ACCESSCTRL_ROM_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_NSU +// Description : If 1, and NSP is also set, ROM can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_ROM_NSU_RESET _u(0x1) +#define ACCESSCTRL_ROM_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_ROM_NSU_MSB _u(0) +#define ACCESSCTRL_ROM_NSU_LSB _u(0) +#define ACCESSCTRL_ROM_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_MAIN +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_MAIN, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_MAIN_OFFSET _u(0x00000018) +#define ACCESSCTRL_XIP_MAIN_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_MAIN_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_DBG +// Description : If 1, XIP_MAIN can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_MAIN_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_MAIN_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_MAIN_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_MAIN_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_DMA +// Description : If 1, XIP_MAIN can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_MAIN_DMA_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_MAIN_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_MAIN_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_MAIN_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_CORE1 +// Description : If 1, XIP_MAIN can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_MAIN_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_MAIN_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_MAIN_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_MAIN_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_CORE0 +// Description : If 1, XIP_MAIN can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_MAIN_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_MAIN_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_MAIN_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_MAIN_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_SP +// Description : If 1, XIP_MAIN can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_MAIN_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_MAIN_SP_MSB _u(3) +#define ACCESSCTRL_XIP_MAIN_SP_LSB _u(3) +#define ACCESSCTRL_XIP_MAIN_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_SU +// Description : If 1, and SP is also set, XIP_MAIN can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_MAIN_SU_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_MAIN_SU_MSB _u(2) +#define ACCESSCTRL_XIP_MAIN_SU_LSB _u(2) +#define ACCESSCTRL_XIP_MAIN_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_NSP +// Description : If 1, XIP_MAIN can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_MAIN_NSP_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_MAIN_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_MAIN_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_MAIN_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_NSU +// Description : If 1, and NSP is also set, XIP_MAIN can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_MAIN_NSU_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_MAIN_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_MAIN_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_MAIN_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM0, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM0_OFFSET _u(0x0000001c) +#define ACCESSCTRL_SRAM0_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM0_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_DBG +// Description : If 1, SRAM0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM0_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM0_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM0_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_DMA +// Description : If 1, SRAM0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM0_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM0_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM0_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_CORE1 +// Description : If 1, SRAM0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM0_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM0_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_CORE0 +// Description : If 1, SRAM0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM0_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM0_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_SP +// Description : If 1, SRAM0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM0_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM0_SP_MSB _u(3) +#define ACCESSCTRL_SRAM0_SP_LSB _u(3) +#define ACCESSCTRL_SRAM0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_SU +// Description : If 1, and SP is also set, SRAM0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM0_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM0_SU_MSB _u(2) +#define ACCESSCTRL_SRAM0_SU_LSB _u(2) +#define ACCESSCTRL_SRAM0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_NSP +// Description : If 1, SRAM0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM0_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM0_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM0_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_NSU +// Description : If 1, and NSP is also set, SRAM0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM0_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM0_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM0_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM1, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM1_OFFSET _u(0x00000020) +#define ACCESSCTRL_SRAM1_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM1_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_DBG +// Description : If 1, SRAM1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM1_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM1_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM1_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_DMA +// Description : If 1, SRAM1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM1_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM1_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM1_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_CORE1 +// Description : If 1, SRAM1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM1_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM1_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_CORE0 +// Description : If 1, SRAM1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM1_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM1_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_SP +// Description : If 1, SRAM1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM1_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM1_SP_MSB _u(3) +#define ACCESSCTRL_SRAM1_SP_LSB _u(3) +#define ACCESSCTRL_SRAM1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_SU +// Description : If 1, and SP is also set, SRAM1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM1_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM1_SU_MSB _u(2) +#define ACCESSCTRL_SRAM1_SU_LSB _u(2) +#define ACCESSCTRL_SRAM1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_NSP +// Description : If 1, SRAM1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM1_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM1_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM1_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_NSU +// Description : If 1, and NSP is also set, SRAM1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM1_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM1_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM1_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM2 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM2, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM2_OFFSET _u(0x00000024) +#define ACCESSCTRL_SRAM2_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM2_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_DBG +// Description : If 1, SRAM2 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM2_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM2_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM2_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM2_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_DMA +// Description : If 1, SRAM2 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM2_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM2_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM2_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM2_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_CORE1 +// Description : If 1, SRAM2 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM2_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM2_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM2_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM2_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_CORE0 +// Description : If 1, SRAM2 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM2_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM2_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM2_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM2_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_SP +// Description : If 1, SRAM2 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM2_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM2_SP_MSB _u(3) +#define ACCESSCTRL_SRAM2_SP_LSB _u(3) +#define ACCESSCTRL_SRAM2_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_SU +// Description : If 1, and SP is also set, SRAM2 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM2_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM2_SU_MSB _u(2) +#define ACCESSCTRL_SRAM2_SU_LSB _u(2) +#define ACCESSCTRL_SRAM2_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_NSP +// Description : If 1, SRAM2 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM2_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM2_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM2_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM2_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_NSU +// Description : If 1, and NSP is also set, SRAM2 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM2_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM2_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM2_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM2_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM3 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM3, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM3_OFFSET _u(0x00000028) +#define ACCESSCTRL_SRAM3_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM3_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_DBG +// Description : If 1, SRAM3 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM3_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM3_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM3_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM3_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_DMA +// Description : If 1, SRAM3 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM3_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM3_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM3_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM3_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_CORE1 +// Description : If 1, SRAM3 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM3_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM3_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM3_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM3_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_CORE0 +// Description : If 1, SRAM3 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM3_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM3_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM3_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM3_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_SP +// Description : If 1, SRAM3 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM3_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM3_SP_MSB _u(3) +#define ACCESSCTRL_SRAM3_SP_LSB _u(3) +#define ACCESSCTRL_SRAM3_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_SU +// Description : If 1, and SP is also set, SRAM3 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM3_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM3_SU_MSB _u(2) +#define ACCESSCTRL_SRAM3_SU_LSB _u(2) +#define ACCESSCTRL_SRAM3_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_NSP +// Description : If 1, SRAM3 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM3_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM3_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM3_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM3_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_NSU +// Description : If 1, and NSP is also set, SRAM3 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM3_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM3_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM3_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM3_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM4 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM4, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM4_OFFSET _u(0x0000002c) +#define ACCESSCTRL_SRAM4_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM4_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_DBG +// Description : If 1, SRAM4 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM4_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM4_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM4_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM4_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_DMA +// Description : If 1, SRAM4 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM4_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM4_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM4_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM4_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_CORE1 +// Description : If 1, SRAM4 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM4_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM4_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM4_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM4_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_CORE0 +// Description : If 1, SRAM4 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM4_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM4_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM4_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM4_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_SP +// Description : If 1, SRAM4 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM4_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM4_SP_MSB _u(3) +#define ACCESSCTRL_SRAM4_SP_LSB _u(3) +#define ACCESSCTRL_SRAM4_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_SU +// Description : If 1, and SP is also set, SRAM4 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM4_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM4_SU_MSB _u(2) +#define ACCESSCTRL_SRAM4_SU_LSB _u(2) +#define ACCESSCTRL_SRAM4_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_NSP +// Description : If 1, SRAM4 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM4_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM4_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM4_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM4_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_NSU +// Description : If 1, and NSP is also set, SRAM4 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM4_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM4_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM4_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM4_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM5 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM5, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM5_OFFSET _u(0x00000030) +#define ACCESSCTRL_SRAM5_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM5_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_DBG +// Description : If 1, SRAM5 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM5_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM5_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM5_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM5_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_DMA +// Description : If 1, SRAM5 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM5_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM5_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM5_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM5_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_CORE1 +// Description : If 1, SRAM5 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM5_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM5_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM5_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM5_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_CORE0 +// Description : If 1, SRAM5 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM5_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM5_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM5_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM5_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_SP +// Description : If 1, SRAM5 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM5_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM5_SP_MSB _u(3) +#define ACCESSCTRL_SRAM5_SP_LSB _u(3) +#define ACCESSCTRL_SRAM5_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_SU +// Description : If 1, and SP is also set, SRAM5 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM5_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM5_SU_MSB _u(2) +#define ACCESSCTRL_SRAM5_SU_LSB _u(2) +#define ACCESSCTRL_SRAM5_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_NSP +// Description : If 1, SRAM5 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM5_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM5_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM5_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM5_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_NSU +// Description : If 1, and NSP is also set, SRAM5 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM5_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM5_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM5_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM5_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM6 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM6, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM6_OFFSET _u(0x00000034) +#define ACCESSCTRL_SRAM6_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM6_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_DBG +// Description : If 1, SRAM6 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM6_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM6_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM6_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM6_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_DMA +// Description : If 1, SRAM6 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM6_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM6_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM6_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM6_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_CORE1 +// Description : If 1, SRAM6 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM6_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM6_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM6_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM6_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_CORE0 +// Description : If 1, SRAM6 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM6_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM6_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM6_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM6_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_SP +// Description : If 1, SRAM6 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM6_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM6_SP_MSB _u(3) +#define ACCESSCTRL_SRAM6_SP_LSB _u(3) +#define ACCESSCTRL_SRAM6_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_SU +// Description : If 1, and SP is also set, SRAM6 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM6_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM6_SU_MSB _u(2) +#define ACCESSCTRL_SRAM6_SU_LSB _u(2) +#define ACCESSCTRL_SRAM6_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_NSP +// Description : If 1, SRAM6 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM6_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM6_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM6_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM6_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_NSU +// Description : If 1, and NSP is also set, SRAM6 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM6_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM6_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM6_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM6_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM7 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM7, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM7_OFFSET _u(0x00000038) +#define ACCESSCTRL_SRAM7_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM7_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_DBG +// Description : If 1, SRAM7 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM7_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM7_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM7_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM7_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_DMA +// Description : If 1, SRAM7 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM7_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM7_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM7_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM7_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_CORE1 +// Description : If 1, SRAM7 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM7_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM7_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM7_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM7_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_CORE0 +// Description : If 1, SRAM7 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM7_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM7_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM7_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM7_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_SP +// Description : If 1, SRAM7 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM7_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM7_SP_MSB _u(3) +#define ACCESSCTRL_SRAM7_SP_LSB _u(3) +#define ACCESSCTRL_SRAM7_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_SU +// Description : If 1, and SP is also set, SRAM7 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM7_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM7_SU_MSB _u(2) +#define ACCESSCTRL_SRAM7_SU_LSB _u(2) +#define ACCESSCTRL_SRAM7_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_NSP +// Description : If 1, SRAM7 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM7_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM7_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM7_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM7_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_NSU +// Description : If 1, and NSP is also set, SRAM7 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM7_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM7_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM7_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM7_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM8 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM8, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM8_OFFSET _u(0x0000003c) +#define ACCESSCTRL_SRAM8_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM8_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_DBG +// Description : If 1, SRAM8 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM8_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM8_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM8_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM8_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_DMA +// Description : If 1, SRAM8 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM8_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM8_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM8_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM8_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_CORE1 +// Description : If 1, SRAM8 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM8_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM8_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM8_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM8_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_CORE0 +// Description : If 1, SRAM8 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM8_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM8_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM8_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM8_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_SP +// Description : If 1, SRAM8 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM8_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM8_SP_MSB _u(3) +#define ACCESSCTRL_SRAM8_SP_LSB _u(3) +#define ACCESSCTRL_SRAM8_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_SU +// Description : If 1, and SP is also set, SRAM8 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM8_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM8_SU_MSB _u(2) +#define ACCESSCTRL_SRAM8_SU_LSB _u(2) +#define ACCESSCTRL_SRAM8_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_NSP +// Description : If 1, SRAM8 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM8_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM8_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM8_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM8_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_NSU +// Description : If 1, and NSP is also set, SRAM8 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM8_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM8_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM8_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM8_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM9 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM9, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM9_OFFSET _u(0x00000040) +#define ACCESSCTRL_SRAM9_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM9_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_DBG +// Description : If 1, SRAM9 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM9_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM9_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM9_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM9_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_DMA +// Description : If 1, SRAM9 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM9_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM9_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM9_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM9_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_CORE1 +// Description : If 1, SRAM9 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM9_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM9_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM9_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM9_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_CORE0 +// Description : If 1, SRAM9 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM9_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM9_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM9_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM9_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_SP +// Description : If 1, SRAM9 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM9_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM9_SP_MSB _u(3) +#define ACCESSCTRL_SRAM9_SP_LSB _u(3) +#define ACCESSCTRL_SRAM9_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_SU +// Description : If 1, and SP is also set, SRAM9 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM9_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM9_SU_MSB _u(2) +#define ACCESSCTRL_SRAM9_SU_LSB _u(2) +#define ACCESSCTRL_SRAM9_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_NSP +// Description : If 1, SRAM9 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM9_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM9_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM9_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM9_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_NSU +// Description : If 1, and NSP is also set, SRAM9 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM9_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM9_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM9_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM9_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_DMA +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// DMA, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_DMA_OFFSET _u(0x00000044) +#define ACCESSCTRL_DMA_BITS _u(0x000000ff) +#define ACCESSCTRL_DMA_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_DBG +// Description : If 1, DMA can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_DMA_DBG_RESET _u(0x1) +#define ACCESSCTRL_DMA_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_DMA_DBG_MSB _u(7) +#define ACCESSCTRL_DMA_DBG_LSB _u(7) +#define ACCESSCTRL_DMA_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_DMA +// Description : If 1, DMA can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_DMA_DMA_RESET _u(0x1) +#define ACCESSCTRL_DMA_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_DMA_DMA_MSB _u(6) +#define ACCESSCTRL_DMA_DMA_LSB _u(6) +#define ACCESSCTRL_DMA_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_CORE1 +// Description : If 1, DMA can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_DMA_CORE1_RESET _u(0x1) +#define ACCESSCTRL_DMA_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_DMA_CORE1_MSB _u(5) +#define ACCESSCTRL_DMA_CORE1_LSB _u(5) +#define ACCESSCTRL_DMA_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_CORE0 +// Description : If 1, DMA can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_DMA_CORE0_RESET _u(0x1) +#define ACCESSCTRL_DMA_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_DMA_CORE0_MSB _u(4) +#define ACCESSCTRL_DMA_CORE0_LSB _u(4) +#define ACCESSCTRL_DMA_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_SP +// Description : If 1, DMA can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_DMA_SP_RESET _u(0x1) +#define ACCESSCTRL_DMA_SP_BITS _u(0x00000008) +#define ACCESSCTRL_DMA_SP_MSB _u(3) +#define ACCESSCTRL_DMA_SP_LSB _u(3) +#define ACCESSCTRL_DMA_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_SU +// Description : If 1, and SP is also set, DMA can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_DMA_SU_RESET _u(0x1) +#define ACCESSCTRL_DMA_SU_BITS _u(0x00000004) +#define ACCESSCTRL_DMA_SU_MSB _u(2) +#define ACCESSCTRL_DMA_SU_LSB _u(2) +#define ACCESSCTRL_DMA_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_NSP +// Description : If 1, DMA can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_DMA_NSP_RESET _u(0x0) +#define ACCESSCTRL_DMA_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_DMA_NSP_MSB _u(1) +#define ACCESSCTRL_DMA_NSP_LSB _u(1) +#define ACCESSCTRL_DMA_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_NSU +// Description : If 1, and NSP is also set, DMA can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_DMA_NSU_RESET _u(0x0) +#define ACCESSCTRL_DMA_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_DMA_NSU_MSB _u(0) +#define ACCESSCTRL_DMA_NSU_LSB _u(0) +#define ACCESSCTRL_DMA_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_USBCTRL +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// USBCTRL, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_USBCTRL_OFFSET _u(0x00000048) +#define ACCESSCTRL_USBCTRL_BITS _u(0x000000ff) +#define ACCESSCTRL_USBCTRL_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_DBG +// Description : If 1, USBCTRL can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_USBCTRL_DBG_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_USBCTRL_DBG_MSB _u(7) +#define ACCESSCTRL_USBCTRL_DBG_LSB _u(7) +#define ACCESSCTRL_USBCTRL_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_DMA +// Description : If 1, USBCTRL can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_USBCTRL_DMA_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_USBCTRL_DMA_MSB _u(6) +#define ACCESSCTRL_USBCTRL_DMA_LSB _u(6) +#define ACCESSCTRL_USBCTRL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_CORE1 +// Description : If 1, USBCTRL can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_USBCTRL_CORE1_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_USBCTRL_CORE1_MSB _u(5) +#define ACCESSCTRL_USBCTRL_CORE1_LSB _u(5) +#define ACCESSCTRL_USBCTRL_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_CORE0 +// Description : If 1, USBCTRL can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_USBCTRL_CORE0_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_USBCTRL_CORE0_MSB _u(4) +#define ACCESSCTRL_USBCTRL_CORE0_LSB _u(4) +#define ACCESSCTRL_USBCTRL_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_SP +// Description : If 1, USBCTRL can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_USBCTRL_SP_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_SP_BITS _u(0x00000008) +#define ACCESSCTRL_USBCTRL_SP_MSB _u(3) +#define ACCESSCTRL_USBCTRL_SP_LSB _u(3) +#define ACCESSCTRL_USBCTRL_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_SU +// Description : If 1, and SP is also set, USBCTRL can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_USBCTRL_SU_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_SU_BITS _u(0x00000004) +#define ACCESSCTRL_USBCTRL_SU_MSB _u(2) +#define ACCESSCTRL_USBCTRL_SU_LSB _u(2) +#define ACCESSCTRL_USBCTRL_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_NSP +// Description : If 1, USBCTRL can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_USBCTRL_NSP_RESET _u(0x0) +#define ACCESSCTRL_USBCTRL_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_USBCTRL_NSP_MSB _u(1) +#define ACCESSCTRL_USBCTRL_NSP_LSB _u(1) +#define ACCESSCTRL_USBCTRL_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_NSU +// Description : If 1, and NSP is also set, USBCTRL can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_USBCTRL_NSU_RESET _u(0x0) +#define ACCESSCTRL_USBCTRL_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_USBCTRL_NSU_MSB _u(0) +#define ACCESSCTRL_USBCTRL_NSU_LSB _u(0) +#define ACCESSCTRL_USBCTRL_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PIO0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PIO0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PIO0_OFFSET _u(0x0000004c) +#define ACCESSCTRL_PIO0_BITS _u(0x000000ff) +#define ACCESSCTRL_PIO0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_DBG +// Description : If 1, PIO0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PIO0_DBG_RESET _u(0x1) +#define ACCESSCTRL_PIO0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PIO0_DBG_MSB _u(7) +#define ACCESSCTRL_PIO0_DBG_LSB _u(7) +#define ACCESSCTRL_PIO0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_DMA +// Description : If 1, PIO0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO0_DMA_RESET _u(0x1) +#define ACCESSCTRL_PIO0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PIO0_DMA_MSB _u(6) +#define ACCESSCTRL_PIO0_DMA_LSB _u(6) +#define ACCESSCTRL_PIO0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_CORE1 +// Description : If 1, PIO0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PIO0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PIO0_CORE1_MSB _u(5) +#define ACCESSCTRL_PIO0_CORE1_LSB _u(5) +#define ACCESSCTRL_PIO0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_CORE0 +// Description : If 1, PIO0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PIO0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PIO0_CORE0_MSB _u(4) +#define ACCESSCTRL_PIO0_CORE0_LSB _u(4) +#define ACCESSCTRL_PIO0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_SP +// Description : If 1, PIO0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PIO0_SP_RESET _u(0x1) +#define ACCESSCTRL_PIO0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PIO0_SP_MSB _u(3) +#define ACCESSCTRL_PIO0_SP_LSB _u(3) +#define ACCESSCTRL_PIO0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_SU +// Description : If 1, and SP is also set, PIO0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PIO0_SU_RESET _u(0x1) +#define ACCESSCTRL_PIO0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PIO0_SU_MSB _u(2) +#define ACCESSCTRL_PIO0_SU_LSB _u(2) +#define ACCESSCTRL_PIO0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_NSP +// Description : If 1, PIO0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PIO0_NSP_RESET _u(0x0) +#define ACCESSCTRL_PIO0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PIO0_NSP_MSB _u(1) +#define ACCESSCTRL_PIO0_NSP_LSB _u(1) +#define ACCESSCTRL_PIO0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_NSU +// Description : If 1, and NSP is also set, PIO0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PIO0_NSU_RESET _u(0x0) +#define ACCESSCTRL_PIO0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PIO0_NSU_MSB _u(0) +#define ACCESSCTRL_PIO0_NSU_LSB _u(0) +#define ACCESSCTRL_PIO0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PIO1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PIO1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PIO1_OFFSET _u(0x00000050) +#define ACCESSCTRL_PIO1_BITS _u(0x000000ff) +#define ACCESSCTRL_PIO1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_DBG +// Description : If 1, PIO1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PIO1_DBG_RESET _u(0x1) +#define ACCESSCTRL_PIO1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PIO1_DBG_MSB _u(7) +#define ACCESSCTRL_PIO1_DBG_LSB _u(7) +#define ACCESSCTRL_PIO1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_DMA +// Description : If 1, PIO1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO1_DMA_RESET _u(0x1) +#define ACCESSCTRL_PIO1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PIO1_DMA_MSB _u(6) +#define ACCESSCTRL_PIO1_DMA_LSB _u(6) +#define ACCESSCTRL_PIO1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_CORE1 +// Description : If 1, PIO1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PIO1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PIO1_CORE1_MSB _u(5) +#define ACCESSCTRL_PIO1_CORE1_LSB _u(5) +#define ACCESSCTRL_PIO1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_CORE0 +// Description : If 1, PIO1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PIO1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PIO1_CORE0_MSB _u(4) +#define ACCESSCTRL_PIO1_CORE0_LSB _u(4) +#define ACCESSCTRL_PIO1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_SP +// Description : If 1, PIO1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PIO1_SP_RESET _u(0x1) +#define ACCESSCTRL_PIO1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PIO1_SP_MSB _u(3) +#define ACCESSCTRL_PIO1_SP_LSB _u(3) +#define ACCESSCTRL_PIO1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_SU +// Description : If 1, and SP is also set, PIO1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PIO1_SU_RESET _u(0x1) +#define ACCESSCTRL_PIO1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PIO1_SU_MSB _u(2) +#define ACCESSCTRL_PIO1_SU_LSB _u(2) +#define ACCESSCTRL_PIO1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_NSP +// Description : If 1, PIO1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PIO1_NSP_RESET _u(0x0) +#define ACCESSCTRL_PIO1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PIO1_NSP_MSB _u(1) +#define ACCESSCTRL_PIO1_NSP_LSB _u(1) +#define ACCESSCTRL_PIO1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_NSU +// Description : If 1, and NSP is also set, PIO1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PIO1_NSU_RESET _u(0x0) +#define ACCESSCTRL_PIO1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PIO1_NSU_MSB _u(0) +#define ACCESSCTRL_PIO1_NSU_LSB _u(0) +#define ACCESSCTRL_PIO1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PIO2 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PIO2, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PIO2_OFFSET _u(0x00000054) +#define ACCESSCTRL_PIO2_BITS _u(0x000000ff) +#define ACCESSCTRL_PIO2_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_DBG +// Description : If 1, PIO2 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PIO2_DBG_RESET _u(0x1) +#define ACCESSCTRL_PIO2_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PIO2_DBG_MSB _u(7) +#define ACCESSCTRL_PIO2_DBG_LSB _u(7) +#define ACCESSCTRL_PIO2_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_DMA +// Description : If 1, PIO2 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO2_DMA_RESET _u(0x1) +#define ACCESSCTRL_PIO2_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PIO2_DMA_MSB _u(6) +#define ACCESSCTRL_PIO2_DMA_LSB _u(6) +#define ACCESSCTRL_PIO2_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_CORE1 +// Description : If 1, PIO2 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO2_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PIO2_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PIO2_CORE1_MSB _u(5) +#define ACCESSCTRL_PIO2_CORE1_LSB _u(5) +#define ACCESSCTRL_PIO2_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_CORE0 +// Description : If 1, PIO2 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO2_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PIO2_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PIO2_CORE0_MSB _u(4) +#define ACCESSCTRL_PIO2_CORE0_LSB _u(4) +#define ACCESSCTRL_PIO2_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_SP +// Description : If 1, PIO2 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PIO2_SP_RESET _u(0x1) +#define ACCESSCTRL_PIO2_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PIO2_SP_MSB _u(3) +#define ACCESSCTRL_PIO2_SP_LSB _u(3) +#define ACCESSCTRL_PIO2_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_SU +// Description : If 1, and SP is also set, PIO2 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PIO2_SU_RESET _u(0x1) +#define ACCESSCTRL_PIO2_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PIO2_SU_MSB _u(2) +#define ACCESSCTRL_PIO2_SU_LSB _u(2) +#define ACCESSCTRL_PIO2_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_NSP +// Description : If 1, PIO2 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PIO2_NSP_RESET _u(0x0) +#define ACCESSCTRL_PIO2_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PIO2_NSP_MSB _u(1) +#define ACCESSCTRL_PIO2_NSP_LSB _u(1) +#define ACCESSCTRL_PIO2_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_NSU +// Description : If 1, and NSP is also set, PIO2 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PIO2_NSU_RESET _u(0x0) +#define ACCESSCTRL_PIO2_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PIO2_NSU_MSB _u(0) +#define ACCESSCTRL_PIO2_NSU_LSB _u(0) +#define ACCESSCTRL_PIO2_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CORESIGHT_TRACE +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// CORESIGHT_TRACE, and at what security/privilege levels they can +// do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_TRACE_OFFSET _u(0x00000058) +#define ACCESSCTRL_CORESIGHT_TRACE_BITS _u(0x000000ff) +#define ACCESSCTRL_CORESIGHT_TRACE_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_DBG +// Description : If 1, CORESIGHT_TRACE can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_MSB _u(7) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_LSB _u(7) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_DMA +// Description : If 1, CORESIGHT_TRACE can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_MSB _u(6) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_LSB _u(6) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_CORE1 +// Description : If 1, CORESIGHT_TRACE can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_MSB _u(5) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_LSB _u(5) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_CORE0 +// Description : If 1, CORESIGHT_TRACE can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_MSB _u(4) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_LSB _u(4) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_SP +// Description : If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_CORESIGHT_TRACE_SP_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_BITS _u(0x00000008) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_MSB _u(3) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_LSB _u(3) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_SU +// Description : If 1, and SP is also set, CORESIGHT_TRACE can be accessed from +// a Secure, Unprivileged context. +#define ACCESSCTRL_CORESIGHT_TRACE_SU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_BITS _u(0x00000004) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_MSB _u(2) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_LSB _u(2) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_NSP +// Description : If 1, CORESIGHT_TRACE can be accessed from a Non-secure, +// Privileged context. +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_MSB _u(1) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_LSB _u(1) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_NSU +// Description : If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from +// a Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_MSB _u(0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_LSB _u(0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CORESIGHT_PERIPH +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// CORESIGHT_PERIPH, and at what security/privilege levels they +// can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_PERIPH_OFFSET _u(0x0000005c) +#define ACCESSCTRL_CORESIGHT_PERIPH_BITS _u(0x000000ff) +#define ACCESSCTRL_CORESIGHT_PERIPH_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_DBG +// Description : If 1, CORESIGHT_PERIPH can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_MSB _u(7) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_LSB _u(7) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_DMA +// Description : If 1, CORESIGHT_PERIPH can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_MSB _u(6) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_LSB _u(6) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_CORE1 +// Description : If 1, CORESIGHT_PERIPH can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_MSB _u(5) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_LSB _u(5) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_CORE0 +// Description : If 1, CORESIGHT_PERIPH can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_MSB _u(4) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_LSB _u(4) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_SP +// Description : If 1, CORESIGHT_PERIPH can be accessed from a Secure, +// Privileged context. +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_BITS _u(0x00000008) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_MSB _u(3) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_LSB _u(3) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_SU +// Description : If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from +// a Secure, Unprivileged context. +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_BITS _u(0x00000004) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_MSB _u(2) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_LSB _u(2) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_NSP +// Description : If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, +// Privileged context. +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_MSB _u(1) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_LSB _u(1) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_NSU +// Description : If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed +// from a Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_MSB _u(0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_LSB _u(0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SYSINFO +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SYSINFO, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SYSINFO_OFFSET _u(0x00000060) +#define ACCESSCTRL_SYSINFO_BITS _u(0x000000ff) +#define ACCESSCTRL_SYSINFO_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_DBG +// Description : If 1, SYSINFO can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SYSINFO_DBG_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SYSINFO_DBG_MSB _u(7) +#define ACCESSCTRL_SYSINFO_DBG_LSB _u(7) +#define ACCESSCTRL_SYSINFO_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_DMA +// Description : If 1, SYSINFO can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSINFO_DMA_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SYSINFO_DMA_MSB _u(6) +#define ACCESSCTRL_SYSINFO_DMA_LSB _u(6) +#define ACCESSCTRL_SYSINFO_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_CORE1 +// Description : If 1, SYSINFO can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSINFO_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SYSINFO_CORE1_MSB _u(5) +#define ACCESSCTRL_SYSINFO_CORE1_LSB _u(5) +#define ACCESSCTRL_SYSINFO_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_CORE0 +// Description : If 1, SYSINFO can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSINFO_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SYSINFO_CORE0_MSB _u(4) +#define ACCESSCTRL_SYSINFO_CORE0_LSB _u(4) +#define ACCESSCTRL_SYSINFO_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_SP +// Description : If 1, SYSINFO can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_SYSINFO_SP_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SYSINFO_SP_MSB _u(3) +#define ACCESSCTRL_SYSINFO_SP_LSB _u(3) +#define ACCESSCTRL_SYSINFO_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_SU +// Description : If 1, and SP is also set, SYSINFO can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_SYSINFO_SU_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SYSINFO_SU_MSB _u(2) +#define ACCESSCTRL_SYSINFO_SU_LSB _u(2) +#define ACCESSCTRL_SYSINFO_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_NSP +// Description : If 1, SYSINFO can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SYSINFO_NSP_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SYSINFO_NSP_MSB _u(1) +#define ACCESSCTRL_SYSINFO_NSP_LSB _u(1) +#define ACCESSCTRL_SYSINFO_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_NSU +// Description : If 1, and NSP is also set, SYSINFO can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SYSINFO_NSU_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SYSINFO_NSU_MSB _u(0) +#define ACCESSCTRL_SYSINFO_NSU_LSB _u(0) +#define ACCESSCTRL_SYSINFO_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_RESETS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// RESETS, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_RESETS_OFFSET _u(0x00000064) +#define ACCESSCTRL_RESETS_BITS _u(0x000000ff) +#define ACCESSCTRL_RESETS_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_DBG +// Description : If 1, RESETS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_RESETS_DBG_RESET _u(0x1) +#define ACCESSCTRL_RESETS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_RESETS_DBG_MSB _u(7) +#define ACCESSCTRL_RESETS_DBG_LSB _u(7) +#define ACCESSCTRL_RESETS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_DMA +// Description : If 1, RESETS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RESETS_DMA_RESET _u(0x1) +#define ACCESSCTRL_RESETS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_RESETS_DMA_MSB _u(6) +#define ACCESSCTRL_RESETS_DMA_LSB _u(6) +#define ACCESSCTRL_RESETS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_CORE1 +// Description : If 1, RESETS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RESETS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_RESETS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_RESETS_CORE1_MSB _u(5) +#define ACCESSCTRL_RESETS_CORE1_LSB _u(5) +#define ACCESSCTRL_RESETS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_CORE0 +// Description : If 1, RESETS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RESETS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_RESETS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_RESETS_CORE0_MSB _u(4) +#define ACCESSCTRL_RESETS_CORE0_LSB _u(4) +#define ACCESSCTRL_RESETS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_SP +// Description : If 1, RESETS can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_RESETS_SP_RESET _u(0x1) +#define ACCESSCTRL_RESETS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_RESETS_SP_MSB _u(3) +#define ACCESSCTRL_RESETS_SP_LSB _u(3) +#define ACCESSCTRL_RESETS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_SU +// Description : If 1, and SP is also set, RESETS can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_RESETS_SU_RESET _u(0x1) +#define ACCESSCTRL_RESETS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_RESETS_SU_MSB _u(2) +#define ACCESSCTRL_RESETS_SU_LSB _u(2) +#define ACCESSCTRL_RESETS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_NSP +// Description : If 1, RESETS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_RESETS_NSP_RESET _u(0x0) +#define ACCESSCTRL_RESETS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_RESETS_NSP_MSB _u(1) +#define ACCESSCTRL_RESETS_NSP_LSB _u(1) +#define ACCESSCTRL_RESETS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_NSU +// Description : If 1, and NSP is also set, RESETS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_RESETS_NSU_RESET _u(0x0) +#define ACCESSCTRL_RESETS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_RESETS_NSU_MSB _u(0) +#define ACCESSCTRL_RESETS_NSU_LSB _u(0) +#define ACCESSCTRL_RESETS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_IO_BANK0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// IO_BANK0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_IO_BANK0_OFFSET _u(0x00000068) +#define ACCESSCTRL_IO_BANK0_BITS _u(0x000000ff) +#define ACCESSCTRL_IO_BANK0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_DBG +// Description : If 1, IO_BANK0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK0_DBG_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_IO_BANK0_DBG_MSB _u(7) +#define ACCESSCTRL_IO_BANK0_DBG_LSB _u(7) +#define ACCESSCTRL_IO_BANK0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_DMA +// Description : If 1, IO_BANK0 can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK0_DMA_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_IO_BANK0_DMA_MSB _u(6) +#define ACCESSCTRL_IO_BANK0_DMA_LSB _u(6) +#define ACCESSCTRL_IO_BANK0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_CORE1 +// Description : If 1, IO_BANK0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_IO_BANK0_CORE1_MSB _u(5) +#define ACCESSCTRL_IO_BANK0_CORE1_LSB _u(5) +#define ACCESSCTRL_IO_BANK0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_CORE0 +// Description : If 1, IO_BANK0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_IO_BANK0_CORE0_MSB _u(4) +#define ACCESSCTRL_IO_BANK0_CORE0_LSB _u(4) +#define ACCESSCTRL_IO_BANK0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_SP +// Description : If 1, IO_BANK0 can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK0_SP_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_IO_BANK0_SP_MSB _u(3) +#define ACCESSCTRL_IO_BANK0_SP_LSB _u(3) +#define ACCESSCTRL_IO_BANK0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_SU +// Description : If 1, and SP is also set, IO_BANK0 can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_IO_BANK0_SU_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_IO_BANK0_SU_MSB _u(2) +#define ACCESSCTRL_IO_BANK0_SU_LSB _u(2) +#define ACCESSCTRL_IO_BANK0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_NSP +// Description : If 1, IO_BANK0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK0_NSP_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_IO_BANK0_NSP_MSB _u(1) +#define ACCESSCTRL_IO_BANK0_NSP_LSB _u(1) +#define ACCESSCTRL_IO_BANK0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_NSU +// Description : If 1, and NSP is also set, IO_BANK0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_IO_BANK0_NSU_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_IO_BANK0_NSU_MSB _u(0) +#define ACCESSCTRL_IO_BANK0_NSU_LSB _u(0) +#define ACCESSCTRL_IO_BANK0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_IO_BANK1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// IO_BANK1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_IO_BANK1_OFFSET _u(0x0000006c) +#define ACCESSCTRL_IO_BANK1_BITS _u(0x000000ff) +#define ACCESSCTRL_IO_BANK1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_DBG +// Description : If 1, IO_BANK1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK1_DBG_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_IO_BANK1_DBG_MSB _u(7) +#define ACCESSCTRL_IO_BANK1_DBG_LSB _u(7) +#define ACCESSCTRL_IO_BANK1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_DMA +// Description : If 1, IO_BANK1 can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK1_DMA_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_IO_BANK1_DMA_MSB _u(6) +#define ACCESSCTRL_IO_BANK1_DMA_LSB _u(6) +#define ACCESSCTRL_IO_BANK1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_CORE1 +// Description : If 1, IO_BANK1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_IO_BANK1_CORE1_MSB _u(5) +#define ACCESSCTRL_IO_BANK1_CORE1_LSB _u(5) +#define ACCESSCTRL_IO_BANK1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_CORE0 +// Description : If 1, IO_BANK1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_IO_BANK1_CORE0_MSB _u(4) +#define ACCESSCTRL_IO_BANK1_CORE0_LSB _u(4) +#define ACCESSCTRL_IO_BANK1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_SP +// Description : If 1, IO_BANK1 can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK1_SP_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_IO_BANK1_SP_MSB _u(3) +#define ACCESSCTRL_IO_BANK1_SP_LSB _u(3) +#define ACCESSCTRL_IO_BANK1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_SU +// Description : If 1, and SP is also set, IO_BANK1 can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_IO_BANK1_SU_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_IO_BANK1_SU_MSB _u(2) +#define ACCESSCTRL_IO_BANK1_SU_LSB _u(2) +#define ACCESSCTRL_IO_BANK1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_NSP +// Description : If 1, IO_BANK1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK1_NSP_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_IO_BANK1_NSP_MSB _u(1) +#define ACCESSCTRL_IO_BANK1_NSP_LSB _u(1) +#define ACCESSCTRL_IO_BANK1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_NSU +// Description : If 1, and NSP is also set, IO_BANK1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_IO_BANK1_NSU_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_IO_BANK1_NSU_MSB _u(0) +#define ACCESSCTRL_IO_BANK1_NSU_LSB _u(0) +#define ACCESSCTRL_IO_BANK1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PADS_BANK0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PADS_BANK0, and at what security/privilege levels they can do +// so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PADS_BANK0_OFFSET _u(0x00000070) +#define ACCESSCTRL_PADS_BANK0_BITS _u(0x000000ff) +#define ACCESSCTRL_PADS_BANK0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_DBG +// Description : If 1, PADS_BANK0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_DBG_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PADS_BANK0_DBG_MSB _u(7) +#define ACCESSCTRL_PADS_BANK0_DBG_LSB _u(7) +#define ACCESSCTRL_PADS_BANK0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_DMA +// Description : If 1, PADS_BANK0 can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_DMA_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PADS_BANK0_DMA_MSB _u(6) +#define ACCESSCTRL_PADS_BANK0_DMA_LSB _u(6) +#define ACCESSCTRL_PADS_BANK0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_CORE1 +// Description : If 1, PADS_BANK0 can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PADS_BANK0_CORE1_MSB _u(5) +#define ACCESSCTRL_PADS_BANK0_CORE1_LSB _u(5) +#define ACCESSCTRL_PADS_BANK0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_CORE0 +// Description : If 1, PADS_BANK0 can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PADS_BANK0_CORE0_MSB _u(4) +#define ACCESSCTRL_PADS_BANK0_CORE0_LSB _u(4) +#define ACCESSCTRL_PADS_BANK0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_SP +// Description : If 1, PADS_BANK0 can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PADS_BANK0_SP_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PADS_BANK0_SP_MSB _u(3) +#define ACCESSCTRL_PADS_BANK0_SP_LSB _u(3) +#define ACCESSCTRL_PADS_BANK0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_SU +// Description : If 1, and SP is also set, PADS_BANK0 can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PADS_BANK0_SU_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PADS_BANK0_SU_MSB _u(2) +#define ACCESSCTRL_PADS_BANK0_SU_LSB _u(2) +#define ACCESSCTRL_PADS_BANK0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_NSP +// Description : If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PADS_BANK0_NSP_RESET _u(0x0) +#define ACCESSCTRL_PADS_BANK0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PADS_BANK0_NSP_MSB _u(1) +#define ACCESSCTRL_PADS_BANK0_NSP_LSB _u(1) +#define ACCESSCTRL_PADS_BANK0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_NSU +// Description : If 1, and NSP is also set, PADS_BANK0 can be accessed from a +// Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PADS_BANK0_NSU_RESET _u(0x0) +#define ACCESSCTRL_PADS_BANK0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PADS_BANK0_NSU_MSB _u(0) +#define ACCESSCTRL_PADS_BANK0_NSU_LSB _u(0) +#define ACCESSCTRL_PADS_BANK0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PADS_QSPI +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PADS_QSPI, and at what security/privilege levels they can do +// so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PADS_QSPI_OFFSET _u(0x00000074) +#define ACCESSCTRL_PADS_QSPI_BITS _u(0x000000ff) +#define ACCESSCTRL_PADS_QSPI_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_DBG +// Description : If 1, PADS_QSPI can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_DBG_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PADS_QSPI_DBG_MSB _u(7) +#define ACCESSCTRL_PADS_QSPI_DBG_LSB _u(7) +#define ACCESSCTRL_PADS_QSPI_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_DMA +// Description : If 1, PADS_QSPI can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_DMA_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PADS_QSPI_DMA_MSB _u(6) +#define ACCESSCTRL_PADS_QSPI_DMA_LSB _u(6) +#define ACCESSCTRL_PADS_QSPI_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_CORE1 +// Description : If 1, PADS_QSPI can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PADS_QSPI_CORE1_MSB _u(5) +#define ACCESSCTRL_PADS_QSPI_CORE1_LSB _u(5) +#define ACCESSCTRL_PADS_QSPI_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_CORE0 +// Description : If 1, PADS_QSPI can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PADS_QSPI_CORE0_MSB _u(4) +#define ACCESSCTRL_PADS_QSPI_CORE0_LSB _u(4) +#define ACCESSCTRL_PADS_QSPI_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_SP +// Description : If 1, PADS_QSPI can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PADS_QSPI_SP_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PADS_QSPI_SP_MSB _u(3) +#define ACCESSCTRL_PADS_QSPI_SP_LSB _u(3) +#define ACCESSCTRL_PADS_QSPI_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_SU +// Description : If 1, and SP is also set, PADS_QSPI can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PADS_QSPI_SU_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PADS_QSPI_SU_MSB _u(2) +#define ACCESSCTRL_PADS_QSPI_SU_LSB _u(2) +#define ACCESSCTRL_PADS_QSPI_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_NSP +// Description : If 1, PADS_QSPI can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PADS_QSPI_NSP_RESET _u(0x0) +#define ACCESSCTRL_PADS_QSPI_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PADS_QSPI_NSP_MSB _u(1) +#define ACCESSCTRL_PADS_QSPI_NSP_LSB _u(1) +#define ACCESSCTRL_PADS_QSPI_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_NSU +// Description : If 1, and NSP is also set, PADS_QSPI can be accessed from a +// Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PADS_QSPI_NSU_RESET _u(0x0) +#define ACCESSCTRL_PADS_QSPI_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PADS_QSPI_NSU_MSB _u(0) +#define ACCESSCTRL_PADS_QSPI_NSU_LSB _u(0) +#define ACCESSCTRL_PADS_QSPI_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_BUSCTRL +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// BUSCTRL, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_BUSCTRL_OFFSET _u(0x00000078) +#define ACCESSCTRL_BUSCTRL_BITS _u(0x000000ff) +#define ACCESSCTRL_BUSCTRL_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_DBG +// Description : If 1, BUSCTRL can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_BUSCTRL_DBG_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_BUSCTRL_DBG_MSB _u(7) +#define ACCESSCTRL_BUSCTRL_DBG_LSB _u(7) +#define ACCESSCTRL_BUSCTRL_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_DMA +// Description : If 1, BUSCTRL can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_BUSCTRL_DMA_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_BUSCTRL_DMA_MSB _u(6) +#define ACCESSCTRL_BUSCTRL_DMA_LSB _u(6) +#define ACCESSCTRL_BUSCTRL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_CORE1 +// Description : If 1, BUSCTRL can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_BUSCTRL_CORE1_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_BUSCTRL_CORE1_MSB _u(5) +#define ACCESSCTRL_BUSCTRL_CORE1_LSB _u(5) +#define ACCESSCTRL_BUSCTRL_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_CORE0 +// Description : If 1, BUSCTRL can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_BUSCTRL_CORE0_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_BUSCTRL_CORE0_MSB _u(4) +#define ACCESSCTRL_BUSCTRL_CORE0_LSB _u(4) +#define ACCESSCTRL_BUSCTRL_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_SP +// Description : If 1, BUSCTRL can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_BUSCTRL_SP_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_SP_BITS _u(0x00000008) +#define ACCESSCTRL_BUSCTRL_SP_MSB _u(3) +#define ACCESSCTRL_BUSCTRL_SP_LSB _u(3) +#define ACCESSCTRL_BUSCTRL_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_SU +// Description : If 1, and SP is also set, BUSCTRL can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_BUSCTRL_SU_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_SU_BITS _u(0x00000004) +#define ACCESSCTRL_BUSCTRL_SU_MSB _u(2) +#define ACCESSCTRL_BUSCTRL_SU_LSB _u(2) +#define ACCESSCTRL_BUSCTRL_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_NSP +// Description : If 1, BUSCTRL can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_BUSCTRL_NSP_RESET _u(0x0) +#define ACCESSCTRL_BUSCTRL_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_BUSCTRL_NSP_MSB _u(1) +#define ACCESSCTRL_BUSCTRL_NSP_LSB _u(1) +#define ACCESSCTRL_BUSCTRL_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_NSU +// Description : If 1, and NSP is also set, BUSCTRL can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_BUSCTRL_NSU_RESET _u(0x0) +#define ACCESSCTRL_BUSCTRL_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_BUSCTRL_NSU_MSB _u(0) +#define ACCESSCTRL_BUSCTRL_NSU_LSB _u(0) +#define ACCESSCTRL_BUSCTRL_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_ADC0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// ADC0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_ADC0_OFFSET _u(0x0000007c) +#define ACCESSCTRL_ADC0_BITS _u(0x000000ff) +#define ACCESSCTRL_ADC0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_DBG +// Description : If 1, ADC0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_ADC0_DBG_RESET _u(0x1) +#define ACCESSCTRL_ADC0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_ADC0_DBG_MSB _u(7) +#define ACCESSCTRL_ADC0_DBG_LSB _u(7) +#define ACCESSCTRL_ADC0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_DMA +// Description : If 1, ADC0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ADC0_DMA_RESET _u(0x1) +#define ACCESSCTRL_ADC0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_ADC0_DMA_MSB _u(6) +#define ACCESSCTRL_ADC0_DMA_LSB _u(6) +#define ACCESSCTRL_ADC0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_CORE1 +// Description : If 1, ADC0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ADC0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_ADC0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_ADC0_CORE1_MSB _u(5) +#define ACCESSCTRL_ADC0_CORE1_LSB _u(5) +#define ACCESSCTRL_ADC0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_CORE0 +// Description : If 1, ADC0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ADC0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_ADC0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_ADC0_CORE0_MSB _u(4) +#define ACCESSCTRL_ADC0_CORE0_LSB _u(4) +#define ACCESSCTRL_ADC0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_SP +// Description : If 1, ADC0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_ADC0_SP_RESET _u(0x1) +#define ACCESSCTRL_ADC0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_ADC0_SP_MSB _u(3) +#define ACCESSCTRL_ADC0_SP_LSB _u(3) +#define ACCESSCTRL_ADC0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_SU +// Description : If 1, and SP is also set, ADC0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_ADC0_SU_RESET _u(0x1) +#define ACCESSCTRL_ADC0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_ADC0_SU_MSB _u(2) +#define ACCESSCTRL_ADC0_SU_LSB _u(2) +#define ACCESSCTRL_ADC0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_NSP +// Description : If 1, ADC0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_ADC0_NSP_RESET _u(0x0) +#define ACCESSCTRL_ADC0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_ADC0_NSP_MSB _u(1) +#define ACCESSCTRL_ADC0_NSP_LSB _u(1) +#define ACCESSCTRL_ADC0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_NSU +// Description : If 1, and NSP is also set, ADC0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_ADC0_NSU_RESET _u(0x0) +#define ACCESSCTRL_ADC0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_ADC0_NSU_MSB _u(0) +#define ACCESSCTRL_ADC0_NSU_LSB _u(0) +#define ACCESSCTRL_ADC0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_HSTX +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// HSTX, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_HSTX_OFFSET _u(0x00000080) +#define ACCESSCTRL_HSTX_BITS _u(0x000000ff) +#define ACCESSCTRL_HSTX_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_DBG +// Description : If 1, HSTX can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_HSTX_DBG_RESET _u(0x1) +#define ACCESSCTRL_HSTX_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_HSTX_DBG_MSB _u(7) +#define ACCESSCTRL_HSTX_DBG_LSB _u(7) +#define ACCESSCTRL_HSTX_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_DMA +// Description : If 1, HSTX can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_HSTX_DMA_RESET _u(0x1) +#define ACCESSCTRL_HSTX_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_HSTX_DMA_MSB _u(6) +#define ACCESSCTRL_HSTX_DMA_LSB _u(6) +#define ACCESSCTRL_HSTX_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_CORE1 +// Description : If 1, HSTX can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_HSTX_CORE1_RESET _u(0x1) +#define ACCESSCTRL_HSTX_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_HSTX_CORE1_MSB _u(5) +#define ACCESSCTRL_HSTX_CORE1_LSB _u(5) +#define ACCESSCTRL_HSTX_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_CORE0 +// Description : If 1, HSTX can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_HSTX_CORE0_RESET _u(0x1) +#define ACCESSCTRL_HSTX_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_HSTX_CORE0_MSB _u(4) +#define ACCESSCTRL_HSTX_CORE0_LSB _u(4) +#define ACCESSCTRL_HSTX_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_SP +// Description : If 1, HSTX can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_HSTX_SP_RESET _u(0x1) +#define ACCESSCTRL_HSTX_SP_BITS _u(0x00000008) +#define ACCESSCTRL_HSTX_SP_MSB _u(3) +#define ACCESSCTRL_HSTX_SP_LSB _u(3) +#define ACCESSCTRL_HSTX_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_SU +// Description : If 1, and SP is also set, HSTX can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_HSTX_SU_RESET _u(0x1) +#define ACCESSCTRL_HSTX_SU_BITS _u(0x00000004) +#define ACCESSCTRL_HSTX_SU_MSB _u(2) +#define ACCESSCTRL_HSTX_SU_LSB _u(2) +#define ACCESSCTRL_HSTX_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_NSP +// Description : If 1, HSTX can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_HSTX_NSP_RESET _u(0x0) +#define ACCESSCTRL_HSTX_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_HSTX_NSP_MSB _u(1) +#define ACCESSCTRL_HSTX_NSP_LSB _u(1) +#define ACCESSCTRL_HSTX_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_NSU +// Description : If 1, and NSP is also set, HSTX can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_HSTX_NSU_RESET _u(0x0) +#define ACCESSCTRL_HSTX_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_HSTX_NSU_MSB _u(0) +#define ACCESSCTRL_HSTX_NSU_LSB _u(0) +#define ACCESSCTRL_HSTX_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_I2C0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// I2C0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_I2C0_OFFSET _u(0x00000084) +#define ACCESSCTRL_I2C0_BITS _u(0x000000ff) +#define ACCESSCTRL_I2C0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_DBG +// Description : If 1, I2C0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_I2C0_DBG_RESET _u(0x1) +#define ACCESSCTRL_I2C0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_I2C0_DBG_MSB _u(7) +#define ACCESSCTRL_I2C0_DBG_LSB _u(7) +#define ACCESSCTRL_I2C0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_DMA +// Description : If 1, I2C0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C0_DMA_RESET _u(0x1) +#define ACCESSCTRL_I2C0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_I2C0_DMA_MSB _u(6) +#define ACCESSCTRL_I2C0_DMA_LSB _u(6) +#define ACCESSCTRL_I2C0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_CORE1 +// Description : If 1, I2C0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_I2C0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_I2C0_CORE1_MSB _u(5) +#define ACCESSCTRL_I2C0_CORE1_LSB _u(5) +#define ACCESSCTRL_I2C0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_CORE0 +// Description : If 1, I2C0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_I2C0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_I2C0_CORE0_MSB _u(4) +#define ACCESSCTRL_I2C0_CORE0_LSB _u(4) +#define ACCESSCTRL_I2C0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_SP +// Description : If 1, I2C0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_I2C0_SP_RESET _u(0x1) +#define ACCESSCTRL_I2C0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_I2C0_SP_MSB _u(3) +#define ACCESSCTRL_I2C0_SP_LSB _u(3) +#define ACCESSCTRL_I2C0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_SU +// Description : If 1, and SP is also set, I2C0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_I2C0_SU_RESET _u(0x1) +#define ACCESSCTRL_I2C0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_I2C0_SU_MSB _u(2) +#define ACCESSCTRL_I2C0_SU_LSB _u(2) +#define ACCESSCTRL_I2C0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_NSP +// Description : If 1, I2C0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_I2C0_NSP_RESET _u(0x0) +#define ACCESSCTRL_I2C0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_I2C0_NSP_MSB _u(1) +#define ACCESSCTRL_I2C0_NSP_LSB _u(1) +#define ACCESSCTRL_I2C0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_NSU +// Description : If 1, and NSP is also set, I2C0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_I2C0_NSU_RESET _u(0x0) +#define ACCESSCTRL_I2C0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_I2C0_NSU_MSB _u(0) +#define ACCESSCTRL_I2C0_NSU_LSB _u(0) +#define ACCESSCTRL_I2C0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_I2C1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// I2C1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_I2C1_OFFSET _u(0x00000088) +#define ACCESSCTRL_I2C1_BITS _u(0x000000ff) +#define ACCESSCTRL_I2C1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_DBG +// Description : If 1, I2C1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_I2C1_DBG_RESET _u(0x1) +#define ACCESSCTRL_I2C1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_I2C1_DBG_MSB _u(7) +#define ACCESSCTRL_I2C1_DBG_LSB _u(7) +#define ACCESSCTRL_I2C1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_DMA +// Description : If 1, I2C1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C1_DMA_RESET _u(0x1) +#define ACCESSCTRL_I2C1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_I2C1_DMA_MSB _u(6) +#define ACCESSCTRL_I2C1_DMA_LSB _u(6) +#define ACCESSCTRL_I2C1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_CORE1 +// Description : If 1, I2C1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_I2C1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_I2C1_CORE1_MSB _u(5) +#define ACCESSCTRL_I2C1_CORE1_LSB _u(5) +#define ACCESSCTRL_I2C1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_CORE0 +// Description : If 1, I2C1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_I2C1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_I2C1_CORE0_MSB _u(4) +#define ACCESSCTRL_I2C1_CORE0_LSB _u(4) +#define ACCESSCTRL_I2C1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_SP +// Description : If 1, I2C1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_I2C1_SP_RESET _u(0x1) +#define ACCESSCTRL_I2C1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_I2C1_SP_MSB _u(3) +#define ACCESSCTRL_I2C1_SP_LSB _u(3) +#define ACCESSCTRL_I2C1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_SU +// Description : If 1, and SP is also set, I2C1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_I2C1_SU_RESET _u(0x1) +#define ACCESSCTRL_I2C1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_I2C1_SU_MSB _u(2) +#define ACCESSCTRL_I2C1_SU_LSB _u(2) +#define ACCESSCTRL_I2C1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_NSP +// Description : If 1, I2C1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_I2C1_NSP_RESET _u(0x0) +#define ACCESSCTRL_I2C1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_I2C1_NSP_MSB _u(1) +#define ACCESSCTRL_I2C1_NSP_LSB _u(1) +#define ACCESSCTRL_I2C1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_NSU +// Description : If 1, and NSP is also set, I2C1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_I2C1_NSU_RESET _u(0x0) +#define ACCESSCTRL_I2C1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_I2C1_NSU_MSB _u(0) +#define ACCESSCTRL_I2C1_NSU_LSB _u(0) +#define ACCESSCTRL_I2C1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PWM +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PWM, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PWM_OFFSET _u(0x0000008c) +#define ACCESSCTRL_PWM_BITS _u(0x000000ff) +#define ACCESSCTRL_PWM_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_DBG +// Description : If 1, PWM can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PWM_DBG_RESET _u(0x1) +#define ACCESSCTRL_PWM_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PWM_DBG_MSB _u(7) +#define ACCESSCTRL_PWM_DBG_LSB _u(7) +#define ACCESSCTRL_PWM_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_DMA +// Description : If 1, PWM can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PWM_DMA_RESET _u(0x1) +#define ACCESSCTRL_PWM_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PWM_DMA_MSB _u(6) +#define ACCESSCTRL_PWM_DMA_LSB _u(6) +#define ACCESSCTRL_PWM_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_CORE1 +// Description : If 1, PWM can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PWM_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PWM_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PWM_CORE1_MSB _u(5) +#define ACCESSCTRL_PWM_CORE1_LSB _u(5) +#define ACCESSCTRL_PWM_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_CORE0 +// Description : If 1, PWM can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PWM_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PWM_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PWM_CORE0_MSB _u(4) +#define ACCESSCTRL_PWM_CORE0_LSB _u(4) +#define ACCESSCTRL_PWM_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_SP +// Description : If 1, PWM can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PWM_SP_RESET _u(0x1) +#define ACCESSCTRL_PWM_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PWM_SP_MSB _u(3) +#define ACCESSCTRL_PWM_SP_LSB _u(3) +#define ACCESSCTRL_PWM_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_SU +// Description : If 1, and SP is also set, PWM can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PWM_SU_RESET _u(0x1) +#define ACCESSCTRL_PWM_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PWM_SU_MSB _u(2) +#define ACCESSCTRL_PWM_SU_LSB _u(2) +#define ACCESSCTRL_PWM_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_NSP +// Description : If 1, PWM can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PWM_NSP_RESET _u(0x0) +#define ACCESSCTRL_PWM_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PWM_NSP_MSB _u(1) +#define ACCESSCTRL_PWM_NSP_LSB _u(1) +#define ACCESSCTRL_PWM_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_NSU +// Description : If 1, and NSP is also set, PWM can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PWM_NSU_RESET _u(0x0) +#define ACCESSCTRL_PWM_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PWM_NSU_MSB _u(0) +#define ACCESSCTRL_PWM_NSU_LSB _u(0) +#define ACCESSCTRL_PWM_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SPI0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SPI0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SPI0_OFFSET _u(0x00000090) +#define ACCESSCTRL_SPI0_BITS _u(0x000000ff) +#define ACCESSCTRL_SPI0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_DBG +// Description : If 1, SPI0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SPI0_DBG_RESET _u(0x1) +#define ACCESSCTRL_SPI0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SPI0_DBG_MSB _u(7) +#define ACCESSCTRL_SPI0_DBG_LSB _u(7) +#define ACCESSCTRL_SPI0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_DMA +// Description : If 1, SPI0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI0_DMA_RESET _u(0x1) +#define ACCESSCTRL_SPI0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SPI0_DMA_MSB _u(6) +#define ACCESSCTRL_SPI0_DMA_LSB _u(6) +#define ACCESSCTRL_SPI0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_CORE1 +// Description : If 1, SPI0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SPI0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SPI0_CORE1_MSB _u(5) +#define ACCESSCTRL_SPI0_CORE1_LSB _u(5) +#define ACCESSCTRL_SPI0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_CORE0 +// Description : If 1, SPI0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SPI0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SPI0_CORE0_MSB _u(4) +#define ACCESSCTRL_SPI0_CORE0_LSB _u(4) +#define ACCESSCTRL_SPI0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_SP +// Description : If 1, SPI0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SPI0_SP_RESET _u(0x1) +#define ACCESSCTRL_SPI0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SPI0_SP_MSB _u(3) +#define ACCESSCTRL_SPI0_SP_LSB _u(3) +#define ACCESSCTRL_SPI0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_SU +// Description : If 1, and SP is also set, SPI0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SPI0_SU_RESET _u(0x1) +#define ACCESSCTRL_SPI0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SPI0_SU_MSB _u(2) +#define ACCESSCTRL_SPI0_SU_LSB _u(2) +#define ACCESSCTRL_SPI0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_NSP +// Description : If 1, SPI0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SPI0_NSP_RESET _u(0x0) +#define ACCESSCTRL_SPI0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SPI0_NSP_MSB _u(1) +#define ACCESSCTRL_SPI0_NSP_LSB _u(1) +#define ACCESSCTRL_SPI0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_NSU +// Description : If 1, and NSP is also set, SPI0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SPI0_NSU_RESET _u(0x0) +#define ACCESSCTRL_SPI0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SPI0_NSU_MSB _u(0) +#define ACCESSCTRL_SPI0_NSU_LSB _u(0) +#define ACCESSCTRL_SPI0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SPI1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SPI1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SPI1_OFFSET _u(0x00000094) +#define ACCESSCTRL_SPI1_BITS _u(0x000000ff) +#define ACCESSCTRL_SPI1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_DBG +// Description : If 1, SPI1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SPI1_DBG_RESET _u(0x1) +#define ACCESSCTRL_SPI1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SPI1_DBG_MSB _u(7) +#define ACCESSCTRL_SPI1_DBG_LSB _u(7) +#define ACCESSCTRL_SPI1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_DMA +// Description : If 1, SPI1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI1_DMA_RESET _u(0x1) +#define ACCESSCTRL_SPI1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SPI1_DMA_MSB _u(6) +#define ACCESSCTRL_SPI1_DMA_LSB _u(6) +#define ACCESSCTRL_SPI1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_CORE1 +// Description : If 1, SPI1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SPI1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SPI1_CORE1_MSB _u(5) +#define ACCESSCTRL_SPI1_CORE1_LSB _u(5) +#define ACCESSCTRL_SPI1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_CORE0 +// Description : If 1, SPI1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SPI1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SPI1_CORE0_MSB _u(4) +#define ACCESSCTRL_SPI1_CORE0_LSB _u(4) +#define ACCESSCTRL_SPI1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_SP +// Description : If 1, SPI1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SPI1_SP_RESET _u(0x1) +#define ACCESSCTRL_SPI1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SPI1_SP_MSB _u(3) +#define ACCESSCTRL_SPI1_SP_LSB _u(3) +#define ACCESSCTRL_SPI1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_SU +// Description : If 1, and SP is also set, SPI1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SPI1_SU_RESET _u(0x1) +#define ACCESSCTRL_SPI1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SPI1_SU_MSB _u(2) +#define ACCESSCTRL_SPI1_SU_LSB _u(2) +#define ACCESSCTRL_SPI1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_NSP +// Description : If 1, SPI1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SPI1_NSP_RESET _u(0x0) +#define ACCESSCTRL_SPI1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SPI1_NSP_MSB _u(1) +#define ACCESSCTRL_SPI1_NSP_LSB _u(1) +#define ACCESSCTRL_SPI1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_NSU +// Description : If 1, and NSP is also set, SPI1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SPI1_NSU_RESET _u(0x0) +#define ACCESSCTRL_SPI1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SPI1_NSU_MSB _u(0) +#define ACCESSCTRL_SPI1_NSU_LSB _u(0) +#define ACCESSCTRL_SPI1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TIMER0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TIMER0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TIMER0_OFFSET _u(0x00000098) +#define ACCESSCTRL_TIMER0_BITS _u(0x000000ff) +#define ACCESSCTRL_TIMER0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_DBG +// Description : If 1, TIMER0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TIMER0_DBG_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TIMER0_DBG_MSB _u(7) +#define ACCESSCTRL_TIMER0_DBG_LSB _u(7) +#define ACCESSCTRL_TIMER0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_DMA +// Description : If 1, TIMER0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER0_DMA_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TIMER0_DMA_MSB _u(6) +#define ACCESSCTRL_TIMER0_DMA_LSB _u(6) +#define ACCESSCTRL_TIMER0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_CORE1 +// Description : If 1, TIMER0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TIMER0_CORE1_MSB _u(5) +#define ACCESSCTRL_TIMER0_CORE1_LSB _u(5) +#define ACCESSCTRL_TIMER0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_CORE0 +// Description : If 1, TIMER0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TIMER0_CORE0_MSB _u(4) +#define ACCESSCTRL_TIMER0_CORE0_LSB _u(4) +#define ACCESSCTRL_TIMER0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_SP +// Description : If 1, TIMER0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TIMER0_SP_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TIMER0_SP_MSB _u(3) +#define ACCESSCTRL_TIMER0_SP_LSB _u(3) +#define ACCESSCTRL_TIMER0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_SU +// Description : If 1, and SP is also set, TIMER0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TIMER0_SU_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TIMER0_SU_MSB _u(2) +#define ACCESSCTRL_TIMER0_SU_LSB _u(2) +#define ACCESSCTRL_TIMER0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_NSP +// Description : If 1, TIMER0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TIMER0_NSP_RESET _u(0x0) +#define ACCESSCTRL_TIMER0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TIMER0_NSP_MSB _u(1) +#define ACCESSCTRL_TIMER0_NSP_LSB _u(1) +#define ACCESSCTRL_TIMER0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_NSU +// Description : If 1, and NSP is also set, TIMER0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TIMER0_NSU_RESET _u(0x0) +#define ACCESSCTRL_TIMER0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TIMER0_NSU_MSB _u(0) +#define ACCESSCTRL_TIMER0_NSU_LSB _u(0) +#define ACCESSCTRL_TIMER0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TIMER1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TIMER1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TIMER1_OFFSET _u(0x0000009c) +#define ACCESSCTRL_TIMER1_BITS _u(0x000000ff) +#define ACCESSCTRL_TIMER1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_DBG +// Description : If 1, TIMER1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TIMER1_DBG_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TIMER1_DBG_MSB _u(7) +#define ACCESSCTRL_TIMER1_DBG_LSB _u(7) +#define ACCESSCTRL_TIMER1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_DMA +// Description : If 1, TIMER1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER1_DMA_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TIMER1_DMA_MSB _u(6) +#define ACCESSCTRL_TIMER1_DMA_LSB _u(6) +#define ACCESSCTRL_TIMER1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_CORE1 +// Description : If 1, TIMER1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TIMER1_CORE1_MSB _u(5) +#define ACCESSCTRL_TIMER1_CORE1_LSB _u(5) +#define ACCESSCTRL_TIMER1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_CORE0 +// Description : If 1, TIMER1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TIMER1_CORE0_MSB _u(4) +#define ACCESSCTRL_TIMER1_CORE0_LSB _u(4) +#define ACCESSCTRL_TIMER1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_SP +// Description : If 1, TIMER1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TIMER1_SP_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TIMER1_SP_MSB _u(3) +#define ACCESSCTRL_TIMER1_SP_LSB _u(3) +#define ACCESSCTRL_TIMER1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_SU +// Description : If 1, and SP is also set, TIMER1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TIMER1_SU_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TIMER1_SU_MSB _u(2) +#define ACCESSCTRL_TIMER1_SU_LSB _u(2) +#define ACCESSCTRL_TIMER1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_NSP +// Description : If 1, TIMER1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TIMER1_NSP_RESET _u(0x0) +#define ACCESSCTRL_TIMER1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TIMER1_NSP_MSB _u(1) +#define ACCESSCTRL_TIMER1_NSP_LSB _u(1) +#define ACCESSCTRL_TIMER1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_NSU +// Description : If 1, and NSP is also set, TIMER1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TIMER1_NSU_RESET _u(0x0) +#define ACCESSCTRL_TIMER1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TIMER1_NSU_MSB _u(0) +#define ACCESSCTRL_TIMER1_NSU_LSB _u(0) +#define ACCESSCTRL_TIMER1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_UART0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// UART0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_UART0_OFFSET _u(0x000000a0) +#define ACCESSCTRL_UART0_BITS _u(0x000000ff) +#define ACCESSCTRL_UART0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_DBG +// Description : If 1, UART0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_UART0_DBG_RESET _u(0x1) +#define ACCESSCTRL_UART0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_UART0_DBG_MSB _u(7) +#define ACCESSCTRL_UART0_DBG_LSB _u(7) +#define ACCESSCTRL_UART0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_DMA +// Description : If 1, UART0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART0_DMA_RESET _u(0x1) +#define ACCESSCTRL_UART0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_UART0_DMA_MSB _u(6) +#define ACCESSCTRL_UART0_DMA_LSB _u(6) +#define ACCESSCTRL_UART0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_CORE1 +// Description : If 1, UART0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_UART0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_UART0_CORE1_MSB _u(5) +#define ACCESSCTRL_UART0_CORE1_LSB _u(5) +#define ACCESSCTRL_UART0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_CORE0 +// Description : If 1, UART0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_UART0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_UART0_CORE0_MSB _u(4) +#define ACCESSCTRL_UART0_CORE0_LSB _u(4) +#define ACCESSCTRL_UART0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_SP +// Description : If 1, UART0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_UART0_SP_RESET _u(0x1) +#define ACCESSCTRL_UART0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_UART0_SP_MSB _u(3) +#define ACCESSCTRL_UART0_SP_LSB _u(3) +#define ACCESSCTRL_UART0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_SU +// Description : If 1, and SP is also set, UART0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_UART0_SU_RESET _u(0x1) +#define ACCESSCTRL_UART0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_UART0_SU_MSB _u(2) +#define ACCESSCTRL_UART0_SU_LSB _u(2) +#define ACCESSCTRL_UART0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_NSP +// Description : If 1, UART0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_UART0_NSP_RESET _u(0x0) +#define ACCESSCTRL_UART0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_UART0_NSP_MSB _u(1) +#define ACCESSCTRL_UART0_NSP_LSB _u(1) +#define ACCESSCTRL_UART0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_NSU +// Description : If 1, and NSP is also set, UART0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_UART0_NSU_RESET _u(0x0) +#define ACCESSCTRL_UART0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_UART0_NSU_MSB _u(0) +#define ACCESSCTRL_UART0_NSU_LSB _u(0) +#define ACCESSCTRL_UART0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_UART1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// UART1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_UART1_OFFSET _u(0x000000a4) +#define ACCESSCTRL_UART1_BITS _u(0x000000ff) +#define ACCESSCTRL_UART1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_DBG +// Description : If 1, UART1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_UART1_DBG_RESET _u(0x1) +#define ACCESSCTRL_UART1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_UART1_DBG_MSB _u(7) +#define ACCESSCTRL_UART1_DBG_LSB _u(7) +#define ACCESSCTRL_UART1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_DMA +// Description : If 1, UART1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART1_DMA_RESET _u(0x1) +#define ACCESSCTRL_UART1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_UART1_DMA_MSB _u(6) +#define ACCESSCTRL_UART1_DMA_LSB _u(6) +#define ACCESSCTRL_UART1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_CORE1 +// Description : If 1, UART1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_UART1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_UART1_CORE1_MSB _u(5) +#define ACCESSCTRL_UART1_CORE1_LSB _u(5) +#define ACCESSCTRL_UART1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_CORE0 +// Description : If 1, UART1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_UART1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_UART1_CORE0_MSB _u(4) +#define ACCESSCTRL_UART1_CORE0_LSB _u(4) +#define ACCESSCTRL_UART1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_SP +// Description : If 1, UART1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_UART1_SP_RESET _u(0x1) +#define ACCESSCTRL_UART1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_UART1_SP_MSB _u(3) +#define ACCESSCTRL_UART1_SP_LSB _u(3) +#define ACCESSCTRL_UART1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_SU +// Description : If 1, and SP is also set, UART1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_UART1_SU_RESET _u(0x1) +#define ACCESSCTRL_UART1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_UART1_SU_MSB _u(2) +#define ACCESSCTRL_UART1_SU_LSB _u(2) +#define ACCESSCTRL_UART1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_NSP +// Description : If 1, UART1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_UART1_NSP_RESET _u(0x0) +#define ACCESSCTRL_UART1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_UART1_NSP_MSB _u(1) +#define ACCESSCTRL_UART1_NSP_LSB _u(1) +#define ACCESSCTRL_UART1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_NSU +// Description : If 1, and NSP is also set, UART1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_UART1_NSU_RESET _u(0x0) +#define ACCESSCTRL_UART1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_UART1_NSU_MSB _u(0) +#define ACCESSCTRL_UART1_NSU_LSB _u(0) +#define ACCESSCTRL_UART1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_OTP +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// OTP, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_OTP_OFFSET _u(0x000000a8) +#define ACCESSCTRL_OTP_BITS _u(0x000000ff) +#define ACCESSCTRL_OTP_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_DBG +// Description : If 1, OTP can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_OTP_DBG_RESET _u(0x1) +#define ACCESSCTRL_OTP_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_OTP_DBG_MSB _u(7) +#define ACCESSCTRL_OTP_DBG_LSB _u(7) +#define ACCESSCTRL_OTP_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_DMA +// Description : If 1, OTP can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_OTP_DMA_RESET _u(0x1) +#define ACCESSCTRL_OTP_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_OTP_DMA_MSB _u(6) +#define ACCESSCTRL_OTP_DMA_LSB _u(6) +#define ACCESSCTRL_OTP_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_CORE1 +// Description : If 1, OTP can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_OTP_CORE1_RESET _u(0x1) +#define ACCESSCTRL_OTP_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_OTP_CORE1_MSB _u(5) +#define ACCESSCTRL_OTP_CORE1_LSB _u(5) +#define ACCESSCTRL_OTP_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_CORE0 +// Description : If 1, OTP can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_OTP_CORE0_RESET _u(0x1) +#define ACCESSCTRL_OTP_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_OTP_CORE0_MSB _u(4) +#define ACCESSCTRL_OTP_CORE0_LSB _u(4) +#define ACCESSCTRL_OTP_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_SP +// Description : If 1, OTP can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_OTP_SP_RESET _u(0x1) +#define ACCESSCTRL_OTP_SP_BITS _u(0x00000008) +#define ACCESSCTRL_OTP_SP_MSB _u(3) +#define ACCESSCTRL_OTP_SP_LSB _u(3) +#define ACCESSCTRL_OTP_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_SU +// Description : If 1, and SP is also set, OTP can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_OTP_SU_RESET _u(0x1) +#define ACCESSCTRL_OTP_SU_BITS _u(0x00000004) +#define ACCESSCTRL_OTP_SU_MSB _u(2) +#define ACCESSCTRL_OTP_SU_LSB _u(2) +#define ACCESSCTRL_OTP_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_NSP +// Description : If 1, OTP can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_OTP_NSP_RESET _u(0x0) +#define ACCESSCTRL_OTP_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_OTP_NSP_MSB _u(1) +#define ACCESSCTRL_OTP_NSP_LSB _u(1) +#define ACCESSCTRL_OTP_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_NSU +// Description : If 1, and NSP is also set, OTP can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_OTP_NSU_RESET _u(0x0) +#define ACCESSCTRL_OTP_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_OTP_NSU_MSB _u(0) +#define ACCESSCTRL_OTP_NSU_LSB _u(0) +#define ACCESSCTRL_OTP_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TBMAN +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TBMAN, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TBMAN_OFFSET _u(0x000000ac) +#define ACCESSCTRL_TBMAN_BITS _u(0x000000ff) +#define ACCESSCTRL_TBMAN_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_DBG +// Description : If 1, TBMAN can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TBMAN_DBG_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TBMAN_DBG_MSB _u(7) +#define ACCESSCTRL_TBMAN_DBG_LSB _u(7) +#define ACCESSCTRL_TBMAN_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_DMA +// Description : If 1, TBMAN can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TBMAN_DMA_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TBMAN_DMA_MSB _u(6) +#define ACCESSCTRL_TBMAN_DMA_LSB _u(6) +#define ACCESSCTRL_TBMAN_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_CORE1 +// Description : If 1, TBMAN can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TBMAN_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TBMAN_CORE1_MSB _u(5) +#define ACCESSCTRL_TBMAN_CORE1_LSB _u(5) +#define ACCESSCTRL_TBMAN_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_CORE0 +// Description : If 1, TBMAN can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TBMAN_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TBMAN_CORE0_MSB _u(4) +#define ACCESSCTRL_TBMAN_CORE0_LSB _u(4) +#define ACCESSCTRL_TBMAN_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_SP +// Description : If 1, TBMAN can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TBMAN_SP_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TBMAN_SP_MSB _u(3) +#define ACCESSCTRL_TBMAN_SP_LSB _u(3) +#define ACCESSCTRL_TBMAN_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_SU +// Description : If 1, and SP is also set, TBMAN can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TBMAN_SU_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TBMAN_SU_MSB _u(2) +#define ACCESSCTRL_TBMAN_SU_LSB _u(2) +#define ACCESSCTRL_TBMAN_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_NSP +// Description : If 1, TBMAN can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TBMAN_NSP_RESET _u(0x0) +#define ACCESSCTRL_TBMAN_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TBMAN_NSP_MSB _u(1) +#define ACCESSCTRL_TBMAN_NSP_LSB _u(1) +#define ACCESSCTRL_TBMAN_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_NSU +// Description : If 1, and NSP is also set, TBMAN can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TBMAN_NSU_RESET _u(0x0) +#define ACCESSCTRL_TBMAN_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TBMAN_NSU_MSB _u(0) +#define ACCESSCTRL_TBMAN_NSU_LSB _u(0) +#define ACCESSCTRL_TBMAN_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_POWMAN +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// POWMAN, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_POWMAN_OFFSET _u(0x000000b0) +#define ACCESSCTRL_POWMAN_BITS _u(0x000000ff) +#define ACCESSCTRL_POWMAN_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_DBG +// Description : If 1, POWMAN can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_POWMAN_DBG_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_POWMAN_DBG_MSB _u(7) +#define ACCESSCTRL_POWMAN_DBG_LSB _u(7) +#define ACCESSCTRL_POWMAN_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_DMA +// Description : If 1, POWMAN can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_POWMAN_DMA_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_POWMAN_DMA_MSB _u(6) +#define ACCESSCTRL_POWMAN_DMA_LSB _u(6) +#define ACCESSCTRL_POWMAN_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_CORE1 +// Description : If 1, POWMAN can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_POWMAN_CORE1_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_POWMAN_CORE1_MSB _u(5) +#define ACCESSCTRL_POWMAN_CORE1_LSB _u(5) +#define ACCESSCTRL_POWMAN_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_CORE0 +// Description : If 1, POWMAN can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_POWMAN_CORE0_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_POWMAN_CORE0_MSB _u(4) +#define ACCESSCTRL_POWMAN_CORE0_LSB _u(4) +#define ACCESSCTRL_POWMAN_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_SP +// Description : If 1, POWMAN can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_POWMAN_SP_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_SP_BITS _u(0x00000008) +#define ACCESSCTRL_POWMAN_SP_MSB _u(3) +#define ACCESSCTRL_POWMAN_SP_LSB _u(3) +#define ACCESSCTRL_POWMAN_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_SU +// Description : If 1, and SP is also set, POWMAN can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_POWMAN_SU_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_SU_BITS _u(0x00000004) +#define ACCESSCTRL_POWMAN_SU_MSB _u(2) +#define ACCESSCTRL_POWMAN_SU_LSB _u(2) +#define ACCESSCTRL_POWMAN_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_NSP +// Description : If 1, POWMAN can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_POWMAN_NSP_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_POWMAN_NSP_MSB _u(1) +#define ACCESSCTRL_POWMAN_NSP_LSB _u(1) +#define ACCESSCTRL_POWMAN_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_NSU +// Description : If 1, and NSP is also set, POWMAN can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_POWMAN_NSU_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_POWMAN_NSU_MSB _u(0) +#define ACCESSCTRL_POWMAN_NSU_LSB _u(0) +#define ACCESSCTRL_POWMAN_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TRNG +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TRNG, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TRNG_OFFSET _u(0x000000b4) +#define ACCESSCTRL_TRNG_BITS _u(0x000000ff) +#define ACCESSCTRL_TRNG_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_DBG +// Description : If 1, TRNG can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TRNG_DBG_RESET _u(0x1) +#define ACCESSCTRL_TRNG_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TRNG_DBG_MSB _u(7) +#define ACCESSCTRL_TRNG_DBG_LSB _u(7) +#define ACCESSCTRL_TRNG_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_DMA +// Description : If 1, TRNG can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TRNG_DMA_RESET _u(0x0) +#define ACCESSCTRL_TRNG_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TRNG_DMA_MSB _u(6) +#define ACCESSCTRL_TRNG_DMA_LSB _u(6) +#define ACCESSCTRL_TRNG_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_CORE1 +// Description : If 1, TRNG can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TRNG_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TRNG_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TRNG_CORE1_MSB _u(5) +#define ACCESSCTRL_TRNG_CORE1_LSB _u(5) +#define ACCESSCTRL_TRNG_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_CORE0 +// Description : If 1, TRNG can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TRNG_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TRNG_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TRNG_CORE0_MSB _u(4) +#define ACCESSCTRL_TRNG_CORE0_LSB _u(4) +#define ACCESSCTRL_TRNG_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_SP +// Description : If 1, TRNG can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TRNG_SP_RESET _u(0x1) +#define ACCESSCTRL_TRNG_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TRNG_SP_MSB _u(3) +#define ACCESSCTRL_TRNG_SP_LSB _u(3) +#define ACCESSCTRL_TRNG_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_SU +// Description : If 1, and SP is also set, TRNG can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TRNG_SU_RESET _u(0x0) +#define ACCESSCTRL_TRNG_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TRNG_SU_MSB _u(2) +#define ACCESSCTRL_TRNG_SU_LSB _u(2) +#define ACCESSCTRL_TRNG_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_NSP +// Description : If 1, TRNG can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TRNG_NSP_RESET _u(0x0) +#define ACCESSCTRL_TRNG_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TRNG_NSP_MSB _u(1) +#define ACCESSCTRL_TRNG_NSP_LSB _u(1) +#define ACCESSCTRL_TRNG_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_NSU +// Description : If 1, and NSP is also set, TRNG can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TRNG_NSU_RESET _u(0x0) +#define ACCESSCTRL_TRNG_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TRNG_NSU_MSB _u(0) +#define ACCESSCTRL_TRNG_NSU_LSB _u(0) +#define ACCESSCTRL_TRNG_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SHA256 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SHA256, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SHA256_OFFSET _u(0x000000b8) +#define ACCESSCTRL_SHA256_BITS _u(0x000000ff) +#define ACCESSCTRL_SHA256_RESET _u(0x000000f8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_DBG +// Description : If 1, SHA256 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SHA256_DBG_RESET _u(0x1) +#define ACCESSCTRL_SHA256_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SHA256_DBG_MSB _u(7) +#define ACCESSCTRL_SHA256_DBG_LSB _u(7) +#define ACCESSCTRL_SHA256_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_DMA +// Description : If 1, SHA256 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SHA256_DMA_RESET _u(0x1) +#define ACCESSCTRL_SHA256_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SHA256_DMA_MSB _u(6) +#define ACCESSCTRL_SHA256_DMA_LSB _u(6) +#define ACCESSCTRL_SHA256_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_CORE1 +// Description : If 1, SHA256 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SHA256_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SHA256_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SHA256_CORE1_MSB _u(5) +#define ACCESSCTRL_SHA256_CORE1_LSB _u(5) +#define ACCESSCTRL_SHA256_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_CORE0 +// Description : If 1, SHA256 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SHA256_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SHA256_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SHA256_CORE0_MSB _u(4) +#define ACCESSCTRL_SHA256_CORE0_LSB _u(4) +#define ACCESSCTRL_SHA256_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_SP +// Description : If 1, SHA256 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SHA256_SP_RESET _u(0x1) +#define ACCESSCTRL_SHA256_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SHA256_SP_MSB _u(3) +#define ACCESSCTRL_SHA256_SP_LSB _u(3) +#define ACCESSCTRL_SHA256_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_SU +// Description : If 1, and SP is also set, SHA256 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SHA256_SU_RESET _u(0x0) +#define ACCESSCTRL_SHA256_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SHA256_SU_MSB _u(2) +#define ACCESSCTRL_SHA256_SU_LSB _u(2) +#define ACCESSCTRL_SHA256_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_NSP +// Description : If 1, SHA256 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SHA256_NSP_RESET _u(0x0) +#define ACCESSCTRL_SHA256_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SHA256_NSP_MSB _u(1) +#define ACCESSCTRL_SHA256_NSP_LSB _u(1) +#define ACCESSCTRL_SHA256_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_NSU +// Description : If 1, and NSP is also set, SHA256 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SHA256_NSU_RESET _u(0x0) +#define ACCESSCTRL_SHA256_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SHA256_NSU_MSB _u(0) +#define ACCESSCTRL_SHA256_NSU_LSB _u(0) +#define ACCESSCTRL_SHA256_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SYSCFG +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SYSCFG, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SYSCFG_OFFSET _u(0x000000bc) +#define ACCESSCTRL_SYSCFG_BITS _u(0x000000ff) +#define ACCESSCTRL_SYSCFG_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_DBG +// Description : If 1, SYSCFG can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SYSCFG_DBG_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SYSCFG_DBG_MSB _u(7) +#define ACCESSCTRL_SYSCFG_DBG_LSB _u(7) +#define ACCESSCTRL_SYSCFG_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_DMA +// Description : If 1, SYSCFG can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSCFG_DMA_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SYSCFG_DMA_MSB _u(6) +#define ACCESSCTRL_SYSCFG_DMA_LSB _u(6) +#define ACCESSCTRL_SYSCFG_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_CORE1 +// Description : If 1, SYSCFG can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSCFG_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SYSCFG_CORE1_MSB _u(5) +#define ACCESSCTRL_SYSCFG_CORE1_LSB _u(5) +#define ACCESSCTRL_SYSCFG_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_CORE0 +// Description : If 1, SYSCFG can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSCFG_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SYSCFG_CORE0_MSB _u(4) +#define ACCESSCTRL_SYSCFG_CORE0_LSB _u(4) +#define ACCESSCTRL_SYSCFG_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_SP +// Description : If 1, SYSCFG can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SYSCFG_SP_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SYSCFG_SP_MSB _u(3) +#define ACCESSCTRL_SYSCFG_SP_LSB _u(3) +#define ACCESSCTRL_SYSCFG_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_SU +// Description : If 1, and SP is also set, SYSCFG can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SYSCFG_SU_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SYSCFG_SU_MSB _u(2) +#define ACCESSCTRL_SYSCFG_SU_LSB _u(2) +#define ACCESSCTRL_SYSCFG_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_NSP +// Description : If 1, SYSCFG can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SYSCFG_NSP_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SYSCFG_NSP_MSB _u(1) +#define ACCESSCTRL_SYSCFG_NSP_LSB _u(1) +#define ACCESSCTRL_SYSCFG_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_NSU +// Description : If 1, and NSP is also set, SYSCFG can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SYSCFG_NSU_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SYSCFG_NSU_MSB _u(0) +#define ACCESSCTRL_SYSCFG_NSU_LSB _u(0) +#define ACCESSCTRL_SYSCFG_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CLOCKS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// CLOCKS, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_CLOCKS_OFFSET _u(0x000000c0) +#define ACCESSCTRL_CLOCKS_BITS _u(0x000000ff) +#define ACCESSCTRL_CLOCKS_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_DBG +// Description : If 1, CLOCKS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CLOCKS_DBG_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_CLOCKS_DBG_MSB _u(7) +#define ACCESSCTRL_CLOCKS_DBG_LSB _u(7) +#define ACCESSCTRL_CLOCKS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_DMA +// Description : If 1, CLOCKS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_CLOCKS_DMA_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_CLOCKS_DMA_MSB _u(6) +#define ACCESSCTRL_CLOCKS_DMA_LSB _u(6) +#define ACCESSCTRL_CLOCKS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_CORE1 +// Description : If 1, CLOCKS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_CLOCKS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_CLOCKS_CORE1_MSB _u(5) +#define ACCESSCTRL_CLOCKS_CORE1_LSB _u(5) +#define ACCESSCTRL_CLOCKS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_CORE0 +// Description : If 1, CLOCKS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_CLOCKS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_CLOCKS_CORE0_MSB _u(4) +#define ACCESSCTRL_CLOCKS_CORE0_LSB _u(4) +#define ACCESSCTRL_CLOCKS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_SP +// Description : If 1, CLOCKS can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_CLOCKS_SP_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_CLOCKS_SP_MSB _u(3) +#define ACCESSCTRL_CLOCKS_SP_LSB _u(3) +#define ACCESSCTRL_CLOCKS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_SU +// Description : If 1, and SP is also set, CLOCKS can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_CLOCKS_SU_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_CLOCKS_SU_MSB _u(2) +#define ACCESSCTRL_CLOCKS_SU_LSB _u(2) +#define ACCESSCTRL_CLOCKS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_NSP +// Description : If 1, CLOCKS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_CLOCKS_NSP_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_CLOCKS_NSP_MSB _u(1) +#define ACCESSCTRL_CLOCKS_NSP_LSB _u(1) +#define ACCESSCTRL_CLOCKS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_NSU +// Description : If 1, and NSP is also set, CLOCKS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_CLOCKS_NSU_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_CLOCKS_NSU_MSB _u(0) +#define ACCESSCTRL_CLOCKS_NSU_LSB _u(0) +#define ACCESSCTRL_CLOCKS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XOSC +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XOSC, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XOSC_OFFSET _u(0x000000c4) +#define ACCESSCTRL_XOSC_BITS _u(0x000000ff) +#define ACCESSCTRL_XOSC_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_DBG +// Description : If 1, XOSC can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XOSC_DBG_RESET _u(0x1) +#define ACCESSCTRL_XOSC_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XOSC_DBG_MSB _u(7) +#define ACCESSCTRL_XOSC_DBG_LSB _u(7) +#define ACCESSCTRL_XOSC_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_DMA +// Description : If 1, XOSC can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XOSC_DMA_RESET _u(0x0) +#define ACCESSCTRL_XOSC_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XOSC_DMA_MSB _u(6) +#define ACCESSCTRL_XOSC_DMA_LSB _u(6) +#define ACCESSCTRL_XOSC_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_CORE1 +// Description : If 1, XOSC can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XOSC_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XOSC_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XOSC_CORE1_MSB _u(5) +#define ACCESSCTRL_XOSC_CORE1_LSB _u(5) +#define ACCESSCTRL_XOSC_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_CORE0 +// Description : If 1, XOSC can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XOSC_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XOSC_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XOSC_CORE0_MSB _u(4) +#define ACCESSCTRL_XOSC_CORE0_LSB _u(4) +#define ACCESSCTRL_XOSC_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_SP +// Description : If 1, XOSC can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_XOSC_SP_RESET _u(0x1) +#define ACCESSCTRL_XOSC_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XOSC_SP_MSB _u(3) +#define ACCESSCTRL_XOSC_SP_LSB _u(3) +#define ACCESSCTRL_XOSC_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_SU +// Description : If 1, and SP is also set, XOSC can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_XOSC_SU_RESET _u(0x0) +#define ACCESSCTRL_XOSC_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XOSC_SU_MSB _u(2) +#define ACCESSCTRL_XOSC_SU_LSB _u(2) +#define ACCESSCTRL_XOSC_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_NSP +// Description : If 1, XOSC can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XOSC_NSP_RESET _u(0x0) +#define ACCESSCTRL_XOSC_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XOSC_NSP_MSB _u(1) +#define ACCESSCTRL_XOSC_NSP_LSB _u(1) +#define ACCESSCTRL_XOSC_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_NSU +// Description : If 1, and NSP is also set, XOSC can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XOSC_NSU_RESET _u(0x0) +#define ACCESSCTRL_XOSC_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XOSC_NSU_MSB _u(0) +#define ACCESSCTRL_XOSC_NSU_LSB _u(0) +#define ACCESSCTRL_XOSC_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_ROSC +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// ROSC, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_ROSC_OFFSET _u(0x000000c8) +#define ACCESSCTRL_ROSC_BITS _u(0x000000ff) +#define ACCESSCTRL_ROSC_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_DBG +// Description : If 1, ROSC can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_ROSC_DBG_RESET _u(0x1) +#define ACCESSCTRL_ROSC_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_ROSC_DBG_MSB _u(7) +#define ACCESSCTRL_ROSC_DBG_LSB _u(7) +#define ACCESSCTRL_ROSC_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_DMA +// Description : If 1, ROSC can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROSC_DMA_RESET _u(0x0) +#define ACCESSCTRL_ROSC_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_ROSC_DMA_MSB _u(6) +#define ACCESSCTRL_ROSC_DMA_LSB _u(6) +#define ACCESSCTRL_ROSC_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_CORE1 +// Description : If 1, ROSC can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROSC_CORE1_RESET _u(0x1) +#define ACCESSCTRL_ROSC_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_ROSC_CORE1_MSB _u(5) +#define ACCESSCTRL_ROSC_CORE1_LSB _u(5) +#define ACCESSCTRL_ROSC_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_CORE0 +// Description : If 1, ROSC can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROSC_CORE0_RESET _u(0x1) +#define ACCESSCTRL_ROSC_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_ROSC_CORE0_MSB _u(4) +#define ACCESSCTRL_ROSC_CORE0_LSB _u(4) +#define ACCESSCTRL_ROSC_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_SP +// Description : If 1, ROSC can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_ROSC_SP_RESET _u(0x1) +#define ACCESSCTRL_ROSC_SP_BITS _u(0x00000008) +#define ACCESSCTRL_ROSC_SP_MSB _u(3) +#define ACCESSCTRL_ROSC_SP_LSB _u(3) +#define ACCESSCTRL_ROSC_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_SU +// Description : If 1, and SP is also set, ROSC can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_ROSC_SU_RESET _u(0x0) +#define ACCESSCTRL_ROSC_SU_BITS _u(0x00000004) +#define ACCESSCTRL_ROSC_SU_MSB _u(2) +#define ACCESSCTRL_ROSC_SU_LSB _u(2) +#define ACCESSCTRL_ROSC_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_NSP +// Description : If 1, ROSC can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_ROSC_NSP_RESET _u(0x0) +#define ACCESSCTRL_ROSC_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_ROSC_NSP_MSB _u(1) +#define ACCESSCTRL_ROSC_NSP_LSB _u(1) +#define ACCESSCTRL_ROSC_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_NSU +// Description : If 1, and NSP is also set, ROSC can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_ROSC_NSU_RESET _u(0x0) +#define ACCESSCTRL_ROSC_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_ROSC_NSU_MSB _u(0) +#define ACCESSCTRL_ROSC_NSU_LSB _u(0) +#define ACCESSCTRL_ROSC_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PLL_SYS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PLL_SYS, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PLL_SYS_OFFSET _u(0x000000cc) +#define ACCESSCTRL_PLL_SYS_BITS _u(0x000000ff) +#define ACCESSCTRL_PLL_SYS_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_DBG +// Description : If 1, PLL_SYS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PLL_SYS_DBG_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PLL_SYS_DBG_MSB _u(7) +#define ACCESSCTRL_PLL_SYS_DBG_LSB _u(7) +#define ACCESSCTRL_PLL_SYS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_DMA +// Description : If 1, PLL_SYS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_SYS_DMA_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PLL_SYS_DMA_MSB _u(6) +#define ACCESSCTRL_PLL_SYS_DMA_LSB _u(6) +#define ACCESSCTRL_PLL_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_CORE1 +// Description : If 1, PLL_SYS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_SYS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PLL_SYS_CORE1_MSB _u(5) +#define ACCESSCTRL_PLL_SYS_CORE1_LSB _u(5) +#define ACCESSCTRL_PLL_SYS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_CORE0 +// Description : If 1, PLL_SYS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_SYS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PLL_SYS_CORE0_MSB _u(4) +#define ACCESSCTRL_PLL_SYS_CORE0_LSB _u(4) +#define ACCESSCTRL_PLL_SYS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_SP +// Description : If 1, PLL_SYS can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PLL_SYS_SP_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PLL_SYS_SP_MSB _u(3) +#define ACCESSCTRL_PLL_SYS_SP_LSB _u(3) +#define ACCESSCTRL_PLL_SYS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_SU +// Description : If 1, and SP is also set, PLL_SYS can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PLL_SYS_SU_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PLL_SYS_SU_MSB _u(2) +#define ACCESSCTRL_PLL_SYS_SU_LSB _u(2) +#define ACCESSCTRL_PLL_SYS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_NSP +// Description : If 1, PLL_SYS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PLL_SYS_NSP_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PLL_SYS_NSP_MSB _u(1) +#define ACCESSCTRL_PLL_SYS_NSP_LSB _u(1) +#define ACCESSCTRL_PLL_SYS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_NSU +// Description : If 1, and NSP is also set, PLL_SYS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PLL_SYS_NSU_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PLL_SYS_NSU_MSB _u(0) +#define ACCESSCTRL_PLL_SYS_NSU_LSB _u(0) +#define ACCESSCTRL_PLL_SYS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PLL_USB +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PLL_USB, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PLL_USB_OFFSET _u(0x000000d0) +#define ACCESSCTRL_PLL_USB_BITS _u(0x000000ff) +#define ACCESSCTRL_PLL_USB_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_DBG +// Description : If 1, PLL_USB can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PLL_USB_DBG_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PLL_USB_DBG_MSB _u(7) +#define ACCESSCTRL_PLL_USB_DBG_LSB _u(7) +#define ACCESSCTRL_PLL_USB_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_DMA +// Description : If 1, PLL_USB can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_USB_DMA_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PLL_USB_DMA_MSB _u(6) +#define ACCESSCTRL_PLL_USB_DMA_LSB _u(6) +#define ACCESSCTRL_PLL_USB_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_CORE1 +// Description : If 1, PLL_USB can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_USB_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PLL_USB_CORE1_MSB _u(5) +#define ACCESSCTRL_PLL_USB_CORE1_LSB _u(5) +#define ACCESSCTRL_PLL_USB_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_CORE0 +// Description : If 1, PLL_USB can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_USB_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PLL_USB_CORE0_MSB _u(4) +#define ACCESSCTRL_PLL_USB_CORE0_LSB _u(4) +#define ACCESSCTRL_PLL_USB_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_SP +// Description : If 1, PLL_USB can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PLL_USB_SP_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PLL_USB_SP_MSB _u(3) +#define ACCESSCTRL_PLL_USB_SP_LSB _u(3) +#define ACCESSCTRL_PLL_USB_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_SU +// Description : If 1, and SP is also set, PLL_USB can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PLL_USB_SU_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PLL_USB_SU_MSB _u(2) +#define ACCESSCTRL_PLL_USB_SU_LSB _u(2) +#define ACCESSCTRL_PLL_USB_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_NSP +// Description : If 1, PLL_USB can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PLL_USB_NSP_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PLL_USB_NSP_MSB _u(1) +#define ACCESSCTRL_PLL_USB_NSP_LSB _u(1) +#define ACCESSCTRL_PLL_USB_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_NSU +// Description : If 1, and NSP is also set, PLL_USB can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PLL_USB_NSU_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PLL_USB_NSU_MSB _u(0) +#define ACCESSCTRL_PLL_USB_NSU_LSB _u(0) +#define ACCESSCTRL_PLL_USB_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TICKS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TICKS, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TICKS_OFFSET _u(0x000000d4) +#define ACCESSCTRL_TICKS_BITS _u(0x000000ff) +#define ACCESSCTRL_TICKS_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_DBG +// Description : If 1, TICKS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TICKS_DBG_RESET _u(0x1) +#define ACCESSCTRL_TICKS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TICKS_DBG_MSB _u(7) +#define ACCESSCTRL_TICKS_DBG_LSB _u(7) +#define ACCESSCTRL_TICKS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_DMA +// Description : If 1, TICKS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TICKS_DMA_RESET _u(0x0) +#define ACCESSCTRL_TICKS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TICKS_DMA_MSB _u(6) +#define ACCESSCTRL_TICKS_DMA_LSB _u(6) +#define ACCESSCTRL_TICKS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_CORE1 +// Description : If 1, TICKS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TICKS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TICKS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TICKS_CORE1_MSB _u(5) +#define ACCESSCTRL_TICKS_CORE1_LSB _u(5) +#define ACCESSCTRL_TICKS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_CORE0 +// Description : If 1, TICKS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TICKS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TICKS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TICKS_CORE0_MSB _u(4) +#define ACCESSCTRL_TICKS_CORE0_LSB _u(4) +#define ACCESSCTRL_TICKS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_SP +// Description : If 1, TICKS can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TICKS_SP_RESET _u(0x1) +#define ACCESSCTRL_TICKS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TICKS_SP_MSB _u(3) +#define ACCESSCTRL_TICKS_SP_LSB _u(3) +#define ACCESSCTRL_TICKS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_SU +// Description : If 1, and SP is also set, TICKS can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TICKS_SU_RESET _u(0x0) +#define ACCESSCTRL_TICKS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TICKS_SU_MSB _u(2) +#define ACCESSCTRL_TICKS_SU_LSB _u(2) +#define ACCESSCTRL_TICKS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_NSP +// Description : If 1, TICKS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TICKS_NSP_RESET _u(0x0) +#define ACCESSCTRL_TICKS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TICKS_NSP_MSB _u(1) +#define ACCESSCTRL_TICKS_NSP_LSB _u(1) +#define ACCESSCTRL_TICKS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_NSU +// Description : If 1, and NSP is also set, TICKS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TICKS_NSU_RESET _u(0x0) +#define ACCESSCTRL_TICKS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TICKS_NSU_MSB _u(0) +#define ACCESSCTRL_TICKS_NSU_LSB _u(0) +#define ACCESSCTRL_TICKS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_WATCHDOG +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// WATCHDOG, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_WATCHDOG_OFFSET _u(0x000000d8) +#define ACCESSCTRL_WATCHDOG_BITS _u(0x000000ff) +#define ACCESSCTRL_WATCHDOG_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_DBG +// Description : If 1, WATCHDOG can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_WATCHDOG_DBG_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_WATCHDOG_DBG_MSB _u(7) +#define ACCESSCTRL_WATCHDOG_DBG_LSB _u(7) +#define ACCESSCTRL_WATCHDOG_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_DMA +// Description : If 1, WATCHDOG can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_WATCHDOG_DMA_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_WATCHDOG_DMA_MSB _u(6) +#define ACCESSCTRL_WATCHDOG_DMA_LSB _u(6) +#define ACCESSCTRL_WATCHDOG_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_CORE1 +// Description : If 1, WATCHDOG can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_WATCHDOG_CORE1_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_WATCHDOG_CORE1_MSB _u(5) +#define ACCESSCTRL_WATCHDOG_CORE1_LSB _u(5) +#define ACCESSCTRL_WATCHDOG_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_CORE0 +// Description : If 1, WATCHDOG can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_WATCHDOG_CORE0_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_WATCHDOG_CORE0_MSB _u(4) +#define ACCESSCTRL_WATCHDOG_CORE0_LSB _u(4) +#define ACCESSCTRL_WATCHDOG_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_SP +// Description : If 1, WATCHDOG can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_WATCHDOG_SP_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_SP_BITS _u(0x00000008) +#define ACCESSCTRL_WATCHDOG_SP_MSB _u(3) +#define ACCESSCTRL_WATCHDOG_SP_LSB _u(3) +#define ACCESSCTRL_WATCHDOG_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_SU +// Description : If 1, and SP is also set, WATCHDOG can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_WATCHDOG_SU_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_SU_BITS _u(0x00000004) +#define ACCESSCTRL_WATCHDOG_SU_MSB _u(2) +#define ACCESSCTRL_WATCHDOG_SU_LSB _u(2) +#define ACCESSCTRL_WATCHDOG_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_NSP +// Description : If 1, WATCHDOG can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_WATCHDOG_NSP_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_WATCHDOG_NSP_MSB _u(1) +#define ACCESSCTRL_WATCHDOG_NSP_LSB _u(1) +#define ACCESSCTRL_WATCHDOG_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_NSU +// Description : If 1, and NSP is also set, WATCHDOG can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_WATCHDOG_NSU_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_WATCHDOG_NSU_MSB _u(0) +#define ACCESSCTRL_WATCHDOG_NSU_LSB _u(0) +#define ACCESSCTRL_WATCHDOG_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_RSM +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// RSM, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_RSM_OFFSET _u(0x000000dc) +#define ACCESSCTRL_RSM_BITS _u(0x000000ff) +#define ACCESSCTRL_RSM_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_DBG +// Description : If 1, RSM can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_RSM_DBG_RESET _u(0x1) +#define ACCESSCTRL_RSM_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_RSM_DBG_MSB _u(7) +#define ACCESSCTRL_RSM_DBG_LSB _u(7) +#define ACCESSCTRL_RSM_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_DMA +// Description : If 1, RSM can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RSM_DMA_RESET _u(0x0) +#define ACCESSCTRL_RSM_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_RSM_DMA_MSB _u(6) +#define ACCESSCTRL_RSM_DMA_LSB _u(6) +#define ACCESSCTRL_RSM_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_CORE1 +// Description : If 1, RSM can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RSM_CORE1_RESET _u(0x1) +#define ACCESSCTRL_RSM_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_RSM_CORE1_MSB _u(5) +#define ACCESSCTRL_RSM_CORE1_LSB _u(5) +#define ACCESSCTRL_RSM_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_CORE0 +// Description : If 1, RSM can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RSM_CORE0_RESET _u(0x1) +#define ACCESSCTRL_RSM_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_RSM_CORE0_MSB _u(4) +#define ACCESSCTRL_RSM_CORE0_LSB _u(4) +#define ACCESSCTRL_RSM_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_SP +// Description : If 1, RSM can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_RSM_SP_RESET _u(0x1) +#define ACCESSCTRL_RSM_SP_BITS _u(0x00000008) +#define ACCESSCTRL_RSM_SP_MSB _u(3) +#define ACCESSCTRL_RSM_SP_LSB _u(3) +#define ACCESSCTRL_RSM_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_SU +// Description : If 1, and SP is also set, RSM can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_RSM_SU_RESET _u(0x0) +#define ACCESSCTRL_RSM_SU_BITS _u(0x00000004) +#define ACCESSCTRL_RSM_SU_MSB _u(2) +#define ACCESSCTRL_RSM_SU_LSB _u(2) +#define ACCESSCTRL_RSM_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_NSP +// Description : If 1, RSM can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_RSM_NSP_RESET _u(0x0) +#define ACCESSCTRL_RSM_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_RSM_NSP_MSB _u(1) +#define ACCESSCTRL_RSM_NSP_LSB _u(1) +#define ACCESSCTRL_RSM_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_NSU +// Description : If 1, and NSP is also set, RSM can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_RSM_NSU_RESET _u(0x0) +#define ACCESSCTRL_RSM_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_RSM_NSU_MSB _u(0) +#define ACCESSCTRL_RSM_NSU_LSB _u(0) +#define ACCESSCTRL_RSM_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_CTRL +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_CTRL, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_CTRL_OFFSET _u(0x000000e0) +#define ACCESSCTRL_XIP_CTRL_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_CTRL_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_DBG +// Description : If 1, XIP_CTRL can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_CTRL_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_CTRL_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_CTRL_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_CTRL_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_DMA +// Description : If 1, XIP_CTRL can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_CTRL_DMA_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_CTRL_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_CTRL_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_CTRL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_CORE1 +// Description : If 1, XIP_CTRL can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_CTRL_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_CTRL_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_CTRL_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_CTRL_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_CORE0 +// Description : If 1, XIP_CTRL can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_CTRL_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_CTRL_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_CTRL_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_CTRL_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_SP +// Description : If 1, XIP_CTRL can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_CTRL_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_CTRL_SP_MSB _u(3) +#define ACCESSCTRL_XIP_CTRL_SP_LSB _u(3) +#define ACCESSCTRL_XIP_CTRL_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_SU +// Description : If 1, and SP is also set, XIP_CTRL can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_CTRL_SU_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_CTRL_SU_MSB _u(2) +#define ACCESSCTRL_XIP_CTRL_SU_LSB _u(2) +#define ACCESSCTRL_XIP_CTRL_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_NSP +// Description : If 1, XIP_CTRL can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_CTRL_NSP_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_CTRL_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_CTRL_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_CTRL_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_NSU +// Description : If 1, and NSP is also set, XIP_CTRL can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_CTRL_NSU_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_CTRL_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_CTRL_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_CTRL_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_QMI +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_QMI, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_QMI_OFFSET _u(0x000000e4) +#define ACCESSCTRL_XIP_QMI_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_QMI_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_DBG +// Description : If 1, XIP_QMI can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_QMI_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_QMI_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_QMI_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_QMI_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_DMA +// Description : If 1, XIP_QMI can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_QMI_DMA_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_QMI_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_QMI_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_QMI_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_CORE1 +// Description : If 1, XIP_QMI can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_QMI_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_QMI_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_QMI_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_QMI_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_CORE0 +// Description : If 1, XIP_QMI can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_QMI_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_QMI_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_QMI_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_QMI_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_SP +// Description : If 1, XIP_QMI can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_QMI_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_QMI_SP_MSB _u(3) +#define ACCESSCTRL_XIP_QMI_SP_LSB _u(3) +#define ACCESSCTRL_XIP_QMI_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_SU +// Description : If 1, and SP is also set, XIP_QMI can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_QMI_SU_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_QMI_SU_MSB _u(2) +#define ACCESSCTRL_XIP_QMI_SU_LSB _u(2) +#define ACCESSCTRL_XIP_QMI_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_NSP +// Description : If 1, XIP_QMI can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_QMI_NSP_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_QMI_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_QMI_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_QMI_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_NSU +// Description : If 1, and NSP is also set, XIP_QMI can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_QMI_NSU_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_QMI_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_QMI_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_QMI_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_AUX +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_AUX, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_AUX_OFFSET _u(0x000000e8) +#define ACCESSCTRL_XIP_AUX_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_AUX_RESET _u(0x000000f8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_DBG +// Description : If 1, XIP_AUX can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_AUX_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_AUX_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_AUX_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_AUX_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_DMA +// Description : If 1, XIP_AUX can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_AUX_DMA_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_AUX_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_AUX_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_AUX_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_CORE1 +// Description : If 1, XIP_AUX can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_AUX_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_AUX_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_AUX_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_AUX_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_CORE0 +// Description : If 1, XIP_AUX can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_AUX_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_AUX_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_AUX_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_AUX_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_SP +// Description : If 1, XIP_AUX can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_AUX_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_AUX_SP_MSB _u(3) +#define ACCESSCTRL_XIP_AUX_SP_LSB _u(3) +#define ACCESSCTRL_XIP_AUX_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_SU +// Description : If 1, and SP is also set, XIP_AUX can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_AUX_SU_RESET _u(0x0) +#define ACCESSCTRL_XIP_AUX_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_AUX_SU_MSB _u(2) +#define ACCESSCTRL_XIP_AUX_SU_LSB _u(2) +#define ACCESSCTRL_XIP_AUX_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_NSP +// Description : If 1, XIP_AUX can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_AUX_NSP_RESET _u(0x0) +#define ACCESSCTRL_XIP_AUX_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_AUX_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_AUX_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_AUX_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_NSU +// Description : If 1, and NSP is also set, XIP_AUX can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_AUX_NSU_RESET _u(0x0) +#define ACCESSCTRL_XIP_AUX_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_AUX_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_AUX_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_AUX_NSU_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_ACCESSCTRL_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/adc.h b/src/rp2350/hardware_regs/include/hardware/regs/adc.h new file mode 100644 index 000000000..1778d502d --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/adc.h @@ -0,0 +1,316 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ADC +// Version : 2 +// Bus type : apb +// Description : Control and data interface to SAR ADC +// ============================================================================= +#ifndef _HARDWARE_REGS_ADC_H +#define _HARDWARE_REGS_ADC_H +// ============================================================================= +// Register : ADC_CS +// Description : ADC Control and Status +#define ADC_CS_OFFSET _u(0x00000000) +#define ADC_CS_BITS _u(0x01fff70f) +#define ADC_CS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_CS_RROBIN +// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to +// disable. +// Otherwise, the ADC will cycle through each enabled channel in a +// round-robin fashion. +// The first channel to be sampled will be the one currently +// indicated by AINSEL. +// AINSEL will be updated after each conversion with the newly- +// selected channel. +#define ADC_CS_RROBIN_RESET _u(0x000) +#define ADC_CS_RROBIN_BITS _u(0x01ff0000) +#define ADC_CS_RROBIN_MSB _u(24) +#define ADC_CS_RROBIN_LSB _u(16) +#define ADC_CS_RROBIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_AINSEL +// Description : Select analog mux input. Updated automatically in round-robin +// mode. +// This is corrected for the package option so only ADC channels +// which are bonded are available, and in the correct order +#define ADC_CS_AINSEL_RESET _u(0x0) +#define ADC_CS_AINSEL_BITS _u(0x0000f000) +#define ADC_CS_AINSEL_MSB _u(15) +#define ADC_CS_AINSEL_LSB _u(12) +#define ADC_CS_AINSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR_STICKY +// Description : Some past ADC conversion encountered an error. Write 1 to +// clear. +#define ADC_CS_ERR_STICKY_RESET _u(0x0) +#define ADC_CS_ERR_STICKY_BITS _u(0x00000400) +#define ADC_CS_ERR_STICKY_MSB _u(10) +#define ADC_CS_ERR_STICKY_LSB _u(10) +#define ADC_CS_ERR_STICKY_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR +// Description : The most recent ADC conversion encountered an error; result is +// undefined or noisy. +#define ADC_CS_ERR_RESET _u(0x0) +#define ADC_CS_ERR_BITS _u(0x00000200) +#define ADC_CS_ERR_MSB _u(9) +#define ADC_CS_ERR_LSB _u(9) +#define ADC_CS_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_READY +// Description : 1 if the ADC is ready to start a new conversion. Implies any +// previous conversion has completed. +// 0 whilst conversion in progress. +#define ADC_CS_READY_RESET _u(0x0) +#define ADC_CS_READY_BITS _u(0x00000100) +#define ADC_CS_READY_MSB _u(8) +#define ADC_CS_READY_LSB _u(8) +#define ADC_CS_READY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_MANY +// Description : Continuously perform conversions whilst this bit is 1. A new +// conversion will start immediately after the previous finishes. +#define ADC_CS_START_MANY_RESET _u(0x0) +#define ADC_CS_START_MANY_BITS _u(0x00000008) +#define ADC_CS_START_MANY_MSB _u(3) +#define ADC_CS_START_MANY_LSB _u(3) +#define ADC_CS_START_MANY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_ONCE +// Description : Start a single conversion. Self-clearing. Ignored if start_many +// is asserted. +#define ADC_CS_START_ONCE_RESET _u(0x0) +#define ADC_CS_START_ONCE_BITS _u(0x00000004) +#define ADC_CS_START_ONCE_MSB _u(2) +#define ADC_CS_START_ONCE_LSB _u(2) +#define ADC_CS_START_ONCE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_TS_EN +// Description : Power on temperature sensor. 1 - enabled. 0 - disabled. +#define ADC_CS_TS_EN_RESET _u(0x0) +#define ADC_CS_TS_EN_BITS _u(0x00000002) +#define ADC_CS_TS_EN_MSB _u(1) +#define ADC_CS_TS_EN_LSB _u(1) +#define ADC_CS_TS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_EN +// Description : Power on ADC and enable its clock. +// 1 - enabled. 0 - disabled. +#define ADC_CS_EN_RESET _u(0x0) +#define ADC_CS_EN_BITS _u(0x00000001) +#define ADC_CS_EN_MSB _u(0) +#define ADC_CS_EN_LSB _u(0) +#define ADC_CS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_RESULT +// Description : Result of most recent ADC conversion +#define ADC_RESULT_OFFSET _u(0x00000004) +#define ADC_RESULT_BITS _u(0x00000fff) +#define ADC_RESULT_RESET _u(0x00000000) +#define ADC_RESULT_MSB _u(11) +#define ADC_RESULT_LSB _u(0) +#define ADC_RESULT_ACCESS "RO" +// ============================================================================= +// Register : ADC_FCS +// Description : FIFO control and status +#define ADC_FCS_OFFSET _u(0x00000008) +#define ADC_FCS_BITS _u(0x0f0f0f0f) +#define ADC_FCS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_THRESH +// Description : DREQ/IRQ asserted when level >= threshold +#define ADC_FCS_THRESH_RESET _u(0x0) +#define ADC_FCS_THRESH_BITS _u(0x0f000000) +#define ADC_FCS_THRESH_MSB _u(27) +#define ADC_FCS_THRESH_LSB _u(24) +#define ADC_FCS_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_LEVEL +// Description : The number of conversion results currently waiting in the FIFO +#define ADC_FCS_LEVEL_RESET _u(0x0) +#define ADC_FCS_LEVEL_BITS _u(0x000f0000) +#define ADC_FCS_LEVEL_MSB _u(19) +#define ADC_FCS_LEVEL_LSB _u(16) +#define ADC_FCS_LEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_OVER +// Description : 1 if the FIFO has been overflowed. Write 1 to clear. +#define ADC_FCS_OVER_RESET _u(0x0) +#define ADC_FCS_OVER_BITS _u(0x00000800) +#define ADC_FCS_OVER_MSB _u(11) +#define ADC_FCS_OVER_LSB _u(11) +#define ADC_FCS_OVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_UNDER +// Description : 1 if the FIFO has been underflowed. Write 1 to clear. +#define ADC_FCS_UNDER_RESET _u(0x0) +#define ADC_FCS_UNDER_BITS _u(0x00000400) +#define ADC_FCS_UNDER_MSB _u(10) +#define ADC_FCS_UNDER_LSB _u(10) +#define ADC_FCS_UNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_FULL +#define ADC_FCS_FULL_RESET _u(0x0) +#define ADC_FCS_FULL_BITS _u(0x00000200) +#define ADC_FCS_FULL_MSB _u(9) +#define ADC_FCS_FULL_LSB _u(9) +#define ADC_FCS_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EMPTY +#define ADC_FCS_EMPTY_RESET _u(0x0) +#define ADC_FCS_EMPTY_BITS _u(0x00000100) +#define ADC_FCS_EMPTY_MSB _u(8) +#define ADC_FCS_EMPTY_LSB _u(8) +#define ADC_FCS_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_DREQ_EN +// Description : If 1: assert DMA requests when FIFO contains data +#define ADC_FCS_DREQ_EN_RESET _u(0x0) +#define ADC_FCS_DREQ_EN_BITS _u(0x00000008) +#define ADC_FCS_DREQ_EN_MSB _u(3) +#define ADC_FCS_DREQ_EN_LSB _u(3) +#define ADC_FCS_DREQ_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_ERR +// Description : If 1: conversion error bit appears in the FIFO alongside the +// result +#define ADC_FCS_ERR_RESET _u(0x0) +#define ADC_FCS_ERR_BITS _u(0x00000004) +#define ADC_FCS_ERR_MSB _u(2) +#define ADC_FCS_ERR_LSB _u(2) +#define ADC_FCS_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_SHIFT +// Description : If 1: FIFO results are right-shifted to be one byte in size. +// Enables DMA to byte buffers. +#define ADC_FCS_SHIFT_RESET _u(0x0) +#define ADC_FCS_SHIFT_BITS _u(0x00000002) +#define ADC_FCS_SHIFT_MSB _u(1) +#define ADC_FCS_SHIFT_LSB _u(1) +#define ADC_FCS_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EN +// Description : If 1: write result to the FIFO after each conversion. +#define ADC_FCS_EN_RESET _u(0x0) +#define ADC_FCS_EN_BITS _u(0x00000001) +#define ADC_FCS_EN_MSB _u(0) +#define ADC_FCS_EN_LSB _u(0) +#define ADC_FCS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_FIFO +// Description : Conversion result FIFO +#define ADC_FIFO_OFFSET _u(0x0000000c) +#define ADC_FIFO_BITS _u(0x00008fff) +#define ADC_FIFO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_ERR +// Description : 1 if this particular sample experienced a conversion error. +// Remains in the same location if the sample is shifted. +#define ADC_FIFO_ERR_RESET "-" +#define ADC_FIFO_ERR_BITS _u(0x00008000) +#define ADC_FIFO_ERR_MSB _u(15) +#define ADC_FIFO_ERR_LSB _u(15) +#define ADC_FIFO_ERR_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_VAL +#define ADC_FIFO_VAL_RESET "-" +#define ADC_FIFO_VAL_BITS _u(0x00000fff) +#define ADC_FIFO_VAL_MSB _u(11) +#define ADC_FIFO_VAL_LSB _u(0) +#define ADC_FIFO_VAL_ACCESS "RF" +// ============================================================================= +// Register : ADC_DIV +// Description : Clock divider. If non-zero, CS_START_MANY will start +// conversions +// at regular intervals rather than back-to-back. +// The divider is reset when either of these fields are written. +// Total period is 1 + INT + FRAC / 256 +#define ADC_DIV_OFFSET _u(0x00000010) +#define ADC_DIV_BITS _u(0x00ffffff) +#define ADC_DIV_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_INT +// Description : Integer part of clock divisor. +#define ADC_DIV_INT_RESET _u(0x0000) +#define ADC_DIV_INT_BITS _u(0x00ffff00) +#define ADC_DIV_INT_MSB _u(23) +#define ADC_DIV_INT_LSB _u(8) +#define ADC_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_FRAC +// Description : Fractional part of clock divisor. First-order delta-sigma. +#define ADC_DIV_FRAC_RESET _u(0x00) +#define ADC_DIV_FRAC_BITS _u(0x000000ff) +#define ADC_DIV_FRAC_MSB _u(7) +#define ADC_DIV_FRAC_LSB _u(0) +#define ADC_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTR +// Description : Raw Interrupts +#define ADC_INTR_OFFSET _u(0x00000014) +#define ADC_INTR_BITS _u(0x00000001) +#define ADC_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTR_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTR_FIFO_RESET _u(0x0) +#define ADC_INTR_FIFO_BITS _u(0x00000001) +#define ADC_INTR_FIFO_MSB _u(0) +#define ADC_INTR_FIFO_LSB _u(0) +#define ADC_INTR_FIFO_ACCESS "RO" +// ============================================================================= +// Register : ADC_INTE +// Description : Interrupt Enable +#define ADC_INTE_OFFSET _u(0x00000018) +#define ADC_INTE_BITS _u(0x00000001) +#define ADC_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTE_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTE_FIFO_RESET _u(0x0) +#define ADC_INTE_FIFO_BITS _u(0x00000001) +#define ADC_INTE_FIFO_MSB _u(0) +#define ADC_INTE_FIFO_LSB _u(0) +#define ADC_INTE_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTF +// Description : Interrupt Force +#define ADC_INTF_OFFSET _u(0x0000001c) +#define ADC_INTF_BITS _u(0x00000001) +#define ADC_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTF_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTF_FIFO_RESET _u(0x0) +#define ADC_INTF_FIFO_BITS _u(0x00000001) +#define ADC_INTF_FIFO_MSB _u(0) +#define ADC_INTF_FIFO_LSB _u(0) +#define ADC_INTF_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTS +// Description : Interrupt status after masking & forcing +#define ADC_INTS_OFFSET _u(0x00000020) +#define ADC_INTS_BITS _u(0x00000001) +#define ADC_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTS_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTS_FIFO_RESET _u(0x0) +#define ADC_INTS_FIFO_BITS _u(0x00000001) +#define ADC_INTS_FIFO_MSB _u(0) +#define ADC_INTS_FIFO_LSB _u(0) +#define ADC_INTS_FIFO_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_ADC_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/addressmap.h b/src/rp2350/hardware_regs/include/hardware/regs/addressmap.h new file mode 100644 index 000000000..0e8df5201 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/addressmap.h @@ -0,0 +1,112 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _ADDRESSMAP_H +#define _ADDRESSMAP_H + +/** + * \file rp2350/addressmap.h + */ + +#include "hardware/platform_defs.h" + +// Register address offsets for atomic RMW aliases +#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) +#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) +#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) +#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) + +#define ROM_BASE _u(0x00000000) +#define XIP_BASE _u(0x10000000) +#define XIP_SRAM_BASE _u(0x13ffc000) +#define XIP_END _u(0x14000000) +#define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000) +#define XIP_SRAM_END _u(0x14000000) +#define XIP_NOCACHE_NOALLOC_END _u(0x18000000) +#define XIP_MAINTENANCE_BASE _u(0x18000000) +#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000) +#define SRAM0_BASE _u(0x20000000) +#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000) +#define SRAM_BASE _u(0x20000000) +#define SRAM_STRIPED_BASE _u(0x20000000) +#define SRAM4_BASE _u(0x20040000) +#define SRAM8_BASE _u(0x20080000) +#define SRAM_STRIPED_END _u(0x20080000) +#define SRAM_SCRATCH_X_BASE _u(0x20080000) +#define SRAM9_BASE _u(0x20081000) +#define SRAM_SCRATCH_Y_BASE _u(0x20081000) +#define SRAM_END _u(0x20082000) +#define SYSINFO_BASE _u(0x40000000) +#define SYSCFG_BASE _u(0x40008000) +#define CLOCKS_BASE _u(0x40010000) +#define PSM_BASE _u(0x40018000) +#define RESETS_BASE _u(0x40020000) +#define IO_BANK0_BASE _u(0x40028000) +#define IO_QSPI_BASE _u(0x40030000) +#define PADS_BANK0_BASE _u(0x40038000) +#define PADS_QSPI_BASE _u(0x40040000) +#define XOSC_BASE _u(0x40048000) +#define PLL_SYS_BASE _u(0x40050000) +#define PLL_USB_BASE _u(0x40058000) +#define ACCESSCTRL_BASE _u(0x40060000) +#define BUSCTRL_BASE _u(0x40068000) +#define UART0_BASE _u(0x40070000) +#define UART1_BASE _u(0x40078000) +#define SPI0_BASE _u(0x40080000) +#define SPI1_BASE _u(0x40088000) +#define I2C0_BASE _u(0x40090000) +#define I2C1_BASE _u(0x40098000) +#define ADC_BASE _u(0x400a0000) +#define PWM_BASE _u(0x400a8000) +#define TIMER0_BASE _u(0x400b0000) +#define TIMER1_BASE _u(0x400b8000) +#define HSTX_CTRL_BASE _u(0x400c0000) +#define XIP_CTRL_BASE _u(0x400c8000) +#define XIP_QMI_BASE _u(0x400d0000) +#define WATCHDOG_BASE _u(0x400d8000) +#define BOOTRAM_BASE _u(0x400e0000) +#define BOOTRAM_END _u(0x400e0400) +#define ROSC_BASE _u(0x400e8000) +#define TRNG_BASE _u(0x400f0000) +#define SHA256_BASE _u(0x400f8000) +#define POWMAN_BASE _u(0x40100000) +#define TICKS_BASE _u(0x40108000) +#define OTP_BASE _u(0x40120000) +#define OTP_DATA_BASE _u(0x40130000) +#define OTP_DATA_RAW_BASE _u(0x40134000) +#define OTP_DATA_GUARDED_BASE _u(0x40138000) +#define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000) +#define CORESIGHT_PERIPH_BASE _u(0x40140000) +#define CORESIGHT_ROMTABLE_BASE _u(0x40140000) +#define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000) +#define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000) +#define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000) +#define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000) +#define CORESIGHT_TPIU_BASE _u(0x40148000) +#define CORESIGHT_CTI_BASE _u(0x40149000) +#define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000) +#define DFT_BASE _u(0x40150000) +#define GLITCH_DETECTOR_BASE _u(0x40158000) +#define TBMAN_BASE _u(0x40160000) +#define DMA_BASE _u(0x50000000) +#define USBCTRL_BASE _u(0x50100000) +#define USBCTRL_DPRAM_BASE _u(0x50100000) +#define USBCTRL_REGS_BASE _u(0x50110000) +#define PIO0_BASE _u(0x50200000) +#define PIO1_BASE _u(0x50300000) +#define PIO2_BASE _u(0x50400000) +#define XIP_AUX_BASE _u(0x50500000) +#define HSTX_FIFO_BASE _u(0x50600000) +#define CORESIGHT_TRACE_BASE _u(0x50700000) +#define SIO_BASE _u(0xd0000000) +#define SIO_NONSEC_BASE _u(0xd0020000) +#define PPB_BASE _u(0xe0000000) +#define PPB_NONSEC_BASE _u(0xe0020000) +#define EPPB_BASE _u(0xe0080000) + +#endif // _ADDRESSMAP_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/bootram.h b/src/rp2350/hardware_regs/include/hardware/regs/bootram.h new file mode 100644 index 000000000..0d8695cb0 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/bootram.h @@ -0,0 +1,130 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : BOOTRAM +// Version : 1 +// Bus type : apb +// Description : Additional registers mapped adjacent to the bootram, for use +// by the bootrom. +// ============================================================================= +#ifndef _HARDWARE_REGS_BOOTRAM_H +#define _HARDWARE_REGS_BOOTRAM_H +// ============================================================================= +// Register : BOOTRAM_WRITE_ONCE0 +// Description : This registers always ORs writes into its current contents. +// Once a bit is set, it can only be cleared by a reset. +#define BOOTRAM_WRITE_ONCE0_OFFSET _u(0x00000800) +#define BOOTRAM_WRITE_ONCE0_BITS _u(0xffffffff) +#define BOOTRAM_WRITE_ONCE0_RESET _u(0x00000000) +#define BOOTRAM_WRITE_ONCE0_MSB _u(31) +#define BOOTRAM_WRITE_ONCE0_LSB _u(0) +#define BOOTRAM_WRITE_ONCE0_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_WRITE_ONCE1 +// Description : This registers always ORs writes into its current contents. +// Once a bit is set, it can only be cleared by a reset. +#define BOOTRAM_WRITE_ONCE1_OFFSET _u(0x00000804) +#define BOOTRAM_WRITE_ONCE1_BITS _u(0xffffffff) +#define BOOTRAM_WRITE_ONCE1_RESET _u(0x00000000) +#define BOOTRAM_WRITE_ONCE1_MSB _u(31) +#define BOOTRAM_WRITE_ONCE1_LSB _u(0) +#define BOOTRAM_WRITE_ONCE1_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK_STAT +// Description : Bootlock status register. 1=unclaimed, 0=claimed. These locks +// function identically to the SIO spinlocks, but are reserved for +// bootrom use. +#define BOOTRAM_BOOTLOCK_STAT_OFFSET _u(0x00000808) +#define BOOTRAM_BOOTLOCK_STAT_BITS _u(0x000000ff) +#define BOOTRAM_BOOTLOCK_STAT_RESET _u(0x000000ff) +#define BOOTRAM_BOOTLOCK_STAT_MSB _u(7) +#define BOOTRAM_BOOTLOCK_STAT_LSB _u(0) +#define BOOTRAM_BOOTLOCK_STAT_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK0 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK0_OFFSET _u(0x0000080c) +#define BOOTRAM_BOOTLOCK0_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK0_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK0_MSB _u(31) +#define BOOTRAM_BOOTLOCK0_LSB _u(0) +#define BOOTRAM_BOOTLOCK0_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK1 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK1_OFFSET _u(0x00000810) +#define BOOTRAM_BOOTLOCK1_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK1_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK1_MSB _u(31) +#define BOOTRAM_BOOTLOCK1_LSB _u(0) +#define BOOTRAM_BOOTLOCK1_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK2 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK2_OFFSET _u(0x00000814) +#define BOOTRAM_BOOTLOCK2_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK2_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK2_MSB _u(31) +#define BOOTRAM_BOOTLOCK2_LSB _u(0) +#define BOOTRAM_BOOTLOCK2_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK3 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK3_OFFSET _u(0x00000818) +#define BOOTRAM_BOOTLOCK3_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK3_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK3_MSB _u(31) +#define BOOTRAM_BOOTLOCK3_LSB _u(0) +#define BOOTRAM_BOOTLOCK3_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK4 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK4_OFFSET _u(0x0000081c) +#define BOOTRAM_BOOTLOCK4_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK4_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK4_MSB _u(31) +#define BOOTRAM_BOOTLOCK4_LSB _u(0) +#define BOOTRAM_BOOTLOCK4_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK5 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK5_OFFSET _u(0x00000820) +#define BOOTRAM_BOOTLOCK5_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK5_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK5_MSB _u(31) +#define BOOTRAM_BOOTLOCK5_LSB _u(0) +#define BOOTRAM_BOOTLOCK5_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK6 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK6_OFFSET _u(0x00000824) +#define BOOTRAM_BOOTLOCK6_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK6_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK6_MSB _u(31) +#define BOOTRAM_BOOTLOCK6_LSB _u(0) +#define BOOTRAM_BOOTLOCK6_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK7 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK7_OFFSET _u(0x00000828) +#define BOOTRAM_BOOTLOCK7_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK7_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK7_MSB _u(31) +#define BOOTRAM_BOOTLOCK7_LSB _u(0) +#define BOOTRAM_BOOTLOCK7_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_BOOTRAM_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/busctrl.h b/src/rp2350/hardware_regs/include/hardware/regs/busctrl.h new file mode 100644 index 000000000..c3bf3e139 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/busctrl.h @@ -0,0 +1,753 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : BUSCTRL +// Version : 1 +// Bus type : apb +// Description : Register block for busfabric control signals and performance +// counters +// ============================================================================= +#ifndef _HARDWARE_REGS_BUSCTRL_H +#define _HARDWARE_REGS_BUSCTRL_H +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY +// Description : Set the priority of each master for bus arbitration. +#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111) +#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_W +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000) +#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12) +#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12) +#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_R +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100) +#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8) +#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8) +#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC1 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010) +#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4) +#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4) +#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC0 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0) +#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY_ACK +// Description : Bus priority acknowledge +// Goes to 1 once all arbiters have registered the new global +// priority levels. +// Arbiters update their local priority when servicing a new +// nonsequential access. +// In normal circumstances this will happen almost immediately. +#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004) +#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0) +#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" +// ============================================================================= +// Register : BUSCTRL_PERFCTR_EN +// Description : Enable the performance counters. If 0, the performance counters +// do not increment. This can be used to precisely start/stop +// event sampling around the profiled section of code. +// +// The performance counters are initially disabled, to save +// energy. +#define BUSCTRL_PERFCTR_EN_OFFSET _u(0x00000008) +#define BUSCTRL_PERFCTR_EN_BITS _u(0x00000001) +#define BUSCTRL_PERFCTR_EN_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR_EN_MSB _u(0) +#define BUSCTRL_PERFCTR_EN_LSB _u(0) +#define BUSCTRL_PERFCTR_EN_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR0 +// Description : Bus fabric performance counter 0 +// Busfabric saturating performance counter 0 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL0 +#define BUSCTRL_PERFCTR0_OFFSET _u(0x0000000c) +#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR0_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR0_MSB _u(23) +#define BUSCTRL_PERFCTR0_LSB _u(0) +#define BUSCTRL_PERFCTR0_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL0 +// Description : Bus fabric performance event select for PERFCTR0 +// Select an event for PERFCTR0. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL0_OFFSET _u(0x00000010) +#define BUSCTRL_PERFSEL0_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL0_MSB _u(6) +#define BUSCTRL_PERFSEL0_LSB _u(0) +#define BUSCTRL_PERFSEL0_ACCESS "RW" +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +// Register : BUSCTRL_PERFCTR1 +// Description : Bus fabric performance counter 1 +// Busfabric saturating performance counter 1 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL1 +#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000014) +#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR1_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR1_MSB _u(23) +#define BUSCTRL_PERFCTR1_LSB _u(0) +#define BUSCTRL_PERFCTR1_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL1 +// Description : Bus fabric performance event select for PERFCTR1 +// Select an event for PERFCTR1. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000018) +#define BUSCTRL_PERFSEL1_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL1_MSB _u(6) +#define BUSCTRL_PERFSEL1_LSB _u(0) +#define BUSCTRL_PERFSEL1_ACCESS "RW" +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +// Register : BUSCTRL_PERFCTR2 +// Description : Bus fabric performance counter 2 +// Busfabric saturating performance counter 2 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL2 +#define BUSCTRL_PERFCTR2_OFFSET _u(0x0000001c) +#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR2_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR2_MSB _u(23) +#define BUSCTRL_PERFCTR2_LSB _u(0) +#define BUSCTRL_PERFCTR2_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL2 +// Description : Bus fabric performance event select for PERFCTR2 +// Select an event for PERFCTR2. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL2_OFFSET _u(0x00000020) +#define BUSCTRL_PERFSEL2_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL2_MSB _u(6) +#define BUSCTRL_PERFSEL2_LSB _u(0) +#define BUSCTRL_PERFSEL2_ACCESS "RW" +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +// Register : BUSCTRL_PERFCTR3 +// Description : Bus fabric performance counter 3 +// Busfabric saturating performance counter 3 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL3 +#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000024) +#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR3_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR3_MSB _u(23) +#define BUSCTRL_PERFCTR3_LSB _u(0) +#define BUSCTRL_PERFCTR3_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL3 +// Description : Bus fabric performance event select for PERFCTR3 +// Select an event for PERFCTR3. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000028) +#define BUSCTRL_PERFSEL3_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL3_MSB _u(6) +#define BUSCTRL_PERFSEL3_LSB _u(0) +#define BUSCTRL_PERFSEL3_ACCESS "RW" +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +#endif // _HARDWARE_REGS_BUSCTRL_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/clocks.h b/src/rp2350/hardware_regs/include/hardware/regs/clocks.h new file mode 100644 index 000000000..fd560c910 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/clocks.h @@ -0,0 +1,2764 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : CLOCKS +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_CLOCKS_H +#define _HARDWARE_REGS_CLOCKS_H +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000) +#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_DIV +#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004) +#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008) +#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c) +#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_DIV +#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010) +#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014) +#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018) +#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc_ph +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_DIV +#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c) +#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020) +#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024) +#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc_ph +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_DIV +#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028) +#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c) +#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_REF_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030) +#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063) +#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb_primary_ref_opcg +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x3) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly +// 0x0 -> rosc_clksrc_ph +// 0x1 -> clksrc_clk_ref_aux +// 0x2 -> xosc_clksrc +// 0x3 -> lposc_clksrc +#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" +#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) +#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_LPOSC_CLKSRC _u(0x3) +// ============================================================================= +// Register : CLOCKS_CLK_REF_DIV +#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034) +#define CLOCKS_CLK_REF_DIV_BITS _u(0x00ff0000) +#define CLOCKS_CLK_REF_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x01) +#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00ff0000) +#define CLOCKS_CLK_REF_DIV_INT_MSB _u(23) +#define CLOCKS_CLK_REF_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_REF_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038) +#define CLOCKS_CLK_REF_SELECTED_BITS _u(0x0000000f) +#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_REF_SELECTED_MSB _u(3) +#define CLOCKS_CLK_REF_SELECTED_LSB _u(0) +#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c) +#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1) +#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_pll_usb +// 0x2 -> rosc_clksrc +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly +// 0x0 -> clk_ref +// 0x1 -> clksrc_clk_sys_aux +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) +// ============================================================================= +// Register : CLOCKS_CLK_SYS_DIV +#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040) +#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044) +#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0x00000003) +#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_SYS_SELECTED_MSB _u(1) +#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0) +#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_PERI_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048) +#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x10000ce0) +#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_PERI_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clk_sys +// 0x1 -> clksrc_pll_sys +// 0x2 -> clksrc_pll_usb +// 0x3 -> rosc_clksrc_ph +// 0x4 -> xosc_clksrc +// 0x5 -> clksrc_gpin0 +// 0x6 -> clksrc_gpin1 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) +// ============================================================================= +// Register : CLOCKS_CLK_PERI_DIV +#define CLOCKS_CLK_PERI_DIV_OFFSET _u(0x0000004c) +#define CLOCKS_CLK_PERI_DIV_BITS _u(0x00030000) +#define CLOCKS_CLK_PERI_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_PERI_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_PERI_DIV_INT_BITS _u(0x00030000) +#define CLOCKS_CLK_PERI_DIV_INT_MSB _u(17) +#define CLOCKS_CLK_PERI_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_PERI_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_PERI_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050) +#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_PERI_SELECTED_MSB _u(0) +#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0) +#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_HSTX_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_HSTX_CTRL_OFFSET _u(0x00000054) +#define CLOCKS_CLK_HSTX_CTRL_BITS _u(0x10130ce0) +#define CLOCKS_CLK_HSTX_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_HSTX_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_HSTX_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_HSTX_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_HSTX_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_HSTX_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clk_sys +// 0x1 -> clksrc_pll_sys +// 0x2 -> clksrc_pll_usb +// 0x3 -> clksrc_gpin0 +// 0x4 -> clksrc_gpin1 +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x3) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x4) +// ============================================================================= +// Register : CLOCKS_CLK_HSTX_DIV +#define CLOCKS_CLK_HSTX_DIV_OFFSET _u(0x00000058) +#define CLOCKS_CLK_HSTX_DIV_BITS _u(0x00030000) +#define CLOCKS_CLK_HSTX_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_HSTX_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_HSTX_DIV_INT_BITS _u(0x00030000) +#define CLOCKS_CLK_HSTX_DIV_INT_MSB _u(17) +#define CLOCKS_CLK_HSTX_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_HSTX_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_HSTX_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_HSTX_SELECTED_OFFSET _u(0x0000005c) +#define CLOCKS_CLK_HSTX_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_HSTX_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_HSTX_SELECTED_MSB _u(0) +#define CLOCKS_CLK_HSTX_SELECTED_LSB _u(0) +#define CLOCKS_CLK_HSTX_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_USB_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000060) +#define CLOCKS_CLK_USB_CTRL_BITS _u(0x10130ce0) +#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_USB_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_USB_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_USB_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_USB_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +// ============================================================================= +// Register : CLOCKS_CLK_USB_DIV +#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000064) +#define CLOCKS_CLK_USB_DIV_BITS _u(0x000f0000) +#define CLOCKS_CLK_USB_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x000f0000) +#define CLOCKS_CLK_USB_DIV_INT_MSB _u(19) +#define CLOCKS_CLK_USB_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_USB_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x00000068) +#define CLOCKS_CLK_USB_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_USB_SELECTED_MSB _u(0) +#define CLOCKS_CLK_USB_SELECTED_LSB _u(0) +#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x0000006c) +#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x10130ce0) +#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_ADC_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +// ============================================================================= +// Register : CLOCKS_CLK_ADC_DIV +#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000070) +#define CLOCKS_CLK_ADC_DIV_BITS _u(0x000f0000) +#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x000f0000) +#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(19) +#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000074) +#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_ADC_SELECTED_MSB _u(0) +#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0) +#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_DFTCLK_XOSC_CTRL +#define CLOCKS_DFTCLK_XOSC_CTRL_OFFSET _u(0x00000078) +#define CLOCKS_DFTCLK_XOSC_CTRL_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_XOSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_DFTCLK_XOSC_CTRL_SRC +// 0x0 -> NULL +// 0x1 -> clksrc_pll_usb_primary +// 0x2 -> clksrc_gpin0 +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_MSB _u(1) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_LSB _u(0) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_ACCESS "RW" +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_NULL _u(0x0) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_CLKSRC_PLL_USB_PRIMARY _u(0x1) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_CLKSRC_GPIN0 _u(0x2) +// ============================================================================= +// Register : CLOCKS_DFTCLK_ROSC_CTRL +#define CLOCKS_DFTCLK_ROSC_CTRL_OFFSET _u(0x0000007c) +#define CLOCKS_DFTCLK_ROSC_CTRL_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_ROSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_DFTCLK_ROSC_CTRL_SRC +// 0x0 -> NULL +// 0x1 -> clksrc_pll_sys_primary_rosc +// 0x2 -> clksrc_gpin1 +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_MSB _u(1) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_LSB _u(0) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_ACCESS "RW" +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_NULL _u(0x0) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_CLKSRC_PLL_SYS_PRIMARY_ROSC _u(0x1) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_CLKSRC_GPIN1 _u(0x2) +// ============================================================================= +// Register : CLOCKS_DFTCLK_LPOSC_CTRL +#define CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET _u(0x00000080) +#define CLOCKS_DFTCLK_LPOSC_CTRL_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_LPOSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_DFTCLK_LPOSC_CTRL_SRC +// 0x0 -> NULL +// 0x1 -> clksrc_pll_usb_primary_lposc +// 0x2 -> clksrc_gpin1 +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_MSB _u(1) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_LSB _u(0) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_ACCESS "RW" +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_NULL _u(0x0) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_CLKSRC_PLL_USB_PRIMARY_LPOSC _u(0x1) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_CLKSRC_GPIN1 _u(0x2) +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_CTRL +#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000084) +#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR +// Description : For clearing the resus after the fault that triggered it has +// been corrected +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE +// Description : Force a resus, for test purposes only +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE +// Description : Enable resus +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT +// Description : This is expressed as a number of clk_ref cycles +// and must be >= 2x clk_ref_freq/min_clk_tst_freq +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_STATUS +#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x00000088) +#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED +// Description : Clock has been resuscitated, correct the error then send +// ctrl_clear=1 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_REF_KHZ +// Description : Reference clock frequency in kHz +#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x0000008c) +#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff) +#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_REF_KHZ_MSB _u(19) +#define CLOCKS_FC0_REF_KHZ_LSB _u(0) +#define CLOCKS_FC0_REF_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MIN_KHZ +// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if +// you are not using the pass/fail flags +#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000090) +#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_MIN_KHZ_MSB _u(24) +#define CLOCKS_FC0_MIN_KHZ_LSB _u(0) +#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MAX_KHZ +// Description : Maximum pass frequency in kHz. This is optional. Set to +// 0x1ffffff if you are not using the pass/fail flags +#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000094) +#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_MSB _u(24) +#define CLOCKS_FC0_MAX_KHZ_LSB _u(0) +#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_DELAY +// Description : Delays the start of frequency counting to allow the mux to +// settle +// Delay is measured in multiples of the reference clock period +#define CLOCKS_FC0_DELAY_OFFSET _u(0x00000098) +#define CLOCKS_FC0_DELAY_BITS _u(0x00000007) +#define CLOCKS_FC0_DELAY_RESET _u(0x00000001) +#define CLOCKS_FC0_DELAY_MSB _u(2) +#define CLOCKS_FC0_DELAY_LSB _u(0) +#define CLOCKS_FC0_DELAY_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_INTERVAL +// Description : The test interval is 0.98us * 2**interval, but let's call it +// 1us * 2**interval +// The default gives a test interval of 250us +#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x0000009c) +#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f) +#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008) +#define CLOCKS_FC0_INTERVAL_MSB _u(3) +#define CLOCKS_FC0_INTERVAL_LSB _u(0) +#define CLOCKS_FC0_INTERVAL_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_SRC +// Description : Clock sent to frequency counter, set to 0 when not required +// Writing to this register initiates the frequency count +// 0x00 -> NULL +// 0x01 -> pll_sys_clksrc_primary +// 0x02 -> pll_usb_clksrc_primary +// 0x03 -> rosc_clksrc +// 0x04 -> rosc_clksrc_ph +// 0x05 -> xosc_clksrc +// 0x06 -> clksrc_gpin0 +// 0x07 -> clksrc_gpin1 +// 0x08 -> clk_ref +// 0x09 -> clk_sys +// 0x0a -> clk_peri +// 0x0b -> clk_usb +// 0x0c -> clk_adc +// 0x0d -> clk_hstx +// 0x0e -> lposc_clksrc +// 0x0f -> otp_clk2fc +// 0x10 -> pll_usb_clksrc_primary_dft +#define CLOCKS_FC0_SRC_OFFSET _u(0x000000a0) +#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) +#define CLOCKS_FC0_SRC_RESET _u(0x00000000) +#define CLOCKS_FC0_SRC_MSB _u(7) +#define CLOCKS_FC0_SRC_LSB _u(0) +#define CLOCKS_FC0_SRC_ACCESS "RW" +#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) +#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) +#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) +#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) +#define CLOCKS_FC0_SRC_VALUE_CLK_HSTX _u(0x0d) +#define CLOCKS_FC0_SRC_VALUE_LPOSC_CLKSRC _u(0x0e) +#define CLOCKS_FC0_SRC_VALUE_OTP_CLK2FC _u(0x0f) +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY_DFT _u(0x10) +// ============================================================================= +// Register : CLOCKS_FC0_STATUS +// Description : Frequency counter status +#define CLOCKS_FC0_STATUS_OFFSET _u(0x000000a4) +#define CLOCKS_FC0_STATUS_BITS _u(0x11111111) +#define CLOCKS_FC0_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DIED +// Description : Test clock stopped during test +#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000) +#define CLOCKS_FC0_STATUS_DIED_MSB _u(28) +#define CLOCKS_FC0_STATUS_DIED_LSB _u(28) +#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAST +// Description : Test clock faster than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000) +#define CLOCKS_FC0_STATUS_FAST_MSB _u(24) +#define CLOCKS_FC0_STATUS_FAST_LSB _u(24) +#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_SLOW +// Description : Test clock slower than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000) +#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20) +#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20) +#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAIL +// Description : Test failed +#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000) +#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16) +#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16) +#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_WAITING +// Description : Waiting for test clock to start +#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000) +#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12) +#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12) +#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_RUNNING +// Description : Test running +#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100) +#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8) +#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8) +#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DONE +// Description : Test complete +#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010) +#define CLOCKS_FC0_STATUS_DONE_MSB _u(4) +#define CLOCKS_FC0_STATUS_DONE_LSB _u(4) +#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_PASS +// Description : Test passed +#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001) +#define CLOCKS_FC0_STATUS_PASS_MSB _u(0) +#define CLOCKS_FC0_STATUS_PASS_LSB _u(0) +#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_RESULT +// Description : Result of frequency measurement, only valid when status_done=1 +#define CLOCKS_FC0_RESULT_OFFSET _u(0x000000a8) +#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff) +#define CLOCKS_FC0_RESULT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_KHZ +#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) +#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) +#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) +#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5) +#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_FRAC +#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) +#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) +#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) +#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0) +#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_WAKE_EN0 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000ac) +#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff) +#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x80000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(31) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(31) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SHA256 +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_BITS _u(0x40000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_MSB _u(30) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_LSB _u(30) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x20000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(29) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(29) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x10000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(28) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(28) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x08000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(27) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(27) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x04000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(26) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(26) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x02000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(25) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(25) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_POWMAN +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_BITS _u(0x01000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_MSB _u(24) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_LSB _u(24) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_REF_POWMAN +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_BITS _u(0x00800000) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_MSB _u(23) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_LSB _u(23) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00400000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(22) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(22) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(21) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(21) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO2 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_BITS _u(0x00100000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_MSB _u(20) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_LSB _u(20) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00080000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(19) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(19) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00040000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(18) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(18) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00020000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(17) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(17) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_OTP +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_BITS _u(0x00010000) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_MSB _u(16) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_LSB _u(16) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_REF_OTP +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_BITS _u(0x00008000) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_MSB _u(15) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_LSB _u(15) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(14) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(14) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(13) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(13) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(12) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(12) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(11) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(11) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_HSTX +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_MSB _u(10) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_LSB _u(10) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_HSTX +#define CLOCKS_WAKE_EN0_CLK_HSTX_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_HSTX_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN0_CLK_HSTX_MSB _u(9) +#define CLOCKS_WAKE_EN0_CLK_HSTX_LSB _u(9) +#define CLOCKS_WAKE_EN0_CLK_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(7) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(7) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(6) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(6) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(5) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(5) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_MSB _u(4) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_LSB _u(4) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(3) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(3) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_ADC +#define CLOCKS_WAKE_EN0_CLK_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_ADC_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN0_CLK_ADC_MSB _u(2) +#define CLOCKS_WAKE_EN0_CLK_ADC_LSB _u(2) +#define CLOCKS_WAKE_EN0_CLK_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_MSB _u(1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_LSB _u(1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_WAKE_EN1 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000b0) +#define CLOCKS_WAKE_EN1_BITS _u(0x7fffffff) +#define CLOCKS_WAKE_EN1_RESET _u(0x7fffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x40000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(30) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(30) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x20000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(29) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(29) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(28) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(28) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_USB +#define CLOCKS_WAKE_EN1_CLK_USB_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_USB_BITS _u(0x08000000) +#define CLOCKS_WAKE_EN1_CLK_USB_MSB _u(27) +#define CLOCKS_WAKE_EN1_CLK_USB_LSB _u(27) +#define CLOCKS_WAKE_EN1_CLK_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x04000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(26) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(26) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x02000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(25) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(25) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x01000000) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(24) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(24) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00800000) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(23) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(23) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00400000) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(22) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(22) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TRNG +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_BITS _u(0x00200000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_MSB _u(21) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_LSB _u(21) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER1 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_BITS _u(0x00100000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_MSB _u(20) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_LSB _u(20) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER0 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_BITS _u(0x00080000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_MSB _u(19) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_LSB _u(19) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TICKS +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_BITS _u(0x00040000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_MSB _u(18) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_LSB _u(18) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_REF_TICKS +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_BITS _u(0x00020000) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_MSB _u(17) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_LSB _u(17) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00010000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(16) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(16) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00008000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(15) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(15) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(14) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(14) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM9 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_MSB _u(13) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_LSB _u(13) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM8 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_MSB _u(12) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_LSB _u(12) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM7 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_MSB _u(11) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_LSB _u(11) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM6 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_MSB _u(10) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_LSB _u(10) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(9) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(9) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(8) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(8) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_MSB _u(7) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_LSB _u(7) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_MSB _u(6) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_LSB _u(6) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_MSB _u(5) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_LSB _u(5) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_MSB _u(4) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_LSB _u(4) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SPI1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_MSB _u(3) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_LSB _u(3) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_SPI1 +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_MSB _u(2) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_LSB _u(2) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SPI0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_MSB _u(1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_LSB _u(1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_SPI0 +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_MSB _u(0) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_LSB _u(0) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN0 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000b4) +#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff) +#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x80000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(31) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(31) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SHA256 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_BITS _u(0x40000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_MSB _u(30) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_LSB _u(30) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x20000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(29) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(29) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x10000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(28) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(28) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x08000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(27) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(27) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x04000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(26) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(26) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x02000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(25) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(25) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_BITS _u(0x01000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_MSB _u(24) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_LSB _u(24) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_REF_POWMAN +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_BITS _u(0x00800000) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_MSB _u(23) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_LSB _u(23) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00400000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(22) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(22) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(21) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(21) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_BITS _u(0x00100000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_MSB _u(20) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_LSB _u(20) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00080000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(19) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(19) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00040000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(18) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(18) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00020000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(17) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(17) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_OTP +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_BITS _u(0x00010000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_MSB _u(16) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_LSB _u(16) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_REF_OTP +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_BITS _u(0x00008000) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_MSB _u(15) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_LSB _u(15) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(14) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(14) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(13) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(13) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(12) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(12) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(11) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(11) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_HSTX +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_MSB _u(10) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_LSB _u(10) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_HSTX +#define CLOCKS_SLEEP_EN0_CLK_HSTX_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_MSB _u(9) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_LSB _u(9) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(7) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(7) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(6) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(6) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(5) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(5) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_MSB _u(4) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_LSB _u(4) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(3) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(3) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_ADC +#define CLOCKS_SLEEP_EN0_CLK_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_ADC_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN0_CLK_ADC_MSB _u(2) +#define CLOCKS_SLEEP_EN0_CLK_ADC_LSB _u(2) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_MSB _u(1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_LSB _u(1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN1 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000b8) +#define CLOCKS_SLEEP_EN1_BITS _u(0x7fffffff) +#define CLOCKS_SLEEP_EN1_RESET _u(0x7fffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x40000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(30) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(30) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x20000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(29) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(29) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(28) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(28) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_USB +#define CLOCKS_SLEEP_EN1_CLK_USB_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_USB_BITS _u(0x08000000) +#define CLOCKS_SLEEP_EN1_CLK_USB_MSB _u(27) +#define CLOCKS_SLEEP_EN1_CLK_USB_LSB _u(27) +#define CLOCKS_SLEEP_EN1_CLK_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x04000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(26) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(26) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x02000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(25) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(25) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x01000000) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(24) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(24) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00800000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(23) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(23) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00400000) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(22) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(22) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TRNG +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_BITS _u(0x00200000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_MSB _u(21) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_LSB _u(21) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_BITS _u(0x00100000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_MSB _u(20) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_LSB _u(20) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_BITS _u(0x00080000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_MSB _u(19) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_LSB _u(19) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TICKS +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_BITS _u(0x00040000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_MSB _u(18) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_LSB _u(18) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_REF_TICKS +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_BITS _u(0x00020000) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_MSB _u(17) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_LSB _u(17) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00010000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(16) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(16) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00008000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(15) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(15) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(14) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(14) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_MSB _u(13) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_LSB _u(13) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_MSB _u(12) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_LSB _u(12) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_MSB _u(11) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_LSB _u(11) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_MSB _u(10) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_LSB _u(10) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(9) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(9) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(8) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(8) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_MSB _u(7) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_LSB _u(7) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_MSB _u(6) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_LSB _u(6) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_MSB _u(5) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_LSB _u(5) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_MSB _u(4) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_LSB _u(4) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SPI1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_MSB _u(3) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_LSB _u(3) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_SPI1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_MSB _u(2) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_LSB _u(2) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SPI0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_MSB _u(1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_LSB _u(1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_SPI0 +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_MSB _u(0) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_LSB _u(0) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_ENABLED0 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED0_OFFSET _u(0x000000bc) +#define CLOCKS_ENABLED0_BITS _u(0xffffffff) +#define CLOCKS_ENABLED0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SIO +#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x80000000) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(31) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(31) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SHA256 +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_BITS _u(0x40000000) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_MSB _u(30) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_LSB _u(30) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PSM +#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x20000000) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(29) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(29) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x10000000) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(28) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(28) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROM +#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x08000000) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(27) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(27) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x04000000) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(26) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(26) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PWM +#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x02000000) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(25) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(25) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_POWMAN +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_BITS _u(0x01000000) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_MSB _u(24) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_LSB _u(24) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_REF_POWMAN +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_BITS _u(0x00800000) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_MSB _u(23) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_LSB _u(23) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00400000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(22) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(22) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(21) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(21) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO2 +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_BITS _u(0x00100000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_MSB _u(20) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_LSB _u(20) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00080000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(19) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(19) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00040000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(18) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(18) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PADS +#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00020000) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(17) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(17) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_OTP +#define CLOCKS_ENABLED0_CLK_SYS_OTP_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_BITS _u(0x00010000) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_MSB _u(16) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_LSB _u(16) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_REF_OTP +#define CLOCKS_ENABLED0_CLK_REF_OTP_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_REF_OTP_BITS _u(0x00008000) +#define CLOCKS_ENABLED0_CLK_REF_OTP_MSB _u(15) +#define CLOCKS_ENABLED0_CLK_REF_OTP_LSB _u(15) +#define CLOCKS_ENABLED0_CLK_REF_OTP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00004000) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(14) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(14) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_IO +#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00002000) +#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(13) +#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(13) +#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00001000) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(12) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(12) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000800) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(11) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(11) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_HSTX +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_BITS _u(0x00000400) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_MSB _u(10) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_LSB _u(10) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_HSTX +#define CLOCKS_ENABLED0_CLK_HSTX_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_HSTX_BITS _u(0x00000200) +#define CLOCKS_ENABLED0_CLK_HSTX_MSB _u(9) +#define CLOCKS_ENABLED0_CLK_HSTX_LSB _u(9) +#define CLOCKS_ENABLED0_CLK_HSTX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_DMA +#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000080) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(7) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(7) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(6) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(6) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(5) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(5) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BOOTRAM +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_MSB _u(4) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_LSB _u(4) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ADC +#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000008) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(3) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(3) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_ADC +#define CLOCKS_ENABLED0_CLK_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_ADC_BITS _u(0x00000004) +#define CLOCKS_ENABLED0_CLK_ADC_MSB _u(2) +#define CLOCKS_ENABLED0_CLK_ADC_LSB _u(2) +#define CLOCKS_ENABLED0_CLK_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_MSB _u(1) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_LSB _u(1) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_ENABLED1 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED1_OFFSET _u(0x000000c0) +#define CLOCKS_ENABLED1_BITS _u(0x7fffffff) +#define CLOCKS_ENABLED1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x40000000) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(30) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(30) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XIP +#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x20000000) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(29) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(29) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(28) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(28) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_USB +#define CLOCKS_ENABLED1_CLK_USB_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_USB_BITS _u(0x08000000) +#define CLOCKS_ENABLED1_CLK_USB_MSB _u(27) +#define CLOCKS_ENABLED1_CLK_USB_LSB _u(27) +#define CLOCKS_ENABLED1_CLK_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x04000000) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(26) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(26) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART1 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x02000000) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(25) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(25) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART1 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x01000000) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(24) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(24) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART0 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00800000) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(23) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(23) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART0 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00400000) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(22) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(22) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TRNG +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_BITS _u(0x00200000) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_MSB _u(21) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_LSB _u(21) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER1 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_BITS _u(0x00100000) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_MSB _u(20) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_LSB _u(20) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER0 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_BITS _u(0x00080000) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_MSB _u(19) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_LSB _u(19) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TICKS +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_BITS _u(0x00040000) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_MSB _u(18) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_LSB _u(18) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_REF_TICKS +#define CLOCKS_ENABLED1_CLK_REF_TICKS_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_BITS _u(0x00020000) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_MSB _u(17) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_LSB _u(17) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00010000) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(16) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(16) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00008000) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(15) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(15) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00004000) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(14) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(14) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM9 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_BITS _u(0x00002000) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_MSB _u(13) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_LSB _u(13) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM8 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_BITS _u(0x00001000) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_MSB _u(12) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_LSB _u(12) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM7 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_BITS _u(0x00000800) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_MSB _u(11) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_LSB _u(11) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM6 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_BITS _u(0x00000400) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_MSB _u(10) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_LSB _u(10) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000200) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(9) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(9) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000100) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(8) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(8) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM3 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_BITS _u(0x00000080) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_MSB _u(7) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_LSB _u(7) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM2 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_BITS _u(0x00000040) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_MSB _u(6) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_LSB _u(6) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_BITS _u(0x00000020) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_MSB _u(5) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_LSB _u(5) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_BITS _u(0x00000010) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_MSB _u(4) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_LSB _u(4) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SPI1 +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_BITS _u(0x00000008) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_MSB _u(3) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_LSB _u(3) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_SPI1 +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_BITS _u(0x00000004) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_MSB _u(2) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_LSB _u(2) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SPI0 +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_BITS _u(0x00000002) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_MSB _u(1) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_LSB _u(1) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_SPI0 +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_BITS _u(0x00000001) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_MSB _u(0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_LSB _u(0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTR +// Description : Raw Interrupts +#define CLOCKS_INTR_OFFSET _u(0x000000c4) +#define CLOCKS_INTR_BITS _u(0x00000001) +#define CLOCKS_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTR_CLK_SYS_RESUS +#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTE +// Description : Interrupt Enable +#define CLOCKS_INTE_OFFSET _u(0x000000c8) +#define CLOCKS_INTE_BITS _u(0x00000001) +#define CLOCKS_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTE_CLK_SYS_RESUS +#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTF +// Description : Interrupt Force +#define CLOCKS_INTF_OFFSET _u(0x000000cc) +#define CLOCKS_INTF_BITS _u(0x00000001) +#define CLOCKS_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTF_CLK_SYS_RESUS +#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTS +// Description : Interrupt status after masking & forcing +#define CLOCKS_INTS_OFFSET _u(0x000000d0) +#define CLOCKS_INTS_BITS _u(0x00000001) +#define CLOCKS_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTS_CLK_SYS_RESUS +#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_CLOCKS_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/coresight_trace.h b/src/rp2350/hardware_regs/include/hardware/regs/coresight_trace.h new file mode 100644 index 000000000..cb4f990d7 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/coresight_trace.h @@ -0,0 +1,85 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : CORESIGHT_TRACE +// Version : 1 +// Bus type : ahbl +// Description : Coresight block - RP specific registers +// ============================================================================= +#ifndef _HARDWARE_REGS_CORESIGHT_TRACE_H +#define _HARDWARE_REGS_CORESIGHT_TRACE_H +// ============================================================================= +// Register : CORESIGHT_TRACE_CTRL_STATUS +// Description : Control and status register +#define CORESIGHT_TRACE_CTRL_STATUS_OFFSET _u(0x00000000) +#define CORESIGHT_TRACE_CTRL_STATUS_BITS _u(0x00000003) +#define CORESIGHT_TRACE_CTRL_STATUS_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW +// Description : This status flag is set high when trace data has been dropped +// due to the FIFO being full at the point trace data was sampled. +// Write 1 to acknowledge and clear the bit. +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_RESET _u(0x0) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_BITS _u(0x00000002) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_MSB _u(1) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_LSB _u(1) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH +// Description : Set to 1 to continuously hold the trace FIFO in a flushed state +// and prevent overflow. +// +// Before clearing this flag, configure and start a DMA channel +// with the correct DREQ for the TRACE_CAPTURE_FIFO register. +// +// Clear this flag to begin sampling trace data, and set once +// again once the trace capture buffer is full. You must configure +// the TPIU in order to generate trace packets to be captured, as +// well as components like the ETM further upstream to generate +// the event stream propagated to the TPIU. +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_RESET _u(0x1) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_BITS _u(0x00000001) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_MSB _u(0) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_LSB _u(0) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_ACCESS "RW" +// ============================================================================= +// Register : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO +// Description : FIFO for trace data captured from the TPIU +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET _u(0x00000004) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_BITS _u(0xffffffff) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA +// Description : Read from an 8 x 32-bit FIFO containing trace data captured +// from the TPIU. +// +// Hardware pushes to the FIFO on rising edges of clk_sys, when +// either of the following is true: +// +// * TPIU TRACECTL output is low (normal trace data) +// +// * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and +// TRACEDATA1 are both low (trigger packet) +// +// These conditions are in accordance with Arm Coresight +// Architecture Spec v3.0 section D3.3.3: Decoding requirements +// for Trace Capture Devices +// +// The data captured into the FIFO is the full 32-bit TRACEDATA +// bus output by the TPIU. Note that the TPIU is a DDR output at +// half of clk_sys, therefore this interface can capture the full +// 32-bit TPIU DDR output bandwidth as it samples once per active +// edge of the TPIU output clock. +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_RESET _u(0x00000000) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_BITS _u(0xffffffff) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MSB _u(31) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_LSB _u(0) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_CORESIGHT_TRACE_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/dma.h b/src/rp2350/hardware_regs/include/hardware/regs/dma.h new file mode 100644 index 000000000..00ecde186 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/dma.h @@ -0,0 +1,9914 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : DMA +// Version : 1 +// Bus type : apb +// Description : DMA with separate read and write masters +// ============================================================================= +#ifndef _HARDWARE_REGS_DMA_H +#define _HARDWARE_REGS_DMA_H +// ============================================================================= +// Register : DMA_CH0_READ_ADDR +// Description : DMA Channel 0 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000) +#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH0_READ_ADDR_MSB _u(31) +#define DMA_CH0_READ_ADDR_LSB _u(0) +#define DMA_CH0_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_WRITE_ADDR +// Description : DMA Channel 0 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004) +#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH0_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_TRANS_COUNT +// Description : DMA Channel 0 Transfer Count +#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008) +#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH0_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH0_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH0_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH0_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH0_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH0_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH0_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH0_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH0_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH0_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH0_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_CTRL_TRIG +// Description : DMA Channel 0 Control and Status +#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010) +#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH0_AL1_CTRL_RESET "-" +#define DMA_CH0_AL1_CTRL_MSB _u(31) +#define DMA_CH0_AL1_CTRL_LSB _u(0) +#define DMA_CH0_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014) +#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL1_READ_ADDR_RESET "-" +#define DMA_CH0_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018) +#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 0 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020) +#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH0_AL2_CTRL_RESET "-" +#define DMA_CH0_AL2_CTRL_MSB _u(31) +#define DMA_CH0_AL2_CTRL_LSB _u(0) +#define DMA_CH0_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024) +#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028) +#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL2_READ_ADDR_RESET "-" +#define DMA_CH0_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 0 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030) +#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH0_AL3_CTRL_RESET "-" +#define DMA_CH0_AL3_CTRL_MSB _u(31) +#define DMA_CH0_AL3_CTRL_LSB _u(0) +#define DMA_CH0_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034) +#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038) +#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_READ_ADDR_TRIG +// Description : Alias for channel 0 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c) +#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_READ_ADDR +// Description : DMA Channel 1 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040) +#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH1_READ_ADDR_MSB _u(31) +#define DMA_CH1_READ_ADDR_LSB _u(0) +#define DMA_CH1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_WRITE_ADDR +// Description : DMA Channel 1 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044) +#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_TRANS_COUNT +// Description : DMA Channel 1 Transfer Count +#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048) +#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH1_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH1_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH1_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH1_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH1_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH1_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH1_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH1_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH1_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH1_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH1_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH1_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH1_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_CTRL_TRIG +// Description : DMA Channel 1 Control and Status +#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) +#define DMA_CH1_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050) +#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH1_AL1_CTRL_RESET "-" +#define DMA_CH1_AL1_CTRL_MSB _u(31) +#define DMA_CH1_AL1_CTRL_LSB _u(0) +#define DMA_CH1_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054) +#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL1_READ_ADDR_RESET "-" +#define DMA_CH1_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058) +#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 1 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060) +#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH1_AL2_CTRL_RESET "-" +#define DMA_CH1_AL2_CTRL_MSB _u(31) +#define DMA_CH1_AL2_CTRL_LSB _u(0) +#define DMA_CH1_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064) +#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068) +#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL2_READ_ADDR_RESET "-" +#define DMA_CH1_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 1 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070) +#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH1_AL3_CTRL_RESET "-" +#define DMA_CH1_AL3_CTRL_MSB _u(31) +#define DMA_CH1_AL3_CTRL_LSB _u(0) +#define DMA_CH1_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074) +#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078) +#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_READ_ADDR_TRIG +// Description : Alias for channel 1 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c) +#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_READ_ADDR +// Description : DMA Channel 2 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080) +#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH2_READ_ADDR_MSB _u(31) +#define DMA_CH2_READ_ADDR_LSB _u(0) +#define DMA_CH2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_WRITE_ADDR +// Description : DMA Channel 2 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084) +#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH2_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_TRANS_COUNT +// Description : DMA Channel 2 Transfer Count +#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088) +#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH2_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH2_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH2_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH2_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH2_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH2_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH2_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH2_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH2_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH2_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH2_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH2_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH2_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_CTRL_TRIG +// Description : DMA Channel 2 Control and Status +#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) +#define DMA_CH2_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090) +#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH2_AL1_CTRL_RESET "-" +#define DMA_CH2_AL1_CTRL_MSB _u(31) +#define DMA_CH2_AL1_CTRL_LSB _u(0) +#define DMA_CH2_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094) +#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL1_READ_ADDR_RESET "-" +#define DMA_CH2_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098) +#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 2 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0) +#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH2_AL2_CTRL_RESET "-" +#define DMA_CH2_AL2_CTRL_MSB _u(31) +#define DMA_CH2_AL2_CTRL_LSB _u(0) +#define DMA_CH2_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4) +#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8) +#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL2_READ_ADDR_RESET "-" +#define DMA_CH2_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 2 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0) +#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH2_AL3_CTRL_RESET "-" +#define DMA_CH2_AL3_CTRL_MSB _u(31) +#define DMA_CH2_AL3_CTRL_LSB _u(0) +#define DMA_CH2_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4) +#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8) +#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_READ_ADDR_TRIG +// Description : Alias for channel 2 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc) +#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_READ_ADDR +// Description : DMA Channel 3 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0) +#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH3_READ_ADDR_MSB _u(31) +#define DMA_CH3_READ_ADDR_LSB _u(0) +#define DMA_CH3_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_WRITE_ADDR +// Description : DMA Channel 3 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4) +#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_TRANS_COUNT +// Description : DMA Channel 3 Transfer Count +#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8) +#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH3_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH3_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH3_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH3_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH3_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH3_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH3_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH3_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH3_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH3_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH3_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH3_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH3_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_CTRL_TRIG +// Description : DMA Channel 3 Control and Status +#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) +#define DMA_CH3_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0) +#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH3_AL1_CTRL_RESET "-" +#define DMA_CH3_AL1_CTRL_MSB _u(31) +#define DMA_CH3_AL1_CTRL_LSB _u(0) +#define DMA_CH3_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4) +#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL1_READ_ADDR_RESET "-" +#define DMA_CH3_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8) +#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 3 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0) +#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH3_AL2_CTRL_RESET "-" +#define DMA_CH3_AL2_CTRL_MSB _u(31) +#define DMA_CH3_AL2_CTRL_LSB _u(0) +#define DMA_CH3_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4) +#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8) +#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL2_READ_ADDR_RESET "-" +#define DMA_CH3_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 3 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0) +#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH3_AL3_CTRL_RESET "-" +#define DMA_CH3_AL3_CTRL_MSB _u(31) +#define DMA_CH3_AL3_CTRL_LSB _u(0) +#define DMA_CH3_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4) +#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8) +#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_READ_ADDR_TRIG +// Description : Alias for channel 3 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc) +#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_READ_ADDR +// Description : DMA Channel 4 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100) +#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH4_READ_ADDR_MSB _u(31) +#define DMA_CH4_READ_ADDR_LSB _u(0) +#define DMA_CH4_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_WRITE_ADDR +// Description : DMA Channel 4 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104) +#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH4_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_TRANS_COUNT +// Description : DMA Channel 4 Transfer Count +#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108) +#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH4_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH4_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH4_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH4_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH4_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH4_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH4_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH4_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH4_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH4_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH4_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH4_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH4_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_CTRL_TRIG +// Description : DMA Channel 4 Control and Status +#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) +#define DMA_CH4_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110) +#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH4_AL1_CTRL_RESET "-" +#define DMA_CH4_AL1_CTRL_MSB _u(31) +#define DMA_CH4_AL1_CTRL_LSB _u(0) +#define DMA_CH4_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114) +#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL1_READ_ADDR_RESET "-" +#define DMA_CH4_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118) +#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 4 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120) +#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH4_AL2_CTRL_RESET "-" +#define DMA_CH4_AL2_CTRL_MSB _u(31) +#define DMA_CH4_AL2_CTRL_LSB _u(0) +#define DMA_CH4_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124) +#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128) +#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL2_READ_ADDR_RESET "-" +#define DMA_CH4_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 4 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130) +#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH4_AL3_CTRL_RESET "-" +#define DMA_CH4_AL3_CTRL_MSB _u(31) +#define DMA_CH4_AL3_CTRL_LSB _u(0) +#define DMA_CH4_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134) +#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138) +#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_READ_ADDR_TRIG +// Description : Alias for channel 4 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c) +#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_READ_ADDR +// Description : DMA Channel 5 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140) +#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH5_READ_ADDR_MSB _u(31) +#define DMA_CH5_READ_ADDR_LSB _u(0) +#define DMA_CH5_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_WRITE_ADDR +// Description : DMA Channel 5 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144) +#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH5_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_TRANS_COUNT +// Description : DMA Channel 5 Transfer Count +#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148) +#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH5_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH5_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH5_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH5_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH5_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH5_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH5_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH5_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH5_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH5_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH5_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH5_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH5_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_CTRL_TRIG +// Description : DMA Channel 5 Control and Status +#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) +#define DMA_CH5_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150) +#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH5_AL1_CTRL_RESET "-" +#define DMA_CH5_AL1_CTRL_MSB _u(31) +#define DMA_CH5_AL1_CTRL_LSB _u(0) +#define DMA_CH5_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154) +#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL1_READ_ADDR_RESET "-" +#define DMA_CH5_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158) +#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 5 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160) +#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH5_AL2_CTRL_RESET "-" +#define DMA_CH5_AL2_CTRL_MSB _u(31) +#define DMA_CH5_AL2_CTRL_LSB _u(0) +#define DMA_CH5_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164) +#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168) +#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL2_READ_ADDR_RESET "-" +#define DMA_CH5_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 5 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170) +#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH5_AL3_CTRL_RESET "-" +#define DMA_CH5_AL3_CTRL_MSB _u(31) +#define DMA_CH5_AL3_CTRL_LSB _u(0) +#define DMA_CH5_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174) +#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178) +#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_READ_ADDR_TRIG +// Description : Alias for channel 5 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c) +#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_READ_ADDR +// Description : DMA Channel 6 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180) +#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH6_READ_ADDR_MSB _u(31) +#define DMA_CH6_READ_ADDR_LSB _u(0) +#define DMA_CH6_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_WRITE_ADDR +// Description : DMA Channel 6 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184) +#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH6_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_TRANS_COUNT +// Description : DMA Channel 6 Transfer Count +#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188) +#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH6_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH6_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH6_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH6_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH6_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH6_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH6_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH6_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH6_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH6_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH6_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH6_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH6_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_CTRL_TRIG +// Description : DMA Channel 6 Control and Status +#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) +#define DMA_CH6_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190) +#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH6_AL1_CTRL_RESET "-" +#define DMA_CH6_AL1_CTRL_MSB _u(31) +#define DMA_CH6_AL1_CTRL_LSB _u(0) +#define DMA_CH6_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194) +#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL1_READ_ADDR_RESET "-" +#define DMA_CH6_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198) +#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 6 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0) +#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH6_AL2_CTRL_RESET "-" +#define DMA_CH6_AL2_CTRL_MSB _u(31) +#define DMA_CH6_AL2_CTRL_LSB _u(0) +#define DMA_CH6_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4) +#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8) +#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL2_READ_ADDR_RESET "-" +#define DMA_CH6_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 6 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0) +#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH6_AL3_CTRL_RESET "-" +#define DMA_CH6_AL3_CTRL_MSB _u(31) +#define DMA_CH6_AL3_CTRL_LSB _u(0) +#define DMA_CH6_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4) +#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8) +#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_READ_ADDR_TRIG +// Description : Alias for channel 6 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc) +#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_READ_ADDR +// Description : DMA Channel 7 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0) +#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH7_READ_ADDR_MSB _u(31) +#define DMA_CH7_READ_ADDR_LSB _u(0) +#define DMA_CH7_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_WRITE_ADDR +// Description : DMA Channel 7 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4) +#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH7_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_TRANS_COUNT +// Description : DMA Channel 7 Transfer Count +#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8) +#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH7_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH7_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH7_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH7_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH7_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH7_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH7_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH7_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH7_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH7_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH7_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH7_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH7_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_CTRL_TRIG +// Description : DMA Channel 7 Control and Status +#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) +#define DMA_CH7_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0) +#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH7_AL1_CTRL_RESET "-" +#define DMA_CH7_AL1_CTRL_MSB _u(31) +#define DMA_CH7_AL1_CTRL_LSB _u(0) +#define DMA_CH7_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4) +#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL1_READ_ADDR_RESET "-" +#define DMA_CH7_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8) +#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 7 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0) +#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH7_AL2_CTRL_RESET "-" +#define DMA_CH7_AL2_CTRL_MSB _u(31) +#define DMA_CH7_AL2_CTRL_LSB _u(0) +#define DMA_CH7_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4) +#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8) +#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL2_READ_ADDR_RESET "-" +#define DMA_CH7_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 7 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0) +#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH7_AL3_CTRL_RESET "-" +#define DMA_CH7_AL3_CTRL_MSB _u(31) +#define DMA_CH7_AL3_CTRL_LSB _u(0) +#define DMA_CH7_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4) +#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8) +#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_READ_ADDR_TRIG +// Description : Alias for channel 7 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc) +#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_READ_ADDR +// Description : DMA Channel 8 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200) +#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH8_READ_ADDR_MSB _u(31) +#define DMA_CH8_READ_ADDR_LSB _u(0) +#define DMA_CH8_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_WRITE_ADDR +// Description : DMA Channel 8 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204) +#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH8_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_TRANS_COUNT +// Description : DMA Channel 8 Transfer Count +#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208) +#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH8_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH8_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH8_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH8_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH8_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH8_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH8_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH8_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH8_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH8_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH8_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH8_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH8_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_CTRL_TRIG +// Description : DMA Channel 8 Control and Status +#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) +#define DMA_CH8_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH8_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210) +#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH8_AL1_CTRL_RESET "-" +#define DMA_CH8_AL1_CTRL_MSB _u(31) +#define DMA_CH8_AL1_CTRL_LSB _u(0) +#define DMA_CH8_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214) +#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL1_READ_ADDR_RESET "-" +#define DMA_CH8_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218) +#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 8 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220) +#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH8_AL2_CTRL_RESET "-" +#define DMA_CH8_AL2_CTRL_MSB _u(31) +#define DMA_CH8_AL2_CTRL_LSB _u(0) +#define DMA_CH8_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224) +#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228) +#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL2_READ_ADDR_RESET "-" +#define DMA_CH8_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 8 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230) +#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH8_AL3_CTRL_RESET "-" +#define DMA_CH8_AL3_CTRL_MSB _u(31) +#define DMA_CH8_AL3_CTRL_LSB _u(0) +#define DMA_CH8_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234) +#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238) +#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_READ_ADDR_TRIG +// Description : Alias for channel 8 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c) +#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_READ_ADDR +// Description : DMA Channel 9 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240) +#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH9_READ_ADDR_MSB _u(31) +#define DMA_CH9_READ_ADDR_LSB _u(0) +#define DMA_CH9_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_WRITE_ADDR +// Description : DMA Channel 9 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244) +#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH9_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_TRANS_COUNT +// Description : DMA Channel 9 Transfer Count +#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248) +#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH9_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH9_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH9_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH9_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH9_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH9_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH9_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH9_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH9_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH9_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH9_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH9_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH9_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_CTRL_TRIG +// Description : DMA Channel 9 Control and Status +#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) +#define DMA_CH9_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH9_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250) +#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH9_AL1_CTRL_RESET "-" +#define DMA_CH9_AL1_CTRL_MSB _u(31) +#define DMA_CH9_AL1_CTRL_LSB _u(0) +#define DMA_CH9_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254) +#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL1_READ_ADDR_RESET "-" +#define DMA_CH9_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258) +#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 9 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260) +#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH9_AL2_CTRL_RESET "-" +#define DMA_CH9_AL2_CTRL_MSB _u(31) +#define DMA_CH9_AL2_CTRL_LSB _u(0) +#define DMA_CH9_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264) +#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268) +#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL2_READ_ADDR_RESET "-" +#define DMA_CH9_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 9 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270) +#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH9_AL3_CTRL_RESET "-" +#define DMA_CH9_AL3_CTRL_MSB _u(31) +#define DMA_CH9_AL3_CTRL_LSB _u(0) +#define DMA_CH9_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274) +#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278) +#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_READ_ADDR_TRIG +// Description : Alias for channel 9 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c) +#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_READ_ADDR +// Description : DMA Channel 10 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280) +#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH10_READ_ADDR_MSB _u(31) +#define DMA_CH10_READ_ADDR_LSB _u(0) +#define DMA_CH10_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_WRITE_ADDR +// Description : DMA Channel 10 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284) +#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH10_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_TRANS_COUNT +// Description : DMA Channel 10 Transfer Count +#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288) +#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH10_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH10_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH10_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH10_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH10_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH10_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH10_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH10_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH10_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH10_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH10_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH10_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH10_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_CTRL_TRIG +// Description : DMA Channel 10 Control and Status +#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) +#define DMA_CH10_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH10_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290) +#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH10_AL1_CTRL_RESET "-" +#define DMA_CH10_AL1_CTRL_MSB _u(31) +#define DMA_CH10_AL1_CTRL_LSB _u(0) +#define DMA_CH10_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294) +#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL1_READ_ADDR_RESET "-" +#define DMA_CH10_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298) +#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 10 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0) +#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH10_AL2_CTRL_RESET "-" +#define DMA_CH10_AL2_CTRL_MSB _u(31) +#define DMA_CH10_AL2_CTRL_LSB _u(0) +#define DMA_CH10_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4) +#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8) +#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL2_READ_ADDR_RESET "-" +#define DMA_CH10_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 10 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0) +#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH10_AL3_CTRL_RESET "-" +#define DMA_CH10_AL3_CTRL_MSB _u(31) +#define DMA_CH10_AL3_CTRL_LSB _u(0) +#define DMA_CH10_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4) +#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8) +#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_READ_ADDR_TRIG +// Description : Alias for channel 10 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc) +#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_READ_ADDR +// Description : DMA Channel 11 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0) +#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH11_READ_ADDR_MSB _u(31) +#define DMA_CH11_READ_ADDR_LSB _u(0) +#define DMA_CH11_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_WRITE_ADDR +// Description : DMA Channel 11 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4) +#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH11_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_TRANS_COUNT +// Description : DMA Channel 11 Transfer Count +#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8) +#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH11_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH11_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH11_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH11_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH11_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH11_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH11_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH11_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH11_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH11_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH11_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH11_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH11_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_CTRL_TRIG +// Description : DMA Channel 11 Control and Status +#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) +#define DMA_CH11_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH11_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0) +#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH11_AL1_CTRL_RESET "-" +#define DMA_CH11_AL1_CTRL_MSB _u(31) +#define DMA_CH11_AL1_CTRL_LSB _u(0) +#define DMA_CH11_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4) +#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL1_READ_ADDR_RESET "-" +#define DMA_CH11_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8) +#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 11 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0) +#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH11_AL2_CTRL_RESET "-" +#define DMA_CH11_AL2_CTRL_MSB _u(31) +#define DMA_CH11_AL2_CTRL_LSB _u(0) +#define DMA_CH11_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4) +#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8) +#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL2_READ_ADDR_RESET "-" +#define DMA_CH11_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 11 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0) +#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH11_AL3_CTRL_RESET "-" +#define DMA_CH11_AL3_CTRL_MSB _u(31) +#define DMA_CH11_AL3_CTRL_LSB _u(0) +#define DMA_CH11_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4) +#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8) +#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_READ_ADDR_TRIG +// Description : Alias for channel 11 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc) +#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_READ_ADDR +// Description : DMA Channel 12 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH12_READ_ADDR_OFFSET _u(0x00000300) +#define DMA_CH12_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH12_READ_ADDR_MSB _u(31) +#define DMA_CH12_READ_ADDR_LSB _u(0) +#define DMA_CH12_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_WRITE_ADDR +// Description : DMA Channel 12 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH12_WRITE_ADDR_OFFSET _u(0x00000304) +#define DMA_CH12_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH12_WRITE_ADDR_MSB _u(31) +#define DMA_CH12_WRITE_ADDR_LSB _u(0) +#define DMA_CH12_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_TRANS_COUNT +// Description : DMA Channel 12 Transfer Count +#define DMA_CH12_TRANS_COUNT_OFFSET _u(0x00000308) +#define DMA_CH12_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH12_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH12_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH12_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH12_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH12_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH12_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH12_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH12_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH12_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH12_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH12_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH12_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH12_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH12_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_CTRL_TRIG +// Description : DMA Channel 12 Control and Status +#define DMA_CH12_CTRL_TRIG_OFFSET _u(0x0000030c) +#define DMA_CH12_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH12_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH12_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH12_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH12_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH12_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH12_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH12_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH12_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH12_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH12_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH12_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH12_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH12_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH12_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH12_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH12_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH12_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH12_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH12_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH12_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH12_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH12_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH12_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_CTRL +// Description : Alias for channel 12 CTRL register +#define DMA_CH12_AL1_CTRL_OFFSET _u(0x00000310) +#define DMA_CH12_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH12_AL1_CTRL_RESET "-" +#define DMA_CH12_AL1_CTRL_MSB _u(31) +#define DMA_CH12_AL1_CTRL_LSB _u(0) +#define DMA_CH12_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_READ_ADDR +// Description : Alias for channel 12 READ_ADDR register +#define DMA_CH12_AL1_READ_ADDR_OFFSET _u(0x00000314) +#define DMA_CH12_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL1_READ_ADDR_RESET "-" +#define DMA_CH12_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH12_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH12_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_WRITE_ADDR +// Description : Alias for channel 12 WRITE_ADDR register +#define DMA_CH12_AL1_WRITE_ADDR_OFFSET _u(0x00000318) +#define DMA_CH12_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH12_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH12_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH12_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 12 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000031c) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_CTRL +// Description : Alias for channel 12 CTRL register +#define DMA_CH12_AL2_CTRL_OFFSET _u(0x00000320) +#define DMA_CH12_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH12_AL2_CTRL_RESET "-" +#define DMA_CH12_AL2_CTRL_MSB _u(31) +#define DMA_CH12_AL2_CTRL_LSB _u(0) +#define DMA_CH12_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_TRANS_COUNT +// Description : Alias for channel 12 TRANS_COUNT register +#define DMA_CH12_AL2_TRANS_COUNT_OFFSET _u(0x00000324) +#define DMA_CH12_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH12_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH12_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH12_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH12_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_READ_ADDR +// Description : Alias for channel 12 READ_ADDR register +#define DMA_CH12_AL2_READ_ADDR_OFFSET _u(0x00000328) +#define DMA_CH12_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL2_READ_ADDR_RESET "-" +#define DMA_CH12_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH12_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH12_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 12 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000032c) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_CTRL +// Description : Alias for channel 12 CTRL register +#define DMA_CH12_AL3_CTRL_OFFSET _u(0x00000330) +#define DMA_CH12_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH12_AL3_CTRL_RESET "-" +#define DMA_CH12_AL3_CTRL_MSB _u(31) +#define DMA_CH12_AL3_CTRL_LSB _u(0) +#define DMA_CH12_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_WRITE_ADDR +// Description : Alias for channel 12 WRITE_ADDR register +#define DMA_CH12_AL3_WRITE_ADDR_OFFSET _u(0x00000334) +#define DMA_CH12_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH12_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH12_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH12_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_TRANS_COUNT +// Description : Alias for channel 12 TRANS_COUNT register +#define DMA_CH12_AL3_TRANS_COUNT_OFFSET _u(0x00000338) +#define DMA_CH12_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH12_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH12_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH12_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH12_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_READ_ADDR_TRIG +// Description : Alias for channel 12 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH12_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000033c) +#define DMA_CH12_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH12_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH12_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH12_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH12_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_READ_ADDR +// Description : DMA Channel 13 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH13_READ_ADDR_OFFSET _u(0x00000340) +#define DMA_CH13_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH13_READ_ADDR_MSB _u(31) +#define DMA_CH13_READ_ADDR_LSB _u(0) +#define DMA_CH13_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_WRITE_ADDR +// Description : DMA Channel 13 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH13_WRITE_ADDR_OFFSET _u(0x00000344) +#define DMA_CH13_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH13_WRITE_ADDR_MSB _u(31) +#define DMA_CH13_WRITE_ADDR_LSB _u(0) +#define DMA_CH13_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_TRANS_COUNT +// Description : DMA Channel 13 Transfer Count +#define DMA_CH13_TRANS_COUNT_OFFSET _u(0x00000348) +#define DMA_CH13_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH13_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH13_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH13_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH13_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH13_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH13_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH13_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH13_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH13_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH13_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH13_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH13_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH13_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH13_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_CTRL_TRIG +// Description : DMA Channel 13 Control and Status +#define DMA_CH13_CTRL_TRIG_OFFSET _u(0x0000034c) +#define DMA_CH13_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH13_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH13_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH13_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH13_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH13_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH13_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH13_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH13_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH13_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH13_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH13_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH13_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH13_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH13_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH13_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH13_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH13_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH13_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH13_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH13_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH13_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH13_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH13_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_CTRL +// Description : Alias for channel 13 CTRL register +#define DMA_CH13_AL1_CTRL_OFFSET _u(0x00000350) +#define DMA_CH13_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH13_AL1_CTRL_RESET "-" +#define DMA_CH13_AL1_CTRL_MSB _u(31) +#define DMA_CH13_AL1_CTRL_LSB _u(0) +#define DMA_CH13_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_READ_ADDR +// Description : Alias for channel 13 READ_ADDR register +#define DMA_CH13_AL1_READ_ADDR_OFFSET _u(0x00000354) +#define DMA_CH13_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL1_READ_ADDR_RESET "-" +#define DMA_CH13_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH13_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH13_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_WRITE_ADDR +// Description : Alias for channel 13 WRITE_ADDR register +#define DMA_CH13_AL1_WRITE_ADDR_OFFSET _u(0x00000358) +#define DMA_CH13_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH13_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH13_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH13_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 13 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000035c) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_CTRL +// Description : Alias for channel 13 CTRL register +#define DMA_CH13_AL2_CTRL_OFFSET _u(0x00000360) +#define DMA_CH13_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH13_AL2_CTRL_RESET "-" +#define DMA_CH13_AL2_CTRL_MSB _u(31) +#define DMA_CH13_AL2_CTRL_LSB _u(0) +#define DMA_CH13_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_TRANS_COUNT +// Description : Alias for channel 13 TRANS_COUNT register +#define DMA_CH13_AL2_TRANS_COUNT_OFFSET _u(0x00000364) +#define DMA_CH13_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH13_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH13_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH13_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH13_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_READ_ADDR +// Description : Alias for channel 13 READ_ADDR register +#define DMA_CH13_AL2_READ_ADDR_OFFSET _u(0x00000368) +#define DMA_CH13_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL2_READ_ADDR_RESET "-" +#define DMA_CH13_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH13_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH13_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 13 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000036c) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_CTRL +// Description : Alias for channel 13 CTRL register +#define DMA_CH13_AL3_CTRL_OFFSET _u(0x00000370) +#define DMA_CH13_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH13_AL3_CTRL_RESET "-" +#define DMA_CH13_AL3_CTRL_MSB _u(31) +#define DMA_CH13_AL3_CTRL_LSB _u(0) +#define DMA_CH13_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_WRITE_ADDR +// Description : Alias for channel 13 WRITE_ADDR register +#define DMA_CH13_AL3_WRITE_ADDR_OFFSET _u(0x00000374) +#define DMA_CH13_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH13_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH13_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH13_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_TRANS_COUNT +// Description : Alias for channel 13 TRANS_COUNT register +#define DMA_CH13_AL3_TRANS_COUNT_OFFSET _u(0x00000378) +#define DMA_CH13_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH13_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH13_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH13_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH13_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_READ_ADDR_TRIG +// Description : Alias for channel 13 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH13_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000037c) +#define DMA_CH13_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH13_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH13_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH13_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH13_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_READ_ADDR +// Description : DMA Channel 14 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH14_READ_ADDR_OFFSET _u(0x00000380) +#define DMA_CH14_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH14_READ_ADDR_MSB _u(31) +#define DMA_CH14_READ_ADDR_LSB _u(0) +#define DMA_CH14_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_WRITE_ADDR +// Description : DMA Channel 14 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH14_WRITE_ADDR_OFFSET _u(0x00000384) +#define DMA_CH14_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH14_WRITE_ADDR_MSB _u(31) +#define DMA_CH14_WRITE_ADDR_LSB _u(0) +#define DMA_CH14_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_TRANS_COUNT +// Description : DMA Channel 14 Transfer Count +#define DMA_CH14_TRANS_COUNT_OFFSET _u(0x00000388) +#define DMA_CH14_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH14_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH14_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH14_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH14_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH14_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH14_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH14_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH14_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH14_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH14_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH14_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH14_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH14_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH14_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_CTRL_TRIG +// Description : DMA Channel 14 Control and Status +#define DMA_CH14_CTRL_TRIG_OFFSET _u(0x0000038c) +#define DMA_CH14_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH14_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH14_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH14_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH14_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH14_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH14_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH14_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH14_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH14_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH14_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH14_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH14_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH14_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH14_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH14_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH14_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH14_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH14_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH14_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH14_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH14_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH14_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH14_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_CTRL +// Description : Alias for channel 14 CTRL register +#define DMA_CH14_AL1_CTRL_OFFSET _u(0x00000390) +#define DMA_CH14_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH14_AL1_CTRL_RESET "-" +#define DMA_CH14_AL1_CTRL_MSB _u(31) +#define DMA_CH14_AL1_CTRL_LSB _u(0) +#define DMA_CH14_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_READ_ADDR +// Description : Alias for channel 14 READ_ADDR register +#define DMA_CH14_AL1_READ_ADDR_OFFSET _u(0x00000394) +#define DMA_CH14_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL1_READ_ADDR_RESET "-" +#define DMA_CH14_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH14_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH14_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_WRITE_ADDR +// Description : Alias for channel 14 WRITE_ADDR register +#define DMA_CH14_AL1_WRITE_ADDR_OFFSET _u(0x00000398) +#define DMA_CH14_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH14_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH14_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH14_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 14 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000039c) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_CTRL +// Description : Alias for channel 14 CTRL register +#define DMA_CH14_AL2_CTRL_OFFSET _u(0x000003a0) +#define DMA_CH14_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH14_AL2_CTRL_RESET "-" +#define DMA_CH14_AL2_CTRL_MSB _u(31) +#define DMA_CH14_AL2_CTRL_LSB _u(0) +#define DMA_CH14_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_TRANS_COUNT +// Description : Alias for channel 14 TRANS_COUNT register +#define DMA_CH14_AL2_TRANS_COUNT_OFFSET _u(0x000003a4) +#define DMA_CH14_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH14_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH14_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH14_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH14_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_READ_ADDR +// Description : Alias for channel 14 READ_ADDR register +#define DMA_CH14_AL2_READ_ADDR_OFFSET _u(0x000003a8) +#define DMA_CH14_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL2_READ_ADDR_RESET "-" +#define DMA_CH14_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH14_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH14_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 14 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ac) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_CTRL +// Description : Alias for channel 14 CTRL register +#define DMA_CH14_AL3_CTRL_OFFSET _u(0x000003b0) +#define DMA_CH14_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH14_AL3_CTRL_RESET "-" +#define DMA_CH14_AL3_CTRL_MSB _u(31) +#define DMA_CH14_AL3_CTRL_LSB _u(0) +#define DMA_CH14_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_WRITE_ADDR +// Description : Alias for channel 14 WRITE_ADDR register +#define DMA_CH14_AL3_WRITE_ADDR_OFFSET _u(0x000003b4) +#define DMA_CH14_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH14_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH14_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH14_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_TRANS_COUNT +// Description : Alias for channel 14 TRANS_COUNT register +#define DMA_CH14_AL3_TRANS_COUNT_OFFSET _u(0x000003b8) +#define DMA_CH14_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH14_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH14_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH14_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH14_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_READ_ADDR_TRIG +// Description : Alias for channel 14 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH14_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003bc) +#define DMA_CH14_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH14_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH14_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH14_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH14_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_READ_ADDR +// Description : DMA Channel 15 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH15_READ_ADDR_OFFSET _u(0x000003c0) +#define DMA_CH15_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH15_READ_ADDR_MSB _u(31) +#define DMA_CH15_READ_ADDR_LSB _u(0) +#define DMA_CH15_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_WRITE_ADDR +// Description : DMA Channel 15 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH15_WRITE_ADDR_OFFSET _u(0x000003c4) +#define DMA_CH15_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH15_WRITE_ADDR_MSB _u(31) +#define DMA_CH15_WRITE_ADDR_LSB _u(0) +#define DMA_CH15_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_TRANS_COUNT +// Description : DMA Channel 15 Transfer Count +#define DMA_CH15_TRANS_COUNT_OFFSET _u(0x000003c8) +#define DMA_CH15_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH15_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH15_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH15_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH15_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH15_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH15_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH15_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH15_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH15_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH15_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH15_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH15_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH15_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH15_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_CTRL_TRIG +// Description : DMA Channel 15 Control and Status +#define DMA_CH15_CTRL_TRIG_OFFSET _u(0x000003cc) +#define DMA_CH15_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH15_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH15_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH15_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH15_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH15_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH15_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH15_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH15_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH15_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH15_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH15_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH15_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH15_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH15_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH15_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH15_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH15_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH15_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH15_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH15_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH15_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH15_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH15_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_CTRL +// Description : Alias for channel 15 CTRL register +#define DMA_CH15_AL1_CTRL_OFFSET _u(0x000003d0) +#define DMA_CH15_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH15_AL1_CTRL_RESET "-" +#define DMA_CH15_AL1_CTRL_MSB _u(31) +#define DMA_CH15_AL1_CTRL_LSB _u(0) +#define DMA_CH15_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_READ_ADDR +// Description : Alias for channel 15 READ_ADDR register +#define DMA_CH15_AL1_READ_ADDR_OFFSET _u(0x000003d4) +#define DMA_CH15_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL1_READ_ADDR_RESET "-" +#define DMA_CH15_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH15_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH15_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_WRITE_ADDR +// Description : Alias for channel 15 WRITE_ADDR register +#define DMA_CH15_AL1_WRITE_ADDR_OFFSET _u(0x000003d8) +#define DMA_CH15_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH15_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH15_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH15_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 15 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000003dc) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_CTRL +// Description : Alias for channel 15 CTRL register +#define DMA_CH15_AL2_CTRL_OFFSET _u(0x000003e0) +#define DMA_CH15_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH15_AL2_CTRL_RESET "-" +#define DMA_CH15_AL2_CTRL_MSB _u(31) +#define DMA_CH15_AL2_CTRL_LSB _u(0) +#define DMA_CH15_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_TRANS_COUNT +// Description : Alias for channel 15 TRANS_COUNT register +#define DMA_CH15_AL2_TRANS_COUNT_OFFSET _u(0x000003e4) +#define DMA_CH15_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH15_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH15_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH15_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH15_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_READ_ADDR +// Description : Alias for channel 15 READ_ADDR register +#define DMA_CH15_AL2_READ_ADDR_OFFSET _u(0x000003e8) +#define DMA_CH15_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL2_READ_ADDR_RESET "-" +#define DMA_CH15_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH15_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH15_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 15 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ec) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_CTRL +// Description : Alias for channel 15 CTRL register +#define DMA_CH15_AL3_CTRL_OFFSET _u(0x000003f0) +#define DMA_CH15_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH15_AL3_CTRL_RESET "-" +#define DMA_CH15_AL3_CTRL_MSB _u(31) +#define DMA_CH15_AL3_CTRL_LSB _u(0) +#define DMA_CH15_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_WRITE_ADDR +// Description : Alias for channel 15 WRITE_ADDR register +#define DMA_CH15_AL3_WRITE_ADDR_OFFSET _u(0x000003f4) +#define DMA_CH15_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH15_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH15_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH15_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_TRANS_COUNT +// Description : Alias for channel 15 TRANS_COUNT register +#define DMA_CH15_AL3_TRANS_COUNT_OFFSET _u(0x000003f8) +#define DMA_CH15_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH15_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH15_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH15_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH15_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_READ_ADDR_TRIG +// Description : Alias for channel 15 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH15_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003fc) +#define DMA_CH15_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH15_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH15_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH15_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH15_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTR +// Description : Interrupt Status (raw) +// Raw interrupt status for DMA Channels 0..15. Bit n corresponds +// to channel n. Ignores any masking or forcing. Channel +// interrupts can be cleared by writing a bit mask to INTR or +// INTS0/1/2/3. +// +// Channel interrupts can be routed to either of four system-level +// IRQs based on INTE0, INTE1, INTE2 and INTE3. +// +// The multiple system-level interrupts might be used to allow +// NVIC IRQ preemption for more time-critical channels, to spread +// IRQ load across different cores, or to target IRQs to different +// security domains. +// +// It is also valid to ignore the multiple IRQs, and just use +// INTE0/INTS0/IRQ 0. +// +// If this register is accessed at a security/privilege level less +// than that of a given channel (as defined by that channel's +// SECCFG_CHx register), then that channel's interrupt status will +// read as 0, ignore writes. +#define DMA_INTR_OFFSET _u(0x00000400) +#define DMA_INTR_BITS _u(0x0000ffff) +#define DMA_INTR_RESET _u(0x00000000) +#define DMA_INTR_MSB _u(15) +#define DMA_INTR_LSB _u(0) +#define DMA_INTR_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE0 +// Description : Interrupt Enables for IRQ 0 +// Set bit n to pass interrupts from channel n to DMA IRQ 0. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ0. +#define DMA_INTE0_OFFSET _u(0x00000404) +#define DMA_INTE0_BITS _u(0x0000ffff) +#define DMA_INTE0_RESET _u(0x00000000) +#define DMA_INTE0_MSB _u(15) +#define DMA_INTE0_LSB _u(0) +#define DMA_INTE0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF0 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS0. The +// interrupt remains asserted until INTF0 is cleared. +#define DMA_INTF0_OFFSET _u(0x00000408) +#define DMA_INTF0_BITS _u(0x0000ffff) +#define DMA_INTF0_RESET _u(0x00000000) +#define DMA_INTF0_MSB _u(15) +#define DMA_INTF0_LSB _u(0) +#define DMA_INTF0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS0 +// Description : Interrupt Status for IRQ 0 +// Indicates active channel interrupt requests which are currently +// causing IRQ 0 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ0) read as 0 in this register, and ignore writes. +#define DMA_INTS0_OFFSET _u(0x0000040c) +#define DMA_INTS0_BITS _u(0x0000ffff) +#define DMA_INTS0_RESET _u(0x00000000) +#define DMA_INTS0_MSB _u(15) +#define DMA_INTS0_LSB _u(0) +#define DMA_INTS0_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE1 +// Description : Interrupt Enables for IRQ 1 +// Set bit n to pass interrupts from channel n to DMA IRQ 1. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ1. +#define DMA_INTE1_OFFSET _u(0x00000414) +#define DMA_INTE1_BITS _u(0x0000ffff) +#define DMA_INTE1_RESET _u(0x00000000) +#define DMA_INTE1_MSB _u(15) +#define DMA_INTE1_LSB _u(0) +#define DMA_INTE1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF1 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS1. The +// interrupt remains asserted until INTF1 is cleared. +#define DMA_INTF1_OFFSET _u(0x00000418) +#define DMA_INTF1_BITS _u(0x0000ffff) +#define DMA_INTF1_RESET _u(0x00000000) +#define DMA_INTF1_MSB _u(15) +#define DMA_INTF1_LSB _u(0) +#define DMA_INTF1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS1 +// Description : Interrupt Status for IRQ 1 +// Indicates active channel interrupt requests which are currently +// causing IRQ 1 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ1) read as 0 in this register, and ignore writes. +#define DMA_INTS1_OFFSET _u(0x0000041c) +#define DMA_INTS1_BITS _u(0x0000ffff) +#define DMA_INTS1_RESET _u(0x00000000) +#define DMA_INTS1_MSB _u(15) +#define DMA_INTS1_LSB _u(0) +#define DMA_INTS1_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE2 +// Description : Interrupt Enables for IRQ 2 +// Set bit n to pass interrupts from channel n to DMA IRQ 2. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ2. +#define DMA_INTE2_OFFSET _u(0x00000424) +#define DMA_INTE2_BITS _u(0x0000ffff) +#define DMA_INTE2_RESET _u(0x00000000) +#define DMA_INTE2_MSB _u(15) +#define DMA_INTE2_LSB _u(0) +#define DMA_INTE2_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF2 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS2. The +// interrupt remains asserted until INTF2 is cleared. +#define DMA_INTF2_OFFSET _u(0x00000428) +#define DMA_INTF2_BITS _u(0x0000ffff) +#define DMA_INTF2_RESET _u(0x00000000) +#define DMA_INTF2_MSB _u(15) +#define DMA_INTF2_LSB _u(0) +#define DMA_INTF2_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS2 +// Description : Interrupt Status for IRQ 2 +// Indicates active channel interrupt requests which are currently +// causing IRQ 2 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ2) read as 0 in this register, and ignore writes. +#define DMA_INTS2_OFFSET _u(0x0000042c) +#define DMA_INTS2_BITS _u(0x0000ffff) +#define DMA_INTS2_RESET _u(0x00000000) +#define DMA_INTS2_MSB _u(15) +#define DMA_INTS2_LSB _u(0) +#define DMA_INTS2_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE3 +// Description : Interrupt Enables for IRQ 3 +// Set bit n to pass interrupts from channel n to DMA IRQ 3. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ3. +#define DMA_INTE3_OFFSET _u(0x00000434) +#define DMA_INTE3_BITS _u(0x0000ffff) +#define DMA_INTE3_RESET _u(0x00000000) +#define DMA_INTE3_MSB _u(15) +#define DMA_INTE3_LSB _u(0) +#define DMA_INTE3_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF3 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS3. The +// interrupt remains asserted until INTF3 is cleared. +#define DMA_INTF3_OFFSET _u(0x00000438) +#define DMA_INTF3_BITS _u(0x0000ffff) +#define DMA_INTF3_RESET _u(0x00000000) +#define DMA_INTF3_MSB _u(15) +#define DMA_INTF3_LSB _u(0) +#define DMA_INTF3_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS3 +// Description : Interrupt Status for IRQ 3 +// Indicates active channel interrupt requests which are currently +// causing IRQ 3 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ3) read as 0 in this register, and ignore writes. +#define DMA_INTS3_OFFSET _u(0x0000043c) +#define DMA_INTS3_BITS _u(0x0000ffff) +#define DMA_INTS3_RESET _u(0x00000000) +#define DMA_INTS3_MSB _u(15) +#define DMA_INTS3_LSB _u(0) +#define DMA_INTS3_ACCESS "WC" +// ============================================================================= +// Register : DMA_TIMER0 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER0_OFFSET _u(0x00000440) +#define DMA_TIMER0_BITS _u(0xffffffff) +#define DMA_TIMER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_X_RESET _u(0x0000) +#define DMA_TIMER0_X_BITS _u(0xffff0000) +#define DMA_TIMER0_X_MSB _u(31) +#define DMA_TIMER0_X_LSB _u(16) +#define DMA_TIMER0_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_Y_RESET _u(0x0000) +#define DMA_TIMER0_Y_BITS _u(0x0000ffff) +#define DMA_TIMER0_Y_MSB _u(15) +#define DMA_TIMER0_Y_LSB _u(0) +#define DMA_TIMER0_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER1 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER1_OFFSET _u(0x00000444) +#define DMA_TIMER1_BITS _u(0xffffffff) +#define DMA_TIMER1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_X_RESET _u(0x0000) +#define DMA_TIMER1_X_BITS _u(0xffff0000) +#define DMA_TIMER1_X_MSB _u(31) +#define DMA_TIMER1_X_LSB _u(16) +#define DMA_TIMER1_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_Y_RESET _u(0x0000) +#define DMA_TIMER1_Y_BITS _u(0x0000ffff) +#define DMA_TIMER1_Y_MSB _u(15) +#define DMA_TIMER1_Y_LSB _u(0) +#define DMA_TIMER1_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER2 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER2_OFFSET _u(0x00000448) +#define DMA_TIMER2_BITS _u(0xffffffff) +#define DMA_TIMER2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_X_RESET _u(0x0000) +#define DMA_TIMER2_X_BITS _u(0xffff0000) +#define DMA_TIMER2_X_MSB _u(31) +#define DMA_TIMER2_X_LSB _u(16) +#define DMA_TIMER2_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_Y_RESET _u(0x0000) +#define DMA_TIMER2_Y_BITS _u(0x0000ffff) +#define DMA_TIMER2_Y_MSB _u(15) +#define DMA_TIMER2_Y_LSB _u(0) +#define DMA_TIMER2_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER3 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER3_OFFSET _u(0x0000044c) +#define DMA_TIMER3_BITS _u(0xffffffff) +#define DMA_TIMER3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_X_RESET _u(0x0000) +#define DMA_TIMER3_X_BITS _u(0xffff0000) +#define DMA_TIMER3_X_MSB _u(31) +#define DMA_TIMER3_X_LSB _u(16) +#define DMA_TIMER3_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_Y_RESET _u(0x0000) +#define DMA_TIMER3_Y_BITS _u(0x0000ffff) +#define DMA_TIMER3_Y_MSB _u(15) +#define DMA_TIMER3_Y_LSB _u(0) +#define DMA_TIMER3_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_MULTI_CHAN_TRIGGER +// Description : Trigger one or more channels simultaneously +// Each bit in this register corresponds to a DMA channel. Writing +// a 1 to the relevant bit is the same as writing to that +// channel's trigger register; the channel will start if it is +// currently enabled and not already busy. +#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000450) +#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff) +#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000) +#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15) +#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0) +#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" +// ============================================================================= +// Register : DMA_SNIFF_CTRL +// Description : Sniffer Control +#define DMA_SNIFF_CTRL_OFFSET _u(0x00000454) +#define DMA_SNIFF_CTRL_BITS _u(0x00000fff) +#define DMA_SNIFF_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_INV +// Description : If set, the result appears inverted (bitwise complement) when +// read. This does not affect the way the checksum is calculated; +// the result is transformed on-the-fly between the result +// register and the bus. +#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800) +#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11) +#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11) +#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_REV +// Description : If set, the result appears bit-reversed when read. This does +// not affect the way the checksum is calculated; the result is +// transformed on-the-fly between the result register and the bus. +#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400) +#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10) +#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10) +#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_BSWAP +// Description : Locally perform a byte reverse on the sniffed data, before +// feeding into checksum. +// +// Note that the sniff hardware is downstream of the DMA channel +// byteswap performed in the read master: if channel CTRL_BSWAP +// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel +// from the sniffer's point of view. +#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0) +#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200) +#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9) +#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9) +#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_CALC +// 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data +// 0x2 -> Calculate a CRC-16-CCITT +// 0x3 -> Calculate a CRC-16-CCITT with bit reversed data +// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) +#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) +#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) +#define DMA_SNIFF_CTRL_CALC_MSB _u(8) +#define DMA_SNIFF_CTRL_CALC_LSB _u(5) +#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_DMACH +// Description : DMA channel for Sniffer to observe +#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0) +#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e) +#define DMA_SNIFF_CTRL_DMACH_MSB _u(4) +#define DMA_SNIFF_CTRL_DMACH_LSB _u(1) +#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_EN +// Description : Enable sniffer +#define DMA_SNIFF_CTRL_EN_RESET _u(0x0) +#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001) +#define DMA_SNIFF_CTRL_EN_MSB _u(0) +#define DMA_SNIFF_CTRL_EN_LSB _u(0) +#define DMA_SNIFF_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_SNIFF_DATA +// Description : Data accumulator for sniff hardware +// Write an initial seed value here before starting a DMA transfer +// on the channel indicated by SNIFF_CTRL_DMACH. The hardware will +// update this register each time it observes a read from the +// indicated channel. Once the channel completes, the final result +// can be read from this register. +#define DMA_SNIFF_DATA_OFFSET _u(0x00000458) +#define DMA_SNIFF_DATA_BITS _u(0xffffffff) +#define DMA_SNIFF_DATA_RESET _u(0x00000000) +#define DMA_SNIFF_DATA_MSB _u(31) +#define DMA_SNIFF_DATA_LSB _u(0) +#define DMA_SNIFF_DATA_ACCESS "RW" +// ============================================================================= +// Register : DMA_FIFO_LEVELS +// Description : Debug RAF, WAF, TDF levels +#define DMA_FIFO_LEVELS_OFFSET _u(0x00000460) +#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff) +#define DMA_FIFO_LEVELS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_RAF_LVL +// Description : Current Read-Address-FIFO fill level +#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000) +#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23) +#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16) +#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_WAF_LVL +// Description : Current Write-Address-FIFO fill level +#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00) +#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15) +#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8) +#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_TDF_LVL +// Description : Current Transfer-Data-FIFO fill level +#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff) +#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7) +#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0) +#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CHAN_ABORT +// Description : Abort an in-progress transfer sequence on one or more channels +// Each bit corresponds to a channel. Writing a 1 aborts whatever +// transfer sequence is in progress on that channel. The bit will +// remain high until any in-flight transfers have been flushed +// through the address and data FIFOs. +// +// After writing, this register must be polled until it returns +// all-zero. Until this point, it is unsafe to restart the +// channel. +#define DMA_CHAN_ABORT_OFFSET _u(0x00000464) +#define DMA_CHAN_ABORT_BITS _u(0x0000ffff) +#define DMA_CHAN_ABORT_RESET _u(0x00000000) +#define DMA_CHAN_ABORT_MSB _u(15) +#define DMA_CHAN_ABORT_LSB _u(0) +#define DMA_CHAN_ABORT_ACCESS "SC" +// ============================================================================= +// Register : DMA_N_CHANNELS +// Description : The number of channels this DMA instance is equipped with. This +// DMA supports up to 16 hardware channels, but can be configured +// with as few as one, to minimise silicon area. +#define DMA_N_CHANNELS_OFFSET _u(0x00000468) +#define DMA_N_CHANNELS_BITS _u(0x0000001f) +#define DMA_N_CHANNELS_RESET "-" +#define DMA_N_CHANNELS_MSB _u(4) +#define DMA_N_CHANNELS_LSB _u(0) +#define DMA_N_CHANNELS_ACCESS "RO" +// ============================================================================= +// Register : DMA_SECCFG_CH0 +// Description : Security configuration for channel 0. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH0_OFFSET _u(0x00000480) +#define DMA_SECCFG_CH0_BITS _u(0x00000007) +#define DMA_SECCFG_CH0_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH0_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH0_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH0_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH0_LOCK_MSB _u(2) +#define DMA_SECCFG_CH0_LOCK_LSB _u(2) +#define DMA_SECCFG_CH0_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH0_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH0_S_RESET _u(0x1) +#define DMA_SECCFG_CH0_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH0_S_MSB _u(1) +#define DMA_SECCFG_CH0_S_LSB _u(1) +#define DMA_SECCFG_CH0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH0_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH0_P_RESET _u(0x1) +#define DMA_SECCFG_CH0_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH0_P_MSB _u(0) +#define DMA_SECCFG_CH0_P_LSB _u(0) +#define DMA_SECCFG_CH0_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH1 +// Description : Security configuration for channel 1. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH1_OFFSET _u(0x00000484) +#define DMA_SECCFG_CH1_BITS _u(0x00000007) +#define DMA_SECCFG_CH1_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH1_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH1_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH1_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH1_LOCK_MSB _u(2) +#define DMA_SECCFG_CH1_LOCK_LSB _u(2) +#define DMA_SECCFG_CH1_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH1_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH1_S_RESET _u(0x1) +#define DMA_SECCFG_CH1_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH1_S_MSB _u(1) +#define DMA_SECCFG_CH1_S_LSB _u(1) +#define DMA_SECCFG_CH1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH1_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH1_P_RESET _u(0x1) +#define DMA_SECCFG_CH1_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH1_P_MSB _u(0) +#define DMA_SECCFG_CH1_P_LSB _u(0) +#define DMA_SECCFG_CH1_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH2 +// Description : Security configuration for channel 2. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH2_OFFSET _u(0x00000488) +#define DMA_SECCFG_CH2_BITS _u(0x00000007) +#define DMA_SECCFG_CH2_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH2_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH2_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH2_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH2_LOCK_MSB _u(2) +#define DMA_SECCFG_CH2_LOCK_LSB _u(2) +#define DMA_SECCFG_CH2_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH2_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH2_S_RESET _u(0x1) +#define DMA_SECCFG_CH2_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH2_S_MSB _u(1) +#define DMA_SECCFG_CH2_S_LSB _u(1) +#define DMA_SECCFG_CH2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH2_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH2_P_RESET _u(0x1) +#define DMA_SECCFG_CH2_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH2_P_MSB _u(0) +#define DMA_SECCFG_CH2_P_LSB _u(0) +#define DMA_SECCFG_CH2_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH3 +// Description : Security configuration for channel 3. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH3_OFFSET _u(0x0000048c) +#define DMA_SECCFG_CH3_BITS _u(0x00000007) +#define DMA_SECCFG_CH3_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH3_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH3_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH3_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH3_LOCK_MSB _u(2) +#define DMA_SECCFG_CH3_LOCK_LSB _u(2) +#define DMA_SECCFG_CH3_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH3_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH3_S_RESET _u(0x1) +#define DMA_SECCFG_CH3_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH3_S_MSB _u(1) +#define DMA_SECCFG_CH3_S_LSB _u(1) +#define DMA_SECCFG_CH3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH3_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH3_P_RESET _u(0x1) +#define DMA_SECCFG_CH3_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH3_P_MSB _u(0) +#define DMA_SECCFG_CH3_P_LSB _u(0) +#define DMA_SECCFG_CH3_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH4 +// Description : Security configuration for channel 4. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH4_OFFSET _u(0x00000490) +#define DMA_SECCFG_CH4_BITS _u(0x00000007) +#define DMA_SECCFG_CH4_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH4_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH4_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH4_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH4_LOCK_MSB _u(2) +#define DMA_SECCFG_CH4_LOCK_LSB _u(2) +#define DMA_SECCFG_CH4_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH4_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH4_S_RESET _u(0x1) +#define DMA_SECCFG_CH4_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH4_S_MSB _u(1) +#define DMA_SECCFG_CH4_S_LSB _u(1) +#define DMA_SECCFG_CH4_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH4_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH4_P_RESET _u(0x1) +#define DMA_SECCFG_CH4_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH4_P_MSB _u(0) +#define DMA_SECCFG_CH4_P_LSB _u(0) +#define DMA_SECCFG_CH4_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH5 +// Description : Security configuration for channel 5. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH5_OFFSET _u(0x00000494) +#define DMA_SECCFG_CH5_BITS _u(0x00000007) +#define DMA_SECCFG_CH5_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH5_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH5_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH5_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH5_LOCK_MSB _u(2) +#define DMA_SECCFG_CH5_LOCK_LSB _u(2) +#define DMA_SECCFG_CH5_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH5_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH5_S_RESET _u(0x1) +#define DMA_SECCFG_CH5_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH5_S_MSB _u(1) +#define DMA_SECCFG_CH5_S_LSB _u(1) +#define DMA_SECCFG_CH5_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH5_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH5_P_RESET _u(0x1) +#define DMA_SECCFG_CH5_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH5_P_MSB _u(0) +#define DMA_SECCFG_CH5_P_LSB _u(0) +#define DMA_SECCFG_CH5_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH6 +// Description : Security configuration for channel 6. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH6_OFFSET _u(0x00000498) +#define DMA_SECCFG_CH6_BITS _u(0x00000007) +#define DMA_SECCFG_CH6_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH6_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH6_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH6_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH6_LOCK_MSB _u(2) +#define DMA_SECCFG_CH6_LOCK_LSB _u(2) +#define DMA_SECCFG_CH6_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH6_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH6_S_RESET _u(0x1) +#define DMA_SECCFG_CH6_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH6_S_MSB _u(1) +#define DMA_SECCFG_CH6_S_LSB _u(1) +#define DMA_SECCFG_CH6_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH6_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH6_P_RESET _u(0x1) +#define DMA_SECCFG_CH6_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH6_P_MSB _u(0) +#define DMA_SECCFG_CH6_P_LSB _u(0) +#define DMA_SECCFG_CH6_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH7 +// Description : Security configuration for channel 7. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH7_OFFSET _u(0x0000049c) +#define DMA_SECCFG_CH7_BITS _u(0x00000007) +#define DMA_SECCFG_CH7_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH7_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH7_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH7_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH7_LOCK_MSB _u(2) +#define DMA_SECCFG_CH7_LOCK_LSB _u(2) +#define DMA_SECCFG_CH7_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH7_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH7_S_RESET _u(0x1) +#define DMA_SECCFG_CH7_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH7_S_MSB _u(1) +#define DMA_SECCFG_CH7_S_LSB _u(1) +#define DMA_SECCFG_CH7_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH7_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH7_P_RESET _u(0x1) +#define DMA_SECCFG_CH7_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH7_P_MSB _u(0) +#define DMA_SECCFG_CH7_P_LSB _u(0) +#define DMA_SECCFG_CH7_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH8 +// Description : Security configuration for channel 8. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH8_OFFSET _u(0x000004a0) +#define DMA_SECCFG_CH8_BITS _u(0x00000007) +#define DMA_SECCFG_CH8_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH8_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH8_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH8_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH8_LOCK_MSB _u(2) +#define DMA_SECCFG_CH8_LOCK_LSB _u(2) +#define DMA_SECCFG_CH8_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH8_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH8_S_RESET _u(0x1) +#define DMA_SECCFG_CH8_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH8_S_MSB _u(1) +#define DMA_SECCFG_CH8_S_LSB _u(1) +#define DMA_SECCFG_CH8_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH8_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH8_P_RESET _u(0x1) +#define DMA_SECCFG_CH8_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH8_P_MSB _u(0) +#define DMA_SECCFG_CH8_P_LSB _u(0) +#define DMA_SECCFG_CH8_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH9 +// Description : Security configuration for channel 9. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH9_OFFSET _u(0x000004a4) +#define DMA_SECCFG_CH9_BITS _u(0x00000007) +#define DMA_SECCFG_CH9_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH9_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH9_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH9_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH9_LOCK_MSB _u(2) +#define DMA_SECCFG_CH9_LOCK_LSB _u(2) +#define DMA_SECCFG_CH9_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH9_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH9_S_RESET _u(0x1) +#define DMA_SECCFG_CH9_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH9_S_MSB _u(1) +#define DMA_SECCFG_CH9_S_LSB _u(1) +#define DMA_SECCFG_CH9_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH9_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH9_P_RESET _u(0x1) +#define DMA_SECCFG_CH9_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH9_P_MSB _u(0) +#define DMA_SECCFG_CH9_P_LSB _u(0) +#define DMA_SECCFG_CH9_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH10 +// Description : Security configuration for channel 10. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH10_OFFSET _u(0x000004a8) +#define DMA_SECCFG_CH10_BITS _u(0x00000007) +#define DMA_SECCFG_CH10_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH10_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH10_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH10_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH10_LOCK_MSB _u(2) +#define DMA_SECCFG_CH10_LOCK_LSB _u(2) +#define DMA_SECCFG_CH10_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH10_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH10_S_RESET _u(0x1) +#define DMA_SECCFG_CH10_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH10_S_MSB _u(1) +#define DMA_SECCFG_CH10_S_LSB _u(1) +#define DMA_SECCFG_CH10_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH10_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH10_P_RESET _u(0x1) +#define DMA_SECCFG_CH10_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH10_P_MSB _u(0) +#define DMA_SECCFG_CH10_P_LSB _u(0) +#define DMA_SECCFG_CH10_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH11 +// Description : Security configuration for channel 11. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH11_OFFSET _u(0x000004ac) +#define DMA_SECCFG_CH11_BITS _u(0x00000007) +#define DMA_SECCFG_CH11_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH11_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH11_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH11_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH11_LOCK_MSB _u(2) +#define DMA_SECCFG_CH11_LOCK_LSB _u(2) +#define DMA_SECCFG_CH11_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH11_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH11_S_RESET _u(0x1) +#define DMA_SECCFG_CH11_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH11_S_MSB _u(1) +#define DMA_SECCFG_CH11_S_LSB _u(1) +#define DMA_SECCFG_CH11_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH11_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH11_P_RESET _u(0x1) +#define DMA_SECCFG_CH11_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH11_P_MSB _u(0) +#define DMA_SECCFG_CH11_P_LSB _u(0) +#define DMA_SECCFG_CH11_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH12 +// Description : Security configuration for channel 12. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH12_OFFSET _u(0x000004b0) +#define DMA_SECCFG_CH12_BITS _u(0x00000007) +#define DMA_SECCFG_CH12_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH12_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH12_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH12_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH12_LOCK_MSB _u(2) +#define DMA_SECCFG_CH12_LOCK_LSB _u(2) +#define DMA_SECCFG_CH12_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH12_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH12_S_RESET _u(0x1) +#define DMA_SECCFG_CH12_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH12_S_MSB _u(1) +#define DMA_SECCFG_CH12_S_LSB _u(1) +#define DMA_SECCFG_CH12_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH12_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH12_P_RESET _u(0x1) +#define DMA_SECCFG_CH12_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH12_P_MSB _u(0) +#define DMA_SECCFG_CH12_P_LSB _u(0) +#define DMA_SECCFG_CH12_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH13 +// Description : Security configuration for channel 13. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH13_OFFSET _u(0x000004b4) +#define DMA_SECCFG_CH13_BITS _u(0x00000007) +#define DMA_SECCFG_CH13_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH13_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH13_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH13_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH13_LOCK_MSB _u(2) +#define DMA_SECCFG_CH13_LOCK_LSB _u(2) +#define DMA_SECCFG_CH13_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH13_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH13_S_RESET _u(0x1) +#define DMA_SECCFG_CH13_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH13_S_MSB _u(1) +#define DMA_SECCFG_CH13_S_LSB _u(1) +#define DMA_SECCFG_CH13_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH13_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH13_P_RESET _u(0x1) +#define DMA_SECCFG_CH13_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH13_P_MSB _u(0) +#define DMA_SECCFG_CH13_P_LSB _u(0) +#define DMA_SECCFG_CH13_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH14 +// Description : Security configuration for channel 14. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH14_OFFSET _u(0x000004b8) +#define DMA_SECCFG_CH14_BITS _u(0x00000007) +#define DMA_SECCFG_CH14_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH14_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH14_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH14_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH14_LOCK_MSB _u(2) +#define DMA_SECCFG_CH14_LOCK_LSB _u(2) +#define DMA_SECCFG_CH14_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH14_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH14_S_RESET _u(0x1) +#define DMA_SECCFG_CH14_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH14_S_MSB _u(1) +#define DMA_SECCFG_CH14_S_LSB _u(1) +#define DMA_SECCFG_CH14_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH14_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH14_P_RESET _u(0x1) +#define DMA_SECCFG_CH14_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH14_P_MSB _u(0) +#define DMA_SECCFG_CH14_P_LSB _u(0) +#define DMA_SECCFG_CH14_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH15 +// Description : Security configuration for channel 15. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH15_OFFSET _u(0x000004bc) +#define DMA_SECCFG_CH15_BITS _u(0x00000007) +#define DMA_SECCFG_CH15_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH15_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH15_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH15_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH15_LOCK_MSB _u(2) +#define DMA_SECCFG_CH15_LOCK_LSB _u(2) +#define DMA_SECCFG_CH15_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH15_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH15_S_RESET _u(0x1) +#define DMA_SECCFG_CH15_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH15_S_MSB _u(1) +#define DMA_SECCFG_CH15_S_LSB _u(1) +#define DMA_SECCFG_CH15_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH15_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH15_P_RESET _u(0x1) +#define DMA_SECCFG_CH15_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH15_P_MSB _u(0) +#define DMA_SECCFG_CH15_P_LSB _u(0) +#define DMA_SECCFG_CH15_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ0 +// Description : Security configuration for IRQ 0. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ0_OFFSET _u(0x000004c0) +#define DMA_SECCFG_IRQ0_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ0_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ0_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ0_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ0_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ0_S_MSB _u(1) +#define DMA_SECCFG_IRQ0_S_LSB _u(1) +#define DMA_SECCFG_IRQ0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ0_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ0_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ0_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ0_P_MSB _u(0) +#define DMA_SECCFG_IRQ0_P_LSB _u(0) +#define DMA_SECCFG_IRQ0_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ1 +// Description : Security configuration for IRQ 1. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ1_OFFSET _u(0x000004c4) +#define DMA_SECCFG_IRQ1_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ1_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ1_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ1_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ1_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ1_S_MSB _u(1) +#define DMA_SECCFG_IRQ1_S_LSB _u(1) +#define DMA_SECCFG_IRQ1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ1_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ1_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ1_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ1_P_MSB _u(0) +#define DMA_SECCFG_IRQ1_P_LSB _u(0) +#define DMA_SECCFG_IRQ1_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ2 +// Description : Security configuration for IRQ 2. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ2_OFFSET _u(0x000004c8) +#define DMA_SECCFG_IRQ2_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ2_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ2_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ2_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ2_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ2_S_MSB _u(1) +#define DMA_SECCFG_IRQ2_S_LSB _u(1) +#define DMA_SECCFG_IRQ2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ2_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ2_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ2_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ2_P_MSB _u(0) +#define DMA_SECCFG_IRQ2_P_LSB _u(0) +#define DMA_SECCFG_IRQ2_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ3 +// Description : Security configuration for IRQ 3. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ3_OFFSET _u(0x000004cc) +#define DMA_SECCFG_IRQ3_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ3_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ3_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ3_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ3_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ3_S_MSB _u(1) +#define DMA_SECCFG_IRQ3_S_LSB _u(1) +#define DMA_SECCFG_IRQ3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ3_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ3_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ3_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ3_P_MSB _u(0) +#define DMA_SECCFG_IRQ3_P_LSB _u(0) +#define DMA_SECCFG_IRQ3_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_MISC +// Description : Miscellaneous security configuration +#define DMA_SECCFG_MISC_OFFSET _u(0x000004d0) +#define DMA_SECCFG_MISC_BITS _u(0x000003ff) +#define DMA_SECCFG_MISC_RESET _u(0x000003ff) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER3_S +// Description : If 1, the TIMER3 register is only accessible from a Secure +// context, and timer DREQ 3 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER3_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER3_S_BITS _u(0x00000200) +#define DMA_SECCFG_MISC_TIMER3_S_MSB _u(9) +#define DMA_SECCFG_MISC_TIMER3_S_LSB _u(9) +#define DMA_SECCFG_MISC_TIMER3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER3_P +// Description : If 1, the TIMER3 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 3 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER3_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER3_P_BITS _u(0x00000100) +#define DMA_SECCFG_MISC_TIMER3_P_MSB _u(8) +#define DMA_SECCFG_MISC_TIMER3_P_LSB _u(8) +#define DMA_SECCFG_MISC_TIMER3_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER2_S +// Description : If 1, the TIMER2 register is only accessible from a Secure +// context, and timer DREQ 2 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER2_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER2_S_BITS _u(0x00000080) +#define DMA_SECCFG_MISC_TIMER2_S_MSB _u(7) +#define DMA_SECCFG_MISC_TIMER2_S_LSB _u(7) +#define DMA_SECCFG_MISC_TIMER2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER2_P +// Description : If 1, the TIMER2 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 2 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER2_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER2_P_BITS _u(0x00000040) +#define DMA_SECCFG_MISC_TIMER2_P_MSB _u(6) +#define DMA_SECCFG_MISC_TIMER2_P_LSB _u(6) +#define DMA_SECCFG_MISC_TIMER2_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER1_S +// Description : If 1, the TIMER1 register is only accessible from a Secure +// context, and timer DREQ 1 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER1_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER1_S_BITS _u(0x00000020) +#define DMA_SECCFG_MISC_TIMER1_S_MSB _u(5) +#define DMA_SECCFG_MISC_TIMER1_S_LSB _u(5) +#define DMA_SECCFG_MISC_TIMER1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER1_P +// Description : If 1, the TIMER1 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 1 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER1_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER1_P_BITS _u(0x00000010) +#define DMA_SECCFG_MISC_TIMER1_P_MSB _u(4) +#define DMA_SECCFG_MISC_TIMER1_P_LSB _u(4) +#define DMA_SECCFG_MISC_TIMER1_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER0_S +// Description : If 1, the TIMER0 register is only accessible from a Secure +// context, and timer DREQ 0 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER0_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER0_S_BITS _u(0x00000008) +#define DMA_SECCFG_MISC_TIMER0_S_MSB _u(3) +#define DMA_SECCFG_MISC_TIMER0_S_LSB _u(3) +#define DMA_SECCFG_MISC_TIMER0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER0_P +// Description : If 1, the TIMER0 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 0 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER0_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER0_P_BITS _u(0x00000004) +#define DMA_SECCFG_MISC_TIMER0_P_MSB _u(2) +#define DMA_SECCFG_MISC_TIMER0_P_LSB _u(2) +#define DMA_SECCFG_MISC_TIMER0_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_SNIFF_S +// Description : If 1, the sniffer can see data transfers from Secure channels, +// and can itself only be accessed from a Secure context. +// +// If 0, the sniffer can be accessed from either a Secure or Non- +// secure context, but can not see data transfers of Secure +// channels. +#define DMA_SECCFG_MISC_SNIFF_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_SNIFF_S_BITS _u(0x00000002) +#define DMA_SECCFG_MISC_SNIFF_S_MSB _u(1) +#define DMA_SECCFG_MISC_SNIFF_S_LSB _u(1) +#define DMA_SECCFG_MISC_SNIFF_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_SNIFF_P +// Description : If 1, the sniffer can see data transfers from Privileged +// channels, and can itself only be accessed from a privileged +// context, or from a Secure context when SNIFF_S is 0. +// +// If 0, the sniffer can be accessed from either a Privileged or +// Unprivileged context (with sufficient security level) but can +// not see transfers from Privileged channels. +#define DMA_SECCFG_MISC_SNIFF_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_SNIFF_P_BITS _u(0x00000001) +#define DMA_SECCFG_MISC_SNIFF_P_MSB _u(0) +#define DMA_SECCFG_MISC_SNIFF_P_LSB _u(0) +#define DMA_SECCFG_MISC_SNIFF_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_CTRL +// Description : Control register for DMA MPU. Accessible only from a Privileged +// context. +#define DMA_MPU_CTRL_OFFSET _u(0x00000500) +#define DMA_MPU_CTRL_BITS _u(0x0000000e) +#define DMA_MPU_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_CTRL_NS_HIDE_ADDR +// Description : By default, when a region's S bit is clear, Non-secure- +// Privileged reads can see the region's base address and limit +// address. Set this bit to make the addresses appear as 0 to Non- +// secure reads, even when the region is Non-secure, to avoid +// leaking information about the processor SAU map. +#define DMA_MPU_CTRL_NS_HIDE_ADDR_RESET _u(0x0) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_BITS _u(0x00000008) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_MSB _u(3) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_LSB _u(3) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_CTRL_S +// Description : Determine whether an address not covered by an active MPU +// region is Secure (1) or Non-secure (0) +#define DMA_MPU_CTRL_S_RESET _u(0x0) +#define DMA_MPU_CTRL_S_BITS _u(0x00000004) +#define DMA_MPU_CTRL_S_MSB _u(2) +#define DMA_MPU_CTRL_S_LSB _u(2) +#define DMA_MPU_CTRL_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_CTRL_P +// Description : Determine whether an address not covered by an active MPU +// region is Privileged (1) or Unprivileged (0) +#define DMA_MPU_CTRL_P_RESET _u(0x0) +#define DMA_MPU_CTRL_P_BITS _u(0x00000002) +#define DMA_MPU_CTRL_P_MSB _u(1) +#define DMA_MPU_CTRL_P_LSB _u(1) +#define DMA_MPU_CTRL_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR0 +// Description : Base address register for MPU region 0. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR0_OFFSET _u(0x00000504) +#define DMA_MPU_BAR0_BITS _u(0xffffffe0) +#define DMA_MPU_BAR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR0_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR0_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR0_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR0_ADDR_MSB _u(31) +#define DMA_MPU_BAR0_ADDR_LSB _u(5) +#define DMA_MPU_BAR0_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR0 +// Description : Limit address register for MPU region 0. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR0_OFFSET _u(0x00000508) +#define DMA_MPU_LAR0_BITS _u(0xffffffe7) +#define DMA_MPU_LAR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR0_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR0_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR0_ADDR_MSB _u(31) +#define DMA_MPU_LAR0_ADDR_LSB _u(5) +#define DMA_MPU_LAR0_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR0_S_RESET _u(0x0) +#define DMA_MPU_LAR0_S_BITS _u(0x00000004) +#define DMA_MPU_LAR0_S_MSB _u(2) +#define DMA_MPU_LAR0_S_LSB _u(2) +#define DMA_MPU_LAR0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR0_P_RESET _u(0x0) +#define DMA_MPU_LAR0_P_BITS _u(0x00000002) +#define DMA_MPU_LAR0_P_MSB _u(1) +#define DMA_MPU_LAR0_P_LSB _u(1) +#define DMA_MPU_LAR0_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR0_EN_RESET _u(0x0) +#define DMA_MPU_LAR0_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR0_EN_MSB _u(0) +#define DMA_MPU_LAR0_EN_LSB _u(0) +#define DMA_MPU_LAR0_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR1 +// Description : Base address register for MPU region 1. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR1_OFFSET _u(0x0000050c) +#define DMA_MPU_BAR1_BITS _u(0xffffffe0) +#define DMA_MPU_BAR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR1_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR1_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR1_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR1_ADDR_MSB _u(31) +#define DMA_MPU_BAR1_ADDR_LSB _u(5) +#define DMA_MPU_BAR1_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR1 +// Description : Limit address register for MPU region 1. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR1_OFFSET _u(0x00000510) +#define DMA_MPU_LAR1_BITS _u(0xffffffe7) +#define DMA_MPU_LAR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR1_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR1_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR1_ADDR_MSB _u(31) +#define DMA_MPU_LAR1_ADDR_LSB _u(5) +#define DMA_MPU_LAR1_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR1_S_RESET _u(0x0) +#define DMA_MPU_LAR1_S_BITS _u(0x00000004) +#define DMA_MPU_LAR1_S_MSB _u(2) +#define DMA_MPU_LAR1_S_LSB _u(2) +#define DMA_MPU_LAR1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR1_P_RESET _u(0x0) +#define DMA_MPU_LAR1_P_BITS _u(0x00000002) +#define DMA_MPU_LAR1_P_MSB _u(1) +#define DMA_MPU_LAR1_P_LSB _u(1) +#define DMA_MPU_LAR1_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR1_EN_RESET _u(0x0) +#define DMA_MPU_LAR1_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR1_EN_MSB _u(0) +#define DMA_MPU_LAR1_EN_LSB _u(0) +#define DMA_MPU_LAR1_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR2 +// Description : Base address register for MPU region 2. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR2_OFFSET _u(0x00000514) +#define DMA_MPU_BAR2_BITS _u(0xffffffe0) +#define DMA_MPU_BAR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR2_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR2_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR2_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR2_ADDR_MSB _u(31) +#define DMA_MPU_BAR2_ADDR_LSB _u(5) +#define DMA_MPU_BAR2_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR2 +// Description : Limit address register for MPU region 2. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR2_OFFSET _u(0x00000518) +#define DMA_MPU_LAR2_BITS _u(0xffffffe7) +#define DMA_MPU_LAR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR2_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR2_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR2_ADDR_MSB _u(31) +#define DMA_MPU_LAR2_ADDR_LSB _u(5) +#define DMA_MPU_LAR2_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR2_S_RESET _u(0x0) +#define DMA_MPU_LAR2_S_BITS _u(0x00000004) +#define DMA_MPU_LAR2_S_MSB _u(2) +#define DMA_MPU_LAR2_S_LSB _u(2) +#define DMA_MPU_LAR2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR2_P_RESET _u(0x0) +#define DMA_MPU_LAR2_P_BITS _u(0x00000002) +#define DMA_MPU_LAR2_P_MSB _u(1) +#define DMA_MPU_LAR2_P_LSB _u(1) +#define DMA_MPU_LAR2_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR2_EN_RESET _u(0x0) +#define DMA_MPU_LAR2_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR2_EN_MSB _u(0) +#define DMA_MPU_LAR2_EN_LSB _u(0) +#define DMA_MPU_LAR2_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR3 +// Description : Base address register for MPU region 3. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR3_OFFSET _u(0x0000051c) +#define DMA_MPU_BAR3_BITS _u(0xffffffe0) +#define DMA_MPU_BAR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR3_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR3_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR3_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR3_ADDR_MSB _u(31) +#define DMA_MPU_BAR3_ADDR_LSB _u(5) +#define DMA_MPU_BAR3_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR3 +// Description : Limit address register for MPU region 3. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR3_OFFSET _u(0x00000520) +#define DMA_MPU_LAR3_BITS _u(0xffffffe7) +#define DMA_MPU_LAR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR3_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR3_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR3_ADDR_MSB _u(31) +#define DMA_MPU_LAR3_ADDR_LSB _u(5) +#define DMA_MPU_LAR3_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR3_S_RESET _u(0x0) +#define DMA_MPU_LAR3_S_BITS _u(0x00000004) +#define DMA_MPU_LAR3_S_MSB _u(2) +#define DMA_MPU_LAR3_S_LSB _u(2) +#define DMA_MPU_LAR3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR3_P_RESET _u(0x0) +#define DMA_MPU_LAR3_P_BITS _u(0x00000002) +#define DMA_MPU_LAR3_P_MSB _u(1) +#define DMA_MPU_LAR3_P_LSB _u(1) +#define DMA_MPU_LAR3_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR3_EN_RESET _u(0x0) +#define DMA_MPU_LAR3_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR3_EN_MSB _u(0) +#define DMA_MPU_LAR3_EN_LSB _u(0) +#define DMA_MPU_LAR3_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR4 +// Description : Base address register for MPU region 4. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR4_OFFSET _u(0x00000524) +#define DMA_MPU_BAR4_BITS _u(0xffffffe0) +#define DMA_MPU_BAR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR4_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR4_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR4_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR4_ADDR_MSB _u(31) +#define DMA_MPU_BAR4_ADDR_LSB _u(5) +#define DMA_MPU_BAR4_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR4 +// Description : Limit address register for MPU region 4. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR4_OFFSET _u(0x00000528) +#define DMA_MPU_LAR4_BITS _u(0xffffffe7) +#define DMA_MPU_LAR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR4_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR4_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR4_ADDR_MSB _u(31) +#define DMA_MPU_LAR4_ADDR_LSB _u(5) +#define DMA_MPU_LAR4_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR4_S_RESET _u(0x0) +#define DMA_MPU_LAR4_S_BITS _u(0x00000004) +#define DMA_MPU_LAR4_S_MSB _u(2) +#define DMA_MPU_LAR4_S_LSB _u(2) +#define DMA_MPU_LAR4_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR4_P_RESET _u(0x0) +#define DMA_MPU_LAR4_P_BITS _u(0x00000002) +#define DMA_MPU_LAR4_P_MSB _u(1) +#define DMA_MPU_LAR4_P_LSB _u(1) +#define DMA_MPU_LAR4_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR4_EN_RESET _u(0x0) +#define DMA_MPU_LAR4_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR4_EN_MSB _u(0) +#define DMA_MPU_LAR4_EN_LSB _u(0) +#define DMA_MPU_LAR4_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR5 +// Description : Base address register for MPU region 5. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR5_OFFSET _u(0x0000052c) +#define DMA_MPU_BAR5_BITS _u(0xffffffe0) +#define DMA_MPU_BAR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR5_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR5_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR5_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR5_ADDR_MSB _u(31) +#define DMA_MPU_BAR5_ADDR_LSB _u(5) +#define DMA_MPU_BAR5_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR5 +// Description : Limit address register for MPU region 5. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR5_OFFSET _u(0x00000530) +#define DMA_MPU_LAR5_BITS _u(0xffffffe7) +#define DMA_MPU_LAR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR5_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR5_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR5_ADDR_MSB _u(31) +#define DMA_MPU_LAR5_ADDR_LSB _u(5) +#define DMA_MPU_LAR5_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR5_S_RESET _u(0x0) +#define DMA_MPU_LAR5_S_BITS _u(0x00000004) +#define DMA_MPU_LAR5_S_MSB _u(2) +#define DMA_MPU_LAR5_S_LSB _u(2) +#define DMA_MPU_LAR5_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR5_P_RESET _u(0x0) +#define DMA_MPU_LAR5_P_BITS _u(0x00000002) +#define DMA_MPU_LAR5_P_MSB _u(1) +#define DMA_MPU_LAR5_P_LSB _u(1) +#define DMA_MPU_LAR5_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR5_EN_RESET _u(0x0) +#define DMA_MPU_LAR5_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR5_EN_MSB _u(0) +#define DMA_MPU_LAR5_EN_LSB _u(0) +#define DMA_MPU_LAR5_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR6 +// Description : Base address register for MPU region 6. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR6_OFFSET _u(0x00000534) +#define DMA_MPU_BAR6_BITS _u(0xffffffe0) +#define DMA_MPU_BAR6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR6_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR6_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR6_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR6_ADDR_MSB _u(31) +#define DMA_MPU_BAR6_ADDR_LSB _u(5) +#define DMA_MPU_BAR6_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR6 +// Description : Limit address register for MPU region 6. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR6_OFFSET _u(0x00000538) +#define DMA_MPU_LAR6_BITS _u(0xffffffe7) +#define DMA_MPU_LAR6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR6_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR6_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR6_ADDR_MSB _u(31) +#define DMA_MPU_LAR6_ADDR_LSB _u(5) +#define DMA_MPU_LAR6_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR6_S_RESET _u(0x0) +#define DMA_MPU_LAR6_S_BITS _u(0x00000004) +#define DMA_MPU_LAR6_S_MSB _u(2) +#define DMA_MPU_LAR6_S_LSB _u(2) +#define DMA_MPU_LAR6_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR6_P_RESET _u(0x0) +#define DMA_MPU_LAR6_P_BITS _u(0x00000002) +#define DMA_MPU_LAR6_P_MSB _u(1) +#define DMA_MPU_LAR6_P_LSB _u(1) +#define DMA_MPU_LAR6_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR6_EN_RESET _u(0x0) +#define DMA_MPU_LAR6_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR6_EN_MSB _u(0) +#define DMA_MPU_LAR6_EN_LSB _u(0) +#define DMA_MPU_LAR6_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR7 +// Description : Base address register for MPU region 7. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR7_OFFSET _u(0x0000053c) +#define DMA_MPU_BAR7_BITS _u(0xffffffe0) +#define DMA_MPU_BAR7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR7_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR7_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR7_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR7_ADDR_MSB _u(31) +#define DMA_MPU_BAR7_ADDR_LSB _u(5) +#define DMA_MPU_BAR7_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR7 +// Description : Limit address register for MPU region 7. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR7_OFFSET _u(0x00000540) +#define DMA_MPU_LAR7_BITS _u(0xffffffe7) +#define DMA_MPU_LAR7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR7_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR7_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR7_ADDR_MSB _u(31) +#define DMA_MPU_LAR7_ADDR_LSB _u(5) +#define DMA_MPU_LAR7_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR7_S_RESET _u(0x0) +#define DMA_MPU_LAR7_S_BITS _u(0x00000004) +#define DMA_MPU_LAR7_S_MSB _u(2) +#define DMA_MPU_LAR7_S_LSB _u(2) +#define DMA_MPU_LAR7_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR7_P_RESET _u(0x0) +#define DMA_MPU_LAR7_P_BITS _u(0x00000002) +#define DMA_MPU_LAR7_P_MSB _u(1) +#define DMA_MPU_LAR7_P_LSB _u(1) +#define DMA_MPU_LAR7_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR7_EN_RESET _u(0x0) +#define DMA_MPU_LAR7_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR7_EN_MSB _u(0) +#define DMA_MPU_LAR7_EN_LSB _u(0) +#define DMA_MPU_LAR7_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800) +#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH0_DBG_CTDREQ_MSB _u(5) +#define DMA_CH0_DBG_CTDREQ_LSB _u(0) +#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH0_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804) +#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH0_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH0_DBG_TCR_MSB _u(31) +#define DMA_CH0_DBG_TCR_LSB _u(0) +#define DMA_CH0_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840) +#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH1_DBG_CTDREQ_MSB _u(5) +#define DMA_CH1_DBG_CTDREQ_LSB _u(0) +#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH1_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844) +#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH1_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH1_DBG_TCR_MSB _u(31) +#define DMA_CH1_DBG_TCR_LSB _u(0) +#define DMA_CH1_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880) +#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH2_DBG_CTDREQ_MSB _u(5) +#define DMA_CH2_DBG_CTDREQ_LSB _u(0) +#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH2_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884) +#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH2_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH2_DBG_TCR_MSB _u(31) +#define DMA_CH2_DBG_TCR_LSB _u(0) +#define DMA_CH2_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0) +#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH3_DBG_CTDREQ_MSB _u(5) +#define DMA_CH3_DBG_CTDREQ_LSB _u(0) +#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH3_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4) +#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH3_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH3_DBG_TCR_MSB _u(31) +#define DMA_CH3_DBG_TCR_LSB _u(0) +#define DMA_CH3_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900) +#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH4_DBG_CTDREQ_MSB _u(5) +#define DMA_CH4_DBG_CTDREQ_LSB _u(0) +#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH4_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904) +#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH4_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH4_DBG_TCR_MSB _u(31) +#define DMA_CH4_DBG_TCR_LSB _u(0) +#define DMA_CH4_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940) +#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH5_DBG_CTDREQ_MSB _u(5) +#define DMA_CH5_DBG_CTDREQ_LSB _u(0) +#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH5_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944) +#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH5_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH5_DBG_TCR_MSB _u(31) +#define DMA_CH5_DBG_TCR_LSB _u(0) +#define DMA_CH5_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980) +#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH6_DBG_CTDREQ_MSB _u(5) +#define DMA_CH6_DBG_CTDREQ_LSB _u(0) +#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH6_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984) +#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH6_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH6_DBG_TCR_MSB _u(31) +#define DMA_CH6_DBG_TCR_LSB _u(0) +#define DMA_CH6_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0) +#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH7_DBG_CTDREQ_MSB _u(5) +#define DMA_CH7_DBG_CTDREQ_LSB _u(0) +#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH7_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4) +#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH7_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH7_DBG_TCR_MSB _u(31) +#define DMA_CH7_DBG_TCR_LSB _u(0) +#define DMA_CH7_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00) +#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH8_DBG_CTDREQ_MSB _u(5) +#define DMA_CH8_DBG_CTDREQ_LSB _u(0) +#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH8_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04) +#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH8_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH8_DBG_TCR_MSB _u(31) +#define DMA_CH8_DBG_TCR_LSB _u(0) +#define DMA_CH8_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40) +#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH9_DBG_CTDREQ_MSB _u(5) +#define DMA_CH9_DBG_CTDREQ_LSB _u(0) +#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH9_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44) +#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH9_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH9_DBG_TCR_MSB _u(31) +#define DMA_CH9_DBG_TCR_LSB _u(0) +#define DMA_CH9_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80) +#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH10_DBG_CTDREQ_MSB _u(5) +#define DMA_CH10_DBG_CTDREQ_LSB _u(0) +#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH10_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84) +#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH10_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH10_DBG_TCR_MSB _u(31) +#define DMA_CH10_DBG_TCR_LSB _u(0) +#define DMA_CH10_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0) +#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH11_DBG_CTDREQ_MSB _u(5) +#define DMA_CH11_DBG_CTDREQ_LSB _u(0) +#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH11_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4) +#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH11_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH11_DBG_TCR_MSB _u(31) +#define DMA_CH11_DBG_TCR_LSB _u(0) +#define DMA_CH11_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH12_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH12_DBG_CTDREQ_OFFSET _u(0x00000b00) +#define DMA_CH12_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH12_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH12_DBG_CTDREQ_MSB _u(5) +#define DMA_CH12_DBG_CTDREQ_LSB _u(0) +#define DMA_CH12_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH12_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH12_DBG_TCR_OFFSET _u(0x00000b04) +#define DMA_CH12_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH12_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH12_DBG_TCR_MSB _u(31) +#define DMA_CH12_DBG_TCR_LSB _u(0) +#define DMA_CH12_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH13_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH13_DBG_CTDREQ_OFFSET _u(0x00000b40) +#define DMA_CH13_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH13_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH13_DBG_CTDREQ_MSB _u(5) +#define DMA_CH13_DBG_CTDREQ_LSB _u(0) +#define DMA_CH13_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH13_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH13_DBG_TCR_OFFSET _u(0x00000b44) +#define DMA_CH13_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH13_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH13_DBG_TCR_MSB _u(31) +#define DMA_CH13_DBG_TCR_LSB _u(0) +#define DMA_CH13_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH14_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH14_DBG_CTDREQ_OFFSET _u(0x00000b80) +#define DMA_CH14_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH14_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH14_DBG_CTDREQ_MSB _u(5) +#define DMA_CH14_DBG_CTDREQ_LSB _u(0) +#define DMA_CH14_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH14_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH14_DBG_TCR_OFFSET _u(0x00000b84) +#define DMA_CH14_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH14_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH14_DBG_TCR_MSB _u(31) +#define DMA_CH14_DBG_TCR_LSB _u(0) +#define DMA_CH14_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH15_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH15_DBG_CTDREQ_OFFSET _u(0x00000bc0) +#define DMA_CH15_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH15_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH15_DBG_CTDREQ_MSB _u(5) +#define DMA_CH15_DBG_CTDREQ_LSB _u(0) +#define DMA_CH15_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH15_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH15_DBG_TCR_OFFSET _u(0x00000bc4) +#define DMA_CH15_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH15_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH15_DBG_TCR_MSB _u(31) +#define DMA_CH15_DBG_TCR_LSB _u(0) +#define DMA_CH15_DBG_TCR_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_DMA_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/dreq.h b/src/rp2350/hardware_regs/include/hardware/regs/dreq.h new file mode 100644 index 000000000..6d126c0df --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/dreq.h @@ -0,0 +1,147 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _DREQ_H +#define _DREQ_H + +/** + * \file rp2350/dreq.h + */ + +#ifdef __ASSEMBLER__ +#define DREQ_PIO0_TX0 0 +#define DREQ_PIO0_TX1 1 +#define DREQ_PIO0_TX2 2 +#define DREQ_PIO0_TX3 3 +#define DREQ_PIO0_RX0 4 +#define DREQ_PIO0_RX1 5 +#define DREQ_PIO0_RX2 6 +#define DREQ_PIO0_RX3 7 +#define DREQ_PIO1_TX0 8 +#define DREQ_PIO1_TX1 9 +#define DREQ_PIO1_TX2 10 +#define DREQ_PIO1_TX3 11 +#define DREQ_PIO1_RX0 12 +#define DREQ_PIO1_RX1 13 +#define DREQ_PIO1_RX2 14 +#define DREQ_PIO1_RX3 15 +#define DREQ_PIO2_TX0 16 +#define DREQ_PIO2_TX1 17 +#define DREQ_PIO2_TX2 18 +#define DREQ_PIO2_TX3 19 +#define DREQ_PIO2_RX0 20 +#define DREQ_PIO2_RX1 21 +#define DREQ_PIO2_RX2 22 +#define DREQ_PIO2_RX3 23 +#define DREQ_SPI0_TX 24 +#define DREQ_SPI0_RX 25 +#define DREQ_SPI1_TX 26 +#define DREQ_SPI1_RX 27 +#define DREQ_UART0_TX 28 +#define DREQ_UART0_RX 29 +#define DREQ_UART1_TX 30 +#define DREQ_UART1_RX 31 +#define DREQ_PWM_WRAP0 32 +#define DREQ_PWM_WRAP1 33 +#define DREQ_PWM_WRAP2 34 +#define DREQ_PWM_WRAP3 35 +#define DREQ_PWM_WRAP4 36 +#define DREQ_PWM_WRAP5 37 +#define DREQ_PWM_WRAP6 38 +#define DREQ_PWM_WRAP7 39 +#define DREQ_PWM_WRAP8 40 +#define DREQ_PWM_WRAP9 41 +#define DREQ_PWM_WRAP10 42 +#define DREQ_PWM_WRAP11 43 +#define DREQ_I2C0_TX 44 +#define DREQ_I2C0_RX 45 +#define DREQ_I2C1_TX 46 +#define DREQ_I2C1_RX 47 +#define DREQ_ADC 48 +#define DREQ_XIP_STREAM 49 +#define DREQ_XIP_QMITX 50 +#define DREQ_XIP_QMIRX 51 +#define DREQ_HSTX 52 +#define DREQ_CORESIGHT 53 +#define DREQ_SHA256 54 +#define DREQ_DMA_TIMER0 59 +#define DREQ_DMA_TIMER1 60 +#define DREQ_DMA_TIMER2 61 +#define DREQ_DMA_TIMER3 62 +#define DREQ_FORCE 63 +#else +/** + * \brief DREQ numbers for DMA pacing on RP2350 (used as typedef \ref dreq_num_t) + * \ingroup hardware_dma + */ +typedef enum dreq_num_rp2350 { + DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ + DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ + DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ + DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ + DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ + DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ + DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ + DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ + DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ + DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ + DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ + DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ + DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ + DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ + DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ + DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ + DREQ_PIO2_TX0 = 16, ///< Select PIO2's TX FIFO 0 as DREQ + DREQ_PIO2_TX1 = 17, ///< Select PIO2's TX FIFO 1 as DREQ + DREQ_PIO2_TX2 = 18, ///< Select PIO2's TX FIFO 2 as DREQ + DREQ_PIO2_TX3 = 19, ///< Select PIO2's TX FIFO 3 as DREQ + DREQ_PIO2_RX0 = 20, ///< Select PIO2's RX FIFO 0 as DREQ + DREQ_PIO2_RX1 = 21, ///< Select PIO2's RX FIFO 1 as DREQ + DREQ_PIO2_RX2 = 22, ///< Select PIO2's RX FIFO 2 as DREQ + DREQ_PIO2_RX3 = 23, ///< Select PIO2's RX FIFO 3 as DREQ + DREQ_SPI0_TX = 24, ///< Select SPI0's TX FIFO as DREQ + DREQ_SPI0_RX = 25, ///< Select SPI0's RX FIFO as DREQ + DREQ_SPI1_TX = 26, ///< Select SPI1's TX FIFO as DREQ + DREQ_SPI1_RX = 27, ///< Select SPI1's RX FIFO as DREQ + DREQ_UART0_TX = 28, ///< Select UART0's TX FIFO as DREQ + DREQ_UART0_RX = 29, ///< Select UART0's RX FIFO as DREQ + DREQ_UART1_TX = 30, ///< Select UART1's TX FIFO as DREQ + DREQ_UART1_RX = 31, ///< Select UART1's RX FIFO as DREQ + DREQ_PWM_WRAP0 = 32, ///< Select PWM Counter 0's Wrap Value as DREQ + DREQ_PWM_WRAP1 = 33, ///< Select PWM Counter 1's Wrap Value as DREQ + DREQ_PWM_WRAP2 = 34, ///< Select PWM Counter 2's Wrap Value as DREQ + DREQ_PWM_WRAP3 = 35, ///< Select PWM Counter 3's Wrap Value as DREQ + DREQ_PWM_WRAP4 = 36, ///< Select PWM Counter 4's Wrap Value as DREQ + DREQ_PWM_WRAP5 = 37, ///< Select PWM Counter 5's Wrap Value as DREQ + DREQ_PWM_WRAP6 = 38, ///< Select PWM Counter 6's Wrap Value as DREQ + DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ + DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ + DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ + DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ + DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ + DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ + DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ + DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ + DREQ_I2C1_RX = 47, ///< Select I2C1's RX FIFO as DREQ + DREQ_ADC = 48, ///< Select the ADC as DREQ + DREQ_XIP_STREAM = 49, ///< Select the XIP Streaming FIFO as DREQ + DREQ_XIP_QMITX = 50, ///< Select XIP_QMITX as DREQ + DREQ_XIP_QMIRX = 51, ///< Select XIP_QMIRX as DREQ + DREQ_HSTX = 52, ///< Select HSTX as DREQ + DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ + DREQ_SHA256 = 54, ///< Select SHA256 as DREQ + DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ + DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ + DREQ_FORCE = 63, ///< Select FORCE as DREQ + DREQ_COUNT +} dreq_num_t; +#endif + +#endif // _DREQ_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h b/src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h new file mode 100644 index 000000000..efdf434b3 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/glitch_detector.h @@ -0,0 +1,213 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : GLITCH_DETECTOR +// Version : 1 +// Bus type : apb +// Description : Glitch detector controls +// ============================================================================= +#ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H +#define _HARDWARE_REGS_GLITCH_DETECTOR_H +// ============================================================================= +// Register : GLITCH_DETECTOR_ARM +// Description : Forcibly arm the glitch detectors, if they are not already +// armed by OTP. When armed, any individual detector trigger will +// cause a restart of the switched core power domain's power-on +// reset state machine. +// +// Glitch detector triggers are recorded accumulatively in +// TRIG_STATUS. If the system is reset by a glitch detector +// trigger, this is recorded in POWMAN_CHIP_RESET. +// +// This register is Secure read/write only. +// 0x5bad -> Do not force the glitch detectors to be armed +// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) +#define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000) +#define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff) +#define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad) +#define GLITCH_DETECTOR_ARM_MSB _u(15) +#define GLITCH_DETECTOR_ARM_LSB _u(0) +#define GLITCH_DETECTOR_ARM_ACCESS "RW" +#define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad) +#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000) +// ============================================================================= +// Register : GLITCH_DETECTOR_DISARM +// Description : None +// Forcibly disarm the glitch detectors, if they are armed by OTP. +// Ignored if ARM is YES. +// +// This register is Secure read/write only. +// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) +// 0xdcaf -> Disarm the glitch detectors +#define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004) +#define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff) +#define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000) +#define GLITCH_DETECTOR_DISARM_MSB _u(15) +#define GLITCH_DETECTOR_DISARM_LSB _u(0) +#define GLITCH_DETECTOR_DISARM_ACCESS "RW" +#define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000) +#define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf) +// ============================================================================= +// Register : GLITCH_DETECTOR_SENSITIVITY +// Description : Adjust the sensitivity of glitch detectors to values other than +// their OTP-provided defaults. +// +// This register is Secure read/write only. +#define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008) +#define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff) +#define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT +// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) +// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register. +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW" +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde) +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV +// Description : Must be the inverse of DET3, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV +// Description : Must be the inverse of DET2, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV +// Description : Must be the inverse of DET1, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV +// Description : Must be the inverse of DET0, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET3 +// Description : Set sensitivity for detector 3. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET2 +// Description : Set sensitivity for detector 2. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET1 +// Description : Set sensitivity for detector 1. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET0 +// Description : Set sensitivity for detector 0. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW" +// ============================================================================= +// Register : GLITCH_DETECTOR_LOCK +// Description : None +// Write any nonzero value to disable writes to ARM, DISARM, +// SENSITIVITY and LOCK. This register is Secure read/write only. +#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c) +#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff) +#define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000) +#define GLITCH_DETECTOR_LOCK_MSB _u(7) +#define GLITCH_DETECTOR_LOCK_LSB _u(0) +#define GLITCH_DETECTOR_LOCK_ACCESS "RW" +// ============================================================================= +// Register : GLITCH_DETECTOR_TRIG_STATUS +// Description : Set when a detector output triggers. Write-1-clear. +// +// (May immediately return high if the detector remains in a +// failed state. Detectors can only be cleared by a full reset of +// the switched core power domain.) +// +// This register is Secure read/write only. +#define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010) +#define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f) +#define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET3 +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET2 +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET1 +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET0 +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC" +// ============================================================================= +// Register : GLITCH_DETECTOR_TRIG_FORCE +// Description : Simulate the firing of one or more detectors. Writing ones to +// this register will set the matching bits in STATUS_TRIG. +// +// If the glitch detectors are currently armed, writing ones will +// also immediately reset the switched core power domain, and set +// the reset reason latches in POWMAN_CHIP_RESET to indicate a +// glitch detector resets. +// +// This register is Secure read/write only. +#define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014) +#define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f) +#define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000) +#define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3) +#define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0) +#define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC" +// ============================================================================= +#endif // _HARDWARE_REGS_GLITCH_DETECTOR_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h b/src/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h new file mode 100644 index 000000000..8f2130445 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/hstx_ctrl.h @@ -0,0 +1,609 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : HSTX_CTRL +// Version : 0 +// Bus type : apb +// Description : Control interface to HSTX. For FIFO write access and status, +// see the HSTX_FIFO register block. +// ============================================================================= +#ifndef _HARDWARE_REGS_HSTX_CTRL_H +#define _HARDWARE_REGS_HSTX_CTRL_H +// ============================================================================= +// Register : HSTX_CTRL_CSR +#define HSTX_CTRL_CSR_OFFSET _u(0x00000000) +#define HSTX_CTRL_CSR_BITS _u(0xff1f1f73) +#define HSTX_CTRL_CSR_RESET _u(0x10050600) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_CLKDIV +// Description : Clock period of the generated clock, measured in HSTX clock +// cycles. Can be odd or even. The generated clock advances only +// on cycles where the shift register shifts. +// +// For example, a clkdiv of 5 would generate a complete output +// clock period for every 5 HSTX clocks (or every 10 half-clocks). +// +// A CLKDIV value of 0 is mapped to a period of 16 HSTX clock +// cycles. +#define HSTX_CTRL_CSR_CLKDIV_RESET _u(0x1) +#define HSTX_CTRL_CSR_CLKDIV_BITS _u(0xf0000000) +#define HSTX_CTRL_CSR_CLKDIV_MSB _u(31) +#define HSTX_CTRL_CSR_CLKDIV_LSB _u(28) +#define HSTX_CTRL_CSR_CLKDIV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_CLKPHASE +// Description : Set the initial phase of the generated clock. +// +// A CLKPHASE of 0 means the clock is initially low, and the first +// rising edge occurs after one half period of the generated clock +// (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 +// will advance the initial clock phase by one half clk_hstx +// period. For example, if CLKDIV=2 and CLKPHASE=1: +// +// * The clock will be initially low +// +// * The first rising edge will be 0.5 clk_hstx cycles after +// asserting first data +// +// * The first falling edge will be 1.5 clk_hstx cycles after +// asserting first data +// +// This configuration would be suitable for serialising at a bit +// rate of clk_hstx with a centre-aligned DDR clock. +// +// When the HSTX is halted by clearing CSR_EN, the clock generator +// will return to its initial phase as configured by the CLKPHASE +// field. +// +// Note CLKPHASE must be strictly less than double the value of +// CLKDIV (one full period), else its operation is undefined. +#define HSTX_CTRL_CSR_CLKPHASE_RESET _u(0x0) +#define HSTX_CTRL_CSR_CLKPHASE_BITS _u(0x0f000000) +#define HSTX_CTRL_CSR_CLKPHASE_MSB _u(27) +#define HSTX_CTRL_CSR_CLKPHASE_LSB _u(24) +#define HSTX_CTRL_CSR_CLKPHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_N_SHIFTS +// Description : Number of times to shift the shift register before refilling it +// from the FIFO. (A count of how many times it has been shifted, +// *not* the total shift distance.) +// +// A register value of 0 means shift 32 times. +#define HSTX_CTRL_CSR_N_SHIFTS_RESET _u(0x05) +#define HSTX_CTRL_CSR_N_SHIFTS_BITS _u(0x001f0000) +#define HSTX_CTRL_CSR_N_SHIFTS_MSB _u(20) +#define HSTX_CTRL_CSR_N_SHIFTS_LSB _u(16) +#define HSTX_CTRL_CSR_N_SHIFTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_SHIFT +// Description : How many bits to right-rotate the shift register by each cycle. +// +// The use of a rotate rather than a shift allows left shifts to +// be emulated, by subtracting the left-shift amount from 32. It +// also allows data to be repeated, when the product of SHIFT and +// N_SHIFTS is greater than 32. +#define HSTX_CTRL_CSR_SHIFT_RESET _u(0x06) +#define HSTX_CTRL_CSR_SHIFT_BITS _u(0x00001f00) +#define HSTX_CTRL_CSR_SHIFT_MSB _u(12) +#define HSTX_CTRL_CSR_SHIFT_LSB _u(8) +#define HSTX_CTRL_CSR_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_COUPLED_SEL +// Description : Select which PIO to use for coupled mode operation. +#define HSTX_CTRL_CSR_COUPLED_SEL_RESET _u(0x0) +#define HSTX_CTRL_CSR_COUPLED_SEL_BITS _u(0x00000060) +#define HSTX_CTRL_CSR_COUPLED_SEL_MSB _u(6) +#define HSTX_CTRL_CSR_COUPLED_SEL_LSB _u(5) +#define HSTX_CTRL_CSR_COUPLED_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_COUPLED_MODE +// Description : Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked +// *directly* from the system clock (not just from some other +// clock source of the same frequency) for this synchronous +// interface to function correctly. +// +// When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 +// through 31 will select bits from the 8-bit PIO-to-HSTX path, +// rather than shifter bits. Indices of 0 through 23 will still +// index the shift register as normal. +// +// The PIO outputs connected to the PIO-to-HSTX bus are those same +// outputs that would appear on the HSTX-capable pins if those +// pins' FUNCSELs were set to PIO instead of HSTX. +// +// For example, if HSTX is on GPIOs 12 through 19, then PIO +// outputs 12 through 19 are connected to the HSTX when coupled +// mode is engaged. +#define HSTX_CTRL_CSR_COUPLED_MODE_RESET _u(0x0) +#define HSTX_CTRL_CSR_COUPLED_MODE_BITS _u(0x00000010) +#define HSTX_CTRL_CSR_COUPLED_MODE_MSB _u(4) +#define HSTX_CTRL_CSR_COUPLED_MODE_LSB _u(4) +#define HSTX_CTRL_CSR_COUPLED_MODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_EXPAND_EN +// Description : Enable the command expander. When 0, raw FIFO data is passed +// directly to the output shift register. When 1, the command +// expander can perform simple operations such as run length +// decoding on data between the FIFO and the shift register. +// +// Do not change CXPD_EN whilst EN is set. It's safe to set +// CXPD_EN simultaneously with setting EN. +#define HSTX_CTRL_CSR_EXPAND_EN_RESET _u(0x0) +#define HSTX_CTRL_CSR_EXPAND_EN_BITS _u(0x00000002) +#define HSTX_CTRL_CSR_EXPAND_EN_MSB _u(1) +#define HSTX_CTRL_CSR_EXPAND_EN_LSB _u(1) +#define HSTX_CTRL_CSR_EXPAND_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_EN +// Description : When EN is 1, the HSTX will shift out data as it appears in the +// FIFO. As long as there is data, the HSTX shift register will +// shift once per clock cycle, and the frequency of popping from +// the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. +// +// When EN is 0, the FIFO is not popped. The shift counter and +// clock generator are also reset to their initial state for as +// long as EN is low. Note the initial phase of the clock +// generator can be configured by the CLKPHASE field. +// +// Once the HSTX is enabled again, and data is pushed to the FIFO, +// the generated clock's first rising edge will be one half-period +// after the first data is launched. +#define HSTX_CTRL_CSR_EN_RESET _u(0x0) +#define HSTX_CTRL_CSR_EN_BITS _u(0x00000001) +#define HSTX_CTRL_CSR_EN_MSB _u(0) +#define HSTX_CTRL_CSR_EN_LSB _u(0) +#define HSTX_CTRL_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT0 +// Description : Data control register for output bit 0 +#define HSTX_CTRL_BIT0_OFFSET _u(0x00000004) +#define HSTX_CTRL_BIT0_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT0_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT0_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT0_CLK_MSB _u(17) +#define HSTX_CTRL_BIT0_CLK_LSB _u(17) +#define HSTX_CTRL_BIT0_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT0_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT0_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT0_INV_MSB _u(16) +#define HSTX_CTRL_BIT0_INV_LSB _u(16) +#define HSTX_CTRL_BIT0_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT0_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT0_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT0_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT0_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT0_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT0_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT0_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT0_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT0_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT0_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT1 +// Description : Data control register for output bit 1 +#define HSTX_CTRL_BIT1_OFFSET _u(0x00000008) +#define HSTX_CTRL_BIT1_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT1_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT1_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT1_CLK_MSB _u(17) +#define HSTX_CTRL_BIT1_CLK_LSB _u(17) +#define HSTX_CTRL_BIT1_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT1_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT1_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT1_INV_MSB _u(16) +#define HSTX_CTRL_BIT1_INV_LSB _u(16) +#define HSTX_CTRL_BIT1_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT1_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT1_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT1_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT1_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT1_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT1_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT1_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT1_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT1_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT1_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT2 +// Description : Data control register for output bit 2 +#define HSTX_CTRL_BIT2_OFFSET _u(0x0000000c) +#define HSTX_CTRL_BIT2_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT2_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT2_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT2_CLK_MSB _u(17) +#define HSTX_CTRL_BIT2_CLK_LSB _u(17) +#define HSTX_CTRL_BIT2_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT2_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT2_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT2_INV_MSB _u(16) +#define HSTX_CTRL_BIT2_INV_LSB _u(16) +#define HSTX_CTRL_BIT2_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT2_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT2_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT2_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT2_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT2_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT2_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT2_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT2_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT2_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT2_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT3 +// Description : Data control register for output bit 3 +#define HSTX_CTRL_BIT3_OFFSET _u(0x00000010) +#define HSTX_CTRL_BIT3_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT3_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT3_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT3_CLK_MSB _u(17) +#define HSTX_CTRL_BIT3_CLK_LSB _u(17) +#define HSTX_CTRL_BIT3_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT3_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT3_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT3_INV_MSB _u(16) +#define HSTX_CTRL_BIT3_INV_LSB _u(16) +#define HSTX_CTRL_BIT3_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT3_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT3_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT3_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT3_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT3_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT3_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT3_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT3_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT3_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT3_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT4 +// Description : Data control register for output bit 4 +#define HSTX_CTRL_BIT4_OFFSET _u(0x00000014) +#define HSTX_CTRL_BIT4_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT4_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT4_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT4_CLK_MSB _u(17) +#define HSTX_CTRL_BIT4_CLK_LSB _u(17) +#define HSTX_CTRL_BIT4_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT4_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT4_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT4_INV_MSB _u(16) +#define HSTX_CTRL_BIT4_INV_LSB _u(16) +#define HSTX_CTRL_BIT4_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT4_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT4_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT4_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT4_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT4_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT4_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT4_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT4_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT4_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT4_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT5 +// Description : Data control register for output bit 5 +#define HSTX_CTRL_BIT5_OFFSET _u(0x00000018) +#define HSTX_CTRL_BIT5_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT5_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT5_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT5_CLK_MSB _u(17) +#define HSTX_CTRL_BIT5_CLK_LSB _u(17) +#define HSTX_CTRL_BIT5_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT5_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT5_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT5_INV_MSB _u(16) +#define HSTX_CTRL_BIT5_INV_LSB _u(16) +#define HSTX_CTRL_BIT5_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT5_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT5_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT5_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT5_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT5_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT5_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT5_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT5_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT5_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT5_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT6 +// Description : Data control register for output bit 6 +#define HSTX_CTRL_BIT6_OFFSET _u(0x0000001c) +#define HSTX_CTRL_BIT6_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT6_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT6_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT6_CLK_MSB _u(17) +#define HSTX_CTRL_BIT6_CLK_LSB _u(17) +#define HSTX_CTRL_BIT6_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT6_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT6_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT6_INV_MSB _u(16) +#define HSTX_CTRL_BIT6_INV_LSB _u(16) +#define HSTX_CTRL_BIT6_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT6_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT6_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT6_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT6_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT6_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT6_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT6_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT6_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT6_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT6_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT7 +// Description : Data control register for output bit 7 +#define HSTX_CTRL_BIT7_OFFSET _u(0x00000020) +#define HSTX_CTRL_BIT7_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT7_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT7_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT7_CLK_MSB _u(17) +#define HSTX_CTRL_BIT7_CLK_LSB _u(17) +#define HSTX_CTRL_BIT7_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT7_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT7_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT7_INV_MSB _u(16) +#define HSTX_CTRL_BIT7_INV_LSB _u(16) +#define HSTX_CTRL_BIT7_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT7_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT7_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT7_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT7_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT7_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT7_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT7_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT7_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT7_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT7_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_EXPAND_SHIFT +// Description : Configure the optional shifter inside the command expander +#define HSTX_CTRL_EXPAND_SHIFT_OFFSET _u(0x00000024) +#define HSTX_CTRL_EXPAND_SHIFT_BITS _u(0x1f1f1f1f) +#define HSTX_CTRL_EXPAND_SHIFT_RESET _u(0x01000100) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS +// Description : Number of times to consume from the shift register before +// refilling it from the FIFO, when the current command is an +// encoded data command (e.g. TMDS). A register value of 0 means +// shift 32 times. +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_RESET _u(0x01) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_BITS _u(0x1f000000) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MSB _u(28) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB _u(24) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT +// Description : How many bits to right-rotate the shift register by each time +// data is pushed to the output shifter, when the current command +// is an encoded data command (e.g. TMDS). +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_BITS _u(0x001f0000) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MSB _u(20) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB _u(16) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS +// Description : Number of times to consume from the shift register before +// refilling it from the FIFO, when the current command is a raw +// data command. A register value of 0 means shift 32 times. +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_RESET _u(0x01) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_BITS _u(0x00001f00) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MSB _u(12) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB _u(8) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT +// Description : How many bits to right-rotate the shift register by each time +// data is pushed to the output shifter, when the current command +// is a raw data command. +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_BITS _u(0x0000001f) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MSB _u(4) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB _u(0) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_EXPAND_TMDS +// Description : Configure the optional TMDS encoder inside the command expander +#define HSTX_CTRL_EXPAND_TMDS_OFFSET _u(0x00000028) +#define HSTX_CTRL_EXPAND_TMDS_BITS _u(0x00ffffff) +#define HSTX_CTRL_EXPAND_TMDS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L2_NBITS +// Description : Number of valid data bits for the lane 2 TMDS encoder, starting +// from bit 7 of the rotated data. Field values of 0 -> 7 encode +// counts of 1 -> 8 bits. +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_RESET _u(0x0) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_BITS _u(0x00e00000) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MSB _u(23) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB _u(21) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L2_ROT +// Description : Right-rotate applied to the current shifter data before the +// lane 2 TMDS encoder. +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_BITS _u(0x001f0000) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_MSB _u(20) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB _u(16) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L1_NBITS +// Description : Number of valid data bits for the lane 1 TMDS encoder, starting +// from bit 7 of the rotated data. Field values of 0 -> 7 encode +// counts of 1 -> 8 bits. +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_RESET _u(0x0) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_BITS _u(0x0000e000) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MSB _u(15) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB _u(13) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L1_ROT +// Description : Right-rotate applied to the current shifter data before the +// lane 1 TMDS encoder. +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_BITS _u(0x00001f00) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_MSB _u(12) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB _u(8) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L0_NBITS +// Description : Number of valid data bits for the lane 0 TMDS encoder, starting +// from bit 7 of the rotated data. Field values of 0 -> 7 encode +// counts of 1 -> 8 bits. +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_RESET _u(0x0) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_BITS _u(0x000000e0) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MSB _u(7) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB _u(5) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L0_ROT +// Description : Right-rotate applied to the current shifter data before the +// lane 0 TMDS encoder. +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_BITS _u(0x0000001f) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_MSB _u(4) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB _u(0) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_HSTX_CTRL_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/hstx_fifo.h b/src/rp2350/hardware_regs/include/hardware/regs/hstx_fifo.h new file mode 100644 index 000000000..d056447c8 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/hstx_fifo.h @@ -0,0 +1,62 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : HSTX_FIFO +// Version : 1 +// Bus type : ahbl +// Description : FIFO status and write access for HSTX +// ============================================================================= +#ifndef _HARDWARE_REGS_HSTX_FIFO_H +#define _HARDWARE_REGS_HSTX_FIFO_H +// ============================================================================= +// Register : HSTX_FIFO_STAT +// Description : FIFO status +#define HSTX_FIFO_STAT_OFFSET _u(0x00000000) +#define HSTX_FIFO_STAT_BITS _u(0x000007ff) +#define HSTX_FIFO_STAT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_WOF +// Description : FIFO was written when full. Write 1 to clear. +#define HSTX_FIFO_STAT_WOF_RESET _u(0x0) +#define HSTX_FIFO_STAT_WOF_BITS _u(0x00000400) +#define HSTX_FIFO_STAT_WOF_MSB _u(10) +#define HSTX_FIFO_STAT_WOF_LSB _u(10) +#define HSTX_FIFO_STAT_WOF_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_EMPTY +#define HSTX_FIFO_STAT_EMPTY_RESET "-" +#define HSTX_FIFO_STAT_EMPTY_BITS _u(0x00000200) +#define HSTX_FIFO_STAT_EMPTY_MSB _u(9) +#define HSTX_FIFO_STAT_EMPTY_LSB _u(9) +#define HSTX_FIFO_STAT_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_FULL +#define HSTX_FIFO_STAT_FULL_RESET "-" +#define HSTX_FIFO_STAT_FULL_BITS _u(0x00000100) +#define HSTX_FIFO_STAT_FULL_MSB _u(8) +#define HSTX_FIFO_STAT_FULL_LSB _u(8) +#define HSTX_FIFO_STAT_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_LEVEL +#define HSTX_FIFO_STAT_LEVEL_RESET _u(0x00) +#define HSTX_FIFO_STAT_LEVEL_BITS _u(0x000000ff) +#define HSTX_FIFO_STAT_LEVEL_MSB _u(7) +#define HSTX_FIFO_STAT_LEVEL_LSB _u(0) +#define HSTX_FIFO_STAT_LEVEL_ACCESS "RO" +// ============================================================================= +// Register : HSTX_FIFO_FIFO +// Description : Write access to FIFO +#define HSTX_FIFO_FIFO_OFFSET _u(0x00000004) +#define HSTX_FIFO_FIFO_BITS _u(0xffffffff) +#define HSTX_FIFO_FIFO_RESET _u(0x00000000) +#define HSTX_FIFO_FIFO_MSB _u(31) +#define HSTX_FIFO_FIFO_LSB _u(0) +#define HSTX_FIFO_FIFO_ACCESS "WF" +// ============================================================================= +#endif // _HARDWARE_REGS_HSTX_FIFO_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/i2c.h b/src/rp2350/hardware_regs/include/hardware/regs/i2c.h new file mode 100644 index 000000000..f44ceb440 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/i2c.h @@ -0,0 +1,2700 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : I2C +// Version : 1 +// Bus type : apb +// Description : DW_apb_i2c address block +// +// List of configuration constants for the Synopsys I2C +// hardware (you may see references to these in I2C register +// header; these are *fixed* values, set at hardware design +// time): +// +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_TX_CMD_BLOCK ................... 0x1 +// IC_HAS_DMA ........................ 0x1 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x0006 +// IC_HS_SCL_LOW_COUNT ............... 0x0008 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0x7 +// IC_ADD_ENCODED_PARAMS ............. 0x0 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_BUS_CLEAR_FEATURE .............. 0x0 +// IC_CAP_LOADING .................... 100 +// IC_FS_SCL_LOW_COUNT ............... 0x000d +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_CLK_TYPE ....................... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x0 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x0 +// IC_RX_BUFFER_DEPTH ................ 16 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 0 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0028 +// IC_SS_SCL_LOW_COUNT ............... 0x002f +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_STAT_FOR_CLK_STRETCH ........... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_TX_BUFFER_DEPTH ................ 16 +// ============================================================================= +#ifndef _HARDWARE_REGS_I2C_H +#define _HARDWARE_REGS_I2C_H +// ============================================================================= +// Register : I2C_IC_CON +// Description : I2C Control Register. This register can be written only when +// the DW_apb_i2c is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// Read/Write Access: - bit 10 is read only. - bit 11 is read only +// - bit 16 is read only - bit 17 is read only - bits 18 and 19 +// are read only. +#define I2C_IC_CON_OFFSET _u(0x00000000) +#define I2C_IC_CON_BITS _u(0x000007ff) +#define I2C_IC_CON_RESET _u(0x00000065) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE +// Description : Master issues the STOP_DET interrupt irrespective of whether +// master is active or not +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL +// Description : This bit controls whether DW_apb_i2c should hold the bus when +// the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as +// described in the IC_RX_FULL_HLD_BUS_EN parameter. +// +// Reset value: 0x0. +// 0x0 -> Overflow when RX_FIFO is full +// 0x1 -> Hold bus when RX_FIFO is full +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_TX_EMPTY_CTRL +// Description : This bit controls the generation of the TX_EMPTY interrupt, as +// described in the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0. +// 0x0 -> Default behaviour of TX_EMPTY interrupt +// 0x1 -> Controlled generation of TX_EMPTY interrupt +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IFADDRESSED +// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when +// it is addressed. - 1'b0: issues the STOP_DET irrespective of +// whether it's addressed or not. Reset value: 0x0 +// +// NOTE: During a general call address, this slave does not issue +// the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if +// the slave responds to the general call address by generating +// ACK. The STOP_DET interrupt is generated only when the +// transmitted address matches the slave address (SAR). +// 0x0 -> slave issues STOP_DET intr always +// 0x1 -> slave issues STOP_DET intr only if addressed +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_SLAVE_DISABLE +// Description : This bit controls whether I2C has its slave disabled, which +// means once the presetn signal is applied, then this bit is set +// and the slave is disabled. +// +// If this bit is set (slave is disabled), DW_apb_i2c functions +// only as a master and does not perform any action that requires +// a slave. +// +// NOTE: Software should ensure that if this bit is written with +// 0, then bit 0 should also be written with a 0. +// 0x0 -> Slave mode is enabled +// 0x1 -> Slave mode is disabled +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_RESTART_EN +// Description : Determines whether RESTART conditions may be sent when acting +// as a master. Some older slaves do not support handling RESTART +// conditions; however, RESTART conditions are used in several +// DW_apb_i2c operations. When RESTART is disabled, the master is +// prohibited from performing the following functions: - Sending a +// START BYTE - Performing any high-speed mode operation - High- +// speed mode operation - Performing direction changes in combined +// format mode - Performing a read operation with a 10-bit address +// By replacing RESTART condition followed by a STOP and a +// subsequent START condition, split operations are broken down +// into multiple DW_apb_i2c transfers. If the above operations are +// performed, it will result in setting bit 6 (TX_ABRT) of the +// IC_RAW_INTR_STAT register. +// +// Reset value: ENABLED +// 0x0 -> Master restart disabled +// 0x1 -> Master restart enabled +#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) +#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" +#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_MASTER +// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or +// 10-bit addressing mode when acting as a master. - 0: 7-bit +// addressing - 1: 10-bit addressing +// 0x0 -> Master 7Bit addressing mode +// 0x1 -> Master 10Bit addressing mode +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_SLAVE +// Description : When acting as a slave, this bit controls whether the +// DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit +// addressing. The DW_apb_i2c ignores transactions that involve +// 10-bit addressing; for 7-bit addressing, only the lower 7 bits +// of the IC_SAR register are compared. - 1: 10-bit addressing. +// The DW_apb_i2c responds to only 10-bit addressing transfers +// that match the full 10 bits of the IC_SAR register. +// 0x0 -> Slave 7Bit addressing +// 0x1 -> Slave 10Bit addressing +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_SPEED +// Description : These bits control at which speed the DW_apb_i2c operates; its +// setting is relevant only if one is operating the DW_apb_i2c in +// master mode. Hardware protects against illegal values being +// programmed by software. These bits must be programmed +// appropriately for slave mode also, as it is used to capture +// correct value of spike filter as per the speed mode. +// +// This register should be programmed only with a value in the +// range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates +// this register with the value of IC_MAX_SPEED_MODE. +// +// 1: standard mode (100 kbit/s) +// +// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) +// +// 3: high speed mode (3.4 Mbit/s) +// +// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 +// 0x1 -> Standard Speed mode of operation +// 0x2 -> Fast or Fast Plus mode of operation +// 0x3 -> High Speed mode of operation +#define I2C_IC_CON_SPEED_RESET _u(0x2) +#define I2C_IC_CON_SPEED_BITS _u(0x00000006) +#define I2C_IC_CON_SPEED_MSB _u(2) +#define I2C_IC_CON_SPEED_LSB _u(1) +#define I2C_IC_CON_SPEED_ACCESS "RW" +#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) +#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) +#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_MASTER_MODE +// Description : This bit controls whether the DW_apb_i2c master is enabled. +// +// NOTE: Software should ensure that if this bit is written with +// '1' then bit 6 should also be written with a '1'. +// 0x0 -> Master mode is disabled +// 0x1 -> Master mode is enabled +#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) +#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) +#define I2C_IC_CON_MASTER_MODE_MSB _u(0) +#define I2C_IC_CON_MASTER_MODE_LSB _u(0) +#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" +#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_TAR +// Description : I2C Target Address Register +// +// This register is 12 bits wide, and bits 31:12 are reserved. +// This register can be written to only when IC_ENABLE[0] is set +// to 0. +// +// Note: If the software or application is aware that the +// DW_apb_i2c is not using the TAR address for the pending +// commands in the Tx FIFO, then it is possible to update the TAR +// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - +// It is not necessary to perform any write to this register if +// DW_apb_i2c is enabled as an I2C slave only. +#define I2C_IC_TAR_OFFSET _u(0x00000004) +#define I2C_IC_TAR_BITS _u(0x00000fff) +#define I2C_IC_TAR_RESET _u(0x00000055) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_SPECIAL +// Description : This bit indicates whether software performs a Device-ID or +// General Call or START BYTE command. - 0: ignore bit 10 +// GC_OR_START and use IC_TAR normally - 1: perform special I2C +// command as specified in Device_ID or GC_OR_START bit Reset +// value: 0x0 +// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE transmission +// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE transmission +#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) +#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) +#define I2C_IC_TAR_SPECIAL_MSB _u(11) +#define I2C_IC_TAR_SPECIAL_LSB _u(11) +#define I2C_IC_TAR_SPECIAL_ACCESS "RW" +#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_GC_OR_START +// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to +// 0, then this bit indicates whether a General Call or START byte +// command is to be performed by the DW_apb_i2c. - 0: General Call +// Address - after issuing a General Call, only writes may be +// performed. Attempting to issue a read command results in +// setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The +// DW_apb_i2c remains in General Call mode until the SPECIAL bit +// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 +// 0x0 -> GENERAL_CALL byte transmission +// 0x1 -> START byte transmission +#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) +#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) +#define I2C_IC_TAR_GC_OR_START_MSB _u(10) +#define I2C_IC_TAR_GC_OR_START_LSB _u(10) +#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" +#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_IC_TAR +// Description : This is the target address for any master transaction. When +// transmitting a General Call, these bits are ignored. To +// generate a START BYTE, the CPU needs to write only once into +// these bits. +// +// If the IC_TAR and IC_SAR are the same, loopback exists but the +// FIFOs are shared between master and slave, so full loopback is +// not feasible. Only one direction loopback mode is supported +// (simplex), not duplex. A master cannot transmit to itself; it +// can transmit to only a slave. +#define I2C_IC_TAR_IC_TAR_RESET _u(0x055) +#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff) +#define I2C_IC_TAR_IC_TAR_MSB _u(9) +#define I2C_IC_TAR_IC_TAR_LSB _u(0) +#define I2C_IC_TAR_IC_TAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SAR +// Description : I2C Slave Address Register +#define I2C_IC_SAR_OFFSET _u(0x00000008) +#define I2C_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_RESET _u(0x00000055) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SAR_IC_SAR +// Description : The IC_SAR holds the slave address when the I2C is operating as +// a slave. For 7-bit addressing, only IC_SAR[6:0] is used. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// Note: The default values cannot be any of the reserved address +// locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct +// operation of the device is not guaranteed if you program the +// IC_SAR or IC_TAR to a reserved value. Refer to +// <> for a complete list of these +// reserved values. +#define I2C_IC_SAR_IC_SAR_RESET _u(0x055) +#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_IC_SAR_MSB _u(9) +#define I2C_IC_SAR_IC_SAR_LSB _u(0) +#define I2C_IC_SAR_IC_SAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DATA_CMD +// Description : I2C Rx/Tx Data Buffer and Command Register; this is the +// register the CPU writes to when filling the TX FIFO and the CPU +// reads from when retrieving bytes from RX FIFO. +// +// The size of the register changes as follows: +// +// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits +// when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when +// IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when +// IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c +// to continue acknowledging reads, a read command should be +// written for every byte that is to be received; otherwise the +// DW_apb_i2c will stop acknowledging. +#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010) +#define I2C_IC_DATA_CMD_BITS _u(0x00000fff) +#define I2C_IC_DATA_CMD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE +// Description : Indicates the first data byte received after the address phase +// for receive transfer in Master receiver or Slave receiver mode. +// +// Reset value : 0x0 +// +// NOTE: In case of APB_DATA_WIDTH=8, +// +// 1. The user has to perform two APB Reads to IC_DATA_CMD in +// order to get status on 11 bit. +// +// 2. In order to read the 11 bit, the user has to perform the +// first data byte read [7:0] (offset 0x10) and then perform the +// second read [15:8] (offset 0x11) in order to know the status of +// 11 bit (whether the data received in previous read is a first +// data byte or not). +// +// 3. The 11th bit is an optional read field, user can ignore 2nd +// byte read [15:8] (offset 0x11) if not interested in +// FIRST_DATA_BYTE status. +// 0x0 -> Sequential data byte received +// 0x1 -> Non sequential data byte received +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_RESTART +// Description : This bit controls whether a RESTART is issued before the byte +// is sent or received. +// +// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data +// is sent/received (according to the value of CMD), regardless of +// whether or not the transfer direction is changing from the +// previous command; if IC_RESTART_EN is 0, a STOP followed by a +// START is issued instead. +// +// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the +// transfer direction is changing from the previous command; if +// IC_RESTART_EN is 0, a STOP followed by a START is issued +// instead. +// +// Reset value: 0x0 +// 0x0 -> Don't Issue RESTART before this command +// 0x1 -> Issue RESTART before this command +#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) +#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" +#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_STOP +// Description : This bit controls whether a STOP is issued after the byte is +// sent or received. +// +// - 1 - STOP is issued after this byte, regardless of whether or +// not the Tx FIFO is empty. If the Tx FIFO is not empty, the +// master immediately tries to start a new transfer by issuing a +// START and arbitrating for the bus. - 0 - STOP is not issued +// after this byte, regardless of whether or not the Tx FIFO is +// empty. If the Tx FIFO is not empty, the master continues the +// current transfer by sending/receiving data bytes according to +// the value of the CMD bit. If the Tx FIFO is empty, the master +// holds the SCL line low and stalls the bus until a new command +// is available in the Tx FIFO. Reset value: 0x0 +// 0x0 -> Don't Issue STOP after this command +// 0x1 -> Issue STOP after this command +#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) +#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) +#define I2C_IC_DATA_CMD_STOP_MSB _u(9) +#define I2C_IC_DATA_CMD_STOP_LSB _u(9) +#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" +#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_CMD +// Description : This bit controls whether a read or a write is performed. This +// bit does not control the direction when the DW_apb_i2con acts +// as a slave. It controls only the direction when it acts as a +// master. +// +// When a command is entered in the TX FIFO, this bit +// distinguishes the write and read commands. In slave-receiver +// mode, this bit is a 'don't care' because writes to this +// register are not required. In slave-transmitter mode, a '0' +// indicates that the data in IC_DATA_CMD is to be transmitted. +// +// When programming this bit, you should remember the following: +// attempting to perform a read operation after a General Call +// command has been sent results in a TX_ABRT interrupt (bit 6 of +// the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the +// IC_TAR register has been cleared. If a '1' is written to this +// bit after receiving a RD_REQ interrupt, then a TX_ABRT +// interrupt occurs. +// +// Reset value: 0x0 +// 0x0 -> Master Write Command +// 0x1 -> Master Read Command +#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) +#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) +#define I2C_IC_DATA_CMD_CMD_MSB _u(8) +#define I2C_IC_DATA_CMD_CMD_LSB _u(8) +#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" +#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) +#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_DAT +// Description : This register contains the data to be transmitted or received +// on the I2C bus. If you are writing to this register and want to +// perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. +// However, when you read this register, these bits return the +// value of data received on the DW_apb_i2c interface. +// +// Reset value: 0x0 +#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00) +#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff) +#define I2C_IC_DATA_CMD_DAT_MSB _u(7) +#define I2C_IC_DATA_CMD_DAT_LSB _u(0) +#define I2C_IC_DATA_CMD_DAT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_HCNT +// Description : Standard Speed I2C Clock SCL High Count Register +#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014) +#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration'. +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +// +// NOTE: This register must not be programmed to a value higher +// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an +// I2C bus idle condition when this counter reaches a value of +// IC_SS_SCL_HCNT + 10. +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_LCNT +// Description : Standard Speed I2C Clock SCL Low Count Register +#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018) +#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration' +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted, results in 8 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of +// DW_apb_i2c. The lower byte must be programmed first, and then +// the upper byte is programmed. +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_HCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register +#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c) +#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for fast mode or fast mode plus. It +// is used in high-speed mode to send the Master Code and START +// BYTE or General CALL. For more information, refer to 'IC_CLK +// Frequency Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. This register can be written only +// when the I2C interface is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH == 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_LCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register +#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020) +#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for fast speed. It is used in high- +// speed mode to send the Master Code and START BYTE or General +// CALL. For more information, refer to 'IC_CLK Frequency +// Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted results in 8 being +// set. For designs with APB_DATA_WIDTH = 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. If the value is less than 8 then the +// count value gets changed to 8. +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_INTR_STAT +// Description : I2C Interrupt Status Register +// +// Each bit in this register has a corresponding mask bit in the +// IC_INTR_MASK register. These bits are cleared by reading the +// matching interrupt clear register. The unmasked raw versions of +// these bits are available in the IC_RAW_INTR_STAT register. +#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c) +#define I2C_IC_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_INTR_STAT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RESTART_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of +// R_RESTART_DET bit. +// +// Reset value: 0x0 +// 0x0 -> R_RESTART_DET interrupt is inactive +// 0x1 -> R_RESTART_DET interrupt is active +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_GEN_CALL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_GEN_CALL interrupt is inactive +// 0x1 -> R_GEN_CALL interrupt is active +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_START_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_START_DET interrupt is inactive +// 0x1 -> R_START_DET interrupt is active +#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_STOP_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_STOP_DET interrupt is inactive +// 0x1 -> R_STOP_DET interrupt is active +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_ACTIVITY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_ACTIVITY interrupt is inactive +// 0x1 -> R_ACTIVITY interrupt is active +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_DONE +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_DONE interrupt is inactive +// 0x1 -> R_RX_DONE interrupt is active +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_ABRT +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_ABRT interrupt is inactive +// 0x1 -> R_TX_ABRT interrupt is active +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RD_REQ +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RD_REQ interrupt is inactive +// 0x1 -> R_RD_REQ interrupt is active +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_EMPTY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_EMPTY interrupt is inactive +// 0x1 -> R_TX_EMPTY interrupt is active +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_OVER interrupt is inactive +// 0x1 -> R_TX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_FULL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_FULL interrupt is inactive +// 0x1 -> R_RX_FULL interrupt is active +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_OVER interrupt is inactive +// 0x1 -> R_RX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_UNDER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER +// bit. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_INTR_MASK +// Description : I2C Interrupt Mask Register. +// +// These bits mask their corresponding interrupt status bits. This +// register is active low; a value of 0 masks the interrupt, +// whereas a value of 1 unmasks the interrupt. +#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030) +#define I2C_IC_INTR_MASK_BITS _u(0x00001fff) +#define I2C_IC_INTR_MASK_RESET _u(0x000008ff) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RESTART_DET +// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is masked +// 0x1 -> RESTART_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_GEN_CALL +// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> GEN_CALL interrupt is masked +// 0x1 -> GEN_CALL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_START_DET +// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is masked +// 0x1 -> START_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_STOP_DET +// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is masked +// 0x1 -> STOP_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_ACTIVITY +// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> ACTIVITY interrupt is masked +// 0x1 -> ACTIVITY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_DONE +// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_DONE interrupt is masked +// 0x1 -> RX_DONE interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_ABRT +// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_ABORT interrupt is masked +// 0x1 -> TX_ABORT interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RD_REQ +// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. +// +// Reset value: 0x1 +// 0x0 -> RD_REQ interrupt is masked +// 0x1 -> RD_REQ interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_EMPTY +// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_EMPTY interrupt is masked +// 0x1 -> TX_EMPTY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_OVER +// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_OVER interrupt is masked +// 0x1 -> TX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_FULL +// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_FULL interrupt is masked +// 0x1 -> RX_FULL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_OVER +// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_OVER interrupt is masked +// 0x1 -> RX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_UNDER +// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_UNDER interrupt is masked +// 0x1 -> RX_UNDER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_RAW_INTR_STAT +// Description : I2C Raw Interrupt Status Register +// +// Unlike the IC_INTR_STAT register, these bits are not masked so +// they always show the true status of the DW_apb_i2c. +#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034) +#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET +// Description : Indicates whether a RESTART condition has occurred on the I2C +// interface when DW_apb_i2c is operating in Slave mode and the +// slave is being addressed. Enabled only when +// IC_SLV_RESTART_DET_EN=1. +// +// Note: However, in high-speed mode or during a START BYTE +// transfer, the RESTART comes before the address field as per the +// I2C protocol. In this case, the slave is not the addressed +// slave when the RESTART is issued, therefore DW_apb_i2c does not +// generate the RESTART_DET interrupt. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is inactive +// 0x1 -> RESTART_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL +// Description : Set only when a General Call address is received and it is +// acknowledged. It stays set until it is cleared either by +// disabling DW_apb_i2c or when the CPU reads bit 0 of the +// IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data +// in the Rx buffer. +// +// Reset value: 0x0 +// 0x0 -> GEN_CALL interrupt is inactive +// 0x1 -> GEN_CALL interrupt is active +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_START_DET +// Description : Indicates whether a START or RESTART condition has occurred on +// the I2C interface regardless of whether DW_apb_i2c is operating +// in slave or master mode. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is inactive +// 0x1 -> START_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_STOP_DET +// Description : Indicates whether a STOP condition has occurred on the I2C +// interface regardless of whether DW_apb_i2c is operating in +// slave or master mode. +// +// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the +// STOP_DET interrupt will be issued only if slave is addressed. +// Note: During a general call address, this slave does not issue +// a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the +// slave responds to the general call address by generating ACK. +// The STOP_DET interrupt is generated only when the transmitted +// address matches the slave address (SAR). - If IC_CON[7]=1'b0 +// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued +// irrespective of whether it is being addressed. In Master Mode: +// - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET +// interrupt will be issued only if Master is active. - If +// IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt +// will be issued irrespective of whether master is active or not. +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is inactive +// 0x1 -> STOP_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY +// Description : This bit captures DW_apb_i2c activity and stays set until it is +// cleared. There are four ways to clear it: - Disabling the +// DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the +// IC_CLR_INTR register - System reset Once this bit is set, it +// stays set unless one of the four methods is used to clear it. +// Even if the DW_apb_i2c module is idle, this bit remains set +// until cleared, indicating that there was activity on the bus. +// +// Reset value: 0x0 +// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive +// 0x1 -> RAW_INTR_ACTIVITY interrupt is active +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_DONE +// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit +// is set to 1 if the master does not acknowledge a transmitted +// byte. This occurs on the last byte of the transmission, +// indicating that the transmission is done. +// +// Reset value: 0x0 +// 0x0 -> RX_DONE interrupt is inactive +// 0x1 -> RX_DONE interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT +// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is +// unable to complete the intended actions on the contents of the +// transmit FIFO. This situation can occur both as an I2C master +// or an I2C slave, and is referred to as a 'transmit abort'. When +// this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates +// the reason why the transmit abort takes places. +// +// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and +// RX_FIFO whenever there is a transmit abort caused by any of the +// events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs +// remains in this flushed state until the register IC_CLR_TX_ABRT +// is read. Once this read is performed, the Tx FIFO is then ready +// to accept more data bytes from the APB interface. +// +// Reset value: 0x0 +// 0x0 -> TX_ABRT interrupt is inactive +// 0x1 -> TX_ABRT interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RD_REQ +// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and +// another I2C master is attempting to read data from DW_apb_i2c. +// The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until +// this interrupt is serviced, which means that the slave has been +// addressed by a remote master that is asking for data to be +// transferred. The processor must respond to this interrupt and +// then write the requested data to the IC_DATA_CMD register. This +// bit is set to 0 just after the processor reads the +// IC_CLR_RD_REQ register. +// +// Reset value: 0x0 +// 0x0 -> RD_REQ interrupt is inactive +// 0x1 -> RD_REQ interrupt is active +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY +// Description : The behavior of the TX_EMPTY interrupt status differs based on +// the TX_EMPTY_CTRL selection in the IC_CON register. - When +// TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit +// buffer is at or below the threshold value set in the IC_TX_TL +// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when +// the transmit buffer is at or below the threshold value set in +// the IC_TX_TL register and the transmission of the address/data +// from the internal shift register for the most recently popped +// command is completed. It is automatically cleared by hardware +// when the buffer level goes above the threshold. When +// IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in +// reset. There the TX FIFO looks like it has no data within it, +// so this bit is set to 1, provided there is activity in the +// master or slave state machines. When there is no longer any +// activity, then with ic_en=0, this bit is set to 0. +// +// Reset value: 0x0. +// 0x0 -> TX_EMPTY interrupt is inactive +// 0x1 -> TX_EMPTY interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_OVER +// Description : Set during transmit if the transmit buffer is filled to +// IC_TX_BUFFER_DEPTH and the processor attempts to issue another +// I2C command by writing to the IC_DATA_CMD register. When the +// module is disabled, this bit keeps its level until the master +// or slave state machines go into idle, and when ic_en goes to 0, +// this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> TX_OVER interrupt is inactive +// 0x1 -> TX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_FULL +// Description : Set when the receive buffer reaches or goes above the RX_TL +// threshold in the IC_RX_TL register. It is automatically cleared +// by hardware when buffer level goes below the threshold. If the +// module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and +// held in reset; therefore the RX FIFO is not full. So this bit +// is cleared once the IC_ENABLE bit 0 is programmed with a 0, +// regardless of the activity that continues. +// +// Reset value: 0x0 +// 0x0 -> RX_FULL interrupt is inactive +// 0x1 -> RX_FULL interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_OVER +// Description : Set if the receive buffer is completely filled to +// IC_RX_BUFFER_DEPTH and an additional byte is received from an +// external I2C device. The DW_apb_i2c acknowledges this, but any +// data bytes received after the FIFO is full are lost. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) +// is programmed to HIGH, then the RX_OVER interrupt never occurs, +// because the Rx FIFO never overflows. +// +// Reset value: 0x0 +// 0x0 -> RX_OVER interrupt is inactive +// 0x1 -> RX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER +// Description : Set if the processor attempts to read the receive buffer when +// it is empty by reading from the IC_DATA_CMD register. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_RX_TL +// Description : I2C Receive FIFO Threshold Register +#define I2C_IC_RX_TL_OFFSET _u(0x00000038) +#define I2C_IC_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RX_TL_RX_TL +// Description : Receive FIFO Threshold Level. +// +// Controls the level of entries (or above) that triggers the +// RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that +// hardware does not allow this value to be set to a value larger +// than the depth of the buffer. If an attempt is made to do that, +// the actual value set will be the maximum depth of the buffer. A +// value of 0 sets the threshold for 1 entry, and a value of 255 +// sets the threshold for 256 entries. +#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00) +#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RX_TL_MSB _u(7) +#define I2C_IC_RX_TL_RX_TL_LSB _u(0) +#define I2C_IC_RX_TL_RX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_TL +// Description : I2C Transmit FIFO Threshold Register +#define I2C_IC_TX_TL_OFFSET _u(0x0000003c) +#define I2C_IC_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_TL_TX_TL +// Description : Transmit FIFO Threshold Level. +// +// Controls the level of entries (or below) that trigger the +// TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that it +// may not be set to value larger than the depth of the buffer. If +// an attempt is made to do that, the actual value set will be the +// maximum depth of the buffer. A value of 0 sets the threshold +// for 0 entries, and a value of 255 sets the threshold for 255 +// entries. +#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00) +#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_TX_TL_MSB _u(7) +#define I2C_IC_TX_TL_TX_TL_LSB _u(0) +#define I2C_IC_TX_TL_TX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_INTR +// Description : Clear Combined and Individual Interrupt Register +#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040) +#define I2C_IC_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_INTR_CLR_INTR +// Description : Read this register to clear the combined interrupt, all +// individual interrupts, and the IC_TX_ABRT_SOURCE register. This +// bit does not clear hardware clearable interrupts but software +// clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE +// register for an exception to clearing IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0) +#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0) +#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0) +#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_UNDER +// Description : Clear RX_UNDER Interrupt Register +#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044) +#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER +// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_OVER +// Description : Clear RX_OVER Interrupt Register +#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048) +#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER +// Description : Read this register to clear the RX_OVER interrupt (bit 1) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_OVER +// Description : Clear TX_OVER Interrupt Register +#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c) +#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER +// Description : Read this register to clear the TX_OVER interrupt (bit 3) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RD_REQ +// Description : Clear RD_REQ Interrupt Register +#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050) +#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ +// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_ABRT +// Description : Clear TX_ABRT Interrupt Register +#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054) +#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT +// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of +// the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE +// register. This also releases the TX FIFO from the flushed/reset +// state, allowing more writes to the TX FIFO. Refer to Bit 9 of +// the IC_TX_ABRT_SOURCE register for an exception to clearing +// IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_DONE +// Description : Clear RX_DONE Interrupt Register +#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058) +#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE +// Description : Read this register to clear the RX_DONE interrupt (bit 7) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_ACTIVITY +// Description : Clear ACTIVITY Interrupt Register +#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c) +#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY +// Description : Reading this register clears the ACTIVITY interrupt if the I2C +// is not active anymore. If the I2C module is still active on the +// bus, the ACTIVITY interrupt bit continues to be set. It is +// automatically cleared by hardware if the module is disabled and +// if there is no further activity on the bus. The value read from +// this register to get status of the ACTIVITY interrupt (bit 8) +// of the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_STOP_DET +// Description : Clear STOP_DET Interrupt Register +#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060) +#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET +// Description : Read this register to clear the STOP_DET interrupt (bit 9) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_START_DET +// Description : Clear START_DET Interrupt Register +#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064) +#define I2C_IC_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_START_DET_CLR_START_DET +// Description : Read this register to clear the START_DET interrupt (bit 10) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_GEN_CALL +// Description : Clear GEN_CALL Interrupt Register +#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068) +#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL +// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_ENABLE +// Description : I2C Enable Register +#define I2C_IC_ENABLE_OFFSET _u(0x0000006c) +#define I2C_IC_ENABLE_BITS _u(0x00000007) +#define I2C_IC_ENABLE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_TX_CMD_BLOCK +// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C +// bus even if Tx FIFO has data to transmit. - 1'b0: The +// transmission of data starts on I2C bus automatically, as soon +// as the first data is available in the Tx FIFO. Note: To block +// the execution of Master commands, set the TX_CMD_BLOCK bit only +// when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle +// state (IC_STATUS[5] == 0). Any further commands put in the Tx +// FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset +// value: IC_TX_CMD_BLOCK_DEFAULT +// 0x0 -> Tx Command execution not blocked +// 0x1 -> Tx Command execution blocked +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ABORT +// Description : When set, the controller initiates the transfer abort. - 0: +// ABORT not initiated or ABORT done - 1: ABORT operation in +// progress The software can abort the I2C transfer in master mode +// by setting this bit. The software can set this bit only when +// ENABLE is already set; otherwise, the controller ignores any +// write to ABORT bit. The software cannot clear the ABORT bit +// once set. In response to an ABORT, the controller issues a STOP +// and flushes the Tx FIFO after completing the current transfer, +// then sets the TX_ABORT interrupt after the abort operation. The +// ABORT bit is cleared automatically after the abort operation. +// +// For a detailed description on how to abort I2C transfers, refer +// to 'Aborting I2C Transfers'. +// +// Reset value: 0x0 +// 0x0 -> ABORT operation not in progress +// 0x1 -> ABORT operation in progress +#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) +#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) +#define I2C_IC_ENABLE_ABORT_MSB _u(1) +#define I2C_IC_ENABLE_ABORT_LSB _u(1) +#define I2C_IC_ENABLE_ABORT_ACCESS "RW" +#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) +#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ENABLE +// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables +// DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: +// Enables DW_apb_i2c Software can disable DW_apb_i2c while it is +// active. However, it is important that care be taken to ensure +// that DW_apb_i2c is disabled properly. A recommended procedure +// is described in 'Disabling DW_apb_i2c'. +// +// When DW_apb_i2c is disabled, the following occurs: - The TX +// FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT +// register are still active until DW_apb_i2c goes into IDLE +// state. If the module is transmitting, it stops as well as +// deletes the contents of the transmit buffer after the current +// transfer is complete. If the module is receiving, the +// DW_apb_i2c stops the current transfer at the end of the current +// byte and does not acknowledge the transfer. +// +// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE +// parameter set to asynchronous (1), there is a two ic_clk delay +// when enabling or disabling the DW_apb_i2c. For a detailed +// description on how to disable DW_apb_i2c, refer to 'Disabling +// DW_apb_i2c' +// +// Reset value: 0x0 +// 0x0 -> I2C is disabled +// 0x1 -> I2C is enabled +#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) +#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) +#define I2C_IC_ENABLE_ENABLE_MSB _u(0) +#define I2C_IC_ENABLE_ENABLE_LSB _u(0) +#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" +#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_STATUS +// Description : I2C Status Register +// +// This is a read-only register used to indicate the current +// transfer status and FIFO status. The status register may be +// read at any time. None of the bits in this register request an +// interrupt. +// +// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE +// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set +// to 0 When the master or slave state machines goes to idle and +// ic_en=0: - Bits 5 and 6 are set to 0 +#define I2C_IC_STATUS_OFFSET _u(0x00000070) +#define I2C_IC_STATUS_BITS _u(0x0000007f) +#define I2C_IC_STATUS_RESET _u(0x00000006) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_SLV_ACTIVITY +// Description : Slave FSM Activity Status. When the Slave Finite State Machine +// (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM +// is in IDLE state so the Slave part of DW_apb_i2c is not Active +// - 1: Slave FSM is not in IDLE state so the Slave part of +// DW_apb_i2c is Active Reset value: 0x0 +// 0x0 -> Slave is idle +// 0x1 -> Slave not idle +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_MST_ACTIVITY +// Description : Master FSM Activity Status. When the Master Finite State +// Machine (FSM) is not in the IDLE state, this bit is set. - 0: +// Master FSM is in IDLE state so the Master part of DW_apb_i2c is +// not Active - 1: Master FSM is not in IDLE state so the Master +// part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, +// ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. +// +// Reset value: 0x0 +// 0x0 -> Master is idle +// 0x1 -> Master not idle +#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) +#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFF +// Description : Receive FIFO Completely Full. When the receive FIFO is +// completely full, this bit is set. When the receive FIFO +// contains one or more empty location, this bit is cleared. - 0: +// Receive FIFO is not full - 1: Receive FIFO is full Reset value: +// 0x0 +// 0x0 -> Rx FIFO not full +// 0x1 -> Rx FIFO is full +#define I2C_IC_STATUS_RFF_RESET _u(0x0) +#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) +#define I2C_IC_STATUS_RFF_MSB _u(4) +#define I2C_IC_STATUS_RFF_LSB _u(4) +#define I2C_IC_STATUS_RFF_ACCESS "RO" +#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) +#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFNE +// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO +// contains one or more entries; it is cleared when the receive +// FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is +// not empty Reset value: 0x0 +// 0x0 -> Rx FIFO is empty +// 0x1 -> Rx FIFO not empty +#define I2C_IC_STATUS_RFNE_RESET _u(0x0) +#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) +#define I2C_IC_STATUS_RFNE_MSB _u(3) +#define I2C_IC_STATUS_RFNE_LSB _u(3) +#define I2C_IC_STATUS_RFNE_ACCESS "RO" +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) +#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFE +// Description : Transmit FIFO Completely Empty. When the transmit FIFO is +// completely empty, this bit is set. When it contains one or more +// valid entries, this bit is cleared. This bit field does not +// request an interrupt. - 0: Transmit FIFO is not empty - 1: +// Transmit FIFO is empty Reset value: 0x1 +// 0x0 -> Tx FIFO not empty +// 0x1 -> Tx FIFO is empty +#define I2C_IC_STATUS_TFE_RESET _u(0x1) +#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) +#define I2C_IC_STATUS_TFE_MSB _u(2) +#define I2C_IC_STATUS_TFE_LSB _u(2) +#define I2C_IC_STATUS_TFE_ACCESS "RO" +#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) +#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFNF +// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one +// or more empty locations, and is cleared when the FIFO is full. +// - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset +// value: 0x1 +// 0x0 -> Tx FIFO is full +// 0x1 -> Tx FIFO not full +#define I2C_IC_STATUS_TFNF_RESET _u(0x1) +#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) +#define I2C_IC_STATUS_TFNF_MSB _u(1) +#define I2C_IC_STATUS_TFNF_LSB _u(1) +#define I2C_IC_STATUS_TFNF_ACCESS "RO" +#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) +#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_ACTIVITY +// Description : I2C Activity Status. Reset value: 0x0 +// 0x0 -> I2C is idle +// 0x1 -> I2C is active +#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_TXFLR +// Description : I2C Transmit FIFO Level Register This register contains the +// number of valid data entries in the transmit FIFO buffer. It is +// cleared whenever: - The I2C is disabled - There is a transmit +// abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT +// register - The slave bulk transmit mode is aborted The register +// increments whenever data is placed into the transmit FIFO and +// decrements when data is taken from the transmit FIFO. +#define I2C_IC_TXFLR_OFFSET _u(0x00000074) +#define I2C_IC_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TXFLR_TXFLR +// Description : Transmit FIFO Level. Contains the number of valid data entries +// in the transmit FIFO. +// +// Reset value: 0x0 +#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00) +#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_TXFLR_MSB _u(4) +#define I2C_IC_TXFLR_TXFLR_LSB _u(0) +#define I2C_IC_TXFLR_TXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_RXFLR +// Description : I2C Receive FIFO Level Register This register contains the +// number of valid data entries in the receive FIFO buffer. It is +// cleared whenever: - The I2C is disabled - Whenever there is a +// transmit abort caused by any of the events tracked in +// IC_TX_ABRT_SOURCE The register increments whenever data is +// placed into the receive FIFO and decrements when data is taken +// from the receive FIFO. +#define I2C_IC_RXFLR_OFFSET _u(0x00000078) +#define I2C_IC_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RXFLR_RXFLR +// Description : Receive FIFO Level. Contains the number of valid data entries +// in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00) +#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RXFLR_MSB _u(4) +#define I2C_IC_RXFLR_RXFLR_LSB _u(0) +#define I2C_IC_RXFLR_RXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_SDA_HOLD +// Description : I2C SDA Hold Time Length Register +// +// The bits [15:0] of this register are used to control the hold +// time of SDA during transmit in both slave and master mode +// (after SCL goes from HIGH to LOW). +// +// The bits [23:16] of this register are used to extend the SDA +// transition (if any) whenever SCL is HIGH in the receiver in +// either master or slave mode. +// +// Writes to this register succeed only when IC_ENABLE[0]=0. +// +// The values in this register are in units of ic_clk period. The +// value programmed in IC_SDA_TX_HOLD must be greater than the +// minimum hold time in each mode (one cycle in master mode, seven +// cycles in slave mode) for the value to be implemented. +// +// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) +// cannot exceed at any time the duration of the low part of scl. +// Therefore the programmed value cannot be larger than +// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of +// the scl period measured in ic_clk cycles. +#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c) +#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff) +#define I2C_IC_SDA_HOLD_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a receiver. +// +// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a transmitter. +// +// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_ABRT_SOURCE +// Description : I2C Transmit Abort Source Register +// +// This register has 32 bits that indicate the source of the +// TX_ABRT bit. Except for Bit 9, this register is cleared +// whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR +// register is read. To clear Bit 9, the source of the +// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled +// (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or +// the GC_OR_START bit must be cleared (IC_TAR[10]). +// +// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this +// bit can be cleared in the same manner as other bits in this +// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed +// before attempting to clear this bit, Bit 9 clears for one cycle +// and is then re-asserted. +#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff) +#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT +// Description : This field indicates the number of Tx FIFO Data Commands which +// are flushed due to TX_ABRT interrupt. It is cleared whenever +// I2C is disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT +// Description : This is a master-mode-only bit. Master has detected the +// transfer abort (IC_ENABLE[1]) +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transfer abort detected by master- scenario not present +// 0x1 -> Transfer abort detected by master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX +// Description : 1: When the processor side responds to a slave mode request for +// data to be transmitted to a remote master and user writes a 1 +// in CMD (bit 8) of IC_DATA_CMD register. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present +// 0x1 -> Slave trying to transmit to remote master in read mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST +// Description : This field indicates that a Slave has lost the bus while +// transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is +// set at the same time. Note: Even though the slave never 'owns' +// the bus, something could go wrong on the bus. This is a fail +// safe check. For instance, during a data transmission at the +// low-to-high transition of SCL, if what is on the data bus is +// not what is supposed to be transmitted, then DW_apb_i2c no +// longer own the bus. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave lost arbitration to remote master- scenario not present +// 0x1 -> Slave lost arbitration to remote master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO +// Description : This field specifies that the Slave has received a read command +// and some data exists in the TX FIFO, so the slave issues a +// TX_ABRT interrupt to flush old data in TX FIFO. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST +// Description : This field specifies that the Master has lost arbitration, or +// if IC_TX_ABRT_SOURCE[14] is also set, then the slave +// transmitter has lost arbitration. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present +// 0x1 -> Master or Slave-Transmitter lost arbitration +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS +// Description : This field indicates that the User tries to initiate a Master +// operation with the Master mode disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User initiating master operation when MASTER disabled- scenario not present +// 0x1 -> User initiating master operation when MASTER disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read +// command in 10-bit addressing mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Receiver +// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT +// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be +// fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL +// bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must +// be cleared (IC_TAR[10]). Once the source of the +// ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in +// the same manner as other bits in this register. If the source +// of the ABRT_SBYTE_NORSTRT is not fixed before attempting to +// clear this bit, bit 9 clears for one cycle and then gets +// reasserted. When this field is set to 1, the restart is +// disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is +// trying to send a START Byte. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present +// 0x1 -> User trying to send START byte when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to +// use the master to transfer data in High Speed mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present +// 0x1 -> User trying to switch Master to HS mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET +// Description : This field indicates that the Master has sent a START Byte and +// the START Byte was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> ACK detected for START byte- scenario not present +// 0x1 -> ACK detected for START byte +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET +// Description : This field indicates that the Master is in High Speed mode and +// the High Speed Master code was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> HS Master code ACKed in HS Mode- scenario not present +// 0x1 -> HS Master code ACKed in HS Mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ +// Description : This field indicates that DW_apb_i2c in the master mode has +// sent a General Call but the user programmed the byte following +// the General Call to be a read from the bus (IC_DATA_CMD[9] is +// set to 1). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL is followed by read from bus-scenario not present +// 0x1 -> GCALL is followed by read from bus +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK +// Description : This field indicates that DW_apb_i2c in master mode has sent a +// General Call and no slave on the bus acknowledged the General +// Call. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL not ACKed by any slave-scenario not present +// 0x1 -> GCALL not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK +// Description : This field indicates the master-mode only bit. When the master +// receives an acknowledgement for the address, but when it sends +// data byte(s) following the address, it did not receive an +// acknowledge from the remote slave(s). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present +// 0x1 -> Transmitted data not ACKed by addressed slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and that the second address byte of the 10-bit address was not +// acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and the first 10-bit address byte was not acknowledged by any +// slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK +// Description : This field indicates that the Master is in 7-bit addressing +// mode and the address sent was not acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> This abort is generated because of NOACK for 7-bit address +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_SLV_DATA_NACK_ONLY +// Description : Generate Slave Data NACK Register +// +// The register is used to generate a NACK for the data part of a +// transfer when DW_apb_i2c is acting as a slave-receiver. This +// register only exists when the IC_SLV_DATA_NACK_ONLY parameter +// is set to 1. When this parameter disabled, this register does +// not exist and writing to the register's address has no effect. +// +// A write can occur on this register if both of the following +// conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) +// - Slave part is inactive (IC_STATUS[6] = 0) Note: The +// IC_STATUS[6] is a register read-back location for the internal +// slv_activity signal; the user should poll this before writing +// the ic_slv_data_nack_only bit. +#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084) +#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK +// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c +// is a slave-receiver. If this register is set to a value of 1, +// it can only generate a NACK after a data byte is received; +// hence, the data transfer is aborted and the data received is +// not pushed to the receive buffer. +// +// When the register is set to a value of 0, it generates +// NACK/ACK, depending on normal criteria. - 1: generate NACK +// after data byte received - 0: generate NACK/ACK normally Reset +// value: 0x0 +// 0x0 -> Slave receiver generates NACK normally +// 0x1 -> Slave receiver generates NACK upon data reception only +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_DMA_CR +// Description : DMA Control Register +// +// The register is used to enable the DMA Controller interface +// operation. There is a separate bit for transmit and receive. +// This can be programmed regardless of the state of IC_ENABLE. +#define I2C_IC_DMA_CR_OFFSET _u(0x00000088) +#define I2C_IC_DMA_CR_BITS _u(0x00000003) +#define I2C_IC_DMA_CR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_TDMAE +// Description : Transmit DMA Enable. This bit enables/disables the transmit +// FIFO DMA channel. Reset value: 0x0 +// 0x0 -> transmit FIFO DMA channel disabled +// 0x1 -> Transmit FIFO DMA channel enabled +#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) +#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_RDMAE +// Description : Receive DMA Enable. This bit enables/disables the receive FIFO +// DMA channel. Reset value: 0x0 +// 0x0 -> Receive FIFO DMA channel disabled +// 0x1 -> Receive FIFO DMA channel enabled +#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) +#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_DMA_TDLR +// Description : DMA Transmit Data Level Register +#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c) +#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_TDLR_DMATDL +// Description : Transmit Data Level. This bit field controls the level at which +// a DMA request is made by the transmit logic. It is equal to the +// watermark level; that is, the dma_tx_req signal is generated +// when the number of valid data entries in the transmit FIFO is +// equal to or below this field value, and TDMAE = 1. +// +// Reset value: 0x0 +#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0) +#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3) +#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0) +#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DMA_RDLR +// Description : I2C Receive Data Level Register +#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090) +#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_RDLR_DMARDL +// Description : Receive Data Level. This bit field controls the level at which +// a DMA request is made by the receive logic. The watermark level +// = DMARDL+1; that is, dma_rx_req is generated when the number of +// valid data entries in the receive FIFO is equal to or more than +// this field value + 1, and RDMAE =1. For instance, when DMARDL +// is 0, then dma_rx_req is asserted when 1 or more data entries +// are present in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0) +#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3) +#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0) +#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SDA_SETUP +// Description : I2C SDA Setup Register +// +// This register controls the amount of time delay (in terms of +// number of ic_clk clock periods) introduced in the rising edge +// of SCL - relative to SDA changing - when DW_apb_i2c services a +// read request in a slave-transmitter operation. The relevant I2C +// requirement is tSU:DAT (note 4) as detailed in the I2C Bus +// Specification. This register must be programmed with a value +// equal to or greater than 2. +// +// Writes to this register succeed only when IC_ENABLE[0] = 0. +// +// Note: The length of setup time is calculated using +// [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires +// 10 ic_clk periods of setup time, they should program a value of +// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c +// when operating as a slave transmitter. +#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094) +#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_RESET _u(0x00000064) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_SETUP_SDA_SETUP +// Description : SDA Setup. It is recommended that if the required delay is +// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP +// should be programmed to a value of 11. IC_SDA_SETUP must be +// programmed with a minimum value of 2. +#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64) +#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7) +#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0) +#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_ACK_GENERAL_CALL +// Description : I2C ACK General Call Register +// +// The register controls whether DW_apb_i2c responds with a ACK or +// NACK when it receives an I2C General Call address. +// +// This register is applicable only when the DW_apb_i2c is in +// slave mode. +#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098) +#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL +// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK +// (by asserting ic_data_oe) when it receives a General Call. +// Otherwise, DW_apb_i2c responds with a NACK (by negating +// ic_data_oe). +// 0x0 -> Generate NACK for a General Call +// 0x1 -> Generate ACK for a General Call +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_ENABLE_STATUS +// Description : I2C Enable Status Register +// +// The register is used to report the DW_apb_i2c hardware status +// when the IC_ENABLE[0] register is set from 1 to 0; that is, +// when DW_apb_i2c is disabled. +// +// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, +// and bit 0 is forced to 1. +// +// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as +// soon as bit 0 is read as '0'. +// +// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for +// bit 0 to be read as 0 because disabling the DW_apb_i2c depends +// on I2C bus activities. +#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c) +#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007) +#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST +// Description : Slave Received Data Lost. This bit indicates if a Slave- +// Receiver operation has been aborted with at least one data byte +// received from an I2C transfer due to the setting bit 0 of +// IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to +// have been actively engaged in an aborted I2C transfer (with +// matching address) and the data phase of the I2C transfer has +// been entered, even though a data byte has been responded with a +// NACK. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit is +// also set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled +// without being actively involved in the data phase of a Slave- +// Receiver transfer. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave RX Data is not lost +// 0x1 -> Slave RX Data is lost +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY +// Description : Slave Disabled While Busy (Transmit, Receive). This bit +// indicates if a potential or active Slave operation has been +// aborted due to the setting bit 0 of the IC_ENABLE register from +// 1 to 0. This bit is set when the CPU writes a 0 to the +// IC_ENABLE register while: +// +// (a) DW_apb_i2c is receiving the address byte of the Slave- +// Transmitter operation from a remote master; +// +// OR, +// +// (b) address and data bytes of the Slave-Receiver operation from +// a remote master. +// +// When read as 1, DW_apb_i2c is deemed to have forced a NACK +// during any part of an I2C transfer, irrespective of whether the +// I2C address matches the slave address set in DW_apb_i2c (IC_SAR +// register) OR if the transfer is completed before IC_ENABLE is +// set to 0 but has not taken effect. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit +// will also be set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled when +// there is master activity, or when the I2C bus is idle. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave is disabled when it is idle +// 0x1 -> Slave is disabled when it is active +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_IC_EN +// Description : ic_en Status. This bit always reflects the value driven on the +// output port ic_en. - When read as 1, DW_apb_i2c is deemed to be +// in an enabled state. - When read as 0, DW_apb_i2c is deemed +// completely inactive. Note: The CPU can safely read this bit +// anytime. When this bit is read as 0, the CPU can safely read +// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). +// +// Reset value: 0x0 +// 0x0 -> I2C disabled +// 0x1 -> I2C enabled +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_FS_SPKLEN +// Description : I2C SS, FS or FM+ spike suppression limit +// +// This register is used to store the duration, measured in ic_clk +// cycles, of the longest spike that is filtered out by the spike +// suppression logic when the component is operating in SS, FS or +// FM+ modes. The relevant I2C requirement is tSP (table 4) as +// detailed in the I2C Bus Specification. This register must be +// programmed with a minimum value of 1. +#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0) +#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN +// Description : This register must be set before any I2C bus transaction can +// take place to ensure stable operation. This register sets the +// duration, measured in ic_clk cycles, of the longest spike in +// the SCL or SDA lines that will be filtered out by the spike +// suppression logic. This register can be written only when the +// I2C interface is disabled which corresponds to the IC_ENABLE[0] +// register being set to 0. Writes at other times have no effect. +// The minimum valid value is 1; hardware prevents values less +// than this being written, and if attempted results in 1 being +// set. or more information, refer to 'Spike Suppression'. +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_RESTART_DET +// Description : Clear RESTART_DET Interrupt Register +#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8) +#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET +// Description : Read this register to clear the RESTART_DET interrupt (bit 12) +// of IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_PARAM_1 +// Description : Component Parameter Register 1 +// +// Note This register is not implemented and therefore reads as 0. +// If it was implemented it would be a constant read-only register +// that contains encoded information about the component's +// parameter settings. Fields shown below are the settings for +// those parameters +#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4) +#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff) +#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH +// Description : TX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH +// Description : RX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS +// Description : Encoded parameters not visible +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HAS_DMA +// Description : DMA handshaking signals are enabled +#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_INTR_IO +// Description : COMBINED Interrupt outputs +#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020) +#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5) +#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5) +#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES +// Description : Programmable count values for each mode. +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE +// Description : MAX SPEED MODE = FAST MODE +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH +// Description : APB data bus width is 32 bits +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_VERSION +// Description : I2C Component Version Register +#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8) +#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_TYPE +// Description : I2C Component Type Register +#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc) +#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_RESET _u(0x44570140) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE +// Description : Designware Component Type number = 0x44_57_01_40. This assigned +// unique hex value is constant and is derived from the two ASCII +// letters 'DW' followed by a 16-bit unsigned number. +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_I2C_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/intctrl.h b/src/rp2350/hardware_regs/include/hardware/regs/intctrl.h new file mode 100644 index 000000000..96ce815e4 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/intctrl.h @@ -0,0 +1,184 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _INTCTRL_H +#define _INTCTRL_H + +/** + * \file rp2350/intctrl.h + */ + +#ifdef __ASSEMBLER__ +#define TIMER0_IRQ_0 0 +#define TIMER0_IRQ_1 1 +#define TIMER0_IRQ_2 2 +#define TIMER0_IRQ_3 3 +#define TIMER1_IRQ_0 4 +#define TIMER1_IRQ_1 5 +#define TIMER1_IRQ_2 6 +#define TIMER1_IRQ_3 7 +#define PWM_IRQ_WRAP_0 8 +#define PWM_IRQ_WRAP_1 9 +#define DMA_IRQ_0 10 +#define DMA_IRQ_1 11 +#define DMA_IRQ_2 12 +#define DMA_IRQ_3 13 +#define USBCTRL_IRQ 14 +#define PIO0_IRQ_0 15 +#define PIO0_IRQ_1 16 +#define PIO1_IRQ_0 17 +#define PIO1_IRQ_1 18 +#define PIO2_IRQ_0 19 +#define PIO2_IRQ_1 20 +#define IO_IRQ_BANK0 21 +#define IO_IRQ_BANK0_NS 22 +#define IO_IRQ_QSPI 23 +#define IO_IRQ_QSPI_NS 24 +#define SIO_IRQ_FIFO 25 +#define SIO_IRQ_BELL 26 +#define SIO_IRQ_FIFO_NS 27 +#define SIO_IRQ_BELL_NS 28 +#define SIO_IRQ_MTIMECMP 29 +#define CLOCKS_IRQ 30 +#define SPI0_IRQ 31 +#define SPI1_IRQ 32 +#define UART0_IRQ 33 +#define UART1_IRQ 34 +#define ADC_IRQ_FIFO 35 +#define I2C0_IRQ 36 +#define I2C1_IRQ 37 +#define OTP_IRQ 38 +#define TRNG_IRQ 39 +#define PROC0_IRQ_CTI 40 +#define PROC1_IRQ_CTI 41 +#define PLL_SYS_IRQ 42 +#define PLL_USB_IRQ 43 +#define POWMAN_IRQ_POW 44 +#define POWMAN_IRQ_TIMER 45 +#define SPAREIRQ_IRQ_0 46 +#define SPAREIRQ_IRQ_1 47 +#define SPAREIRQ_IRQ_2 48 +#define SPAREIRQ_IRQ_3 49 +#define SPAREIRQ_IRQ_4 50 +#define SPAREIRQ_IRQ_5 51 +#else +/** + * \brief Interrupt numbers on RP2350 (used as typedef \ref irq_num_t) + * \ingroup hardware_irq + */ +typedef enum irq_num_rp2350 { + TIMER0_IRQ_0 = 0, ///< Select TIMER0's IRQ 0 output + TIMER0_IRQ_1 = 1, ///< Select TIMER0's IRQ 1 output + TIMER0_IRQ_2 = 2, ///< Select TIMER0's IRQ 2 output + TIMER0_IRQ_3 = 3, ///< Select TIMER0's IRQ 3 output + TIMER1_IRQ_0 = 4, ///< Select TIMER1's IRQ 0 output + TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output + TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output + TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output + PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output + PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output + DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output + DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output + DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output + DMA_IRQ_3 = 13, ///< Select DMA's IRQ 3 output + USBCTRL_IRQ = 14, ///< Select USBCTRL's IRQ output + PIO0_IRQ_0 = 15, ///< Select PIO0's IRQ 0 output + PIO0_IRQ_1 = 16, ///< Select PIO0's IRQ 1 output + PIO1_IRQ_0 = 17, ///< Select PIO1's IRQ 0 output + PIO1_IRQ_1 = 18, ///< Select PIO1's IRQ 1 output + PIO2_IRQ_0 = 19, ///< Select PIO2's IRQ 0 output + PIO2_IRQ_1 = 20, ///< Select PIO2's IRQ 1 output + IO_IRQ_BANK0 = 21, ///< Select IO_BANK0's IRQ output + IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output + IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output + IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output + SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output + SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output + SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output + SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output + SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output + CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output + SPI0_IRQ = 31, ///< Select SPI0's IRQ output + SPI1_IRQ = 32, ///< Select SPI1's IRQ output + UART0_IRQ = 33, ///< Select UART0's IRQ output + UART1_IRQ = 34, ///< Select UART1's IRQ output + ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output + I2C0_IRQ = 36, ///< Select I2C0's IRQ output + I2C1_IRQ = 37, ///< Select I2C1's IRQ output + OTP_IRQ = 38, ///< Select OTP's IRQ output + TRNG_IRQ = 39, ///< Select TRNG's IRQ output + PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output + PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output + PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output + PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output + POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output + POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output + SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0 + SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1 + SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2 + SPARE_IRQ_3 = 49, ///< Select SPARE IRQ 3 + SPARE_IRQ_4 = 50, ///< Select SPARE IRQ 4 + SPARE_IRQ_5 = 51, ///< Select SPARE IRQ 5 + IRQ_COUNT +} irq_num_t; +#endif + +#define isr_timer0_0 isr_irq0 +#define isr_timer0_1 isr_irq1 +#define isr_timer0_2 isr_irq2 +#define isr_timer0_3 isr_irq3 +#define isr_timer1_0 isr_irq4 +#define isr_timer1_1 isr_irq5 +#define isr_timer1_2 isr_irq6 +#define isr_timer1_3 isr_irq7 +#define isr_pwm_wrap_0 isr_irq8 +#define isr_pwm_wrap_1 isr_irq9 +#define isr_dma_0 isr_irq10 +#define isr_dma_1 isr_irq11 +#define isr_dma_2 isr_irq12 +#define isr_dma_3 isr_irq13 +#define isr_usbctrl isr_irq14 +#define isr_pio0_0 isr_irq15 +#define isr_pio0_1 isr_irq16 +#define isr_pio1_0 isr_irq17 +#define isr_pio1_1 isr_irq18 +#define isr_pio2_0 isr_irq19 +#define isr_pio2_1 isr_irq20 +#define isr_io_bank0 isr_irq21 +#define isr_io_bank0_ns isr_irq22 +#define isr_io_qspi isr_irq23 +#define isr_io_qspi_ns isr_irq24 +#define isr_sio_fifo isr_irq25 +#define isr_sio_bell isr_irq26 +#define isr_sio_fifo_ns isr_irq27 +#define isr_sio_bell_ns isr_irq28 +#define isr_sio_mtimecmp isr_irq29 +#define isr_clocks isr_irq30 +#define isr_spi0 isr_irq31 +#define isr_spi1 isr_irq32 +#define isr_uart0 isr_irq33 +#define isr_uart1 isr_irq34 +#define isr_adc_fifo isr_irq35 +#define isr_i2c0 isr_irq36 +#define isr_i2c1 isr_irq37 +#define isr_otp isr_irq38 +#define isr_trng isr_irq39 +#define isr_proc0_cti isr_irq40 +#define isr_proc1_cti isr_irq41 +#define isr_pll_sys isr_irq42 +#define isr_pll_usb isr_irq43 +#define isr_powman_pow isr_irq44 +#define isr_powman_timer isr_irq45 +#define isr_spare_0 isr_irq46 +#define isr_spare_1 isr_irq47 +#define isr_spare_2 isr_irq48 +#define isr_spare_3 isr_irq49 +#define isr_spare_4 isr_irq50 +#define isr_spare_5 isr_irq51 + +#endif // _INTCTRL_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/io_bank0.h b/src/rp2350/hardware_regs/include/hardware/regs/io_bank0.h new file mode 100644 index 000000000..6c2f96ecb --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/io_bank0.h @@ -0,0 +1,22339 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_BANK0 +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_IO_BANK0_H +#define _HARDWARE_REGS_IO_BANK0_H +// ============================================================================= +// Register : IO_BANK0_GPIO0_STATUS +#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) +#define IO_BANK0_GPIO0_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO0_CTRL +#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) +#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tck +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> siob_proc_0 +// 0x06 -> pio0_0 +// 0x07 -> pio1_0 +// 0x08 -> pio2_0 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIOB_PROC_0 _u(0x05) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO2_0 _u(0x08) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO1_STATUS +#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) +#define IO_BANK0_GPIO1_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO1_CTRL +#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) +#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tms +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> siob_proc_1 +// 0x06 -> pio0_1 +// 0x07 -> pio1_1 +// 0x08 -> pio2_1 +// 0x09 -> coresight_traceclk +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIOB_PROC_1 _u(0x05) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO2_1 _u(0x08) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACECLK _u(0x09) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO2_STATUS +#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) +#define IO_BANK0_GPIO2_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO2_CTRL +#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) +#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdi +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> siob_proc_2 +// 0x06 -> pio0_2 +// 0x07 -> pio1_2 +// 0x08 -> pio2_2 +// 0x09 -> coresight_tracedata_0 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIOB_PROC_2 _u(0x05) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO2_2 _u(0x08) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_0 _u(0x09) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO3_STATUS +#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) +#define IO_BANK0_GPIO3_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO3_CTRL +#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) +#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdo +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> siob_proc_3 +// 0x06 -> pio0_3 +// 0x07 -> pio1_3 +// 0x08 -> pio2_3 +// 0x09 -> coresight_tracedata_1 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIOB_PROC_3 _u(0x05) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO2_3 _u(0x08) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_1 _u(0x09) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO4_STATUS +#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) +#define IO_BANK0_GPIO4_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO4_CTRL +#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) +#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> siob_proc_4 +// 0x06 -> pio0_4 +// 0x07 -> pio1_4 +// 0x08 -> pio2_4 +// 0x09 -> coresight_tracedata_2 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIOB_PROC_4 _u(0x05) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO2_4 _u(0x08) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_2 _u(0x09) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO5_STATUS +#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) +#define IO_BANK0_GPIO5_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO5_CTRL +#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) +#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> siob_proc_5 +// 0x06 -> pio0_5 +// 0x07 -> pio1_5 +// 0x08 -> pio2_5 +// 0x09 -> coresight_tracedata_3 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIOB_PROC_5 _u(0x05) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO2_5 _u(0x08) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_3 _u(0x09) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO6_STATUS +#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) +#define IO_BANK0_GPIO6_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO6_CTRL +#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) +#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> siob_proc_6 +// 0x06 -> pio0_6 +// 0x07 -> pio1_6 +// 0x08 -> pio2_6 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIOB_PROC_6 _u(0x05) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO2_6 _u(0x08) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO7_STATUS +#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) +#define IO_BANK0_GPIO7_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO7_CTRL +#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) +#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> siob_proc_7 +// 0x06 -> pio0_7 +// 0x07 -> pio1_7 +// 0x08 -> pio2_7 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIOB_PROC_7 _u(0x05) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO2_7 _u(0x08) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO8_STATUS +#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) +#define IO_BANK0_GPIO8_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO8_CTRL +#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) +#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> siob_proc_8 +// 0x06 -> pio0_8 +// 0x07 -> pio1_8 +// 0x08 -> pio2_8 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIOB_PROC_8 _u(0x05) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO2_8 _u(0x08) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO9_STATUS +#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) +#define IO_BANK0_GPIO9_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO9_CTRL +#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) +#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> siob_proc_9 +// 0x06 -> pio0_9 +// 0x07 -> pio1_9 +// 0x08 -> pio2_9 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIOB_PROC_9 _u(0x05) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO2_9 _u(0x08) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO10_STATUS +#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) +#define IO_BANK0_GPIO10_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO10_CTRL +#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) +#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> siob_proc_10 +// 0x06 -> pio0_10 +// 0x07 -> pio1_10 +// 0x08 -> pio2_10 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIOB_PROC_10 _u(0x05) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO2_10 _u(0x08) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO11_STATUS +#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) +#define IO_BANK0_GPIO11_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO11_CTRL +#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) +#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> siob_proc_11 +// 0x06 -> pio0_11 +// 0x07 -> pio1_11 +// 0x08 -> pio2_11 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIOB_PROC_11 _u(0x05) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO2_11 _u(0x08) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO12_STATUS +#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) +#define IO_BANK0_GPIO12_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO12_CTRL +#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) +#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_0 +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> siob_proc_12 +// 0x06 -> pio0_12 +// 0x07 -> pio1_12 +// 0x08 -> pio2_12 +// 0x09 -> clocks_gpin_0 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_HSTX_0 _u(0x00) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIOB_PROC_12 _u(0x05) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO2_12 _u(0x08) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO13_STATUS +#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) +#define IO_BANK0_GPIO13_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO13_CTRL +#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) +#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_1 +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> siob_proc_13 +// 0x06 -> pio0_13 +// 0x07 -> pio1_13 +// 0x08 -> pio2_13 +// 0x09 -> clocks_gpout_0 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_HSTX_1 _u(0x00) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIOB_PROC_13 _u(0x05) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO2_13 _u(0x08) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO14_STATUS +#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) +#define IO_BANK0_GPIO14_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO14_CTRL +#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) +#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_2 +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_7 +// 0x05 -> siob_proc_14 +// 0x06 -> pio0_14 +// 0x07 -> pio1_14 +// 0x08 -> pio2_14 +// 0x09 -> clocks_gpin_1 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_HSTX_2 _u(0x00) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIOB_PROC_14 _u(0x05) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO2_14 _u(0x08) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO15_STATUS +#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) +#define IO_BANK0_GPIO15_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO15_CTRL +#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) +#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_3 +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_7 +// 0x05 -> siob_proc_15 +// 0x06 -> pio0_15 +// 0x07 -> pio1_15 +// 0x08 -> pio2_15 +// 0x09 -> clocks_gpout_1 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_HSTX_3 _u(0x00) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIOB_PROC_15 _u(0x05) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO2_15 _u(0x08) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO16_STATUS +#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) +#define IO_BANK0_GPIO16_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO16_CTRL +#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) +#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_4 +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> siob_proc_16 +// 0x06 -> pio0_16 +// 0x07 -> pio1_16 +// 0x08 -> pio2_16 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_HSTX_4 _u(0x00) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIOB_PROC_16 _u(0x05) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO2_16 _u(0x08) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO17_STATUS +#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) +#define IO_BANK0_GPIO17_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO17_CTRL +#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) +#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_5 +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> siob_proc_17 +// 0x06 -> pio0_17 +// 0x07 -> pio1_17 +// 0x08 -> pio2_17 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_HSTX_5 _u(0x00) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIOB_PROC_17 _u(0x05) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO2_17 _u(0x08) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO18_STATUS +#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) +#define IO_BANK0_GPIO18_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO18_CTRL +#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) +#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_6 +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> siob_proc_18 +// 0x06 -> pio0_18 +// 0x07 -> pio1_18 +// 0x08 -> pio2_18 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_HSTX_6 _u(0x00) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIOB_PROC_18 _u(0x05) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO2_18 _u(0x08) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO19_STATUS +#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) +#define IO_BANK0_GPIO19_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO19_CTRL +#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) +#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_7 +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> siob_proc_19 +// 0x06 -> pio0_19 +// 0x07 -> pio1_19 +// 0x08 -> pio2_19 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_HSTX_7 _u(0x00) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIOB_PROC_19 _u(0x05) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO2_19 _u(0x08) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO20_STATUS +#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) +#define IO_BANK0_GPIO20_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO20_CTRL +#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) +#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> siob_proc_20 +// 0x06 -> pio0_20 +// 0x07 -> pio1_20 +// 0x08 -> pio2_20 +// 0x09 -> clocks_gpin_0 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIOB_PROC_20 _u(0x05) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO2_20 _u(0x08) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO21_STATUS +#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) +#define IO_BANK0_GPIO21_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO21_CTRL +#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) +#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> siob_proc_21 +// 0x06 -> pio0_21 +// 0x07 -> pio1_21 +// 0x08 -> pio2_21 +// 0x09 -> clocks_gpout_0 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIOB_PROC_21 _u(0x05) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO2_21 _u(0x08) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO22_STATUS +#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) +#define IO_BANK0_GPIO22_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO22_CTRL +#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) +#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> siob_proc_22 +// 0x06 -> pio0_22 +// 0x07 -> pio1_22 +// 0x08 -> pio2_22 +// 0x09 -> clocks_gpin_1 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIOB_PROC_22 _u(0x05) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO2_22 _u(0x08) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO23_STATUS +#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) +#define IO_BANK0_GPIO23_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO23_CTRL +#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) +#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> siob_proc_23 +// 0x06 -> pio0_23 +// 0x07 -> pio1_23 +// 0x08 -> pio2_23 +// 0x09 -> clocks_gpout_1 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIOB_PROC_23 _u(0x05) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO2_23 _u(0x08) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO24_STATUS +#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0) +#define IO_BANK0_GPIO24_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO24_CTRL +#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4) +#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> siob_proc_24 +// 0x06 -> pio0_24 +// 0x07 -> pio1_24 +// 0x08 -> pio2_24 +// 0x09 -> clocks_gpout_2 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIOB_PROC_24 _u(0x05) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO2_24 _u(0x08) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x09) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO25_STATUS +#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8) +#define IO_BANK0_GPIO25_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO25_CTRL +#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc) +#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> siob_proc_25 +// 0x06 -> pio0_25 +// 0x07 -> pio1_25 +// 0x08 -> pio2_25 +// 0x09 -> clocks_gpout_3 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIOB_PROC_25 _u(0x05) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO2_25 _u(0x08) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x09) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO26_STATUS +#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0) +#define IO_BANK0_GPIO26_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO26_CTRL +#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4) +#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> siob_proc_26 +// 0x06 -> pio0_26 +// 0x07 -> pio1_26 +// 0x08 -> pio2_26 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIOB_PROC_26 _u(0x05) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO2_26 _u(0x08) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO27_STATUS +#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8) +#define IO_BANK0_GPIO27_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO27_CTRL +#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc) +#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> siob_proc_27 +// 0x06 -> pio0_27 +// 0x07 -> pio1_27 +// 0x08 -> pio2_27 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIOB_PROC_27 _u(0x05) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO2_27 _u(0x08) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO28_STATUS +#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0) +#define IO_BANK0_GPIO28_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO28_CTRL +#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4) +#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> siob_proc_28 +// 0x06 -> pio0_28 +// 0x07 -> pio1_28 +// 0x08 -> pio2_28 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIOB_PROC_28 _u(0x05) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO2_28 _u(0x08) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO29_STATUS +#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8) +#define IO_BANK0_GPIO29_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO29_CTRL +#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec) +#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> siob_proc_29 +// 0x06 -> pio0_29 +// 0x07 -> pio1_29 +// 0x08 -> pio2_29 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIOB_PROC_29 _u(0x05) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO2_29 _u(0x08) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO30_STATUS +#define IO_BANK0_GPIO30_STATUS_OFFSET _u(0x000000f0) +#define IO_BANK0_GPIO30_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO30_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO30_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO30_CTRL +#define IO_BANK0_GPIO30_CTRL_OFFSET _u(0x000000f4) +#define IO_BANK0_GPIO30_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO30_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO30_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO30_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO30_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO30_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO30_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO30_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO30_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO30_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO30_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO30_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_7 +// 0x05 -> siob_proc_30 +// 0x06 -> pio0_30 +// 0x07 -> pio1_30 +// 0x08 -> pio2_30 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SIOB_PROC_30 _u(0x05) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO0_30 _u(0x06) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO1_30 _u(0x07) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO2_30 _u(0x08) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO31_STATUS +#define IO_BANK0_GPIO31_STATUS_OFFSET _u(0x000000f8) +#define IO_BANK0_GPIO31_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO31_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO31_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO31_CTRL +#define IO_BANK0_GPIO31_CTRL_OFFSET _u(0x000000fc) +#define IO_BANK0_GPIO31_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO31_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO31_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO31_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO31_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO31_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO31_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO31_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO31_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO31_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO31_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO31_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_7 +// 0x05 -> siob_proc_31 +// 0x06 -> pio0_31 +// 0x07 -> pio1_31 +// 0x08 -> pio2_31 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SIOB_PROC_31 _u(0x05) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO0_31 _u(0x06) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO1_31 _u(0x07) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO2_31 _u(0x08) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO32_STATUS +#define IO_BANK0_GPIO32_STATUS_OFFSET _u(0x00000100) +#define IO_BANK0_GPIO32_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO32_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO32_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO32_CTRL +#define IO_BANK0_GPIO32_CTRL_OFFSET _u(0x00000104) +#define IO_BANK0_GPIO32_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO32_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO32_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO32_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO32_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO32_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO32_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO32_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO32_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO32_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO32_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO32_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_8 +// 0x05 -> siob_proc_32 +// 0x06 -> pio0_32 +// 0x07 -> pio1_32 +// 0x08 -> pio2_32 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SIOB_PROC_32 _u(0x05) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO0_32 _u(0x06) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO1_32 _u(0x07) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO2_32 _u(0x08) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO33_STATUS +#define IO_BANK0_GPIO33_STATUS_OFFSET _u(0x00000108) +#define IO_BANK0_GPIO33_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO33_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO33_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO33_CTRL +#define IO_BANK0_GPIO33_CTRL_OFFSET _u(0x0000010c) +#define IO_BANK0_GPIO33_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO33_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO33_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO33_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO33_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO33_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO33_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO33_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO33_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO33_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO33_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO33_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_8 +// 0x05 -> siob_proc_33 +// 0x06 -> pio0_33 +// 0x07 -> pio1_33 +// 0x08 -> pio2_33 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SIOB_PROC_33 _u(0x05) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO0_33 _u(0x06) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO1_33 _u(0x07) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO2_33 _u(0x08) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO34_STATUS +#define IO_BANK0_GPIO34_STATUS_OFFSET _u(0x00000110) +#define IO_BANK0_GPIO34_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO34_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO34_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO34_CTRL +#define IO_BANK0_GPIO34_CTRL_OFFSET _u(0x00000114) +#define IO_BANK0_GPIO34_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO34_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO34_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO34_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO34_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO34_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO34_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO34_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO34_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO34_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO34_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO34_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_9 +// 0x05 -> siob_proc_34 +// 0x06 -> pio0_34 +// 0x07 -> pio1_34 +// 0x08 -> pio2_34 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SIOB_PROC_34 _u(0x05) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO0_34 _u(0x06) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO1_34 _u(0x07) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO2_34 _u(0x08) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO35_STATUS +#define IO_BANK0_GPIO35_STATUS_OFFSET _u(0x00000118) +#define IO_BANK0_GPIO35_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO35_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO35_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO35_CTRL +#define IO_BANK0_GPIO35_CTRL_OFFSET _u(0x0000011c) +#define IO_BANK0_GPIO35_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO35_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO35_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO35_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO35_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO35_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO35_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO35_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO35_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO35_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO35_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO35_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_9 +// 0x05 -> siob_proc_35 +// 0x06 -> pio0_35 +// 0x07 -> pio1_35 +// 0x08 -> pio2_35 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SIOB_PROC_35 _u(0x05) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO0_35 _u(0x06) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO1_35 _u(0x07) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO2_35 _u(0x08) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO36_STATUS +#define IO_BANK0_GPIO36_STATUS_OFFSET _u(0x00000120) +#define IO_BANK0_GPIO36_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO36_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO36_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO36_CTRL +#define IO_BANK0_GPIO36_CTRL_OFFSET _u(0x00000124) +#define IO_BANK0_GPIO36_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO36_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO36_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO36_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO36_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO36_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO36_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO36_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO36_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO36_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO36_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO36_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_10 +// 0x05 -> siob_proc_36 +// 0x06 -> pio0_36 +// 0x07 -> pio1_36 +// 0x08 -> pio2_36 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SIOB_PROC_36 _u(0x05) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO0_36 _u(0x06) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO1_36 _u(0x07) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO2_36 _u(0x08) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO37_STATUS +#define IO_BANK0_GPIO37_STATUS_OFFSET _u(0x00000128) +#define IO_BANK0_GPIO37_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO37_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO37_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO37_CTRL +#define IO_BANK0_GPIO37_CTRL_OFFSET _u(0x0000012c) +#define IO_BANK0_GPIO37_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO37_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO37_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO37_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO37_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO37_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO37_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO37_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO37_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO37_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO37_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO37_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_10 +// 0x05 -> siob_proc_37 +// 0x06 -> pio0_37 +// 0x07 -> pio1_37 +// 0x08 -> pio2_37 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SIOB_PROC_37 _u(0x05) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO0_37 _u(0x06) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO1_37 _u(0x07) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO2_37 _u(0x08) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO38_STATUS +#define IO_BANK0_GPIO38_STATUS_OFFSET _u(0x00000130) +#define IO_BANK0_GPIO38_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO38_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO38_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO38_CTRL +#define IO_BANK0_GPIO38_CTRL_OFFSET _u(0x00000134) +#define IO_BANK0_GPIO38_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO38_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO38_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO38_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO38_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO38_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO38_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO38_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO38_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO38_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO38_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO38_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_11 +// 0x05 -> siob_proc_38 +// 0x06 -> pio0_38 +// 0x07 -> pio1_38 +// 0x08 -> pio2_38 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SIOB_PROC_38 _u(0x05) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO0_38 _u(0x06) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO1_38 _u(0x07) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO2_38 _u(0x08) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO39_STATUS +#define IO_BANK0_GPIO39_STATUS_OFFSET _u(0x00000138) +#define IO_BANK0_GPIO39_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO39_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO39_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO39_CTRL +#define IO_BANK0_GPIO39_CTRL_OFFSET _u(0x0000013c) +#define IO_BANK0_GPIO39_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO39_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO39_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO39_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO39_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO39_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO39_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO39_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO39_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO39_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO39_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO39_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_11 +// 0x05 -> siob_proc_39 +// 0x06 -> pio0_39 +// 0x07 -> pio1_39 +// 0x08 -> pio2_39 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SIOB_PROC_39 _u(0x05) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO0_39 _u(0x06) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO1_39 _u(0x07) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO2_39 _u(0x08) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO40_STATUS +#define IO_BANK0_GPIO40_STATUS_OFFSET _u(0x00000140) +#define IO_BANK0_GPIO40_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO40_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO40_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO40_CTRL +#define IO_BANK0_GPIO40_CTRL_OFFSET _u(0x00000144) +#define IO_BANK0_GPIO40_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO40_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO40_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO40_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO40_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO40_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO40_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO40_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO40_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO40_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO40_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO40_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_8 +// 0x05 -> siob_proc_40 +// 0x06 -> pio0_40 +// 0x07 -> pio1_40 +// 0x08 -> pio2_40 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SIOB_PROC_40 _u(0x05) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO0_40 _u(0x06) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO1_40 _u(0x07) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO2_40 _u(0x08) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO41_STATUS +#define IO_BANK0_GPIO41_STATUS_OFFSET _u(0x00000148) +#define IO_BANK0_GPIO41_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO41_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO41_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO41_CTRL +#define IO_BANK0_GPIO41_CTRL_OFFSET _u(0x0000014c) +#define IO_BANK0_GPIO41_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO41_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO41_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO41_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO41_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO41_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO41_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO41_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO41_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO41_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO41_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO41_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_8 +// 0x05 -> siob_proc_41 +// 0x06 -> pio0_41 +// 0x07 -> pio1_41 +// 0x08 -> pio2_41 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SIOB_PROC_41 _u(0x05) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO0_41 _u(0x06) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO1_41 _u(0x07) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO2_41 _u(0x08) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO42_STATUS +#define IO_BANK0_GPIO42_STATUS_OFFSET _u(0x00000150) +#define IO_BANK0_GPIO42_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO42_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO42_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO42_CTRL +#define IO_BANK0_GPIO42_CTRL_OFFSET _u(0x00000154) +#define IO_BANK0_GPIO42_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO42_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO42_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO42_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO42_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO42_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO42_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO42_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO42_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO42_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO42_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO42_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_9 +// 0x05 -> siob_proc_42 +// 0x06 -> pio0_42 +// 0x07 -> pio1_42 +// 0x08 -> pio2_42 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SIOB_PROC_42 _u(0x05) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO0_42 _u(0x06) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO1_42 _u(0x07) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO2_42 _u(0x08) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO43_STATUS +#define IO_BANK0_GPIO43_STATUS_OFFSET _u(0x00000158) +#define IO_BANK0_GPIO43_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO43_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO43_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO43_CTRL +#define IO_BANK0_GPIO43_CTRL_OFFSET _u(0x0000015c) +#define IO_BANK0_GPIO43_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO43_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO43_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO43_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO43_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO43_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO43_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO43_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO43_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO43_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO43_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO43_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_9 +// 0x05 -> siob_proc_43 +// 0x06 -> pio0_43 +// 0x07 -> pio1_43 +// 0x08 -> pio2_43 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SIOB_PROC_43 _u(0x05) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO0_43 _u(0x06) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO1_43 _u(0x07) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO2_43 _u(0x08) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO44_STATUS +#define IO_BANK0_GPIO44_STATUS_OFFSET _u(0x00000160) +#define IO_BANK0_GPIO44_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO44_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO44_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO44_CTRL +#define IO_BANK0_GPIO44_CTRL_OFFSET _u(0x00000164) +#define IO_BANK0_GPIO44_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO44_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO44_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO44_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO44_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO44_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO44_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO44_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO44_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO44_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO44_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO44_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_10 +// 0x05 -> siob_proc_44 +// 0x06 -> pio0_44 +// 0x07 -> pio1_44 +// 0x08 -> pio2_44 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SIOB_PROC_44 _u(0x05) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO0_44 _u(0x06) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO1_44 _u(0x07) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO2_44 _u(0x08) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO45_STATUS +#define IO_BANK0_GPIO45_STATUS_OFFSET _u(0x00000168) +#define IO_BANK0_GPIO45_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO45_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO45_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO45_CTRL +#define IO_BANK0_GPIO45_CTRL_OFFSET _u(0x0000016c) +#define IO_BANK0_GPIO45_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO45_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO45_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO45_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO45_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO45_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO45_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO45_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO45_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO45_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO45_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO45_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_10 +// 0x05 -> siob_proc_45 +// 0x06 -> pio0_45 +// 0x07 -> pio1_45 +// 0x08 -> pio2_45 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SIOB_PROC_45 _u(0x05) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO0_45 _u(0x06) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO1_45 _u(0x07) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO2_45 _u(0x08) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO46_STATUS +#define IO_BANK0_GPIO46_STATUS_OFFSET _u(0x00000170) +#define IO_BANK0_GPIO46_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO46_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO46_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO46_CTRL +#define IO_BANK0_GPIO46_CTRL_OFFSET _u(0x00000174) +#define IO_BANK0_GPIO46_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO46_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO46_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO46_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO46_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO46_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO46_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO46_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO46_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO46_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO46_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO46_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_11 +// 0x05 -> siob_proc_46 +// 0x06 -> pio0_46 +// 0x07 -> pio1_46 +// 0x08 -> pio2_46 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SIOB_PROC_46 _u(0x05) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO0_46 _u(0x06) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO1_46 _u(0x07) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO2_46 _u(0x08) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO47_STATUS +#define IO_BANK0_GPIO47_STATUS_OFFSET _u(0x00000178) +#define IO_BANK0_GPIO47_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO47_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO47_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO47_CTRL +#define IO_BANK0_GPIO47_CTRL_OFFSET _u(0x0000017c) +#define IO_BANK0_GPIO47_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO47_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO47_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO47_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO47_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO47_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO47_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO47_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO47_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO47_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO47_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO47_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_11 +// 0x05 -> siob_proc_47 +// 0x06 -> pio0_47 +// 0x07 -> pio1_47 +// 0x08 -> pio2_47 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SIOB_PROC_47 _u(0x05) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO0_47 _u(0x06) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO1_47 _u(0x07) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO2_47 _u(0x08) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE0 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE1 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_OFFSET _u(0x00000204) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET _u(0x00000208) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_OFFSET _u(0x0000020c) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE0 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET _u(0x00000210) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE1 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_OFFSET _u(0x00000214) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET _u(0x00000218) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_OFFSET _u(0x0000021c) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET _u(0x00000220) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_OFFSET _u(0x00000224) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET _u(0x00000228) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_OFFSET _u(0x0000022c) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR0 +// Description : Raw Interrupts +#define IO_BANK0_INTR0_OFFSET _u(0x00000230) +#define IO_BANK0_INTR0_BITS _u(0xffffffff) +#define IO_BANK0_INTR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR1 +// Description : Raw Interrupts +#define IO_BANK0_INTR1_OFFSET _u(0x00000234) +#define IO_BANK0_INTR1_BITS _u(0xffffffff) +#define IO_BANK0_INTR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR2 +// Description : Raw Interrupts +#define IO_BANK0_INTR2_OFFSET _u(0x00000238) +#define IO_BANK0_INTR2_BITS _u(0xffffffff) +#define IO_BANK0_INTR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR3 +// Description : Raw Interrupts +#define IO_BANK0_INTR3_OFFSET _u(0x0000023c) +#define IO_BANK0_INTR3_BITS _u(0xffffffff) +#define IO_BANK0_INTR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_EDGE_LOW +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_EDGE_LOW +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR4 +// Description : Raw Interrupts +#define IO_BANK0_INTR4_OFFSET _u(0x00000240) +#define IO_BANK0_INTR4_BITS _u(0xffffffff) +#define IO_BANK0_INTR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_EDGE_LOW +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_EDGE_LOW +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_EDGE_LOW +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_EDGE_LOW +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_EDGE_LOW +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_EDGE_LOW +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_EDGE_LOW +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_EDGE_LOW +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR5 +// Description : Raw Interrupts +#define IO_BANK0_INTR5_OFFSET _u(0x00000244) +#define IO_BANK0_INTR5_BITS _u(0xffffffff) +#define IO_BANK0_INTR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_EDGE_LOW +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_EDGE_LOW +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_EDGE_LOW +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_EDGE_LOW +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_EDGE_LOW +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_EDGE_LOW +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_EDGE_LOW +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_EDGE_LOW +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE0 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000248) +#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE1 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x0000024c) +#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE2 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000250) +#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE3 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x00000254) +#define IO_BANK0_PROC0_INTE3_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE4 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE4_OFFSET _u(0x00000258) +#define IO_BANK0_PROC0_INTE4_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE5 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE5_OFFSET _u(0x0000025c) +#define IO_BANK0_PROC0_INTE5_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF0 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000260) +#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF1 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000264) +#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF2 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000268) +#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF3 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000026c) +#define IO_BANK0_PROC0_INTF3_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF4 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF4_OFFSET _u(0x00000270) +#define IO_BANK0_PROC0_INTF4_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF5 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF5_OFFSET _u(0x00000274) +#define IO_BANK0_PROC0_INTF5_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS0 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000278) +#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS1 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x0000027c) +#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS2 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000280) +#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS3 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x00000284) +#define IO_BANK0_PROC0_INTS3_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS4 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS4_OFFSET _u(0x00000288) +#define IO_BANK0_PROC0_INTS4_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS5 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS5_OFFSET _u(0x0000028c) +#define IO_BANK0_PROC0_INTS5_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE0 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000290) +#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE1 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000294) +#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE2 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000298) +#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE3 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000029c) +#define IO_BANK0_PROC1_INTE3_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE4 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE4_OFFSET _u(0x000002a0) +#define IO_BANK0_PROC1_INTE4_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE5 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE5_OFFSET _u(0x000002a4) +#define IO_BANK0_PROC1_INTE5_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF0 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x000002a8) +#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF1 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x000002ac) +#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF2 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x000002b0) +#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF3 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x000002b4) +#define IO_BANK0_PROC1_INTF3_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF4 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF4_OFFSET _u(0x000002b8) +#define IO_BANK0_PROC1_INTF4_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF5 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF5_OFFSET _u(0x000002bc) +#define IO_BANK0_PROC1_INTF5_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS0 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x000002c0) +#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS1 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x000002c4) +#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS2 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x000002c8) +#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS3 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x000002cc) +#define IO_BANK0_PROC1_INTS3_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS4 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS4_OFFSET _u(0x000002d0) +#define IO_BANK0_PROC1_INTS4_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS5 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS5_OFFSET _u(0x000002d4) +#define IO_BANK0_PROC1_INTS5_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE0 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x000002d8) +#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE1 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x000002dc) +#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE2 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x000002e0) +#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE3 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x000002e4) +#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE4 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE4_OFFSET _u(0x000002e8) +#define IO_BANK0_DORMANT_WAKE_INTE4_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE5 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE5_OFFSET _u(0x000002ec) +#define IO_BANK0_DORMANT_WAKE_INTE5_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF0 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x000002f0) +#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF1 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x000002f4) +#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF2 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x000002f8) +#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF3 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x000002fc) +#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF4 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF4_OFFSET _u(0x00000300) +#define IO_BANK0_DORMANT_WAKE_INTF4_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF5 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF5_OFFSET _u(0x00000304) +#define IO_BANK0_DORMANT_WAKE_INTF5_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS0 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000308) +#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS1 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x0000030c) +#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS2 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000310) +#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS3 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x00000314) +#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS4 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS4_OFFSET _u(0x00000318) +#define IO_BANK0_DORMANT_WAKE_INTS4_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS5 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS5_OFFSET _u(0x0000031c) +#define IO_BANK0_DORMANT_WAKE_INTS5_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_IO_BANK0_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h b/src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h new file mode 100644 index 000000000..668105264 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/io_qspi.h @@ -0,0 +1,3663 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_QSPI +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_IO_QSPI_H +#define _HARDWARE_REGS_IO_QSPI_H +// ============================================================================= +// Register : IO_QSPI_USBPHY_DP_STATUS +#define IO_QSPI_USBPHY_DP_STATUS_OFFSET _u(0x00000000) +#define IO_QSPI_USBPHY_DP_STATUS_BITS _u(0x04022200) +#define IO_QSPI_USBPHY_DP_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_USBPHY_DP_CTRL +#define IO_QSPI_USBPHY_DP_CTRL_OFFSET _u(0x00000004) +#define IO_QSPI_USBPHY_DP_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_USBPHY_DP_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x05 -> siob_proc_56 +// 0x1f -> null +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_SIOB_PROC_56 _u(0x05) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_USBPHY_DM_STATUS +#define IO_QSPI_USBPHY_DM_STATUS_OFFSET _u(0x00000008) +#define IO_QSPI_USBPHY_DM_STATUS_BITS _u(0x04022200) +#define IO_QSPI_USBPHY_DM_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_USBPHY_DM_CTRL +#define IO_QSPI_USBPHY_DM_CTRL_OFFSET _u(0x0000000c) +#define IO_QSPI_USBPHY_DM_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_USBPHY_DM_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x05 -> siob_proc_57 +// 0x1f -> null +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_SIOB_PROC_57 _u(0x05) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000010) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000014) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x05 -> siob_proc_58 +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIOB_PROC_58 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_STATUS +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000018) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_CTRL +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000001c) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_ss_n_0 +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x05 -> siob_proc_59 +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N_0 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIOB_PROC_59 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000020) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000024) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd0 +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x05 -> siob_proc_60 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIOB_PROC_60 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000028) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000002c) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd1 +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x05 -> siob_proc_61 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIOB_PROC_61 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000030) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000034) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd2 +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x05 -> siob_proc_62 +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIOB_PROC_62 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000038) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000003c) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd3 +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x05 -> siob_proc_63 +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIOB_PROC_63 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC0_SECURE +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET _u(0x00000200) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET _u(0x00000204) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC1_SECURE +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET _u(0x00000208) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET _u(0x0000020c) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET _u(0x00000210) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET _u(0x00000214) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_INTR +// Description : Raw Interrupts +#define IO_QSPI_INTR_OFFSET _u(0x00000218) +#define IO_QSPI_INTR_BITS _u(0xffffffff) +#define IO_QSPI_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_EDGE_LOW +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_EDGE_LOW +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTE +// Description : Interrupt Enable for proc0 +#define IO_QSPI_PROC0_INTE_OFFSET _u(0x0000021c) +#define IO_QSPI_PROC0_INTE_BITS _u(0xffffffff) +#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTF +// Description : Interrupt Force for proc0 +#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000220) +#define IO_QSPI_PROC0_INTF_BITS _u(0xffffffff) +#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTS +// Description : Interrupt status after masking & forcing for proc0 +#define IO_QSPI_PROC0_INTS_OFFSET _u(0x00000224) +#define IO_QSPI_PROC0_INTS_BITS _u(0xffffffff) +#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTE +// Description : Interrupt Enable for proc1 +#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000228) +#define IO_QSPI_PROC1_INTE_BITS _u(0xffffffff) +#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTF +// Description : Interrupt Force for proc1 +#define IO_QSPI_PROC1_INTF_OFFSET _u(0x0000022c) +#define IO_QSPI_PROC1_INTF_BITS _u(0xffffffff) +#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTS +// Description : Interrupt status after masking & forcing for proc1 +#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000230) +#define IO_QSPI_PROC1_INTS_BITS _u(0xffffffff) +#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTE +// Description : Interrupt Enable for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x00000234) +#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0xffffffff) +#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTF +// Description : Interrupt Force for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000238) +#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0xffffffff) +#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTS +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x0000023c) +#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0xffffffff) +#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_IO_QSPI_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/m33.h b/src/rp2350/hardware_regs/include/hardware/regs/m33.h new file mode 100644 index 000000000..b555317de --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/m33.h @@ -0,0 +1,8988 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : M33 +// Version : 1 +// Bus type : apb +// Description : TEAL registers accessible through the debug interface +// ============================================================================= +#ifndef _HARDWARE_REGS_M33_H +#define _HARDWARE_REGS_M33_H +// ============================================================================= +// Register : M33_ITM_STIM0 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM0_OFFSET _u(0x00000000) +#define M33_ITM_STIM0_BITS _u(0xffffffff) +#define M33_ITM_STIM0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM0_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM0_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM0_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM0_STIMULUS_MSB _u(31) +#define M33_ITM_STIM0_STIMULUS_LSB _u(0) +#define M33_ITM_STIM0_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM1 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM1_OFFSET _u(0x00000004) +#define M33_ITM_STIM1_BITS _u(0xffffffff) +#define M33_ITM_STIM1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM1_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM1_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM1_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM1_STIMULUS_MSB _u(31) +#define M33_ITM_STIM1_STIMULUS_LSB _u(0) +#define M33_ITM_STIM1_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM2 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM2_OFFSET _u(0x00000008) +#define M33_ITM_STIM2_BITS _u(0xffffffff) +#define M33_ITM_STIM2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM2_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM2_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM2_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM2_STIMULUS_MSB _u(31) +#define M33_ITM_STIM2_STIMULUS_LSB _u(0) +#define M33_ITM_STIM2_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM3 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM3_OFFSET _u(0x0000000c) +#define M33_ITM_STIM3_BITS _u(0xffffffff) +#define M33_ITM_STIM3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM3_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM3_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM3_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM3_STIMULUS_MSB _u(31) +#define M33_ITM_STIM3_STIMULUS_LSB _u(0) +#define M33_ITM_STIM3_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM4 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM4_OFFSET _u(0x00000010) +#define M33_ITM_STIM4_BITS _u(0xffffffff) +#define M33_ITM_STIM4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM4_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM4_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM4_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM4_STIMULUS_MSB _u(31) +#define M33_ITM_STIM4_STIMULUS_LSB _u(0) +#define M33_ITM_STIM4_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM5 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM5_OFFSET _u(0x00000014) +#define M33_ITM_STIM5_BITS _u(0xffffffff) +#define M33_ITM_STIM5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM5_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM5_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM5_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM5_STIMULUS_MSB _u(31) +#define M33_ITM_STIM5_STIMULUS_LSB _u(0) +#define M33_ITM_STIM5_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM6 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM6_OFFSET _u(0x00000018) +#define M33_ITM_STIM6_BITS _u(0xffffffff) +#define M33_ITM_STIM6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM6_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM6_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM6_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM6_STIMULUS_MSB _u(31) +#define M33_ITM_STIM6_STIMULUS_LSB _u(0) +#define M33_ITM_STIM6_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM7 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM7_OFFSET _u(0x0000001c) +#define M33_ITM_STIM7_BITS _u(0xffffffff) +#define M33_ITM_STIM7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM7_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM7_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM7_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM7_STIMULUS_MSB _u(31) +#define M33_ITM_STIM7_STIMULUS_LSB _u(0) +#define M33_ITM_STIM7_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM8 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM8_OFFSET _u(0x00000020) +#define M33_ITM_STIM8_BITS _u(0xffffffff) +#define M33_ITM_STIM8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM8_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM8_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM8_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM8_STIMULUS_MSB _u(31) +#define M33_ITM_STIM8_STIMULUS_LSB _u(0) +#define M33_ITM_STIM8_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM9 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM9_OFFSET _u(0x00000024) +#define M33_ITM_STIM9_BITS _u(0xffffffff) +#define M33_ITM_STIM9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM9_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM9_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM9_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM9_STIMULUS_MSB _u(31) +#define M33_ITM_STIM9_STIMULUS_LSB _u(0) +#define M33_ITM_STIM9_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM10 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM10_OFFSET _u(0x00000028) +#define M33_ITM_STIM10_BITS _u(0xffffffff) +#define M33_ITM_STIM10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM10_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM10_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM10_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM10_STIMULUS_MSB _u(31) +#define M33_ITM_STIM10_STIMULUS_LSB _u(0) +#define M33_ITM_STIM10_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM11 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM11_OFFSET _u(0x0000002c) +#define M33_ITM_STIM11_BITS _u(0xffffffff) +#define M33_ITM_STIM11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM11_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM11_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM11_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM11_STIMULUS_MSB _u(31) +#define M33_ITM_STIM11_STIMULUS_LSB _u(0) +#define M33_ITM_STIM11_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM12 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM12_OFFSET _u(0x00000030) +#define M33_ITM_STIM12_BITS _u(0xffffffff) +#define M33_ITM_STIM12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM12_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM12_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM12_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM12_STIMULUS_MSB _u(31) +#define M33_ITM_STIM12_STIMULUS_LSB _u(0) +#define M33_ITM_STIM12_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM13 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM13_OFFSET _u(0x00000034) +#define M33_ITM_STIM13_BITS _u(0xffffffff) +#define M33_ITM_STIM13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM13_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM13_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM13_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM13_STIMULUS_MSB _u(31) +#define M33_ITM_STIM13_STIMULUS_LSB _u(0) +#define M33_ITM_STIM13_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM14 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM14_OFFSET _u(0x00000038) +#define M33_ITM_STIM14_BITS _u(0xffffffff) +#define M33_ITM_STIM14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM14_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM14_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM14_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM14_STIMULUS_MSB _u(31) +#define M33_ITM_STIM14_STIMULUS_LSB _u(0) +#define M33_ITM_STIM14_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM15 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM15_OFFSET _u(0x0000003c) +#define M33_ITM_STIM15_BITS _u(0xffffffff) +#define M33_ITM_STIM15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM15_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM15_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM15_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM15_STIMULUS_MSB _u(31) +#define M33_ITM_STIM15_STIMULUS_LSB _u(0) +#define M33_ITM_STIM15_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM16 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM16_OFFSET _u(0x00000040) +#define M33_ITM_STIM16_BITS _u(0xffffffff) +#define M33_ITM_STIM16_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM16_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM16_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM16_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM16_STIMULUS_MSB _u(31) +#define M33_ITM_STIM16_STIMULUS_LSB _u(0) +#define M33_ITM_STIM16_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM17 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM17_OFFSET _u(0x00000044) +#define M33_ITM_STIM17_BITS _u(0xffffffff) +#define M33_ITM_STIM17_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM17_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM17_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM17_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM17_STIMULUS_MSB _u(31) +#define M33_ITM_STIM17_STIMULUS_LSB _u(0) +#define M33_ITM_STIM17_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM18 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM18_OFFSET _u(0x00000048) +#define M33_ITM_STIM18_BITS _u(0xffffffff) +#define M33_ITM_STIM18_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM18_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM18_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM18_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM18_STIMULUS_MSB _u(31) +#define M33_ITM_STIM18_STIMULUS_LSB _u(0) +#define M33_ITM_STIM18_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM19 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM19_OFFSET _u(0x0000004c) +#define M33_ITM_STIM19_BITS _u(0xffffffff) +#define M33_ITM_STIM19_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM19_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM19_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM19_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM19_STIMULUS_MSB _u(31) +#define M33_ITM_STIM19_STIMULUS_LSB _u(0) +#define M33_ITM_STIM19_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM20 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM20_OFFSET _u(0x00000050) +#define M33_ITM_STIM20_BITS _u(0xffffffff) +#define M33_ITM_STIM20_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM20_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM20_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM20_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM20_STIMULUS_MSB _u(31) +#define M33_ITM_STIM20_STIMULUS_LSB _u(0) +#define M33_ITM_STIM20_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM21 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM21_OFFSET _u(0x00000054) +#define M33_ITM_STIM21_BITS _u(0xffffffff) +#define M33_ITM_STIM21_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM21_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM21_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM21_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM21_STIMULUS_MSB _u(31) +#define M33_ITM_STIM21_STIMULUS_LSB _u(0) +#define M33_ITM_STIM21_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM22 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM22_OFFSET _u(0x00000058) +#define M33_ITM_STIM22_BITS _u(0xffffffff) +#define M33_ITM_STIM22_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM22_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM22_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM22_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM22_STIMULUS_MSB _u(31) +#define M33_ITM_STIM22_STIMULUS_LSB _u(0) +#define M33_ITM_STIM22_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM23 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM23_OFFSET _u(0x0000005c) +#define M33_ITM_STIM23_BITS _u(0xffffffff) +#define M33_ITM_STIM23_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM23_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM23_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM23_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM23_STIMULUS_MSB _u(31) +#define M33_ITM_STIM23_STIMULUS_LSB _u(0) +#define M33_ITM_STIM23_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM24 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM24_OFFSET _u(0x00000060) +#define M33_ITM_STIM24_BITS _u(0xffffffff) +#define M33_ITM_STIM24_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM24_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM24_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM24_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM24_STIMULUS_MSB _u(31) +#define M33_ITM_STIM24_STIMULUS_LSB _u(0) +#define M33_ITM_STIM24_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM25 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM25_OFFSET _u(0x00000064) +#define M33_ITM_STIM25_BITS _u(0xffffffff) +#define M33_ITM_STIM25_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM25_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM25_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM25_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM25_STIMULUS_MSB _u(31) +#define M33_ITM_STIM25_STIMULUS_LSB _u(0) +#define M33_ITM_STIM25_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM26 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM26_OFFSET _u(0x00000068) +#define M33_ITM_STIM26_BITS _u(0xffffffff) +#define M33_ITM_STIM26_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM26_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM26_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM26_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM26_STIMULUS_MSB _u(31) +#define M33_ITM_STIM26_STIMULUS_LSB _u(0) +#define M33_ITM_STIM26_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM27 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM27_OFFSET _u(0x0000006c) +#define M33_ITM_STIM27_BITS _u(0xffffffff) +#define M33_ITM_STIM27_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM27_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM27_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM27_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM27_STIMULUS_MSB _u(31) +#define M33_ITM_STIM27_STIMULUS_LSB _u(0) +#define M33_ITM_STIM27_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM28 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM28_OFFSET _u(0x00000070) +#define M33_ITM_STIM28_BITS _u(0xffffffff) +#define M33_ITM_STIM28_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM28_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM28_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM28_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM28_STIMULUS_MSB _u(31) +#define M33_ITM_STIM28_STIMULUS_LSB _u(0) +#define M33_ITM_STIM28_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM29 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM29_OFFSET _u(0x00000074) +#define M33_ITM_STIM29_BITS _u(0xffffffff) +#define M33_ITM_STIM29_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM29_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM29_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM29_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM29_STIMULUS_MSB _u(31) +#define M33_ITM_STIM29_STIMULUS_LSB _u(0) +#define M33_ITM_STIM29_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM30 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM30_OFFSET _u(0x00000078) +#define M33_ITM_STIM30_BITS _u(0xffffffff) +#define M33_ITM_STIM30_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM30_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM30_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM30_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM30_STIMULUS_MSB _u(31) +#define M33_ITM_STIM30_STIMULUS_LSB _u(0) +#define M33_ITM_STIM30_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM31 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM31_OFFSET _u(0x0000007c) +#define M33_ITM_STIM31_BITS _u(0xffffffff) +#define M33_ITM_STIM31_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM31_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM31_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM31_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM31_STIMULUS_MSB _u(31) +#define M33_ITM_STIM31_STIMULUS_LSB _u(0) +#define M33_ITM_STIM31_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_TER0 +// Description : Provide an individual enable bit for each ITM_STIM register +#define M33_ITM_TER0_OFFSET _u(0x00000e00) +#define M33_ITM_TER0_BITS _u(0xffffffff) +#define M33_ITM_TER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TER0_STIMENA +// Description : For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + +// m) is enabled +#define M33_ITM_TER0_STIMENA_RESET _u(0x00000000) +#define M33_ITM_TER0_STIMENA_BITS _u(0xffffffff) +#define M33_ITM_TER0_STIMENA_MSB _u(31) +#define M33_ITM_TER0_STIMENA_LSB _u(0) +#define M33_ITM_TER0_STIMENA_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_TPR +// Description : Controls which stimulus ports can be accessed by unprivileged +// code +#define M33_ITM_TPR_OFFSET _u(0x00000e40) +#define M33_ITM_TPR_BITS _u(0x0000000f) +#define M33_ITM_TPR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TPR_PRIVMASK +// Description : Bit mask to enable tracing on ITM stimulus ports +#define M33_ITM_TPR_PRIVMASK_RESET _u(0x0) +#define M33_ITM_TPR_PRIVMASK_BITS _u(0x0000000f) +#define M33_ITM_TPR_PRIVMASK_MSB _u(3) +#define M33_ITM_TPR_PRIVMASK_LSB _u(0) +#define M33_ITM_TPR_PRIVMASK_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_TCR +// Description : Configures and controls transfers through the ITM interface +#define M33_ITM_TCR_OFFSET _u(0x00000e80) +#define M33_ITM_TCR_BITS _u(0x00ff0f3f) +#define M33_ITM_TCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_BUSY +// Description : Indicates whether the ITM is currently processing events +#define M33_ITM_TCR_BUSY_RESET _u(0x0) +#define M33_ITM_TCR_BUSY_BITS _u(0x00800000) +#define M33_ITM_TCR_BUSY_MSB _u(23) +#define M33_ITM_TCR_BUSY_LSB _u(23) +#define M33_ITM_TCR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TRACEBUSID +// Description : Identifier for multi-source trace stream formatting. If multi- +// source trace is in use, the debugger must write a unique non- +// zero trace ID value to this field +#define M33_ITM_TCR_TRACEBUSID_RESET _u(0x00) +#define M33_ITM_TCR_TRACEBUSID_BITS _u(0x007f0000) +#define M33_ITM_TCR_TRACEBUSID_MSB _u(22) +#define M33_ITM_TCR_TRACEBUSID_LSB _u(16) +#define M33_ITM_TCR_TRACEBUSID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_GTSFREQ +// Description : Defines how often the ITM generates a global timestamp, based +// on the global timestamp clock frequency, or disables generation +// of global timestamps +#define M33_ITM_TCR_GTSFREQ_RESET _u(0x0) +#define M33_ITM_TCR_GTSFREQ_BITS _u(0x00000c00) +#define M33_ITM_TCR_GTSFREQ_MSB _u(11) +#define M33_ITM_TCR_GTSFREQ_LSB _u(10) +#define M33_ITM_TCR_GTSFREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TSPRESCALE +// Description : Local timestamp prescaler, used with the trace packet reference +// clock +#define M33_ITM_TCR_TSPRESCALE_RESET _u(0x0) +#define M33_ITM_TCR_TSPRESCALE_BITS _u(0x00000300) +#define M33_ITM_TCR_TSPRESCALE_MSB _u(9) +#define M33_ITM_TCR_TSPRESCALE_LSB _u(8) +#define M33_ITM_TCR_TSPRESCALE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_STALLENA +// Description : Stall the PE to guarantee delivery of Data Trace packets. +#define M33_ITM_TCR_STALLENA_RESET _u(0x0) +#define M33_ITM_TCR_STALLENA_BITS _u(0x00000020) +#define M33_ITM_TCR_STALLENA_MSB _u(5) +#define M33_ITM_TCR_STALLENA_LSB _u(5) +#define M33_ITM_TCR_STALLENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_SWOENA +// Description : Enables asynchronous clocking of the timestamp counter +#define M33_ITM_TCR_SWOENA_RESET _u(0x0) +#define M33_ITM_TCR_SWOENA_BITS _u(0x00000010) +#define M33_ITM_TCR_SWOENA_MSB _u(4) +#define M33_ITM_TCR_SWOENA_LSB _u(4) +#define M33_ITM_TCR_SWOENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TXENA +// Description : Enables forwarding of hardware event packet from the DWT unit +// to the ITM for output to the TPIU +#define M33_ITM_TCR_TXENA_RESET _u(0x0) +#define M33_ITM_TCR_TXENA_BITS _u(0x00000008) +#define M33_ITM_TCR_TXENA_MSB _u(3) +#define M33_ITM_TCR_TXENA_LSB _u(3) +#define M33_ITM_TCR_TXENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_SYNCENA +// Description : Enables Synchronization packet transmission for a synchronous +// TPIU +#define M33_ITM_TCR_SYNCENA_RESET _u(0x0) +#define M33_ITM_TCR_SYNCENA_BITS _u(0x00000004) +#define M33_ITM_TCR_SYNCENA_MSB _u(2) +#define M33_ITM_TCR_SYNCENA_LSB _u(2) +#define M33_ITM_TCR_SYNCENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TSENA +// Description : Enables Local timestamp generation +#define M33_ITM_TCR_TSENA_RESET _u(0x0) +#define M33_ITM_TCR_TSENA_BITS _u(0x00000002) +#define M33_ITM_TCR_TSENA_MSB _u(1) +#define M33_ITM_TCR_TSENA_LSB _u(1) +#define M33_ITM_TCR_TSENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_ITMENA +// Description : Enables the ITM +#define M33_ITM_TCR_ITMENA_RESET _u(0x0) +#define M33_ITM_TCR_ITMENA_BITS _u(0x00000001) +#define M33_ITM_TCR_ITMENA_MSB _u(0) +#define M33_ITM_TCR_ITMENA_LSB _u(0) +#define M33_ITM_TCR_ITMENA_ACCESS "RW" +// ============================================================================= +// Register : M33_INT_ATREADY +// Description : Integration Mode: Read ATB Ready +#define M33_INT_ATREADY_OFFSET _u(0x00000ef0) +#define M33_INT_ATREADY_BITS _u(0x00000003) +#define M33_INT_ATREADY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATREADY_AFVALID +// Description : A read of this bit returns the value of AFVALID +#define M33_INT_ATREADY_AFVALID_RESET _u(0x0) +#define M33_INT_ATREADY_AFVALID_BITS _u(0x00000002) +#define M33_INT_ATREADY_AFVALID_MSB _u(1) +#define M33_INT_ATREADY_AFVALID_LSB _u(1) +#define M33_INT_ATREADY_AFVALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATREADY_ATREADY +// Description : A read of this bit returns the value of ATREADY +#define M33_INT_ATREADY_ATREADY_RESET _u(0x0) +#define M33_INT_ATREADY_ATREADY_BITS _u(0x00000001) +#define M33_INT_ATREADY_ATREADY_MSB _u(0) +#define M33_INT_ATREADY_ATREADY_LSB _u(0) +#define M33_INT_ATREADY_ATREADY_ACCESS "RO" +// ============================================================================= +// Register : M33_INT_ATVALID +// Description : Integration Mode: Write ATB Valid +#define M33_INT_ATVALID_OFFSET _u(0x00000ef8) +#define M33_INT_ATVALID_BITS _u(0x00000003) +#define M33_INT_ATVALID_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATVALID_AFREADY +// Description : A write to this bit gives the value of AFREADY +#define M33_INT_ATVALID_AFREADY_RESET _u(0x0) +#define M33_INT_ATVALID_AFREADY_BITS _u(0x00000002) +#define M33_INT_ATVALID_AFREADY_MSB _u(1) +#define M33_INT_ATVALID_AFREADY_LSB _u(1) +#define M33_INT_ATVALID_AFREADY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATVALID_ATREADY +// Description : A write to this bit gives the value of ATVALID +#define M33_INT_ATVALID_ATREADY_RESET _u(0x0) +#define M33_INT_ATVALID_ATREADY_BITS _u(0x00000001) +#define M33_INT_ATVALID_ATREADY_MSB _u(0) +#define M33_INT_ATVALID_ATREADY_LSB _u(0) +#define M33_INT_ATVALID_ATREADY_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_ITCTRL +// Description : Integration Mode Control Register +#define M33_ITM_ITCTRL_OFFSET _u(0x00000f00) +#define M33_ITM_ITCTRL_BITS _u(0x00000001) +#define M33_ITM_ITCTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_ITCTRL_IME +// Description : Integration mode enable bit - The possible values are: 0 - The +// trace unit is not in integration mode. 1 - The trace unit is in +// integration mode. This mode enables: A debug agent to perform +// topology detection. SoC test software to perform integration +// testing. +#define M33_ITM_ITCTRL_IME_RESET _u(0x0) +#define M33_ITM_ITCTRL_IME_BITS _u(0x00000001) +#define M33_ITM_ITCTRL_IME_MSB _u(0) +#define M33_ITM_ITCTRL_IME_LSB _u(0) +#define M33_ITM_ITCTRL_IME_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_DEVARCH +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_DEVARCH_OFFSET _u(0x00000fbc) +#define M33_ITM_DEVARCH_BITS _u(0xffffffff) +#define M33_ITM_DEVARCH_RESET _u(0x47701a01) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_ITM_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_ITM_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_ITM_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_ITM_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_ITM_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_ITM_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_ITM_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_ITM_DEVARCH_PRESENT_MSB _u(20) +#define M33_ITM_DEVARCH_PRESENT_LSB _u(20) +#define M33_ITM_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_ITM_DEVARCH_REVISION_RESET _u(0x0) +#define M33_ITM_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_ITM_DEVARCH_REVISION_MSB _u(19) +#define M33_ITM_DEVARCH_REVISION_LSB _u(16) +#define M33_ITM_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_ITM_DEVARCH_ARCHVER_RESET _u(0x1) +#define M33_ITM_DEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_ITM_DEVARCH_ARCHVER_MSB _u(15) +#define M33_ITM_DEVARCH_ARCHVER_LSB _u(12) +#define M33_ITM_DEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_ITM_DEVARCH_ARCHPART_RESET _u(0xa01) +#define M33_ITM_DEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_ITM_DEVARCH_ARCHPART_MSB _u(11) +#define M33_ITM_DEVARCH_ARCHPART_LSB _u(0) +#define M33_ITM_DEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_DEVTYPE +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_DEVTYPE_OFFSET _u(0x00000fcc) +#define M33_ITM_DEVTYPE_BITS _u(0x000000ff) +#define M33_ITM_DEVTYPE_RESET _u(0x00000043) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVTYPE_SUB +// Description : Component sub-type +#define M33_ITM_DEVTYPE_SUB_RESET _u(0x4) +#define M33_ITM_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_ITM_DEVTYPE_SUB_MSB _u(7) +#define M33_ITM_DEVTYPE_SUB_LSB _u(4) +#define M33_ITM_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVTYPE_MAJOR +// Description : Component major type +#define M33_ITM_DEVTYPE_MAJOR_RESET _u(0x3) +#define M33_ITM_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_ITM_DEVTYPE_MAJOR_MSB _u(3) +#define M33_ITM_DEVTYPE_MAJOR_LSB _u(0) +#define M33_ITM_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR4 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR4_OFFSET _u(0x00000fd0) +#define M33_ITM_PIDR4_BITS _u(0x000000ff) +#define M33_ITM_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR4_SIZE_RESET _u(0x0) +#define M33_ITM_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_ITM_PIDR4_SIZE_MSB _u(7) +#define M33_ITM_PIDR4_SIZE_LSB _u(4) +#define M33_ITM_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR4_DES_2_RESET _u(0x4) +#define M33_ITM_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_ITM_PIDR4_DES_2_MSB _u(3) +#define M33_ITM_PIDR4_DES_2_LSB _u(0) +#define M33_ITM_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR5 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR5_OFFSET _u(0x00000fd4) +#define M33_ITM_PIDR5_BITS _u(0x00000000) +#define M33_ITM_PIDR5_RESET _u(0x00000000) +#define M33_ITM_PIDR5_MSB _u(31) +#define M33_ITM_PIDR5_LSB _u(0) +#define M33_ITM_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_PIDR6 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR6_OFFSET _u(0x00000fd8) +#define M33_ITM_PIDR6_BITS _u(0x00000000) +#define M33_ITM_PIDR6_RESET _u(0x00000000) +#define M33_ITM_PIDR6_MSB _u(31) +#define M33_ITM_PIDR6_LSB _u(0) +#define M33_ITM_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_PIDR7 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR7_OFFSET _u(0x00000fdc) +#define M33_ITM_PIDR7_BITS _u(0x00000000) +#define M33_ITM_PIDR7_RESET _u(0x00000000) +#define M33_ITM_PIDR7_MSB _u(31) +#define M33_ITM_PIDR7_LSB _u(0) +#define M33_ITM_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_PIDR0 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR0_OFFSET _u(0x00000fe0) +#define M33_ITM_PIDR0_BITS _u(0x000000ff) +#define M33_ITM_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR0_PART_0_RESET _u(0x21) +#define M33_ITM_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_ITM_PIDR0_PART_0_MSB _u(7) +#define M33_ITM_PIDR0_PART_0_LSB _u(0) +#define M33_ITM_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR1 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR1_OFFSET _u(0x00000fe4) +#define M33_ITM_PIDR1_BITS _u(0x000000ff) +#define M33_ITM_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR1_DES_0_RESET _u(0xb) +#define M33_ITM_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_ITM_PIDR1_DES_0_MSB _u(7) +#define M33_ITM_PIDR1_DES_0_LSB _u(4) +#define M33_ITM_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR1_PART_1_RESET _u(0xd) +#define M33_ITM_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_ITM_PIDR1_PART_1_MSB _u(3) +#define M33_ITM_PIDR1_PART_1_LSB _u(0) +#define M33_ITM_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR2 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR2_OFFSET _u(0x00000fe8) +#define M33_ITM_PIDR2_BITS _u(0x000000ff) +#define M33_ITM_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR2_REVISION_RESET _u(0x0) +#define M33_ITM_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_ITM_PIDR2_REVISION_MSB _u(7) +#define M33_ITM_PIDR2_REVISION_LSB _u(4) +#define M33_ITM_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR2_JEDEC_RESET _u(0x1) +#define M33_ITM_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_ITM_PIDR2_JEDEC_MSB _u(3) +#define M33_ITM_PIDR2_JEDEC_LSB _u(3) +#define M33_ITM_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR2_DES_1_RESET _u(0x3) +#define M33_ITM_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_ITM_PIDR2_DES_1_MSB _u(2) +#define M33_ITM_PIDR2_DES_1_LSB _u(0) +#define M33_ITM_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR3 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR3_OFFSET _u(0x00000fec) +#define M33_ITM_PIDR3_BITS _u(0x000000ff) +#define M33_ITM_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR3_REVAND_RESET _u(0x0) +#define M33_ITM_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_ITM_PIDR3_REVAND_MSB _u(7) +#define M33_ITM_PIDR3_REVAND_LSB _u(4) +#define M33_ITM_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR3_CMOD_RESET _u(0x0) +#define M33_ITM_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_ITM_PIDR3_CMOD_MSB _u(3) +#define M33_ITM_PIDR3_CMOD_LSB _u(0) +#define M33_ITM_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR0 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR0_OFFSET _u(0x00000ff0) +#define M33_ITM_CIDR0_BITS _u(0x000000ff) +#define M33_ITM_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_ITM_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_ITM_CIDR0_PRMBL_0_MSB _u(7) +#define M33_ITM_CIDR0_PRMBL_0_LSB _u(0) +#define M33_ITM_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR1 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR1_OFFSET _u(0x00000ff4) +#define M33_ITM_CIDR1_BITS _u(0x000000ff) +#define M33_ITM_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR1_CLASS_RESET _u(0x9) +#define M33_ITM_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_ITM_CIDR1_CLASS_MSB _u(7) +#define M33_ITM_CIDR1_CLASS_LSB _u(4) +#define M33_ITM_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_ITM_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_ITM_CIDR1_PRMBL_1_MSB _u(3) +#define M33_ITM_CIDR1_PRMBL_1_LSB _u(0) +#define M33_ITM_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR2 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR2_OFFSET _u(0x00000ff8) +#define M33_ITM_CIDR2_BITS _u(0x000000ff) +#define M33_ITM_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_ITM_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_ITM_CIDR2_PRMBL_2_MSB _u(7) +#define M33_ITM_CIDR2_PRMBL_2_LSB _u(0) +#define M33_ITM_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR3 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR3_OFFSET _u(0x00000ffc) +#define M33_ITM_CIDR3_BITS _u(0x000000ff) +#define M33_ITM_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_ITM_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_ITM_CIDR3_PRMBL_3_MSB _u(7) +#define M33_ITM_CIDR3_PRMBL_3_LSB _u(0) +#define M33_ITM_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CTRL +// Description : Provides configuration and status information for the DWT unit, +// and used to control features of the unit +#define M33_DWT_CTRL_OFFSET _u(0x00001000) +#define M33_DWT_CTRL_BITS _u(0xffff1fff) +#define M33_DWT_CTRL_RESET _u(0x73741824) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NUMCOMP +// Description : Number of DWT comparators implemented +#define M33_DWT_CTRL_NUMCOMP_RESET _u(0x7) +#define M33_DWT_CTRL_NUMCOMP_BITS _u(0xf0000000) +#define M33_DWT_CTRL_NUMCOMP_MSB _u(31) +#define M33_DWT_CTRL_NUMCOMP_LSB _u(28) +#define M33_DWT_CTRL_NUMCOMP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOTRCPKT +// Description : Indicates whether the implementation does not support trace +#define M33_DWT_CTRL_NOTRCPKT_RESET _u(0x0) +#define M33_DWT_CTRL_NOTRCPKT_BITS _u(0x08000000) +#define M33_DWT_CTRL_NOTRCPKT_MSB _u(27) +#define M33_DWT_CTRL_NOTRCPKT_LSB _u(27) +#define M33_DWT_CTRL_NOTRCPKT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOEXTTRIG +// Description : Reserved, RAZ +#define M33_DWT_CTRL_NOEXTTRIG_RESET _u(0x0) +#define M33_DWT_CTRL_NOEXTTRIG_BITS _u(0x04000000) +#define M33_DWT_CTRL_NOEXTTRIG_MSB _u(26) +#define M33_DWT_CTRL_NOEXTTRIG_LSB _u(26) +#define M33_DWT_CTRL_NOEXTTRIG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOCYCCNT +// Description : Indicates whether the implementation does not include a cycle +// counter +#define M33_DWT_CTRL_NOCYCCNT_RESET _u(0x1) +#define M33_DWT_CTRL_NOCYCCNT_BITS _u(0x02000000) +#define M33_DWT_CTRL_NOCYCCNT_MSB _u(25) +#define M33_DWT_CTRL_NOCYCCNT_LSB _u(25) +#define M33_DWT_CTRL_NOCYCCNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOPRFCNT +// Description : Indicates whether the implementation does not include the +// profiling counters +#define M33_DWT_CTRL_NOPRFCNT_RESET _u(0x1) +#define M33_DWT_CTRL_NOPRFCNT_BITS _u(0x01000000) +#define M33_DWT_CTRL_NOPRFCNT_MSB _u(24) +#define M33_DWT_CTRL_NOPRFCNT_LSB _u(24) +#define M33_DWT_CTRL_NOPRFCNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCDISS +// Description : Controls whether the cycle counter is disabled in Secure state +#define M33_DWT_CTRL_CYCDISS_RESET _u(0x0) +#define M33_DWT_CTRL_CYCDISS_BITS _u(0x00800000) +#define M33_DWT_CTRL_CYCDISS_MSB _u(23) +#define M33_DWT_CTRL_CYCDISS_LSB _u(23) +#define M33_DWT_CTRL_CYCDISS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCEVTENA +// Description : Enables Event Counter packet generation on POSTCNT underflow +#define M33_DWT_CTRL_CYCEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_CYCEVTENA_BITS _u(0x00400000) +#define M33_DWT_CTRL_CYCEVTENA_MSB _u(22) +#define M33_DWT_CTRL_CYCEVTENA_LSB _u(22) +#define M33_DWT_CTRL_CYCEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_FOLDEVTENA +// Description : Enables DWT_FOLDCNT counter +#define M33_DWT_CTRL_FOLDEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_FOLDEVTENA_BITS _u(0x00200000) +#define M33_DWT_CTRL_FOLDEVTENA_MSB _u(21) +#define M33_DWT_CTRL_FOLDEVTENA_LSB _u(21) +#define M33_DWT_CTRL_FOLDEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_LSUEVTENA +// Description : Enables DWT_LSUCNT counter +#define M33_DWT_CTRL_LSUEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_LSUEVTENA_BITS _u(0x00100000) +#define M33_DWT_CTRL_LSUEVTENA_MSB _u(20) +#define M33_DWT_CTRL_LSUEVTENA_LSB _u(20) +#define M33_DWT_CTRL_LSUEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_SLEEPEVTENA +// Description : Enable DWT_SLEEPCNT counter +#define M33_DWT_CTRL_SLEEPEVTENA_RESET _u(0x0) +#define M33_DWT_CTRL_SLEEPEVTENA_BITS _u(0x00080000) +#define M33_DWT_CTRL_SLEEPEVTENA_MSB _u(19) +#define M33_DWT_CTRL_SLEEPEVTENA_LSB _u(19) +#define M33_DWT_CTRL_SLEEPEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_EXCEVTENA +// Description : Enables DWT_EXCCNT counter +#define M33_DWT_CTRL_EXCEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_EXCEVTENA_BITS _u(0x00040000) +#define M33_DWT_CTRL_EXCEVTENA_MSB _u(18) +#define M33_DWT_CTRL_EXCEVTENA_LSB _u(18) +#define M33_DWT_CTRL_EXCEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CPIEVTENA +// Description : Enables DWT_CPICNT counter +#define M33_DWT_CTRL_CPIEVTENA_RESET _u(0x0) +#define M33_DWT_CTRL_CPIEVTENA_BITS _u(0x00020000) +#define M33_DWT_CTRL_CPIEVTENA_MSB _u(17) +#define M33_DWT_CTRL_CPIEVTENA_LSB _u(17) +#define M33_DWT_CTRL_CPIEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_EXTTRCENA +// Description : Enables generation of Exception Trace packets +#define M33_DWT_CTRL_EXTTRCENA_RESET _u(0x0) +#define M33_DWT_CTRL_EXTTRCENA_BITS _u(0x00010000) +#define M33_DWT_CTRL_EXTTRCENA_MSB _u(16) +#define M33_DWT_CTRL_EXTTRCENA_LSB _u(16) +#define M33_DWT_CTRL_EXTTRCENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_PCSAMPLENA +// Description : Enables use of POSTCNT counter as a timer for Periodic PC +// Sample packet generation +#define M33_DWT_CTRL_PCSAMPLENA_RESET _u(0x1) +#define M33_DWT_CTRL_PCSAMPLENA_BITS _u(0x00001000) +#define M33_DWT_CTRL_PCSAMPLENA_MSB _u(12) +#define M33_DWT_CTRL_PCSAMPLENA_LSB _u(12) +#define M33_DWT_CTRL_PCSAMPLENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_SYNCTAP +// Description : Selects the position of the synchronization packet counter tap +// on the CYCCNT counter. This determines the Synchronization +// packet rate +#define M33_DWT_CTRL_SYNCTAP_RESET _u(0x2) +#define M33_DWT_CTRL_SYNCTAP_BITS _u(0x00000c00) +#define M33_DWT_CTRL_SYNCTAP_MSB _u(11) +#define M33_DWT_CTRL_SYNCTAP_LSB _u(10) +#define M33_DWT_CTRL_SYNCTAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCTAP +// Description : Selects the position of the POSTCNT tap on the CYCCNT counter +#define M33_DWT_CTRL_CYCTAP_RESET _u(0x0) +#define M33_DWT_CTRL_CYCTAP_BITS _u(0x00000200) +#define M33_DWT_CTRL_CYCTAP_MSB _u(9) +#define M33_DWT_CTRL_CYCTAP_LSB _u(9) +#define M33_DWT_CTRL_CYCTAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_POSTINIT +// Description : Initial value for the POSTCNT counter +#define M33_DWT_CTRL_POSTINIT_RESET _u(0x1) +#define M33_DWT_CTRL_POSTINIT_BITS _u(0x000001e0) +#define M33_DWT_CTRL_POSTINIT_MSB _u(8) +#define M33_DWT_CTRL_POSTINIT_LSB _u(5) +#define M33_DWT_CTRL_POSTINIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_POSTPRESET +// Description : Reload value for the POSTCNT counter +#define M33_DWT_CTRL_POSTPRESET_RESET _u(0x2) +#define M33_DWT_CTRL_POSTPRESET_BITS _u(0x0000001e) +#define M33_DWT_CTRL_POSTPRESET_MSB _u(4) +#define M33_DWT_CTRL_POSTPRESET_LSB _u(1) +#define M33_DWT_CTRL_POSTPRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCCNTENA +// Description : Enables CYCCNT +#define M33_DWT_CTRL_CYCCNTENA_RESET _u(0x0) +#define M33_DWT_CTRL_CYCCNTENA_BITS _u(0x00000001) +#define M33_DWT_CTRL_CYCCNTENA_MSB _u(0) +#define M33_DWT_CTRL_CYCCNTENA_LSB _u(0) +#define M33_DWT_CTRL_CYCCNTENA_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_CYCCNT +// Description : Shows or sets the value of the processor cycle counter, CYCCNT +#define M33_DWT_CYCCNT_OFFSET _u(0x00001004) +#define M33_DWT_CYCCNT_BITS _u(0xffffffff) +#define M33_DWT_CYCCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CYCCNT_CYCCNT +// Description : Increments one on each processor clock cycle when +// DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, +// CYCCNT wraps to zero +#define M33_DWT_CYCCNT_CYCCNT_RESET _u(0x00000000) +#define M33_DWT_CYCCNT_CYCCNT_BITS _u(0xffffffff) +#define M33_DWT_CYCCNT_CYCCNT_MSB _u(31) +#define M33_DWT_CYCCNT_CYCCNT_LSB _u(0) +#define M33_DWT_CYCCNT_CYCCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_EXCCNT +// Description : Counts the total cycles spent in exception processing +#define M33_DWT_EXCCNT_OFFSET _u(0x0000100c) +#define M33_DWT_EXCCNT_BITS _u(0x000000ff) +#define M33_DWT_EXCCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_EXCCNT_EXCCNT +// Description : Counts one on each cycle when all of the following are true: - +// DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction +// is executed, see DWT_CPICNT. - An exception-entry or exception- +// exit related operation is in progress. - Either +// SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the +// operation is set to Non-secure and NoninvasiveDebugAllowed() == +// TRUE. +#define M33_DWT_EXCCNT_EXCCNT_RESET _u(0x00) +#define M33_DWT_EXCCNT_EXCCNT_BITS _u(0x000000ff) +#define M33_DWT_EXCCNT_EXCCNT_MSB _u(7) +#define M33_DWT_EXCCNT_EXCCNT_LSB _u(0) +#define M33_DWT_EXCCNT_EXCCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_LSUCNT +// Description : Increments on the additional cycles required to execute all +// load or store instructions +#define M33_DWT_LSUCNT_OFFSET _u(0x00001014) +#define M33_DWT_LSUCNT_BITS _u(0x000000ff) +#define M33_DWT_LSUCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_LSUCNT_LSUCNT +// Description : Counts one on each cycle when all of the following are true: - +// DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction +// is executed, see DWT_CPICNT. - No exception-entry or exception- +// exit operation is in progress, see DWT_EXCCNT. - A load-store +// operation is in progress. - Either +// SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the +// operation is set to Non-secure and NoninvasiveDebugAllowed() == +// TRUE. +#define M33_DWT_LSUCNT_LSUCNT_RESET _u(0x00) +#define M33_DWT_LSUCNT_LSUCNT_BITS _u(0x000000ff) +#define M33_DWT_LSUCNT_LSUCNT_MSB _u(7) +#define M33_DWT_LSUCNT_LSUCNT_LSB _u(0) +#define M33_DWT_LSUCNT_LSUCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FOLDCNT +// Description : Increments on the additional cycles required to execute all +// load or store instructions +#define M33_DWT_FOLDCNT_OFFSET _u(0x00001018) +#define M33_DWT_FOLDCNT_BITS _u(0x000000ff) +#define M33_DWT_FOLDCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FOLDCNT_FOLDCNT +// Description : Counts on each cycle when all of the following are true: - +// DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two +// instructions are executed, see DWT_CPICNT. - Either +// SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non- +// secure state and NoninvasiveDebugAllowed() == TRUE. The counter +// is incremented by the number of instructions executed, minus +// one +#define M33_DWT_FOLDCNT_FOLDCNT_RESET _u(0x00) +#define M33_DWT_FOLDCNT_FOLDCNT_BITS _u(0x000000ff) +#define M33_DWT_FOLDCNT_FOLDCNT_MSB _u(7) +#define M33_DWT_FOLDCNT_FOLDCNT_LSB _u(0) +#define M33_DWT_FOLDCNT_FOLDCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP0 +// Description : Provides a reference value for use by watchpoint comparator 0 +#define M33_DWT_COMP0_OFFSET _u(0x00001020) +#define M33_DWT_COMP0_BITS _u(0xffffffff) +#define M33_DWT_COMP0_RESET _u(0x00000000) +#define M33_DWT_COMP0_MSB _u(31) +#define M33_DWT_COMP0_LSB _u(0) +#define M33_DWT_COMP0_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION0 +// Description : Controls the operation of watchpoint comparator 0 +#define M33_DWT_FUNCTION0_OFFSET _u(0x00001028) +#define M33_DWT_FUNCTION0_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION0_RESET _u(0x58000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION0_ID_RESET _u(0x0b) +#define M33_DWT_FUNCTION0_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION0_ID_MSB _u(31) +#define M33_DWT_FUNCTION0_ID_LSB _u(27) +#define M33_DWT_FUNCTION0_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION0_MATCHED_RESET _u(0x0) +#define M33_DWT_FUNCTION0_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION0_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION0_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION0_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION0_DATAVSIZE_RESET _u(0x0) +#define M33_DWT_FUNCTION0_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION0_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION0_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION0_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION0_ACTION_RESET _u(0x0) +#define M33_DWT_FUNCTION0_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION0_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION0_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION0_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION0_MATCH_RESET _u(0x0) +#define M33_DWT_FUNCTION0_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION0_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION0_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION0_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP1 +// Description : Provides a reference value for use by watchpoint comparator 1 +#define M33_DWT_COMP1_OFFSET _u(0x00001030) +#define M33_DWT_COMP1_BITS _u(0xffffffff) +#define M33_DWT_COMP1_RESET _u(0x00000000) +#define M33_DWT_COMP1_MSB _u(31) +#define M33_DWT_COMP1_LSB _u(0) +#define M33_DWT_COMP1_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION1 +// Description : Controls the operation of watchpoint comparator 1 +#define M33_DWT_FUNCTION1_OFFSET _u(0x00001038) +#define M33_DWT_FUNCTION1_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION1_RESET _u(0x89000828) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION1_ID_RESET _u(0x11) +#define M33_DWT_FUNCTION1_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION1_ID_MSB _u(31) +#define M33_DWT_FUNCTION1_ID_LSB _u(27) +#define M33_DWT_FUNCTION1_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION1_MATCHED_RESET _u(0x1) +#define M33_DWT_FUNCTION1_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION1_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION1_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION1_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION1_DATAVSIZE_RESET _u(0x2) +#define M33_DWT_FUNCTION1_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION1_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION1_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION1_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION1_ACTION_RESET _u(0x2) +#define M33_DWT_FUNCTION1_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION1_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION1_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION1_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION1_MATCH_RESET _u(0x8) +#define M33_DWT_FUNCTION1_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION1_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION1_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION1_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP2 +// Description : Provides a reference value for use by watchpoint comparator 2 +#define M33_DWT_COMP2_OFFSET _u(0x00001040) +#define M33_DWT_COMP2_BITS _u(0xffffffff) +#define M33_DWT_COMP2_RESET _u(0x00000000) +#define M33_DWT_COMP2_MSB _u(31) +#define M33_DWT_COMP2_LSB _u(0) +#define M33_DWT_COMP2_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION2 +// Description : Controls the operation of watchpoint comparator 2 +#define M33_DWT_FUNCTION2_OFFSET _u(0x00001048) +#define M33_DWT_FUNCTION2_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION2_RESET _u(0x50000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION2_ID_RESET _u(0x0a) +#define M33_DWT_FUNCTION2_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION2_ID_MSB _u(31) +#define M33_DWT_FUNCTION2_ID_LSB _u(27) +#define M33_DWT_FUNCTION2_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION2_MATCHED_RESET _u(0x0) +#define M33_DWT_FUNCTION2_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION2_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION2_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION2_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION2_DATAVSIZE_RESET _u(0x0) +#define M33_DWT_FUNCTION2_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION2_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION2_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION2_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION2_ACTION_RESET _u(0x0) +#define M33_DWT_FUNCTION2_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION2_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION2_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION2_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION2_MATCH_RESET _u(0x0) +#define M33_DWT_FUNCTION2_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION2_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION2_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION2_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP3 +// Description : Provides a reference value for use by watchpoint comparator 3 +#define M33_DWT_COMP3_OFFSET _u(0x00001050) +#define M33_DWT_COMP3_BITS _u(0xffffffff) +#define M33_DWT_COMP3_RESET _u(0x00000000) +#define M33_DWT_COMP3_MSB _u(31) +#define M33_DWT_COMP3_LSB _u(0) +#define M33_DWT_COMP3_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION3 +// Description : Controls the operation of watchpoint comparator 3 +#define M33_DWT_FUNCTION3_OFFSET _u(0x00001058) +#define M33_DWT_FUNCTION3_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION3_RESET _u(0x20000800) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION3_ID_RESET _u(0x04) +#define M33_DWT_FUNCTION3_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION3_ID_MSB _u(31) +#define M33_DWT_FUNCTION3_ID_LSB _u(27) +#define M33_DWT_FUNCTION3_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION3_MATCHED_RESET _u(0x0) +#define M33_DWT_FUNCTION3_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION3_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION3_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION3_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION3_DATAVSIZE_RESET _u(0x2) +#define M33_DWT_FUNCTION3_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION3_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION3_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION3_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION3_ACTION_RESET _u(0x0) +#define M33_DWT_FUNCTION3_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION3_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION3_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION3_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION3_MATCH_RESET _u(0x0) +#define M33_DWT_FUNCTION3_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION3_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION3_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION3_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_DEVARCH +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_DEVARCH_OFFSET _u(0x00001fbc) +#define M33_DWT_DEVARCH_BITS _u(0xffffffff) +#define M33_DWT_DEVARCH_RESET _u(0x47701a02) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_DWT_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_DWT_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_DWT_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_DWT_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_DWT_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_DWT_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_DWT_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_DWT_DEVARCH_PRESENT_MSB _u(20) +#define M33_DWT_DEVARCH_PRESENT_LSB _u(20) +#define M33_DWT_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_DWT_DEVARCH_REVISION_RESET _u(0x0) +#define M33_DWT_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_DWT_DEVARCH_REVISION_MSB _u(19) +#define M33_DWT_DEVARCH_REVISION_LSB _u(16) +#define M33_DWT_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_DWT_DEVARCH_ARCHVER_RESET _u(0x1) +#define M33_DWT_DEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_DWT_DEVARCH_ARCHVER_MSB _u(15) +#define M33_DWT_DEVARCH_ARCHVER_LSB _u(12) +#define M33_DWT_DEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_DWT_DEVARCH_ARCHPART_RESET _u(0xa02) +#define M33_DWT_DEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_DWT_DEVARCH_ARCHPART_MSB _u(11) +#define M33_DWT_DEVARCH_ARCHPART_LSB _u(0) +#define M33_DWT_DEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_DEVTYPE +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_DEVTYPE_OFFSET _u(0x00001fcc) +#define M33_DWT_DEVTYPE_BITS _u(0x000000ff) +#define M33_DWT_DEVTYPE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVTYPE_SUB +// Description : Component sub-type +#define M33_DWT_DEVTYPE_SUB_RESET _u(0x0) +#define M33_DWT_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_DWT_DEVTYPE_SUB_MSB _u(7) +#define M33_DWT_DEVTYPE_SUB_LSB _u(4) +#define M33_DWT_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVTYPE_MAJOR +// Description : Component major type +#define M33_DWT_DEVTYPE_MAJOR_RESET _u(0x0) +#define M33_DWT_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_DWT_DEVTYPE_MAJOR_MSB _u(3) +#define M33_DWT_DEVTYPE_MAJOR_LSB _u(0) +#define M33_DWT_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR4 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR4_OFFSET _u(0x00001fd0) +#define M33_DWT_PIDR4_BITS _u(0x000000ff) +#define M33_DWT_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR4_SIZE_RESET _u(0x0) +#define M33_DWT_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_DWT_PIDR4_SIZE_MSB _u(7) +#define M33_DWT_PIDR4_SIZE_LSB _u(4) +#define M33_DWT_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR4_DES_2_RESET _u(0x4) +#define M33_DWT_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_DWT_PIDR4_DES_2_MSB _u(3) +#define M33_DWT_PIDR4_DES_2_LSB _u(0) +#define M33_DWT_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR5 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR5_OFFSET _u(0x00001fd4) +#define M33_DWT_PIDR5_BITS _u(0x00000000) +#define M33_DWT_PIDR5_RESET _u(0x00000000) +#define M33_DWT_PIDR5_MSB _u(31) +#define M33_DWT_PIDR5_LSB _u(0) +#define M33_DWT_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_PIDR6 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR6_OFFSET _u(0x00001fd8) +#define M33_DWT_PIDR6_BITS _u(0x00000000) +#define M33_DWT_PIDR6_RESET _u(0x00000000) +#define M33_DWT_PIDR6_MSB _u(31) +#define M33_DWT_PIDR6_LSB _u(0) +#define M33_DWT_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_PIDR7 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR7_OFFSET _u(0x00001fdc) +#define M33_DWT_PIDR7_BITS _u(0x00000000) +#define M33_DWT_PIDR7_RESET _u(0x00000000) +#define M33_DWT_PIDR7_MSB _u(31) +#define M33_DWT_PIDR7_LSB _u(0) +#define M33_DWT_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_PIDR0 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR0_OFFSET _u(0x00001fe0) +#define M33_DWT_PIDR0_BITS _u(0x000000ff) +#define M33_DWT_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR0_PART_0_RESET _u(0x21) +#define M33_DWT_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_DWT_PIDR0_PART_0_MSB _u(7) +#define M33_DWT_PIDR0_PART_0_LSB _u(0) +#define M33_DWT_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR1 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR1_OFFSET _u(0x00001fe4) +#define M33_DWT_PIDR1_BITS _u(0x000000ff) +#define M33_DWT_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR1_DES_0_RESET _u(0xb) +#define M33_DWT_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_DWT_PIDR1_DES_0_MSB _u(7) +#define M33_DWT_PIDR1_DES_0_LSB _u(4) +#define M33_DWT_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR1_PART_1_RESET _u(0xd) +#define M33_DWT_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_DWT_PIDR1_PART_1_MSB _u(3) +#define M33_DWT_PIDR1_PART_1_LSB _u(0) +#define M33_DWT_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR2 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR2_OFFSET _u(0x00001fe8) +#define M33_DWT_PIDR2_BITS _u(0x000000ff) +#define M33_DWT_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR2_REVISION_RESET _u(0x0) +#define M33_DWT_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_DWT_PIDR2_REVISION_MSB _u(7) +#define M33_DWT_PIDR2_REVISION_LSB _u(4) +#define M33_DWT_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR2_JEDEC_RESET _u(0x1) +#define M33_DWT_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_DWT_PIDR2_JEDEC_MSB _u(3) +#define M33_DWT_PIDR2_JEDEC_LSB _u(3) +#define M33_DWT_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR2_DES_1_RESET _u(0x3) +#define M33_DWT_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_DWT_PIDR2_DES_1_MSB _u(2) +#define M33_DWT_PIDR2_DES_1_LSB _u(0) +#define M33_DWT_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR3 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR3_OFFSET _u(0x00001fec) +#define M33_DWT_PIDR3_BITS _u(0x000000ff) +#define M33_DWT_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR3_REVAND_RESET _u(0x0) +#define M33_DWT_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_DWT_PIDR3_REVAND_MSB _u(7) +#define M33_DWT_PIDR3_REVAND_LSB _u(4) +#define M33_DWT_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR3_CMOD_RESET _u(0x0) +#define M33_DWT_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_DWT_PIDR3_CMOD_MSB _u(3) +#define M33_DWT_PIDR3_CMOD_LSB _u(0) +#define M33_DWT_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR0 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR0_OFFSET _u(0x00001ff0) +#define M33_DWT_CIDR0_BITS _u(0x000000ff) +#define M33_DWT_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_DWT_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_DWT_CIDR0_PRMBL_0_MSB _u(7) +#define M33_DWT_CIDR0_PRMBL_0_LSB _u(0) +#define M33_DWT_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR1 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR1_OFFSET _u(0x00001ff4) +#define M33_DWT_CIDR1_BITS _u(0x000000ff) +#define M33_DWT_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR1_CLASS_RESET _u(0x9) +#define M33_DWT_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_DWT_CIDR1_CLASS_MSB _u(7) +#define M33_DWT_CIDR1_CLASS_LSB _u(4) +#define M33_DWT_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_DWT_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_DWT_CIDR1_PRMBL_1_MSB _u(3) +#define M33_DWT_CIDR1_PRMBL_1_LSB _u(0) +#define M33_DWT_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR2 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR2_OFFSET _u(0x00001ff8) +#define M33_DWT_CIDR2_BITS _u(0x000000ff) +#define M33_DWT_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_DWT_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_DWT_CIDR2_PRMBL_2_MSB _u(7) +#define M33_DWT_CIDR2_PRMBL_2_LSB _u(0) +#define M33_DWT_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR3 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR3_OFFSET _u(0x00001ffc) +#define M33_DWT_CIDR3_BITS _u(0x000000ff) +#define M33_DWT_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_DWT_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_DWT_CIDR3_PRMBL_3_MSB _u(7) +#define M33_DWT_CIDR3_PRMBL_3_LSB _u(0) +#define M33_DWT_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CTRL +// Description : Provides FPB implementation information, and the global enable +// for the FPB unit +#define M33_FP_CTRL_OFFSET _u(0x00002000) +#define M33_FP_CTRL_BITS _u(0xf0007ff3) +#define M33_FP_CTRL_RESET _u(0x60005580) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_REV +// Description : Flash Patch and Breakpoint Unit architecture revision +#define M33_FP_CTRL_REV_RESET _u(0x6) +#define M33_FP_CTRL_REV_BITS _u(0xf0000000) +#define M33_FP_CTRL_REV_MSB _u(31) +#define M33_FP_CTRL_REV_LSB _u(28) +#define M33_FP_CTRL_REV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_NUM_CODE_14_12_ +// Description : Indicates the number of implemented instruction address +// comparators. Zero indicates no Instruction Address comparators +// are implemented. The Instruction Address comparators are +// numbered from 0 to NUM_CODE - 1 +#define M33_FP_CTRL_NUM_CODE_14_12__RESET _u(0x5) +#define M33_FP_CTRL_NUM_CODE_14_12__BITS _u(0x00007000) +#define M33_FP_CTRL_NUM_CODE_14_12__MSB _u(14) +#define M33_FP_CTRL_NUM_CODE_14_12__LSB _u(12) +#define M33_FP_CTRL_NUM_CODE_14_12__ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_NUM_LIT +// Description : Indicates the number of implemented literal address +// comparators. The Literal Address comparators are numbered from +// NUM_CODE to NUM_CODE + NUM_LIT - 1 +#define M33_FP_CTRL_NUM_LIT_RESET _u(0x5) +#define M33_FP_CTRL_NUM_LIT_BITS _u(0x00000f00) +#define M33_FP_CTRL_NUM_LIT_MSB _u(11) +#define M33_FP_CTRL_NUM_LIT_LSB _u(8) +#define M33_FP_CTRL_NUM_LIT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_NUM_CODE_7_4_ +// Description : Indicates the number of implemented instruction address +// comparators. Zero indicates no Instruction Address comparators +// are implemented. The Instruction Address comparators are +// numbered from 0 to NUM_CODE - 1 +#define M33_FP_CTRL_NUM_CODE_7_4__RESET _u(0x8) +#define M33_FP_CTRL_NUM_CODE_7_4__BITS _u(0x000000f0) +#define M33_FP_CTRL_NUM_CODE_7_4__MSB _u(7) +#define M33_FP_CTRL_NUM_CODE_7_4__LSB _u(4) +#define M33_FP_CTRL_NUM_CODE_7_4__ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_KEY +// Description : Writes to the FP_CTRL are ignored unless KEY is concurrently +// written to one +#define M33_FP_CTRL_KEY_RESET _u(0x0) +#define M33_FP_CTRL_KEY_BITS _u(0x00000002) +#define M33_FP_CTRL_KEY_MSB _u(1) +#define M33_FP_CTRL_KEY_LSB _u(1) +#define M33_FP_CTRL_KEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_ENABLE +// Description : Enables the FPB +#define M33_FP_CTRL_ENABLE_RESET _u(0x0) +#define M33_FP_CTRL_ENABLE_BITS _u(0x00000001) +#define M33_FP_CTRL_ENABLE_MSB _u(0) +#define M33_FP_CTRL_ENABLE_LSB _u(0) +#define M33_FP_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_REMAP +// Description : Indicates whether the implementation supports Flash Patch remap +// and, if it does, holds the target address for remap +#define M33_FP_REMAP_OFFSET _u(0x00002004) +#define M33_FP_REMAP_BITS _u(0x3fffffe0) +#define M33_FP_REMAP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_REMAP_RMPSPT +// Description : Indicates whether the FPB unit supports the Flash Patch remap +// function +#define M33_FP_REMAP_RMPSPT_RESET _u(0x0) +#define M33_FP_REMAP_RMPSPT_BITS _u(0x20000000) +#define M33_FP_REMAP_RMPSPT_MSB _u(29) +#define M33_FP_REMAP_RMPSPT_LSB _u(29) +#define M33_FP_REMAP_RMPSPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_REMAP_REMAP +// Description : Holds the bits[28:5] of the Flash Patch remap address +#define M33_FP_REMAP_REMAP_RESET _u(0x000000) +#define M33_FP_REMAP_REMAP_BITS _u(0x1fffffe0) +#define M33_FP_REMAP_REMAP_MSB _u(28) +#define M33_FP_REMAP_REMAP_LSB _u(5) +#define M33_FP_REMAP_REMAP_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_COMP0 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP0_OFFSET _u(0x00002008) +#define M33_FP_COMP0_BITS _u(0x00000001) +#define M33_FP_COMP0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP0_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP0_BE_RESET _u(0x0) +#define M33_FP_COMP0_BE_BITS _u(0x00000001) +#define M33_FP_COMP0_BE_MSB _u(0) +#define M33_FP_COMP0_BE_LSB _u(0) +#define M33_FP_COMP0_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP1 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP1_OFFSET _u(0x0000200c) +#define M33_FP_COMP1_BITS _u(0x00000001) +#define M33_FP_COMP1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP1_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP1_BE_RESET _u(0x0) +#define M33_FP_COMP1_BE_BITS _u(0x00000001) +#define M33_FP_COMP1_BE_MSB _u(0) +#define M33_FP_COMP1_BE_LSB _u(0) +#define M33_FP_COMP1_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP2 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP2_OFFSET _u(0x00002010) +#define M33_FP_COMP2_BITS _u(0x00000001) +#define M33_FP_COMP2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP2_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP2_BE_RESET _u(0x0) +#define M33_FP_COMP2_BE_BITS _u(0x00000001) +#define M33_FP_COMP2_BE_MSB _u(0) +#define M33_FP_COMP2_BE_LSB _u(0) +#define M33_FP_COMP2_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP3 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP3_OFFSET _u(0x00002014) +#define M33_FP_COMP3_BITS _u(0x00000001) +#define M33_FP_COMP3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP3_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP3_BE_RESET _u(0x0) +#define M33_FP_COMP3_BE_BITS _u(0x00000001) +#define M33_FP_COMP3_BE_MSB _u(0) +#define M33_FP_COMP3_BE_LSB _u(0) +#define M33_FP_COMP3_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP4 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP4_OFFSET _u(0x00002018) +#define M33_FP_COMP4_BITS _u(0x00000001) +#define M33_FP_COMP4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP4_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP4_BE_RESET _u(0x0) +#define M33_FP_COMP4_BE_BITS _u(0x00000001) +#define M33_FP_COMP4_BE_MSB _u(0) +#define M33_FP_COMP4_BE_LSB _u(0) +#define M33_FP_COMP4_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP5 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP5_OFFSET _u(0x0000201c) +#define M33_FP_COMP5_BITS _u(0x00000001) +#define M33_FP_COMP5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP5_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP5_BE_RESET _u(0x0) +#define M33_FP_COMP5_BE_BITS _u(0x00000001) +#define M33_FP_COMP5_BE_MSB _u(0) +#define M33_FP_COMP5_BE_LSB _u(0) +#define M33_FP_COMP5_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP6 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP6_OFFSET _u(0x00002020) +#define M33_FP_COMP6_BITS _u(0x00000001) +#define M33_FP_COMP6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP6_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP6_BE_RESET _u(0x0) +#define M33_FP_COMP6_BE_BITS _u(0x00000001) +#define M33_FP_COMP6_BE_MSB _u(0) +#define M33_FP_COMP6_BE_LSB _u(0) +#define M33_FP_COMP6_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP7 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP7_OFFSET _u(0x00002024) +#define M33_FP_COMP7_BITS _u(0x00000001) +#define M33_FP_COMP7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP7_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP7_BE_RESET _u(0x0) +#define M33_FP_COMP7_BE_BITS _u(0x00000001) +#define M33_FP_COMP7_BE_MSB _u(0) +#define M33_FP_COMP7_BE_LSB _u(0) +#define M33_FP_COMP7_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_DEVARCH +// Description : Provides CoreSight discovery information for the FPB +#define M33_FP_DEVARCH_OFFSET _u(0x00002fbc) +#define M33_FP_DEVARCH_BITS _u(0xffffffff) +#define M33_FP_DEVARCH_RESET _u(0x47701a03) +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_FP_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_FP_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_FP_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_FP_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_FP_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_FP_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_FP_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_FP_DEVARCH_PRESENT_MSB _u(20) +#define M33_FP_DEVARCH_PRESENT_LSB _u(20) +#define M33_FP_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_FP_DEVARCH_REVISION_RESET _u(0x0) +#define M33_FP_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_FP_DEVARCH_REVISION_MSB _u(19) +#define M33_FP_DEVARCH_REVISION_LSB _u(16) +#define M33_FP_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_FP_DEVARCH_ARCHVER_RESET _u(0x1) +#define M33_FP_DEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_FP_DEVARCH_ARCHVER_MSB _u(15) +#define M33_FP_DEVARCH_ARCHVER_LSB _u(12) +#define M33_FP_DEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_FP_DEVARCH_ARCHPART_RESET _u(0xa03) +#define M33_FP_DEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_FP_DEVARCH_ARCHPART_MSB _u(11) +#define M33_FP_DEVARCH_ARCHPART_LSB _u(0) +#define M33_FP_DEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_DEVTYPE +// Description : Provides CoreSight discovery information for the FPB +#define M33_FP_DEVTYPE_OFFSET _u(0x00002fcc) +#define M33_FP_DEVTYPE_BITS _u(0x000000ff) +#define M33_FP_DEVTYPE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVTYPE_SUB +// Description : Component sub-type +#define M33_FP_DEVTYPE_SUB_RESET _u(0x0) +#define M33_FP_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_FP_DEVTYPE_SUB_MSB _u(7) +#define M33_FP_DEVTYPE_SUB_LSB _u(4) +#define M33_FP_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVTYPE_MAJOR +// Description : Component major type +#define M33_FP_DEVTYPE_MAJOR_RESET _u(0x0) +#define M33_FP_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_FP_DEVTYPE_MAJOR_MSB _u(3) +#define M33_FP_DEVTYPE_MAJOR_LSB _u(0) +#define M33_FP_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR4 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR4_OFFSET _u(0x00002fd0) +#define M33_FP_PIDR4_BITS _u(0x000000ff) +#define M33_FP_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR4_SIZE_RESET _u(0x0) +#define M33_FP_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_FP_PIDR4_SIZE_MSB _u(7) +#define M33_FP_PIDR4_SIZE_LSB _u(4) +#define M33_FP_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR4_DES_2_RESET _u(0x4) +#define M33_FP_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_FP_PIDR4_DES_2_MSB _u(3) +#define M33_FP_PIDR4_DES_2_LSB _u(0) +#define M33_FP_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR5 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR5_OFFSET _u(0x00002fd4) +#define M33_FP_PIDR5_BITS _u(0x00000000) +#define M33_FP_PIDR5_RESET _u(0x00000000) +#define M33_FP_PIDR5_MSB _u(31) +#define M33_FP_PIDR5_LSB _u(0) +#define M33_FP_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_PIDR6 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR6_OFFSET _u(0x00002fd8) +#define M33_FP_PIDR6_BITS _u(0x00000000) +#define M33_FP_PIDR6_RESET _u(0x00000000) +#define M33_FP_PIDR6_MSB _u(31) +#define M33_FP_PIDR6_LSB _u(0) +#define M33_FP_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_PIDR7 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR7_OFFSET _u(0x00002fdc) +#define M33_FP_PIDR7_BITS _u(0x00000000) +#define M33_FP_PIDR7_RESET _u(0x00000000) +#define M33_FP_PIDR7_MSB _u(31) +#define M33_FP_PIDR7_LSB _u(0) +#define M33_FP_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_PIDR0 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR0_OFFSET _u(0x00002fe0) +#define M33_FP_PIDR0_BITS _u(0x000000ff) +#define M33_FP_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR0_PART_0_RESET _u(0x21) +#define M33_FP_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_FP_PIDR0_PART_0_MSB _u(7) +#define M33_FP_PIDR0_PART_0_LSB _u(0) +#define M33_FP_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR1 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR1_OFFSET _u(0x00002fe4) +#define M33_FP_PIDR1_BITS _u(0x000000ff) +#define M33_FP_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR1_DES_0_RESET _u(0xb) +#define M33_FP_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_FP_PIDR1_DES_0_MSB _u(7) +#define M33_FP_PIDR1_DES_0_LSB _u(4) +#define M33_FP_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR1_PART_1_RESET _u(0xd) +#define M33_FP_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_FP_PIDR1_PART_1_MSB _u(3) +#define M33_FP_PIDR1_PART_1_LSB _u(0) +#define M33_FP_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR2 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR2_OFFSET _u(0x00002fe8) +#define M33_FP_PIDR2_BITS _u(0x000000ff) +#define M33_FP_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR2_REVISION_RESET _u(0x0) +#define M33_FP_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_FP_PIDR2_REVISION_MSB _u(7) +#define M33_FP_PIDR2_REVISION_LSB _u(4) +#define M33_FP_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR2_JEDEC_RESET _u(0x1) +#define M33_FP_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_FP_PIDR2_JEDEC_MSB _u(3) +#define M33_FP_PIDR2_JEDEC_LSB _u(3) +#define M33_FP_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR2_DES_1_RESET _u(0x3) +#define M33_FP_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_FP_PIDR2_DES_1_MSB _u(2) +#define M33_FP_PIDR2_DES_1_LSB _u(0) +#define M33_FP_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR3 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR3_OFFSET _u(0x00002fec) +#define M33_FP_PIDR3_BITS _u(0x000000ff) +#define M33_FP_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR3_REVAND_RESET _u(0x0) +#define M33_FP_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_FP_PIDR3_REVAND_MSB _u(7) +#define M33_FP_PIDR3_REVAND_LSB _u(4) +#define M33_FP_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR3_CMOD_RESET _u(0x0) +#define M33_FP_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_FP_PIDR3_CMOD_MSB _u(3) +#define M33_FP_PIDR3_CMOD_LSB _u(0) +#define M33_FP_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR0 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR0_OFFSET _u(0x00002ff0) +#define M33_FP_CIDR0_BITS _u(0x000000ff) +#define M33_FP_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_FP_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_FP_CIDR0_PRMBL_0_MSB _u(7) +#define M33_FP_CIDR0_PRMBL_0_LSB _u(0) +#define M33_FP_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR1 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR1_OFFSET _u(0x00002ff4) +#define M33_FP_CIDR1_BITS _u(0x000000ff) +#define M33_FP_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR1_CLASS_RESET _u(0x9) +#define M33_FP_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_FP_CIDR1_CLASS_MSB _u(7) +#define M33_FP_CIDR1_CLASS_LSB _u(4) +#define M33_FP_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_FP_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_FP_CIDR1_PRMBL_1_MSB _u(3) +#define M33_FP_CIDR1_PRMBL_1_LSB _u(0) +#define M33_FP_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR2 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR2_OFFSET _u(0x00002ff8) +#define M33_FP_CIDR2_BITS _u(0x000000ff) +#define M33_FP_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_FP_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_FP_CIDR2_PRMBL_2_MSB _u(7) +#define M33_FP_CIDR2_PRMBL_2_LSB _u(0) +#define M33_FP_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR3 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR3_OFFSET _u(0x00002ffc) +#define M33_FP_CIDR3_BITS _u(0x000000ff) +#define M33_FP_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_FP_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_FP_CIDR3_PRMBL_3_MSB _u(7) +#define M33_FP_CIDR3_PRMBL_3_LSB _u(0) +#define M33_FP_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_ICTR +// Description : Provides information about the interrupt controller +#define M33_ICTR_OFFSET _u(0x0000e004) +#define M33_ICTR_BITS _u(0x0000000f) +#define M33_ICTR_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : M33_ICTR_INTLINESNUM +// Description : Indicates the number of the highest implemented register in +// each of the NVIC control register sets, or in the case of +// NVIC_IPR*n, 4×INTLINESNUM +#define M33_ICTR_INTLINESNUM_RESET _u(0x1) +#define M33_ICTR_INTLINESNUM_BITS _u(0x0000000f) +#define M33_ICTR_INTLINESNUM_MSB _u(3) +#define M33_ICTR_INTLINESNUM_LSB _u(0) +#define M33_ICTR_INTLINESNUM_ACCESS "RO" +// ============================================================================= +// Register : M33_ACTLR +// Description : Provides IMPLEMENTATION DEFINED configuration and control +// options +#define M33_ACTLR_OFFSET _u(0x0000e008) +#define M33_ACTLR_BITS _u(0x20001605) +#define M33_ACTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_EXTEXCLALL +// Description : External Exclusives Allowed with no MPU +#define M33_ACTLR_EXTEXCLALL_RESET _u(0x0) +#define M33_ACTLR_EXTEXCLALL_BITS _u(0x20000000) +#define M33_ACTLR_EXTEXCLALL_MSB _u(29) +#define M33_ACTLR_EXTEXCLALL_LSB _u(29) +#define M33_ACTLR_EXTEXCLALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISITMATBFLUSH +// Description : Disable ATB Flush +#define M33_ACTLR_DISITMATBFLUSH_RESET _u(0x0) +#define M33_ACTLR_DISITMATBFLUSH_BITS _u(0x00001000) +#define M33_ACTLR_DISITMATBFLUSH_MSB _u(12) +#define M33_ACTLR_DISITMATBFLUSH_LSB _u(12) +#define M33_ACTLR_DISITMATBFLUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_FPEXCODIS +// Description : Disable FPU exception outputs +#define M33_ACTLR_FPEXCODIS_RESET _u(0x0) +#define M33_ACTLR_FPEXCODIS_BITS _u(0x00000400) +#define M33_ACTLR_FPEXCODIS_MSB _u(10) +#define M33_ACTLR_FPEXCODIS_LSB _u(10) +#define M33_ACTLR_FPEXCODIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISOOFP +// Description : Disable out-of-order FP instruction completion +#define M33_ACTLR_DISOOFP_RESET _u(0x0) +#define M33_ACTLR_DISOOFP_BITS _u(0x00000200) +#define M33_ACTLR_DISOOFP_MSB _u(9) +#define M33_ACTLR_DISOOFP_LSB _u(9) +#define M33_ACTLR_DISOOFP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISFOLD +// Description : Disable dual-issue. +#define M33_ACTLR_DISFOLD_RESET _u(0x0) +#define M33_ACTLR_DISFOLD_BITS _u(0x00000004) +#define M33_ACTLR_DISFOLD_MSB _u(2) +#define M33_ACTLR_DISFOLD_LSB _u(2) +#define M33_ACTLR_DISFOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISMCYCINT +// Description : Disable dual-issue. +#define M33_ACTLR_DISMCYCINT_RESET _u(0x0) +#define M33_ACTLR_DISMCYCINT_BITS _u(0x00000001) +#define M33_ACTLR_DISMCYCINT_MSB _u(0) +#define M33_ACTLR_DISMCYCINT_LSB _u(0) +#define M33_ACTLR_DISMCYCINT_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_CSR +// Description : Use the SysTick Control and Status Register to enable the +// SysTick features. +#define M33_SYST_CSR_OFFSET _u(0x0000e010) +#define M33_SYST_CSR_BITS _u(0x00010007) +#define M33_SYST_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_COUNTFLAG +// Description : Returns 1 if timer counted to 0 since last time this was read. +// Clears on read by application or debugger. +#define M33_SYST_CSR_COUNTFLAG_RESET _u(0x0) +#define M33_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) +#define M33_SYST_CSR_COUNTFLAG_MSB _u(16) +#define M33_SYST_CSR_COUNTFLAG_LSB _u(16) +#define M33_SYST_CSR_COUNTFLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_CLKSOURCE +// Description : SysTick clock source. Always reads as one if SYST_CALIB reports +// NOREF. +// Selects the SysTick timer clock source: +// 0 = External reference clock. +// 1 = Processor clock. +#define M33_SYST_CSR_CLKSOURCE_RESET _u(0x0) +#define M33_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) +#define M33_SYST_CSR_CLKSOURCE_MSB _u(2) +#define M33_SYST_CSR_CLKSOURCE_LSB _u(2) +#define M33_SYST_CSR_CLKSOURCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_TICKINT +// Description : Enables SysTick exception request: +// 0 = Counting down to zero does not assert the SysTick exception +// request. +// 1 = Counting down to zero to asserts the SysTick exception +// request. +#define M33_SYST_CSR_TICKINT_RESET _u(0x0) +#define M33_SYST_CSR_TICKINT_BITS _u(0x00000002) +#define M33_SYST_CSR_TICKINT_MSB _u(1) +#define M33_SYST_CSR_TICKINT_LSB _u(1) +#define M33_SYST_CSR_TICKINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_ENABLE +// Description : Enable SysTick counter: +// 0 = Counter disabled. +// 1 = Counter enabled. +#define M33_SYST_CSR_ENABLE_RESET _u(0x0) +#define M33_SYST_CSR_ENABLE_BITS _u(0x00000001) +#define M33_SYST_CSR_ENABLE_MSB _u(0) +#define M33_SYST_CSR_ENABLE_LSB _u(0) +#define M33_SYST_CSR_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_RVR +// Description : Use the SysTick Reload Value Register to specify the start +// value to load into the current value register when the counter +// reaches 0. It can be any value between 0 and 0x00FFFFFF. A +// start value of 0 is possible, but has no effect because the +// SysTick interrupt and COUNTFLAG are activated when counting +// from 1 to 0. The reset value of this register is UNKNOWN. +// To generate a multi-shot timer with a period of N processor +// clock cycles, use a RELOAD value of N-1. For example, if the +// SysTick interrupt is required every 100 clock pulses, set +// RELOAD to 99. +#define M33_SYST_RVR_OFFSET _u(0x0000e014) +#define M33_SYST_RVR_BITS _u(0x00ffffff) +#define M33_SYST_RVR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_RVR_RELOAD +// Description : Value to load into the SysTick Current Value Register when the +// counter reaches 0. +#define M33_SYST_RVR_RELOAD_RESET _u(0x000000) +#define M33_SYST_RVR_RELOAD_BITS _u(0x00ffffff) +#define M33_SYST_RVR_RELOAD_MSB _u(23) +#define M33_SYST_RVR_RELOAD_LSB _u(0) +#define M33_SYST_RVR_RELOAD_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_CVR +// Description : Use the SysTick Current Value Register to find the current +// value in the register. The reset value of this register is +// UNKNOWN. +#define M33_SYST_CVR_OFFSET _u(0x0000e018) +#define M33_SYST_CVR_BITS _u(0x00ffffff) +#define M33_SYST_CVR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CVR_CURRENT +// Description : Reads return the current value of the SysTick counter. This +// register is write-clear. Writing to it with any value clears +// the register to 0. Clearing this register also clears the +// COUNTFLAG bit of the SysTick Control and Status Register. +#define M33_SYST_CVR_CURRENT_RESET _u(0x000000) +#define M33_SYST_CVR_CURRENT_BITS _u(0x00ffffff) +#define M33_SYST_CVR_CURRENT_MSB _u(23) +#define M33_SYST_CVR_CURRENT_LSB _u(0) +#define M33_SYST_CVR_CURRENT_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_CALIB +// Description : Use the SysTick Calibration Value Register to enable software +// to scale to any required speed using divide and multiply. +#define M33_SYST_CALIB_OFFSET _u(0x0000e01c) +#define M33_SYST_CALIB_BITS _u(0xc0ffffff) +#define M33_SYST_CALIB_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CALIB_NOREF +// Description : If reads as 1, the Reference clock is not provided - the +// CLKSOURCE bit of the SysTick Control and Status register will +// be forced to 1 and cannot be cleared to 0. +#define M33_SYST_CALIB_NOREF_RESET _u(0x0) +#define M33_SYST_CALIB_NOREF_BITS _u(0x80000000) +#define M33_SYST_CALIB_NOREF_MSB _u(31) +#define M33_SYST_CALIB_NOREF_LSB _u(31) +#define M33_SYST_CALIB_NOREF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CALIB_SKEW +// Description : If reads as 1, the calibration value for 10ms is inexact (due +// to clock frequency). +#define M33_SYST_CALIB_SKEW_RESET _u(0x0) +#define M33_SYST_CALIB_SKEW_BITS _u(0x40000000) +#define M33_SYST_CALIB_SKEW_MSB _u(30) +#define M33_SYST_CALIB_SKEW_LSB _u(30) +#define M33_SYST_CALIB_SKEW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CALIB_TENMS +// Description : An optional Reload value to be used for 10ms (100Hz) timing, +// subject to system clock skew errors. If the value reads as 0, +// the calibration value is not known. +#define M33_SYST_CALIB_TENMS_RESET _u(0x000000) +#define M33_SYST_CALIB_TENMS_BITS _u(0x00ffffff) +#define M33_SYST_CALIB_TENMS_MSB _u(23) +#define M33_SYST_CALIB_TENMS_LSB _u(0) +#define M33_SYST_CALIB_TENMS_ACCESS "RO" +// ============================================================================= +// Register : M33_NVIC_ISER0 +// Description : Enables or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ISER0_OFFSET _u(0x0000e100) +#define M33_NVIC_ISER0_BITS _u(0xffffffff) +#define M33_NVIC_ISER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISER0_SETENA +// Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ISER0_SETENA_RESET _u(0x00000000) +#define M33_NVIC_ISER0_SETENA_BITS _u(0xffffffff) +#define M33_NVIC_ISER0_SETENA_MSB _u(31) +#define M33_NVIC_ISER0_SETENA_LSB _u(0) +#define M33_NVIC_ISER0_SETENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ISER1 +// Description : Enables or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ISER1_OFFSET _u(0x0000e104) +#define M33_NVIC_ISER1_BITS _u(0xffffffff) +#define M33_NVIC_ISER1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISER1_SETENA +// Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ISER1_SETENA_RESET _u(0x00000000) +#define M33_NVIC_ISER1_SETENA_BITS _u(0xffffffff) +#define M33_NVIC_ISER1_SETENA_MSB _u(31) +#define M33_NVIC_ISER1_SETENA_LSB _u(0) +#define M33_NVIC_ISER1_SETENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICER0 +// Description : Clears or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ICER0_OFFSET _u(0x0000e180) +#define M33_NVIC_ICER0_BITS _u(0xffffffff) +#define M33_NVIC_ICER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICER0_CLRENA +// Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ICER0_CLRENA_RESET _u(0x00000000) +#define M33_NVIC_ICER0_CLRENA_BITS _u(0xffffffff) +#define M33_NVIC_ICER0_CLRENA_MSB _u(31) +#define M33_NVIC_ICER0_CLRENA_LSB _u(0) +#define M33_NVIC_ICER0_CLRENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICER1 +// Description : Clears or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ICER1_OFFSET _u(0x0000e184) +#define M33_NVIC_ICER1_BITS _u(0xffffffff) +#define M33_NVIC_ICER1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICER1_CLRENA +// Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ICER1_CLRENA_RESET _u(0x00000000) +#define M33_NVIC_ICER1_CLRENA_BITS _u(0xffffffff) +#define M33_NVIC_ICER1_CLRENA_MSB _u(31) +#define M33_NVIC_ICER1_CLRENA_LSB _u(0) +#define M33_NVIC_ICER1_CLRENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ISPR0 +// Description : Enables or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ISPR0_OFFSET _u(0x0000e200) +#define M33_NVIC_ISPR0_BITS _u(0xffffffff) +#define M33_NVIC_ISPR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISPR0_SETPEND +// Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ISPR0_SETPEND_RESET _u(0x00000000) +#define M33_NVIC_ISPR0_SETPEND_BITS _u(0xffffffff) +#define M33_NVIC_ISPR0_SETPEND_MSB _u(31) +#define M33_NVIC_ISPR0_SETPEND_LSB _u(0) +#define M33_NVIC_ISPR0_SETPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ISPR1 +// Description : Enables or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ISPR1_OFFSET _u(0x0000e204) +#define M33_NVIC_ISPR1_BITS _u(0xffffffff) +#define M33_NVIC_ISPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISPR1_SETPEND +// Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ISPR1_SETPEND_RESET _u(0x00000000) +#define M33_NVIC_ISPR1_SETPEND_BITS _u(0xffffffff) +#define M33_NVIC_ISPR1_SETPEND_MSB _u(31) +#define M33_NVIC_ISPR1_SETPEND_LSB _u(0) +#define M33_NVIC_ISPR1_SETPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICPR0 +// Description : Clears or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ICPR0_OFFSET _u(0x0000e280) +#define M33_NVIC_ICPR0_BITS _u(0xffffffff) +#define M33_NVIC_ICPR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICPR0_CLRPEND +// Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ICPR0_CLRPEND_RESET _u(0x00000000) +#define M33_NVIC_ICPR0_CLRPEND_BITS _u(0xffffffff) +#define M33_NVIC_ICPR0_CLRPEND_MSB _u(31) +#define M33_NVIC_ICPR0_CLRPEND_LSB _u(0) +#define M33_NVIC_ICPR0_CLRPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICPR1 +// Description : Clears or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ICPR1_OFFSET _u(0x0000e284) +#define M33_NVIC_ICPR1_BITS _u(0xffffffff) +#define M33_NVIC_ICPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICPR1_CLRPEND +// Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ICPR1_CLRPEND_RESET _u(0x00000000) +#define M33_NVIC_ICPR1_CLRPEND_BITS _u(0xffffffff) +#define M33_NVIC_ICPR1_CLRPEND_MSB _u(31) +#define M33_NVIC_ICPR1_CLRPEND_LSB _u(0) +#define M33_NVIC_ICPR1_CLRPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IABR0 +// Description : For each group of 32 interrupts, shows the active state of each +// interrupt +#define M33_NVIC_IABR0_OFFSET _u(0x0000e300) +#define M33_NVIC_IABR0_BITS _u(0xffffffff) +#define M33_NVIC_IABR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IABR0_ACTIVE +// Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for +// interrupt 32*n+m +#define M33_NVIC_IABR0_ACTIVE_RESET _u(0x00000000) +#define M33_NVIC_IABR0_ACTIVE_BITS _u(0xffffffff) +#define M33_NVIC_IABR0_ACTIVE_MSB _u(31) +#define M33_NVIC_IABR0_ACTIVE_LSB _u(0) +#define M33_NVIC_IABR0_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IABR1 +// Description : For each group of 32 interrupts, shows the active state of each +// interrupt +#define M33_NVIC_IABR1_OFFSET _u(0x0000e304) +#define M33_NVIC_IABR1_BITS _u(0xffffffff) +#define M33_NVIC_IABR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IABR1_ACTIVE +// Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for +// interrupt 32*n+m +#define M33_NVIC_IABR1_ACTIVE_RESET _u(0x00000000) +#define M33_NVIC_IABR1_ACTIVE_BITS _u(0xffffffff) +#define M33_NVIC_IABR1_ACTIVE_MSB _u(31) +#define M33_NVIC_IABR1_ACTIVE_LSB _u(0) +#define M33_NVIC_IABR1_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ITNS0 +// Description : For each group of 32 interrupts, determines whether each +// interrupt targets Non-secure or Secure state +#define M33_NVIC_ITNS0_OFFSET _u(0x0000e380) +#define M33_NVIC_ITNS0_BITS _u(0xffffffff) +#define M33_NVIC_ITNS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ITNS0_ITNS +// Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state +// for interrupt 32*n+m +#define M33_NVIC_ITNS0_ITNS_RESET _u(0x00000000) +#define M33_NVIC_ITNS0_ITNS_BITS _u(0xffffffff) +#define M33_NVIC_ITNS0_ITNS_MSB _u(31) +#define M33_NVIC_ITNS0_ITNS_LSB _u(0) +#define M33_NVIC_ITNS0_ITNS_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ITNS1 +// Description : For each group of 32 interrupts, determines whether each +// interrupt targets Non-secure or Secure state +#define M33_NVIC_ITNS1_OFFSET _u(0x0000e384) +#define M33_NVIC_ITNS1_BITS _u(0xffffffff) +#define M33_NVIC_ITNS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ITNS1_ITNS +// Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state +// for interrupt 32*n+m +#define M33_NVIC_ITNS1_ITNS_RESET _u(0x00000000) +#define M33_NVIC_ITNS1_ITNS_BITS _u(0xffffffff) +#define M33_NVIC_ITNS1_ITNS_MSB _u(31) +#define M33_NVIC_ITNS1_ITNS_LSB _u(0) +#define M33_NVIC_ITNS1_ITNS_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR0 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR0_OFFSET _u(0x0000e400) +#define M33_NVIC_IPR0_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR0_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR0_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR0_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR0_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR0_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR0_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR0_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR0_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR0_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR0_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR0_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR0_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR1 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR1_OFFSET _u(0x0000e404) +#define M33_NVIC_IPR1_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR1_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR1_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR1_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR1_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR1_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR1_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR1_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR1_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR1_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR1_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR1_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR1_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR2 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR2_OFFSET _u(0x0000e408) +#define M33_NVIC_IPR2_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR2_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR2_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR2_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR2_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR2_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR2_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR2_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR2_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR2_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR2_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR2_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR2_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR3 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR3_OFFSET _u(0x0000e40c) +#define M33_NVIC_IPR3_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR3_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR3_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR3_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR3_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR3_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR3_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR3_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR3_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR3_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR3_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR3_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR3_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR4 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR4_OFFSET _u(0x0000e410) +#define M33_NVIC_IPR4_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR4_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR4_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR4_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR4_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR4_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR4_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR4_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR4_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR4_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR4_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR4_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR4_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR5 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR5_OFFSET _u(0x0000e414) +#define M33_NVIC_IPR5_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR5_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR5_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR5_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR5_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR5_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR5_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR5_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR5_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR5_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR5_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR5_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR5_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR6 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR6_OFFSET _u(0x0000e418) +#define M33_NVIC_IPR6_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR6_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR6_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR6_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR6_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR6_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR6_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR6_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR6_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR6_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR6_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR6_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR6_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR7 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR7_OFFSET _u(0x0000e41c) +#define M33_NVIC_IPR7_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR7_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR7_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR7_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR7_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR7_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR7_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR7_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR7_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR7_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR7_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR7_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR7_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR8 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR8_OFFSET _u(0x0000e420) +#define M33_NVIC_IPR8_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR8_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR8_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR8_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR8_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR8_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR8_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR8_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR8_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR8_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR8_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR8_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR8_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR9 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR9_OFFSET _u(0x0000e424) +#define M33_NVIC_IPR9_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR9_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR9_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR9_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR9_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR9_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR9_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR9_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR9_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR9_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR9_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR9_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR9_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR10 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR10_OFFSET _u(0x0000e428) +#define M33_NVIC_IPR10_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR10_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR10_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR10_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR10_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR10_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR10_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR10_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR10_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR10_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR10_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR10_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR10_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR11 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR11_OFFSET _u(0x0000e42c) +#define M33_NVIC_IPR11_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR11_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR11_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR11_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR11_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR11_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR11_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR11_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR11_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR11_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR11_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR11_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR11_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR12 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR12_OFFSET _u(0x0000e430) +#define M33_NVIC_IPR12_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR12_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR12_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR12_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR12_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR12_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR12_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR12_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR12_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR12_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR12_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR12_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR12_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR13 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR13_OFFSET _u(0x0000e434) +#define M33_NVIC_IPR13_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR13_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR13_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR13_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR13_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR13_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR13_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR13_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR13_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR13_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR13_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR13_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR13_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR14 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR14_OFFSET _u(0x0000e438) +#define M33_NVIC_IPR14_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR14_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR14_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR14_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR14_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR14_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR14_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR14_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR14_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR14_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR14_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR14_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR14_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR15 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR15_OFFSET _u(0x0000e43c) +#define M33_NVIC_IPR15_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR15_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR15_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR15_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR15_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR15_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR15_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR15_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR15_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR15_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR15_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR15_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR15_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_CPUID +// Description : Provides identification information for the PE, including an +// implementer code for the device and a device ID number +#define M33_CPUID_OFFSET _u(0x0000ed00) +#define M33_CPUID_BITS _u(0xffffffff) +#define M33_CPUID_RESET _u(0x411fd210) +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_IMPLEMENTER +// Description : This field must hold an implementer code that has been assigned +// by ARM +#define M33_CPUID_IMPLEMENTER_RESET _u(0x41) +#define M33_CPUID_IMPLEMENTER_BITS _u(0xff000000) +#define M33_CPUID_IMPLEMENTER_MSB _u(31) +#define M33_CPUID_IMPLEMENTER_LSB _u(24) +#define M33_CPUID_IMPLEMENTER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_VARIANT +// Description : IMPLEMENTATION DEFINED variant number. Typically, this field is +// used to distinguish between different product variants, or +// major revisions of a product +#define M33_CPUID_VARIANT_RESET _u(0x1) +#define M33_CPUID_VARIANT_BITS _u(0x00f00000) +#define M33_CPUID_VARIANT_MSB _u(23) +#define M33_CPUID_VARIANT_LSB _u(20) +#define M33_CPUID_VARIANT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_ARCHITECTURE +// Description : Defines the Architecture implemented by the PE +#define M33_CPUID_ARCHITECTURE_RESET _u(0xf) +#define M33_CPUID_ARCHITECTURE_BITS _u(0x000f0000) +#define M33_CPUID_ARCHITECTURE_MSB _u(19) +#define M33_CPUID_ARCHITECTURE_LSB _u(16) +#define M33_CPUID_ARCHITECTURE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_PARTNO +// Description : IMPLEMENTATION DEFINED primary part number for the device +#define M33_CPUID_PARTNO_RESET _u(0xd21) +#define M33_CPUID_PARTNO_BITS _u(0x0000fff0) +#define M33_CPUID_PARTNO_MSB _u(15) +#define M33_CPUID_PARTNO_LSB _u(4) +#define M33_CPUID_PARTNO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_REVISION +// Description : IMPLEMENTATION DEFINED revision number for the device +#define M33_CPUID_REVISION_RESET _u(0x0) +#define M33_CPUID_REVISION_BITS _u(0x0000000f) +#define M33_CPUID_REVISION_MSB _u(3) +#define M33_CPUID_REVISION_LSB _u(0) +#define M33_CPUID_REVISION_ACCESS "RO" +// ============================================================================= +// Register : M33_ICSR +// Description : Controls and provides status information for NMI, PendSV, +// SysTick and interrupts +#define M33_ICSR_OFFSET _u(0x0000ed04) +#define M33_ICSR_BITS _u(0xdfdff9ff) +#define M33_ICSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDNMISET +// Description : Indicates whether the NMI exception is pending +#define M33_ICSR_PENDNMISET_RESET _u(0x0) +#define M33_ICSR_PENDNMISET_BITS _u(0x80000000) +#define M33_ICSR_PENDNMISET_MSB _u(31) +#define M33_ICSR_PENDNMISET_LSB _u(31) +#define M33_ICSR_PENDNMISET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDNMICLR +// Description : Allows the NMI exception pend state to be cleared +#define M33_ICSR_PENDNMICLR_RESET _u(0x0) +#define M33_ICSR_PENDNMICLR_BITS _u(0x40000000) +#define M33_ICSR_PENDNMICLR_MSB _u(30) +#define M33_ICSR_PENDNMICLR_LSB _u(30) +#define M33_ICSR_PENDNMICLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSVSET +// Description : Indicates whether the PendSV `FTSSS exception is pending +#define M33_ICSR_PENDSVSET_RESET _u(0x0) +#define M33_ICSR_PENDSVSET_BITS _u(0x10000000) +#define M33_ICSR_PENDSVSET_MSB _u(28) +#define M33_ICSR_PENDSVSET_LSB _u(28) +#define M33_ICSR_PENDSVSET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSVCLR +// Description : Allows the PendSV exception pend state to be cleared `FTSSS +#define M33_ICSR_PENDSVCLR_RESET _u(0x0) +#define M33_ICSR_PENDSVCLR_BITS _u(0x08000000) +#define M33_ICSR_PENDSVCLR_MSB _u(27) +#define M33_ICSR_PENDSVCLR_LSB _u(27) +#define M33_ICSR_PENDSVCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSTSET +// Description : Indicates whether the SysTick `FTSSS exception is pending +#define M33_ICSR_PENDSTSET_RESET _u(0x0) +#define M33_ICSR_PENDSTSET_BITS _u(0x04000000) +#define M33_ICSR_PENDSTSET_MSB _u(26) +#define M33_ICSR_PENDSTSET_LSB _u(26) +#define M33_ICSR_PENDSTSET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSTCLR +// Description : Allows the SysTick exception pend state to be cleared `FTSSS +#define M33_ICSR_PENDSTCLR_RESET _u(0x0) +#define M33_ICSR_PENDSTCLR_BITS _u(0x02000000) +#define M33_ICSR_PENDSTCLR_MSB _u(25) +#define M33_ICSR_PENDSTCLR_LSB _u(25) +#define M33_ICSR_PENDSTCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_STTNS +// Description : Controls whether in a single SysTick implementation, the +// SysTick is Secure or Non-secure +#define M33_ICSR_STTNS_RESET _u(0x0) +#define M33_ICSR_STTNS_BITS _u(0x01000000) +#define M33_ICSR_STTNS_MSB _u(24) +#define M33_ICSR_STTNS_LSB _u(24) +#define M33_ICSR_STTNS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_ISRPREEMPT +// Description : Indicates whether a pending exception will be serviced on exit +// from debug halt state +#define M33_ICSR_ISRPREEMPT_RESET _u(0x0) +#define M33_ICSR_ISRPREEMPT_BITS _u(0x00800000) +#define M33_ICSR_ISRPREEMPT_MSB _u(23) +#define M33_ICSR_ISRPREEMPT_LSB _u(23) +#define M33_ICSR_ISRPREEMPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_ISRPENDING +// Description : Indicates whether an external interrupt, generated by the NVIC, +// is pending +#define M33_ICSR_ISRPENDING_RESET _u(0x0) +#define M33_ICSR_ISRPENDING_BITS _u(0x00400000) +#define M33_ICSR_ISRPENDING_MSB _u(22) +#define M33_ICSR_ISRPENDING_LSB _u(22) +#define M33_ICSR_ISRPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_VECTPENDING +// Description : The exception number of the highest priority pending and +// enabled interrupt +#define M33_ICSR_VECTPENDING_RESET _u(0x000) +#define M33_ICSR_VECTPENDING_BITS _u(0x001ff000) +#define M33_ICSR_VECTPENDING_MSB _u(20) +#define M33_ICSR_VECTPENDING_LSB _u(12) +#define M33_ICSR_VECTPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_RETTOBASE +// Description : In Handler mode, indicates whether there is more than one +// active exception +#define M33_ICSR_RETTOBASE_RESET _u(0x0) +#define M33_ICSR_RETTOBASE_BITS _u(0x00000800) +#define M33_ICSR_RETTOBASE_MSB _u(11) +#define M33_ICSR_RETTOBASE_LSB _u(11) +#define M33_ICSR_RETTOBASE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_VECTACTIVE +// Description : The exception number of the current executing exception +#define M33_ICSR_VECTACTIVE_RESET _u(0x000) +#define M33_ICSR_VECTACTIVE_BITS _u(0x000001ff) +#define M33_ICSR_VECTACTIVE_MSB _u(8) +#define M33_ICSR_VECTACTIVE_LSB _u(0) +#define M33_ICSR_VECTACTIVE_ACCESS "RO" +// ============================================================================= +// Register : M33_VTOR +// Description : The VTOR indicates the offset of the vector table base address +// from memory address 0x00000000. +#define M33_VTOR_OFFSET _u(0x0000ed08) +#define M33_VTOR_BITS _u(0xffffff80) +#define M33_VTOR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_VTOR_TBLOFF +// Description : Vector table base offset field. It contains bits[31:7] of the +// offset of the table base from the bottom of the memory map. +#define M33_VTOR_TBLOFF_RESET _u(0x0000000) +#define M33_VTOR_TBLOFF_BITS _u(0xffffff80) +#define M33_VTOR_TBLOFF_MSB _u(31) +#define M33_VTOR_TBLOFF_LSB _u(7) +#define M33_VTOR_TBLOFF_ACCESS "RW" +// ============================================================================= +// Register : M33_AIRCR +// Description : Use the Application Interrupt and Reset Control Register to: +// determine data endianness, clear all active state information +// from debug halt mode, request a system reset. +#define M33_AIRCR_OFFSET _u(0x0000ed0c) +#define M33_AIRCR_BITS _u(0xffffe70e) +#define M33_AIRCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_VECTKEY +// Description : Register key: +// Reads as Unknown +// On writes, write 0x05FA to VECTKEY, otherwise the write is +// ignored. +#define M33_AIRCR_VECTKEY_RESET _u(0x0000) +#define M33_AIRCR_VECTKEY_BITS _u(0xffff0000) +#define M33_AIRCR_VECTKEY_MSB _u(31) +#define M33_AIRCR_VECTKEY_LSB _u(16) +#define M33_AIRCR_VECTKEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_ENDIANESS +// Description : Data endianness implemented: +// 0 = Little-endian. +#define M33_AIRCR_ENDIANESS_RESET _u(0x0) +#define M33_AIRCR_ENDIANESS_BITS _u(0x00008000) +#define M33_AIRCR_ENDIANESS_MSB _u(15) +#define M33_AIRCR_ENDIANESS_LSB _u(15) +#define M33_AIRCR_ENDIANESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_PRIS +// Description : Prioritize Secure exceptions. The value of this bit defines +// whether Secure exception priority boosting is enabled. +// 0 Priority ranges of Secure and Non-secure exceptions are +// identical. +// 1 Non-secure exceptions are de-prioritized. +#define M33_AIRCR_PRIS_RESET _u(0x0) +#define M33_AIRCR_PRIS_BITS _u(0x00004000) +#define M33_AIRCR_PRIS_MSB _u(14) +#define M33_AIRCR_PRIS_LSB _u(14) +#define M33_AIRCR_PRIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_BFHFNMINS +// Description : BusFault, HardFault, and NMI Non-secure enable. +// 0 BusFault, HardFault, and NMI are Secure. +// 1 BusFault and NMI are Non-secure and exceptions can target +// Non-secure HardFault. +#define M33_AIRCR_BFHFNMINS_RESET _u(0x0) +#define M33_AIRCR_BFHFNMINS_BITS _u(0x00002000) +#define M33_AIRCR_BFHFNMINS_MSB _u(13) +#define M33_AIRCR_BFHFNMINS_LSB _u(13) +#define M33_AIRCR_BFHFNMINS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_PRIGROUP +// Description : Interrupt priority grouping field. This field determines the +// split of group priority from subpriority. +// See https://developer.arm.com/documentation/100235/0004/the- +// cortex-m33-peripherals/system-control-block/application- +// interrupt-and-reset-control-register?lang=en +#define M33_AIRCR_PRIGROUP_RESET _u(0x0) +#define M33_AIRCR_PRIGROUP_BITS _u(0x00000700) +#define M33_AIRCR_PRIGROUP_MSB _u(10) +#define M33_AIRCR_PRIGROUP_LSB _u(8) +#define M33_AIRCR_PRIGROUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_SYSRESETREQS +// Description : System reset request, Secure state only. +// 0 SYSRESETREQ functionality is available to both Security +// states. +// 1 SYSRESETREQ functionality is only available to Secure state. +#define M33_AIRCR_SYSRESETREQS_RESET _u(0x0) +#define M33_AIRCR_SYSRESETREQS_BITS _u(0x00000008) +#define M33_AIRCR_SYSRESETREQS_MSB _u(3) +#define M33_AIRCR_SYSRESETREQS_LSB _u(3) +#define M33_AIRCR_SYSRESETREQS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_SYSRESETREQ +// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the +// outer system to be asserted to request a reset. The intention +// is to force a large system reset of all major components except +// for debug. The C_HALT bit in the DHCSR is cleared as a result +// of the system reset requested. The debugger does not lose +// contact with the device. +#define M33_AIRCR_SYSRESETREQ_RESET _u(0x0) +#define M33_AIRCR_SYSRESETREQ_BITS _u(0x00000004) +#define M33_AIRCR_SYSRESETREQ_MSB _u(2) +#define M33_AIRCR_SYSRESETREQ_LSB _u(2) +#define M33_AIRCR_SYSRESETREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_VECTCLRACTIVE +// Description : Clears all active state information for fixed and configurable +// exceptions. This bit: is self-clearing, can only be set by the +// DAP when the core is halted. When set: clears all active +// exception status of the processor, forces a return to Thread +// mode, forces an IPSR of 0. A debugger must re-initialize the +// stack. +#define M33_AIRCR_VECTCLRACTIVE_RESET _u(0x0) +#define M33_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) +#define M33_AIRCR_VECTCLRACTIVE_MSB _u(1) +#define M33_AIRCR_VECTCLRACTIVE_LSB _u(1) +#define M33_AIRCR_VECTCLRACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M33_SCR +// Description : System Control Register. Use the System Control Register for +// power-management functions: signal to the system when the +// processor can enter a low power state, control how the +// processor enters and exits low power states. +#define M33_SCR_OFFSET _u(0x0000ed10) +#define M33_SCR_BITS _u(0x0000001e) +#define M33_SCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SEVONPEND +// Description : Send Event on Pending bit: +// 0 = Only enabled interrupts or events can wakeup the processor, +// disabled interrupts are excluded. +// 1 = Enabled events and all interrupts, including disabled +// interrupts, can wakeup the processor. +// When an event or interrupt becomes pending, the event signal +// wakes up the processor from WFE. If the +// processor is not waiting for an event, the event is registered +// and affects the next WFE. +// The processor also wakes up on execution of an SEV instruction +// or an external event. +#define M33_SCR_SEVONPEND_RESET _u(0x0) +#define M33_SCR_SEVONPEND_BITS _u(0x00000010) +#define M33_SCR_SEVONPEND_MSB _u(4) +#define M33_SCR_SEVONPEND_LSB _u(4) +#define M33_SCR_SEVONPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SLEEPDEEPS +// Description : 0 SLEEPDEEP is available to both security states +// 1 SLEEPDEEP is only available to Secure state +#define M33_SCR_SLEEPDEEPS_RESET _u(0x0) +#define M33_SCR_SLEEPDEEPS_BITS _u(0x00000008) +#define M33_SCR_SLEEPDEEPS_MSB _u(3) +#define M33_SCR_SLEEPDEEPS_LSB _u(3) +#define M33_SCR_SLEEPDEEPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SLEEPDEEP +// Description : Controls whether the processor uses sleep or deep sleep as its +// low power mode: +// 0 = Sleep. +// 1 = Deep sleep. +#define M33_SCR_SLEEPDEEP_RESET _u(0x0) +#define M33_SCR_SLEEPDEEP_BITS _u(0x00000004) +#define M33_SCR_SLEEPDEEP_MSB _u(2) +#define M33_SCR_SLEEPDEEP_LSB _u(2) +#define M33_SCR_SLEEPDEEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SLEEPONEXIT +// Description : Indicates sleep-on-exit when returning from Handler mode to +// Thread mode: +// 0 = Do not sleep when returning to Thread mode. +// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread +// mode. +// Setting this bit to 1 enables an interrupt driven application +// to avoid returning to an empty main application. +#define M33_SCR_SLEEPONEXIT_RESET _u(0x0) +#define M33_SCR_SLEEPONEXIT_BITS _u(0x00000002) +#define M33_SCR_SLEEPONEXIT_MSB _u(1) +#define M33_SCR_SLEEPONEXIT_LSB _u(1) +#define M33_SCR_SLEEPONEXIT_ACCESS "RW" +// ============================================================================= +// Register : M33_CCR +// Description : Sets or returns configuration and control data +#define M33_CCR_OFFSET _u(0x0000ed14) +#define M33_CCR_BITS _u(0x0007071b) +#define M33_CCR_RESET _u(0x00000201) +// ----------------------------------------------------------------------------- +// Field : M33_CCR_BP +// Description : Enables program flow prediction `FTSSS +#define M33_CCR_BP_RESET _u(0x0) +#define M33_CCR_BP_BITS _u(0x00040000) +#define M33_CCR_BP_MSB _u(18) +#define M33_CCR_BP_LSB _u(18) +#define M33_CCR_BP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_IC +// Description : This is a global enable bit for instruction caches in the +// selected Security state +#define M33_CCR_IC_RESET _u(0x0) +#define M33_CCR_IC_BITS _u(0x00020000) +#define M33_CCR_IC_MSB _u(17) +#define M33_CCR_IC_LSB _u(17) +#define M33_CCR_IC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_DC +// Description : Enables data caching of all data accesses to Normal memory +// `FTSSS +#define M33_CCR_DC_RESET _u(0x0) +#define M33_CCR_DC_BITS _u(0x00010000) +#define M33_CCR_DC_MSB _u(16) +#define M33_CCR_DC_LSB _u(16) +#define M33_CCR_DC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_STKOFHFNMIGN +// Description : Controls the effect of a stack limit violation while executing +// at a requested priority less than 0 +#define M33_CCR_STKOFHFNMIGN_RESET _u(0x0) +#define M33_CCR_STKOFHFNMIGN_BITS _u(0x00000400) +#define M33_CCR_STKOFHFNMIGN_MSB _u(10) +#define M33_CCR_STKOFHFNMIGN_LSB _u(10) +#define M33_CCR_STKOFHFNMIGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_RES1 +// Description : Reserved, RES1 +#define M33_CCR_RES1_RESET _u(0x1) +#define M33_CCR_RES1_BITS _u(0x00000200) +#define M33_CCR_RES1_MSB _u(9) +#define M33_CCR_RES1_LSB _u(9) +#define M33_CCR_RES1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_BFHFNMIGN +// Description : Determines the effect of precise BusFaults on handlers running +// at a requested priority less than 0 +#define M33_CCR_BFHFNMIGN_RESET _u(0x0) +#define M33_CCR_BFHFNMIGN_BITS _u(0x00000100) +#define M33_CCR_BFHFNMIGN_MSB _u(8) +#define M33_CCR_BFHFNMIGN_LSB _u(8) +#define M33_CCR_BFHFNMIGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_DIV_0_TRP +// Description : Controls the generation of a DIVBYZERO UsageFault when +// attempting to perform integer division by zero +#define M33_CCR_DIV_0_TRP_RESET _u(0x0) +#define M33_CCR_DIV_0_TRP_BITS _u(0x00000010) +#define M33_CCR_DIV_0_TRP_MSB _u(4) +#define M33_CCR_DIV_0_TRP_LSB _u(4) +#define M33_CCR_DIV_0_TRP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_UNALIGN_TRP +// Description : Controls the trapping of unaligned word or halfword accesses +#define M33_CCR_UNALIGN_TRP_RESET _u(0x0) +#define M33_CCR_UNALIGN_TRP_BITS _u(0x00000008) +#define M33_CCR_UNALIGN_TRP_MSB _u(3) +#define M33_CCR_UNALIGN_TRP_LSB _u(3) +#define M33_CCR_UNALIGN_TRP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_USERSETMPEND +// Description : Determines whether unprivileged accesses are permitted to pend +// interrupts via the STIR +#define M33_CCR_USERSETMPEND_RESET _u(0x0) +#define M33_CCR_USERSETMPEND_BITS _u(0x00000002) +#define M33_CCR_USERSETMPEND_MSB _u(1) +#define M33_CCR_USERSETMPEND_LSB _u(1) +#define M33_CCR_USERSETMPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_RES1_1 +// Description : Reserved, RES1 +#define M33_CCR_RES1_1_RESET _u(0x1) +#define M33_CCR_RES1_1_BITS _u(0x00000001) +#define M33_CCR_RES1_1_MSB _u(0) +#define M33_CCR_RES1_1_LSB _u(0) +#define M33_CCR_RES1_1_ACCESS "RO" +// ============================================================================= +// Register : M33_SHPR1 +// Description : Sets or returns priority for system handlers 4 - 7 +#define M33_SHPR1_OFFSET _u(0x0000ed18) +#define M33_SHPR1_BITS _u(0xe0e0e0e0) +#define M33_SHPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_7_3 +// Description : Priority of system handler 7, SecureFault +#define M33_SHPR1_PRI_7_3_RESET _u(0x0) +#define M33_SHPR1_PRI_7_3_BITS _u(0xe0000000) +#define M33_SHPR1_PRI_7_3_MSB _u(31) +#define M33_SHPR1_PRI_7_3_LSB _u(29) +#define M33_SHPR1_PRI_7_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_6_3 +// Description : Priority of system handler 6, SecureFault +#define M33_SHPR1_PRI_6_3_RESET _u(0x0) +#define M33_SHPR1_PRI_6_3_BITS _u(0x00e00000) +#define M33_SHPR1_PRI_6_3_MSB _u(23) +#define M33_SHPR1_PRI_6_3_LSB _u(21) +#define M33_SHPR1_PRI_6_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_5_3 +// Description : Priority of system handler 5, SecureFault +#define M33_SHPR1_PRI_5_3_RESET _u(0x0) +#define M33_SHPR1_PRI_5_3_BITS _u(0x0000e000) +#define M33_SHPR1_PRI_5_3_MSB _u(15) +#define M33_SHPR1_PRI_5_3_LSB _u(13) +#define M33_SHPR1_PRI_5_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_4_3 +// Description : Priority of system handler 4, SecureFault +#define M33_SHPR1_PRI_4_3_RESET _u(0x0) +#define M33_SHPR1_PRI_4_3_BITS _u(0x000000e0) +#define M33_SHPR1_PRI_4_3_MSB _u(7) +#define M33_SHPR1_PRI_4_3_LSB _u(5) +#define M33_SHPR1_PRI_4_3_ACCESS "RW" +// ============================================================================= +// Register : M33_SHPR2 +// Description : Sets or returns priority for system handlers 8 - 11 +#define M33_SHPR2_OFFSET _u(0x0000ed1c) +#define M33_SHPR2_BITS _u(0xe0ffffff) +#define M33_SHPR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_11_3 +// Description : Priority of system handler 11, SecureFault +#define M33_SHPR2_PRI_11_3_RESET _u(0x0) +#define M33_SHPR2_PRI_11_3_BITS _u(0xe0000000) +#define M33_SHPR2_PRI_11_3_MSB _u(31) +#define M33_SHPR2_PRI_11_3_LSB _u(29) +#define M33_SHPR2_PRI_11_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_10 +// Description : Reserved, RES0 +#define M33_SHPR2_PRI_10_RESET _u(0x00) +#define M33_SHPR2_PRI_10_BITS _u(0x00ff0000) +#define M33_SHPR2_PRI_10_MSB _u(23) +#define M33_SHPR2_PRI_10_LSB _u(16) +#define M33_SHPR2_PRI_10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_9 +// Description : Reserved, RES0 +#define M33_SHPR2_PRI_9_RESET _u(0x00) +#define M33_SHPR2_PRI_9_BITS _u(0x0000ff00) +#define M33_SHPR2_PRI_9_MSB _u(15) +#define M33_SHPR2_PRI_9_LSB _u(8) +#define M33_SHPR2_PRI_9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_8 +// Description : Reserved, RES0 +#define M33_SHPR2_PRI_8_RESET _u(0x00) +#define M33_SHPR2_PRI_8_BITS _u(0x000000ff) +#define M33_SHPR2_PRI_8_MSB _u(7) +#define M33_SHPR2_PRI_8_LSB _u(0) +#define M33_SHPR2_PRI_8_ACCESS "RO" +// ============================================================================= +// Register : M33_SHPR3 +// Description : Sets or returns priority for system handlers 12 - 15 +#define M33_SHPR3_OFFSET _u(0x0000ed20) +#define M33_SHPR3_BITS _u(0xe0e0ffe0) +#define M33_SHPR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_15_3 +// Description : Priority of system handler 15, SecureFault +#define M33_SHPR3_PRI_15_3_RESET _u(0x0) +#define M33_SHPR3_PRI_15_3_BITS _u(0xe0000000) +#define M33_SHPR3_PRI_15_3_MSB _u(31) +#define M33_SHPR3_PRI_15_3_LSB _u(29) +#define M33_SHPR3_PRI_15_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_14_3 +// Description : Priority of system handler 14, SecureFault +#define M33_SHPR3_PRI_14_3_RESET _u(0x0) +#define M33_SHPR3_PRI_14_3_BITS _u(0x00e00000) +#define M33_SHPR3_PRI_14_3_MSB _u(23) +#define M33_SHPR3_PRI_14_3_LSB _u(21) +#define M33_SHPR3_PRI_14_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_13 +// Description : Reserved, RES0 +#define M33_SHPR3_PRI_13_RESET _u(0x00) +#define M33_SHPR3_PRI_13_BITS _u(0x0000ff00) +#define M33_SHPR3_PRI_13_MSB _u(15) +#define M33_SHPR3_PRI_13_LSB _u(8) +#define M33_SHPR3_PRI_13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_12_3 +// Description : Priority of system handler 12, SecureFault +#define M33_SHPR3_PRI_12_3_RESET _u(0x0) +#define M33_SHPR3_PRI_12_3_BITS _u(0x000000e0) +#define M33_SHPR3_PRI_12_3_MSB _u(7) +#define M33_SHPR3_PRI_12_3_LSB _u(5) +#define M33_SHPR3_PRI_12_3_ACCESS "RW" +// ============================================================================= +// Register : M33_SHCSR +// Description : Provides access to the active and pending status of system +// exceptions +#define M33_SHCSR_OFFSET _u(0x0000ed24) +#define M33_SHCSR_BITS _u(0x003ffdbf) +#define M33_SHCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_HARDFAULTPENDED +// Description : `IAAMO the pending state of the HardFault exception `CTTSSS +#define M33_SHCSR_HARDFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_HARDFAULTPENDED_BITS _u(0x00200000) +#define M33_SHCSR_HARDFAULTPENDED_MSB _u(21) +#define M33_SHCSR_HARDFAULTPENDED_LSB _u(21) +#define M33_SHCSR_HARDFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SECUREFAULTPENDED +// Description : `IAAMO the pending state of the SecureFault exception +#define M33_SHCSR_SECUREFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_SECUREFAULTPENDED_BITS _u(0x00100000) +#define M33_SHCSR_SECUREFAULTPENDED_MSB _u(20) +#define M33_SHCSR_SECUREFAULTPENDED_LSB _u(20) +#define M33_SHCSR_SECUREFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SECUREFAULTENA +// Description : `DW the SecureFault exception is enabled +#define M33_SHCSR_SECUREFAULTENA_RESET _u(0x0) +#define M33_SHCSR_SECUREFAULTENA_BITS _u(0x00080000) +#define M33_SHCSR_SECUREFAULTENA_MSB _u(19) +#define M33_SHCSR_SECUREFAULTENA_LSB _u(19) +#define M33_SHCSR_SECUREFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_USGFAULTENA +// Description : `DW the UsageFault exception is enabled `FTSSS +#define M33_SHCSR_USGFAULTENA_RESET _u(0x0) +#define M33_SHCSR_USGFAULTENA_BITS _u(0x00040000) +#define M33_SHCSR_USGFAULTENA_MSB _u(18) +#define M33_SHCSR_USGFAULTENA_LSB _u(18) +#define M33_SHCSR_USGFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_BUSFAULTENA +// Description : `DW the BusFault exception is enabled +#define M33_SHCSR_BUSFAULTENA_RESET _u(0x0) +#define M33_SHCSR_BUSFAULTENA_BITS _u(0x00020000) +#define M33_SHCSR_BUSFAULTENA_MSB _u(17) +#define M33_SHCSR_BUSFAULTENA_LSB _u(17) +#define M33_SHCSR_BUSFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MEMFAULTENA +// Description : `DW the MemManage exception is enabled `FTSSS +#define M33_SHCSR_MEMFAULTENA_RESET _u(0x0) +#define M33_SHCSR_MEMFAULTENA_BITS _u(0x00010000) +#define M33_SHCSR_MEMFAULTENA_MSB _u(16) +#define M33_SHCSR_MEMFAULTENA_LSB _u(16) +#define M33_SHCSR_MEMFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SVCALLPENDED +// Description : `IAAMO the pending state of the SVCall exception `FTSSS +#define M33_SHCSR_SVCALLPENDED_RESET _u(0x0) +#define M33_SHCSR_SVCALLPENDED_BITS _u(0x00008000) +#define M33_SHCSR_SVCALLPENDED_MSB _u(15) +#define M33_SHCSR_SVCALLPENDED_LSB _u(15) +#define M33_SHCSR_SVCALLPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_BUSFAULTPENDED +// Description : `IAAMO the pending state of the BusFault exception +#define M33_SHCSR_BUSFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_BUSFAULTPENDED_BITS _u(0x00004000) +#define M33_SHCSR_BUSFAULTPENDED_MSB _u(14) +#define M33_SHCSR_BUSFAULTPENDED_LSB _u(14) +#define M33_SHCSR_BUSFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MEMFAULTPENDED +// Description : `IAAMO the pending state of the MemManage exception `FTSSS +#define M33_SHCSR_MEMFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_MEMFAULTPENDED_BITS _u(0x00002000) +#define M33_SHCSR_MEMFAULTPENDED_MSB _u(13) +#define M33_SHCSR_MEMFAULTPENDED_LSB _u(13) +#define M33_SHCSR_MEMFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_USGFAULTPENDED +// Description : The UsageFault exception is banked between Security states, +// `IAAMO the pending state of the UsageFault exception `FTSSS +#define M33_SHCSR_USGFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_USGFAULTPENDED_BITS _u(0x00001000) +#define M33_SHCSR_USGFAULTPENDED_MSB _u(12) +#define M33_SHCSR_USGFAULTPENDED_LSB _u(12) +#define M33_SHCSR_USGFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SYSTICKACT +// Description : `IAAMO the active state of the SysTick exception `FTSSS +#define M33_SHCSR_SYSTICKACT_RESET _u(0x0) +#define M33_SHCSR_SYSTICKACT_BITS _u(0x00000800) +#define M33_SHCSR_SYSTICKACT_MSB _u(11) +#define M33_SHCSR_SYSTICKACT_LSB _u(11) +#define M33_SHCSR_SYSTICKACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_PENDSVACT +// Description : `IAAMO the active state of the PendSV exception `FTSSS +#define M33_SHCSR_PENDSVACT_RESET _u(0x0) +#define M33_SHCSR_PENDSVACT_BITS _u(0x00000400) +#define M33_SHCSR_PENDSVACT_MSB _u(10) +#define M33_SHCSR_PENDSVACT_LSB _u(10) +#define M33_SHCSR_PENDSVACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MONITORACT +// Description : `IAAMO the active state of the DebugMonitor exception +#define M33_SHCSR_MONITORACT_RESET _u(0x0) +#define M33_SHCSR_MONITORACT_BITS _u(0x00000100) +#define M33_SHCSR_MONITORACT_MSB _u(8) +#define M33_SHCSR_MONITORACT_LSB _u(8) +#define M33_SHCSR_MONITORACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SVCALLACT +// Description : `IAAMO the active state of the SVCall exception `FTSSS +#define M33_SHCSR_SVCALLACT_RESET _u(0x0) +#define M33_SHCSR_SVCALLACT_BITS _u(0x00000080) +#define M33_SHCSR_SVCALLACT_MSB _u(7) +#define M33_SHCSR_SVCALLACT_LSB _u(7) +#define M33_SHCSR_SVCALLACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_NMIACT +// Description : `IAAMO the active state of the NMI exception +#define M33_SHCSR_NMIACT_RESET _u(0x0) +#define M33_SHCSR_NMIACT_BITS _u(0x00000020) +#define M33_SHCSR_NMIACT_MSB _u(5) +#define M33_SHCSR_NMIACT_LSB _u(5) +#define M33_SHCSR_NMIACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SECUREFAULTACT +// Description : `IAAMO the active state of the SecureFault exception +#define M33_SHCSR_SECUREFAULTACT_RESET _u(0x0) +#define M33_SHCSR_SECUREFAULTACT_BITS _u(0x00000010) +#define M33_SHCSR_SECUREFAULTACT_MSB _u(4) +#define M33_SHCSR_SECUREFAULTACT_LSB _u(4) +#define M33_SHCSR_SECUREFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_USGFAULTACT +// Description : `IAAMO the active state of the UsageFault exception `FTSSS +#define M33_SHCSR_USGFAULTACT_RESET _u(0x0) +#define M33_SHCSR_USGFAULTACT_BITS _u(0x00000008) +#define M33_SHCSR_USGFAULTACT_MSB _u(3) +#define M33_SHCSR_USGFAULTACT_LSB _u(3) +#define M33_SHCSR_USGFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_HARDFAULTACT +// Description : Indicates and allows limited modification of the active state +// of the HardFault exception `FTSSS +#define M33_SHCSR_HARDFAULTACT_RESET _u(0x0) +#define M33_SHCSR_HARDFAULTACT_BITS _u(0x00000004) +#define M33_SHCSR_HARDFAULTACT_MSB _u(2) +#define M33_SHCSR_HARDFAULTACT_LSB _u(2) +#define M33_SHCSR_HARDFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_BUSFAULTACT +// Description : `IAAMO the active state of the BusFault exception +#define M33_SHCSR_BUSFAULTACT_RESET _u(0x0) +#define M33_SHCSR_BUSFAULTACT_BITS _u(0x00000002) +#define M33_SHCSR_BUSFAULTACT_MSB _u(1) +#define M33_SHCSR_BUSFAULTACT_LSB _u(1) +#define M33_SHCSR_BUSFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MEMFAULTACT +// Description : `IAAMO the active state of the MemManage exception `FTSSS +#define M33_SHCSR_MEMFAULTACT_RESET _u(0x0) +#define M33_SHCSR_MEMFAULTACT_BITS _u(0x00000001) +#define M33_SHCSR_MEMFAULTACT_MSB _u(0) +#define M33_SHCSR_MEMFAULTACT_LSB _u(0) +#define M33_SHCSR_MEMFAULTACT_ACCESS "RW" +// ============================================================================= +// Register : M33_CFSR +// Description : Contains the three Configurable Fault Status Registers. +// +// 31:16 UFSR: Provides information on UsageFault exceptions +// +// 15:8 BFSR: Provides information on BusFault exceptions +// +// 7:0 MMFSR: Provides information on MemManage exceptions +#define M33_CFSR_OFFSET _u(0x0000ed28) +#define M33_CFSR_BITS _u(0x031fbfff) +#define M33_CFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_DIVBYZERO +// Description : Sticky flag indicating whether an integer division by zero +// error has occurred +#define M33_CFSR_UFSR_DIVBYZERO_RESET _u(0x0) +#define M33_CFSR_UFSR_DIVBYZERO_BITS _u(0x02000000) +#define M33_CFSR_UFSR_DIVBYZERO_MSB _u(25) +#define M33_CFSR_UFSR_DIVBYZERO_LSB _u(25) +#define M33_CFSR_UFSR_DIVBYZERO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_UNALIGNED +// Description : Sticky flag indicating whether an unaligned access error has +// occurred +#define M33_CFSR_UFSR_UNALIGNED_RESET _u(0x0) +#define M33_CFSR_UFSR_UNALIGNED_BITS _u(0x01000000) +#define M33_CFSR_UFSR_UNALIGNED_MSB _u(24) +#define M33_CFSR_UFSR_UNALIGNED_LSB _u(24) +#define M33_CFSR_UFSR_UNALIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_STKOF +// Description : Sticky flag indicating whether a stack overflow error has +// occurred +#define M33_CFSR_UFSR_STKOF_RESET _u(0x0) +#define M33_CFSR_UFSR_STKOF_BITS _u(0x00100000) +#define M33_CFSR_UFSR_STKOF_MSB _u(20) +#define M33_CFSR_UFSR_STKOF_LSB _u(20) +#define M33_CFSR_UFSR_STKOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_NOCP +// Description : Sticky flag indicating whether a coprocessor disabled or not +// present error has occurred +#define M33_CFSR_UFSR_NOCP_RESET _u(0x0) +#define M33_CFSR_UFSR_NOCP_BITS _u(0x00080000) +#define M33_CFSR_UFSR_NOCP_MSB _u(19) +#define M33_CFSR_UFSR_NOCP_LSB _u(19) +#define M33_CFSR_UFSR_NOCP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_INVPC +// Description : Sticky flag indicating whether an integrity check error has +// occurred +#define M33_CFSR_UFSR_INVPC_RESET _u(0x0) +#define M33_CFSR_UFSR_INVPC_BITS _u(0x00040000) +#define M33_CFSR_UFSR_INVPC_MSB _u(18) +#define M33_CFSR_UFSR_INVPC_LSB _u(18) +#define M33_CFSR_UFSR_INVPC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_INVSTATE +// Description : Sticky flag indicating whether an EPSR.T or EPSR.IT validity +// error has occurred +#define M33_CFSR_UFSR_INVSTATE_RESET _u(0x0) +#define M33_CFSR_UFSR_INVSTATE_BITS _u(0x00020000) +#define M33_CFSR_UFSR_INVSTATE_MSB _u(17) +#define M33_CFSR_UFSR_INVSTATE_LSB _u(17) +#define M33_CFSR_UFSR_INVSTATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_UNDEFINSTR +// Description : Sticky flag indicating whether an undefined instruction error +// has occurred +#define M33_CFSR_UFSR_UNDEFINSTR_RESET _u(0x0) +#define M33_CFSR_UFSR_UNDEFINSTR_BITS _u(0x00010000) +#define M33_CFSR_UFSR_UNDEFINSTR_MSB _u(16) +#define M33_CFSR_UFSR_UNDEFINSTR_LSB _u(16) +#define M33_CFSR_UFSR_UNDEFINSTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_BFARVALID +// Description : Indicates validity of the contents of the BFAR register +#define M33_CFSR_BFSR_BFARVALID_RESET _u(0x0) +#define M33_CFSR_BFSR_BFARVALID_BITS _u(0x00008000) +#define M33_CFSR_BFSR_BFARVALID_MSB _u(15) +#define M33_CFSR_BFSR_BFARVALID_LSB _u(15) +#define M33_CFSR_BFSR_BFARVALID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_LSPERR +// Description : Records whether a BusFault occurred during FP lazy state +// preservation +#define M33_CFSR_BFSR_LSPERR_RESET _u(0x0) +#define M33_CFSR_BFSR_LSPERR_BITS _u(0x00002000) +#define M33_CFSR_BFSR_LSPERR_MSB _u(13) +#define M33_CFSR_BFSR_LSPERR_LSB _u(13) +#define M33_CFSR_BFSR_LSPERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_STKERR +// Description : Records whether a derived BusFault occurred during exception +// entry stacking +#define M33_CFSR_BFSR_STKERR_RESET _u(0x0) +#define M33_CFSR_BFSR_STKERR_BITS _u(0x00001000) +#define M33_CFSR_BFSR_STKERR_MSB _u(12) +#define M33_CFSR_BFSR_STKERR_LSB _u(12) +#define M33_CFSR_BFSR_STKERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_UNSTKERR +// Description : Records whether a derived BusFault occurred during exception +// return unstacking +#define M33_CFSR_BFSR_UNSTKERR_RESET _u(0x0) +#define M33_CFSR_BFSR_UNSTKERR_BITS _u(0x00000800) +#define M33_CFSR_BFSR_UNSTKERR_MSB _u(11) +#define M33_CFSR_BFSR_UNSTKERR_LSB _u(11) +#define M33_CFSR_BFSR_UNSTKERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_IMPRECISERR +// Description : Records whether an imprecise data access error has occurred +#define M33_CFSR_BFSR_IMPRECISERR_RESET _u(0x0) +#define M33_CFSR_BFSR_IMPRECISERR_BITS _u(0x00000400) +#define M33_CFSR_BFSR_IMPRECISERR_MSB _u(10) +#define M33_CFSR_BFSR_IMPRECISERR_LSB _u(10) +#define M33_CFSR_BFSR_IMPRECISERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_PRECISERR +// Description : Records whether a precise data access error has occurred +#define M33_CFSR_BFSR_PRECISERR_RESET _u(0x0) +#define M33_CFSR_BFSR_PRECISERR_BITS _u(0x00000200) +#define M33_CFSR_BFSR_PRECISERR_MSB _u(9) +#define M33_CFSR_BFSR_PRECISERR_LSB _u(9) +#define M33_CFSR_BFSR_PRECISERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_IBUSERR +// Description : Records whether a BusFault on an instruction prefetch has +// occurred +#define M33_CFSR_BFSR_IBUSERR_RESET _u(0x0) +#define M33_CFSR_BFSR_IBUSERR_BITS _u(0x00000100) +#define M33_CFSR_BFSR_IBUSERR_MSB _u(8) +#define M33_CFSR_BFSR_IBUSERR_LSB _u(8) +#define M33_CFSR_BFSR_IBUSERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_MMFSR +// Description : Provides information on MemManage exceptions +#define M33_CFSR_MMFSR_RESET _u(0x00) +#define M33_CFSR_MMFSR_BITS _u(0x000000ff) +#define M33_CFSR_MMFSR_MSB _u(7) +#define M33_CFSR_MMFSR_LSB _u(0) +#define M33_CFSR_MMFSR_ACCESS "RW" +// ============================================================================= +// Register : M33_HFSR +// Description : Shows the cause of any HardFaults +#define M33_HFSR_OFFSET _u(0x0000ed2c) +#define M33_HFSR_BITS _u(0xc0000002) +#define M33_HFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_HFSR_DEBUGEVT +// Description : Indicates when a Debug event has occurred +#define M33_HFSR_DEBUGEVT_RESET _u(0x0) +#define M33_HFSR_DEBUGEVT_BITS _u(0x80000000) +#define M33_HFSR_DEBUGEVT_MSB _u(31) +#define M33_HFSR_DEBUGEVT_LSB _u(31) +#define M33_HFSR_DEBUGEVT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_HFSR_FORCED +// Description : Indicates that a fault with configurable priority has been +// escalated to a HardFault exception, because it could not be +// made active, because of priority, or because it was disabled +#define M33_HFSR_FORCED_RESET _u(0x0) +#define M33_HFSR_FORCED_BITS _u(0x40000000) +#define M33_HFSR_FORCED_MSB _u(30) +#define M33_HFSR_FORCED_LSB _u(30) +#define M33_HFSR_FORCED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_HFSR_VECTTBL +// Description : Indicates when a fault has occurred because of a vector table +// read error on exception processing +#define M33_HFSR_VECTTBL_RESET _u(0x0) +#define M33_HFSR_VECTTBL_BITS _u(0x00000002) +#define M33_HFSR_VECTTBL_MSB _u(1) +#define M33_HFSR_VECTTBL_LSB _u(1) +#define M33_HFSR_VECTTBL_ACCESS "RW" +// ============================================================================= +// Register : M33_DFSR +// Description : Shows which debug event occurred +#define M33_DFSR_OFFSET _u(0x0000ed30) +#define M33_DFSR_BITS _u(0x0000001f) +#define M33_DFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_EXTERNAL +// Description : Sticky flag indicating whether an External debug request debug +// event has occurred +#define M33_DFSR_EXTERNAL_RESET _u(0x0) +#define M33_DFSR_EXTERNAL_BITS _u(0x00000010) +#define M33_DFSR_EXTERNAL_MSB _u(4) +#define M33_DFSR_EXTERNAL_LSB _u(4) +#define M33_DFSR_EXTERNAL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_VCATCH +// Description : Sticky flag indicating whether a Vector catch debug event has +// occurred +#define M33_DFSR_VCATCH_RESET _u(0x0) +#define M33_DFSR_VCATCH_BITS _u(0x00000008) +#define M33_DFSR_VCATCH_MSB _u(3) +#define M33_DFSR_VCATCH_LSB _u(3) +#define M33_DFSR_VCATCH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_DWTTRAP +// Description : Sticky flag indicating whether a Watchpoint debug event has +// occurred +#define M33_DFSR_DWTTRAP_RESET _u(0x0) +#define M33_DFSR_DWTTRAP_BITS _u(0x00000004) +#define M33_DFSR_DWTTRAP_MSB _u(2) +#define M33_DFSR_DWTTRAP_LSB _u(2) +#define M33_DFSR_DWTTRAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_BKPT +// Description : Sticky flag indicating whether a Breakpoint debug event has +// occurred +#define M33_DFSR_BKPT_RESET _u(0x0) +#define M33_DFSR_BKPT_BITS _u(0x00000002) +#define M33_DFSR_BKPT_MSB _u(1) +#define M33_DFSR_BKPT_LSB _u(1) +#define M33_DFSR_BKPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_HALTED +// Description : Sticky flag indicating that a Halt request debug event or Step +// debug event has occurred +#define M33_DFSR_HALTED_RESET _u(0x0) +#define M33_DFSR_HALTED_BITS _u(0x00000001) +#define M33_DFSR_HALTED_MSB _u(0) +#define M33_DFSR_HALTED_LSB _u(0) +#define M33_DFSR_HALTED_ACCESS "RW" +// ============================================================================= +// Register : M33_MMFAR +// Description : Shows the address of the memory location that caused an MPU +// fault +#define M33_MMFAR_OFFSET _u(0x0000ed34) +#define M33_MMFAR_BITS _u(0xffffffff) +#define M33_MMFAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MMFAR_ADDRESS +// Description : This register is updated with the address of a location that +// produced a MemManage fault. The MMFSR shows the cause of the +// fault, and whether this field is valid. This field is valid +// only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN +#define M33_MMFAR_ADDRESS_RESET _u(0x00000000) +#define M33_MMFAR_ADDRESS_BITS _u(0xffffffff) +#define M33_MMFAR_ADDRESS_MSB _u(31) +#define M33_MMFAR_ADDRESS_LSB _u(0) +#define M33_MMFAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_BFAR +// Description : Shows the address associated with a precise data access +// BusFault +#define M33_BFAR_OFFSET _u(0x0000ed38) +#define M33_BFAR_BITS _u(0xffffffff) +#define M33_BFAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_BFAR_ADDRESS +// Description : This register is updated with the address of a location that +// produced a BusFault. The BFSR shows the reason for the fault. +// This field is valid only when BFSR.BFARVALID is set, otherwise +// it is UNKNOWN +#define M33_BFAR_ADDRESS_RESET _u(0x00000000) +#define M33_BFAR_ADDRESS_BITS _u(0xffffffff) +#define M33_BFAR_ADDRESS_MSB _u(31) +#define M33_BFAR_ADDRESS_LSB _u(0) +#define M33_BFAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_ID_PFR0 +// Description : Gives top-level information about the instruction set supported +// by the PE +#define M33_ID_PFR0_OFFSET _u(0x0000ed40) +#define M33_ID_PFR0_BITS _u(0x000000ff) +#define M33_ID_PFR0_RESET _u(0x00000030) +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR0_STATE1 +// Description : T32 instruction set support +#define M33_ID_PFR0_STATE1_RESET _u(0x3) +#define M33_ID_PFR0_STATE1_BITS _u(0x000000f0) +#define M33_ID_PFR0_STATE1_MSB _u(7) +#define M33_ID_PFR0_STATE1_LSB _u(4) +#define M33_ID_PFR0_STATE1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR0_STATE0 +// Description : A32 instruction set support +#define M33_ID_PFR0_STATE0_RESET _u(0x0) +#define M33_ID_PFR0_STATE0_BITS _u(0x0000000f) +#define M33_ID_PFR0_STATE0_MSB _u(3) +#define M33_ID_PFR0_STATE0_LSB _u(0) +#define M33_ID_PFR0_STATE0_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_PFR1 +// Description : Gives information about the programmers' model and Extensions +// support +#define M33_ID_PFR1_OFFSET _u(0x0000ed44) +#define M33_ID_PFR1_BITS _u(0x00000ff0) +#define M33_ID_PFR1_RESET _u(0x00000520) +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR1_MPROGMOD +// Description : Identifies support for the M-Profile programmers' model support +#define M33_ID_PFR1_MPROGMOD_RESET _u(0x5) +#define M33_ID_PFR1_MPROGMOD_BITS _u(0x00000f00) +#define M33_ID_PFR1_MPROGMOD_MSB _u(11) +#define M33_ID_PFR1_MPROGMOD_LSB _u(8) +#define M33_ID_PFR1_MPROGMOD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR1_SECURITY +// Description : Identifies whether the Security Extension is implemented +#define M33_ID_PFR1_SECURITY_RESET _u(0x2) +#define M33_ID_PFR1_SECURITY_BITS _u(0x000000f0) +#define M33_ID_PFR1_SECURITY_MSB _u(7) +#define M33_ID_PFR1_SECURITY_LSB _u(4) +#define M33_ID_PFR1_SECURITY_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_DFR0 +// Description : Provides top level information about the debug system +#define M33_ID_DFR0_OFFSET _u(0x0000ed48) +#define M33_ID_DFR0_BITS _u(0x00f00000) +#define M33_ID_DFR0_RESET _u(0x00200000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_DFR0_MPROFDBG +// Description : Indicates the supported M-profile debug architecture +#define M33_ID_DFR0_MPROFDBG_RESET _u(0x2) +#define M33_ID_DFR0_MPROFDBG_BITS _u(0x00f00000) +#define M33_ID_DFR0_MPROFDBG_MSB _u(23) +#define M33_ID_DFR0_MPROFDBG_LSB _u(20) +#define M33_ID_DFR0_MPROFDBG_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_AFR0 +// Description : Provides information about the IMPLEMENTATION DEFINED features +// of the PE +#define M33_ID_AFR0_OFFSET _u(0x0000ed4c) +#define M33_ID_AFR0_BITS _u(0x0000ffff) +#define M33_ID_AFR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF3 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF3_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF3_BITS _u(0x0000f000) +#define M33_ID_AFR0_IMPDEF3_MSB _u(15) +#define M33_ID_AFR0_IMPDEF3_LSB _u(12) +#define M33_ID_AFR0_IMPDEF3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF2 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF2_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF2_BITS _u(0x00000f00) +#define M33_ID_AFR0_IMPDEF2_MSB _u(11) +#define M33_ID_AFR0_IMPDEF2_LSB _u(8) +#define M33_ID_AFR0_IMPDEF2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF1 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF1_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF1_BITS _u(0x000000f0) +#define M33_ID_AFR0_IMPDEF1_MSB _u(7) +#define M33_ID_AFR0_IMPDEF1_LSB _u(4) +#define M33_ID_AFR0_IMPDEF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF0 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF0_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF0_BITS _u(0x0000000f) +#define M33_ID_AFR0_IMPDEF0_MSB _u(3) +#define M33_ID_AFR0_IMPDEF0_LSB _u(0) +#define M33_ID_AFR0_IMPDEF0_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_MMFR0 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR0_OFFSET _u(0x0000ed50) +#define M33_ID_MMFR0_BITS _u(0x00fffff0) +#define M33_ID_MMFR0_RESET _u(0x00101f40) +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_AUXREG +// Description : Indicates support for Auxiliary Control Registers +#define M33_ID_MMFR0_AUXREG_RESET _u(0x1) +#define M33_ID_MMFR0_AUXREG_BITS _u(0x00f00000) +#define M33_ID_MMFR0_AUXREG_MSB _u(23) +#define M33_ID_MMFR0_AUXREG_LSB _u(20) +#define M33_ID_MMFR0_AUXREG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_TCM +// Description : Indicates support for tightly coupled memories (TCMs) +#define M33_ID_MMFR0_TCM_RESET _u(0x0) +#define M33_ID_MMFR0_TCM_BITS _u(0x000f0000) +#define M33_ID_MMFR0_TCM_MSB _u(19) +#define M33_ID_MMFR0_TCM_LSB _u(16) +#define M33_ID_MMFR0_TCM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_SHARELVL +// Description : Indicates the number of shareability levels implemented +#define M33_ID_MMFR0_SHARELVL_RESET _u(0x1) +#define M33_ID_MMFR0_SHARELVL_BITS _u(0x0000f000) +#define M33_ID_MMFR0_SHARELVL_MSB _u(15) +#define M33_ID_MMFR0_SHARELVL_LSB _u(12) +#define M33_ID_MMFR0_SHARELVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_OUTERSHR +// Description : Indicates the outermost shareability domain implemented +#define M33_ID_MMFR0_OUTERSHR_RESET _u(0xf) +#define M33_ID_MMFR0_OUTERSHR_BITS _u(0x00000f00) +#define M33_ID_MMFR0_OUTERSHR_MSB _u(11) +#define M33_ID_MMFR0_OUTERSHR_LSB _u(8) +#define M33_ID_MMFR0_OUTERSHR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_PMSA +// Description : Indicates support for the protected memory system architecture +// (PMSA) +#define M33_ID_MMFR0_PMSA_RESET _u(0x4) +#define M33_ID_MMFR0_PMSA_BITS _u(0x000000f0) +#define M33_ID_MMFR0_PMSA_MSB _u(7) +#define M33_ID_MMFR0_PMSA_LSB _u(4) +#define M33_ID_MMFR0_PMSA_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_MMFR1 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR1_OFFSET _u(0x0000ed54) +#define M33_ID_MMFR1_BITS _u(0x00000000) +#define M33_ID_MMFR1_RESET _u(0x00000000) +#define M33_ID_MMFR1_MSB _u(31) +#define M33_ID_MMFR1_LSB _u(0) +#define M33_ID_MMFR1_ACCESS "RW" +// ============================================================================= +// Register : M33_ID_MMFR2 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR2_OFFSET _u(0x0000ed58) +#define M33_ID_MMFR2_BITS _u(0x0f000000) +#define M33_ID_MMFR2_RESET _u(0x01000000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR2_WFISTALL +// Description : Indicates the support for Wait For Interrupt (WFI) stalling +#define M33_ID_MMFR2_WFISTALL_RESET _u(0x1) +#define M33_ID_MMFR2_WFISTALL_BITS _u(0x0f000000) +#define M33_ID_MMFR2_WFISTALL_MSB _u(27) +#define M33_ID_MMFR2_WFISTALL_LSB _u(24) +#define M33_ID_MMFR2_WFISTALL_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_MMFR3 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR3_OFFSET _u(0x0000ed5c) +#define M33_ID_MMFR3_BITS _u(0x00000fff) +#define M33_ID_MMFR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR3_BPMAINT +// Description : Indicates the supported branch predictor maintenance +#define M33_ID_MMFR3_BPMAINT_RESET _u(0x0) +#define M33_ID_MMFR3_BPMAINT_BITS _u(0x00000f00) +#define M33_ID_MMFR3_BPMAINT_MSB _u(11) +#define M33_ID_MMFR3_BPMAINT_LSB _u(8) +#define M33_ID_MMFR3_BPMAINT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR3_CMAINTSW +// Description : Indicates the supported cache maintenance operations by set/way +#define M33_ID_MMFR3_CMAINTSW_RESET _u(0x0) +#define M33_ID_MMFR3_CMAINTSW_BITS _u(0x000000f0) +#define M33_ID_MMFR3_CMAINTSW_MSB _u(7) +#define M33_ID_MMFR3_CMAINTSW_LSB _u(4) +#define M33_ID_MMFR3_CMAINTSW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR3_CMAINTVA +// Description : Indicates the supported cache maintenance operations by address +#define M33_ID_MMFR3_CMAINTVA_RESET _u(0x0) +#define M33_ID_MMFR3_CMAINTVA_BITS _u(0x0000000f) +#define M33_ID_MMFR3_CMAINTVA_MSB _u(3) +#define M33_ID_MMFR3_CMAINTVA_LSB _u(0) +#define M33_ID_MMFR3_CMAINTVA_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR0 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR0_OFFSET _u(0x0000ed60) +#define M33_ID_ISAR0_BITS _u(0x0ffffff0) +#define M33_ID_ISAR0_RESET _u(0x08092300) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_DIVIDE +// Description : Indicates the supported Divide instructions +#define M33_ID_ISAR0_DIVIDE_RESET _u(0x8) +#define M33_ID_ISAR0_DIVIDE_BITS _u(0x0f000000) +#define M33_ID_ISAR0_DIVIDE_MSB _u(27) +#define M33_ID_ISAR0_DIVIDE_LSB _u(24) +#define M33_ID_ISAR0_DIVIDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_DEBUG +// Description : Indicates the implemented Debug instructions +#define M33_ID_ISAR0_DEBUG_RESET _u(0x0) +#define M33_ID_ISAR0_DEBUG_BITS _u(0x00f00000) +#define M33_ID_ISAR0_DEBUG_MSB _u(23) +#define M33_ID_ISAR0_DEBUG_LSB _u(20) +#define M33_ID_ISAR0_DEBUG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_COPROC +// Description : Indicates the supported Coprocessor instructions +#define M33_ID_ISAR0_COPROC_RESET _u(0x9) +#define M33_ID_ISAR0_COPROC_BITS _u(0x000f0000) +#define M33_ID_ISAR0_COPROC_MSB _u(19) +#define M33_ID_ISAR0_COPROC_LSB _u(16) +#define M33_ID_ISAR0_COPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_CMPBRANCH +// Description : Indicates the supported combined Compare and Branch +// instructions +#define M33_ID_ISAR0_CMPBRANCH_RESET _u(0x2) +#define M33_ID_ISAR0_CMPBRANCH_BITS _u(0x0000f000) +#define M33_ID_ISAR0_CMPBRANCH_MSB _u(15) +#define M33_ID_ISAR0_CMPBRANCH_LSB _u(12) +#define M33_ID_ISAR0_CMPBRANCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_BITFIELD +// Description : Indicates the supported bit field instructions +#define M33_ID_ISAR0_BITFIELD_RESET _u(0x3) +#define M33_ID_ISAR0_BITFIELD_BITS _u(0x00000f00) +#define M33_ID_ISAR0_BITFIELD_MSB _u(11) +#define M33_ID_ISAR0_BITFIELD_LSB _u(8) +#define M33_ID_ISAR0_BITFIELD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_BITCOUNT +// Description : Indicates the supported bit count instructions +#define M33_ID_ISAR0_BITCOUNT_RESET _u(0x0) +#define M33_ID_ISAR0_BITCOUNT_BITS _u(0x000000f0) +#define M33_ID_ISAR0_BITCOUNT_MSB _u(7) +#define M33_ID_ISAR0_BITCOUNT_LSB _u(4) +#define M33_ID_ISAR0_BITCOUNT_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR1 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR1_OFFSET _u(0x0000ed64) +#define M33_ID_ISAR1_BITS _u(0x0ffff000) +#define M33_ID_ISAR1_RESET _u(0x05725000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_INTERWORK +// Description : Indicates the implemented Interworking instructions +#define M33_ID_ISAR1_INTERWORK_RESET _u(0x5) +#define M33_ID_ISAR1_INTERWORK_BITS _u(0x0f000000) +#define M33_ID_ISAR1_INTERWORK_MSB _u(27) +#define M33_ID_ISAR1_INTERWORK_LSB _u(24) +#define M33_ID_ISAR1_INTERWORK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_IMMEDIATE +// Description : Indicates the implemented for data-processing instructions with +// long immediates +#define M33_ID_ISAR1_IMMEDIATE_RESET _u(0x7) +#define M33_ID_ISAR1_IMMEDIATE_BITS _u(0x00f00000) +#define M33_ID_ISAR1_IMMEDIATE_MSB _u(23) +#define M33_ID_ISAR1_IMMEDIATE_LSB _u(20) +#define M33_ID_ISAR1_IMMEDIATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_IFTHEN +// Description : Indicates the implemented If-Then instructions +#define M33_ID_ISAR1_IFTHEN_RESET _u(0x2) +#define M33_ID_ISAR1_IFTHEN_BITS _u(0x000f0000) +#define M33_ID_ISAR1_IFTHEN_MSB _u(19) +#define M33_ID_ISAR1_IFTHEN_LSB _u(16) +#define M33_ID_ISAR1_IFTHEN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_EXTEND +// Description : Indicates the implemented Extend instructions +#define M33_ID_ISAR1_EXTEND_RESET _u(0x5) +#define M33_ID_ISAR1_EXTEND_BITS _u(0x0000f000) +#define M33_ID_ISAR1_EXTEND_MSB _u(15) +#define M33_ID_ISAR1_EXTEND_LSB _u(12) +#define M33_ID_ISAR1_EXTEND_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR2 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR2_OFFSET _u(0x0000ed68) +#define M33_ID_ISAR2_BITS _u(0xf0ffffff) +#define M33_ID_ISAR2_RESET _u(0x30173426) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_REVERSAL +// Description : Indicates the implemented Reversal instructions +#define M33_ID_ISAR2_REVERSAL_RESET _u(0x3) +#define M33_ID_ISAR2_REVERSAL_BITS _u(0xf0000000) +#define M33_ID_ISAR2_REVERSAL_MSB _u(31) +#define M33_ID_ISAR2_REVERSAL_LSB _u(28) +#define M33_ID_ISAR2_REVERSAL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULTU +// Description : Indicates the implemented advanced unsigned Multiply +// instructions +#define M33_ID_ISAR2_MULTU_RESET _u(0x1) +#define M33_ID_ISAR2_MULTU_BITS _u(0x00f00000) +#define M33_ID_ISAR2_MULTU_MSB _u(23) +#define M33_ID_ISAR2_MULTU_LSB _u(20) +#define M33_ID_ISAR2_MULTU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULTS +// Description : Indicates the implemented advanced signed Multiply instructions +#define M33_ID_ISAR2_MULTS_RESET _u(0x7) +#define M33_ID_ISAR2_MULTS_BITS _u(0x000f0000) +#define M33_ID_ISAR2_MULTS_MSB _u(19) +#define M33_ID_ISAR2_MULTS_LSB _u(16) +#define M33_ID_ISAR2_MULTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULT +// Description : Indicates the implemented additional Multiply instructions +#define M33_ID_ISAR2_MULT_RESET _u(0x3) +#define M33_ID_ISAR2_MULT_BITS _u(0x0000f000) +#define M33_ID_ISAR2_MULT_MSB _u(15) +#define M33_ID_ISAR2_MULT_LSB _u(12) +#define M33_ID_ISAR2_MULT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULTIACCESSINT +// Description : Indicates the support for interruptible multi-access +// instructions +#define M33_ID_ISAR2_MULTIACCESSINT_RESET _u(0x4) +#define M33_ID_ISAR2_MULTIACCESSINT_BITS _u(0x00000f00) +#define M33_ID_ISAR2_MULTIACCESSINT_MSB _u(11) +#define M33_ID_ISAR2_MULTIACCESSINT_LSB _u(8) +#define M33_ID_ISAR2_MULTIACCESSINT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MEMHINT +// Description : Indicates the implemented Memory Hint instructions +#define M33_ID_ISAR2_MEMHINT_RESET _u(0x2) +#define M33_ID_ISAR2_MEMHINT_BITS _u(0x000000f0) +#define M33_ID_ISAR2_MEMHINT_MSB _u(7) +#define M33_ID_ISAR2_MEMHINT_LSB _u(4) +#define M33_ID_ISAR2_MEMHINT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_LOADSTORE +// Description : Indicates the implemented additional load/store instructions +#define M33_ID_ISAR2_LOADSTORE_RESET _u(0x6) +#define M33_ID_ISAR2_LOADSTORE_BITS _u(0x0000000f) +#define M33_ID_ISAR2_LOADSTORE_MSB _u(3) +#define M33_ID_ISAR2_LOADSTORE_LSB _u(0) +#define M33_ID_ISAR2_LOADSTORE_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR3 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR3_OFFSET _u(0x0000ed6c) +#define M33_ID_ISAR3_BITS _u(0x0fffffff) +#define M33_ID_ISAR3_RESET _u(0x07895729) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_TRUENOP +// Description : Indicates the implemented true NOP instructions +#define M33_ID_ISAR3_TRUENOP_RESET _u(0x7) +#define M33_ID_ISAR3_TRUENOP_BITS _u(0x0f000000) +#define M33_ID_ISAR3_TRUENOP_MSB _u(27) +#define M33_ID_ISAR3_TRUENOP_LSB _u(24) +#define M33_ID_ISAR3_TRUENOP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_T32COPY +// Description : Indicates the support for T32 non flag-setting MOV instructions +#define M33_ID_ISAR3_T32COPY_RESET _u(0x8) +#define M33_ID_ISAR3_T32COPY_BITS _u(0x00f00000) +#define M33_ID_ISAR3_T32COPY_MSB _u(23) +#define M33_ID_ISAR3_T32COPY_LSB _u(20) +#define M33_ID_ISAR3_T32COPY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_TABBRANCH +// Description : Indicates the implemented Table Branch instructions +#define M33_ID_ISAR3_TABBRANCH_RESET _u(0x9) +#define M33_ID_ISAR3_TABBRANCH_BITS _u(0x000f0000) +#define M33_ID_ISAR3_TABBRANCH_MSB _u(19) +#define M33_ID_ISAR3_TABBRANCH_LSB _u(16) +#define M33_ID_ISAR3_TABBRANCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SYNCHPRIM +// Description : Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate +// the implemented Synchronization Primitive instructions +#define M33_ID_ISAR3_SYNCHPRIM_RESET _u(0x5) +#define M33_ID_ISAR3_SYNCHPRIM_BITS _u(0x0000f000) +#define M33_ID_ISAR3_SYNCHPRIM_MSB _u(15) +#define M33_ID_ISAR3_SYNCHPRIM_LSB _u(12) +#define M33_ID_ISAR3_SYNCHPRIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SVC +// Description : Indicates the implemented SVC instructions +#define M33_ID_ISAR3_SVC_RESET _u(0x7) +#define M33_ID_ISAR3_SVC_BITS _u(0x00000f00) +#define M33_ID_ISAR3_SVC_MSB _u(11) +#define M33_ID_ISAR3_SVC_LSB _u(8) +#define M33_ID_ISAR3_SVC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SIMD +// Description : Indicates the implemented SIMD instructions +#define M33_ID_ISAR3_SIMD_RESET _u(0x2) +#define M33_ID_ISAR3_SIMD_BITS _u(0x000000f0) +#define M33_ID_ISAR3_SIMD_MSB _u(7) +#define M33_ID_ISAR3_SIMD_LSB _u(4) +#define M33_ID_ISAR3_SIMD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SATURATE +// Description : Indicates the implemented saturating instructions +#define M33_ID_ISAR3_SATURATE_RESET _u(0x9) +#define M33_ID_ISAR3_SATURATE_BITS _u(0x0000000f) +#define M33_ID_ISAR3_SATURATE_MSB _u(3) +#define M33_ID_ISAR3_SATURATE_LSB _u(0) +#define M33_ID_ISAR3_SATURATE_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR4 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR4_OFFSET _u(0x0000ed70) +#define M33_ID_ISAR4_BITS _u(0x0fff0fff) +#define M33_ID_ISAR4_RESET _u(0x01310132) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_PSR_M +// Description : Indicates the implemented M profile instructions to modify the +// PSRs +#define M33_ID_ISAR4_PSR_M_RESET _u(0x1) +#define M33_ID_ISAR4_PSR_M_BITS _u(0x0f000000) +#define M33_ID_ISAR4_PSR_M_MSB _u(27) +#define M33_ID_ISAR4_PSR_M_LSB _u(24) +#define M33_ID_ISAR4_PSR_M_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_SYNCPRIM_FRAC +// Description : Used in conjunction with ID_ISAR3.SynchPrim to indicate the +// implemented Synchronization Primitive instructions +#define M33_ID_ISAR4_SYNCPRIM_FRAC_RESET _u(0x3) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_BITS _u(0x00f00000) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_MSB _u(23) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_LSB _u(20) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_BARRIER +// Description : Indicates the implemented Barrier instructions +#define M33_ID_ISAR4_BARRIER_RESET _u(0x1) +#define M33_ID_ISAR4_BARRIER_BITS _u(0x000f0000) +#define M33_ID_ISAR4_BARRIER_MSB _u(19) +#define M33_ID_ISAR4_BARRIER_LSB _u(16) +#define M33_ID_ISAR4_BARRIER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_WRITEBACK +// Description : Indicates the support for writeback addressing modes +#define M33_ID_ISAR4_WRITEBACK_RESET _u(0x1) +#define M33_ID_ISAR4_WRITEBACK_BITS _u(0x00000f00) +#define M33_ID_ISAR4_WRITEBACK_MSB _u(11) +#define M33_ID_ISAR4_WRITEBACK_LSB _u(8) +#define M33_ID_ISAR4_WRITEBACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_WITHSHIFTS +// Description : Indicates the support for writeback addressing modes +#define M33_ID_ISAR4_WITHSHIFTS_RESET _u(0x3) +#define M33_ID_ISAR4_WITHSHIFTS_BITS _u(0x000000f0) +#define M33_ID_ISAR4_WITHSHIFTS_MSB _u(7) +#define M33_ID_ISAR4_WITHSHIFTS_LSB _u(4) +#define M33_ID_ISAR4_WITHSHIFTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_UNPRIV +// Description : Indicates the implemented unprivileged instructions +#define M33_ID_ISAR4_UNPRIV_RESET _u(0x2) +#define M33_ID_ISAR4_UNPRIV_BITS _u(0x0000000f) +#define M33_ID_ISAR4_UNPRIV_MSB _u(3) +#define M33_ID_ISAR4_UNPRIV_LSB _u(0) +#define M33_ID_ISAR4_UNPRIV_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR5 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR5_OFFSET _u(0x0000ed74) +#define M33_ID_ISAR5_BITS _u(0x00000000) +#define M33_ID_ISAR5_RESET _u(0x00000000) +#define M33_ID_ISAR5_MSB _u(31) +#define M33_ID_ISAR5_LSB _u(0) +#define M33_ID_ISAR5_ACCESS "RW" +// ============================================================================= +// Register : M33_CTR +// Description : Provides information about the architecture of the caches. CTR +// is RES0 if CLIDR is zero. +#define M33_CTR_OFFSET _u(0x0000ed7c) +#define M33_CTR_BITS _u(0x8fffc00f) +#define M33_CTR_RESET _u(0x8000c000) +// ----------------------------------------------------------------------------- +// Field : M33_CTR_RES1 +// Description : Reserved, RES1 +#define M33_CTR_RES1_RESET _u(0x1) +#define M33_CTR_RES1_BITS _u(0x80000000) +#define M33_CTR_RES1_MSB _u(31) +#define M33_CTR_RES1_LSB _u(31) +#define M33_CTR_RES1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_CWG +// Description : Log2 of the number of words of the maximum size of memory that +// can be overwritten as a result of the eviction of a cache entry +// that has had a memory location in it modified +#define M33_CTR_CWG_RESET _u(0x0) +#define M33_CTR_CWG_BITS _u(0x0f000000) +#define M33_CTR_CWG_MSB _u(27) +#define M33_CTR_CWG_LSB _u(24) +#define M33_CTR_CWG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_ERG +// Description : Log2 of the number of words of the maximum size of the +// reservation granule that has been implemented for the Load- +// Exclusive and Store-Exclusive instructions +#define M33_CTR_ERG_RESET _u(0x0) +#define M33_CTR_ERG_BITS _u(0x00f00000) +#define M33_CTR_ERG_MSB _u(23) +#define M33_CTR_ERG_LSB _u(20) +#define M33_CTR_ERG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_DMINLINE +// Description : Log2 of the number of words in the smallest cache line of all +// the data caches and unified caches that are controlled by the +// PE +#define M33_CTR_DMINLINE_RESET _u(0x0) +#define M33_CTR_DMINLINE_BITS _u(0x000f0000) +#define M33_CTR_DMINLINE_MSB _u(19) +#define M33_CTR_DMINLINE_LSB _u(16) +#define M33_CTR_DMINLINE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_RES1_1 +// Description : Reserved, RES1 +#define M33_CTR_RES1_1_RESET _u(0x3) +#define M33_CTR_RES1_1_BITS _u(0x0000c000) +#define M33_CTR_RES1_1_MSB _u(15) +#define M33_CTR_RES1_1_LSB _u(14) +#define M33_CTR_RES1_1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_IMINLINE +// Description : Log2 of the number of words in the smallest cache line of all +// the instruction caches that are controlled by the PE +#define M33_CTR_IMINLINE_RESET _u(0x0) +#define M33_CTR_IMINLINE_BITS _u(0x0000000f) +#define M33_CTR_IMINLINE_MSB _u(3) +#define M33_CTR_IMINLINE_LSB _u(0) +#define M33_CTR_IMINLINE_ACCESS "RO" +// ============================================================================= +// Register : M33_CPACR +// Description : Specifies the access privileges for coprocessors and the FP +// Extension +#define M33_CPACR_OFFSET _u(0x0000ed88) +#define M33_CPACR_BITS _u(0x00f0ffff) +#define M33_CPACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP11 +// Description : The value in this field is ignored. If the implementation does +// not include the FP Extension, this field is RAZ/WI. If the +// value of this bit is not programmed to the same value as the +// CP10 field, then the value is UNKNOWN +#define M33_CPACR_CP11_RESET _u(0x0) +#define M33_CPACR_CP11_BITS _u(0x00c00000) +#define M33_CPACR_CP11_MSB _u(23) +#define M33_CPACR_CP11_LSB _u(22) +#define M33_CPACR_CP11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP10 +// Description : Defines the access rights for the floating-point functionality +#define M33_CPACR_CP10_RESET _u(0x0) +#define M33_CPACR_CP10_BITS _u(0x00300000) +#define M33_CPACR_CP10_MSB _u(21) +#define M33_CPACR_CP10_LSB _u(20) +#define M33_CPACR_CP10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP7 +// Description : Controls access privileges for coprocessor 7 +#define M33_CPACR_CP7_RESET _u(0x0) +#define M33_CPACR_CP7_BITS _u(0x0000c000) +#define M33_CPACR_CP7_MSB _u(15) +#define M33_CPACR_CP7_LSB _u(14) +#define M33_CPACR_CP7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP6 +// Description : Controls access privileges for coprocessor 6 +#define M33_CPACR_CP6_RESET _u(0x0) +#define M33_CPACR_CP6_BITS _u(0x00003000) +#define M33_CPACR_CP6_MSB _u(13) +#define M33_CPACR_CP6_LSB _u(12) +#define M33_CPACR_CP6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP5 +// Description : Controls access privileges for coprocessor 5 +#define M33_CPACR_CP5_RESET _u(0x0) +#define M33_CPACR_CP5_BITS _u(0x00000c00) +#define M33_CPACR_CP5_MSB _u(11) +#define M33_CPACR_CP5_LSB _u(10) +#define M33_CPACR_CP5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP4 +// Description : Controls access privileges for coprocessor 4 +#define M33_CPACR_CP4_RESET _u(0x0) +#define M33_CPACR_CP4_BITS _u(0x00000300) +#define M33_CPACR_CP4_MSB _u(9) +#define M33_CPACR_CP4_LSB _u(8) +#define M33_CPACR_CP4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP3 +// Description : Controls access privileges for coprocessor 3 +#define M33_CPACR_CP3_RESET _u(0x0) +#define M33_CPACR_CP3_BITS _u(0x000000c0) +#define M33_CPACR_CP3_MSB _u(7) +#define M33_CPACR_CP3_LSB _u(6) +#define M33_CPACR_CP3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP2 +// Description : Controls access privileges for coprocessor 2 +#define M33_CPACR_CP2_RESET _u(0x0) +#define M33_CPACR_CP2_BITS _u(0x00000030) +#define M33_CPACR_CP2_MSB _u(5) +#define M33_CPACR_CP2_LSB _u(4) +#define M33_CPACR_CP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP1 +// Description : Controls access privileges for coprocessor 1 +#define M33_CPACR_CP1_RESET _u(0x0) +#define M33_CPACR_CP1_BITS _u(0x0000000c) +#define M33_CPACR_CP1_MSB _u(3) +#define M33_CPACR_CP1_LSB _u(2) +#define M33_CPACR_CP1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP0 +// Description : Controls access privileges for coprocessor 0 +#define M33_CPACR_CP0_RESET _u(0x0) +#define M33_CPACR_CP0_BITS _u(0x00000003) +#define M33_CPACR_CP0_MSB _u(1) +#define M33_CPACR_CP0_LSB _u(0) +#define M33_CPACR_CP0_ACCESS "RW" +// ============================================================================= +// Register : M33_NSACR +// Description : Defines the Non-secure access permissions for both the FP +// Extension and coprocessors CP0 to CP7 +#define M33_NSACR_OFFSET _u(0x0000ed8c) +#define M33_NSACR_BITS _u(0x00000cff) +#define M33_NSACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP11 +// Description : Enables Non-secure access to the Floating-point Extension +#define M33_NSACR_CP11_RESET _u(0x0) +#define M33_NSACR_CP11_BITS _u(0x00000800) +#define M33_NSACR_CP11_MSB _u(11) +#define M33_NSACR_CP11_LSB _u(11) +#define M33_NSACR_CP11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP10 +// Description : Enables Non-secure access to the Floating-point Extension +#define M33_NSACR_CP10_RESET _u(0x0) +#define M33_NSACR_CP10_BITS _u(0x00000400) +#define M33_NSACR_CP10_MSB _u(10) +#define M33_NSACR_CP10_LSB _u(10) +#define M33_NSACR_CP10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP7 +// Description : Enables Non-secure access to coprocessor CP7 +#define M33_NSACR_CP7_RESET _u(0x0) +#define M33_NSACR_CP7_BITS _u(0x00000080) +#define M33_NSACR_CP7_MSB _u(7) +#define M33_NSACR_CP7_LSB _u(7) +#define M33_NSACR_CP7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP6 +// Description : Enables Non-secure access to coprocessor CP6 +#define M33_NSACR_CP6_RESET _u(0x0) +#define M33_NSACR_CP6_BITS _u(0x00000040) +#define M33_NSACR_CP6_MSB _u(6) +#define M33_NSACR_CP6_LSB _u(6) +#define M33_NSACR_CP6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP5 +// Description : Enables Non-secure access to coprocessor CP5 +#define M33_NSACR_CP5_RESET _u(0x0) +#define M33_NSACR_CP5_BITS _u(0x00000020) +#define M33_NSACR_CP5_MSB _u(5) +#define M33_NSACR_CP5_LSB _u(5) +#define M33_NSACR_CP5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP4 +// Description : Enables Non-secure access to coprocessor CP4 +#define M33_NSACR_CP4_RESET _u(0x0) +#define M33_NSACR_CP4_BITS _u(0x00000010) +#define M33_NSACR_CP4_MSB _u(4) +#define M33_NSACR_CP4_LSB _u(4) +#define M33_NSACR_CP4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP3 +// Description : Enables Non-secure access to coprocessor CP3 +#define M33_NSACR_CP3_RESET _u(0x0) +#define M33_NSACR_CP3_BITS _u(0x00000008) +#define M33_NSACR_CP3_MSB _u(3) +#define M33_NSACR_CP3_LSB _u(3) +#define M33_NSACR_CP3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP2 +// Description : Enables Non-secure access to coprocessor CP2 +#define M33_NSACR_CP2_RESET _u(0x0) +#define M33_NSACR_CP2_BITS _u(0x00000004) +#define M33_NSACR_CP2_MSB _u(2) +#define M33_NSACR_CP2_LSB _u(2) +#define M33_NSACR_CP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP1 +// Description : Enables Non-secure access to coprocessor CP1 +#define M33_NSACR_CP1_RESET _u(0x0) +#define M33_NSACR_CP1_BITS _u(0x00000002) +#define M33_NSACR_CP1_MSB _u(1) +#define M33_NSACR_CP1_LSB _u(1) +#define M33_NSACR_CP1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP0 +// Description : Enables Non-secure access to coprocessor CP0 +#define M33_NSACR_CP0_RESET _u(0x0) +#define M33_NSACR_CP0_BITS _u(0x00000001) +#define M33_NSACR_CP0_MSB _u(0) +#define M33_NSACR_CP0_LSB _u(0) +#define M33_NSACR_CP0_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_TYPE +// Description : The MPU Type Register indicates how many regions the MPU `FTSSS +// supports +#define M33_MPU_TYPE_OFFSET _u(0x0000ed90) +#define M33_MPU_TYPE_BITS _u(0x0000ff01) +#define M33_MPU_TYPE_RESET _u(0x00000800) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_TYPE_DREGION +// Description : Number of regions supported by the MPU +#define M33_MPU_TYPE_DREGION_RESET _u(0x08) +#define M33_MPU_TYPE_DREGION_BITS _u(0x0000ff00) +#define M33_MPU_TYPE_DREGION_MSB _u(15) +#define M33_MPU_TYPE_DREGION_LSB _u(8) +#define M33_MPU_TYPE_DREGION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_TYPE_SEPARATE +// Description : Indicates support for separate instructions and data address +// regions +#define M33_MPU_TYPE_SEPARATE_RESET _u(0x0) +#define M33_MPU_TYPE_SEPARATE_BITS _u(0x00000001) +#define M33_MPU_TYPE_SEPARATE_MSB _u(0) +#define M33_MPU_TYPE_SEPARATE_LSB _u(0) +#define M33_MPU_TYPE_SEPARATE_ACCESS "RO" +// ============================================================================= +// Register : M33_MPU_CTRL +// Description : Enables the MPU and, when the MPU is enabled, controls whether +// the default memory map is enabled as a background region for +// privileged accesses, and whether the MPU is enabled for +// HardFaults, NMIs, and exception handlers when FAULTMASK is set +// to 1 +#define M33_MPU_CTRL_OFFSET _u(0x0000ed94) +#define M33_MPU_CTRL_BITS _u(0x00000007) +#define M33_MPU_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_CTRL_PRIVDEFENA +// Description : Controls whether the default memory map is enabled for +// privileged software +#define M33_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) +#define M33_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) +#define M33_MPU_CTRL_PRIVDEFENA_MSB _u(2) +#define M33_MPU_CTRL_PRIVDEFENA_LSB _u(2) +#define M33_MPU_CTRL_PRIVDEFENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_CTRL_HFNMIENA +// Description : Controls whether handlers executing with priority less than 0 +// access memory with the MPU enabled or disabled. This applies to +// HardFaults, NMIs, and exception handlers when FAULTMASK is set +// to 1 +#define M33_MPU_CTRL_HFNMIENA_RESET _u(0x0) +#define M33_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) +#define M33_MPU_CTRL_HFNMIENA_MSB _u(1) +#define M33_MPU_CTRL_HFNMIENA_LSB _u(1) +#define M33_MPU_CTRL_HFNMIENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_CTRL_ENABLE +// Description : Enables the MPU +#define M33_MPU_CTRL_ENABLE_RESET _u(0x0) +#define M33_MPU_CTRL_ENABLE_BITS _u(0x00000001) +#define M33_MPU_CTRL_ENABLE_MSB _u(0) +#define M33_MPU_CTRL_ENABLE_LSB _u(0) +#define M33_MPU_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RNR +// Description : Selects the region currently accessed by MPU_RBAR and MPU_RLAR +#define M33_MPU_RNR_OFFSET _u(0x0000ed98) +#define M33_MPU_RNR_BITS _u(0x00000007) +#define M33_MPU_RNR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RNR_REGION +// Description : Indicates the memory region accessed by MPU_RBAR and MPU_RLAR +#define M33_MPU_RNR_REGION_RESET _u(0x0) +#define M33_MPU_RNR_REGION_BITS _u(0x00000007) +#define M33_MPU_RNR_REGION_MSB _u(2) +#define M33_MPU_RNR_REGION_LSB _u(0) +#define M33_MPU_RNR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR +// Description : Provides indirect read and write access to the base address of +// the currently selected MPU region `FTSSS +#define M33_MPU_RBAR_OFFSET _u(0x0000ed9c) +#define M33_MPU_RBAR_BITS _u(0xffffffff) +#define M33_MPU_RBAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_BASE_MSB _u(31) +#define M33_MPU_RBAR_BASE_LSB _u(5) +#define M33_MPU_RBAR_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_SH_RESET _u(0x0) +#define M33_MPU_RBAR_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_SH_MSB _u(4) +#define M33_MPU_RBAR_SH_LSB _u(3) +#define M33_MPU_RBAR_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_AP_RESET _u(0x0) +#define M33_MPU_RBAR_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_AP_MSB _u(2) +#define M33_MPU_RBAR_AP_LSB _u(1) +#define M33_MPU_RBAR_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_XN_RESET _u(0x0) +#define M33_MPU_RBAR_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_XN_MSB _u(0) +#define M33_MPU_RBAR_XN_LSB _u(0) +#define M33_MPU_RBAR_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region `FTSSS +#define M33_MPU_RLAR_OFFSET _u(0x0000eda0) +#define M33_MPU_RLAR_BITS _u(0xffffffef) +#define M33_MPU_RLAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_EN +// Description : Region enable +#define M33_MPU_RLAR_EN_RESET _u(0x0) +#define M33_MPU_RLAR_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_EN_MSB _u(0) +#define M33_MPU_RLAR_EN_LSB _u(0) +#define M33_MPU_RLAR_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR_A1 +// Description : Provides indirect read and write access to the base address of +// the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS +#define M33_MPU_RBAR_A1_OFFSET _u(0x0000eda4) +#define M33_MPU_RBAR_A1_BITS _u(0xffffffff) +#define M33_MPU_RBAR_A1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_A1_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_A1_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_A1_BASE_MSB _u(31) +#define M33_MPU_RBAR_A1_BASE_LSB _u(5) +#define M33_MPU_RBAR_A1_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_A1_SH_RESET _u(0x0) +#define M33_MPU_RBAR_A1_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_A1_SH_MSB _u(4) +#define M33_MPU_RBAR_A1_SH_LSB _u(3) +#define M33_MPU_RBAR_A1_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_A1_AP_RESET _u(0x0) +#define M33_MPU_RBAR_A1_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_A1_AP_MSB _u(2) +#define M33_MPU_RBAR_A1_AP_LSB _u(1) +#define M33_MPU_RBAR_A1_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_A1_XN_RESET _u(0x0) +#define M33_MPU_RBAR_A1_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_A1_XN_MSB _u(0) +#define M33_MPU_RBAR_A1_XN_LSB _u(0) +#define M33_MPU_RBAR_A1_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR_A1 +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region selected by +// MPU_RNR[7:2]:(1[1:0]) `FTSSS +#define M33_MPU_RLAR_A1_OFFSET _u(0x0000eda8) +#define M33_MPU_RLAR_A1_BITS _u(0xffffffef) +#define M33_MPU_RLAR_A1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A1_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_A1_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_A1_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_A1_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_A1_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_A1_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A1_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_A1_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_A1_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_A1_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_A1_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_A1_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A1_EN +// Description : Region enable +#define M33_MPU_RLAR_A1_EN_RESET _u(0x0) +#define M33_MPU_RLAR_A1_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_A1_EN_MSB _u(0) +#define M33_MPU_RLAR_A1_EN_LSB _u(0) +#define M33_MPU_RLAR_A1_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR_A2 +// Description : Provides indirect read and write access to the base address of +// the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS +#define M33_MPU_RBAR_A2_OFFSET _u(0x0000edac) +#define M33_MPU_RBAR_A2_BITS _u(0xffffffff) +#define M33_MPU_RBAR_A2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_A2_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_A2_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_A2_BASE_MSB _u(31) +#define M33_MPU_RBAR_A2_BASE_LSB _u(5) +#define M33_MPU_RBAR_A2_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_A2_SH_RESET _u(0x0) +#define M33_MPU_RBAR_A2_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_A2_SH_MSB _u(4) +#define M33_MPU_RBAR_A2_SH_LSB _u(3) +#define M33_MPU_RBAR_A2_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_A2_AP_RESET _u(0x0) +#define M33_MPU_RBAR_A2_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_A2_AP_MSB _u(2) +#define M33_MPU_RBAR_A2_AP_LSB _u(1) +#define M33_MPU_RBAR_A2_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_A2_XN_RESET _u(0x0) +#define M33_MPU_RBAR_A2_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_A2_XN_MSB _u(0) +#define M33_MPU_RBAR_A2_XN_LSB _u(0) +#define M33_MPU_RBAR_A2_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR_A2 +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region selected by +// MPU_RNR[7:2]:(2[1:0]) `FTSSS +#define M33_MPU_RLAR_A2_OFFSET _u(0x0000edb0) +#define M33_MPU_RLAR_A2_BITS _u(0xffffffef) +#define M33_MPU_RLAR_A2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A2_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_A2_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_A2_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_A2_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_A2_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_A2_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A2_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_A2_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_A2_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_A2_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_A2_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_A2_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A2_EN +// Description : Region enable +#define M33_MPU_RLAR_A2_EN_RESET _u(0x0) +#define M33_MPU_RLAR_A2_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_A2_EN_MSB _u(0) +#define M33_MPU_RLAR_A2_EN_LSB _u(0) +#define M33_MPU_RLAR_A2_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR_A3 +// Description : Provides indirect read and write access to the base address of +// the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS +#define M33_MPU_RBAR_A3_OFFSET _u(0x0000edb4) +#define M33_MPU_RBAR_A3_BITS _u(0xffffffff) +#define M33_MPU_RBAR_A3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_A3_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_A3_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_A3_BASE_MSB _u(31) +#define M33_MPU_RBAR_A3_BASE_LSB _u(5) +#define M33_MPU_RBAR_A3_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_A3_SH_RESET _u(0x0) +#define M33_MPU_RBAR_A3_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_A3_SH_MSB _u(4) +#define M33_MPU_RBAR_A3_SH_LSB _u(3) +#define M33_MPU_RBAR_A3_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_A3_AP_RESET _u(0x0) +#define M33_MPU_RBAR_A3_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_A3_AP_MSB _u(2) +#define M33_MPU_RBAR_A3_AP_LSB _u(1) +#define M33_MPU_RBAR_A3_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_A3_XN_RESET _u(0x0) +#define M33_MPU_RBAR_A3_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_A3_XN_MSB _u(0) +#define M33_MPU_RBAR_A3_XN_LSB _u(0) +#define M33_MPU_RBAR_A3_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR_A3 +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region selected by +// MPU_RNR[7:2]:(3[1:0]) `FTSSS +#define M33_MPU_RLAR_A3_OFFSET _u(0x0000edb8) +#define M33_MPU_RLAR_A3_BITS _u(0xffffffef) +#define M33_MPU_RLAR_A3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A3_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_A3_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_A3_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_A3_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_A3_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_A3_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A3_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_A3_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_A3_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_A3_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_A3_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_A3_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A3_EN +// Description : Region enable +#define M33_MPU_RLAR_A3_EN_RESET _u(0x0) +#define M33_MPU_RLAR_A3_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_A3_EN_MSB _u(0) +#define M33_MPU_RLAR_A3_EN_LSB _u(0) +#define M33_MPU_RLAR_A3_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_MAIR0 +// Description : Along with MPU_MAIR1, provides the memory attribute encodings +// corresponding to the AttrIndex values +#define M33_MPU_MAIR0_OFFSET _u(0x0000edc0) +#define M33_MPU_MAIR0_BITS _u(0xffffffff) +#define M33_MPU_MAIR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR3 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 3 +#define M33_MPU_MAIR0_ATTR3_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR3_BITS _u(0xff000000) +#define M33_MPU_MAIR0_ATTR3_MSB _u(31) +#define M33_MPU_MAIR0_ATTR3_LSB _u(24) +#define M33_MPU_MAIR0_ATTR3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR2 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 2 +#define M33_MPU_MAIR0_ATTR2_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR2_BITS _u(0x00ff0000) +#define M33_MPU_MAIR0_ATTR2_MSB _u(23) +#define M33_MPU_MAIR0_ATTR2_LSB _u(16) +#define M33_MPU_MAIR0_ATTR2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR1 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 1 +#define M33_MPU_MAIR0_ATTR1_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR1_BITS _u(0x0000ff00) +#define M33_MPU_MAIR0_ATTR1_MSB _u(15) +#define M33_MPU_MAIR0_ATTR1_LSB _u(8) +#define M33_MPU_MAIR0_ATTR1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR0 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 0 +#define M33_MPU_MAIR0_ATTR0_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR0_BITS _u(0x000000ff) +#define M33_MPU_MAIR0_ATTR0_MSB _u(7) +#define M33_MPU_MAIR0_ATTR0_LSB _u(0) +#define M33_MPU_MAIR0_ATTR0_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_MAIR1 +// Description : Along with MPU_MAIR0, provides the memory attribute encodings +// corresponding to the AttrIndex values +#define M33_MPU_MAIR1_OFFSET _u(0x0000edc4) +#define M33_MPU_MAIR1_BITS _u(0xffffffff) +#define M33_MPU_MAIR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR7 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 7 +#define M33_MPU_MAIR1_ATTR7_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR7_BITS _u(0xff000000) +#define M33_MPU_MAIR1_ATTR7_MSB _u(31) +#define M33_MPU_MAIR1_ATTR7_LSB _u(24) +#define M33_MPU_MAIR1_ATTR7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR6 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 6 +#define M33_MPU_MAIR1_ATTR6_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR6_BITS _u(0x00ff0000) +#define M33_MPU_MAIR1_ATTR6_MSB _u(23) +#define M33_MPU_MAIR1_ATTR6_LSB _u(16) +#define M33_MPU_MAIR1_ATTR6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR5 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 5 +#define M33_MPU_MAIR1_ATTR5_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR5_BITS _u(0x0000ff00) +#define M33_MPU_MAIR1_ATTR5_MSB _u(15) +#define M33_MPU_MAIR1_ATTR5_LSB _u(8) +#define M33_MPU_MAIR1_ATTR5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR4 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 4 +#define M33_MPU_MAIR1_ATTR4_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR4_BITS _u(0x000000ff) +#define M33_MPU_MAIR1_ATTR4_MSB _u(7) +#define M33_MPU_MAIR1_ATTR4_LSB _u(0) +#define M33_MPU_MAIR1_ATTR4_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_CTRL +// Description : Allows enabling of the Security Attribution Unit +#define M33_SAU_CTRL_OFFSET _u(0x0000edd0) +#define M33_SAU_CTRL_BITS _u(0x00000003) +#define M33_SAU_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_CTRL_ALLNS +// Description : When SAU_CTRL.ENABLE is 0 this bit controls if the memory is +// marked as Non-secure or Secure +#define M33_SAU_CTRL_ALLNS_RESET _u(0x0) +#define M33_SAU_CTRL_ALLNS_BITS _u(0x00000002) +#define M33_SAU_CTRL_ALLNS_MSB _u(1) +#define M33_SAU_CTRL_ALLNS_LSB _u(1) +#define M33_SAU_CTRL_ALLNS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SAU_CTRL_ENABLE +// Description : Enables the SAU +#define M33_SAU_CTRL_ENABLE_RESET _u(0x0) +#define M33_SAU_CTRL_ENABLE_BITS _u(0x00000001) +#define M33_SAU_CTRL_ENABLE_MSB _u(0) +#define M33_SAU_CTRL_ENABLE_LSB _u(0) +#define M33_SAU_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_TYPE +// Description : Indicates the number of regions implemented by the Security +// Attribution Unit +#define M33_SAU_TYPE_OFFSET _u(0x0000edd4) +#define M33_SAU_TYPE_BITS _u(0x000000ff) +#define M33_SAU_TYPE_RESET _u(0x00000008) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_TYPE_SREGION +// Description : The number of implemented SAU regions +#define M33_SAU_TYPE_SREGION_RESET _u(0x08) +#define M33_SAU_TYPE_SREGION_BITS _u(0x000000ff) +#define M33_SAU_TYPE_SREGION_MSB _u(7) +#define M33_SAU_TYPE_SREGION_LSB _u(0) +#define M33_SAU_TYPE_SREGION_ACCESS "RO" +// ============================================================================= +// Register : M33_SAU_RNR +// Description : Selects the region currently accessed by SAU_RBAR and SAU_RLAR +#define M33_SAU_RNR_OFFSET _u(0x0000edd8) +#define M33_SAU_RNR_BITS _u(0x000000ff) +#define M33_SAU_RNR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RNR_REGION +// Description : Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR +#define M33_SAU_RNR_REGION_RESET _u(0x00) +#define M33_SAU_RNR_REGION_BITS _u(0x000000ff) +#define M33_SAU_RNR_REGION_MSB _u(7) +#define M33_SAU_RNR_REGION_LSB _u(0) +#define M33_SAU_RNR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_RBAR +// Description : Provides indirect read and write access to the base address of +// the currently selected SAU region +#define M33_SAU_RBAR_OFFSET _u(0x0000eddc) +#define M33_SAU_RBAR_BITS _u(0xffffffe0) +#define M33_SAU_RBAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RBAR_BADDR +// Description : Holds bits [31:5] of the base address for the selected SAU +// region +#define M33_SAU_RBAR_BADDR_RESET _u(0x0000000) +#define M33_SAU_RBAR_BADDR_BITS _u(0xffffffe0) +#define M33_SAU_RBAR_BADDR_MSB _u(31) +#define M33_SAU_RBAR_BADDR_LSB _u(5) +#define M33_SAU_RBAR_BADDR_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_RLAR +// Description : Provides indirect read and write access to the limit address of +// the currently selected SAU region +#define M33_SAU_RLAR_OFFSET _u(0x0000ede0) +#define M33_SAU_RLAR_BITS _u(0xffffffe3) +#define M33_SAU_RLAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RLAR_LADDR +// Description : Holds bits [31:5] of the limit address for the selected SAU +// region +#define M33_SAU_RLAR_LADDR_RESET _u(0x0000000) +#define M33_SAU_RLAR_LADDR_BITS _u(0xffffffe0) +#define M33_SAU_RLAR_LADDR_MSB _u(31) +#define M33_SAU_RLAR_LADDR_LSB _u(5) +#define M33_SAU_RLAR_LADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RLAR_NSC +// Description : Controls whether Non-secure state is permitted to execute an SG +// instruction from this region +#define M33_SAU_RLAR_NSC_RESET _u(0x0) +#define M33_SAU_RLAR_NSC_BITS _u(0x00000002) +#define M33_SAU_RLAR_NSC_MSB _u(1) +#define M33_SAU_RLAR_NSC_LSB _u(1) +#define M33_SAU_RLAR_NSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RLAR_ENABLE +// Description : SAU region enable +#define M33_SAU_RLAR_ENABLE_RESET _u(0x0) +#define M33_SAU_RLAR_ENABLE_BITS _u(0x00000001) +#define M33_SAU_RLAR_ENABLE_MSB _u(0) +#define M33_SAU_RLAR_ENABLE_LSB _u(0) +#define M33_SAU_RLAR_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_SFSR +// Description : Provides information about any security related faults +#define M33_SFSR_OFFSET _u(0x0000ede4) +#define M33_SFSR_BITS _u(0x000000ff) +#define M33_SFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_LSERR +// Description : Sticky flag indicating that an error occurred during lazy state +// activation or deactivation +#define M33_SFSR_LSERR_RESET _u(0x0) +#define M33_SFSR_LSERR_BITS _u(0x00000080) +#define M33_SFSR_LSERR_MSB _u(7) +#define M33_SFSR_LSERR_LSB _u(7) +#define M33_SFSR_LSERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_SFARVALID +// Description : This bit is set when the SFAR register contains a valid value. +// As with similar fields, such as BFSR.BFARVALID and +// MMFSR.MMARVALID, this bit can be cleared by other exceptions, +// such as BusFault +#define M33_SFSR_SFARVALID_RESET _u(0x0) +#define M33_SFSR_SFARVALID_BITS _u(0x00000040) +#define M33_SFSR_SFARVALID_MSB _u(6) +#define M33_SFSR_SFARVALID_LSB _u(6) +#define M33_SFSR_SFARVALID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_LSPERR +// Description : Stick flag indicating that an SAU or IDAU violation occurred +// during the lazy preservation of floating-point state +#define M33_SFSR_LSPERR_RESET _u(0x0) +#define M33_SFSR_LSPERR_BITS _u(0x00000020) +#define M33_SFSR_LSPERR_MSB _u(5) +#define M33_SFSR_LSPERR_LSB _u(5) +#define M33_SFSR_LSPERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVTRAN +// Description : Sticky flag indicating that an exception was raised due to a +// branch that was not flagged as being domain crossing causing a +// transition from Secure to Non-secure memory +#define M33_SFSR_INVTRAN_RESET _u(0x0) +#define M33_SFSR_INVTRAN_BITS _u(0x00000010) +#define M33_SFSR_INVTRAN_MSB _u(4) +#define M33_SFSR_INVTRAN_LSB _u(4) +#define M33_SFSR_INVTRAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_AUVIOL +// Description : Sticky flag indicating that an attempt was made to access parts +// of the address space that are marked as Secure with NS-Req for +// the transaction set to Non-secure. This bit is not set if the +// violation occurred during lazy state preservation. See LSPERR +#define M33_SFSR_AUVIOL_RESET _u(0x0) +#define M33_SFSR_AUVIOL_BITS _u(0x00000008) +#define M33_SFSR_AUVIOL_MSB _u(3) +#define M33_SFSR_AUVIOL_LSB _u(3) +#define M33_SFSR_AUVIOL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVER +// Description : This can be caused by EXC_RETURN.DCRS being set to 0 when +// returning from an exception in the Non-secure state, or by +// EXC_RETURN.ES being set to 1 when returning from an exception +// in the Non-secure state +#define M33_SFSR_INVER_RESET _u(0x0) +#define M33_SFSR_INVER_BITS _u(0x00000004) +#define M33_SFSR_INVER_MSB _u(2) +#define M33_SFSR_INVER_LSB _u(2) +#define M33_SFSR_INVER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVIS +// Description : This bit is set if the integrity signature in an exception +// stack frame is found to be invalid during the unstacking +// operation +#define M33_SFSR_INVIS_RESET _u(0x0) +#define M33_SFSR_INVIS_BITS _u(0x00000002) +#define M33_SFSR_INVIS_MSB _u(1) +#define M33_SFSR_INVIS_LSB _u(1) +#define M33_SFSR_INVIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVEP +// Description : This bit is set if a function call from the Non-secure state or +// exception targets a non-SG instruction in the Secure state. +// This bit is also set if the target address is a SG instruction, +// but there is no matching SAU/IDAU region with the NSC flag set +#define M33_SFSR_INVEP_RESET _u(0x0) +#define M33_SFSR_INVEP_BITS _u(0x00000001) +#define M33_SFSR_INVEP_MSB _u(0) +#define M33_SFSR_INVEP_LSB _u(0) +#define M33_SFSR_INVEP_ACCESS "RW" +// ============================================================================= +// Register : M33_SFAR +// Description : Shows the address of the memory location that caused a Security +// violation +#define M33_SFAR_OFFSET _u(0x0000ede8) +#define M33_SFAR_BITS _u(0xffffffff) +#define M33_SFAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SFAR_ADDRESS +// Description : The address of an access that caused a attribution unit +// violation. This field is only valid when SFSR.SFARVALID is set. +// This allows the actual flip flops associated with this register +// to be shared with other fault address registers. If an +// implementation chooses to share the storage in this way, care +// must be taken to not leak Secure address information to the +// Non-secure state. One way of achieving this is to share the +// SFAR register with the MMFAR_S register, which is not +// accessible to the Non-secure state +#define M33_SFAR_ADDRESS_RESET _u(0x00000000) +#define M33_SFAR_ADDRESS_BITS _u(0xffffffff) +#define M33_SFAR_ADDRESS_MSB _u(31) +#define M33_SFAR_ADDRESS_LSB _u(0) +#define M33_SFAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_DHCSR +// Description : Controls halting debug +#define M33_DHCSR_OFFSET _u(0x0000edf0) +#define M33_DHCSR_BITS _u(0x071f002f) +#define M33_DHCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_RESTART_ST +// Description : Indicates the PE has processed a request to clear DHCSR.C_HALT +// to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT +// from 1 to 0, or an External Restart Request +#define M33_DHCSR_S_RESTART_ST_RESET _u(0x0) +#define M33_DHCSR_S_RESTART_ST_BITS _u(0x04000000) +#define M33_DHCSR_S_RESTART_ST_MSB _u(26) +#define M33_DHCSR_S_RESTART_ST_LSB _u(26) +#define M33_DHCSR_S_RESTART_ST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_RESET_ST +// Description : Indicates whether the PE has been reset since the last read of +// the DHCSR +#define M33_DHCSR_S_RESET_ST_RESET _u(0x0) +#define M33_DHCSR_S_RESET_ST_BITS _u(0x02000000) +#define M33_DHCSR_S_RESET_ST_MSB _u(25) +#define M33_DHCSR_S_RESET_ST_LSB _u(25) +#define M33_DHCSR_S_RESET_ST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_RETIRE_ST +// Description : Set to 1 every time the PE retires one of more instructions +#define M33_DHCSR_S_RETIRE_ST_RESET _u(0x0) +#define M33_DHCSR_S_RETIRE_ST_BITS _u(0x01000000) +#define M33_DHCSR_S_RETIRE_ST_MSB _u(24) +#define M33_DHCSR_S_RETIRE_ST_LSB _u(24) +#define M33_DHCSR_S_RETIRE_ST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_SDE +// Description : Indicates whether Secure invasive debug is allowed +#define M33_DHCSR_S_SDE_RESET _u(0x0) +#define M33_DHCSR_S_SDE_BITS _u(0x00100000) +#define M33_DHCSR_S_SDE_MSB _u(20) +#define M33_DHCSR_S_SDE_LSB _u(20) +#define M33_DHCSR_S_SDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_LOCKUP +// Description : Indicates whether the PE is in Lockup state +#define M33_DHCSR_S_LOCKUP_RESET _u(0x0) +#define M33_DHCSR_S_LOCKUP_BITS _u(0x00080000) +#define M33_DHCSR_S_LOCKUP_MSB _u(19) +#define M33_DHCSR_S_LOCKUP_LSB _u(19) +#define M33_DHCSR_S_LOCKUP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_SLEEP +// Description : Indicates whether the PE is sleeping +#define M33_DHCSR_S_SLEEP_RESET _u(0x0) +#define M33_DHCSR_S_SLEEP_BITS _u(0x00040000) +#define M33_DHCSR_S_SLEEP_MSB _u(18) +#define M33_DHCSR_S_SLEEP_LSB _u(18) +#define M33_DHCSR_S_SLEEP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_HALT +// Description : Indicates whether the PE is in Debug state +#define M33_DHCSR_S_HALT_RESET _u(0x0) +#define M33_DHCSR_S_HALT_BITS _u(0x00020000) +#define M33_DHCSR_S_HALT_MSB _u(17) +#define M33_DHCSR_S_HALT_LSB _u(17) +#define M33_DHCSR_S_HALT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_REGRDY +// Description : Handshake flag to transfers through the DCRDR +#define M33_DHCSR_S_REGRDY_RESET _u(0x0) +#define M33_DHCSR_S_REGRDY_BITS _u(0x00010000) +#define M33_DHCSR_S_REGRDY_MSB _u(16) +#define M33_DHCSR_S_REGRDY_LSB _u(16) +#define M33_DHCSR_S_REGRDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_SNAPSTALL +// Description : Allow imprecise entry to Debug state +#define M33_DHCSR_C_SNAPSTALL_RESET _u(0x0) +#define M33_DHCSR_C_SNAPSTALL_BITS _u(0x00000020) +#define M33_DHCSR_C_SNAPSTALL_MSB _u(5) +#define M33_DHCSR_C_SNAPSTALL_LSB _u(5) +#define M33_DHCSR_C_SNAPSTALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_MASKINTS +// Description : When debug is enabled, the debugger can write to this bit to +// mask PendSV, SysTick and external configurable interrupts +#define M33_DHCSR_C_MASKINTS_RESET _u(0x0) +#define M33_DHCSR_C_MASKINTS_BITS _u(0x00000008) +#define M33_DHCSR_C_MASKINTS_MSB _u(3) +#define M33_DHCSR_C_MASKINTS_LSB _u(3) +#define M33_DHCSR_C_MASKINTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_STEP +// Description : Enable single instruction step +#define M33_DHCSR_C_STEP_RESET _u(0x0) +#define M33_DHCSR_C_STEP_BITS _u(0x00000004) +#define M33_DHCSR_C_STEP_MSB _u(2) +#define M33_DHCSR_C_STEP_LSB _u(2) +#define M33_DHCSR_C_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_HALT +// Description : PE enter Debug state halt request +#define M33_DHCSR_C_HALT_RESET _u(0x0) +#define M33_DHCSR_C_HALT_BITS _u(0x00000002) +#define M33_DHCSR_C_HALT_MSB _u(1) +#define M33_DHCSR_C_HALT_LSB _u(1) +#define M33_DHCSR_C_HALT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_DEBUGEN +// Description : Enable Halting debug +#define M33_DHCSR_C_DEBUGEN_RESET _u(0x0) +#define M33_DHCSR_C_DEBUGEN_BITS _u(0x00000001) +#define M33_DHCSR_C_DEBUGEN_MSB _u(0) +#define M33_DHCSR_C_DEBUGEN_LSB _u(0) +#define M33_DHCSR_C_DEBUGEN_ACCESS "RW" +// ============================================================================= +// Register : M33_DCRSR +// Description : With the DCRDR, provides debug access to the general-purpose +// registers, special-purpose registers, and the FP extension +// registers. A write to the DCRSR specifies the register to +// transfer, whether the transfer is a read or write, and starts +// the transfer +#define M33_DCRSR_OFFSET _u(0x0000edf4) +#define M33_DCRSR_BITS _u(0x0001007f) +#define M33_DCRSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DCRSR_REGWNR +// Description : Specifies the access type for the transfer +#define M33_DCRSR_REGWNR_RESET _u(0x0) +#define M33_DCRSR_REGWNR_BITS _u(0x00010000) +#define M33_DCRSR_REGWNR_MSB _u(16) +#define M33_DCRSR_REGWNR_LSB _u(16) +#define M33_DCRSR_REGWNR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DCRSR_REGSEL +// Description : Specifies the general-purpose register, special-purpose +// register, or FP register to transfer +#define M33_DCRSR_REGSEL_RESET _u(0x00) +#define M33_DCRSR_REGSEL_BITS _u(0x0000007f) +#define M33_DCRSR_REGSEL_MSB _u(6) +#define M33_DCRSR_REGSEL_LSB _u(0) +#define M33_DCRSR_REGSEL_ACCESS "RW" +// ============================================================================= +// Register : M33_DCRDR +// Description : With the DCRSR, provides debug access to the general-purpose +// registers, special-purpose registers, and the FP Extension +// registers. If the Main Extension is implemented, it can also be +// used for message passing between an external debugger and a +// debug agent running on the PE +#define M33_DCRDR_OFFSET _u(0x0000edf8) +#define M33_DCRDR_BITS _u(0xffffffff) +#define M33_DCRDR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DCRDR_DBGTMP +// Description : Provides debug access for reading and writing the general- +// purpose registers, special-purpose registers, and Floating- +// point Extension registers +#define M33_DCRDR_DBGTMP_RESET _u(0x00000000) +#define M33_DCRDR_DBGTMP_BITS _u(0xffffffff) +#define M33_DCRDR_DBGTMP_MSB _u(31) +#define M33_DCRDR_DBGTMP_LSB _u(0) +#define M33_DCRDR_DBGTMP_ACCESS "RW" +// ============================================================================= +// Register : M33_DEMCR +// Description : Manages vector catch behavior and DebugMonitor handling when +// debugging +#define M33_DEMCR_OFFSET _u(0x0000edfc) +#define M33_DEMCR_BITS _u(0x011f0ff1) +#define M33_DEMCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_TRCENA +// Description : Global enable for all DWT and ITM features +#define M33_DEMCR_TRCENA_RESET _u(0x0) +#define M33_DEMCR_TRCENA_BITS _u(0x01000000) +#define M33_DEMCR_TRCENA_MSB _u(24) +#define M33_DEMCR_TRCENA_LSB _u(24) +#define M33_DEMCR_TRCENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_SDME +// Description : Indicates whether the DebugMonitor targets the Secure or the +// Non-secure state and whether debug events are allowed in Secure +// state +#define M33_DEMCR_SDME_RESET _u(0x0) +#define M33_DEMCR_SDME_BITS _u(0x00100000) +#define M33_DEMCR_SDME_MSB _u(20) +#define M33_DEMCR_SDME_LSB _u(20) +#define M33_DEMCR_SDME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_REQ +// Description : DebugMonitor semaphore bit +#define M33_DEMCR_MON_REQ_RESET _u(0x0) +#define M33_DEMCR_MON_REQ_BITS _u(0x00080000) +#define M33_DEMCR_MON_REQ_MSB _u(19) +#define M33_DEMCR_MON_REQ_LSB _u(19) +#define M33_DEMCR_MON_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_STEP +// Description : Enable DebugMonitor stepping +#define M33_DEMCR_MON_STEP_RESET _u(0x0) +#define M33_DEMCR_MON_STEP_BITS _u(0x00040000) +#define M33_DEMCR_MON_STEP_MSB _u(18) +#define M33_DEMCR_MON_STEP_LSB _u(18) +#define M33_DEMCR_MON_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_PEND +// Description : Sets or clears the pending state of the DebugMonitor exception +#define M33_DEMCR_MON_PEND_RESET _u(0x0) +#define M33_DEMCR_MON_PEND_BITS _u(0x00020000) +#define M33_DEMCR_MON_PEND_MSB _u(17) +#define M33_DEMCR_MON_PEND_LSB _u(17) +#define M33_DEMCR_MON_PEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_EN +// Description : Enable the DebugMonitor exception +#define M33_DEMCR_MON_EN_RESET _u(0x0) +#define M33_DEMCR_MON_EN_BITS _u(0x00010000) +#define M33_DEMCR_MON_EN_MSB _u(16) +#define M33_DEMCR_MON_EN_LSB _u(16) +#define M33_DEMCR_MON_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_SFERR +// Description : SecureFault exception halting debug vector catch enable +#define M33_DEMCR_VC_SFERR_RESET _u(0x0) +#define M33_DEMCR_VC_SFERR_BITS _u(0x00000800) +#define M33_DEMCR_VC_SFERR_MSB _u(11) +#define M33_DEMCR_VC_SFERR_LSB _u(11) +#define M33_DEMCR_VC_SFERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_HARDERR +// Description : HardFault exception halting debug vector catch enable +#define M33_DEMCR_VC_HARDERR_RESET _u(0x0) +#define M33_DEMCR_VC_HARDERR_BITS _u(0x00000400) +#define M33_DEMCR_VC_HARDERR_MSB _u(10) +#define M33_DEMCR_VC_HARDERR_LSB _u(10) +#define M33_DEMCR_VC_HARDERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_INTERR +// Description : Enable halting debug vector catch for faults during exception +// entry and return +#define M33_DEMCR_VC_INTERR_RESET _u(0x0) +#define M33_DEMCR_VC_INTERR_BITS _u(0x00000200) +#define M33_DEMCR_VC_INTERR_MSB _u(9) +#define M33_DEMCR_VC_INTERR_LSB _u(9) +#define M33_DEMCR_VC_INTERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_BUSERR +// Description : BusFault exception halting debug vector catch enable +#define M33_DEMCR_VC_BUSERR_RESET _u(0x0) +#define M33_DEMCR_VC_BUSERR_BITS _u(0x00000100) +#define M33_DEMCR_VC_BUSERR_MSB _u(8) +#define M33_DEMCR_VC_BUSERR_LSB _u(8) +#define M33_DEMCR_VC_BUSERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_STATERR +// Description : Enable halting debug trap on a UsageFault exception caused by a +// state information error, for example an Undefined Instruction +// exception +#define M33_DEMCR_VC_STATERR_RESET _u(0x0) +#define M33_DEMCR_VC_STATERR_BITS _u(0x00000080) +#define M33_DEMCR_VC_STATERR_MSB _u(7) +#define M33_DEMCR_VC_STATERR_LSB _u(7) +#define M33_DEMCR_VC_STATERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_CHKERR +// Description : Enable halting debug trap on a UsageFault exception caused by a +// checking error, for example an alignment check error +#define M33_DEMCR_VC_CHKERR_RESET _u(0x0) +#define M33_DEMCR_VC_CHKERR_BITS _u(0x00000040) +#define M33_DEMCR_VC_CHKERR_MSB _u(6) +#define M33_DEMCR_VC_CHKERR_LSB _u(6) +#define M33_DEMCR_VC_CHKERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_NOCPERR +// Description : Enable halting debug trap on a UsageFault caused by an access +// to a coprocessor +#define M33_DEMCR_VC_NOCPERR_RESET _u(0x0) +#define M33_DEMCR_VC_NOCPERR_BITS _u(0x00000020) +#define M33_DEMCR_VC_NOCPERR_MSB _u(5) +#define M33_DEMCR_VC_NOCPERR_LSB _u(5) +#define M33_DEMCR_VC_NOCPERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_MMERR +// Description : Enable halting debug trap on a MemManage exception +#define M33_DEMCR_VC_MMERR_RESET _u(0x0) +#define M33_DEMCR_VC_MMERR_BITS _u(0x00000010) +#define M33_DEMCR_VC_MMERR_MSB _u(4) +#define M33_DEMCR_VC_MMERR_LSB _u(4) +#define M33_DEMCR_VC_MMERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_CORERESET +// Description : Enable Reset Vector Catch. This causes a warm reset to halt a +// running system +#define M33_DEMCR_VC_CORERESET_RESET _u(0x0) +#define M33_DEMCR_VC_CORERESET_BITS _u(0x00000001) +#define M33_DEMCR_VC_CORERESET_MSB _u(0) +#define M33_DEMCR_VC_CORERESET_LSB _u(0) +#define M33_DEMCR_VC_CORERESET_ACCESS "RW" +// ============================================================================= +// Register : M33_DSCSR +// Description : Provides control and status information for Secure debug +#define M33_DSCSR_OFFSET _u(0x0000ee08) +#define M33_DSCSR_BITS _u(0x00030003) +#define M33_DSCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_CDSKEY +// Description : Writes to the CDS bit are ignored unless CDSKEY is concurrently +// written to zero +#define M33_DSCSR_CDSKEY_RESET _u(0x0) +#define M33_DSCSR_CDSKEY_BITS _u(0x00020000) +#define M33_DSCSR_CDSKEY_MSB _u(17) +#define M33_DSCSR_CDSKEY_LSB _u(17) +#define M33_DSCSR_CDSKEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_CDS +// Description : This field indicates the current Security state of the +// processor +#define M33_DSCSR_CDS_RESET _u(0x0) +#define M33_DSCSR_CDS_BITS _u(0x00010000) +#define M33_DSCSR_CDS_MSB _u(16) +#define M33_DSCSR_CDS_LSB _u(16) +#define M33_DSCSR_CDS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_SBRSEL +// Description : If SBRSELEN is 1 this bit selects whether the Non-secure or the +// Secure version of the memory-mapped Banked registers are +// accessible to the debugger +#define M33_DSCSR_SBRSEL_RESET _u(0x0) +#define M33_DSCSR_SBRSEL_BITS _u(0x00000002) +#define M33_DSCSR_SBRSEL_MSB _u(1) +#define M33_DSCSR_SBRSEL_LSB _u(1) +#define M33_DSCSR_SBRSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_SBRSELEN +// Description : Controls whether the SBRSEL field or the current Security state +// of the processor selects which version of the memory-mapped +// Banked registers are accessed to the debugger +#define M33_DSCSR_SBRSELEN_RESET _u(0x0) +#define M33_DSCSR_SBRSELEN_BITS _u(0x00000001) +#define M33_DSCSR_SBRSELEN_MSB _u(0) +#define M33_DSCSR_SBRSELEN_LSB _u(0) +#define M33_DSCSR_SBRSELEN_ACCESS "RW" +// ============================================================================= +// Register : M33_STIR +// Description : Provides a mechanism for software to generate an interrupt +#define M33_STIR_OFFSET _u(0x0000ef00) +#define M33_STIR_BITS _u(0x000001ff) +#define M33_STIR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_STIR_INTID +// Description : Indicates the interrupt to be pended. The value written is +// (ExceptionNumber - 16) +#define M33_STIR_INTID_RESET _u(0x000) +#define M33_STIR_INTID_BITS _u(0x000001ff) +#define M33_STIR_INTID_MSB _u(8) +#define M33_STIR_INTID_LSB _u(0) +#define M33_STIR_INTID_ACCESS "RW" +// ============================================================================= +// Register : M33_FPCCR +// Description : Holds control data for the Floating-point extension +#define M33_FPCCR_OFFSET _u(0x0000ef34) +#define M33_FPCCR_BITS _u(0xfc0007ff) +#define M33_FPCCR_RESET _u(0x20000472) +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_ASPEN +// Description : When this bit is set to 1, execution of a floating-point +// instruction sets the CONTROL.FPCA bit to 1 +#define M33_FPCCR_ASPEN_RESET _u(0x0) +#define M33_FPCCR_ASPEN_BITS _u(0x80000000) +#define M33_FPCCR_ASPEN_MSB _u(31) +#define M33_FPCCR_ASPEN_LSB _u(31) +#define M33_FPCCR_ASPEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_LSPEN +// Description : Enables lazy context save of floating-point state +#define M33_FPCCR_LSPEN_RESET _u(0x0) +#define M33_FPCCR_LSPEN_BITS _u(0x40000000) +#define M33_FPCCR_LSPEN_MSB _u(30) +#define M33_FPCCR_LSPEN_LSB _u(30) +#define M33_FPCCR_LSPEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_LSPENS +// Description : This bit controls whether the LSPEN bit is writeable from the +// Non-secure state +#define M33_FPCCR_LSPENS_RESET _u(0x1) +#define M33_FPCCR_LSPENS_BITS _u(0x20000000) +#define M33_FPCCR_LSPENS_MSB _u(29) +#define M33_FPCCR_LSPENS_LSB _u(29) +#define M33_FPCCR_LSPENS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_CLRONRET +// Description : Clear floating-point caller saved registers on exception return +#define M33_FPCCR_CLRONRET_RESET _u(0x0) +#define M33_FPCCR_CLRONRET_BITS _u(0x10000000) +#define M33_FPCCR_CLRONRET_MSB _u(28) +#define M33_FPCCR_CLRONRET_LSB _u(28) +#define M33_FPCCR_CLRONRET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_CLRONRETS +// Description : This bit controls whether the CLRONRET bit is writeable from +// the Non-secure state +#define M33_FPCCR_CLRONRETS_RESET _u(0x0) +#define M33_FPCCR_CLRONRETS_BITS _u(0x08000000) +#define M33_FPCCR_CLRONRETS_MSB _u(27) +#define M33_FPCCR_CLRONRETS_LSB _u(27) +#define M33_FPCCR_CLRONRETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_TS +// Description : Treat floating-point registers as Secure enable +#define M33_FPCCR_TS_RESET _u(0x0) +#define M33_FPCCR_TS_BITS _u(0x04000000) +#define M33_FPCCR_TS_MSB _u(26) +#define M33_FPCCR_TS_LSB _u(26) +#define M33_FPCCR_TS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_UFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the UsageFault +// exception to pending +#define M33_FPCCR_UFRDY_RESET _u(0x1) +#define M33_FPCCR_UFRDY_BITS _u(0x00000400) +#define M33_FPCCR_UFRDY_MSB _u(10) +#define M33_FPCCR_UFRDY_LSB _u(10) +#define M33_FPCCR_UFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_SPLIMVIOL +// Description : This bit is banked between the Security states and indicates +// whether the floating-point context violates the stack pointer +// limit that was active when lazy state preservation was +// activated. SPLIMVIOL modifies the lazy floating-point state +// preservation behavior +#define M33_FPCCR_SPLIMVIOL_RESET _u(0x0) +#define M33_FPCCR_SPLIMVIOL_BITS _u(0x00000200) +#define M33_FPCCR_SPLIMVIOL_MSB _u(9) +#define M33_FPCCR_SPLIMVIOL_LSB _u(9) +#define M33_FPCCR_SPLIMVIOL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_MONRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the DebugMonitor +// exception to pending +#define M33_FPCCR_MONRDY_RESET _u(0x0) +#define M33_FPCCR_MONRDY_BITS _u(0x00000100) +#define M33_FPCCR_MONRDY_MSB _u(8) +#define M33_FPCCR_MONRDY_LSB _u(8) +#define M33_FPCCR_MONRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_SFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the SecureFault +// exception to pending. This bit is only present in the Secure +// version of the register, and behaves as RAZ/WI when accessed +// from the Non-secure state +#define M33_FPCCR_SFRDY_RESET _u(0x0) +#define M33_FPCCR_SFRDY_BITS _u(0x00000080) +#define M33_FPCCR_SFRDY_MSB _u(7) +#define M33_FPCCR_SFRDY_LSB _u(7) +#define M33_FPCCR_SFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_BFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the BusFault +// exception to pending +#define M33_FPCCR_BFRDY_RESET _u(0x1) +#define M33_FPCCR_BFRDY_BITS _u(0x00000040) +#define M33_FPCCR_BFRDY_MSB _u(6) +#define M33_FPCCR_BFRDY_LSB _u(6) +#define M33_FPCCR_BFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_MMRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the MemManage +// exception to pending +#define M33_FPCCR_MMRDY_RESET _u(0x1) +#define M33_FPCCR_MMRDY_BITS _u(0x00000020) +#define M33_FPCCR_MMRDY_MSB _u(5) +#define M33_FPCCR_MMRDY_LSB _u(5) +#define M33_FPCCR_MMRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_HFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the HardFault +// exception to pending +#define M33_FPCCR_HFRDY_RESET _u(0x1) +#define M33_FPCCR_HFRDY_BITS _u(0x00000010) +#define M33_FPCCR_HFRDY_MSB _u(4) +#define M33_FPCCR_HFRDY_LSB _u(4) +#define M33_FPCCR_HFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_THREAD +// Description : Indicates the PE mode when it allocated the floating-point +// stack frame +#define M33_FPCCR_THREAD_RESET _u(0x0) +#define M33_FPCCR_THREAD_BITS _u(0x00000008) +#define M33_FPCCR_THREAD_MSB _u(3) +#define M33_FPCCR_THREAD_LSB _u(3) +#define M33_FPCCR_THREAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_S +// Description : Security status of the floating-point context. This bit is only +// present in the Secure version of the register, and behaves as +// RAZ/WI when accessed from the Non-secure state. This bit is +// updated whenever lazy state preservation is activated, or when +// a floating-point instruction is executed +#define M33_FPCCR_S_RESET _u(0x0) +#define M33_FPCCR_S_BITS _u(0x00000004) +#define M33_FPCCR_S_MSB _u(2) +#define M33_FPCCR_S_LSB _u(2) +#define M33_FPCCR_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_USER +// Description : Indicates the privilege level of the software executing when +// the PE allocated the floating-point stack frame +#define M33_FPCCR_USER_RESET _u(0x1) +#define M33_FPCCR_USER_BITS _u(0x00000002) +#define M33_FPCCR_USER_MSB _u(1) +#define M33_FPCCR_USER_LSB _u(1) +#define M33_FPCCR_USER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_LSPACT +// Description : Indicates whether lazy preservation of the floating-point state +// is active +#define M33_FPCCR_LSPACT_RESET _u(0x0) +#define M33_FPCCR_LSPACT_BITS _u(0x00000001) +#define M33_FPCCR_LSPACT_MSB _u(0) +#define M33_FPCCR_LSPACT_LSB _u(0) +#define M33_FPCCR_LSPACT_ACCESS "RW" +// ============================================================================= +// Register : M33_FPCAR +// Description : Holds the location of the unpopulated floating-point register +// space allocated on an exception stack frame +#define M33_FPCAR_OFFSET _u(0x0000ef38) +#define M33_FPCAR_BITS _u(0xfffffff8) +#define M33_FPCAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FPCAR_ADDRESS +// Description : The location of the unpopulated floating-point register space +// allocated on an exception stack frame +#define M33_FPCAR_ADDRESS_RESET _u(0x00000000) +#define M33_FPCAR_ADDRESS_BITS _u(0xfffffff8) +#define M33_FPCAR_ADDRESS_MSB _u(31) +#define M33_FPCAR_ADDRESS_LSB _u(3) +#define M33_FPCAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_FPDSCR +// Description : Holds the default values for the floating-point status control +// data that the PE assigns to the FPSCR when it creates a new +// floating-point context +#define M33_FPDSCR_OFFSET _u(0x0000ef3c) +#define M33_FPDSCR_BITS _u(0x07c00000) +#define M33_FPDSCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_AHP +// Description : Default value for FPSCR.AHP +#define M33_FPDSCR_AHP_RESET _u(0x0) +#define M33_FPDSCR_AHP_BITS _u(0x04000000) +#define M33_FPDSCR_AHP_MSB _u(26) +#define M33_FPDSCR_AHP_LSB _u(26) +#define M33_FPDSCR_AHP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_DN +// Description : Default value for FPSCR.DN +#define M33_FPDSCR_DN_RESET _u(0x0) +#define M33_FPDSCR_DN_BITS _u(0x02000000) +#define M33_FPDSCR_DN_MSB _u(25) +#define M33_FPDSCR_DN_LSB _u(25) +#define M33_FPDSCR_DN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_FZ +// Description : Default value for FPSCR.FZ +#define M33_FPDSCR_FZ_RESET _u(0x0) +#define M33_FPDSCR_FZ_BITS _u(0x01000000) +#define M33_FPDSCR_FZ_MSB _u(24) +#define M33_FPDSCR_FZ_LSB _u(24) +#define M33_FPDSCR_FZ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_RMODE +// Description : Default value for FPSCR.RMode +#define M33_FPDSCR_RMODE_RESET _u(0x0) +#define M33_FPDSCR_RMODE_BITS _u(0x00c00000) +#define M33_FPDSCR_RMODE_MSB _u(23) +#define M33_FPDSCR_RMODE_LSB _u(22) +#define M33_FPDSCR_RMODE_ACCESS "RW" +// ============================================================================= +// Register : M33_MVFR0 +// Description : Describes the features provided by the Floating-point Extension +#define M33_MVFR0_OFFSET _u(0x0000ef40) +#define M33_MVFR0_BITS _u(0xf0ff0fff) +#define M33_MVFR0_RESET _u(0x60540601) +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPROUND +// Description : Indicates the rounding modes supported by the FP Extension +#define M33_MVFR0_FPROUND_RESET _u(0x6) +#define M33_MVFR0_FPROUND_BITS _u(0xf0000000) +#define M33_MVFR0_FPROUND_MSB _u(31) +#define M33_MVFR0_FPROUND_LSB _u(28) +#define M33_MVFR0_FPROUND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPSQRT +// Description : Indicates the support for FP square root operations +#define M33_MVFR0_FPSQRT_RESET _u(0x5) +#define M33_MVFR0_FPSQRT_BITS _u(0x00f00000) +#define M33_MVFR0_FPSQRT_MSB _u(23) +#define M33_MVFR0_FPSQRT_LSB _u(20) +#define M33_MVFR0_FPSQRT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPDIVIDE +// Description : Indicates the support for FP divide operations +#define M33_MVFR0_FPDIVIDE_RESET _u(0x4) +#define M33_MVFR0_FPDIVIDE_BITS _u(0x000f0000) +#define M33_MVFR0_FPDIVIDE_MSB _u(19) +#define M33_MVFR0_FPDIVIDE_LSB _u(16) +#define M33_MVFR0_FPDIVIDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPDP +// Description : Indicates support for FP double-precision operations +#define M33_MVFR0_FPDP_RESET _u(0x6) +#define M33_MVFR0_FPDP_BITS _u(0x00000f00) +#define M33_MVFR0_FPDP_MSB _u(11) +#define M33_MVFR0_FPDP_LSB _u(8) +#define M33_MVFR0_FPDP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPSP +// Description : Indicates support for FP single-precision operations +#define M33_MVFR0_FPSP_RESET _u(0x0) +#define M33_MVFR0_FPSP_BITS _u(0x000000f0) +#define M33_MVFR0_FPSP_MSB _u(7) +#define M33_MVFR0_FPSP_LSB _u(4) +#define M33_MVFR0_FPSP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_SIMDREG +// Description : Indicates size of FP register file +#define M33_MVFR0_SIMDREG_RESET _u(0x1) +#define M33_MVFR0_SIMDREG_BITS _u(0x0000000f) +#define M33_MVFR0_SIMDREG_MSB _u(3) +#define M33_MVFR0_SIMDREG_LSB _u(0) +#define M33_MVFR0_SIMDREG_ACCESS "RO" +// ============================================================================= +// Register : M33_MVFR1 +// Description : Describes the features provided by the Floating-point Extension +#define M33_MVFR1_OFFSET _u(0x0000ef44) +#define M33_MVFR1_BITS _u(0xff0000ff) +#define M33_MVFR1_RESET _u(0x85000089) +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FMAC +// Description : Indicates whether the FP Extension implements the fused +// multiply accumulate instructions +#define M33_MVFR1_FMAC_RESET _u(0x8) +#define M33_MVFR1_FMAC_BITS _u(0xf0000000) +#define M33_MVFR1_FMAC_MSB _u(31) +#define M33_MVFR1_FMAC_LSB _u(28) +#define M33_MVFR1_FMAC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FPHP +// Description : Indicates whether the FP Extension implements half-precision FP +// conversion instructions +#define M33_MVFR1_FPHP_RESET _u(0x5) +#define M33_MVFR1_FPHP_BITS _u(0x0f000000) +#define M33_MVFR1_FPHP_MSB _u(27) +#define M33_MVFR1_FPHP_LSB _u(24) +#define M33_MVFR1_FPHP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FPDNAN +// Description : Indicates whether the FP hardware implementation supports NaN +// propagation +#define M33_MVFR1_FPDNAN_RESET _u(0x8) +#define M33_MVFR1_FPDNAN_BITS _u(0x000000f0) +#define M33_MVFR1_FPDNAN_MSB _u(7) +#define M33_MVFR1_FPDNAN_LSB _u(4) +#define M33_MVFR1_FPDNAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FPFTZ +// Description : Indicates whether subnormals are always flushed-to-zero +#define M33_MVFR1_FPFTZ_RESET _u(0x9) +#define M33_MVFR1_FPFTZ_BITS _u(0x0000000f) +#define M33_MVFR1_FPFTZ_MSB _u(3) +#define M33_MVFR1_FPFTZ_LSB _u(0) +#define M33_MVFR1_FPFTZ_ACCESS "RO" +// ============================================================================= +// Register : M33_MVFR2 +// Description : Describes the features provided by the Floating-point Extension +#define M33_MVFR2_OFFSET _u(0x0000ef48) +#define M33_MVFR2_BITS _u(0x000000f0) +#define M33_MVFR2_RESET _u(0x00000060) +// ----------------------------------------------------------------------------- +// Field : M33_MVFR2_FPMISC +// Description : Indicates support for miscellaneous FP features +#define M33_MVFR2_FPMISC_RESET _u(0x6) +#define M33_MVFR2_FPMISC_BITS _u(0x000000f0) +#define M33_MVFR2_FPMISC_MSB _u(7) +#define M33_MVFR2_FPMISC_LSB _u(4) +#define M33_MVFR2_FPMISC_ACCESS "RO" +// ============================================================================= +// Register : M33_DDEVARCH +// Description : Provides CoreSight discovery information for the SCS +#define M33_DDEVARCH_OFFSET _u(0x0000efbc) +#define M33_DDEVARCH_BITS _u(0xffffffff) +#define M33_DDEVARCH_RESET _u(0x47702a04) +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_DDEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_DDEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_DDEVARCH_ARCHITECT_MSB _u(31) +#define M33_DDEVARCH_ARCHITECT_LSB _u(21) +#define M33_DDEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_DDEVARCH_PRESENT_RESET _u(0x1) +#define M33_DDEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_DDEVARCH_PRESENT_MSB _u(20) +#define M33_DDEVARCH_PRESENT_LSB _u(20) +#define M33_DDEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_DDEVARCH_REVISION_RESET _u(0x0) +#define M33_DDEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_DDEVARCH_REVISION_MSB _u(19) +#define M33_DDEVARCH_REVISION_LSB _u(16) +#define M33_DDEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_DDEVARCH_ARCHVER_RESET _u(0x2) +#define M33_DDEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_DDEVARCH_ARCHVER_MSB _u(15) +#define M33_DDEVARCH_ARCHVER_LSB _u(12) +#define M33_DDEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_DDEVARCH_ARCHPART_RESET _u(0xa04) +#define M33_DDEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_DDEVARCH_ARCHPART_MSB _u(11) +#define M33_DDEVARCH_ARCHPART_LSB _u(0) +#define M33_DDEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_DDEVTYPE +// Description : Provides CoreSight discovery information for the SCS +#define M33_DDEVTYPE_OFFSET _u(0x0000efcc) +#define M33_DDEVTYPE_BITS _u(0x000000ff) +#define M33_DDEVTYPE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DDEVTYPE_SUB +// Description : Component sub-type +#define M33_DDEVTYPE_SUB_RESET _u(0x0) +#define M33_DDEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_DDEVTYPE_SUB_MSB _u(7) +#define M33_DDEVTYPE_SUB_LSB _u(4) +#define M33_DDEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVTYPE_MAJOR +// Description : CoreSight major type +#define M33_DDEVTYPE_MAJOR_RESET _u(0x0) +#define M33_DDEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_DDEVTYPE_MAJOR_MSB _u(3) +#define M33_DDEVTYPE_MAJOR_LSB _u(0) +#define M33_DDEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR4 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR4_OFFSET _u(0x0000efd0) +#define M33_DPIDR4_BITS _u(0x000000ff) +#define M33_DPIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_DPIDR4_SIZE_RESET _u(0x0) +#define M33_DPIDR4_SIZE_BITS _u(0x000000f0) +#define M33_DPIDR4_SIZE_MSB _u(7) +#define M33_DPIDR4_SIZE_LSB _u(4) +#define M33_DPIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR4_DES_2_RESET _u(0x4) +#define M33_DPIDR4_DES_2_BITS _u(0x0000000f) +#define M33_DPIDR4_DES_2_MSB _u(3) +#define M33_DPIDR4_DES_2_LSB _u(0) +#define M33_DPIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR5 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR5_OFFSET _u(0x0000efd4) +#define M33_DPIDR5_BITS _u(0x00000000) +#define M33_DPIDR5_RESET _u(0x00000000) +#define M33_DPIDR5_MSB _u(31) +#define M33_DPIDR5_LSB _u(0) +#define M33_DPIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_DPIDR6 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR6_OFFSET _u(0x0000efd8) +#define M33_DPIDR6_BITS _u(0x00000000) +#define M33_DPIDR6_RESET _u(0x00000000) +#define M33_DPIDR6_MSB _u(31) +#define M33_DPIDR6_LSB _u(0) +#define M33_DPIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_DPIDR7 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR7_OFFSET _u(0x0000efdc) +#define M33_DPIDR7_BITS _u(0x00000000) +#define M33_DPIDR7_RESET _u(0x00000000) +#define M33_DPIDR7_MSB _u(31) +#define M33_DPIDR7_LSB _u(0) +#define M33_DPIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_DPIDR0 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR0_OFFSET _u(0x0000efe0) +#define M33_DPIDR0_BITS _u(0x000000ff) +#define M33_DPIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR0_PART_0_RESET _u(0x21) +#define M33_DPIDR0_PART_0_BITS _u(0x000000ff) +#define M33_DPIDR0_PART_0_MSB _u(7) +#define M33_DPIDR0_PART_0_LSB _u(0) +#define M33_DPIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR1 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR1_OFFSET _u(0x0000efe4) +#define M33_DPIDR1_BITS _u(0x000000ff) +#define M33_DPIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR1_DES_0_RESET _u(0xb) +#define M33_DPIDR1_DES_0_BITS _u(0x000000f0) +#define M33_DPIDR1_DES_0_MSB _u(7) +#define M33_DPIDR1_DES_0_LSB _u(4) +#define M33_DPIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR1_PART_1_RESET _u(0xd) +#define M33_DPIDR1_PART_1_BITS _u(0x0000000f) +#define M33_DPIDR1_PART_1_MSB _u(3) +#define M33_DPIDR1_PART_1_LSB _u(0) +#define M33_DPIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR2 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR2_OFFSET _u(0x0000efe8) +#define M33_DPIDR2_BITS _u(0x000000ff) +#define M33_DPIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_DPIDR2_REVISION_RESET _u(0x0) +#define M33_DPIDR2_REVISION_BITS _u(0x000000f0) +#define M33_DPIDR2_REVISION_MSB _u(7) +#define M33_DPIDR2_REVISION_LSB _u(4) +#define M33_DPIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_DPIDR2_JEDEC_RESET _u(0x1) +#define M33_DPIDR2_JEDEC_BITS _u(0x00000008) +#define M33_DPIDR2_JEDEC_MSB _u(3) +#define M33_DPIDR2_JEDEC_LSB _u(3) +#define M33_DPIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR2_DES_1_RESET _u(0x3) +#define M33_DPIDR2_DES_1_BITS _u(0x00000007) +#define M33_DPIDR2_DES_1_MSB _u(2) +#define M33_DPIDR2_DES_1_LSB _u(0) +#define M33_DPIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR3 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR3_OFFSET _u(0x0000efec) +#define M33_DPIDR3_BITS _u(0x000000ff) +#define M33_DPIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_DPIDR3_REVAND_RESET _u(0x0) +#define M33_DPIDR3_REVAND_BITS _u(0x000000f0) +#define M33_DPIDR3_REVAND_MSB _u(7) +#define M33_DPIDR3_REVAND_LSB _u(4) +#define M33_DPIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_DPIDR3_CMOD_RESET _u(0x0) +#define M33_DPIDR3_CMOD_BITS _u(0x0000000f) +#define M33_DPIDR3_CMOD_MSB _u(3) +#define M33_DPIDR3_CMOD_LSB _u(0) +#define M33_DPIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR0 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR0_OFFSET _u(0x0000eff0) +#define M33_DCIDR0_BITS _u(0x000000ff) +#define M33_DCIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_DCIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_DCIDR0_PRMBL_0_MSB _u(7) +#define M33_DCIDR0_PRMBL_0_LSB _u(0) +#define M33_DCIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR1 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR1_OFFSET _u(0x0000eff4) +#define M33_DCIDR1_BITS _u(0x000000ff) +#define M33_DCIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_DCIDR1_CLASS_RESET _u(0x9) +#define M33_DCIDR1_CLASS_BITS _u(0x000000f0) +#define M33_DCIDR1_CLASS_MSB _u(7) +#define M33_DCIDR1_CLASS_LSB _u(4) +#define M33_DCIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR1_PRMBL_1_RESET _u(0x0) +#define M33_DCIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_DCIDR1_PRMBL_1_MSB _u(3) +#define M33_DCIDR1_PRMBL_1_LSB _u(0) +#define M33_DCIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR2 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR2_OFFSET _u(0x0000eff8) +#define M33_DCIDR2_BITS _u(0x000000ff) +#define M33_DCIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR2_PRMBL_2_RESET _u(0x05) +#define M33_DCIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_DCIDR2_PRMBL_2_MSB _u(7) +#define M33_DCIDR2_PRMBL_2_LSB _u(0) +#define M33_DCIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR3 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR3_OFFSET _u(0x0000effc) +#define M33_DCIDR3_BITS _u(0x000000ff) +#define M33_DCIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_DCIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_DCIDR3_PRMBL_3_MSB _u(7) +#define M33_DCIDR3_PRMBL_3_LSB _u(0) +#define M33_DCIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPRGCTLR +// Description : Programming Control Register +#define M33_TRCPRGCTLR_OFFSET _u(0x00041004) +#define M33_TRCPRGCTLR_BITS _u(0x00000001) +#define M33_TRCPRGCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPRGCTLR_EN +// Description : Trace Unit Enable +#define M33_TRCPRGCTLR_EN_RESET _u(0x0) +#define M33_TRCPRGCTLR_EN_BITS _u(0x00000001) +#define M33_TRCPRGCTLR_EN_MSB _u(0) +#define M33_TRCPRGCTLR_EN_LSB _u(0) +#define M33_TRCPRGCTLR_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSTATR +// Description : The TRCSTATR indicates the ETM-Teal status +#define M33_TRCSTATR_OFFSET _u(0x0004100c) +#define M33_TRCSTATR_BITS _u(0x00000003) +#define M33_TRCSTATR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTATR_PMSTABLE +// Description : Indicates whether the ETM-Teal registers are stable and can be +// read +#define M33_TRCSTATR_PMSTABLE_RESET _u(0x0) +#define M33_TRCSTATR_PMSTABLE_BITS _u(0x00000002) +#define M33_TRCSTATR_PMSTABLE_MSB _u(1) +#define M33_TRCSTATR_PMSTABLE_LSB _u(1) +#define M33_TRCSTATR_PMSTABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTATR_IDLE +// Description : Indicates that the trace unit is inactive +#define M33_TRCSTATR_IDLE_RESET _u(0x0) +#define M33_TRCSTATR_IDLE_BITS _u(0x00000001) +#define M33_TRCSTATR_IDLE_MSB _u(0) +#define M33_TRCSTATR_IDLE_LSB _u(0) +#define M33_TRCSTATR_IDLE_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCONFIGR +// Description : The TRCCONFIGR sets the basic tracing options for the trace +// unit +#define M33_TRCCONFIGR_OFFSET _u(0x00041010) +#define M33_TRCCONFIGR_BITS _u(0x00001ff8) +#define M33_TRCCONFIGR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_RS +// Description : Return stack enable +#define M33_TRCCONFIGR_RS_RESET _u(0x0) +#define M33_TRCCONFIGR_RS_BITS _u(0x00001000) +#define M33_TRCCONFIGR_RS_MSB _u(12) +#define M33_TRCCONFIGR_RS_LSB _u(12) +#define M33_TRCCONFIGR_RS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_TS +// Description : Global timestamp tracing +#define M33_TRCCONFIGR_TS_RESET _u(0x0) +#define M33_TRCCONFIGR_TS_BITS _u(0x00000800) +#define M33_TRCCONFIGR_TS_MSB _u(11) +#define M33_TRCCONFIGR_TS_LSB _u(11) +#define M33_TRCCONFIGR_TS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_COND +// Description : Conditional instruction tracing +#define M33_TRCCONFIGR_COND_RESET _u(0x00) +#define M33_TRCCONFIGR_COND_BITS _u(0x000007e0) +#define M33_TRCCONFIGR_COND_MSB _u(10) +#define M33_TRCCONFIGR_COND_LSB _u(5) +#define M33_TRCCONFIGR_COND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_CCI +// Description : Cycle counting in instruction trace +#define M33_TRCCONFIGR_CCI_RESET _u(0x0) +#define M33_TRCCONFIGR_CCI_BITS _u(0x00000010) +#define M33_TRCCONFIGR_CCI_MSB _u(4) +#define M33_TRCCONFIGR_CCI_LSB _u(4) +#define M33_TRCCONFIGR_CCI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_BB +// Description : Branch broadcast mode +#define M33_TRCCONFIGR_BB_RESET _u(0x0) +#define M33_TRCCONFIGR_BB_BITS _u(0x00000008) +#define M33_TRCCONFIGR_BB_MSB _u(3) +#define M33_TRCCONFIGR_BB_LSB _u(3) +#define M33_TRCCONFIGR_BB_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCEVENTCTL0R +// Description : The TRCEVENTCTL0R controls the tracing of events in the trace +// stream. The events also drive the ETM-Teal external outputs. +#define M33_TRCEVENTCTL0R_OFFSET _u(0x00041020) +#define M33_TRCEVENTCTL0R_BITS _u(0x00008787) +#define M33_TRCEVENTCTL0R_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_TYPE1 +// Description : Selects the resource type for event 1 +#define M33_TRCEVENTCTL0R_TYPE1_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_TYPE1_BITS _u(0x00008000) +#define M33_TRCEVENTCTL0R_TYPE1_MSB _u(15) +#define M33_TRCEVENTCTL0R_TYPE1_LSB _u(15) +#define M33_TRCEVENTCTL0R_TYPE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_SEL1 +// Description : Selects the resource number, based on the value of TYPE1: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL1[2:0] +#define M33_TRCEVENTCTL0R_SEL1_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_SEL1_BITS _u(0x00000700) +#define M33_TRCEVENTCTL0R_SEL1_MSB _u(10) +#define M33_TRCEVENTCTL0R_SEL1_LSB _u(8) +#define M33_TRCEVENTCTL0R_SEL1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_TYPE0 +// Description : Selects the resource type for event 0 +#define M33_TRCEVENTCTL0R_TYPE0_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_TYPE0_BITS _u(0x00000080) +#define M33_TRCEVENTCTL0R_TYPE0_MSB _u(7) +#define M33_TRCEVENTCTL0R_TYPE0_LSB _u(7) +#define M33_TRCEVENTCTL0R_TYPE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_SEL0 +// Description : Selects the resource number, based on the value of TYPE0: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL0[2:0] +#define M33_TRCEVENTCTL0R_SEL0_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_SEL0_BITS _u(0x00000007) +#define M33_TRCEVENTCTL0R_SEL0_MSB _u(2) +#define M33_TRCEVENTCTL0R_SEL0_LSB _u(0) +#define M33_TRCEVENTCTL0R_SEL0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCEVENTCTL1R +// Description : The TRCEVENTCTL1R controls how the events selected by +// TRCEVENTCTL0R behave +#define M33_TRCEVENTCTL1R_OFFSET _u(0x00041024) +#define M33_TRCEVENTCTL1R_BITS _u(0x00001803) +#define M33_TRCEVENTCTL1R_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_LPOVERRIDE +// Description : Low power state behavior override +#define M33_TRCEVENTCTL1R_LPOVERRIDE_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_BITS _u(0x00001000) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_MSB _u(12) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_LSB _u(12) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_ATB +// Description : ATB enabled +#define M33_TRCEVENTCTL1R_ATB_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_ATB_BITS _u(0x00000800) +#define M33_TRCEVENTCTL1R_ATB_MSB _u(11) +#define M33_TRCEVENTCTL1R_ATB_LSB _u(11) +#define M33_TRCEVENTCTL1R_ATB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_INSTEN1 +// Description : One bit per event, to enable generation of an event element in +// the instruction trace stream when the selected event occurs +#define M33_TRCEVENTCTL1R_INSTEN1_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_INSTEN1_BITS _u(0x00000002) +#define M33_TRCEVENTCTL1R_INSTEN1_MSB _u(1) +#define M33_TRCEVENTCTL1R_INSTEN1_LSB _u(1) +#define M33_TRCEVENTCTL1R_INSTEN1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_INSTEN0 +// Description : One bit per event, to enable generation of an event element in +// the instruction trace stream when the selected event occurs +#define M33_TRCEVENTCTL1R_INSTEN0_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_INSTEN0_BITS _u(0x00000001) +#define M33_TRCEVENTCTL1R_INSTEN0_MSB _u(0) +#define M33_TRCEVENTCTL1R_INSTEN0_LSB _u(0) +#define M33_TRCEVENTCTL1R_INSTEN0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSTALLCTLR +// Description : The TRCSTALLCTLR enables ETM-Teal to stall the processor if the +// ETM-Teal FIFO goes over the programmed level to minimize risk +// of overflow +#define M33_TRCSTALLCTLR_OFFSET _u(0x0004102c) +#define M33_TRCSTALLCTLR_BITS _u(0x0000050c) +#define M33_TRCSTALLCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTALLCTLR_INSTPRIORITY +// Description : Reserved, RES0 +#define M33_TRCSTALLCTLR_INSTPRIORITY_RESET _u(0x0) +#define M33_TRCSTALLCTLR_INSTPRIORITY_BITS _u(0x00000400) +#define M33_TRCSTALLCTLR_INSTPRIORITY_MSB _u(10) +#define M33_TRCSTALLCTLR_INSTPRIORITY_LSB _u(10) +#define M33_TRCSTALLCTLR_INSTPRIORITY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTALLCTLR_ISTALL +// Description : Stall processor based on instruction trace buffer space +#define M33_TRCSTALLCTLR_ISTALL_RESET _u(0x0) +#define M33_TRCSTALLCTLR_ISTALL_BITS _u(0x00000100) +#define M33_TRCSTALLCTLR_ISTALL_MSB _u(8) +#define M33_TRCSTALLCTLR_ISTALL_LSB _u(8) +#define M33_TRCSTALLCTLR_ISTALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTALLCTLR_LEVEL +// Description : Threshold at which stalling becomes active. This provides four +// levels. This level can be varied to optimize the level of +// invasion caused by stalling, balanced against the risk of a +// FIFO overflow +#define M33_TRCSTALLCTLR_LEVEL_RESET _u(0x0) +#define M33_TRCSTALLCTLR_LEVEL_BITS _u(0x0000000c) +#define M33_TRCSTALLCTLR_LEVEL_MSB _u(3) +#define M33_TRCSTALLCTLR_LEVEL_LSB _u(2) +#define M33_TRCSTALLCTLR_LEVEL_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCTSCTLR +// Description : The TRCTSCTLR controls the insertion of global timestamps into +// the trace stream. A timestamp is always inserted into the +// instruction trace stream +#define M33_TRCTSCTLR_OFFSET _u(0x00041030) +#define M33_TRCTSCTLR_BITS _u(0x00000083) +#define M33_TRCTSCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCTSCTLR_TYPE0 +// Description : Selects the resource type for event 0 +#define M33_TRCTSCTLR_TYPE0_RESET _u(0x0) +#define M33_TRCTSCTLR_TYPE0_BITS _u(0x00000080) +#define M33_TRCTSCTLR_TYPE0_MSB _u(7) +#define M33_TRCTSCTLR_TYPE0_LSB _u(7) +#define M33_TRCTSCTLR_TYPE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCTSCTLR_SEL0 +// Description : Selects the resource number, based on the value of TYPE0: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL0[2:0] +#define M33_TRCTSCTLR_SEL0_RESET _u(0x0) +#define M33_TRCTSCTLR_SEL0_BITS _u(0x00000003) +#define M33_TRCTSCTLR_SEL0_MSB _u(1) +#define M33_TRCTSCTLR_SEL0_LSB _u(0) +#define M33_TRCTSCTLR_SEL0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSYNCPR +// Description : The TRCSYNCPR specifies the period of trace synchronization of +// the trace streams. TRCSYNCPR defines a number of bytes of trace +// between requests for trace synchronization. This value is +// always a power of two +#define M33_TRCSYNCPR_OFFSET _u(0x00041034) +#define M33_TRCSYNCPR_BITS _u(0x0000001f) +#define M33_TRCSYNCPR_RESET _u(0x0000000a) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSYNCPR_PERIOD +// Description : Defines the number of bytes of trace between trace +// synchronization requests as a total of the number of bytes +// generated by the instruction stream. The number of bytes is 2N +// where N is the value of this field: - A value of zero disables +// these periodic trace synchronization requests, but does not +// disable other trace synchronization requests. - The minimum +// value that can be programmed, other than zero, is 8, providing +// a minimum trace synchronization period of 256 bytes. - The +// maximum value is 20, providing a maximum trace synchronization +// period of 2^20 bytes +#define M33_TRCSYNCPR_PERIOD_RESET _u(0x0a) +#define M33_TRCSYNCPR_PERIOD_BITS _u(0x0000001f) +#define M33_TRCSYNCPR_PERIOD_MSB _u(4) +#define M33_TRCSYNCPR_PERIOD_LSB _u(0) +#define M33_TRCSYNCPR_PERIOD_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCCCTLR +// Description : The TRCCCCTLR sets the threshold value for instruction trace +// cycle counting. The threshold represents the minimum interval +// between cycle count trace packets +#define M33_TRCCCCTLR_OFFSET _u(0x00041038) +#define M33_TRCCCCTLR_BITS _u(0x00000fff) +#define M33_TRCCCCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCCCTLR_THRESHOLD +// Description : Instruction trace cycle count threshold +#define M33_TRCCCCTLR_THRESHOLD_RESET _u(0x000) +#define M33_TRCCCCTLR_THRESHOLD_BITS _u(0x00000fff) +#define M33_TRCCCCTLR_THRESHOLD_MSB _u(11) +#define M33_TRCCCCTLR_THRESHOLD_LSB _u(0) +#define M33_TRCCCCTLR_THRESHOLD_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCVICTLR +// Description : The TRCVICTLR controls instruction trace filtering +#define M33_TRCVICTLR_OFFSET _u(0x00041080) +#define M33_TRCVICTLR_BITS _u(0x00090e83) +#define M33_TRCVICTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_EXLEVEL_S3 +// Description : In Secure state, each bit controls whether instruction tracing +// is enabled for the corresponding exception level +#define M33_TRCVICTLR_EXLEVEL_S3_RESET _u(0x0) +#define M33_TRCVICTLR_EXLEVEL_S3_BITS _u(0x00080000) +#define M33_TRCVICTLR_EXLEVEL_S3_MSB _u(19) +#define M33_TRCVICTLR_EXLEVEL_S3_LSB _u(19) +#define M33_TRCVICTLR_EXLEVEL_S3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_EXLEVEL_S0 +// Description : In Secure state, each bit controls whether instruction tracing +// is enabled for the corresponding exception level +#define M33_TRCVICTLR_EXLEVEL_S0_RESET _u(0x0) +#define M33_TRCVICTLR_EXLEVEL_S0_BITS _u(0x00010000) +#define M33_TRCVICTLR_EXLEVEL_S0_MSB _u(16) +#define M33_TRCVICTLR_EXLEVEL_S0_LSB _u(16) +#define M33_TRCVICTLR_EXLEVEL_S0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_TRCERR +// Description : Selects whether a system error exception must always be traced +#define M33_TRCVICTLR_TRCERR_RESET _u(0x0) +#define M33_TRCVICTLR_TRCERR_BITS _u(0x00000800) +#define M33_TRCVICTLR_TRCERR_MSB _u(11) +#define M33_TRCVICTLR_TRCERR_LSB _u(11) +#define M33_TRCVICTLR_TRCERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_TRCRESET +// Description : Selects whether a reset exception must always be traced +#define M33_TRCVICTLR_TRCRESET_RESET _u(0x0) +#define M33_TRCVICTLR_TRCRESET_BITS _u(0x00000400) +#define M33_TRCVICTLR_TRCRESET_MSB _u(10) +#define M33_TRCVICTLR_TRCRESET_LSB _u(10) +#define M33_TRCVICTLR_TRCRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_SSSTATUS +// Description : Indicates the current status of the start/stop logic +#define M33_TRCVICTLR_SSSTATUS_RESET _u(0x0) +#define M33_TRCVICTLR_SSSTATUS_BITS _u(0x00000200) +#define M33_TRCVICTLR_SSSTATUS_MSB _u(9) +#define M33_TRCVICTLR_SSSTATUS_LSB _u(9) +#define M33_TRCVICTLR_SSSTATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_TYPE0 +// Description : Selects the resource type for event 0 +#define M33_TRCVICTLR_TYPE0_RESET _u(0x0) +#define M33_TRCVICTLR_TYPE0_BITS _u(0x00000080) +#define M33_TRCVICTLR_TYPE0_MSB _u(7) +#define M33_TRCVICTLR_TYPE0_LSB _u(7) +#define M33_TRCVICTLR_TYPE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_SEL0 +// Description : Selects the resource number, based on the value of TYPE0: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL0[2:0] +#define M33_TRCVICTLR_SEL0_RESET _u(0x0) +#define M33_TRCVICTLR_SEL0_BITS _u(0x00000003) +#define M33_TRCVICTLR_SEL0_MSB _u(1) +#define M33_TRCVICTLR_SEL0_LSB _u(0) +#define M33_TRCVICTLR_SEL0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCCNTRLDVR0 +// Description : The TRCCNTRLDVR defines the reload value for the reduced +// function counter +#define M33_TRCCNTRLDVR0_OFFSET _u(0x00041140) +#define M33_TRCCNTRLDVR0_BITS _u(0x0000ffff) +#define M33_TRCCNTRLDVR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCNTRLDVR0_VALUE +// Description : Defines the reload value for the counter. This value is loaded +// into the counter each time the reload event occurs +#define M33_TRCCNTRLDVR0_VALUE_RESET _u(0x0000) +#define M33_TRCCNTRLDVR0_VALUE_BITS _u(0x0000ffff) +#define M33_TRCCNTRLDVR0_VALUE_MSB _u(15) +#define M33_TRCCNTRLDVR0_VALUE_LSB _u(0) +#define M33_TRCCNTRLDVR0_VALUE_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCIDR8 +// Description : TRCIDR8 +#define M33_TRCIDR8_OFFSET _u(0x00041180) +#define M33_TRCIDR8_BITS _u(0xffffffff) +#define M33_TRCIDR8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR8_MAXSPEC +// Description : reads as `ImpDef +#define M33_TRCIDR8_MAXSPEC_RESET _u(0x00000000) +#define M33_TRCIDR8_MAXSPEC_BITS _u(0xffffffff) +#define M33_TRCIDR8_MAXSPEC_MSB _u(31) +#define M33_TRCIDR8_MAXSPEC_LSB _u(0) +#define M33_TRCIDR8_MAXSPEC_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR9 +// Description : TRCIDR9 +#define M33_TRCIDR9_OFFSET _u(0x00041184) +#define M33_TRCIDR9_BITS _u(0xffffffff) +#define M33_TRCIDR9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR9_NUMP0KEY +// Description : reads as `ImpDef +#define M33_TRCIDR9_NUMP0KEY_RESET _u(0x00000000) +#define M33_TRCIDR9_NUMP0KEY_BITS _u(0xffffffff) +#define M33_TRCIDR9_NUMP0KEY_MSB _u(31) +#define M33_TRCIDR9_NUMP0KEY_LSB _u(0) +#define M33_TRCIDR9_NUMP0KEY_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR10 +// Description : TRCIDR10 +#define M33_TRCIDR10_OFFSET _u(0x00041188) +#define M33_TRCIDR10_BITS _u(0xffffffff) +#define M33_TRCIDR10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR10_NUMP1KEY +// Description : reads as `ImpDef +#define M33_TRCIDR10_NUMP1KEY_RESET _u(0x00000000) +#define M33_TRCIDR10_NUMP1KEY_BITS _u(0xffffffff) +#define M33_TRCIDR10_NUMP1KEY_MSB _u(31) +#define M33_TRCIDR10_NUMP1KEY_LSB _u(0) +#define M33_TRCIDR10_NUMP1KEY_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR11 +// Description : TRCIDR11 +#define M33_TRCIDR11_OFFSET _u(0x0004118c) +#define M33_TRCIDR11_BITS _u(0xffffffff) +#define M33_TRCIDR11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR11_NUMP1SPC +// Description : reads as `ImpDef +#define M33_TRCIDR11_NUMP1SPC_RESET _u(0x00000000) +#define M33_TRCIDR11_NUMP1SPC_BITS _u(0xffffffff) +#define M33_TRCIDR11_NUMP1SPC_MSB _u(31) +#define M33_TRCIDR11_NUMP1SPC_LSB _u(0) +#define M33_TRCIDR11_NUMP1SPC_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR12 +// Description : TRCIDR12 +#define M33_TRCIDR12_OFFSET _u(0x00041190) +#define M33_TRCIDR12_BITS _u(0xffffffff) +#define M33_TRCIDR12_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR12_NUMCONDKEY +// Description : reads as `ImpDef +#define M33_TRCIDR12_NUMCONDKEY_RESET _u(0x00000001) +#define M33_TRCIDR12_NUMCONDKEY_BITS _u(0xffffffff) +#define M33_TRCIDR12_NUMCONDKEY_MSB _u(31) +#define M33_TRCIDR12_NUMCONDKEY_LSB _u(0) +#define M33_TRCIDR12_NUMCONDKEY_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR13 +// Description : TRCIDR13 +#define M33_TRCIDR13_OFFSET _u(0x00041194) +#define M33_TRCIDR13_BITS _u(0xffffffff) +#define M33_TRCIDR13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR13_NUMCONDSPC +// Description : reads as `ImpDef +#define M33_TRCIDR13_NUMCONDSPC_RESET _u(0x00000000) +#define M33_TRCIDR13_NUMCONDSPC_BITS _u(0xffffffff) +#define M33_TRCIDR13_NUMCONDSPC_MSB _u(31) +#define M33_TRCIDR13_NUMCONDSPC_LSB _u(0) +#define M33_TRCIDR13_NUMCONDSPC_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIMSPEC +// Description : The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC +// features, and enables any features that are provided +#define M33_TRCIMSPEC_OFFSET _u(0x000411c0) +#define M33_TRCIMSPEC_BITS _u(0x0000000f) +#define M33_TRCIMSPEC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIMSPEC_SUPPORT +// Description : Reserved, RES0 +#define M33_TRCIMSPEC_SUPPORT_RESET _u(0x0) +#define M33_TRCIMSPEC_SUPPORT_BITS _u(0x0000000f) +#define M33_TRCIMSPEC_SUPPORT_MSB _u(3) +#define M33_TRCIMSPEC_SUPPORT_LSB _u(0) +#define M33_TRCIMSPEC_SUPPORT_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR0 +// Description : TRCIDR0 +#define M33_TRCIDR0_OFFSET _u(0x000411e0) +#define M33_TRCIDR0_BITS _u(0x3f03feff) +#define M33_TRCIDR0_RESET _u(0x280006e1) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_COMMOPT +// Description : reads as `ImpDef +#define M33_TRCIDR0_COMMOPT_RESET _u(0x1) +#define M33_TRCIDR0_COMMOPT_BITS _u(0x20000000) +#define M33_TRCIDR0_COMMOPT_MSB _u(29) +#define M33_TRCIDR0_COMMOPT_LSB _u(29) +#define M33_TRCIDR0_COMMOPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TSSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR0_TSSIZE_RESET _u(0x08) +#define M33_TRCIDR0_TSSIZE_BITS _u(0x1f000000) +#define M33_TRCIDR0_TSSIZE_MSB _u(28) +#define M33_TRCIDR0_TSSIZE_LSB _u(24) +#define M33_TRCIDR0_TSSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCEXDATA +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCEXDATA_RESET _u(0x0) +#define M33_TRCIDR0_TRCEXDATA_BITS _u(0x00020000) +#define M33_TRCIDR0_TRCEXDATA_MSB _u(17) +#define M33_TRCIDR0_TRCEXDATA_LSB _u(17) +#define M33_TRCIDR0_TRCEXDATA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_QSUPP +// Description : reads as `ImpDef +#define M33_TRCIDR0_QSUPP_RESET _u(0x0) +#define M33_TRCIDR0_QSUPP_BITS _u(0x00018000) +#define M33_TRCIDR0_QSUPP_MSB _u(16) +#define M33_TRCIDR0_QSUPP_LSB _u(15) +#define M33_TRCIDR0_QSUPP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_QFILT +// Description : reads as `ImpDef +#define M33_TRCIDR0_QFILT_RESET _u(0x0) +#define M33_TRCIDR0_QFILT_BITS _u(0x00004000) +#define M33_TRCIDR0_QFILT_MSB _u(14) +#define M33_TRCIDR0_QFILT_LSB _u(14) +#define M33_TRCIDR0_QFILT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_CONDTYPE +// Description : reads as `ImpDef +#define M33_TRCIDR0_CONDTYPE_RESET _u(0x0) +#define M33_TRCIDR0_CONDTYPE_BITS _u(0x00003000) +#define M33_TRCIDR0_CONDTYPE_MSB _u(13) +#define M33_TRCIDR0_CONDTYPE_LSB _u(12) +#define M33_TRCIDR0_CONDTYPE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_NUMEVENT +// Description : reads as `ImpDef +#define M33_TRCIDR0_NUMEVENT_RESET _u(0x1) +#define M33_TRCIDR0_NUMEVENT_BITS _u(0x00000c00) +#define M33_TRCIDR0_NUMEVENT_MSB _u(11) +#define M33_TRCIDR0_NUMEVENT_LSB _u(10) +#define M33_TRCIDR0_NUMEVENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_RETSTACK +// Description : reads as `ImpDef +#define M33_TRCIDR0_RETSTACK_RESET _u(0x1) +#define M33_TRCIDR0_RETSTACK_BITS _u(0x00000200) +#define M33_TRCIDR0_RETSTACK_MSB _u(9) +#define M33_TRCIDR0_RETSTACK_LSB _u(9) +#define M33_TRCIDR0_RETSTACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCCCI +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCCCI_RESET _u(0x1) +#define M33_TRCIDR0_TRCCCI_BITS _u(0x00000080) +#define M33_TRCIDR0_TRCCCI_MSB _u(7) +#define M33_TRCIDR0_TRCCCI_LSB _u(7) +#define M33_TRCIDR0_TRCCCI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCCOND +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCCOND_RESET _u(0x1) +#define M33_TRCIDR0_TRCCOND_BITS _u(0x00000040) +#define M33_TRCIDR0_TRCCOND_MSB _u(6) +#define M33_TRCIDR0_TRCCOND_LSB _u(6) +#define M33_TRCIDR0_TRCCOND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCBB +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCBB_RESET _u(0x1) +#define M33_TRCIDR0_TRCBB_BITS _u(0x00000020) +#define M33_TRCIDR0_TRCBB_MSB _u(5) +#define M33_TRCIDR0_TRCBB_LSB _u(5) +#define M33_TRCIDR0_TRCBB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCDATA +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCDATA_RESET _u(0x0) +#define M33_TRCIDR0_TRCDATA_BITS _u(0x00000018) +#define M33_TRCIDR0_TRCDATA_MSB _u(4) +#define M33_TRCIDR0_TRCDATA_LSB _u(3) +#define M33_TRCIDR0_TRCDATA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_INSTP0 +// Description : reads as `ImpDef +#define M33_TRCIDR0_INSTP0_RESET _u(0x0) +#define M33_TRCIDR0_INSTP0_BITS _u(0x00000006) +#define M33_TRCIDR0_INSTP0_MSB _u(2) +#define M33_TRCIDR0_INSTP0_LSB _u(1) +#define M33_TRCIDR0_INSTP0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_RES1 +// Description : Reserved, RES1 +#define M33_TRCIDR0_RES1_RESET _u(0x1) +#define M33_TRCIDR0_RES1_BITS _u(0x00000001) +#define M33_TRCIDR0_RES1_MSB _u(0) +#define M33_TRCIDR0_RES1_LSB _u(0) +#define M33_TRCIDR0_RES1_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR1 +// Description : TRCIDR1 +#define M33_TRCIDR1_OFFSET _u(0x000411e4) +#define M33_TRCIDR1_BITS _u(0xff00ffff) +#define M33_TRCIDR1_RESET _u(0x4100f421) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_DESIGNER +// Description : reads as `ImpDef +#define M33_TRCIDR1_DESIGNER_RESET _u(0x41) +#define M33_TRCIDR1_DESIGNER_BITS _u(0xff000000) +#define M33_TRCIDR1_DESIGNER_MSB _u(31) +#define M33_TRCIDR1_DESIGNER_LSB _u(24) +#define M33_TRCIDR1_DESIGNER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_RES1 +// Description : Reserved, RES1 +#define M33_TRCIDR1_RES1_RESET _u(0xf) +#define M33_TRCIDR1_RES1_BITS _u(0x0000f000) +#define M33_TRCIDR1_RES1_MSB _u(15) +#define M33_TRCIDR1_RES1_LSB _u(12) +#define M33_TRCIDR1_RES1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_TRCARCHMAJ +// Description : reads as 0b0100 +#define M33_TRCIDR1_TRCARCHMAJ_RESET _u(0x4) +#define M33_TRCIDR1_TRCARCHMAJ_BITS _u(0x00000f00) +#define M33_TRCIDR1_TRCARCHMAJ_MSB _u(11) +#define M33_TRCIDR1_TRCARCHMAJ_LSB _u(8) +#define M33_TRCIDR1_TRCARCHMAJ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_TRCARCHMIN +// Description : reads as 0b0000 +#define M33_TRCIDR1_TRCARCHMIN_RESET _u(0x2) +#define M33_TRCIDR1_TRCARCHMIN_BITS _u(0x000000f0) +#define M33_TRCIDR1_TRCARCHMIN_MSB _u(7) +#define M33_TRCIDR1_TRCARCHMIN_LSB _u(4) +#define M33_TRCIDR1_TRCARCHMIN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_REVISION +// Description : reads as `ImpDef +#define M33_TRCIDR1_REVISION_RESET _u(0x1) +#define M33_TRCIDR1_REVISION_BITS _u(0x0000000f) +#define M33_TRCIDR1_REVISION_MSB _u(3) +#define M33_TRCIDR1_REVISION_LSB _u(0) +#define M33_TRCIDR1_REVISION_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR2 +// Description : TRCIDR2 +#define M33_TRCIDR2_OFFSET _u(0x000411e8) +#define M33_TRCIDR2_BITS _u(0x1fffffff) +#define M33_TRCIDR2_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_CCSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_CCSIZE_RESET _u(0x0) +#define M33_TRCIDR2_CCSIZE_BITS _u(0x1e000000) +#define M33_TRCIDR2_CCSIZE_MSB _u(28) +#define M33_TRCIDR2_CCSIZE_LSB _u(25) +#define M33_TRCIDR2_CCSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_DVSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_DVSIZE_RESET _u(0x00) +#define M33_TRCIDR2_DVSIZE_BITS _u(0x01f00000) +#define M33_TRCIDR2_DVSIZE_MSB _u(24) +#define M33_TRCIDR2_DVSIZE_LSB _u(20) +#define M33_TRCIDR2_DVSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_DASIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_DASIZE_RESET _u(0x00) +#define M33_TRCIDR2_DASIZE_BITS _u(0x000f8000) +#define M33_TRCIDR2_DASIZE_MSB _u(19) +#define M33_TRCIDR2_DASIZE_LSB _u(15) +#define M33_TRCIDR2_DASIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_VMIDSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_VMIDSIZE_RESET _u(0x00) +#define M33_TRCIDR2_VMIDSIZE_BITS _u(0x00007c00) +#define M33_TRCIDR2_VMIDSIZE_MSB _u(14) +#define M33_TRCIDR2_VMIDSIZE_LSB _u(10) +#define M33_TRCIDR2_VMIDSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_CIDSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_CIDSIZE_RESET _u(0x00) +#define M33_TRCIDR2_CIDSIZE_BITS _u(0x000003e0) +#define M33_TRCIDR2_CIDSIZE_MSB _u(9) +#define M33_TRCIDR2_CIDSIZE_LSB _u(5) +#define M33_TRCIDR2_CIDSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_IASIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_IASIZE_RESET _u(0x04) +#define M33_TRCIDR2_IASIZE_BITS _u(0x0000001f) +#define M33_TRCIDR2_IASIZE_MSB _u(4) +#define M33_TRCIDR2_IASIZE_LSB _u(0) +#define M33_TRCIDR2_IASIZE_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR3 +// Description : TRCIDR3 +#define M33_TRCIDR3_OFFSET _u(0x000411ec) +#define M33_TRCIDR3_BITS _u(0xffff0fff) +#define M33_TRCIDR3_RESET _u(0x0f090004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_NOOVERFLOW +// Description : reads as `ImpDef +#define M33_TRCIDR3_NOOVERFLOW_RESET _u(0x0) +#define M33_TRCIDR3_NOOVERFLOW_BITS _u(0x80000000) +#define M33_TRCIDR3_NOOVERFLOW_MSB _u(31) +#define M33_TRCIDR3_NOOVERFLOW_LSB _u(31) +#define M33_TRCIDR3_NOOVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_NUMPROC +// Description : reads as `ImpDef +#define M33_TRCIDR3_NUMPROC_RESET _u(0x0) +#define M33_TRCIDR3_NUMPROC_BITS _u(0x70000000) +#define M33_TRCIDR3_NUMPROC_MSB _u(30) +#define M33_TRCIDR3_NUMPROC_LSB _u(28) +#define M33_TRCIDR3_NUMPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_SYSSTALL +// Description : reads as `ImpDef +#define M33_TRCIDR3_SYSSTALL_RESET _u(0x1) +#define M33_TRCIDR3_SYSSTALL_BITS _u(0x08000000) +#define M33_TRCIDR3_SYSSTALL_MSB _u(27) +#define M33_TRCIDR3_SYSSTALL_LSB _u(27) +#define M33_TRCIDR3_SYSSTALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_STALLCTL +// Description : reads as `ImpDef +#define M33_TRCIDR3_STALLCTL_RESET _u(0x1) +#define M33_TRCIDR3_STALLCTL_BITS _u(0x04000000) +#define M33_TRCIDR3_STALLCTL_MSB _u(26) +#define M33_TRCIDR3_STALLCTL_LSB _u(26) +#define M33_TRCIDR3_STALLCTL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_SYNCPR +// Description : reads as `ImpDef +#define M33_TRCIDR3_SYNCPR_RESET _u(0x1) +#define M33_TRCIDR3_SYNCPR_BITS _u(0x02000000) +#define M33_TRCIDR3_SYNCPR_MSB _u(25) +#define M33_TRCIDR3_SYNCPR_LSB _u(25) +#define M33_TRCIDR3_SYNCPR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_TRCERR +// Description : reads as `ImpDef +#define M33_TRCIDR3_TRCERR_RESET _u(0x1) +#define M33_TRCIDR3_TRCERR_BITS _u(0x01000000) +#define M33_TRCIDR3_TRCERR_MSB _u(24) +#define M33_TRCIDR3_TRCERR_LSB _u(24) +#define M33_TRCIDR3_TRCERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_EXLEVEL_NS +// Description : reads as `ImpDef +#define M33_TRCIDR3_EXLEVEL_NS_RESET _u(0x0) +#define M33_TRCIDR3_EXLEVEL_NS_BITS _u(0x00f00000) +#define M33_TRCIDR3_EXLEVEL_NS_MSB _u(23) +#define M33_TRCIDR3_EXLEVEL_NS_LSB _u(20) +#define M33_TRCIDR3_EXLEVEL_NS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_EXLEVEL_S +// Description : reads as `ImpDef +#define M33_TRCIDR3_EXLEVEL_S_RESET _u(0x9) +#define M33_TRCIDR3_EXLEVEL_S_BITS _u(0x000f0000) +#define M33_TRCIDR3_EXLEVEL_S_MSB _u(19) +#define M33_TRCIDR3_EXLEVEL_S_LSB _u(16) +#define M33_TRCIDR3_EXLEVEL_S_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_CCITMIN +// Description : reads as `ImpDef +#define M33_TRCIDR3_CCITMIN_RESET _u(0x004) +#define M33_TRCIDR3_CCITMIN_BITS _u(0x00000fff) +#define M33_TRCIDR3_CCITMIN_MSB _u(11) +#define M33_TRCIDR3_CCITMIN_LSB _u(0) +#define M33_TRCIDR3_CCITMIN_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR4 +// Description : TRCIDR4 +#define M33_TRCIDR4_OFFSET _u(0x000411f0) +#define M33_TRCIDR4_BITS _u(0xfffff1ff) +#define M33_TRCIDR4_RESET _u(0x00114000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMVMIDC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMVMIDC_RESET _u(0x0) +#define M33_TRCIDR4_NUMVMIDC_BITS _u(0xf0000000) +#define M33_TRCIDR4_NUMVMIDC_MSB _u(31) +#define M33_TRCIDR4_NUMVMIDC_LSB _u(28) +#define M33_TRCIDR4_NUMVMIDC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMCIDC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMCIDC_RESET _u(0x0) +#define M33_TRCIDR4_NUMCIDC_BITS _u(0x0f000000) +#define M33_TRCIDR4_NUMCIDC_MSB _u(27) +#define M33_TRCIDR4_NUMCIDC_LSB _u(24) +#define M33_TRCIDR4_NUMCIDC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMSSCC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMSSCC_RESET _u(0x1) +#define M33_TRCIDR4_NUMSSCC_BITS _u(0x00f00000) +#define M33_TRCIDR4_NUMSSCC_MSB _u(23) +#define M33_TRCIDR4_NUMSSCC_LSB _u(20) +#define M33_TRCIDR4_NUMSSCC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMRSPAIR +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMRSPAIR_RESET _u(0x1) +#define M33_TRCIDR4_NUMRSPAIR_BITS _u(0x000f0000) +#define M33_TRCIDR4_NUMRSPAIR_MSB _u(19) +#define M33_TRCIDR4_NUMRSPAIR_LSB _u(16) +#define M33_TRCIDR4_NUMRSPAIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMPC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMPC_RESET _u(0x4) +#define M33_TRCIDR4_NUMPC_BITS _u(0x0000f000) +#define M33_TRCIDR4_NUMPC_MSB _u(15) +#define M33_TRCIDR4_NUMPC_LSB _u(12) +#define M33_TRCIDR4_NUMPC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_SUPPDAC +// Description : reads as `ImpDef +#define M33_TRCIDR4_SUPPDAC_RESET _u(0x0) +#define M33_TRCIDR4_SUPPDAC_BITS _u(0x00000100) +#define M33_TRCIDR4_SUPPDAC_MSB _u(8) +#define M33_TRCIDR4_SUPPDAC_LSB _u(8) +#define M33_TRCIDR4_SUPPDAC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMDVC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMDVC_RESET _u(0x0) +#define M33_TRCIDR4_NUMDVC_BITS _u(0x000000f0) +#define M33_TRCIDR4_NUMDVC_MSB _u(7) +#define M33_TRCIDR4_NUMDVC_LSB _u(4) +#define M33_TRCIDR4_NUMDVC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMACPAIRS +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMACPAIRS_RESET _u(0x0) +#define M33_TRCIDR4_NUMACPAIRS_BITS _u(0x0000000f) +#define M33_TRCIDR4_NUMACPAIRS_MSB _u(3) +#define M33_TRCIDR4_NUMACPAIRS_LSB _u(0) +#define M33_TRCIDR4_NUMACPAIRS_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR5 +// Description : TRCIDR5 +#define M33_TRCIDR5_OFFSET _u(0x000411f4) +#define M33_TRCIDR5_BITS _u(0xfeff0fff) +#define M33_TRCIDR5_RESET _u(0x90c70004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_REDFUNCNTR +// Description : reads as `ImpDef +#define M33_TRCIDR5_REDFUNCNTR_RESET _u(0x1) +#define M33_TRCIDR5_REDFUNCNTR_BITS _u(0x80000000) +#define M33_TRCIDR5_REDFUNCNTR_MSB _u(31) +#define M33_TRCIDR5_REDFUNCNTR_LSB _u(31) +#define M33_TRCIDR5_REDFUNCNTR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMCNTR +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMCNTR_RESET _u(0x1) +#define M33_TRCIDR5_NUMCNTR_BITS _u(0x70000000) +#define M33_TRCIDR5_NUMCNTR_MSB _u(30) +#define M33_TRCIDR5_NUMCNTR_LSB _u(28) +#define M33_TRCIDR5_NUMCNTR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMSEQSTATE +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMSEQSTATE_RESET _u(0x0) +#define M33_TRCIDR5_NUMSEQSTATE_BITS _u(0x0e000000) +#define M33_TRCIDR5_NUMSEQSTATE_MSB _u(27) +#define M33_TRCIDR5_NUMSEQSTATE_LSB _u(25) +#define M33_TRCIDR5_NUMSEQSTATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_LPOVERRIDE +// Description : reads as `ImpDef +#define M33_TRCIDR5_LPOVERRIDE_RESET _u(0x1) +#define M33_TRCIDR5_LPOVERRIDE_BITS _u(0x00800000) +#define M33_TRCIDR5_LPOVERRIDE_MSB _u(23) +#define M33_TRCIDR5_LPOVERRIDE_LSB _u(23) +#define M33_TRCIDR5_LPOVERRIDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_ATBTRIG +// Description : reads as `ImpDef +#define M33_TRCIDR5_ATBTRIG_RESET _u(0x1) +#define M33_TRCIDR5_ATBTRIG_BITS _u(0x00400000) +#define M33_TRCIDR5_ATBTRIG_MSB _u(22) +#define M33_TRCIDR5_ATBTRIG_LSB _u(22) +#define M33_TRCIDR5_ATBTRIG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_TRACEIDSIZE +// Description : reads as 0x07 +#define M33_TRCIDR5_TRACEIDSIZE_RESET _u(0x07) +#define M33_TRCIDR5_TRACEIDSIZE_BITS _u(0x003f0000) +#define M33_TRCIDR5_TRACEIDSIZE_MSB _u(21) +#define M33_TRCIDR5_TRACEIDSIZE_LSB _u(16) +#define M33_TRCIDR5_TRACEIDSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMEXTINSEL +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMEXTINSEL_RESET _u(0x0) +#define M33_TRCIDR5_NUMEXTINSEL_BITS _u(0x00000e00) +#define M33_TRCIDR5_NUMEXTINSEL_MSB _u(11) +#define M33_TRCIDR5_NUMEXTINSEL_LSB _u(9) +#define M33_TRCIDR5_NUMEXTINSEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMEXTIN +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMEXTIN_RESET _u(0x004) +#define M33_TRCIDR5_NUMEXTIN_BITS _u(0x000001ff) +#define M33_TRCIDR5_NUMEXTIN_MSB _u(8) +#define M33_TRCIDR5_NUMEXTIN_LSB _u(0) +#define M33_TRCIDR5_NUMEXTIN_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR6 +// Description : TRCIDR6 +#define M33_TRCIDR6_OFFSET _u(0x000411f8) +#define M33_TRCIDR6_BITS _u(0x00000000) +#define M33_TRCIDR6_RESET _u(0x00000000) +#define M33_TRCIDR6_MSB _u(31) +#define M33_TRCIDR6_LSB _u(0) +#define M33_TRCIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCIDR7 +// Description : TRCIDR7 +#define M33_TRCIDR7_OFFSET _u(0x000411fc) +#define M33_TRCIDR7_BITS _u(0x00000000) +#define M33_TRCIDR7_RESET _u(0x00000000) +#define M33_TRCIDR7_MSB _u(31) +#define M33_TRCIDR7_LSB _u(0) +#define M33_TRCIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCRSCTLR2 +// Description : The TRCRSCTLR controls the trace resources +#define M33_TRCRSCTLR2_OFFSET _u(0x00041208) +#define M33_TRCRSCTLR2_BITS _u(0x003700ff) +#define M33_TRCRSCTLR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_PAIRINV +// Description : Inverts the result of a combined pair of resources. This bit +// is only implemented on the lower register for a pair of +// resource selectors +#define M33_TRCRSCTLR2_PAIRINV_RESET _u(0x0) +#define M33_TRCRSCTLR2_PAIRINV_BITS _u(0x00200000) +#define M33_TRCRSCTLR2_PAIRINV_MSB _u(21) +#define M33_TRCRSCTLR2_PAIRINV_LSB _u(21) +#define M33_TRCRSCTLR2_PAIRINV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_INV +// Description : Inverts the selected resources +#define M33_TRCRSCTLR2_INV_RESET _u(0x0) +#define M33_TRCRSCTLR2_INV_BITS _u(0x00100000) +#define M33_TRCRSCTLR2_INV_MSB _u(20) +#define M33_TRCRSCTLR2_INV_LSB _u(20) +#define M33_TRCRSCTLR2_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_GROUP +// Description : Selects a group of resource +#define M33_TRCRSCTLR2_GROUP_RESET _u(0x0) +#define M33_TRCRSCTLR2_GROUP_BITS _u(0x00070000) +#define M33_TRCRSCTLR2_GROUP_MSB _u(18) +#define M33_TRCRSCTLR2_GROUP_LSB _u(16) +#define M33_TRCRSCTLR2_GROUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_SELECT +// Description : Selects one or more resources from the wanted group. One bit is +// provided per resource from the group +#define M33_TRCRSCTLR2_SELECT_RESET _u(0x00) +#define M33_TRCRSCTLR2_SELECT_BITS _u(0x000000ff) +#define M33_TRCRSCTLR2_SELECT_MSB _u(7) +#define M33_TRCRSCTLR2_SELECT_LSB _u(0) +#define M33_TRCRSCTLR2_SELECT_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCRSCTLR3 +// Description : The TRCRSCTLR controls the trace resources +#define M33_TRCRSCTLR3_OFFSET _u(0x0004120c) +#define M33_TRCRSCTLR3_BITS _u(0x003700ff) +#define M33_TRCRSCTLR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_PAIRINV +// Description : Inverts the result of a combined pair of resources. This bit +// is only implemented on the lower register for a pair of +// resource selectors +#define M33_TRCRSCTLR3_PAIRINV_RESET _u(0x0) +#define M33_TRCRSCTLR3_PAIRINV_BITS _u(0x00200000) +#define M33_TRCRSCTLR3_PAIRINV_MSB _u(21) +#define M33_TRCRSCTLR3_PAIRINV_LSB _u(21) +#define M33_TRCRSCTLR3_PAIRINV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_INV +// Description : Inverts the selected resources +#define M33_TRCRSCTLR3_INV_RESET _u(0x0) +#define M33_TRCRSCTLR3_INV_BITS _u(0x00100000) +#define M33_TRCRSCTLR3_INV_MSB _u(20) +#define M33_TRCRSCTLR3_INV_LSB _u(20) +#define M33_TRCRSCTLR3_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_GROUP +// Description : Selects a group of resource +#define M33_TRCRSCTLR3_GROUP_RESET _u(0x0) +#define M33_TRCRSCTLR3_GROUP_BITS _u(0x00070000) +#define M33_TRCRSCTLR3_GROUP_MSB _u(18) +#define M33_TRCRSCTLR3_GROUP_LSB _u(16) +#define M33_TRCRSCTLR3_GROUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_SELECT +// Description : Selects one or more resources from the wanted group. One bit is +// provided per resource from the group +#define M33_TRCRSCTLR3_SELECT_RESET _u(0x00) +#define M33_TRCRSCTLR3_SELECT_BITS _u(0x000000ff) +#define M33_TRCRSCTLR3_SELECT_MSB _u(7) +#define M33_TRCRSCTLR3_SELECT_LSB _u(0) +#define M33_TRCRSCTLR3_SELECT_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSSCSR +// Description : Controls the corresponding single-shot comparator resource +#define M33_TRCSSCSR_OFFSET _u(0x000412a0) +#define M33_TRCSSCSR_BITS _u(0x8000000f) +#define M33_TRCSSCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_STATUS +// Description : Single-shot status bit. Indicates if any of the comparators, +// that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched +#define M33_TRCSSCSR_STATUS_RESET _u(0x0) +#define M33_TRCSSCSR_STATUS_BITS _u(0x80000000) +#define M33_TRCSSCSR_STATUS_MSB _u(31) +#define M33_TRCSSCSR_STATUS_LSB _u(31) +#define M33_TRCSSCSR_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_PC +// Description : Reserved, RES1 +#define M33_TRCSSCSR_PC_RESET _u(0x0) +#define M33_TRCSSCSR_PC_BITS _u(0x00000008) +#define M33_TRCSSCSR_PC_MSB _u(3) +#define M33_TRCSSCSR_PC_LSB _u(3) +#define M33_TRCSSCSR_PC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_DV +// Description : Reserved, RES0 +#define M33_TRCSSCSR_DV_RESET _u(0x0) +#define M33_TRCSSCSR_DV_BITS _u(0x00000004) +#define M33_TRCSSCSR_DV_MSB _u(2) +#define M33_TRCSSCSR_DV_LSB _u(2) +#define M33_TRCSSCSR_DV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_DA +// Description : Reserved, RES0 +#define M33_TRCSSCSR_DA_RESET _u(0x0) +#define M33_TRCSSCSR_DA_BITS _u(0x00000002) +#define M33_TRCSSCSR_DA_MSB _u(1) +#define M33_TRCSSCSR_DA_LSB _u(1) +#define M33_TRCSSCSR_DA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_INST +// Description : Reserved, RES0 +#define M33_TRCSSCSR_INST_RESET _u(0x0) +#define M33_TRCSSCSR_INST_BITS _u(0x00000001) +#define M33_TRCSSCSR_INST_MSB _u(0) +#define M33_TRCSSCSR_INST_LSB _u(0) +#define M33_TRCSSCSR_INST_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCSSPCICR +// Description : Selects the PE comparator inputs for Single-shot control +#define M33_TRCSSPCICR_OFFSET _u(0x000412c0) +#define M33_TRCSSPCICR_BITS _u(0x0000000f) +#define M33_TRCSSPCICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSPCICR_PC +// Description : Selects one or more PE comparator inputs for Single-shot +// control. TRCIDR4.NUMPC defines the size of the PC field. 1 +// bit is provided for each implemented PE comparator input. For +// example, if bit[1] == 1 this selects PE comparator input 1 for +// Single-shot control +#define M33_TRCSSPCICR_PC_RESET _u(0x0) +#define M33_TRCSSPCICR_PC_BITS _u(0x0000000f) +#define M33_TRCSSPCICR_PC_MSB _u(3) +#define M33_TRCSSPCICR_PC_LSB _u(0) +#define M33_TRCSSPCICR_PC_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPDCR +// Description : Requests the system to provide power to the trace unit +#define M33_TRCPDCR_OFFSET _u(0x00041310) +#define M33_TRCPDCR_BITS _u(0x00000008) +#define M33_TRCPDCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDCR_PU +// Description : Powerup request bit: +#define M33_TRCPDCR_PU_RESET _u(0x0) +#define M33_TRCPDCR_PU_BITS _u(0x00000008) +#define M33_TRCPDCR_PU_MSB _u(3) +#define M33_TRCPDCR_PU_LSB _u(3) +#define M33_TRCPDCR_PU_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPDSR +// Description : Returns the following information about the trace unit: - OS +// Lock status. - Core power domain status. - Power interruption +// status +#define M33_TRCPDSR_OFFSET _u(0x00041314) +#define M33_TRCPDSR_BITS _u(0x00000023) +#define M33_TRCPDSR_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDSR_OSLK +// Description : OS Lock status bit: +#define M33_TRCPDSR_OSLK_RESET _u(0x0) +#define M33_TRCPDSR_OSLK_BITS _u(0x00000020) +#define M33_TRCPDSR_OSLK_MSB _u(5) +#define M33_TRCPDSR_OSLK_LSB _u(5) +#define M33_TRCPDSR_OSLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDSR_STICKYPD +// Description : Sticky powerdown status bit. Indicates whether the trace +// register state is valid: +#define M33_TRCPDSR_STICKYPD_RESET _u(0x1) +#define M33_TRCPDSR_STICKYPD_BITS _u(0x00000002) +#define M33_TRCPDSR_STICKYPD_MSB _u(1) +#define M33_TRCPDSR_STICKYPD_LSB _u(1) +#define M33_TRCPDSR_STICKYPD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDSR_POWER +// Description : Power status bit: +#define M33_TRCPDSR_POWER_RESET _u(0x1) +#define M33_TRCPDSR_POWER_BITS _u(0x00000001) +#define M33_TRCPDSR_POWER_MSB _u(0) +#define M33_TRCPDSR_POWER_LSB _u(0) +#define M33_TRCPDSR_POWER_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCITATBIDR +// Description : Trace Integration ATB Identification Register +#define M33_TRCITATBIDR_OFFSET _u(0x00041ee4) +#define M33_TRCITATBIDR_BITS _u(0x0000007f) +#define M33_TRCITATBIDR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCITATBIDR_ID +// Description : Trace ID +#define M33_TRCITATBIDR_ID_RESET _u(0x00) +#define M33_TRCITATBIDR_ID_BITS _u(0x0000007f) +#define M33_TRCITATBIDR_ID_MSB _u(6) +#define M33_TRCITATBIDR_ID_LSB _u(0) +#define M33_TRCITATBIDR_ID_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCITIATBINR +// Description : Trace Integration Instruction ATB In Register +#define M33_TRCITIATBINR_OFFSET _u(0x00041ef4) +#define M33_TRCITIATBINR_BITS _u(0x00000003) +#define M33_TRCITIATBINR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBINR_AFVALIDM +// Description : Integration Mode instruction AFVALIDM in +#define M33_TRCITIATBINR_AFVALIDM_RESET _u(0x0) +#define M33_TRCITIATBINR_AFVALIDM_BITS _u(0x00000002) +#define M33_TRCITIATBINR_AFVALIDM_MSB _u(1) +#define M33_TRCITIATBINR_AFVALIDM_LSB _u(1) +#define M33_TRCITIATBINR_AFVALIDM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBINR_ATREADYM +// Description : Integration Mode instruction ATREADYM in +#define M33_TRCITIATBINR_ATREADYM_RESET _u(0x0) +#define M33_TRCITIATBINR_ATREADYM_BITS _u(0x00000001) +#define M33_TRCITIATBINR_ATREADYM_MSB _u(0) +#define M33_TRCITIATBINR_ATREADYM_LSB _u(0) +#define M33_TRCITIATBINR_ATREADYM_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCITIATBOUTR +// Description : Trace Integration Instruction ATB Out Register +#define M33_TRCITIATBOUTR_OFFSET _u(0x00041efc) +#define M33_TRCITIATBOUTR_BITS _u(0x00000003) +#define M33_TRCITIATBOUTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBOUTR_AFREADY +// Description : Integration Mode instruction AFREADY out +#define M33_TRCITIATBOUTR_AFREADY_RESET _u(0x0) +#define M33_TRCITIATBOUTR_AFREADY_BITS _u(0x00000002) +#define M33_TRCITIATBOUTR_AFREADY_MSB _u(1) +#define M33_TRCITIATBOUTR_AFREADY_LSB _u(1) +#define M33_TRCITIATBOUTR_AFREADY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBOUTR_ATVALID +// Description : Integration Mode instruction ATVALID out +#define M33_TRCITIATBOUTR_ATVALID_RESET _u(0x0) +#define M33_TRCITIATBOUTR_ATVALID_BITS _u(0x00000001) +#define M33_TRCITIATBOUTR_ATVALID_MSB _u(0) +#define M33_TRCITIATBOUTR_ATVALID_LSB _u(0) +#define M33_TRCITIATBOUTR_ATVALID_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCCLAIMSET +// Description : Claim Tag Set Register +#define M33_TRCCLAIMSET_OFFSET _u(0x00041fa0) +#define M33_TRCCLAIMSET_BITS _u(0x0000000f) +#define M33_TRCCLAIMSET_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET3 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET3_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET3_BITS _u(0x00000008) +#define M33_TRCCLAIMSET_SET3_MSB _u(3) +#define M33_TRCCLAIMSET_SET3_LSB _u(3) +#define M33_TRCCLAIMSET_SET3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET2 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET2_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET2_BITS _u(0x00000004) +#define M33_TRCCLAIMSET_SET2_MSB _u(2) +#define M33_TRCCLAIMSET_SET2_LSB _u(2) +#define M33_TRCCLAIMSET_SET2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET1 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET1_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET1_BITS _u(0x00000002) +#define M33_TRCCLAIMSET_SET1_MSB _u(1) +#define M33_TRCCLAIMSET_SET1_LSB _u(1) +#define M33_TRCCLAIMSET_SET1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET0 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET0_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET0_BITS _u(0x00000001) +#define M33_TRCCLAIMSET_SET0_MSB _u(0) +#define M33_TRCCLAIMSET_SET0_LSB _u(0) +#define M33_TRCCLAIMSET_SET0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCCLAIMCLR +// Description : Claim Tag Clear Register +#define M33_TRCCLAIMCLR_OFFSET _u(0x00041fa4) +#define M33_TRCCLAIMCLR_BITS _u(0x0000000f) +#define M33_TRCCLAIMCLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR3 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR3_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR3_BITS _u(0x00000008) +#define M33_TRCCLAIMCLR_CLR3_MSB _u(3) +#define M33_TRCCLAIMCLR_CLR3_LSB _u(3) +#define M33_TRCCLAIMCLR_CLR3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR2 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR2_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR2_BITS _u(0x00000004) +#define M33_TRCCLAIMCLR_CLR2_MSB _u(2) +#define M33_TRCCLAIMCLR_CLR2_LSB _u(2) +#define M33_TRCCLAIMCLR_CLR2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR1 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR1_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR1_BITS _u(0x00000002) +#define M33_TRCCLAIMCLR_CLR1_MSB _u(1) +#define M33_TRCCLAIMCLR_CLR1_LSB _u(1) +#define M33_TRCCLAIMCLR_CLR1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR0 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR0_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR0_BITS _u(0x00000001) +#define M33_TRCCLAIMCLR_CLR0_MSB _u(0) +#define M33_TRCCLAIMCLR_CLR0_LSB _u(0) +#define M33_TRCCLAIMCLR_CLR0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCAUTHSTATUS +// Description : Returns the level of tracing that the trace unit can support +#define M33_TRCAUTHSTATUS_OFFSET _u(0x00041fb8) +#define M33_TRCAUTHSTATUS_BITS _u(0x000000ff) +#define M33_TRCAUTHSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_SNID +// Description : Indicates whether the system enables the trace unit to support +// Secure non-invasive debug: +#define M33_TRCAUTHSTATUS_SNID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_SNID_BITS _u(0x000000c0) +#define M33_TRCAUTHSTATUS_SNID_MSB _u(7) +#define M33_TRCAUTHSTATUS_SNID_LSB _u(6) +#define M33_TRCAUTHSTATUS_SNID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_SID +// Description : Indicates whether the trace unit supports Secure invasive +// debug: +#define M33_TRCAUTHSTATUS_SID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_SID_BITS _u(0x00000030) +#define M33_TRCAUTHSTATUS_SID_MSB _u(5) +#define M33_TRCAUTHSTATUS_SID_LSB _u(4) +#define M33_TRCAUTHSTATUS_SID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_NSNID +// Description : Indicates whether the system enables the trace unit to support +// Non-secure non-invasive debug: +#define M33_TRCAUTHSTATUS_NSNID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_NSNID_BITS _u(0x0000000c) +#define M33_TRCAUTHSTATUS_NSNID_MSB _u(3) +#define M33_TRCAUTHSTATUS_NSNID_LSB _u(2) +#define M33_TRCAUTHSTATUS_NSNID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_NSID +// Description : Indicates whether the trace unit supports Non-secure invasive +// debug: +#define M33_TRCAUTHSTATUS_NSID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_NSID_BITS _u(0x00000003) +#define M33_TRCAUTHSTATUS_NSID_MSB _u(1) +#define M33_TRCAUTHSTATUS_NSID_LSB _u(0) +#define M33_TRCAUTHSTATUS_NSID_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCDEVARCH +// Description : TRCDEVARCH +#define M33_TRCDEVARCH_OFFSET _u(0x00041fbc) +#define M33_TRCDEVARCH_BITS _u(0xffffffff) +#define M33_TRCDEVARCH_RESET _u(0x47724a13) +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_ARCHITECT +// Description : reads as 0b01000111011 +#define M33_TRCDEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_TRCDEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_TRCDEVARCH_ARCHITECT_MSB _u(31) +#define M33_TRCDEVARCH_ARCHITECT_LSB _u(21) +#define M33_TRCDEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_PRESENT +// Description : reads as 0b1 +#define M33_TRCDEVARCH_PRESENT_RESET _u(0x1) +#define M33_TRCDEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_TRCDEVARCH_PRESENT_MSB _u(20) +#define M33_TRCDEVARCH_PRESENT_LSB _u(20) +#define M33_TRCDEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_REVISION +// Description : reads as 0b0000 +#define M33_TRCDEVARCH_REVISION_RESET _u(0x2) +#define M33_TRCDEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_TRCDEVARCH_REVISION_MSB _u(19) +#define M33_TRCDEVARCH_REVISION_LSB _u(16) +#define M33_TRCDEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_ARCHID +// Description : reads as 0b0100101000010011 +#define M33_TRCDEVARCH_ARCHID_RESET _u(0x4a13) +#define M33_TRCDEVARCH_ARCHID_BITS _u(0x0000ffff) +#define M33_TRCDEVARCH_ARCHID_MSB _u(15) +#define M33_TRCDEVARCH_ARCHID_LSB _u(0) +#define M33_TRCDEVARCH_ARCHID_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCDEVID +// Description : TRCDEVID +#define M33_TRCDEVID_OFFSET _u(0x00041fc8) +#define M33_TRCDEVID_BITS _u(0x00000000) +#define M33_TRCDEVID_RESET _u(0x00000000) +#define M33_TRCDEVID_MSB _u(31) +#define M33_TRCDEVID_LSB _u(0) +#define M33_TRCDEVID_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCDEVTYPE +// Description : TRCDEVTYPE +#define M33_TRCDEVTYPE_OFFSET _u(0x00041fcc) +#define M33_TRCDEVTYPE_BITS _u(0x000000ff) +#define M33_TRCDEVTYPE_RESET _u(0x00000013) +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVTYPE_SUB +// Description : reads as 0b0001 +#define M33_TRCDEVTYPE_SUB_RESET _u(0x1) +#define M33_TRCDEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_TRCDEVTYPE_SUB_MSB _u(7) +#define M33_TRCDEVTYPE_SUB_LSB _u(4) +#define M33_TRCDEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVTYPE_MAJOR +// Description : reads as 0b0011 +#define M33_TRCDEVTYPE_MAJOR_RESET _u(0x3) +#define M33_TRCDEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_TRCDEVTYPE_MAJOR_MSB _u(3) +#define M33_TRCDEVTYPE_MAJOR_LSB _u(0) +#define M33_TRCDEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR4 +// Description : TRCPIDR4 +#define M33_TRCPIDR4_OFFSET _u(0x00041fd0) +#define M33_TRCPIDR4_BITS _u(0x000000ff) +#define M33_TRCPIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR4_SIZE +// Description : reads as `ImpDef +#define M33_TRCPIDR4_SIZE_RESET _u(0x0) +#define M33_TRCPIDR4_SIZE_BITS _u(0x000000f0) +#define M33_TRCPIDR4_SIZE_MSB _u(7) +#define M33_TRCPIDR4_SIZE_LSB _u(4) +#define M33_TRCPIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR4_DES_2 +// Description : reads as `ImpDef +#define M33_TRCPIDR4_DES_2_RESET _u(0x4) +#define M33_TRCPIDR4_DES_2_BITS _u(0x0000000f) +#define M33_TRCPIDR4_DES_2_MSB _u(3) +#define M33_TRCPIDR4_DES_2_LSB _u(0) +#define M33_TRCPIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR5 +// Description : TRCPIDR5 +#define M33_TRCPIDR5_OFFSET _u(0x00041fd4) +#define M33_TRCPIDR5_BITS _u(0x00000000) +#define M33_TRCPIDR5_RESET _u(0x00000000) +#define M33_TRCPIDR5_MSB _u(31) +#define M33_TRCPIDR5_LSB _u(0) +#define M33_TRCPIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPIDR6 +// Description : TRCPIDR6 +#define M33_TRCPIDR6_OFFSET _u(0x00041fd8) +#define M33_TRCPIDR6_BITS _u(0x00000000) +#define M33_TRCPIDR6_RESET _u(0x00000000) +#define M33_TRCPIDR6_MSB _u(31) +#define M33_TRCPIDR6_LSB _u(0) +#define M33_TRCPIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPIDR7 +// Description : TRCPIDR7 +#define M33_TRCPIDR7_OFFSET _u(0x00041fdc) +#define M33_TRCPIDR7_BITS _u(0x00000000) +#define M33_TRCPIDR7_RESET _u(0x00000000) +#define M33_TRCPIDR7_MSB _u(31) +#define M33_TRCPIDR7_LSB _u(0) +#define M33_TRCPIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPIDR0 +// Description : TRCPIDR0 +#define M33_TRCPIDR0_OFFSET _u(0x00041fe0) +#define M33_TRCPIDR0_BITS _u(0x000000ff) +#define M33_TRCPIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR0_PART_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR0_PART_0_RESET _u(0x21) +#define M33_TRCPIDR0_PART_0_BITS _u(0x000000ff) +#define M33_TRCPIDR0_PART_0_MSB _u(7) +#define M33_TRCPIDR0_PART_0_LSB _u(0) +#define M33_TRCPIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR1 +// Description : TRCPIDR1 +#define M33_TRCPIDR1_OFFSET _u(0x00041fe4) +#define M33_TRCPIDR1_BITS _u(0x000000ff) +#define M33_TRCPIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR1_DES_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR1_DES_0_RESET _u(0xb) +#define M33_TRCPIDR1_DES_0_BITS _u(0x000000f0) +#define M33_TRCPIDR1_DES_0_MSB _u(7) +#define M33_TRCPIDR1_DES_0_LSB _u(4) +#define M33_TRCPIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR1_PART_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR1_PART_0_RESET _u(0xd) +#define M33_TRCPIDR1_PART_0_BITS _u(0x0000000f) +#define M33_TRCPIDR1_PART_0_MSB _u(3) +#define M33_TRCPIDR1_PART_0_LSB _u(0) +#define M33_TRCPIDR1_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR2 +// Description : TRCPIDR2 +#define M33_TRCPIDR2_OFFSET _u(0x00041fe8) +#define M33_TRCPIDR2_BITS _u(0x000000ff) +#define M33_TRCPIDR2_RESET _u(0x0000002b) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR2_REVISION +// Description : reads as `ImpDef +#define M33_TRCPIDR2_REVISION_RESET _u(0x2) +#define M33_TRCPIDR2_REVISION_BITS _u(0x000000f0) +#define M33_TRCPIDR2_REVISION_MSB _u(7) +#define M33_TRCPIDR2_REVISION_LSB _u(4) +#define M33_TRCPIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR2_JEDEC +// Description : reads as 0b1 +#define M33_TRCPIDR2_JEDEC_RESET _u(0x1) +#define M33_TRCPIDR2_JEDEC_BITS _u(0x00000008) +#define M33_TRCPIDR2_JEDEC_MSB _u(3) +#define M33_TRCPIDR2_JEDEC_LSB _u(3) +#define M33_TRCPIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR2_DES_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR2_DES_0_RESET _u(0x3) +#define M33_TRCPIDR2_DES_0_BITS _u(0x00000007) +#define M33_TRCPIDR2_DES_0_MSB _u(2) +#define M33_TRCPIDR2_DES_0_LSB _u(0) +#define M33_TRCPIDR2_DES_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR3 +// Description : TRCPIDR3 +#define M33_TRCPIDR3_OFFSET _u(0x00041fec) +#define M33_TRCPIDR3_BITS _u(0x000000ff) +#define M33_TRCPIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR3_REVAND +// Description : reads as `ImpDef +#define M33_TRCPIDR3_REVAND_RESET _u(0x0) +#define M33_TRCPIDR3_REVAND_BITS _u(0x000000f0) +#define M33_TRCPIDR3_REVAND_MSB _u(7) +#define M33_TRCPIDR3_REVAND_LSB _u(4) +#define M33_TRCPIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR3_CMOD +// Description : reads as `ImpDef +#define M33_TRCPIDR3_CMOD_RESET _u(0x0) +#define M33_TRCPIDR3_CMOD_BITS _u(0x0000000f) +#define M33_TRCPIDR3_CMOD_MSB _u(3) +#define M33_TRCPIDR3_CMOD_LSB _u(0) +#define M33_TRCPIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR0 +// Description : TRCCIDR0 +#define M33_TRCCIDR0_OFFSET _u(0x00041ff0) +#define M33_TRCCIDR0_BITS _u(0x000000ff) +#define M33_TRCCIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR0_PRMBL_0 +// Description : reads as 0b00001101 +#define M33_TRCCIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_TRCCIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_TRCCIDR0_PRMBL_0_MSB _u(7) +#define M33_TRCCIDR0_PRMBL_0_LSB _u(0) +#define M33_TRCCIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR1 +// Description : TRCCIDR1 +#define M33_TRCCIDR1_OFFSET _u(0x00041ff4) +#define M33_TRCCIDR1_BITS _u(0x000000ff) +#define M33_TRCCIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR1_CLASS +// Description : reads as 0b1001 +#define M33_TRCCIDR1_CLASS_RESET _u(0x9) +#define M33_TRCCIDR1_CLASS_BITS _u(0x000000f0) +#define M33_TRCCIDR1_CLASS_MSB _u(7) +#define M33_TRCCIDR1_CLASS_LSB _u(4) +#define M33_TRCCIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR1_PRMBL_1 +// Description : reads as 0b0000 +#define M33_TRCCIDR1_PRMBL_1_RESET _u(0x0) +#define M33_TRCCIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_TRCCIDR1_PRMBL_1_MSB _u(3) +#define M33_TRCCIDR1_PRMBL_1_LSB _u(0) +#define M33_TRCCIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR2 +// Description : TRCCIDR2 +#define M33_TRCCIDR2_OFFSET _u(0x00041ff8) +#define M33_TRCCIDR2_BITS _u(0x000000ff) +#define M33_TRCCIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR2_PRMBL_2 +// Description : reads as 0b00000101 +#define M33_TRCCIDR2_PRMBL_2_RESET _u(0x05) +#define M33_TRCCIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_TRCCIDR2_PRMBL_2_MSB _u(7) +#define M33_TRCCIDR2_PRMBL_2_LSB _u(0) +#define M33_TRCCIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR3 +// Description : TRCCIDR3 +#define M33_TRCCIDR3_OFFSET _u(0x00041ffc) +#define M33_TRCCIDR3_BITS _u(0x000000ff) +#define M33_TRCCIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR3_PRMBL_3 +// Description : reads as 0b10110001 +#define M33_TRCCIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_TRCCIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_TRCCIDR3_PRMBL_3_MSB _u(7) +#define M33_TRCCIDR3_PRMBL_3_LSB _u(0) +#define M33_TRCCIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_CTICONTROL +// Description : CTI Control Register +#define M33_CTICONTROL_OFFSET _u(0x00042000) +#define M33_CTICONTROL_BITS _u(0x00000001) +#define M33_CTICONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTICONTROL_GLBEN +// Description : Enables or disables the CTI +#define M33_CTICONTROL_GLBEN_RESET _u(0x0) +#define M33_CTICONTROL_GLBEN_BITS _u(0x00000001) +#define M33_CTICONTROL_GLBEN_MSB _u(0) +#define M33_CTICONTROL_GLBEN_LSB _u(0) +#define M33_CTICONTROL_GLBEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINTACK +// Description : CTI Interrupt Acknowledge Register +#define M33_CTIINTACK_OFFSET _u(0x00042010) +#define M33_CTIINTACK_BITS _u(0x000000ff) +#define M33_CTIINTACK_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINTACK_INTACK +// Description : Acknowledges the corresponding ctitrigout output. There is one +// bit of the register for each ctitrigout output. When a 1 is +// written to a bit in this register, the corresponding ctitrigout +// is acknowledged, causing it to be cleared. +#define M33_CTIINTACK_INTACK_RESET _u(0x00) +#define M33_CTIINTACK_INTACK_BITS _u(0x000000ff) +#define M33_CTIINTACK_INTACK_MSB _u(7) +#define M33_CTIINTACK_INTACK_LSB _u(0) +#define M33_CTIINTACK_INTACK_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIAPPSET +// Description : CTI Application Trigger Set Register +#define M33_CTIAPPSET_OFFSET _u(0x00042014) +#define M33_CTIAPPSET_BITS _u(0x0000000f) +#define M33_CTIAPPSET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIAPPSET_APPSET +// Description : Setting a bit HIGH generates a channel event for the selected +// channel. There is one bit of the register for each channel +#define M33_CTIAPPSET_APPSET_RESET _u(0x0) +#define M33_CTIAPPSET_APPSET_BITS _u(0x0000000f) +#define M33_CTIAPPSET_APPSET_MSB _u(3) +#define M33_CTIAPPSET_APPSET_LSB _u(0) +#define M33_CTIAPPSET_APPSET_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIAPPCLEAR +// Description : CTI Application Trigger Clear Register +#define M33_CTIAPPCLEAR_OFFSET _u(0x00042018) +#define M33_CTIAPPCLEAR_BITS _u(0x0000000f) +#define M33_CTIAPPCLEAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIAPPCLEAR_APPCLEAR +// Description : Sets the corresponding bits in the CTIAPPSET to 0. There is one +// bit of the register for each channel. +#define M33_CTIAPPCLEAR_APPCLEAR_RESET _u(0x0) +#define M33_CTIAPPCLEAR_APPCLEAR_BITS _u(0x0000000f) +#define M33_CTIAPPCLEAR_APPCLEAR_MSB _u(3) +#define M33_CTIAPPCLEAR_APPCLEAR_LSB _u(0) +#define M33_CTIAPPCLEAR_APPCLEAR_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIAPPPULSE +// Description : CTI Application Pulse Register +#define M33_CTIAPPPULSE_OFFSET _u(0x0004201c) +#define M33_CTIAPPPULSE_BITS _u(0x0000000f) +#define M33_CTIAPPPULSE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIAPPPULSE_APPULSE +// Description : Setting a bit HIGH generates a channel event pulse for the +// selected channel. There is one bit of the register for each +// channel. +#define M33_CTIAPPPULSE_APPULSE_RESET _u(0x0) +#define M33_CTIAPPPULSE_APPULSE_BITS _u(0x0000000f) +#define M33_CTIAPPPULSE_APPULSE_MSB _u(3) +#define M33_CTIAPPPULSE_APPULSE_LSB _u(0) +#define M33_CTIAPPPULSE_APPULSE_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN0 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN0_OFFSET _u(0x00042020) +#define M33_CTIINEN0_BITS _u(0x0000000f) +#define M33_CTIINEN0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN0_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN0_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN0_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN0_TRIGINEN_MSB _u(3) +#define M33_CTIINEN0_TRIGINEN_LSB _u(0) +#define M33_CTIINEN0_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN1 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN1_OFFSET _u(0x00042024) +#define M33_CTIINEN1_BITS _u(0x0000000f) +#define M33_CTIINEN1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN1_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN1_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN1_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN1_TRIGINEN_MSB _u(3) +#define M33_CTIINEN1_TRIGINEN_LSB _u(0) +#define M33_CTIINEN1_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN2 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN2_OFFSET _u(0x00042028) +#define M33_CTIINEN2_BITS _u(0x0000000f) +#define M33_CTIINEN2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN2_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN2_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN2_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN2_TRIGINEN_MSB _u(3) +#define M33_CTIINEN2_TRIGINEN_LSB _u(0) +#define M33_CTIINEN2_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN3 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN3_OFFSET _u(0x0004202c) +#define M33_CTIINEN3_BITS _u(0x0000000f) +#define M33_CTIINEN3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN3_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN3_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN3_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN3_TRIGINEN_MSB _u(3) +#define M33_CTIINEN3_TRIGINEN_LSB _u(0) +#define M33_CTIINEN3_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN4 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN4_OFFSET _u(0x00042030) +#define M33_CTIINEN4_BITS _u(0x0000000f) +#define M33_CTIINEN4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN4_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN4_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN4_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN4_TRIGINEN_MSB _u(3) +#define M33_CTIINEN4_TRIGINEN_LSB _u(0) +#define M33_CTIINEN4_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN5 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN5_OFFSET _u(0x00042034) +#define M33_CTIINEN5_BITS _u(0x0000000f) +#define M33_CTIINEN5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN5_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN5_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN5_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN5_TRIGINEN_MSB _u(3) +#define M33_CTIINEN5_TRIGINEN_LSB _u(0) +#define M33_CTIINEN5_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN6 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN6_OFFSET _u(0x00042038) +#define M33_CTIINEN6_BITS _u(0x0000000f) +#define M33_CTIINEN6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN6_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN6_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN6_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN6_TRIGINEN_MSB _u(3) +#define M33_CTIINEN6_TRIGINEN_LSB _u(0) +#define M33_CTIINEN6_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN7 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN7_OFFSET _u(0x0004203c) +#define M33_CTIINEN7_BITS _u(0x0000000f) +#define M33_CTIINEN7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN7_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN7_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN7_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN7_TRIGINEN_MSB _u(3) +#define M33_CTIINEN7_TRIGINEN_LSB _u(0) +#define M33_CTIINEN7_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN0 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN0_OFFSET _u(0x000420a0) +#define M33_CTIOUTEN0_BITS _u(0x0000000f) +#define M33_CTIOUTEN0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN0_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN0_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN0_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN0_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN0_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN0_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN1 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN1_OFFSET _u(0x000420a4) +#define M33_CTIOUTEN1_BITS _u(0x0000000f) +#define M33_CTIOUTEN1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN1_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN1_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN1_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN1_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN1_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN1_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN2 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN2_OFFSET _u(0x000420a8) +#define M33_CTIOUTEN2_BITS _u(0x0000000f) +#define M33_CTIOUTEN2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN2_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN2_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN2_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN2_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN2_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN2_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN3 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN3_OFFSET _u(0x000420ac) +#define M33_CTIOUTEN3_BITS _u(0x0000000f) +#define M33_CTIOUTEN3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN3_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN3_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN3_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN3_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN3_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN3_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN4 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN4_OFFSET _u(0x000420b0) +#define M33_CTIOUTEN4_BITS _u(0x0000000f) +#define M33_CTIOUTEN4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN4_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN4_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN4_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN4_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN4_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN4_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN5 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN5_OFFSET _u(0x000420b4) +#define M33_CTIOUTEN5_BITS _u(0x0000000f) +#define M33_CTIOUTEN5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN5_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN5_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN5_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN5_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN5_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN5_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN6 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN6_OFFSET _u(0x000420b8) +#define M33_CTIOUTEN6_BITS _u(0x0000000f) +#define M33_CTIOUTEN6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN6_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN6_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN6_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN6_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN6_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN6_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN7 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN7_OFFSET _u(0x000420bc) +#define M33_CTIOUTEN7_BITS _u(0x0000000f) +#define M33_CTIOUTEN7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN7_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN7_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN7_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN7_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN7_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN7_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTITRIGINSTATUS +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTITRIGINSTATUS_OFFSET _u(0x00042130) +#define M33_CTITRIGINSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGINSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTITRIGINSTATUS_TRIGINSTATUS +// Description : Shows the status of the ctitrigin inputs. There is one bit of +// the field for each trigger input.Because the register provides +// a view of the raw ctitrigin inputs, the reset value is UNKNOWN. +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_RESET _u(0x00) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_MSB _u(7) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_LSB _u(0) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_ACCESS "RO" +// ============================================================================= +// Register : M33_CTITRIGOUTSTATUS +// Description : CTI Trigger In Status Register +#define M33_CTITRIGOUTSTATUS_OFFSET _u(0x00042134) +#define M33_CTITRIGOUTSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGOUTSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS +// Description : Shows the status of the ctitrigout outputs. There is one bit of +// the field for each trigger output. +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_RESET _u(0x00) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_MSB _u(7) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_LSB _u(0) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_ACCESS "RO" +// ============================================================================= +// Register : M33_CTICHINSTATUS +// Description : CTI Channel In Status Register +#define M33_CTICHINSTATUS_OFFSET _u(0x00042138) +#define M33_CTICHINSTATUS_BITS _u(0x0000000f) +#define M33_CTICHINSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTICHINSTATUS_CTICHOUTSTATUS +// Description : Shows the status of the ctichout outputs. There is one bit of +// the field for each channel output +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_RESET _u(0x0) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_BITS _u(0x0000000f) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_MSB _u(3) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_LSB _u(0) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_ACCESS "RO" +// ============================================================================= +// Register : M33_CTIGATE +// Description : Enable CTI Channel Gate register +#define M33_CTIGATE_OFFSET _u(0x00042140) +#define M33_CTIGATE_BITS _u(0x0000000f) +#define M33_CTIGATE_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN3 +// Description : Enable ctichout3. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN3_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN3_BITS _u(0x00000008) +#define M33_CTIGATE_CTIGATEEN3_MSB _u(3) +#define M33_CTIGATE_CTIGATEEN3_LSB _u(3) +#define M33_CTIGATE_CTIGATEEN3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN2 +// Description : Enable ctichout2. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN2_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN2_BITS _u(0x00000004) +#define M33_CTIGATE_CTIGATEEN2_MSB _u(2) +#define M33_CTIGATE_CTIGATEEN2_LSB _u(2) +#define M33_CTIGATE_CTIGATEEN2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN1 +// Description : Enable ctichout1. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN1_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN1_BITS _u(0x00000002) +#define M33_CTIGATE_CTIGATEEN1_MSB _u(1) +#define M33_CTIGATE_CTIGATEEN1_LSB _u(1) +#define M33_CTIGATE_CTIGATEEN1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN0 +// Description : Enable ctichout0. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN0_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN0_BITS _u(0x00000001) +#define M33_CTIGATE_CTIGATEEN0_MSB _u(0) +#define M33_CTIGATE_CTIGATEEN0_LSB _u(0) +#define M33_CTIGATE_CTIGATEEN0_ACCESS "RW" +// ============================================================================= +// Register : M33_ASICCTL +// Description : External Multiplexer Control register +#define M33_ASICCTL_OFFSET _u(0x00042144) +#define M33_ASICCTL_BITS _u(0x00000000) +#define M33_ASICCTL_RESET _u(0x00000000) +#define M33_ASICCTL_MSB _u(31) +#define M33_ASICCTL_LSB _u(0) +#define M33_ASICCTL_ACCESS "RW" +// ============================================================================= +// Register : M33_ITCHOUT +// Description : Integration Test Channel Output register +#define M33_ITCHOUT_OFFSET _u(0x00042ee4) +#define M33_ITCHOUT_BITS _u(0x0000000f) +#define M33_ITCHOUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITCHOUT_CTCHOUT +// Description : Sets the value of the ctichout outputs +#define M33_ITCHOUT_CTCHOUT_RESET _u(0x0) +#define M33_ITCHOUT_CTCHOUT_BITS _u(0x0000000f) +#define M33_ITCHOUT_CTCHOUT_MSB _u(3) +#define M33_ITCHOUT_CTCHOUT_LSB _u(0) +#define M33_ITCHOUT_CTCHOUT_ACCESS "RW" +// ============================================================================= +// Register : M33_ITTRIGOUT +// Description : Integration Test Trigger Output register +#define M33_ITTRIGOUT_OFFSET _u(0x00042ee8) +#define M33_ITTRIGOUT_BITS _u(0x000000ff) +#define M33_ITTRIGOUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITTRIGOUT_CTTRIGOUT +// Description : Sets the value of the ctitrigout outputs +#define M33_ITTRIGOUT_CTTRIGOUT_RESET _u(0x00) +#define M33_ITTRIGOUT_CTTRIGOUT_BITS _u(0x000000ff) +#define M33_ITTRIGOUT_CTTRIGOUT_MSB _u(7) +#define M33_ITTRIGOUT_CTTRIGOUT_LSB _u(0) +#define M33_ITTRIGOUT_CTTRIGOUT_ACCESS "RW" +// ============================================================================= +// Register : M33_ITCHIN +// Description : Integration Test Channel Input register +#define M33_ITCHIN_OFFSET _u(0x00042ef4) +#define M33_ITCHIN_BITS _u(0x0000000f) +#define M33_ITCHIN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITCHIN_CTCHIN +// Description : Reads the value of the ctichin inputs. +#define M33_ITCHIN_CTCHIN_RESET _u(0x0) +#define M33_ITCHIN_CTCHIN_BITS _u(0x0000000f) +#define M33_ITCHIN_CTCHIN_MSB _u(3) +#define M33_ITCHIN_CTCHIN_LSB _u(0) +#define M33_ITCHIN_CTCHIN_ACCESS "RO" +// ============================================================================= +// Register : M33_ITCTRL +// Description : Integration Mode Control register +#define M33_ITCTRL_OFFSET _u(0x00042f00) +#define M33_ITCTRL_BITS _u(0x00000001) +#define M33_ITCTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITCTRL_IME +// Description : Integration Mode Enable +#define M33_ITCTRL_IME_RESET _u(0x0) +#define M33_ITCTRL_IME_BITS _u(0x00000001) +#define M33_ITCTRL_IME_MSB _u(0) +#define M33_ITCTRL_IME_LSB _u(0) +#define M33_ITCTRL_IME_ACCESS "RW" +// ============================================================================= +// Register : M33_DEVARCH +// Description : Device Architecture register +#define M33_DEVARCH_OFFSET _u(0x00042fbc) +#define M33_DEVARCH_BITS _u(0xffffffff) +#define M33_DEVARCH_RESET _u(0x47701a14) +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_ARCHITECT +// Description : Indicates the component architect +#define M33_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_PRESENT +// Description : Indicates whether the DEVARCH register is present +#define M33_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_DEVARCH_PRESENT_MSB _u(20) +#define M33_DEVARCH_PRESENT_LSB _u(20) +#define M33_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_REVISION +// Description : Indicates the architecture revision +#define M33_DEVARCH_REVISION_RESET _u(0x0) +#define M33_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_DEVARCH_REVISION_MSB _u(19) +#define M33_DEVARCH_REVISION_LSB _u(16) +#define M33_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_ARCHID +// Description : Indicates the component +#define M33_DEVARCH_ARCHID_RESET _u(0x1a14) +#define M33_DEVARCH_ARCHID_BITS _u(0x0000ffff) +#define M33_DEVARCH_ARCHID_MSB _u(15) +#define M33_DEVARCH_ARCHID_LSB _u(0) +#define M33_DEVARCH_ARCHID_ACCESS "RO" +// ============================================================================= +// Register : M33_DEVID +// Description : Device Configuration register +#define M33_DEVID_OFFSET _u(0x00042fc8) +#define M33_DEVID_BITS _u(0x000fff1f) +#define M33_DEVID_RESET _u(0x00040800) +// ----------------------------------------------------------------------------- +// Field : M33_DEVID_NUMCH +// Description : Number of ECT channels available +#define M33_DEVID_NUMCH_RESET _u(0x4) +#define M33_DEVID_NUMCH_BITS _u(0x000f0000) +#define M33_DEVID_NUMCH_MSB _u(19) +#define M33_DEVID_NUMCH_LSB _u(16) +#define M33_DEVID_NUMCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVID_NUMTRIG +// Description : Number of ECT triggers available. +#define M33_DEVID_NUMTRIG_RESET _u(0x08) +#define M33_DEVID_NUMTRIG_BITS _u(0x0000ff00) +#define M33_DEVID_NUMTRIG_MSB _u(15) +#define M33_DEVID_NUMTRIG_LSB _u(8) +#define M33_DEVID_NUMTRIG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVID_EXTMUXNUM +// Description : Indicates the number of multiplexers available on Trigger +// Inputs and Trigger Outputs that are using asicctl. The default +// value of 0b00000 indicates that no multiplexing is present. +// This value of this bit depends on the Verilog define EXTMUXNUM +// that you must change accordingly. +#define M33_DEVID_EXTMUXNUM_RESET _u(0x00) +#define M33_DEVID_EXTMUXNUM_BITS _u(0x0000001f) +#define M33_DEVID_EXTMUXNUM_MSB _u(4) +#define M33_DEVID_EXTMUXNUM_LSB _u(0) +#define M33_DEVID_EXTMUXNUM_ACCESS "RO" +// ============================================================================= +// Register : M33_DEVTYPE +// Description : Device Type Identifier register +#define M33_DEVTYPE_OFFSET _u(0x00042fcc) +#define M33_DEVTYPE_BITS _u(0x000000ff) +#define M33_DEVTYPE_RESET _u(0x00000014) +// ----------------------------------------------------------------------------- +// Field : M33_DEVTYPE_SUB +// Description : Sub-classification of the type of the debug component as +// specified in the ARM Architecture Specification within the +// major classification as specified in the MAJOR field. +#define M33_DEVTYPE_SUB_RESET _u(0x1) +#define M33_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_DEVTYPE_SUB_MSB _u(7) +#define M33_DEVTYPE_SUB_LSB _u(4) +#define M33_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVTYPE_MAJOR +// Description : Major classification of the type of the debug component as +// specified in the ARM Architecture Specification for this debug +// and trace component. +#define M33_DEVTYPE_MAJOR_RESET _u(0x4) +#define M33_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_DEVTYPE_MAJOR_MSB _u(3) +#define M33_DEVTYPE_MAJOR_LSB _u(0) +#define M33_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR4 +// Description : CoreSight Peripheral ID4 +#define M33_PIDR4_OFFSET _u(0x00042fd0) +#define M33_PIDR4_BITS _u(0x000000ff) +#define M33_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR4_SIZE +// Description : Always 0b0000. Indicates that the device only occupies 4KB of +// memory +#define M33_PIDR4_SIZE_RESET _u(0x0) +#define M33_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_PIDR4_SIZE_MSB _u(7) +#define M33_PIDR4_SIZE_LSB _u(4) +#define M33_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR4_DES_2 +// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify +// the designer of the component. +#define M33_PIDR4_DES_2_RESET _u(0x4) +#define M33_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_PIDR4_DES_2_MSB _u(3) +#define M33_PIDR4_DES_2_LSB _u(0) +#define M33_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR5 +// Description : CoreSight Peripheral ID5 +#define M33_PIDR5_OFFSET _u(0x00042fd4) +#define M33_PIDR5_BITS _u(0x00000000) +#define M33_PIDR5_RESET _u(0x00000000) +#define M33_PIDR5_MSB _u(31) +#define M33_PIDR5_LSB _u(0) +#define M33_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_PIDR6 +// Description : CoreSight Peripheral ID6 +#define M33_PIDR6_OFFSET _u(0x00042fd8) +#define M33_PIDR6_BITS _u(0x00000000) +#define M33_PIDR6_RESET _u(0x00000000) +#define M33_PIDR6_MSB _u(31) +#define M33_PIDR6_LSB _u(0) +#define M33_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_PIDR7 +// Description : CoreSight Peripheral ID7 +#define M33_PIDR7_OFFSET _u(0x00042fdc) +#define M33_PIDR7_BITS _u(0x00000000) +#define M33_PIDR7_RESET _u(0x00000000) +#define M33_PIDR7_MSB _u(31) +#define M33_PIDR7_LSB _u(0) +#define M33_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_PIDR0 +// Description : CoreSight Peripheral ID0 +#define M33_PIDR0_OFFSET _u(0x00042fe0) +#define M33_PIDR0_BITS _u(0x000000ff) +#define M33_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR0_PART_0 +// Description : Bits[7:0] of the 12-bit part number of the component. The +// designer of the component assigns this part number. +#define M33_PIDR0_PART_0_RESET _u(0x21) +#define M33_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_PIDR0_PART_0_MSB _u(7) +#define M33_PIDR0_PART_0_LSB _u(0) +#define M33_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR1 +// Description : CoreSight Peripheral ID1 +#define M33_PIDR1_OFFSET _u(0x00042fe4) +#define M33_PIDR1_BITS _u(0x000000ff) +#define M33_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR1_DES_0 +// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify +// the designer of the component. +#define M33_PIDR1_DES_0_RESET _u(0xb) +#define M33_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_PIDR1_DES_0_MSB _u(7) +#define M33_PIDR1_DES_0_LSB _u(4) +#define M33_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR1_PART_1 +// Description : Bits[11:8] of the 12-bit part number of the component. The +// designer of the component assigns this part number. +#define M33_PIDR1_PART_1_RESET _u(0xd) +#define M33_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_PIDR1_PART_1_MSB _u(3) +#define M33_PIDR1_PART_1_LSB _u(0) +#define M33_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR2 +// Description : CoreSight Peripheral ID2 +#define M33_PIDR2_OFFSET _u(0x00042fe8) +#define M33_PIDR2_BITS _u(0x000000ff) +#define M33_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR2_REVISION +// Description : This device is at r1p0 +#define M33_PIDR2_REVISION_RESET _u(0x0) +#define M33_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_PIDR2_REVISION_MSB _u(7) +#define M33_PIDR2_REVISION_LSB _u(4) +#define M33_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR2_JEDEC +// Description : Always 1. Indicates that the JEDEC-assigned designer ID is +// used. +#define M33_PIDR2_JEDEC_RESET _u(0x1) +#define M33_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_PIDR2_JEDEC_MSB _u(3) +#define M33_PIDR2_JEDEC_LSB _u(3) +#define M33_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR2_DES_1 +// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify +// the designer of the component. +#define M33_PIDR2_DES_1_RESET _u(0x3) +#define M33_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_PIDR2_DES_1_MSB _u(2) +#define M33_PIDR2_DES_1_LSB _u(0) +#define M33_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR3 +// Description : CoreSight Peripheral ID3 +#define M33_PIDR3_OFFSET _u(0x00042fec) +#define M33_PIDR3_BITS _u(0x000000ff) +#define M33_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR3_REVAND +// Description : Indicates minor errata fixes specific to the revision of the +// component being used, for example metal fixes after +// implementation. In most cases, this field is 0b0000. ARM +// recommends that the component designers ensure that a metal fix +// can change this field if required, for example, by driving it +// from registers that reset to 0b0000. +#define M33_PIDR3_REVAND_RESET _u(0x0) +#define M33_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_PIDR3_REVAND_MSB _u(7) +#define M33_PIDR3_REVAND_LSB _u(4) +#define M33_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR3_CMOD +// Description : Customer Modified. Indicates whether the customer has modified +// the behavior of the component. In most cases, this field is +// 0b0000. Customers change this value when they make authorized +// modifications to this component. +#define M33_PIDR3_CMOD_RESET _u(0x0) +#define M33_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_PIDR3_CMOD_MSB _u(3) +#define M33_PIDR3_CMOD_LSB _u(0) +#define M33_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR0 +// Description : CoreSight Component ID0 +#define M33_CIDR0_OFFSET _u(0x00042ff0) +#define M33_CIDR0_BITS _u(0x000000ff) +#define M33_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR0_PRMBL_0 +// Description : Preamble[0]. Contains bits[7:0] of the component identification +// code +#define M33_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_CIDR0_PRMBL_0_MSB _u(7) +#define M33_CIDR0_PRMBL_0_LSB _u(0) +#define M33_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR1 +// Description : CoreSight Component ID1 +#define M33_CIDR1_OFFSET _u(0x00042ff4) +#define M33_CIDR1_BITS _u(0x000000ff) +#define M33_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR1_CLASS +// Description : Class of the component, for example, whether the component is a +// ROM table or a generic CoreSight component. Contains +// bits[15:12] of the component identification code. +#define M33_CIDR1_CLASS_RESET _u(0x9) +#define M33_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_CIDR1_CLASS_MSB _u(7) +#define M33_CIDR1_CLASS_LSB _u(4) +#define M33_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CIDR1_PRMBL_1 +// Description : Preamble[1]. Contains bits[11:8] of the component +// identification code. +#define M33_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_CIDR1_PRMBL_1_MSB _u(3) +#define M33_CIDR1_PRMBL_1_LSB _u(0) +#define M33_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR2 +// Description : CoreSight Component ID2 +#define M33_CIDR2_OFFSET _u(0x00042ff8) +#define M33_CIDR2_BITS _u(0x000000ff) +#define M33_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR2_PRMBL_2 +// Description : Preamble[2]. Contains bits[23:16] of the component +// identification code. +#define M33_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_CIDR2_PRMBL_2_MSB _u(7) +#define M33_CIDR2_PRMBL_2_LSB _u(0) +#define M33_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR3 +// Description : CoreSight Component ID3 +#define M33_CIDR3_OFFSET _u(0x00042ffc) +#define M33_CIDR3_BITS _u(0x000000ff) +#define M33_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR3_PRMBL_3 +// Description : Preamble[3]. Contains bits[31:24] of the component +// identification code. +#define M33_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_CIDR3_PRMBL_3_MSB _u(7) +#define M33_CIDR3_PRMBL_3_LSB _u(0) +#define M33_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_M33_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h b/src/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h new file mode 100644 index 000000000..93b5143b2 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/m33_eppb.h @@ -0,0 +1,80 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : M33_EPPB +// Version : 1 +// Bus type : apb +// Description : Cortex-M33 EPPB vendor register block for RP2350 +// ============================================================================= +#ifndef _HARDWARE_REGS_M33_EPPB_H +#define _HARDWARE_REGS_M33_EPPB_H +// ============================================================================= +// Register : M33_EPPB_NMI_MASK0 +// Description : NMI mask for IRQs 0 through 31. This register is core-local, +// and is reset by a processor warm reset. +#define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000) +#define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff) +#define M33_EPPB_NMI_MASK0_RESET _u(0x00000000) +#define M33_EPPB_NMI_MASK0_MSB _u(31) +#define M33_EPPB_NMI_MASK0_LSB _u(0) +#define M33_EPPB_NMI_MASK0_ACCESS "RW" +// ============================================================================= +// Register : M33_EPPB_NMI_MASK1 +// Description : NMI mask for IRQs 0 though 51. This register is core-local, and +// is reset by a processor warm reset. +#define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004) +#define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff) +#define M33_EPPB_NMI_MASK1_RESET _u(0x00000000) +#define M33_EPPB_NMI_MASK1_MSB _u(19) +#define M33_EPPB_NMI_MASK1_LSB _u(0) +#define M33_EPPB_NMI_MASK1_ACCESS "RW" +// ============================================================================= +// Register : M33_EPPB_SLEEPCTRL +// Description : Nonstandard sleep control register +#define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008) +#define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007) +#define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002) +// ----------------------------------------------------------------------------- +// Field : M33_EPPB_SLEEPCTRL_WICENACK +// Description : Status signal from the processor's interrupt controller. +// Changes to WICENREQ are eventually reflected in WICENACK. +#define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0) +#define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004) +#define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2) +#define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2) +#define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_EPPB_SLEEPCTRL_WICENREQ +// Description : Request that the next processor deep sleep is a WIC sleep. +// After setting this bit, before sleeping, poll WICENACK to +// ensure the processor interrupt controller has acknowledged the +// change. +#define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1) +#define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002) +#define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1) +#define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1) +#define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP +// Description : By default, any processor sleep will deassert the system-level +// clock request. Reenabling the clocks incurs 5 cycles of +// additional latency on wakeup. +// +// Setting LIGHT_SLEEP to 1 keeps the clock request asserted +// during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster +// wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not +// affected, and will always deassert the system-level clock +// request. +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_M33_EPPB_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/otp.h b/src/rp2350/hardware_regs/include/hardware/regs/otp.h new file mode 100644 index 000000000..cd9c6e85e --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/otp.h @@ -0,0 +1,3467 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : OTP +// Version : 1 +// Bus type : apb +// Description : SNPS OTP control IF (SBPI and RPi wrapper control) +// ============================================================================= +#ifndef _HARDWARE_REGS_OTP_H +#define _HARDWARE_REGS_OTP_H +// ============================================================================= +// Register : OTP_SW_LOCK0 +// Description : Software lock register for page 0. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK0_OFFSET _u(0x00000000) +#define OTP_SW_LOCK0_BITS _u(0x0000000f) +#define OTP_SW_LOCK0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK0_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK0_NSEC_RESET "-" +#define OTP_SW_LOCK0_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK0_NSEC_MSB _u(3) +#define OTP_SW_LOCK0_NSEC_LSB _u(2) +#define OTP_SW_LOCK0_NSEC_ACCESS "RW" +#define OTP_SW_LOCK0_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK0_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK0_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK0_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK0_SEC_RESET "-" +#define OTP_SW_LOCK0_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK0_SEC_MSB _u(1) +#define OTP_SW_LOCK0_SEC_LSB _u(0) +#define OTP_SW_LOCK0_SEC_ACCESS "RW" +#define OTP_SW_LOCK0_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK0_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK0_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK1 +// Description : Software lock register for page 1. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK1_OFFSET _u(0x00000004) +#define OTP_SW_LOCK1_BITS _u(0x0000000f) +#define OTP_SW_LOCK1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK1_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK1_NSEC_RESET "-" +#define OTP_SW_LOCK1_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK1_NSEC_MSB _u(3) +#define OTP_SW_LOCK1_NSEC_LSB _u(2) +#define OTP_SW_LOCK1_NSEC_ACCESS "RW" +#define OTP_SW_LOCK1_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK1_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK1_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK1_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK1_SEC_RESET "-" +#define OTP_SW_LOCK1_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK1_SEC_MSB _u(1) +#define OTP_SW_LOCK1_SEC_LSB _u(0) +#define OTP_SW_LOCK1_SEC_ACCESS "RW" +#define OTP_SW_LOCK1_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK1_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK1_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK2 +// Description : Software lock register for page 2. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK2_OFFSET _u(0x00000008) +#define OTP_SW_LOCK2_BITS _u(0x0000000f) +#define OTP_SW_LOCK2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK2_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK2_NSEC_RESET "-" +#define OTP_SW_LOCK2_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK2_NSEC_MSB _u(3) +#define OTP_SW_LOCK2_NSEC_LSB _u(2) +#define OTP_SW_LOCK2_NSEC_ACCESS "RW" +#define OTP_SW_LOCK2_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK2_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK2_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK2_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK2_SEC_RESET "-" +#define OTP_SW_LOCK2_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK2_SEC_MSB _u(1) +#define OTP_SW_LOCK2_SEC_LSB _u(0) +#define OTP_SW_LOCK2_SEC_ACCESS "RW" +#define OTP_SW_LOCK2_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK2_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK2_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK3 +// Description : Software lock register for page 3. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK3_OFFSET _u(0x0000000c) +#define OTP_SW_LOCK3_BITS _u(0x0000000f) +#define OTP_SW_LOCK3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK3_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK3_NSEC_RESET "-" +#define OTP_SW_LOCK3_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK3_NSEC_MSB _u(3) +#define OTP_SW_LOCK3_NSEC_LSB _u(2) +#define OTP_SW_LOCK3_NSEC_ACCESS "RW" +#define OTP_SW_LOCK3_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK3_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK3_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK3_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK3_SEC_RESET "-" +#define OTP_SW_LOCK3_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK3_SEC_MSB _u(1) +#define OTP_SW_LOCK3_SEC_LSB _u(0) +#define OTP_SW_LOCK3_SEC_ACCESS "RW" +#define OTP_SW_LOCK3_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK3_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK3_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK4 +// Description : Software lock register for page 4. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK4_OFFSET _u(0x00000010) +#define OTP_SW_LOCK4_BITS _u(0x0000000f) +#define OTP_SW_LOCK4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK4_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK4_NSEC_RESET "-" +#define OTP_SW_LOCK4_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK4_NSEC_MSB _u(3) +#define OTP_SW_LOCK4_NSEC_LSB _u(2) +#define OTP_SW_LOCK4_NSEC_ACCESS "RW" +#define OTP_SW_LOCK4_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK4_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK4_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK4_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK4_SEC_RESET "-" +#define OTP_SW_LOCK4_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK4_SEC_MSB _u(1) +#define OTP_SW_LOCK4_SEC_LSB _u(0) +#define OTP_SW_LOCK4_SEC_ACCESS "RW" +#define OTP_SW_LOCK4_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK4_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK4_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK5 +// Description : Software lock register for page 5. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK5_OFFSET _u(0x00000014) +#define OTP_SW_LOCK5_BITS _u(0x0000000f) +#define OTP_SW_LOCK5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK5_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK5_NSEC_RESET "-" +#define OTP_SW_LOCK5_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK5_NSEC_MSB _u(3) +#define OTP_SW_LOCK5_NSEC_LSB _u(2) +#define OTP_SW_LOCK5_NSEC_ACCESS "RW" +#define OTP_SW_LOCK5_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK5_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK5_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK5_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK5_SEC_RESET "-" +#define OTP_SW_LOCK5_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK5_SEC_MSB _u(1) +#define OTP_SW_LOCK5_SEC_LSB _u(0) +#define OTP_SW_LOCK5_SEC_ACCESS "RW" +#define OTP_SW_LOCK5_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK5_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK5_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK6 +// Description : Software lock register for page 6. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK6_OFFSET _u(0x00000018) +#define OTP_SW_LOCK6_BITS _u(0x0000000f) +#define OTP_SW_LOCK6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK6_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK6_NSEC_RESET "-" +#define OTP_SW_LOCK6_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK6_NSEC_MSB _u(3) +#define OTP_SW_LOCK6_NSEC_LSB _u(2) +#define OTP_SW_LOCK6_NSEC_ACCESS "RW" +#define OTP_SW_LOCK6_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK6_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK6_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK6_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK6_SEC_RESET "-" +#define OTP_SW_LOCK6_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK6_SEC_MSB _u(1) +#define OTP_SW_LOCK6_SEC_LSB _u(0) +#define OTP_SW_LOCK6_SEC_ACCESS "RW" +#define OTP_SW_LOCK6_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK6_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK6_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK7 +// Description : Software lock register for page 7. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK7_OFFSET _u(0x0000001c) +#define OTP_SW_LOCK7_BITS _u(0x0000000f) +#define OTP_SW_LOCK7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK7_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK7_NSEC_RESET "-" +#define OTP_SW_LOCK7_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK7_NSEC_MSB _u(3) +#define OTP_SW_LOCK7_NSEC_LSB _u(2) +#define OTP_SW_LOCK7_NSEC_ACCESS "RW" +#define OTP_SW_LOCK7_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK7_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK7_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK7_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK7_SEC_RESET "-" +#define OTP_SW_LOCK7_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK7_SEC_MSB _u(1) +#define OTP_SW_LOCK7_SEC_LSB _u(0) +#define OTP_SW_LOCK7_SEC_ACCESS "RW" +#define OTP_SW_LOCK7_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK7_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK7_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK8 +// Description : Software lock register for page 8. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK8_OFFSET _u(0x00000020) +#define OTP_SW_LOCK8_BITS _u(0x0000000f) +#define OTP_SW_LOCK8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK8_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK8_NSEC_RESET "-" +#define OTP_SW_LOCK8_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK8_NSEC_MSB _u(3) +#define OTP_SW_LOCK8_NSEC_LSB _u(2) +#define OTP_SW_LOCK8_NSEC_ACCESS "RW" +#define OTP_SW_LOCK8_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK8_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK8_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK8_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK8_SEC_RESET "-" +#define OTP_SW_LOCK8_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK8_SEC_MSB _u(1) +#define OTP_SW_LOCK8_SEC_LSB _u(0) +#define OTP_SW_LOCK8_SEC_ACCESS "RW" +#define OTP_SW_LOCK8_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK8_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK8_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK9 +// Description : Software lock register for page 9. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK9_OFFSET _u(0x00000024) +#define OTP_SW_LOCK9_BITS _u(0x0000000f) +#define OTP_SW_LOCK9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK9_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK9_NSEC_RESET "-" +#define OTP_SW_LOCK9_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK9_NSEC_MSB _u(3) +#define OTP_SW_LOCK9_NSEC_LSB _u(2) +#define OTP_SW_LOCK9_NSEC_ACCESS "RW" +#define OTP_SW_LOCK9_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK9_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK9_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK9_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK9_SEC_RESET "-" +#define OTP_SW_LOCK9_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK9_SEC_MSB _u(1) +#define OTP_SW_LOCK9_SEC_LSB _u(0) +#define OTP_SW_LOCK9_SEC_ACCESS "RW" +#define OTP_SW_LOCK9_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK9_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK9_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK10 +// Description : Software lock register for page 10. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK10_OFFSET _u(0x00000028) +#define OTP_SW_LOCK10_BITS _u(0x0000000f) +#define OTP_SW_LOCK10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK10_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK10_NSEC_RESET "-" +#define OTP_SW_LOCK10_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK10_NSEC_MSB _u(3) +#define OTP_SW_LOCK10_NSEC_LSB _u(2) +#define OTP_SW_LOCK10_NSEC_ACCESS "RW" +#define OTP_SW_LOCK10_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK10_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK10_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK10_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK10_SEC_RESET "-" +#define OTP_SW_LOCK10_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK10_SEC_MSB _u(1) +#define OTP_SW_LOCK10_SEC_LSB _u(0) +#define OTP_SW_LOCK10_SEC_ACCESS "RW" +#define OTP_SW_LOCK10_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK10_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK10_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK11 +// Description : Software lock register for page 11. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK11_OFFSET _u(0x0000002c) +#define OTP_SW_LOCK11_BITS _u(0x0000000f) +#define OTP_SW_LOCK11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK11_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK11_NSEC_RESET "-" +#define OTP_SW_LOCK11_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK11_NSEC_MSB _u(3) +#define OTP_SW_LOCK11_NSEC_LSB _u(2) +#define OTP_SW_LOCK11_NSEC_ACCESS "RW" +#define OTP_SW_LOCK11_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK11_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK11_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK11_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK11_SEC_RESET "-" +#define OTP_SW_LOCK11_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK11_SEC_MSB _u(1) +#define OTP_SW_LOCK11_SEC_LSB _u(0) +#define OTP_SW_LOCK11_SEC_ACCESS "RW" +#define OTP_SW_LOCK11_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK11_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK11_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK12 +// Description : Software lock register for page 12. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK12_OFFSET _u(0x00000030) +#define OTP_SW_LOCK12_BITS _u(0x0000000f) +#define OTP_SW_LOCK12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK12_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK12_NSEC_RESET "-" +#define OTP_SW_LOCK12_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK12_NSEC_MSB _u(3) +#define OTP_SW_LOCK12_NSEC_LSB _u(2) +#define OTP_SW_LOCK12_NSEC_ACCESS "RW" +#define OTP_SW_LOCK12_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK12_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK12_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK12_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK12_SEC_RESET "-" +#define OTP_SW_LOCK12_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK12_SEC_MSB _u(1) +#define OTP_SW_LOCK12_SEC_LSB _u(0) +#define OTP_SW_LOCK12_SEC_ACCESS "RW" +#define OTP_SW_LOCK12_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK12_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK12_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK13 +// Description : Software lock register for page 13. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK13_OFFSET _u(0x00000034) +#define OTP_SW_LOCK13_BITS _u(0x0000000f) +#define OTP_SW_LOCK13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK13_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK13_NSEC_RESET "-" +#define OTP_SW_LOCK13_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK13_NSEC_MSB _u(3) +#define OTP_SW_LOCK13_NSEC_LSB _u(2) +#define OTP_SW_LOCK13_NSEC_ACCESS "RW" +#define OTP_SW_LOCK13_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK13_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK13_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK13_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK13_SEC_RESET "-" +#define OTP_SW_LOCK13_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK13_SEC_MSB _u(1) +#define OTP_SW_LOCK13_SEC_LSB _u(0) +#define OTP_SW_LOCK13_SEC_ACCESS "RW" +#define OTP_SW_LOCK13_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK13_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK13_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK14 +// Description : Software lock register for page 14. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK14_OFFSET _u(0x00000038) +#define OTP_SW_LOCK14_BITS _u(0x0000000f) +#define OTP_SW_LOCK14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK14_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK14_NSEC_RESET "-" +#define OTP_SW_LOCK14_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK14_NSEC_MSB _u(3) +#define OTP_SW_LOCK14_NSEC_LSB _u(2) +#define OTP_SW_LOCK14_NSEC_ACCESS "RW" +#define OTP_SW_LOCK14_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK14_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK14_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK14_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK14_SEC_RESET "-" +#define OTP_SW_LOCK14_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK14_SEC_MSB _u(1) +#define OTP_SW_LOCK14_SEC_LSB _u(0) +#define OTP_SW_LOCK14_SEC_ACCESS "RW" +#define OTP_SW_LOCK14_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK14_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK14_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK15 +// Description : Software lock register for page 15. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK15_OFFSET _u(0x0000003c) +#define OTP_SW_LOCK15_BITS _u(0x0000000f) +#define OTP_SW_LOCK15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK15_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK15_NSEC_RESET "-" +#define OTP_SW_LOCK15_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK15_NSEC_MSB _u(3) +#define OTP_SW_LOCK15_NSEC_LSB _u(2) +#define OTP_SW_LOCK15_NSEC_ACCESS "RW" +#define OTP_SW_LOCK15_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK15_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK15_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK15_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK15_SEC_RESET "-" +#define OTP_SW_LOCK15_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK15_SEC_MSB _u(1) +#define OTP_SW_LOCK15_SEC_LSB _u(0) +#define OTP_SW_LOCK15_SEC_ACCESS "RW" +#define OTP_SW_LOCK15_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK15_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK15_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK16 +// Description : Software lock register for page 16. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK16_OFFSET _u(0x00000040) +#define OTP_SW_LOCK16_BITS _u(0x0000000f) +#define OTP_SW_LOCK16_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK16_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK16_NSEC_RESET "-" +#define OTP_SW_LOCK16_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK16_NSEC_MSB _u(3) +#define OTP_SW_LOCK16_NSEC_LSB _u(2) +#define OTP_SW_LOCK16_NSEC_ACCESS "RW" +#define OTP_SW_LOCK16_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK16_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK16_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK16_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK16_SEC_RESET "-" +#define OTP_SW_LOCK16_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK16_SEC_MSB _u(1) +#define OTP_SW_LOCK16_SEC_LSB _u(0) +#define OTP_SW_LOCK16_SEC_ACCESS "RW" +#define OTP_SW_LOCK16_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK16_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK16_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK17 +// Description : Software lock register for page 17. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK17_OFFSET _u(0x00000044) +#define OTP_SW_LOCK17_BITS _u(0x0000000f) +#define OTP_SW_LOCK17_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK17_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK17_NSEC_RESET "-" +#define OTP_SW_LOCK17_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK17_NSEC_MSB _u(3) +#define OTP_SW_LOCK17_NSEC_LSB _u(2) +#define OTP_SW_LOCK17_NSEC_ACCESS "RW" +#define OTP_SW_LOCK17_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK17_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK17_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK17_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK17_SEC_RESET "-" +#define OTP_SW_LOCK17_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK17_SEC_MSB _u(1) +#define OTP_SW_LOCK17_SEC_LSB _u(0) +#define OTP_SW_LOCK17_SEC_ACCESS "RW" +#define OTP_SW_LOCK17_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK17_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK17_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK18 +// Description : Software lock register for page 18. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK18_OFFSET _u(0x00000048) +#define OTP_SW_LOCK18_BITS _u(0x0000000f) +#define OTP_SW_LOCK18_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK18_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK18_NSEC_RESET "-" +#define OTP_SW_LOCK18_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK18_NSEC_MSB _u(3) +#define OTP_SW_LOCK18_NSEC_LSB _u(2) +#define OTP_SW_LOCK18_NSEC_ACCESS "RW" +#define OTP_SW_LOCK18_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK18_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK18_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK18_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK18_SEC_RESET "-" +#define OTP_SW_LOCK18_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK18_SEC_MSB _u(1) +#define OTP_SW_LOCK18_SEC_LSB _u(0) +#define OTP_SW_LOCK18_SEC_ACCESS "RW" +#define OTP_SW_LOCK18_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK18_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK18_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK19 +// Description : Software lock register for page 19. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK19_OFFSET _u(0x0000004c) +#define OTP_SW_LOCK19_BITS _u(0x0000000f) +#define OTP_SW_LOCK19_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK19_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK19_NSEC_RESET "-" +#define OTP_SW_LOCK19_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK19_NSEC_MSB _u(3) +#define OTP_SW_LOCK19_NSEC_LSB _u(2) +#define OTP_SW_LOCK19_NSEC_ACCESS "RW" +#define OTP_SW_LOCK19_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK19_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK19_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK19_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK19_SEC_RESET "-" +#define OTP_SW_LOCK19_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK19_SEC_MSB _u(1) +#define OTP_SW_LOCK19_SEC_LSB _u(0) +#define OTP_SW_LOCK19_SEC_ACCESS "RW" +#define OTP_SW_LOCK19_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK19_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK19_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK20 +// Description : Software lock register for page 20. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK20_OFFSET _u(0x00000050) +#define OTP_SW_LOCK20_BITS _u(0x0000000f) +#define OTP_SW_LOCK20_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK20_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK20_NSEC_RESET "-" +#define OTP_SW_LOCK20_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK20_NSEC_MSB _u(3) +#define OTP_SW_LOCK20_NSEC_LSB _u(2) +#define OTP_SW_LOCK20_NSEC_ACCESS "RW" +#define OTP_SW_LOCK20_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK20_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK20_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK20_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK20_SEC_RESET "-" +#define OTP_SW_LOCK20_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK20_SEC_MSB _u(1) +#define OTP_SW_LOCK20_SEC_LSB _u(0) +#define OTP_SW_LOCK20_SEC_ACCESS "RW" +#define OTP_SW_LOCK20_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK20_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK20_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK21 +// Description : Software lock register for page 21. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK21_OFFSET _u(0x00000054) +#define OTP_SW_LOCK21_BITS _u(0x0000000f) +#define OTP_SW_LOCK21_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK21_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK21_NSEC_RESET "-" +#define OTP_SW_LOCK21_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK21_NSEC_MSB _u(3) +#define OTP_SW_LOCK21_NSEC_LSB _u(2) +#define OTP_SW_LOCK21_NSEC_ACCESS "RW" +#define OTP_SW_LOCK21_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK21_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK21_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK21_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK21_SEC_RESET "-" +#define OTP_SW_LOCK21_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK21_SEC_MSB _u(1) +#define OTP_SW_LOCK21_SEC_LSB _u(0) +#define OTP_SW_LOCK21_SEC_ACCESS "RW" +#define OTP_SW_LOCK21_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK21_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK21_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK22 +// Description : Software lock register for page 22. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK22_OFFSET _u(0x00000058) +#define OTP_SW_LOCK22_BITS _u(0x0000000f) +#define OTP_SW_LOCK22_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK22_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK22_NSEC_RESET "-" +#define OTP_SW_LOCK22_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK22_NSEC_MSB _u(3) +#define OTP_SW_LOCK22_NSEC_LSB _u(2) +#define OTP_SW_LOCK22_NSEC_ACCESS "RW" +#define OTP_SW_LOCK22_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK22_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK22_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK22_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK22_SEC_RESET "-" +#define OTP_SW_LOCK22_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK22_SEC_MSB _u(1) +#define OTP_SW_LOCK22_SEC_LSB _u(0) +#define OTP_SW_LOCK22_SEC_ACCESS "RW" +#define OTP_SW_LOCK22_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK22_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK22_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK23 +// Description : Software lock register for page 23. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK23_OFFSET _u(0x0000005c) +#define OTP_SW_LOCK23_BITS _u(0x0000000f) +#define OTP_SW_LOCK23_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK23_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK23_NSEC_RESET "-" +#define OTP_SW_LOCK23_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK23_NSEC_MSB _u(3) +#define OTP_SW_LOCK23_NSEC_LSB _u(2) +#define OTP_SW_LOCK23_NSEC_ACCESS "RW" +#define OTP_SW_LOCK23_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK23_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK23_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK23_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK23_SEC_RESET "-" +#define OTP_SW_LOCK23_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK23_SEC_MSB _u(1) +#define OTP_SW_LOCK23_SEC_LSB _u(0) +#define OTP_SW_LOCK23_SEC_ACCESS "RW" +#define OTP_SW_LOCK23_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK23_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK23_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK24 +// Description : Software lock register for page 24. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK24_OFFSET _u(0x00000060) +#define OTP_SW_LOCK24_BITS _u(0x0000000f) +#define OTP_SW_LOCK24_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK24_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK24_NSEC_RESET "-" +#define OTP_SW_LOCK24_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK24_NSEC_MSB _u(3) +#define OTP_SW_LOCK24_NSEC_LSB _u(2) +#define OTP_SW_LOCK24_NSEC_ACCESS "RW" +#define OTP_SW_LOCK24_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK24_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK24_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK24_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK24_SEC_RESET "-" +#define OTP_SW_LOCK24_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK24_SEC_MSB _u(1) +#define OTP_SW_LOCK24_SEC_LSB _u(0) +#define OTP_SW_LOCK24_SEC_ACCESS "RW" +#define OTP_SW_LOCK24_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK24_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK24_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK25 +// Description : Software lock register for page 25. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK25_OFFSET _u(0x00000064) +#define OTP_SW_LOCK25_BITS _u(0x0000000f) +#define OTP_SW_LOCK25_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK25_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK25_NSEC_RESET "-" +#define OTP_SW_LOCK25_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK25_NSEC_MSB _u(3) +#define OTP_SW_LOCK25_NSEC_LSB _u(2) +#define OTP_SW_LOCK25_NSEC_ACCESS "RW" +#define OTP_SW_LOCK25_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK25_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK25_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK25_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK25_SEC_RESET "-" +#define OTP_SW_LOCK25_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK25_SEC_MSB _u(1) +#define OTP_SW_LOCK25_SEC_LSB _u(0) +#define OTP_SW_LOCK25_SEC_ACCESS "RW" +#define OTP_SW_LOCK25_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK25_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK25_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK26 +// Description : Software lock register for page 26. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK26_OFFSET _u(0x00000068) +#define OTP_SW_LOCK26_BITS _u(0x0000000f) +#define OTP_SW_LOCK26_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK26_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK26_NSEC_RESET "-" +#define OTP_SW_LOCK26_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK26_NSEC_MSB _u(3) +#define OTP_SW_LOCK26_NSEC_LSB _u(2) +#define OTP_SW_LOCK26_NSEC_ACCESS "RW" +#define OTP_SW_LOCK26_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK26_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK26_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK26_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK26_SEC_RESET "-" +#define OTP_SW_LOCK26_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK26_SEC_MSB _u(1) +#define OTP_SW_LOCK26_SEC_LSB _u(0) +#define OTP_SW_LOCK26_SEC_ACCESS "RW" +#define OTP_SW_LOCK26_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK26_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK26_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK27 +// Description : Software lock register for page 27. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK27_OFFSET _u(0x0000006c) +#define OTP_SW_LOCK27_BITS _u(0x0000000f) +#define OTP_SW_LOCK27_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK27_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK27_NSEC_RESET "-" +#define OTP_SW_LOCK27_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK27_NSEC_MSB _u(3) +#define OTP_SW_LOCK27_NSEC_LSB _u(2) +#define OTP_SW_LOCK27_NSEC_ACCESS "RW" +#define OTP_SW_LOCK27_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK27_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK27_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK27_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK27_SEC_RESET "-" +#define OTP_SW_LOCK27_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK27_SEC_MSB _u(1) +#define OTP_SW_LOCK27_SEC_LSB _u(0) +#define OTP_SW_LOCK27_SEC_ACCESS "RW" +#define OTP_SW_LOCK27_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK27_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK27_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK28 +// Description : Software lock register for page 28. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK28_OFFSET _u(0x00000070) +#define OTP_SW_LOCK28_BITS _u(0x0000000f) +#define OTP_SW_LOCK28_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK28_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK28_NSEC_RESET "-" +#define OTP_SW_LOCK28_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK28_NSEC_MSB _u(3) +#define OTP_SW_LOCK28_NSEC_LSB _u(2) +#define OTP_SW_LOCK28_NSEC_ACCESS "RW" +#define OTP_SW_LOCK28_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK28_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK28_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK28_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK28_SEC_RESET "-" +#define OTP_SW_LOCK28_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK28_SEC_MSB _u(1) +#define OTP_SW_LOCK28_SEC_LSB _u(0) +#define OTP_SW_LOCK28_SEC_ACCESS "RW" +#define OTP_SW_LOCK28_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK28_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK28_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK29 +// Description : Software lock register for page 29. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK29_OFFSET _u(0x00000074) +#define OTP_SW_LOCK29_BITS _u(0x0000000f) +#define OTP_SW_LOCK29_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK29_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK29_NSEC_RESET "-" +#define OTP_SW_LOCK29_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK29_NSEC_MSB _u(3) +#define OTP_SW_LOCK29_NSEC_LSB _u(2) +#define OTP_SW_LOCK29_NSEC_ACCESS "RW" +#define OTP_SW_LOCK29_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK29_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK29_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK29_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK29_SEC_RESET "-" +#define OTP_SW_LOCK29_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK29_SEC_MSB _u(1) +#define OTP_SW_LOCK29_SEC_LSB _u(0) +#define OTP_SW_LOCK29_SEC_ACCESS "RW" +#define OTP_SW_LOCK29_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK29_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK29_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK30 +// Description : Software lock register for page 30. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK30_OFFSET _u(0x00000078) +#define OTP_SW_LOCK30_BITS _u(0x0000000f) +#define OTP_SW_LOCK30_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK30_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK30_NSEC_RESET "-" +#define OTP_SW_LOCK30_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK30_NSEC_MSB _u(3) +#define OTP_SW_LOCK30_NSEC_LSB _u(2) +#define OTP_SW_LOCK30_NSEC_ACCESS "RW" +#define OTP_SW_LOCK30_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK30_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK30_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK30_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK30_SEC_RESET "-" +#define OTP_SW_LOCK30_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK30_SEC_MSB _u(1) +#define OTP_SW_LOCK30_SEC_LSB _u(0) +#define OTP_SW_LOCK30_SEC_ACCESS "RW" +#define OTP_SW_LOCK30_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK30_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK30_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK31 +// Description : Software lock register for page 31. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK31_OFFSET _u(0x0000007c) +#define OTP_SW_LOCK31_BITS _u(0x0000000f) +#define OTP_SW_LOCK31_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK31_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK31_NSEC_RESET "-" +#define OTP_SW_LOCK31_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK31_NSEC_MSB _u(3) +#define OTP_SW_LOCK31_NSEC_LSB _u(2) +#define OTP_SW_LOCK31_NSEC_ACCESS "RW" +#define OTP_SW_LOCK31_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK31_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK31_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK31_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK31_SEC_RESET "-" +#define OTP_SW_LOCK31_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK31_SEC_MSB _u(1) +#define OTP_SW_LOCK31_SEC_LSB _u(0) +#define OTP_SW_LOCK31_SEC_ACCESS "RW" +#define OTP_SW_LOCK31_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK31_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK31_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK32 +// Description : Software lock register for page 32. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK32_OFFSET _u(0x00000080) +#define OTP_SW_LOCK32_BITS _u(0x0000000f) +#define OTP_SW_LOCK32_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK32_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK32_NSEC_RESET "-" +#define OTP_SW_LOCK32_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK32_NSEC_MSB _u(3) +#define OTP_SW_LOCK32_NSEC_LSB _u(2) +#define OTP_SW_LOCK32_NSEC_ACCESS "RW" +#define OTP_SW_LOCK32_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK32_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK32_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK32_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK32_SEC_RESET "-" +#define OTP_SW_LOCK32_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK32_SEC_MSB _u(1) +#define OTP_SW_LOCK32_SEC_LSB _u(0) +#define OTP_SW_LOCK32_SEC_ACCESS "RW" +#define OTP_SW_LOCK32_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK32_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK32_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK33 +// Description : Software lock register for page 33. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK33_OFFSET _u(0x00000084) +#define OTP_SW_LOCK33_BITS _u(0x0000000f) +#define OTP_SW_LOCK33_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK33_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK33_NSEC_RESET "-" +#define OTP_SW_LOCK33_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK33_NSEC_MSB _u(3) +#define OTP_SW_LOCK33_NSEC_LSB _u(2) +#define OTP_SW_LOCK33_NSEC_ACCESS "RW" +#define OTP_SW_LOCK33_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK33_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK33_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK33_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK33_SEC_RESET "-" +#define OTP_SW_LOCK33_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK33_SEC_MSB _u(1) +#define OTP_SW_LOCK33_SEC_LSB _u(0) +#define OTP_SW_LOCK33_SEC_ACCESS "RW" +#define OTP_SW_LOCK33_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK33_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK33_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK34 +// Description : Software lock register for page 34. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK34_OFFSET _u(0x00000088) +#define OTP_SW_LOCK34_BITS _u(0x0000000f) +#define OTP_SW_LOCK34_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK34_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK34_NSEC_RESET "-" +#define OTP_SW_LOCK34_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK34_NSEC_MSB _u(3) +#define OTP_SW_LOCK34_NSEC_LSB _u(2) +#define OTP_SW_LOCK34_NSEC_ACCESS "RW" +#define OTP_SW_LOCK34_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK34_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK34_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK34_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK34_SEC_RESET "-" +#define OTP_SW_LOCK34_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK34_SEC_MSB _u(1) +#define OTP_SW_LOCK34_SEC_LSB _u(0) +#define OTP_SW_LOCK34_SEC_ACCESS "RW" +#define OTP_SW_LOCK34_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK34_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK34_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK35 +// Description : Software lock register for page 35. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK35_OFFSET _u(0x0000008c) +#define OTP_SW_LOCK35_BITS _u(0x0000000f) +#define OTP_SW_LOCK35_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK35_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK35_NSEC_RESET "-" +#define OTP_SW_LOCK35_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK35_NSEC_MSB _u(3) +#define OTP_SW_LOCK35_NSEC_LSB _u(2) +#define OTP_SW_LOCK35_NSEC_ACCESS "RW" +#define OTP_SW_LOCK35_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK35_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK35_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK35_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK35_SEC_RESET "-" +#define OTP_SW_LOCK35_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK35_SEC_MSB _u(1) +#define OTP_SW_LOCK35_SEC_LSB _u(0) +#define OTP_SW_LOCK35_SEC_ACCESS "RW" +#define OTP_SW_LOCK35_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK35_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK35_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK36 +// Description : Software lock register for page 36. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK36_OFFSET _u(0x00000090) +#define OTP_SW_LOCK36_BITS _u(0x0000000f) +#define OTP_SW_LOCK36_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK36_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK36_NSEC_RESET "-" +#define OTP_SW_LOCK36_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK36_NSEC_MSB _u(3) +#define OTP_SW_LOCK36_NSEC_LSB _u(2) +#define OTP_SW_LOCK36_NSEC_ACCESS "RW" +#define OTP_SW_LOCK36_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK36_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK36_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK36_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK36_SEC_RESET "-" +#define OTP_SW_LOCK36_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK36_SEC_MSB _u(1) +#define OTP_SW_LOCK36_SEC_LSB _u(0) +#define OTP_SW_LOCK36_SEC_ACCESS "RW" +#define OTP_SW_LOCK36_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK36_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK36_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK37 +// Description : Software lock register for page 37. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK37_OFFSET _u(0x00000094) +#define OTP_SW_LOCK37_BITS _u(0x0000000f) +#define OTP_SW_LOCK37_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK37_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK37_NSEC_RESET "-" +#define OTP_SW_LOCK37_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK37_NSEC_MSB _u(3) +#define OTP_SW_LOCK37_NSEC_LSB _u(2) +#define OTP_SW_LOCK37_NSEC_ACCESS "RW" +#define OTP_SW_LOCK37_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK37_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK37_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK37_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK37_SEC_RESET "-" +#define OTP_SW_LOCK37_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK37_SEC_MSB _u(1) +#define OTP_SW_LOCK37_SEC_LSB _u(0) +#define OTP_SW_LOCK37_SEC_ACCESS "RW" +#define OTP_SW_LOCK37_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK37_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK37_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK38 +// Description : Software lock register for page 38. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK38_OFFSET _u(0x00000098) +#define OTP_SW_LOCK38_BITS _u(0x0000000f) +#define OTP_SW_LOCK38_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK38_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK38_NSEC_RESET "-" +#define OTP_SW_LOCK38_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK38_NSEC_MSB _u(3) +#define OTP_SW_LOCK38_NSEC_LSB _u(2) +#define OTP_SW_LOCK38_NSEC_ACCESS "RW" +#define OTP_SW_LOCK38_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK38_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK38_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK38_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK38_SEC_RESET "-" +#define OTP_SW_LOCK38_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK38_SEC_MSB _u(1) +#define OTP_SW_LOCK38_SEC_LSB _u(0) +#define OTP_SW_LOCK38_SEC_ACCESS "RW" +#define OTP_SW_LOCK38_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK38_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK38_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK39 +// Description : Software lock register for page 39. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK39_OFFSET _u(0x0000009c) +#define OTP_SW_LOCK39_BITS _u(0x0000000f) +#define OTP_SW_LOCK39_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK39_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK39_NSEC_RESET "-" +#define OTP_SW_LOCK39_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK39_NSEC_MSB _u(3) +#define OTP_SW_LOCK39_NSEC_LSB _u(2) +#define OTP_SW_LOCK39_NSEC_ACCESS "RW" +#define OTP_SW_LOCK39_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK39_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK39_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK39_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK39_SEC_RESET "-" +#define OTP_SW_LOCK39_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK39_SEC_MSB _u(1) +#define OTP_SW_LOCK39_SEC_LSB _u(0) +#define OTP_SW_LOCK39_SEC_ACCESS "RW" +#define OTP_SW_LOCK39_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK39_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK39_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK40 +// Description : Software lock register for page 40. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK40_OFFSET _u(0x000000a0) +#define OTP_SW_LOCK40_BITS _u(0x0000000f) +#define OTP_SW_LOCK40_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK40_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK40_NSEC_RESET "-" +#define OTP_SW_LOCK40_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK40_NSEC_MSB _u(3) +#define OTP_SW_LOCK40_NSEC_LSB _u(2) +#define OTP_SW_LOCK40_NSEC_ACCESS "RW" +#define OTP_SW_LOCK40_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK40_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK40_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK40_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK40_SEC_RESET "-" +#define OTP_SW_LOCK40_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK40_SEC_MSB _u(1) +#define OTP_SW_LOCK40_SEC_LSB _u(0) +#define OTP_SW_LOCK40_SEC_ACCESS "RW" +#define OTP_SW_LOCK40_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK40_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK40_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK41 +// Description : Software lock register for page 41. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK41_OFFSET _u(0x000000a4) +#define OTP_SW_LOCK41_BITS _u(0x0000000f) +#define OTP_SW_LOCK41_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK41_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK41_NSEC_RESET "-" +#define OTP_SW_LOCK41_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK41_NSEC_MSB _u(3) +#define OTP_SW_LOCK41_NSEC_LSB _u(2) +#define OTP_SW_LOCK41_NSEC_ACCESS "RW" +#define OTP_SW_LOCK41_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK41_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK41_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK41_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK41_SEC_RESET "-" +#define OTP_SW_LOCK41_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK41_SEC_MSB _u(1) +#define OTP_SW_LOCK41_SEC_LSB _u(0) +#define OTP_SW_LOCK41_SEC_ACCESS "RW" +#define OTP_SW_LOCK41_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK41_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK41_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK42 +// Description : Software lock register for page 42. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK42_OFFSET _u(0x000000a8) +#define OTP_SW_LOCK42_BITS _u(0x0000000f) +#define OTP_SW_LOCK42_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK42_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK42_NSEC_RESET "-" +#define OTP_SW_LOCK42_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK42_NSEC_MSB _u(3) +#define OTP_SW_LOCK42_NSEC_LSB _u(2) +#define OTP_SW_LOCK42_NSEC_ACCESS "RW" +#define OTP_SW_LOCK42_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK42_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK42_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK42_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK42_SEC_RESET "-" +#define OTP_SW_LOCK42_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK42_SEC_MSB _u(1) +#define OTP_SW_LOCK42_SEC_LSB _u(0) +#define OTP_SW_LOCK42_SEC_ACCESS "RW" +#define OTP_SW_LOCK42_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK42_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK42_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK43 +// Description : Software lock register for page 43. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK43_OFFSET _u(0x000000ac) +#define OTP_SW_LOCK43_BITS _u(0x0000000f) +#define OTP_SW_LOCK43_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK43_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK43_NSEC_RESET "-" +#define OTP_SW_LOCK43_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK43_NSEC_MSB _u(3) +#define OTP_SW_LOCK43_NSEC_LSB _u(2) +#define OTP_SW_LOCK43_NSEC_ACCESS "RW" +#define OTP_SW_LOCK43_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK43_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK43_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK43_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK43_SEC_RESET "-" +#define OTP_SW_LOCK43_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK43_SEC_MSB _u(1) +#define OTP_SW_LOCK43_SEC_LSB _u(0) +#define OTP_SW_LOCK43_SEC_ACCESS "RW" +#define OTP_SW_LOCK43_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK43_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK43_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK44 +// Description : Software lock register for page 44. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK44_OFFSET _u(0x000000b0) +#define OTP_SW_LOCK44_BITS _u(0x0000000f) +#define OTP_SW_LOCK44_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK44_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK44_NSEC_RESET "-" +#define OTP_SW_LOCK44_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK44_NSEC_MSB _u(3) +#define OTP_SW_LOCK44_NSEC_LSB _u(2) +#define OTP_SW_LOCK44_NSEC_ACCESS "RW" +#define OTP_SW_LOCK44_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK44_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK44_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK44_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK44_SEC_RESET "-" +#define OTP_SW_LOCK44_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK44_SEC_MSB _u(1) +#define OTP_SW_LOCK44_SEC_LSB _u(0) +#define OTP_SW_LOCK44_SEC_ACCESS "RW" +#define OTP_SW_LOCK44_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK44_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK44_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK45 +// Description : Software lock register for page 45. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK45_OFFSET _u(0x000000b4) +#define OTP_SW_LOCK45_BITS _u(0x0000000f) +#define OTP_SW_LOCK45_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK45_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK45_NSEC_RESET "-" +#define OTP_SW_LOCK45_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK45_NSEC_MSB _u(3) +#define OTP_SW_LOCK45_NSEC_LSB _u(2) +#define OTP_SW_LOCK45_NSEC_ACCESS "RW" +#define OTP_SW_LOCK45_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK45_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK45_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK45_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK45_SEC_RESET "-" +#define OTP_SW_LOCK45_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK45_SEC_MSB _u(1) +#define OTP_SW_LOCK45_SEC_LSB _u(0) +#define OTP_SW_LOCK45_SEC_ACCESS "RW" +#define OTP_SW_LOCK45_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK45_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK45_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK46 +// Description : Software lock register for page 46. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK46_OFFSET _u(0x000000b8) +#define OTP_SW_LOCK46_BITS _u(0x0000000f) +#define OTP_SW_LOCK46_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK46_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK46_NSEC_RESET "-" +#define OTP_SW_LOCK46_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK46_NSEC_MSB _u(3) +#define OTP_SW_LOCK46_NSEC_LSB _u(2) +#define OTP_SW_LOCK46_NSEC_ACCESS "RW" +#define OTP_SW_LOCK46_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK46_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK46_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK46_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK46_SEC_RESET "-" +#define OTP_SW_LOCK46_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK46_SEC_MSB _u(1) +#define OTP_SW_LOCK46_SEC_LSB _u(0) +#define OTP_SW_LOCK46_SEC_ACCESS "RW" +#define OTP_SW_LOCK46_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK46_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK46_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK47 +// Description : Software lock register for page 47. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK47_OFFSET _u(0x000000bc) +#define OTP_SW_LOCK47_BITS _u(0x0000000f) +#define OTP_SW_LOCK47_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK47_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK47_NSEC_RESET "-" +#define OTP_SW_LOCK47_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK47_NSEC_MSB _u(3) +#define OTP_SW_LOCK47_NSEC_LSB _u(2) +#define OTP_SW_LOCK47_NSEC_ACCESS "RW" +#define OTP_SW_LOCK47_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK47_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK47_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK47_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK47_SEC_RESET "-" +#define OTP_SW_LOCK47_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK47_SEC_MSB _u(1) +#define OTP_SW_LOCK47_SEC_LSB _u(0) +#define OTP_SW_LOCK47_SEC_ACCESS "RW" +#define OTP_SW_LOCK47_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK47_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK47_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK48 +// Description : Software lock register for page 48. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK48_OFFSET _u(0x000000c0) +#define OTP_SW_LOCK48_BITS _u(0x0000000f) +#define OTP_SW_LOCK48_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK48_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK48_NSEC_RESET "-" +#define OTP_SW_LOCK48_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK48_NSEC_MSB _u(3) +#define OTP_SW_LOCK48_NSEC_LSB _u(2) +#define OTP_SW_LOCK48_NSEC_ACCESS "RW" +#define OTP_SW_LOCK48_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK48_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK48_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK48_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK48_SEC_RESET "-" +#define OTP_SW_LOCK48_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK48_SEC_MSB _u(1) +#define OTP_SW_LOCK48_SEC_LSB _u(0) +#define OTP_SW_LOCK48_SEC_ACCESS "RW" +#define OTP_SW_LOCK48_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK48_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK48_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK49 +// Description : Software lock register for page 49. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK49_OFFSET _u(0x000000c4) +#define OTP_SW_LOCK49_BITS _u(0x0000000f) +#define OTP_SW_LOCK49_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK49_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK49_NSEC_RESET "-" +#define OTP_SW_LOCK49_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK49_NSEC_MSB _u(3) +#define OTP_SW_LOCK49_NSEC_LSB _u(2) +#define OTP_SW_LOCK49_NSEC_ACCESS "RW" +#define OTP_SW_LOCK49_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK49_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK49_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK49_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK49_SEC_RESET "-" +#define OTP_SW_LOCK49_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK49_SEC_MSB _u(1) +#define OTP_SW_LOCK49_SEC_LSB _u(0) +#define OTP_SW_LOCK49_SEC_ACCESS "RW" +#define OTP_SW_LOCK49_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK49_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK49_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK50 +// Description : Software lock register for page 50. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK50_OFFSET _u(0x000000c8) +#define OTP_SW_LOCK50_BITS _u(0x0000000f) +#define OTP_SW_LOCK50_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK50_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK50_NSEC_RESET "-" +#define OTP_SW_LOCK50_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK50_NSEC_MSB _u(3) +#define OTP_SW_LOCK50_NSEC_LSB _u(2) +#define OTP_SW_LOCK50_NSEC_ACCESS "RW" +#define OTP_SW_LOCK50_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK50_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK50_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK50_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK50_SEC_RESET "-" +#define OTP_SW_LOCK50_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK50_SEC_MSB _u(1) +#define OTP_SW_LOCK50_SEC_LSB _u(0) +#define OTP_SW_LOCK50_SEC_ACCESS "RW" +#define OTP_SW_LOCK50_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK50_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK50_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK51 +// Description : Software lock register for page 51. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK51_OFFSET _u(0x000000cc) +#define OTP_SW_LOCK51_BITS _u(0x0000000f) +#define OTP_SW_LOCK51_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK51_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK51_NSEC_RESET "-" +#define OTP_SW_LOCK51_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK51_NSEC_MSB _u(3) +#define OTP_SW_LOCK51_NSEC_LSB _u(2) +#define OTP_SW_LOCK51_NSEC_ACCESS "RW" +#define OTP_SW_LOCK51_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK51_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK51_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK51_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK51_SEC_RESET "-" +#define OTP_SW_LOCK51_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK51_SEC_MSB _u(1) +#define OTP_SW_LOCK51_SEC_LSB _u(0) +#define OTP_SW_LOCK51_SEC_ACCESS "RW" +#define OTP_SW_LOCK51_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK51_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK51_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK52 +// Description : Software lock register for page 52. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK52_OFFSET _u(0x000000d0) +#define OTP_SW_LOCK52_BITS _u(0x0000000f) +#define OTP_SW_LOCK52_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK52_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK52_NSEC_RESET "-" +#define OTP_SW_LOCK52_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK52_NSEC_MSB _u(3) +#define OTP_SW_LOCK52_NSEC_LSB _u(2) +#define OTP_SW_LOCK52_NSEC_ACCESS "RW" +#define OTP_SW_LOCK52_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK52_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK52_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK52_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK52_SEC_RESET "-" +#define OTP_SW_LOCK52_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK52_SEC_MSB _u(1) +#define OTP_SW_LOCK52_SEC_LSB _u(0) +#define OTP_SW_LOCK52_SEC_ACCESS "RW" +#define OTP_SW_LOCK52_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK52_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK52_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK53 +// Description : Software lock register for page 53. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK53_OFFSET _u(0x000000d4) +#define OTP_SW_LOCK53_BITS _u(0x0000000f) +#define OTP_SW_LOCK53_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK53_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK53_NSEC_RESET "-" +#define OTP_SW_LOCK53_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK53_NSEC_MSB _u(3) +#define OTP_SW_LOCK53_NSEC_LSB _u(2) +#define OTP_SW_LOCK53_NSEC_ACCESS "RW" +#define OTP_SW_LOCK53_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK53_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK53_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK53_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK53_SEC_RESET "-" +#define OTP_SW_LOCK53_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK53_SEC_MSB _u(1) +#define OTP_SW_LOCK53_SEC_LSB _u(0) +#define OTP_SW_LOCK53_SEC_ACCESS "RW" +#define OTP_SW_LOCK53_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK53_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK53_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK54 +// Description : Software lock register for page 54. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK54_OFFSET _u(0x000000d8) +#define OTP_SW_LOCK54_BITS _u(0x0000000f) +#define OTP_SW_LOCK54_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK54_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK54_NSEC_RESET "-" +#define OTP_SW_LOCK54_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK54_NSEC_MSB _u(3) +#define OTP_SW_LOCK54_NSEC_LSB _u(2) +#define OTP_SW_LOCK54_NSEC_ACCESS "RW" +#define OTP_SW_LOCK54_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK54_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK54_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK54_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK54_SEC_RESET "-" +#define OTP_SW_LOCK54_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK54_SEC_MSB _u(1) +#define OTP_SW_LOCK54_SEC_LSB _u(0) +#define OTP_SW_LOCK54_SEC_ACCESS "RW" +#define OTP_SW_LOCK54_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK54_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK54_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK55 +// Description : Software lock register for page 55. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK55_OFFSET _u(0x000000dc) +#define OTP_SW_LOCK55_BITS _u(0x0000000f) +#define OTP_SW_LOCK55_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK55_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK55_NSEC_RESET "-" +#define OTP_SW_LOCK55_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK55_NSEC_MSB _u(3) +#define OTP_SW_LOCK55_NSEC_LSB _u(2) +#define OTP_SW_LOCK55_NSEC_ACCESS "RW" +#define OTP_SW_LOCK55_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK55_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK55_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK55_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK55_SEC_RESET "-" +#define OTP_SW_LOCK55_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK55_SEC_MSB _u(1) +#define OTP_SW_LOCK55_SEC_LSB _u(0) +#define OTP_SW_LOCK55_SEC_ACCESS "RW" +#define OTP_SW_LOCK55_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK55_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK55_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK56 +// Description : Software lock register for page 56. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK56_OFFSET _u(0x000000e0) +#define OTP_SW_LOCK56_BITS _u(0x0000000f) +#define OTP_SW_LOCK56_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK56_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK56_NSEC_RESET "-" +#define OTP_SW_LOCK56_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK56_NSEC_MSB _u(3) +#define OTP_SW_LOCK56_NSEC_LSB _u(2) +#define OTP_SW_LOCK56_NSEC_ACCESS "RW" +#define OTP_SW_LOCK56_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK56_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK56_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK56_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK56_SEC_RESET "-" +#define OTP_SW_LOCK56_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK56_SEC_MSB _u(1) +#define OTP_SW_LOCK56_SEC_LSB _u(0) +#define OTP_SW_LOCK56_SEC_ACCESS "RW" +#define OTP_SW_LOCK56_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK56_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK56_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK57 +// Description : Software lock register for page 57. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK57_OFFSET _u(0x000000e4) +#define OTP_SW_LOCK57_BITS _u(0x0000000f) +#define OTP_SW_LOCK57_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK57_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK57_NSEC_RESET "-" +#define OTP_SW_LOCK57_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK57_NSEC_MSB _u(3) +#define OTP_SW_LOCK57_NSEC_LSB _u(2) +#define OTP_SW_LOCK57_NSEC_ACCESS "RW" +#define OTP_SW_LOCK57_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK57_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK57_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK57_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK57_SEC_RESET "-" +#define OTP_SW_LOCK57_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK57_SEC_MSB _u(1) +#define OTP_SW_LOCK57_SEC_LSB _u(0) +#define OTP_SW_LOCK57_SEC_ACCESS "RW" +#define OTP_SW_LOCK57_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK57_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK57_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK58 +// Description : Software lock register for page 58. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK58_OFFSET _u(0x000000e8) +#define OTP_SW_LOCK58_BITS _u(0x0000000f) +#define OTP_SW_LOCK58_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK58_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK58_NSEC_RESET "-" +#define OTP_SW_LOCK58_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK58_NSEC_MSB _u(3) +#define OTP_SW_LOCK58_NSEC_LSB _u(2) +#define OTP_SW_LOCK58_NSEC_ACCESS "RW" +#define OTP_SW_LOCK58_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK58_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK58_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK58_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK58_SEC_RESET "-" +#define OTP_SW_LOCK58_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK58_SEC_MSB _u(1) +#define OTP_SW_LOCK58_SEC_LSB _u(0) +#define OTP_SW_LOCK58_SEC_ACCESS "RW" +#define OTP_SW_LOCK58_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK58_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK58_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK59 +// Description : Software lock register for page 59. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK59_OFFSET _u(0x000000ec) +#define OTP_SW_LOCK59_BITS _u(0x0000000f) +#define OTP_SW_LOCK59_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK59_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK59_NSEC_RESET "-" +#define OTP_SW_LOCK59_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK59_NSEC_MSB _u(3) +#define OTP_SW_LOCK59_NSEC_LSB _u(2) +#define OTP_SW_LOCK59_NSEC_ACCESS "RW" +#define OTP_SW_LOCK59_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK59_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK59_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK59_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK59_SEC_RESET "-" +#define OTP_SW_LOCK59_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK59_SEC_MSB _u(1) +#define OTP_SW_LOCK59_SEC_LSB _u(0) +#define OTP_SW_LOCK59_SEC_ACCESS "RW" +#define OTP_SW_LOCK59_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK59_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK59_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK60 +// Description : Software lock register for page 60. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK60_OFFSET _u(0x000000f0) +#define OTP_SW_LOCK60_BITS _u(0x0000000f) +#define OTP_SW_LOCK60_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK60_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK60_NSEC_RESET "-" +#define OTP_SW_LOCK60_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK60_NSEC_MSB _u(3) +#define OTP_SW_LOCK60_NSEC_LSB _u(2) +#define OTP_SW_LOCK60_NSEC_ACCESS "RW" +#define OTP_SW_LOCK60_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK60_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK60_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK60_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK60_SEC_RESET "-" +#define OTP_SW_LOCK60_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK60_SEC_MSB _u(1) +#define OTP_SW_LOCK60_SEC_LSB _u(0) +#define OTP_SW_LOCK60_SEC_ACCESS "RW" +#define OTP_SW_LOCK60_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK60_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK60_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK61 +// Description : Software lock register for page 61. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK61_OFFSET _u(0x000000f4) +#define OTP_SW_LOCK61_BITS _u(0x0000000f) +#define OTP_SW_LOCK61_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK61_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK61_NSEC_RESET "-" +#define OTP_SW_LOCK61_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK61_NSEC_MSB _u(3) +#define OTP_SW_LOCK61_NSEC_LSB _u(2) +#define OTP_SW_LOCK61_NSEC_ACCESS "RW" +#define OTP_SW_LOCK61_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK61_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK61_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK61_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK61_SEC_RESET "-" +#define OTP_SW_LOCK61_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK61_SEC_MSB _u(1) +#define OTP_SW_LOCK61_SEC_LSB _u(0) +#define OTP_SW_LOCK61_SEC_ACCESS "RW" +#define OTP_SW_LOCK61_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK61_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK61_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK62 +// Description : Software lock register for page 62. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK62_OFFSET _u(0x000000f8) +#define OTP_SW_LOCK62_BITS _u(0x0000000f) +#define OTP_SW_LOCK62_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK62_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK62_NSEC_RESET "-" +#define OTP_SW_LOCK62_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK62_NSEC_MSB _u(3) +#define OTP_SW_LOCK62_NSEC_LSB _u(2) +#define OTP_SW_LOCK62_NSEC_ACCESS "RW" +#define OTP_SW_LOCK62_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK62_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK62_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK62_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK62_SEC_RESET "-" +#define OTP_SW_LOCK62_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK62_SEC_MSB _u(1) +#define OTP_SW_LOCK62_SEC_LSB _u(0) +#define OTP_SW_LOCK62_SEC_ACCESS "RW" +#define OTP_SW_LOCK62_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK62_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK62_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK63 +// Description : Software lock register for page 63. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK63_OFFSET _u(0x000000fc) +#define OTP_SW_LOCK63_BITS _u(0x0000000f) +#define OTP_SW_LOCK63_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK63_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK63_NSEC_RESET "-" +#define OTP_SW_LOCK63_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK63_NSEC_MSB _u(3) +#define OTP_SW_LOCK63_NSEC_LSB _u(2) +#define OTP_SW_LOCK63_NSEC_ACCESS "RW" +#define OTP_SW_LOCK63_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK63_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK63_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK63_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK63_SEC_RESET "-" +#define OTP_SW_LOCK63_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK63_SEC_MSB _u(1) +#define OTP_SW_LOCK63_SEC_LSB _u(0) +#define OTP_SW_LOCK63_SEC_ACCESS "RW" +#define OTP_SW_LOCK63_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK63_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK63_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SBPI_INSTR +// Description : Dispatch instructions to the SBPI interface, used for +// programming the OTP fuses. +#define OTP_SBPI_INSTR_OFFSET _u(0x00000100) +#define OTP_SBPI_INSTR_BITS _u(0x7fffffff) +#define OTP_SBPI_INSTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_EXEC +// Description : Execute instruction +#define OTP_SBPI_INSTR_EXEC_RESET _u(0x0) +#define OTP_SBPI_INSTR_EXEC_BITS _u(0x40000000) +#define OTP_SBPI_INSTR_EXEC_MSB _u(30) +#define OTP_SBPI_INSTR_EXEC_LSB _u(30) +#define OTP_SBPI_INSTR_EXEC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_IS_WR +// Description : Payload type is write +#define OTP_SBPI_INSTR_IS_WR_RESET _u(0x0) +#define OTP_SBPI_INSTR_IS_WR_BITS _u(0x20000000) +#define OTP_SBPI_INSTR_IS_WR_MSB _u(29) +#define OTP_SBPI_INSTR_IS_WR_LSB _u(29) +#define OTP_SBPI_INSTR_IS_WR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_HAS_PAYLOAD +// Description : Instruction has payload (data to be written or to be read) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_RESET _u(0x0) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_BITS _u(0x10000000) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_MSB _u(28) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_LSB _u(28) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_PAYLOAD_SIZE_M1 +// Description : Instruction payload size in bytes minus 1 +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_RESET _u(0x0) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_BITS _u(0x0f000000) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_MSB _u(27) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_LSB _u(24) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_TARGET +// Description : Instruction target, it can be PMC (0x3a) or DAP (0x02) +#define OTP_SBPI_INSTR_TARGET_RESET _u(0x00) +#define OTP_SBPI_INSTR_TARGET_BITS _u(0x00ff0000) +#define OTP_SBPI_INSTR_TARGET_MSB _u(23) +#define OTP_SBPI_INSTR_TARGET_LSB _u(16) +#define OTP_SBPI_INSTR_TARGET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_CMD +#define OTP_SBPI_INSTR_CMD_RESET _u(0x00) +#define OTP_SBPI_INSTR_CMD_BITS _u(0x0000ff00) +#define OTP_SBPI_INSTR_CMD_MSB _u(15) +#define OTP_SBPI_INSTR_CMD_LSB _u(8) +#define OTP_SBPI_INSTR_CMD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_SHORT_WDATA +// Description : wdata to be used only when payload_size_m1=0 +#define OTP_SBPI_INSTR_SHORT_WDATA_RESET _u(0x00) +#define OTP_SBPI_INSTR_SHORT_WDATA_BITS _u(0x000000ff) +#define OTP_SBPI_INSTR_SHORT_WDATA_MSB _u(7) +#define OTP_SBPI_INSTR_SHORT_WDATA_LSB _u(0) +#define OTP_SBPI_INSTR_SHORT_WDATA_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_0 +// Description : SBPI write payload bytes 3..0 +#define OTP_SBPI_WDATA_0_OFFSET _u(0x00000104) +#define OTP_SBPI_WDATA_0_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_0_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_0_MSB _u(31) +#define OTP_SBPI_WDATA_0_LSB _u(0) +#define OTP_SBPI_WDATA_0_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_1 +// Description : SBPI write payload bytes 7..4 +#define OTP_SBPI_WDATA_1_OFFSET _u(0x00000108) +#define OTP_SBPI_WDATA_1_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_1_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_1_MSB _u(31) +#define OTP_SBPI_WDATA_1_LSB _u(0) +#define OTP_SBPI_WDATA_1_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_2 +// Description : SBPI write payload bytes 11..8 +#define OTP_SBPI_WDATA_2_OFFSET _u(0x0000010c) +#define OTP_SBPI_WDATA_2_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_2_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_2_MSB _u(31) +#define OTP_SBPI_WDATA_2_LSB _u(0) +#define OTP_SBPI_WDATA_2_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_3 +// Description : SBPI write payload bytes 15..12 +#define OTP_SBPI_WDATA_3_OFFSET _u(0x00000110) +#define OTP_SBPI_WDATA_3_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_3_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_3_MSB _u(31) +#define OTP_SBPI_WDATA_3_LSB _u(0) +#define OTP_SBPI_WDATA_3_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_RDATA_0 +// Description : Read payload bytes 3..0. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_0_OFFSET _u(0x00000114) +#define OTP_SBPI_RDATA_0_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_0_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_0_MSB _u(31) +#define OTP_SBPI_RDATA_0_LSB _u(0) +#define OTP_SBPI_RDATA_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_RDATA_1 +// Description : Read payload bytes 7..4. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_1_OFFSET _u(0x00000118) +#define OTP_SBPI_RDATA_1_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_1_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_1_MSB _u(31) +#define OTP_SBPI_RDATA_1_LSB _u(0) +#define OTP_SBPI_RDATA_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_RDATA_2 +// Description : Read payload bytes 11..8. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_2_OFFSET _u(0x0000011c) +#define OTP_SBPI_RDATA_2_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_2_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_2_MSB _u(31) +#define OTP_SBPI_RDATA_2_LSB _u(0) +#define OTP_SBPI_RDATA_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_RDATA_3 +// Description : Read payload bytes 15..12. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_3_OFFSET _u(0x00000120) +#define OTP_SBPI_RDATA_3_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_3_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_3_MSB _u(31) +#define OTP_SBPI_RDATA_3_LSB _u(0) +#define OTP_SBPI_RDATA_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_STATUS +#define OTP_SBPI_STATUS_OFFSET _u(0x00000124) +#define OTP_SBPI_STATUS_BITS _u(0x00ff1111) +#define OTP_SBPI_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_MISO +// Description : SBPI MISO (master in - slave out): response from SBPI +#define OTP_SBPI_STATUS_MISO_RESET "-" +#define OTP_SBPI_STATUS_MISO_BITS _u(0x00ff0000) +#define OTP_SBPI_STATUS_MISO_MSB _u(23) +#define OTP_SBPI_STATUS_MISO_LSB _u(16) +#define OTP_SBPI_STATUS_MISO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_FLAG +// Description : SBPI flag +#define OTP_SBPI_STATUS_FLAG_RESET "-" +#define OTP_SBPI_STATUS_FLAG_BITS _u(0x00001000) +#define OTP_SBPI_STATUS_FLAG_MSB _u(12) +#define OTP_SBPI_STATUS_FLAG_LSB _u(12) +#define OTP_SBPI_STATUS_FLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_INSTR_MISS +// Description : Last instruction missed (dropped), as the previous has not +// finished running +#define OTP_SBPI_STATUS_INSTR_MISS_RESET _u(0x0) +#define OTP_SBPI_STATUS_INSTR_MISS_BITS _u(0x00000100) +#define OTP_SBPI_STATUS_INSTR_MISS_MSB _u(8) +#define OTP_SBPI_STATUS_INSTR_MISS_LSB _u(8) +#define OTP_SBPI_STATUS_INSTR_MISS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_INSTR_DONE +// Description : Last instruction done +#define OTP_SBPI_STATUS_INSTR_DONE_RESET _u(0x0) +#define OTP_SBPI_STATUS_INSTR_DONE_BITS _u(0x00000010) +#define OTP_SBPI_STATUS_INSTR_DONE_MSB _u(4) +#define OTP_SBPI_STATUS_INSTR_DONE_LSB _u(4) +#define OTP_SBPI_STATUS_INSTR_DONE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_RDATA_VLD +// Description : Read command has returned data +#define OTP_SBPI_STATUS_RDATA_VLD_RESET _u(0x0) +#define OTP_SBPI_STATUS_RDATA_VLD_BITS _u(0x00000001) +#define OTP_SBPI_STATUS_RDATA_VLD_MSB _u(0) +#define OTP_SBPI_STATUS_RDATA_VLD_LSB _u(0) +#define OTP_SBPI_STATUS_RDATA_VLD_ACCESS "WC" +// ============================================================================= +// Register : OTP_USR +// Description : Controls for APB data read interface (USER interface) +#define OTP_USR_OFFSET _u(0x00000128) +#define OTP_USR_BITS _u(0x00000011) +#define OTP_USR_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : OTP_USR_PD +// Description : Power-down; 1 disables current reference. Must be 0 to read +// data from the OTP. +#define OTP_USR_PD_RESET _u(0x0) +#define OTP_USR_PD_BITS _u(0x00000010) +#define OTP_USR_PD_MSB _u(4) +#define OTP_USR_PD_LSB _u(4) +#define OTP_USR_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_USR_DCTRL +// Description : 1 enables USER interface; 0 disables USER interface (enables +// SBPI). +// +// This bit must be cleared before performing any SBPI access, +// such as when programming the OTP. The APB data read interface +// (USER interface) will be inaccessible during this time, and +// will return a bus error if any read is attempted. +#define OTP_USR_DCTRL_RESET _u(0x1) +#define OTP_USR_DCTRL_BITS _u(0x00000001) +#define OTP_USR_DCTRL_MSB _u(0) +#define OTP_USR_DCTRL_LSB _u(0) +#define OTP_USR_DCTRL_ACCESS "RW" +// ============================================================================= +// Register : OTP_DBG +// Description : Debug for OTP power-on state machine +#define OTP_DBG_OFFSET _u(0x0000012c) +#define OTP_DBG_BITS _u(0x000010ff) +#define OTP_DBG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_CUSTOMER_RMA_FLAG +// Description : The chip is in RMA mode +#define OTP_DBG_CUSTOMER_RMA_FLAG_RESET "-" +#define OTP_DBG_CUSTOMER_RMA_FLAG_BITS _u(0x00001000) +#define OTP_DBG_CUSTOMER_RMA_FLAG_MSB _u(12) +#define OTP_DBG_CUSTOMER_RMA_FLAG_LSB _u(12) +#define OTP_DBG_CUSTOMER_RMA_FLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_PSM_STATE +// Description : Monitor the PSM FSM's state +#define OTP_DBG_PSM_STATE_RESET "-" +#define OTP_DBG_PSM_STATE_BITS _u(0x000000f0) +#define OTP_DBG_PSM_STATE_MSB _u(7) +#define OTP_DBG_PSM_STATE_LSB _u(4) +#define OTP_DBG_PSM_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_ROSC_UP +// Description : Ring oscillator is up and running +#define OTP_DBG_ROSC_UP_RESET "-" +#define OTP_DBG_ROSC_UP_BITS _u(0x00000008) +#define OTP_DBG_ROSC_UP_MSB _u(3) +#define OTP_DBG_ROSC_UP_LSB _u(3) +#define OTP_DBG_ROSC_UP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_ROSC_UP_SEEN +// Description : Ring oscillator was seen up and running +#define OTP_DBG_ROSC_UP_SEEN_RESET _u(0x0) +#define OTP_DBG_ROSC_UP_SEEN_BITS _u(0x00000004) +#define OTP_DBG_ROSC_UP_SEEN_MSB _u(2) +#define OTP_DBG_ROSC_UP_SEEN_LSB _u(2) +#define OTP_DBG_ROSC_UP_SEEN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_BOOT_DONE +// Description : PSM boot done status flag +#define OTP_DBG_BOOT_DONE_RESET "-" +#define OTP_DBG_BOOT_DONE_BITS _u(0x00000002) +#define OTP_DBG_BOOT_DONE_MSB _u(1) +#define OTP_DBG_BOOT_DONE_LSB _u(1) +#define OTP_DBG_BOOT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_PSM_DONE +// Description : PSM done status flag +#define OTP_DBG_PSM_DONE_RESET "-" +#define OTP_DBG_PSM_DONE_BITS _u(0x00000001) +#define OTP_DBG_PSM_DONE_MSB _u(0) +#define OTP_DBG_PSM_DONE_LSB _u(0) +#define OTP_DBG_PSM_DONE_ACCESS "RO" +// ============================================================================= +// Register : OTP_BIST +// Description : During BIST, count address locations that have at least one +// leaky bit +#define OTP_BIST_OFFSET _u(0x00000134) +#define OTP_BIST_BITS _u(0x7fff1fff) +#define OTP_BIST_RESET _u(0x0fff0000) +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_FAIL +// Description : Flag if the count of address locations with at least one leaky +// bit exceeds cnt_max +#define OTP_BIST_CNT_FAIL_RESET "-" +#define OTP_BIST_CNT_FAIL_BITS _u(0x40000000) +#define OTP_BIST_CNT_FAIL_MSB _u(30) +#define OTP_BIST_CNT_FAIL_LSB _u(30) +#define OTP_BIST_CNT_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_CLR +// Description : Clear counter before use +#define OTP_BIST_CNT_CLR_RESET _u(0x0) +#define OTP_BIST_CNT_CLR_BITS _u(0x20000000) +#define OTP_BIST_CNT_CLR_MSB _u(29) +#define OTP_BIST_CNT_CLR_LSB _u(29) +#define OTP_BIST_CNT_CLR_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_ENA +// Description : Enable the counter before the BIST function is initiated +#define OTP_BIST_CNT_ENA_RESET _u(0x0) +#define OTP_BIST_CNT_ENA_BITS _u(0x10000000) +#define OTP_BIST_CNT_ENA_MSB _u(28) +#define OTP_BIST_CNT_ENA_LSB _u(28) +#define OTP_BIST_CNT_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_MAX +// Description : The cnt_fail flag will be set if the number of leaky locations +// exceeds this number +#define OTP_BIST_CNT_MAX_RESET _u(0xfff) +#define OTP_BIST_CNT_MAX_BITS _u(0x0fff0000) +#define OTP_BIST_CNT_MAX_MSB _u(27) +#define OTP_BIST_CNT_MAX_LSB _u(16) +#define OTP_BIST_CNT_MAX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT +// Description : Number of locations that have at least one leaky bit. Note: +// This count is true only if the BIST was initiated without the +// fix option. +#define OTP_BIST_CNT_RESET "-" +#define OTP_BIST_CNT_BITS _u(0x00001fff) +#define OTP_BIST_CNT_MSB _u(12) +#define OTP_BIST_CNT_LSB _u(0) +#define OTP_BIST_CNT_ACCESS "RO" +// ============================================================================= +// Register : OTP_CRT_KEY_W0 +// Description : Word 0 (bits 31..0) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W0_OFFSET _u(0x00000138) +#define OTP_CRT_KEY_W0_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W0_RESET _u(0x00000000) +#define OTP_CRT_KEY_W0_MSB _u(31) +#define OTP_CRT_KEY_W0_LSB _u(0) +#define OTP_CRT_KEY_W0_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRT_KEY_W1 +// Description : Word 1 (bits 63..32) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W1_OFFSET _u(0x0000013c) +#define OTP_CRT_KEY_W1_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W1_RESET _u(0x00000000) +#define OTP_CRT_KEY_W1_MSB _u(31) +#define OTP_CRT_KEY_W1_LSB _u(0) +#define OTP_CRT_KEY_W1_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRT_KEY_W2 +// Description : Word 2 (bits 95..64) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W2_OFFSET _u(0x00000140) +#define OTP_CRT_KEY_W2_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W2_RESET _u(0x00000000) +#define OTP_CRT_KEY_W2_MSB _u(31) +#define OTP_CRT_KEY_W2_LSB _u(0) +#define OTP_CRT_KEY_W2_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRT_KEY_W3 +// Description : Word 3 (bits 127..96) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W3_OFFSET _u(0x00000144) +#define OTP_CRT_KEY_W3_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W3_RESET _u(0x00000000) +#define OTP_CRT_KEY_W3_MSB _u(31) +#define OTP_CRT_KEY_W3_LSB _u(0) +#define OTP_CRT_KEY_W3_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRITICAL +// Description : Quickly check values of critical flags read during boot up +#define OTP_CRITICAL_OFFSET _u(0x00000148) +#define OTP_CRITICAL_BITS _u(0x0003007f) +#define OTP_CRITICAL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_RISCV_DISABLE +#define OTP_CRITICAL_RISCV_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_RISCV_DISABLE_BITS _u(0x00020000) +#define OTP_CRITICAL_RISCV_DISABLE_MSB _u(17) +#define OTP_CRITICAL_RISCV_DISABLE_LSB _u(17) +#define OTP_CRITICAL_RISCV_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_ARM_DISABLE +#define OTP_CRITICAL_ARM_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_ARM_DISABLE_BITS _u(0x00010000) +#define OTP_CRITICAL_ARM_DISABLE_MSB _u(16) +#define OTP_CRITICAL_ARM_DISABLE_LSB _u(16) +#define OTP_CRITICAL_ARM_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_GLITCH_DETECTOR_SENS +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_RESET _u(0x0) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_BITS _u(0x00000060) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_MSB _u(6) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_LSB _u(5) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_GLITCH_DETECTOR_ENABLE +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_RESET _u(0x0) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_BITS _u(0x00000010) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_MSB _u(4) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_LSB _u(4) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_DEFAULT_ARCHSEL +#define OTP_CRITICAL_DEFAULT_ARCHSEL_RESET _u(0x0) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_BITS _u(0x00000008) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_MSB _u(3) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_LSB _u(3) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_DEBUG_DISABLE +#define OTP_CRITICAL_DEBUG_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_DEBUG_DISABLE_BITS _u(0x00000004) +#define OTP_CRITICAL_DEBUG_DISABLE_MSB _u(2) +#define OTP_CRITICAL_DEBUG_DISABLE_LSB _u(2) +#define OTP_CRITICAL_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_SECURE_DEBUG_DISABLE +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_BITS _u(0x00000002) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_MSB _u(1) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_LSB _u(1) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_SECURE_BOOT_ENABLE +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_RESET _u(0x0) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_BITS _u(0x00000001) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_MSB _u(0) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_LSB _u(0) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_ACCESS "RO" +// ============================================================================= +// Register : OTP_KEY_VALID +// Description : Which keys were valid (enrolled) at boot time +#define OTP_KEY_VALID_OFFSET _u(0x0000014c) +#define OTP_KEY_VALID_BITS _u(0x000000ff) +#define OTP_KEY_VALID_RESET _u(0x00000000) +#define OTP_KEY_VALID_MSB _u(7) +#define OTP_KEY_VALID_LSB _u(0) +#define OTP_KEY_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DEBUGEN +// Description : Enable a debug feature that has been disabled. Debug features +// are disabled if one of the relevant critical boot flags is set +// in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug +// key is marked valid in OTP, and the matching key value has not +// been supplied over SWD. +// +// Specifically: +// +// - The DEBUG_DISABLE flag disables all debug features. This can +// be fully overridden by setting all bits of this register. +// +// - The SECURE_DEBUG_DISABLE flag disables secure processor +// debug. This can be fully overridden by setting the PROC0_SECURE +// and PROC1_SECURE bits of this register. +// +// - If a single debug key has been registered, and no matching +// key value has been supplied over SWD, then all debug features +// are disabled. This can be fully overridden by setting all bits +// of this register. +// +// - If both debug keys have been registered, and the Non-secure +// key's value (key 6) has been supplied over SWD, secure +// processor debug is disabled. This can be fully overridden by +// setting the PROC0_SECURE and PROC1_SECURE bits of this +// register. +// +// - If both debug keys have been registered, and the Secure key's +// value (key 5) has been supplied over SWD, then no debug +// features are disabled by the key mechanism. However, note that +// in this case debug features may still be disabled by the +// critical boot flags. +#define OTP_DEBUGEN_OFFSET _u(0x00000150) +#define OTP_DEBUGEN_BITS _u(0x0000010f) +#define OTP_DEBUGEN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_MISC +// Description : Enable other debug components. Specifically, the CTI, and the +// APB-AP used to access the RISC-V Debug Module. +// +// These components are disabled by default if either of the debug +// disable critical flags is set, or if at least one debug key has +// been enrolled and the least secure of these enrolled key values +// has not been provided over SWD. +#define OTP_DEBUGEN_MISC_RESET _u(0x0) +#define OTP_DEBUGEN_MISC_BITS _u(0x00000100) +#define OTP_DEBUGEN_MISC_MSB _u(8) +#define OTP_DEBUGEN_MISC_LSB _u(8) +#define OTP_DEBUGEN_MISC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC1_SECURE +// Description : Permit core 1's Mem-AP to generate Secure accesses, assuming it +// is enabled at all. Also enable secure debug of core 1 (SPIDEN +// and SPNIDEN). +// +// Secure debug of core 1 is disabled by default if the secure +// debug disable critical flag is set, or if at least one debug +// key has been enrolled and the most secure of these enrolled key +// values not yet provided over SWD. +#define OTP_DEBUGEN_PROC1_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_PROC1_SECURE_BITS _u(0x00000008) +#define OTP_DEBUGEN_PROC1_SECURE_MSB _u(3) +#define OTP_DEBUGEN_PROC1_SECURE_LSB _u(3) +#define OTP_DEBUGEN_PROC1_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC1 +// Description : Enable core 1's Mem-AP if it is currently disabled. +// +// The Mem-AP is disabled by default if either of the debug +// disable critical flags is set, or if at least one debug key has +// been enrolled and the least secure of these enrolled key values +// has not been provided over SWD. +#define OTP_DEBUGEN_PROC1_RESET _u(0x0) +#define OTP_DEBUGEN_PROC1_BITS _u(0x00000004) +#define OTP_DEBUGEN_PROC1_MSB _u(2) +#define OTP_DEBUGEN_PROC1_LSB _u(2) +#define OTP_DEBUGEN_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC0_SECURE +// Description : Permit core 0's Mem-AP to generate Secure accesses, assuming it +// is enabled at all. Also enable secure debug of core 0 (SPIDEN +// and SPNIDEN). +// +// Secure debug of core 0 is disabled by default if the secure +// debug disable critical flag is set, or if at least one debug +// key has been enrolled and the most secure of these enrolled key +// values not yet provided over SWD. +// +// Note also that core Mem-APs are unconditionally disabled when a +// core is switched to RISC-V mode (by setting the ARCHSEL bit and +// performing a warm reset of the core). +#define OTP_DEBUGEN_PROC0_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_PROC0_SECURE_BITS _u(0x00000002) +#define OTP_DEBUGEN_PROC0_SECURE_MSB _u(1) +#define OTP_DEBUGEN_PROC0_SECURE_LSB _u(1) +#define OTP_DEBUGEN_PROC0_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC0 +// Description : Enable core 0's Mem-AP if it is currently disabled. +// +// The Mem-AP is disabled by default if either of the debug +// disable critical flags is set, or if at least one debug key has +// been enrolled and the least secure of these enrolled key values +// has not been provided over SWD. +// +// Note also that core Mem-APs are unconditionally disabled when a +// core is switched to RISC-V mode (by setting the ARCHSEL bit and +// performing a warm reset of the core). +#define OTP_DEBUGEN_PROC0_RESET _u(0x0) +#define OTP_DEBUGEN_PROC0_BITS _u(0x00000001) +#define OTP_DEBUGEN_PROC0_MSB _u(0) +#define OTP_DEBUGEN_PROC0_LSB _u(0) +#define OTP_DEBUGEN_PROC0_ACCESS "RW" +// ============================================================================= +// Register : OTP_DEBUGEN_LOCK +// Description : Write 1s to lock corresponding bits in DEBUGEN. This register +// is reset by the processor cold reset. +#define OTP_DEBUGEN_LOCK_OFFSET _u(0x00000154) +#define OTP_DEBUGEN_LOCK_BITS _u(0x0000010f) +#define OTP_DEBUGEN_LOCK_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_MISC +// Description : Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once +// set. +#define OTP_DEBUGEN_LOCK_MISC_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_MISC_BITS _u(0x00000100) +#define OTP_DEBUGEN_LOCK_MISC_MSB _u(8) +#define OTP_DEBUGEN_LOCK_MISC_LSB _u(8) +#define OTP_DEBUGEN_LOCK_MISC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC1_SECURE +// Description : Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be +// cleared once set. +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_BITS _u(0x00000008) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_MSB _u(3) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_LSB _u(3) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC1 +// Description : Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once +// set. +#define OTP_DEBUGEN_LOCK_PROC1_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC1_BITS _u(0x00000004) +#define OTP_DEBUGEN_LOCK_PROC1_MSB _u(2) +#define OTP_DEBUGEN_LOCK_PROC1_LSB _u(2) +#define OTP_DEBUGEN_LOCK_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC0_SECURE +// Description : Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be +// cleared once set. +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_BITS _u(0x00000002) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_MSB _u(1) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_LSB _u(1) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC0 +// Description : Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once +// set. +#define OTP_DEBUGEN_LOCK_PROC0_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC0_BITS _u(0x00000001) +#define OTP_DEBUGEN_LOCK_PROC0_MSB _u(0) +#define OTP_DEBUGEN_LOCK_PROC0_LSB _u(0) +#define OTP_DEBUGEN_LOCK_PROC0_ACCESS "RW" +// ============================================================================= +// Register : OTP_ARCHSEL +// Description : Architecture select (Arm/RISC-V). The default and allowable +// values of this register are constrained by the critical boot +// flags. +// +// This register is reset by the earliest reset in the switched +// core power domain (before a processor cold reset). +// +// Cores sample their architecture select signal on a warm reset. +// The source of the warm reset could be the system power-up state +// machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V +// hartresetreq. +// +// Note that when an Arm core is deselected, its cold reset domain +// is also held in reset, since in particular the SYSRESETREQ bit +// becomes inaccessible once the core is deselected. Note also the +// RISC-V cores do not have a cold reset domain, since their +// corresponding controls are located in the Debug Module. +#define OTP_ARCHSEL_OFFSET _u(0x00000158) +#define OTP_ARCHSEL_BITS _u(0x00000003) +#define OTP_ARCHSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_CORE1 +// Description : Select architecture for core 1. +// 0x0 -> Switch core 1 to Arm (Cortex-M33) +// 0x1 -> Switch core 1 to RISC-V (Hazard3) +#define OTP_ARCHSEL_CORE1_RESET _u(0x0) +#define OTP_ARCHSEL_CORE1_BITS _u(0x00000002) +#define OTP_ARCHSEL_CORE1_MSB _u(1) +#define OTP_ARCHSEL_CORE1_LSB _u(1) +#define OTP_ARCHSEL_CORE1_ACCESS "RW" +#define OTP_ARCHSEL_CORE1_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_CORE1_VALUE_RISCV _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_CORE0 +// Description : Select architecture for core 0. +// 0x0 -> Switch core 0 to Arm (Cortex-M33) +// 0x1 -> Switch core 0 to RISC-V (Hazard3) +#define OTP_ARCHSEL_CORE0_RESET _u(0x0) +#define OTP_ARCHSEL_CORE0_BITS _u(0x00000001) +#define OTP_ARCHSEL_CORE0_MSB _u(0) +#define OTP_ARCHSEL_CORE0_LSB _u(0) +#define OTP_ARCHSEL_CORE0_ACCESS "RW" +#define OTP_ARCHSEL_CORE0_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_CORE0_VALUE_RISCV _u(0x1) +// ============================================================================= +// Register : OTP_ARCHSEL_STATUS +// Description : Get the current architecture select state of each core. Cores +// sample the current value of the ARCHSEL register when their +// warm reset is released, at which point the corresponding bit in +// this register will also update. +#define OTP_ARCHSEL_STATUS_OFFSET _u(0x0000015c) +#define OTP_ARCHSEL_STATUS_BITS _u(0x00000003) +#define OTP_ARCHSEL_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_STATUS_CORE1 +// Description : Current architecture for core 0. Updated on processor warm +// reset. +// 0x0 -> Core 1 is currently Arm (Cortex-M33) +// 0x1 -> Core 1 is currently RISC-V (Hazard3) +#define OTP_ARCHSEL_STATUS_CORE1_RESET _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE1_BITS _u(0x00000002) +#define OTP_ARCHSEL_STATUS_CORE1_MSB _u(1) +#define OTP_ARCHSEL_STATUS_CORE1_LSB _u(1) +#define OTP_ARCHSEL_STATUS_CORE1_ACCESS "RO" +#define OTP_ARCHSEL_STATUS_CORE1_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE1_VALUE_RISCV _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_STATUS_CORE0 +// Description : Current architecture for core 0. Updated on processor warm +// reset. +// 0x0 -> Core 0 is currently Arm (Cortex-M33) +// 0x1 -> Core 0 is currently RISC-V (Hazard3) +#define OTP_ARCHSEL_STATUS_CORE0_RESET _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE0_BITS _u(0x00000001) +#define OTP_ARCHSEL_STATUS_CORE0_MSB _u(0) +#define OTP_ARCHSEL_STATUS_CORE0_LSB _u(0) +#define OTP_ARCHSEL_STATUS_CORE0_ACCESS "RO" +#define OTP_ARCHSEL_STATUS_CORE0_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE0_VALUE_RISCV _u(0x1) +// ============================================================================= +// Register : OTP_BOOTDIS +// Description : Tell the bootrom to ignore scratch register boot vectors (both +// power manager and watchdog) on the next power up. +// +// If an early boot stage has soft-locked some OTP pages in order +// to protect their contents from later stages, there is a risk +// that Secure code running at a later stage can unlock the pages +// by performing a watchdog reset that resets the OTP. +// +// This register can be used to ensure that the bootloader runs as +// normal on the next power up, preventing Secure code at a later +// stage from accessing OTP in its unlocked state. +// +// Should be used in conjunction with the power manager BOOTDIS +// register. +#define OTP_BOOTDIS_OFFSET _u(0x00000160) +#define OTP_BOOTDIS_BITS _u(0x00000003) +#define OTP_BOOTDIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_BOOTDIS_NEXT +// Description : This flag always ORs writes into its current contents. It can +// be set but not cleared by software. +// +// The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the +// core is powered down. Simultaneously, the BOOTDIS_NEXT bit is +// cleared. Setting this bit means that the boot scratch registers +// will be ignored following the next core power down. +// +// This flag should be set by an early boot stage that has soft- +// locked OTP pages, to prevent later stages from unlocking it via +// watchdog reset. +#define OTP_BOOTDIS_NEXT_RESET _u(0x0) +#define OTP_BOOTDIS_NEXT_BITS _u(0x00000002) +#define OTP_BOOTDIS_NEXT_MSB _u(1) +#define OTP_BOOTDIS_NEXT_LSB _u(1) +#define OTP_BOOTDIS_NEXT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_BOOTDIS_NOW +// Description : When the core is powered down, the current value of +// BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is +// cleared. +// +// The bootrom checks this flag before reading the boot scratch +// registers. If it is set, the bootrom clears it, and ignores the +// BOOT registers. This prevents Secure software from diverting +// the boot path before a bootloader has had the chance to soft +// lock OTP pages containing sensitive data. +#define OTP_BOOTDIS_NOW_RESET _u(0x0) +#define OTP_BOOTDIS_NOW_BITS _u(0x00000001) +#define OTP_BOOTDIS_NOW_MSB _u(0) +#define OTP_BOOTDIS_NOW_LSB _u(0) +#define OTP_BOOTDIS_NOW_ACCESS "WC" +// ============================================================================= +// Register : OTP_INTR +// Description : Raw Interrupts +#define OTP_INTR_OFFSET _u(0x00000164) +#define OTP_INTR_BITS _u(0x0000001f) +#define OTP_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_APB_RD_NSEC_FAIL +#define OTP_INTR_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTR_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTR_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTR_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTR_APB_RD_NSEC_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_APB_RD_SEC_FAIL +#define OTP_INTR_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTR_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTR_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTR_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTR_APB_RD_SEC_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_APB_DCTRL_FAIL +#define OTP_INTR_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTR_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTR_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTR_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTR_APB_DCTRL_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_SBPI_WR_FAIL +#define OTP_INTR_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTR_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTR_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTR_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTR_SBPI_WR_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_SBPI_FLAG_N +#define OTP_INTR_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTR_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTR_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTR_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTR_SBPI_FLAG_N_ACCESS "RO" +// ============================================================================= +// Register : OTP_INTE +// Description : Interrupt Enable +#define OTP_INTE_OFFSET _u(0x00000168) +#define OTP_INTE_BITS _u(0x0000001f) +#define OTP_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_APB_RD_NSEC_FAIL +#define OTP_INTE_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTE_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTE_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTE_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTE_APB_RD_NSEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_APB_RD_SEC_FAIL +#define OTP_INTE_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTE_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTE_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTE_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTE_APB_RD_SEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_APB_DCTRL_FAIL +#define OTP_INTE_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTE_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTE_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTE_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTE_APB_DCTRL_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_SBPI_WR_FAIL +#define OTP_INTE_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTE_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTE_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTE_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTE_SBPI_WR_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_SBPI_FLAG_N +#define OTP_INTE_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTE_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTE_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTE_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTE_SBPI_FLAG_N_ACCESS "RW" +// ============================================================================= +// Register : OTP_INTF +// Description : Interrupt Force +#define OTP_INTF_OFFSET _u(0x0000016c) +#define OTP_INTF_BITS _u(0x0000001f) +#define OTP_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_APB_RD_NSEC_FAIL +#define OTP_INTF_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTF_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTF_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTF_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTF_APB_RD_NSEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_APB_RD_SEC_FAIL +#define OTP_INTF_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTF_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTF_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTF_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTF_APB_RD_SEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_APB_DCTRL_FAIL +#define OTP_INTF_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTF_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTF_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTF_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTF_APB_DCTRL_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_SBPI_WR_FAIL +#define OTP_INTF_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTF_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTF_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTF_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTF_SBPI_WR_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_SBPI_FLAG_N +#define OTP_INTF_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTF_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTF_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTF_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTF_SBPI_FLAG_N_ACCESS "RW" +// ============================================================================= +// Register : OTP_INTS +// Description : Interrupt status after masking & forcing +#define OTP_INTS_OFFSET _u(0x00000170) +#define OTP_INTS_BITS _u(0x0000001f) +#define OTP_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_APB_RD_NSEC_FAIL +#define OTP_INTS_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTS_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTS_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTS_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTS_APB_RD_NSEC_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_APB_RD_SEC_FAIL +#define OTP_INTS_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTS_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTS_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTS_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTS_APB_RD_SEC_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_APB_DCTRL_FAIL +#define OTP_INTS_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTS_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTS_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTS_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTS_APB_DCTRL_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_SBPI_WR_FAIL +#define OTP_INTS_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTS_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTS_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTS_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTS_SBPI_WR_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_SBPI_FLAG_N +#define OTP_INTS_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTS_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTS_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTS_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTS_SBPI_FLAG_N_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_OTP_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/otp_data.h b/src/rp2350/hardware_regs/include/hardware/regs/otp_data.h new file mode 100644 index 000000000..57d1d47d8 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/otp_data.h @@ -0,0 +1,12373 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : OTP_DATA +// Version : 1 +// Bus type : apb +// Description : Predefined OTP data layout for RP2350 +// ============================================================================= +#ifndef _HARDWARE_REGS_OTP_DATA_H +#define _HARDWARE_REGS_OTP_DATA_H +// ============================================================================= +// Register : OTP_DATA_CHIPID0 +// Description : Bits 15:0 of public device ID. (ECC) +// +// The CHIPID0..3 rows contain a 64-bit random identifier for this +// chip, which can be read from the USB bootloader PICOBOOT +// interface or from the get_sys_info ROM API. +// +// The number of random bits makes the occurrence of twins +// exceedingly unlikely: for example, a fleet of a hundred million +// devices has a 99.97% probability of no twinned IDs. This is +// estimated to be lower than the occurrence of process errors in +// the assignment of sequential random IDs, and for practical +// purposes CHIPID may be treated as unique. +#define OTP_DATA_CHIPID0_ROW _u(0x00000000) +#define OTP_DATA_CHIPID0_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID0_RESET "-" +#define OTP_DATA_CHIPID0_WIDTH _u(16) +#define OTP_DATA_CHIPID0_MSB _u(15) +#define OTP_DATA_CHIPID0_LSB _u(0) +#define OTP_DATA_CHIPID0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CHIPID1 +// Description : Bits 31:16 of public device ID (ECC) +#define OTP_DATA_CHIPID1_ROW _u(0x00000001) +#define OTP_DATA_CHIPID1_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID1_RESET "-" +#define OTP_DATA_CHIPID1_WIDTH _u(16) +#define OTP_DATA_CHIPID1_MSB _u(15) +#define OTP_DATA_CHIPID1_LSB _u(0) +#define OTP_DATA_CHIPID1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CHIPID2 +// Description : Bits 47:32 of public device ID (ECC) +#define OTP_DATA_CHIPID2_ROW _u(0x00000002) +#define OTP_DATA_CHIPID2_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID2_RESET "-" +#define OTP_DATA_CHIPID2_WIDTH _u(16) +#define OTP_DATA_CHIPID2_MSB _u(15) +#define OTP_DATA_CHIPID2_LSB _u(0) +#define OTP_DATA_CHIPID2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CHIPID3 +// Description : Bits 63:48 of public device ID (ECC) +#define OTP_DATA_CHIPID3_ROW _u(0x00000003) +#define OTP_DATA_CHIPID3_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID3_RESET "-" +#define OTP_DATA_CHIPID3_WIDTH _u(16) +#define OTP_DATA_CHIPID3_MSB _u(15) +#define OTP_DATA_CHIPID3_LSB _u(0) +#define OTP_DATA_CHIPID3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID0 +// Description : Bits 15:0 of private per-device random number (ECC) +// +// The RANDID0..7 rows form a 128-bit random number generated +// during device test. +// +// This ID is not exposed through the USB PICOBOOT GET_INFO +// command or the ROM `get_sys_info()` API. However note that the +// USB PICOBOOT OTP access point can read the entirety of page 0, +// so this value is not meaningfully private unless the USB +// PICOBOOT interface is disabled via the +// DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. +#define OTP_DATA_RANDID0_ROW _u(0x00000004) +#define OTP_DATA_RANDID0_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID0_RESET "-" +#define OTP_DATA_RANDID0_WIDTH _u(16) +#define OTP_DATA_RANDID0_MSB _u(15) +#define OTP_DATA_RANDID0_LSB _u(0) +#define OTP_DATA_RANDID0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID1 +// Description : Bits 31:16 of private per-device random number (ECC) +#define OTP_DATA_RANDID1_ROW _u(0x00000005) +#define OTP_DATA_RANDID1_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID1_RESET "-" +#define OTP_DATA_RANDID1_WIDTH _u(16) +#define OTP_DATA_RANDID1_MSB _u(15) +#define OTP_DATA_RANDID1_LSB _u(0) +#define OTP_DATA_RANDID1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID2 +// Description : Bits 47:32 of private per-device random number (ECC) +#define OTP_DATA_RANDID2_ROW _u(0x00000006) +#define OTP_DATA_RANDID2_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID2_RESET "-" +#define OTP_DATA_RANDID2_WIDTH _u(16) +#define OTP_DATA_RANDID2_MSB _u(15) +#define OTP_DATA_RANDID2_LSB _u(0) +#define OTP_DATA_RANDID2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID3 +// Description : Bits 63:48 of private per-device random number (ECC) +#define OTP_DATA_RANDID3_ROW _u(0x00000007) +#define OTP_DATA_RANDID3_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID3_RESET "-" +#define OTP_DATA_RANDID3_WIDTH _u(16) +#define OTP_DATA_RANDID3_MSB _u(15) +#define OTP_DATA_RANDID3_LSB _u(0) +#define OTP_DATA_RANDID3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID4 +// Description : Bits 79:64 of private per-device random number (ECC) +#define OTP_DATA_RANDID4_ROW _u(0x00000008) +#define OTP_DATA_RANDID4_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID4_RESET "-" +#define OTP_DATA_RANDID4_WIDTH _u(16) +#define OTP_DATA_RANDID4_MSB _u(15) +#define OTP_DATA_RANDID4_LSB _u(0) +#define OTP_DATA_RANDID4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID5 +// Description : Bits 95:80 of private per-device random number (ECC) +#define OTP_DATA_RANDID5_ROW _u(0x00000009) +#define OTP_DATA_RANDID5_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID5_RESET "-" +#define OTP_DATA_RANDID5_WIDTH _u(16) +#define OTP_DATA_RANDID5_MSB _u(15) +#define OTP_DATA_RANDID5_LSB _u(0) +#define OTP_DATA_RANDID5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID6 +// Description : Bits 111:96 of private per-device random number (ECC) +#define OTP_DATA_RANDID6_ROW _u(0x0000000a) +#define OTP_DATA_RANDID6_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID6_RESET "-" +#define OTP_DATA_RANDID6_WIDTH _u(16) +#define OTP_DATA_RANDID6_MSB _u(15) +#define OTP_DATA_RANDID6_LSB _u(0) +#define OTP_DATA_RANDID6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID7 +// Description : Bits 127:112 of private per-device random number (ECC) +#define OTP_DATA_RANDID7_ROW _u(0x0000000b) +#define OTP_DATA_RANDID7_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID7_RESET "-" +#define OTP_DATA_RANDID7_WIDTH _u(16) +#define OTP_DATA_RANDID7_MSB _u(15) +#define OTP_DATA_RANDID7_LSB _u(0) +#define OTP_DATA_RANDID7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_ROSC_CALIB +// Description : Ring oscillator frequency in kHz, measured during manufacturing +// (ECC) +// +// This is measured at 1.1 V, at room temperature, with the ROSC +// configuration registers in their reset state. +#define OTP_DATA_ROSC_CALIB_ROW _u(0x00000010) +#define OTP_DATA_ROSC_CALIB_BITS _u(0x0000ffff) +#define OTP_DATA_ROSC_CALIB_RESET "-" +#define OTP_DATA_ROSC_CALIB_WIDTH _u(16) +#define OTP_DATA_ROSC_CALIB_MSB _u(15) +#define OTP_DATA_ROSC_CALIB_LSB _u(0) +#define OTP_DATA_ROSC_CALIB_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_LPOSC_CALIB +// Description : Low-power oscillator frequency in Hz, measured during +// manufacturing (ECC) +// +// This is measured at 1.1V, at room temperature, with the LPOSC +// trim register in its reset state. +#define OTP_DATA_LPOSC_CALIB_ROW _u(0x00000011) +#define OTP_DATA_LPOSC_CALIB_BITS _u(0x0000ffff) +#define OTP_DATA_LPOSC_CALIB_RESET "-" +#define OTP_DATA_LPOSC_CALIB_WIDTH _u(16) +#define OTP_DATA_LPOSC_CALIB_MSB _u(15) +#define OTP_DATA_LPOSC_CALIB_LSB _u(0) +#define OTP_DATA_LPOSC_CALIB_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_NUM_GPIOS +// Description : The number of main user GPIOs (bank 0). Should read 48 in the +// QFN80 package, and 30 in the QFN60 package. (ECC) +#define OTP_DATA_NUM_GPIOS_ROW _u(0x00000018) +#define OTP_DATA_NUM_GPIOS_BITS _u(0x000000ff) +#define OTP_DATA_NUM_GPIOS_RESET "-" +#define OTP_DATA_NUM_GPIOS_WIDTH _u(16) +#define OTP_DATA_NUM_GPIOS_MSB _u(7) +#define OTP_DATA_NUM_GPIOS_LSB _u(0) +#define OTP_DATA_NUM_GPIOS_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_INFO_CRC0 +// Description : Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b +// (polynomial 0x4c11db7, input reflected, output reflected, seed +// all-ones, final XOR all-ones) (ECC) +#define OTP_DATA_INFO_CRC0_ROW _u(0x00000036) +#define OTP_DATA_INFO_CRC0_BITS _u(0x0000ffff) +#define OTP_DATA_INFO_CRC0_RESET "-" +#define OTP_DATA_INFO_CRC0_WIDTH _u(16) +#define OTP_DATA_INFO_CRC0_MSB _u(15) +#define OTP_DATA_INFO_CRC0_LSB _u(0) +#define OTP_DATA_INFO_CRC0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_INFO_CRC1 +// Description : Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) +#define OTP_DATA_INFO_CRC1_ROW _u(0x00000037) +#define OTP_DATA_INFO_CRC1_BITS _u(0x0000ffff) +#define OTP_DATA_INFO_CRC1_RESET "-" +#define OTP_DATA_INFO_CRC1_WIDTH _u(16) +#define OTP_DATA_INFO_CRC1_MSB _u(15) +#define OTP_DATA_INFO_CRC1_LSB _u(0) +#define OTP_DATA_INFO_CRC1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0 +// Description : Page 0 critical boot flags (RBIT-8) +#define OTP_DATA_CRIT0_ROW _u(0x00000038) +#define OTP_DATA_CRIT0_BITS _u(0x00000003) +#define OTP_DATA_CRIT0_RESET _u(0x00000000) +#define OTP_DATA_CRIT0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT0_RISCV_DISABLE +// Description : Permanently disable RISC-V processors (Hazard3) +#define OTP_DATA_CRIT0_RISCV_DISABLE_RESET "-" +#define OTP_DATA_CRIT0_RISCV_DISABLE_BITS _u(0x00000002) +#define OTP_DATA_CRIT0_RISCV_DISABLE_MSB _u(1) +#define OTP_DATA_CRIT0_RISCV_DISABLE_LSB _u(1) +#define OTP_DATA_CRIT0_RISCV_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT0_ARM_DISABLE +// Description : Permanently disable ARM processors (Cortex-M33) +#define OTP_DATA_CRIT0_ARM_DISABLE_RESET "-" +#define OTP_DATA_CRIT0_ARM_DISABLE_BITS _u(0x00000001) +#define OTP_DATA_CRIT0_ARM_DISABLE_MSB _u(0) +#define OTP_DATA_CRIT0_ARM_DISABLE_LSB _u(0) +#define OTP_DATA_CRIT0_ARM_DISABLE_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R1 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R1_ROW _u(0x00000039) +#define OTP_DATA_CRIT0_R1_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R1_RESET "-" +#define OTP_DATA_CRIT0_R1_WIDTH _u(24) +#define OTP_DATA_CRIT0_R1_MSB _u(23) +#define OTP_DATA_CRIT0_R1_LSB _u(0) +#define OTP_DATA_CRIT0_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R2 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R2_ROW _u(0x0000003a) +#define OTP_DATA_CRIT0_R2_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R2_RESET "-" +#define OTP_DATA_CRIT0_R2_WIDTH _u(24) +#define OTP_DATA_CRIT0_R2_MSB _u(23) +#define OTP_DATA_CRIT0_R2_LSB _u(0) +#define OTP_DATA_CRIT0_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R3 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R3_ROW _u(0x0000003b) +#define OTP_DATA_CRIT0_R3_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R3_RESET "-" +#define OTP_DATA_CRIT0_R3_WIDTH _u(24) +#define OTP_DATA_CRIT0_R3_MSB _u(23) +#define OTP_DATA_CRIT0_R3_LSB _u(0) +#define OTP_DATA_CRIT0_R3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R4 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R4_ROW _u(0x0000003c) +#define OTP_DATA_CRIT0_R4_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R4_RESET "-" +#define OTP_DATA_CRIT0_R4_WIDTH _u(24) +#define OTP_DATA_CRIT0_R4_MSB _u(23) +#define OTP_DATA_CRIT0_R4_LSB _u(0) +#define OTP_DATA_CRIT0_R4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R5 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R5_ROW _u(0x0000003d) +#define OTP_DATA_CRIT0_R5_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R5_RESET "-" +#define OTP_DATA_CRIT0_R5_WIDTH _u(24) +#define OTP_DATA_CRIT0_R5_MSB _u(23) +#define OTP_DATA_CRIT0_R5_LSB _u(0) +#define OTP_DATA_CRIT0_R5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R6 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R6_ROW _u(0x0000003e) +#define OTP_DATA_CRIT0_R6_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R6_RESET "-" +#define OTP_DATA_CRIT0_R6_WIDTH _u(24) +#define OTP_DATA_CRIT0_R6_MSB _u(23) +#define OTP_DATA_CRIT0_R6_LSB _u(0) +#define OTP_DATA_CRIT0_R6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R7 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R7_ROW _u(0x0000003f) +#define OTP_DATA_CRIT0_R7_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R7_RESET "-" +#define OTP_DATA_CRIT0_R7_WIDTH _u(24) +#define OTP_DATA_CRIT0_R7_MSB _u(23) +#define OTP_DATA_CRIT0_R7_LSB _u(0) +#define OTP_DATA_CRIT0_R7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1 +// Description : Page 1 critical boot flags (RBIT-8) +#define OTP_DATA_CRIT1_ROW _u(0x00000040) +#define OTP_DATA_CRIT1_BITS _u(0x0000007f) +#define OTP_DATA_CRIT1_RESET _u(0x00000000) +#define OTP_DATA_CRIT1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS +// Description : Increase the sensitivity of the glitch detectors from their +// default. +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_RESET "-" +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_BITS _u(0x00000060) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_MSB _u(6) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_LSB _u(5) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE +// Description : Arm the glitch detectors to reset the system if an abnormal +// clock/power event is observed. +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_RESET "-" +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_BITS _u(0x00000010) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_MSB _u(4) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_LSB _u(4) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_BOOT_ARCH +// Description : Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if +// ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. +#define OTP_DATA_CRIT1_BOOT_ARCH_RESET "-" +#define OTP_DATA_CRIT1_BOOT_ARCH_BITS _u(0x00000008) +#define OTP_DATA_CRIT1_BOOT_ARCH_MSB _u(3) +#define OTP_DATA_CRIT1_BOOT_ARCH_LSB _u(3) +#define OTP_DATA_CRIT1_BOOT_ARCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_DEBUG_DISABLE +// Description : Disable all debug access +#define OTP_DATA_CRIT1_DEBUG_DISABLE_RESET "-" +#define OTP_DATA_CRIT1_DEBUG_DISABLE_BITS _u(0x00000004) +#define OTP_DATA_CRIT1_DEBUG_DISABLE_MSB _u(2) +#define OTP_DATA_CRIT1_DEBUG_DISABLE_LSB _u(2) +#define OTP_DATA_CRIT1_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE +// Description : Disable Secure debug access +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_RESET "-" +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_BITS _u(0x00000002) +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_MSB _u(1) +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_LSB _u(1) +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_SECURE_BOOT_ENABLE +// Description : Enable boot signature enforcement, and permanently disable the +// RISC-V cores. +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_RESET "-" +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_BITS _u(0x00000001) +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_MSB _u(0) +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_LSB _u(0) +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R1 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R1_ROW _u(0x00000041) +#define OTP_DATA_CRIT1_R1_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R1_RESET "-" +#define OTP_DATA_CRIT1_R1_WIDTH _u(24) +#define OTP_DATA_CRIT1_R1_MSB _u(23) +#define OTP_DATA_CRIT1_R1_LSB _u(0) +#define OTP_DATA_CRIT1_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R2 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R2_ROW _u(0x00000042) +#define OTP_DATA_CRIT1_R2_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R2_RESET "-" +#define OTP_DATA_CRIT1_R2_WIDTH _u(24) +#define OTP_DATA_CRIT1_R2_MSB _u(23) +#define OTP_DATA_CRIT1_R2_LSB _u(0) +#define OTP_DATA_CRIT1_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R3 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R3_ROW _u(0x00000043) +#define OTP_DATA_CRIT1_R3_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R3_RESET "-" +#define OTP_DATA_CRIT1_R3_WIDTH _u(24) +#define OTP_DATA_CRIT1_R3_MSB _u(23) +#define OTP_DATA_CRIT1_R3_LSB _u(0) +#define OTP_DATA_CRIT1_R3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R4 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R4_ROW _u(0x00000044) +#define OTP_DATA_CRIT1_R4_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R4_RESET "-" +#define OTP_DATA_CRIT1_R4_WIDTH _u(24) +#define OTP_DATA_CRIT1_R4_MSB _u(23) +#define OTP_DATA_CRIT1_R4_LSB _u(0) +#define OTP_DATA_CRIT1_R4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R5 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R5_ROW _u(0x00000045) +#define OTP_DATA_CRIT1_R5_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R5_RESET "-" +#define OTP_DATA_CRIT1_R5_WIDTH _u(24) +#define OTP_DATA_CRIT1_R5_MSB _u(23) +#define OTP_DATA_CRIT1_R5_LSB _u(0) +#define OTP_DATA_CRIT1_R5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R6 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R6_ROW _u(0x00000046) +#define OTP_DATA_CRIT1_R6_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R6_RESET "-" +#define OTP_DATA_CRIT1_R6_WIDTH _u(24) +#define OTP_DATA_CRIT1_R6_MSB _u(23) +#define OTP_DATA_CRIT1_R6_LSB _u(0) +#define OTP_DATA_CRIT1_R6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R7 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R7_ROW _u(0x00000047) +#define OTP_DATA_CRIT1_R7_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R7_RESET "-" +#define OTP_DATA_CRIT1_R7_WIDTH _u(24) +#define OTP_DATA_CRIT1_R7_MSB _u(23) +#define OTP_DATA_CRIT1_R7_LSB _u(0) +#define OTP_DATA_CRIT1_R7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS0 +// Description : Disable/Enable boot paths/features in the RP2350 mask ROM. +// Disables always supersede enables. Enables are provided where +// there are other configurations in OTP that must be valid. +// (RBIT-3) +#define OTP_DATA_BOOT_FLAGS0_ROW _u(0x00000048) +#define OTP_DATA_BOOT_FLAGS0_BITS _u(0x003fffff) +#define OTP_DATA_BOOT_FLAGS0_RESET _u(0x00000000) +#define OTP_DATA_BOOT_FLAGS0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_BITS _u(0x00200000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_MSB _u(21) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_LSB _u(21) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY +// Description : Disable all access to XIP after entering an SRAM binary. +// +// Note that this will cause bootrom APIs that access XIP to fail, +// including APIs that interact with the partition table. +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_BITS _u(0x00100000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_MSB _u(20) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_LSB _u(20) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_BITS _u(0x00080000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_MSB _u(19) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_LSB _u(19) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_BITS _u(0x00040000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_MSB _u(18) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_LSB _u(18) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_BITS _u(0x00020000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_MSB _u(17) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_LSB _u(17) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_BITS _u(0x00010000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_MSB _u(16) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_LSB _u(16) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_BITS _u(0x00008000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_MSB _u(15) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_LSB _u(15) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT +// Description : Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN +// will be loaded, starting from OTPBOOT_SRC, into the SRAM +// location specified by OTPBOOT_DST1 and OTPBOOT_DST0. +// +// The loaded program image is stored with ECC, 16 bits per row, +// and must contain a valid IMAGE_DEF. Do not set this bit without +// first programming an image into OTP and configuring +// OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. +// +// Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of +// OTP rows. Equivalently, the image must be a multiple of 32 bits +// in size, and must start at a 32-bit-aligned address in the ECC +// read data address window. +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_BITS _u(0x00004000) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_MSB _u(14) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_LSB _u(14) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT +// Description : Takes precedence over ENABLE_OTP_BOOT. +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_BITS _u(0x00002000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_MSB _u(13) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_LSB _u(13) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_BITS _u(0x00001000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_MSB _u(12) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_LSB _u(12) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED +// Description : Require binaries to have a rollback version. Set automatically +// the first time a binary with a rollback version is booted. +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_BITS _u(0x00000800) +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_MSB _u(11) +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_LSB _u(11) +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE +// Description : Require a partition table to be hashed (if not signed) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_BITS _u(0x00000400) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_MSB _u(10) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_LSB _u(10) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE +// Description : Require a partition table to be signed +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_BITS _u(0x00000200) +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_MSB _u(9) +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_LSB _u(9) +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH +// Description : Disable auto-switch of CPU architecture on boot when the (only) +// binary to be booted is for the other Arm/RISC-V architecture +// and both architectures are enabled +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_BITS _u(0x00000100) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_MSB _u(8) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_LSB _u(8) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY +// Description : Restrict flash boot path to use of a single binary at the start +// of flash +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_BITS _u(0x00000080) +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_MSB _u(7) +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_LSB _u(7) +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE +// Description : Override the limit for default flash metadata scanning. +// +// The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure +// FLASH_PARTITION_SLOT_SIZE is valid before setting this bit +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_BITS _u(0x00000040) +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_MSB _u(6) +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_LSB _u(6) +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE +// Description : Mark FLASH_DEVINFO as containing valid, ECC'd data which +// describes external flash devices. +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_BITS _u(0x00000020) +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_MSB _u(5) +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_LSB _u(5) +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV +// Description : Enable quartering of ROSC divisor during signature check, to +// reduce secure boot time +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_BITS _u(0x00000010) +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_MSB _u(4) +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_LSB _u(4) +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8 +// Description : If 1, configure the QSPI pads for 1.8 V operation when +// accessing flash for the first time from the bootrom, using the +// VOLTAGE_SELECT register for the QSPI pads bank. This slightly +// improves the input timing of the pads at low voltages, but does +// not affect their output characteristics. +// +// If 0, leave VOLTAGE_SELECT in its reset state (suitable for +// operation at and above 2.5 V) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_BITS _u(0x00000008) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_MSB _u(3) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_LSB _u(3) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG +// Description : Enable loading of the non-default XOSC and PLL configuration +// before entering BOOTSEL mode. +// +// Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly +// programmed before setting this bit. +// +// If this bit is set, user software may use the contents of +// BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based +// on the fixed USB boot frequency of 48 MHz. +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_BITS _u(0x00000004) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_MSB _u(2) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_LSB _u(2) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED +// Description : Enable bootloader activity LED. If set, bootsel_led_cfg is +// assumed to be valid +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_BITS _u(0x00000002) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_MSB _u(1) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_LSB _u(1) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2 +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_BITS _u(0x00000001) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_MSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS0_R1 +// Description : Redundant copy of BOOT_FLAGS0 +#define OTP_DATA_BOOT_FLAGS0_R1_ROW _u(0x00000049) +#define OTP_DATA_BOOT_FLAGS0_R1_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS0_R1_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_R1_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS0_R1_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS0_R1_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS0_R2 +// Description : Redundant copy of BOOT_FLAGS0 +#define OTP_DATA_BOOT_FLAGS0_R2_ROW _u(0x0000004a) +#define OTP_DATA_BOOT_FLAGS0_R2_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS0_R2_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_R2_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS0_R2_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS0_R2_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS1 +// Description : Disable/Enable boot paths/features in the RP2350 mask ROM. +// Disables always supersede enables. Enables are provided where +// there are other configurations in OTP that must be valid. +// (RBIT-3) +#define OTP_DATA_BOOT_FLAGS1_ROW _u(0x0000004b) +#define OTP_DATA_BOOT_FLAGS1_BITS _u(0x000f0f0f) +#define OTP_DATA_BOOT_FLAGS1_RESET _u(0x00000000) +#define OTP_DATA_BOOT_FLAGS1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP +// Description : Enable entering BOOTSEL mode via double-tap of the RUN/RSTn +// pin. Adds a significant delay to boot time, as configured by +// DOUBLE_TAP_DELAY. +// +// This functions by waiting at startup (i.e. following a reset) +// to see if a second reset is applied soon afterward. The second +// reset is detected by the bootrom with help of the +// POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the +// external reset pin, and the bootrom enters BOOTSEL mode +// (NSBOOT) to await further instruction over USB or UART. +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_BITS _u(0x00080000) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_MSB _u(19) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_LSB _u(19) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY +// Description : Adjust how long to wait for a second reset when double tap +// BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 +// milliseconds, and each unit of this field adds an additional 50 +// milliseconds. +// +// For example, settings this field to its maximum value of 7 will +// cause the chip to wait for 400 milliseconds at boot to check +// for a second reset which requests entry to BOOTSEL mode. +// +// 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate +// value. +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_BITS _u(0x00070000) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_MSB _u(18) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_LSB _u(16) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_KEY_INVALID +// Description : Mark a boot key as invalid, or prevent it from ever becoming +// valid. The bootrom will ignore any boot key marked as invalid +// during secure boot signature checks. +// +// Each bit in this field corresponds to one of the four 256-bit +// boot key hashes that may be stored in page 2 of the OTP. +// +// When provisioning boot keys, it's recommended to mark any boot +// key slots you don't intend to use as KEY_INVALID, so that +// spurious keys can not be installed at a later time. +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_BITS _u(0x00000f00) +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_MSB _u(11) +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_LSB _u(8) +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_KEY_VALID +// Description : Mark each of the possible boot keys as valid. The bootrom will +// check signatures against all valid boot keys, and ignore +// invalid boot keys. +// +// Each bit in this field corresponds to one of the four 256-bit +// boot key hashes that may be stored in page 2 of the OTP. +// +// A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit +// is set. Boot keys are considered valid only when KEY_VALID is +// set and KEY_INVALID is clear. +// +// Do not mark a boot key as KEY_VALID if it does not contain a +// valid SHA-256 hash of your secp256k1 public key. Verify keys +// after programming, before setting the KEY_VALID bits -- a boot +// key with uncorrectable ECC faults will render your device +// unbootable if secure boot is enabled. +// +// Do not enable secure boot without first installing a valid key. +// This will render your device unbootable. +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_BITS _u(0x0000000f) +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_MSB _u(3) +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS1_R1 +// Description : Redundant copy of BOOT_FLAGS1 +#define OTP_DATA_BOOT_FLAGS1_R1_ROW _u(0x0000004c) +#define OTP_DATA_BOOT_FLAGS1_R1_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS1_R1_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_R1_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS1_R1_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS1_R1_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS1_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS1_R2 +// Description : Redundant copy of BOOT_FLAGS1 +#define OTP_DATA_BOOT_FLAGS1_R2_ROW _u(0x0000004d) +#define OTP_DATA_BOOT_FLAGS1_R2_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS1_R2_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_R2_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS1_R2_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS1_R2_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS1_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION0 +// Description : Default boot version thermometer counter, bits 23:0 (RBIT-3) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_ROW _u(0x0000004e) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION0_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION0_R1 +// Description : Redundant copy of DEFAULT_BOOT_VERSION0 +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_ROW _u(0x0000004f) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION0_R2 +// Description : Redundant copy of DEFAULT_BOOT_VERSION0 +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_ROW _u(0x00000050) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION1 +// Description : Default boot version thermometer counter, bits 47:24 (RBIT-3) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_ROW _u(0x00000051) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION1_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION1_R1 +// Description : Redundant copy of DEFAULT_BOOT_VERSION1 +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_ROW _u(0x00000052) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION1_R2 +// Description : Redundant copy of DEFAULT_BOOT_VERSION1 +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_ROW _u(0x00000053) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_FLASH_DEVINFO +// Description : Stores information about external flash device(s). (ECC) +// +// Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. +#define OTP_DATA_FLASH_DEVINFO_ROW _u(0x00000054) +#define OTP_DATA_FLASH_DEVINFO_BITS _u(0x0000ffbf) +#define OTP_DATA_FLASH_DEVINFO_RESET _u(0x00000000) +#define OTP_DATA_FLASH_DEVINFO_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_CS1_SIZE +// Description : The size of the flash/PSRAM device on chip select 1 +// (addressable at 0x11000000 through 0x11ffffff). +// +// A value of zero is decoded as a size of zero (no device). +// Nonzero values are decoded as 4kiB << CS1_SIZE. For example, +// four megabytes is encoded with a CS1_SIZE value of 10, and 16 +// megabytes is encoded with a CS1_SIZE value of 12. +// +// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of +// zero is used. +// 0x0 -> NONE +// 0x1 -> 8K +// 0x2 -> 16K +// 0x3 -> 32K +// 0x4 -> 64k +// 0x5 -> 128K +// 0x6 -> 256K +// 0x7 -> 512K +// 0x8 -> 1M +// 0x9 -> 2M +// 0xa -> 4M +// 0xb -> 8M +// 0xc -> 16M +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_BITS _u(0x0000f000) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_MSB _u(15) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_LSB _u(12) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_ACCESS "RO" +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_NONE _u(0x0) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_8K _u(0x1) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_16K _u(0x2) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_32K _u(0x3) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_64K _u(0x4) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_128K _u(0x5) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_256K _u(0x6) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_512K _u(0x7) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_1M _u(0x8) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_2M _u(0x9) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_4M _u(0xa) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_8M _u(0xb) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_16M _u(0xc) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_CS0_SIZE +// Description : The size of the flash/PSRAM device on chip select 0 +// (addressable at 0x10000000 through 0x10ffffff). +// +// A value of zero is decoded as a size of zero (no device). +// Nonzero values are decoded as 4kiB << CS0_SIZE. For example, +// four megabytes is encoded with a CS0_SIZE value of 10, and 16 +// megabytes is encoded with a CS0_SIZE value of 12. +// +// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of +// 12 (16 MiB) is used. +// 0x0 -> NONE +// 0x1 -> 8K +// 0x2 -> 16K +// 0x3 -> 32K +// 0x4 -> 64k +// 0x5 -> 128K +// 0x6 -> 256K +// 0x7 -> 512K +// 0x8 -> 1M +// 0x9 -> 2M +// 0xa -> 4M +// 0xb -> 8M +// 0xc -> 16M +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_BITS _u(0x00000f00) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_MSB _u(11) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_LSB _u(8) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_ACCESS "RO" +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_NONE _u(0x0) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_8K _u(0x1) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_16K _u(0x2) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_32K _u(0x3) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_64K _u(0x4) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_128K _u(0x5) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_256K _u(0x6) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_512K _u(0x7) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_1M _u(0x8) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_2M _u(0x9) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_4M _u(0xa) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_8M _u(0xb) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_16M _u(0xc) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED +// Description : If true, all attached devices are assumed to support (or +// ignore, in the case of PSRAM) a block erase command with a +// command prefix of D8h, an erase size of 64 kiB, and a 24-bit +// address. Almost all 25-series flash devices support this +// command. +// +// If set, the bootrom will use the D8h erase command where it is +// able, to accelerate bulk erase operations. This makes flash +// programming faster. +// +// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field +// defaults to false. +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_BITS _u(0x00000080) +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_MSB _u(7) +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_LSB _u(7) +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_CS1_GPIO +// Description : Indicate a GPIO number to be used for the secondary flash chip +// select (CS1), which selects the external QSPI device mapped at +// system addresses 0x11000000 through 0x11ffffff. There is no +// such configuration for CS0, as the primary chip select has a +// dedicated pin. +// +// On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. +// +// Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the +// bootrom will automatically configure this GPIO as a second chip +// select upon entering the flash boot path, or entering any other +// path that may use the QSPI flash interface, such as BOOTSEL +// mode (nsboot). +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_BITS _u(0x0000003f) +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_MSB _u(5) +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_LSB _u(0) +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_FLASH_PARTITION_SLOT_SIZE +// Description : Gap between partition table slot 0 and slot 1 at the start of +// flash (the default size is 4096 bytes) (ECC) Enabled by the +// OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size +// is 4096 * (value + 1) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_ROW _u(0x00000055) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_BITS _u(0x0000ffff) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_RESET "-" +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_WIDTH _u(16) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_MSB _u(15) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_LSB _u(0) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTSEL_LED_CFG +// Description : Pin configuration for LED status, used by USB bootloader. (ECC) +// Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. +#define OTP_DATA_BOOTSEL_LED_CFG_ROW _u(0x00000056) +#define OTP_DATA_BOOTSEL_LED_CFG_BITS _u(0x0000013f) +#define OTP_DATA_BOOTSEL_LED_CFG_RESET _u(0x00000000) +#define OTP_DATA_BOOTSEL_LED_CFG_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW +// Description : LED is active-low. (Default: active-high.) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_RESET "-" +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_BITS _u(0x00000100) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_MSB _u(8) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_LSB _u(8) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_LED_CFG_PIN +// Description : GPIO index to use for bootloader activity LED. +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_RESET "-" +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_BITS _u(0x0000003f) +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_MSB _u(5) +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_LSB _u(0) +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTSEL_PLL_CFG +// Description : Optional PLL configuration for BOOTSEL mode. (ECC) +// +// This should be configured to produce an exact 48 MHz based on +// the crystal oscillator frequency. User mode software may also +// use this value to calculate the expected crystal frequency +// based on an assumed 48 MHz PLL output. +// +// If no configuration is given, the crystal is assumed to be 12 +// MHz. +// +// The PLL frequency can be calculated as: +// +// PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x +// POSTDIV2) +// +// Conversely the crystal frequency can be calculated as: +// +// XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / +// FBDIV +// +// (Note the +1 on REFDIV is because the value stored in this OTP +// location is the actual divisor value minus one.) +// +// Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is +// set in BOOT_FLAGS0. That bit should be set only after this row +// and BOOTSEL_XOSC_CFG are both correctly programmed. +#define OTP_DATA_BOOTSEL_PLL_CFG_ROW _u(0x00000057) +#define OTP_DATA_BOOTSEL_PLL_CFG_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTSEL_PLL_CFG_RESET _u(0x00000000) +#define OTP_DATA_BOOTSEL_PLL_CFG_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_REFDIV +// Description : PLL reference divisor, minus one. +// +// Programming a value of 0 means a reference divisor of 1. +// Programming a value of 1 means a reference divisor of 2 (for +// exceptionally fast XIN inputs) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_BITS _u(0x00008000) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_MSB _u(15) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_LSB _u(15) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2 +// Description : PLL post-divide 2 divisor, in the range 1..7 inclusive. +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_BITS _u(0x00007000) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_MSB _u(14) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_LSB _u(12) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1 +// Description : PLL post-divide 1 divisor, in the range 1..7 inclusive. +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_BITS _u(0x00000e00) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_MSB _u(11) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_LSB _u(9) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_FBDIV +// Description : PLL feedback divisor, in the range 16..320 inclusive. +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_BITS _u(0x000001ff) +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_MSB _u(8) +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_LSB _u(0) +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTSEL_XOSC_CFG +// Description : Non-default crystal oscillator configuration for the USB +// bootloader. (ECC) +// +// These values may also be used by user code configuring the +// crystal oscillator. +// +// Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is +// set in BOOT_FLAGS0. That bit should be set only after this row +// and BOOTSEL_PLL_CFG are both correctly programmed. +#define OTP_DATA_BOOTSEL_XOSC_CFG_ROW _u(0x00000058) +#define OTP_DATA_BOOTSEL_XOSC_CFG_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RESET _u(0x00000000) +#define OTP_DATA_BOOTSEL_XOSC_CFG_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_XOSC_CFG_RANGE +// Description : Value of the XOSC_CTRL_FREQ_RANGE register. +// 0x0 -> 1_15MHZ +// 0x1 -> 10_30MHZ +// 0x2 -> 25_60MHZ +// 0x3 -> 40_100MHZ +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_RESET "-" +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_BITS _u(0x0000c000) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_MSB _u(15) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_LSB _u(14) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_ACCESS "RO" +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_1_15MHZ _u(0x0) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_10_30MHZ _u(0x1) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_25_60MHZ _u(0x2) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_40_100MHZ _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP +// Description : Value of the XOSC_STARTUP register +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_RESET "-" +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_BITS _u(0x00003fff) +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_MSB _u(13) +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_LSB _u(0) +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_BOOT_FLAGS +// Description : USB boot specific feature flags (RBIT-3) +#define OTP_DATA_USB_BOOT_FLAGS_ROW _u(0x00000059) +#define OTP_DATA_USB_BOOT_FLAGS_BITS _u(0x00c0ffff) +#define OTP_DATA_USB_BOOT_FLAGS_RESET _u(0x00000000) +#define OTP_DATA_USB_BOOT_FLAGS_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP +// Description : Swap DM/DP during USB boot, to support board layouts with +// mirrored USB routing (deliberate or accidental). +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_BITS _u(0x00800000) +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_MSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_LSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID +// Description : valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the +// USB_WHITE_LABEL struct (index 15) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_BITS _u(0x00400000) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_MSB _u(22) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_LSB _u(22) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID +// Description : valid flag for the USB_WHITE_LABEL_ADDR field +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_BITS _u(0x00008000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_MSB _u(15) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_LSB _u(15) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID +// Description : valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the +// USB_WHITE_LABEL struct (index 14) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_BITS _u(0x00004000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_MSB _u(14) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_LSB _u(14) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID +// Description : valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the +// USB_WHITE_LABEL struct (index 13) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_BITS _u(0x00002000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_MSB _u(13) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_LSB _u(13) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID +// Description : valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the +// USB_WHITE_LABEL struct (index 12) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_BITS _u(0x00001000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_MSB _u(12) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_LSB _u(12) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID +// Description : valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the +// USB_WHITE_LABEL struct (index 11) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_BITS _u(0x00000800) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_MSB _u(11) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_LSB _u(11) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID +// Description : valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the +// USB_WHITE_LABEL struct (index 10) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_BITS _u(0x00000400) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_MSB _u(10) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_LSB _u(10) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID +// Description : valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the +// USB_WHITE_LABEL struct (index 9) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_BITS _u(0x00000200) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_MSB _u(9) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_LSB _u(9) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID +// Description : valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL +// struct (index 8) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_BITS _u(0x00000100) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_MSB _u(8) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_LSB _u(8) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID +// Description : valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of +// the USB_WHITE_LABEL struct (index 7) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_BITS _u(0x00000080) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_MSB _u(7) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_LSB _u(7) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID +// Description : valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the +// USB_WHITE_LABEL struct (index 6) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_BITS _u(0x00000040) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_MSB _u(6) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_LSB _u(6) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID +// Description : valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the +// USB_WHITE_LABEL struct (index 5) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_BITS _u(0x00000020) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_MSB _u(5) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_LSB _u(5) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID +// Description : valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the +// USB_WHITE_LABEL struct (index 4) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_BITS _u(0x00000010) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_MSB _u(4) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_LSB _u(4) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID +// Description : valid flag for USB_DEVICE_LANG_ID_VALUE entry of the +// USB_WHITE_LABEL struct (index 3) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_BITS _u(0x00000008) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_MSB _u(3) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_LSB _u(3) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID +// Description : valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the +// USB_WHITE_LABEL struct (index 2) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_BITS _u(0x00000004) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_MSB _u(2) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_LSB _u(2) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID +// Description : valid flag for USB_DEVICE_PID_VALUE entry of the +// USB_WHITE_LABEL struct (index 1) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_BITS _u(0x00000002) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_MSB _u(1) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_LSB _u(1) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID +// Description : valid flag for USB_DEVICE_VID_VALUE entry of the +// USB_WHITE_LABEL struct (index 0) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_BITS _u(0x00000001) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_MSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_LSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_BOOT_FLAGS_R1 +// Description : Redundant copy of USB_BOOT_FLAGS +#define OTP_DATA_USB_BOOT_FLAGS_R1_ROW _u(0x0000005a) +#define OTP_DATA_USB_BOOT_FLAGS_R1_BITS _u(0x00ffffff) +#define OTP_DATA_USB_BOOT_FLAGS_R1_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_R1_WIDTH _u(24) +#define OTP_DATA_USB_BOOT_FLAGS_R1_MSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_R1_LSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_BOOT_FLAGS_R2 +// Description : Redundant copy of USB_BOOT_FLAGS +#define OTP_DATA_USB_BOOT_FLAGS_R2_ROW _u(0x0000005b) +#define OTP_DATA_USB_BOOT_FLAGS_R2_BITS _u(0x00ffffff) +#define OTP_DATA_USB_BOOT_FLAGS_R2_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_R2_WIDTH _u(24) +#define OTP_DATA_USB_BOOT_FLAGS_R2_MSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_R2_LSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_WHITE_LABEL_ADDR +// Description : Row index of the USB_WHITE_LABEL structure within OTP (ECC) +// +// The table has 16 rows, each of which are also ECC and marked +// valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). +// +// The entries are either _VALUEs where the 16 bit value is used +// as is, or _STRDEFs which acts as a pointers to a string value. +// +// The value stored in a _STRDEF is two separate bytes: The low +// seven bits of the first (LSB) byte indicates the number of +// characters in the string, and the top bit of the first (LSB) +// byte if set to indicate that each character in the string is +// two bytes (Unicode) versus one byte if unset. The second (MSB) +// byte represents the location of the string data, and is encoded +// as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the +// row of the start of the string is USB_WHITE_LABEL_ADDR value + +// msb_byte. +// +// In each case, the corresponding valid bit enables replacing the +// default value for the corresponding item provided by the boot +// rom. +// +// Note that Unicode _STRDEFs are only supported for +// USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and +// USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored +// if specified for other fields, and non-unicode values for these +// three items will be converted to Unicode characters by setting +// the upper 8 bits to zero. +// +// Note that if the USB_WHITE_LABEL structure or the corresponding +// strings are not readable by BOOTSEL mode based on OTP +// permissions, or if alignment requirements are not met, then the +// corresponding default values are used. +// +// The index values indicate where each field is located (row +// USB_WHITE_LABEL_ADDR value + index): +// 0x0000 -> INDEX_USB_DEVICE_VID_VALUE +// 0x0001 -> INDEX_USB_DEVICE_PID_VALUE +// 0x0002 -> INDEX_USB_DEVICE_BCD_DEVICE_VALUE +// 0x0003 -> INDEX_USB_DEVICE_LANG_ID_VALUE +// 0x0004 -> INDEX_USB_DEVICE_MANUFACTURER_STRDEF +// 0x0005 -> INDEX_USB_DEVICE_PRODUCT_STRDEF +// 0x0006 -> INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF +// 0x0007 -> INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES +// 0x0008 -> INDEX_VOLUME_LABEL_STRDEF +// 0x0009 -> INDEX_SCSI_INQUIRY_VENDOR_STRDEF +// 0x000a -> INDEX_SCSI_INQUIRY_PRODUCT_STRDEF +// 0x000b -> INDEX_SCSI_INQUIRY_VERSION_STRDEF +// 0x000c -> INDEX_INDEX_HTM_REDIRECT_URL_STRDEF +// 0x000d -> INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF +// 0x000e -> INDEX_INFO_UF2_TXT_MODEL_STRDEF +// 0x000f -> INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF +#define OTP_DATA_USB_WHITE_LABEL_ADDR_ROW _u(0x0000005c) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_BITS _u(0x0000ffff) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_RESET "-" +#define OTP_DATA_USB_WHITE_LABEL_ADDR_WIDTH _u(16) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_MSB _u(15) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_LSB _u(0) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_ACCESS "RO" +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_VID_VALUE _u(0x0000) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_PID_VALUE _u(0x0001) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_BCD_DEVICE_VALUE _u(0x0002) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_LANG_ID_VALUE _u(0x0003) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_MANUFACTURER_STRDEF _u(0x0004) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_PRODUCT_STRDEF _u(0x0005) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF _u(0x0006) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES _u(0x0007) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_VOLUME_LABEL_STRDEF _u(0x0008) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_VENDOR_STRDEF _u(0x0009) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_PRODUCT_STRDEF _u(0x000a) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_VERSION_STRDEF _u(0x000b) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INDEX_HTM_REDIRECT_URL_STRDEF _u(0x000c) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF _u(0x000d) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INFO_UF2_TXT_MODEL_STRDEF _u(0x000e) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF _u(0x000f) +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_SRC +// Description : OTP start row for the OTP boot image. (ECC) +// +// If OTP boot is enabled, the bootrom will load from this +// location into SRAM and then directly enter the loaded image. +// Note that the image must be signed if SECURE_BOOT_ENABLE is +// set. The image itself is assumed to be ECC-protected. +// +// This must be an even number. Equivalently, the OTP boot image +// must start at a word-aligned location in the ECC read data +// address window. +#define OTP_DATA_OTPBOOT_SRC_ROW _u(0x0000005e) +#define OTP_DATA_OTPBOOT_SRC_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_SRC_RESET "-" +#define OTP_DATA_OTPBOOT_SRC_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_SRC_MSB _u(15) +#define OTP_DATA_OTPBOOT_SRC_LSB _u(0) +#define OTP_DATA_OTPBOOT_SRC_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_LEN +// Description : Length in rows of the OTP boot image. (ECC) +// +// OTPBOOT_LEN must be even. The total image size must be a +// multiple of 4 bytes (32 bits). +#define OTP_DATA_OTPBOOT_LEN_ROW _u(0x0000005f) +#define OTP_DATA_OTPBOOT_LEN_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_LEN_RESET "-" +#define OTP_DATA_OTPBOOT_LEN_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_LEN_MSB _u(15) +#define OTP_DATA_OTPBOOT_LEN_LSB _u(0) +#define OTP_DATA_OTPBOOT_LEN_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_DST0 +// Description : Bits 15:0 of the OTP boot image load destination (and entry +// point). (ECC) +// +// This must be a location in main SRAM (main SRAM is addresses +// 0x20000000 through 0x20082000) and must be word-aligned. +#define OTP_DATA_OTPBOOT_DST0_ROW _u(0x00000060) +#define OTP_DATA_OTPBOOT_DST0_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_DST0_RESET "-" +#define OTP_DATA_OTPBOOT_DST0_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_DST0_MSB _u(15) +#define OTP_DATA_OTPBOOT_DST0_LSB _u(0) +#define OTP_DATA_OTPBOOT_DST0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_DST1 +// Description : Bits 31:16 of the OTP boot image load destination (and entry +// point). (ECC) +// +// This must be a location in main SRAM (main SRAM is addresses +// 0x20000000 through 0x20082000) and must be word-aligned. +#define OTP_DATA_OTPBOOT_DST1_ROW _u(0x00000061) +#define OTP_DATA_OTPBOOT_DST1_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_DST1_RESET "-" +#define OTP_DATA_OTPBOOT_DST1_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_DST1_MSB _u(15) +#define OTP_DATA_OTPBOOT_DST1_LSB _u(0) +#define OTP_DATA_OTPBOOT_DST1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_0_ROW _u(0x00000080) +#define OTP_DATA_BOOTKEY0_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_0_RESET "-" +#define OTP_DATA_BOOTKEY0_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_0_MSB _u(15) +#define OTP_DATA_BOOTKEY0_0_LSB _u(0) +#define OTP_DATA_BOOTKEY0_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_1_ROW _u(0x00000081) +#define OTP_DATA_BOOTKEY0_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_1_RESET "-" +#define OTP_DATA_BOOTKEY0_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_1_MSB _u(15) +#define OTP_DATA_BOOTKEY0_1_LSB _u(0) +#define OTP_DATA_BOOTKEY0_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_2_ROW _u(0x00000082) +#define OTP_DATA_BOOTKEY0_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_2_RESET "-" +#define OTP_DATA_BOOTKEY0_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_2_MSB _u(15) +#define OTP_DATA_BOOTKEY0_2_LSB _u(0) +#define OTP_DATA_BOOTKEY0_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_3_ROW _u(0x00000083) +#define OTP_DATA_BOOTKEY0_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_3_RESET "-" +#define OTP_DATA_BOOTKEY0_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_3_MSB _u(15) +#define OTP_DATA_BOOTKEY0_3_LSB _u(0) +#define OTP_DATA_BOOTKEY0_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_4_ROW _u(0x00000084) +#define OTP_DATA_BOOTKEY0_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_4_RESET "-" +#define OTP_DATA_BOOTKEY0_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_4_MSB _u(15) +#define OTP_DATA_BOOTKEY0_4_LSB _u(0) +#define OTP_DATA_BOOTKEY0_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_5_ROW _u(0x00000085) +#define OTP_DATA_BOOTKEY0_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_5_RESET "-" +#define OTP_DATA_BOOTKEY0_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_5_MSB _u(15) +#define OTP_DATA_BOOTKEY0_5_LSB _u(0) +#define OTP_DATA_BOOTKEY0_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_6_ROW _u(0x00000086) +#define OTP_DATA_BOOTKEY0_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_6_RESET "-" +#define OTP_DATA_BOOTKEY0_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_6_MSB _u(15) +#define OTP_DATA_BOOTKEY0_6_LSB _u(0) +#define OTP_DATA_BOOTKEY0_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_7_ROW _u(0x00000087) +#define OTP_DATA_BOOTKEY0_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_7_RESET "-" +#define OTP_DATA_BOOTKEY0_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_7_MSB _u(15) +#define OTP_DATA_BOOTKEY0_7_LSB _u(0) +#define OTP_DATA_BOOTKEY0_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_8_ROW _u(0x00000088) +#define OTP_DATA_BOOTKEY0_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_8_RESET "-" +#define OTP_DATA_BOOTKEY0_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_8_MSB _u(15) +#define OTP_DATA_BOOTKEY0_8_LSB _u(0) +#define OTP_DATA_BOOTKEY0_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_9_ROW _u(0x00000089) +#define OTP_DATA_BOOTKEY0_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_9_RESET "-" +#define OTP_DATA_BOOTKEY0_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_9_MSB _u(15) +#define OTP_DATA_BOOTKEY0_9_LSB _u(0) +#define OTP_DATA_BOOTKEY0_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_10_ROW _u(0x0000008a) +#define OTP_DATA_BOOTKEY0_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_10_RESET "-" +#define OTP_DATA_BOOTKEY0_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_10_MSB _u(15) +#define OTP_DATA_BOOTKEY0_10_LSB _u(0) +#define OTP_DATA_BOOTKEY0_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_11_ROW _u(0x0000008b) +#define OTP_DATA_BOOTKEY0_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_11_RESET "-" +#define OTP_DATA_BOOTKEY0_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_11_MSB _u(15) +#define OTP_DATA_BOOTKEY0_11_LSB _u(0) +#define OTP_DATA_BOOTKEY0_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_12_ROW _u(0x0000008c) +#define OTP_DATA_BOOTKEY0_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_12_RESET "-" +#define OTP_DATA_BOOTKEY0_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_12_MSB _u(15) +#define OTP_DATA_BOOTKEY0_12_LSB _u(0) +#define OTP_DATA_BOOTKEY0_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_13_ROW _u(0x0000008d) +#define OTP_DATA_BOOTKEY0_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_13_RESET "-" +#define OTP_DATA_BOOTKEY0_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_13_MSB _u(15) +#define OTP_DATA_BOOTKEY0_13_LSB _u(0) +#define OTP_DATA_BOOTKEY0_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_14_ROW _u(0x0000008e) +#define OTP_DATA_BOOTKEY0_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_14_RESET "-" +#define OTP_DATA_BOOTKEY0_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_14_MSB _u(15) +#define OTP_DATA_BOOTKEY0_14_LSB _u(0) +#define OTP_DATA_BOOTKEY0_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_15_ROW _u(0x0000008f) +#define OTP_DATA_BOOTKEY0_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_15_RESET "-" +#define OTP_DATA_BOOTKEY0_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_15_MSB _u(15) +#define OTP_DATA_BOOTKEY0_15_LSB _u(0) +#define OTP_DATA_BOOTKEY0_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_0_ROW _u(0x00000090) +#define OTP_DATA_BOOTKEY1_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_0_RESET "-" +#define OTP_DATA_BOOTKEY1_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_0_MSB _u(15) +#define OTP_DATA_BOOTKEY1_0_LSB _u(0) +#define OTP_DATA_BOOTKEY1_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_1_ROW _u(0x00000091) +#define OTP_DATA_BOOTKEY1_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_1_RESET "-" +#define OTP_DATA_BOOTKEY1_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_1_MSB _u(15) +#define OTP_DATA_BOOTKEY1_1_LSB _u(0) +#define OTP_DATA_BOOTKEY1_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_2_ROW _u(0x00000092) +#define OTP_DATA_BOOTKEY1_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_2_RESET "-" +#define OTP_DATA_BOOTKEY1_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_2_MSB _u(15) +#define OTP_DATA_BOOTKEY1_2_LSB _u(0) +#define OTP_DATA_BOOTKEY1_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_3_ROW _u(0x00000093) +#define OTP_DATA_BOOTKEY1_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_3_RESET "-" +#define OTP_DATA_BOOTKEY1_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_3_MSB _u(15) +#define OTP_DATA_BOOTKEY1_3_LSB _u(0) +#define OTP_DATA_BOOTKEY1_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_4_ROW _u(0x00000094) +#define OTP_DATA_BOOTKEY1_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_4_RESET "-" +#define OTP_DATA_BOOTKEY1_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_4_MSB _u(15) +#define OTP_DATA_BOOTKEY1_4_LSB _u(0) +#define OTP_DATA_BOOTKEY1_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_5_ROW _u(0x00000095) +#define OTP_DATA_BOOTKEY1_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_5_RESET "-" +#define OTP_DATA_BOOTKEY1_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_5_MSB _u(15) +#define OTP_DATA_BOOTKEY1_5_LSB _u(0) +#define OTP_DATA_BOOTKEY1_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_6_ROW _u(0x00000096) +#define OTP_DATA_BOOTKEY1_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_6_RESET "-" +#define OTP_DATA_BOOTKEY1_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_6_MSB _u(15) +#define OTP_DATA_BOOTKEY1_6_LSB _u(0) +#define OTP_DATA_BOOTKEY1_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_7_ROW _u(0x00000097) +#define OTP_DATA_BOOTKEY1_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_7_RESET "-" +#define OTP_DATA_BOOTKEY1_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_7_MSB _u(15) +#define OTP_DATA_BOOTKEY1_7_LSB _u(0) +#define OTP_DATA_BOOTKEY1_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_8_ROW _u(0x00000098) +#define OTP_DATA_BOOTKEY1_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_8_RESET "-" +#define OTP_DATA_BOOTKEY1_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_8_MSB _u(15) +#define OTP_DATA_BOOTKEY1_8_LSB _u(0) +#define OTP_DATA_BOOTKEY1_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_9_ROW _u(0x00000099) +#define OTP_DATA_BOOTKEY1_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_9_RESET "-" +#define OTP_DATA_BOOTKEY1_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_9_MSB _u(15) +#define OTP_DATA_BOOTKEY1_9_LSB _u(0) +#define OTP_DATA_BOOTKEY1_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_10_ROW _u(0x0000009a) +#define OTP_DATA_BOOTKEY1_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_10_RESET "-" +#define OTP_DATA_BOOTKEY1_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_10_MSB _u(15) +#define OTP_DATA_BOOTKEY1_10_LSB _u(0) +#define OTP_DATA_BOOTKEY1_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_11_ROW _u(0x0000009b) +#define OTP_DATA_BOOTKEY1_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_11_RESET "-" +#define OTP_DATA_BOOTKEY1_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_11_MSB _u(15) +#define OTP_DATA_BOOTKEY1_11_LSB _u(0) +#define OTP_DATA_BOOTKEY1_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_12_ROW _u(0x0000009c) +#define OTP_DATA_BOOTKEY1_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_12_RESET "-" +#define OTP_DATA_BOOTKEY1_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_12_MSB _u(15) +#define OTP_DATA_BOOTKEY1_12_LSB _u(0) +#define OTP_DATA_BOOTKEY1_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_13_ROW _u(0x0000009d) +#define OTP_DATA_BOOTKEY1_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_13_RESET "-" +#define OTP_DATA_BOOTKEY1_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_13_MSB _u(15) +#define OTP_DATA_BOOTKEY1_13_LSB _u(0) +#define OTP_DATA_BOOTKEY1_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_14_ROW _u(0x0000009e) +#define OTP_DATA_BOOTKEY1_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_14_RESET "-" +#define OTP_DATA_BOOTKEY1_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_14_MSB _u(15) +#define OTP_DATA_BOOTKEY1_14_LSB _u(0) +#define OTP_DATA_BOOTKEY1_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_15_ROW _u(0x0000009f) +#define OTP_DATA_BOOTKEY1_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_15_RESET "-" +#define OTP_DATA_BOOTKEY1_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_15_MSB _u(15) +#define OTP_DATA_BOOTKEY1_15_LSB _u(0) +#define OTP_DATA_BOOTKEY1_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_0_ROW _u(0x000000a0) +#define OTP_DATA_BOOTKEY2_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_0_RESET "-" +#define OTP_DATA_BOOTKEY2_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_0_MSB _u(15) +#define OTP_DATA_BOOTKEY2_0_LSB _u(0) +#define OTP_DATA_BOOTKEY2_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_1_ROW _u(0x000000a1) +#define OTP_DATA_BOOTKEY2_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_1_RESET "-" +#define OTP_DATA_BOOTKEY2_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_1_MSB _u(15) +#define OTP_DATA_BOOTKEY2_1_LSB _u(0) +#define OTP_DATA_BOOTKEY2_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_2_ROW _u(0x000000a2) +#define OTP_DATA_BOOTKEY2_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_2_RESET "-" +#define OTP_DATA_BOOTKEY2_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_2_MSB _u(15) +#define OTP_DATA_BOOTKEY2_2_LSB _u(0) +#define OTP_DATA_BOOTKEY2_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_3_ROW _u(0x000000a3) +#define OTP_DATA_BOOTKEY2_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_3_RESET "-" +#define OTP_DATA_BOOTKEY2_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_3_MSB _u(15) +#define OTP_DATA_BOOTKEY2_3_LSB _u(0) +#define OTP_DATA_BOOTKEY2_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_4_ROW _u(0x000000a4) +#define OTP_DATA_BOOTKEY2_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_4_RESET "-" +#define OTP_DATA_BOOTKEY2_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_4_MSB _u(15) +#define OTP_DATA_BOOTKEY2_4_LSB _u(0) +#define OTP_DATA_BOOTKEY2_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_5_ROW _u(0x000000a5) +#define OTP_DATA_BOOTKEY2_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_5_RESET "-" +#define OTP_DATA_BOOTKEY2_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_5_MSB _u(15) +#define OTP_DATA_BOOTKEY2_5_LSB _u(0) +#define OTP_DATA_BOOTKEY2_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_6_ROW _u(0x000000a6) +#define OTP_DATA_BOOTKEY2_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_6_RESET "-" +#define OTP_DATA_BOOTKEY2_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_6_MSB _u(15) +#define OTP_DATA_BOOTKEY2_6_LSB _u(0) +#define OTP_DATA_BOOTKEY2_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_7_ROW _u(0x000000a7) +#define OTP_DATA_BOOTKEY2_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_7_RESET "-" +#define OTP_DATA_BOOTKEY2_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_7_MSB _u(15) +#define OTP_DATA_BOOTKEY2_7_LSB _u(0) +#define OTP_DATA_BOOTKEY2_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_8_ROW _u(0x000000a8) +#define OTP_DATA_BOOTKEY2_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_8_RESET "-" +#define OTP_DATA_BOOTKEY2_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_8_MSB _u(15) +#define OTP_DATA_BOOTKEY2_8_LSB _u(0) +#define OTP_DATA_BOOTKEY2_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_9_ROW _u(0x000000a9) +#define OTP_DATA_BOOTKEY2_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_9_RESET "-" +#define OTP_DATA_BOOTKEY2_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_9_MSB _u(15) +#define OTP_DATA_BOOTKEY2_9_LSB _u(0) +#define OTP_DATA_BOOTKEY2_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_10_ROW _u(0x000000aa) +#define OTP_DATA_BOOTKEY2_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_10_RESET "-" +#define OTP_DATA_BOOTKEY2_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_10_MSB _u(15) +#define OTP_DATA_BOOTKEY2_10_LSB _u(0) +#define OTP_DATA_BOOTKEY2_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_11_ROW _u(0x000000ab) +#define OTP_DATA_BOOTKEY2_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_11_RESET "-" +#define OTP_DATA_BOOTKEY2_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_11_MSB _u(15) +#define OTP_DATA_BOOTKEY2_11_LSB _u(0) +#define OTP_DATA_BOOTKEY2_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_12_ROW _u(0x000000ac) +#define OTP_DATA_BOOTKEY2_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_12_RESET "-" +#define OTP_DATA_BOOTKEY2_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_12_MSB _u(15) +#define OTP_DATA_BOOTKEY2_12_LSB _u(0) +#define OTP_DATA_BOOTKEY2_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_13_ROW _u(0x000000ad) +#define OTP_DATA_BOOTKEY2_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_13_RESET "-" +#define OTP_DATA_BOOTKEY2_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_13_MSB _u(15) +#define OTP_DATA_BOOTKEY2_13_LSB _u(0) +#define OTP_DATA_BOOTKEY2_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_14_ROW _u(0x000000ae) +#define OTP_DATA_BOOTKEY2_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_14_RESET "-" +#define OTP_DATA_BOOTKEY2_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_14_MSB _u(15) +#define OTP_DATA_BOOTKEY2_14_LSB _u(0) +#define OTP_DATA_BOOTKEY2_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_15_ROW _u(0x000000af) +#define OTP_DATA_BOOTKEY2_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_15_RESET "-" +#define OTP_DATA_BOOTKEY2_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_15_MSB _u(15) +#define OTP_DATA_BOOTKEY2_15_LSB _u(0) +#define OTP_DATA_BOOTKEY2_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_0_ROW _u(0x000000b0) +#define OTP_DATA_BOOTKEY3_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_0_RESET "-" +#define OTP_DATA_BOOTKEY3_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_0_MSB _u(15) +#define OTP_DATA_BOOTKEY3_0_LSB _u(0) +#define OTP_DATA_BOOTKEY3_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_1_ROW _u(0x000000b1) +#define OTP_DATA_BOOTKEY3_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_1_RESET "-" +#define OTP_DATA_BOOTKEY3_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_1_MSB _u(15) +#define OTP_DATA_BOOTKEY3_1_LSB _u(0) +#define OTP_DATA_BOOTKEY3_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_2_ROW _u(0x000000b2) +#define OTP_DATA_BOOTKEY3_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_2_RESET "-" +#define OTP_DATA_BOOTKEY3_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_2_MSB _u(15) +#define OTP_DATA_BOOTKEY3_2_LSB _u(0) +#define OTP_DATA_BOOTKEY3_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_3_ROW _u(0x000000b3) +#define OTP_DATA_BOOTKEY3_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_3_RESET "-" +#define OTP_DATA_BOOTKEY3_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_3_MSB _u(15) +#define OTP_DATA_BOOTKEY3_3_LSB _u(0) +#define OTP_DATA_BOOTKEY3_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_4_ROW _u(0x000000b4) +#define OTP_DATA_BOOTKEY3_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_4_RESET "-" +#define OTP_DATA_BOOTKEY3_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_4_MSB _u(15) +#define OTP_DATA_BOOTKEY3_4_LSB _u(0) +#define OTP_DATA_BOOTKEY3_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_5_ROW _u(0x000000b5) +#define OTP_DATA_BOOTKEY3_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_5_RESET "-" +#define OTP_DATA_BOOTKEY3_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_5_MSB _u(15) +#define OTP_DATA_BOOTKEY3_5_LSB _u(0) +#define OTP_DATA_BOOTKEY3_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_6_ROW _u(0x000000b6) +#define OTP_DATA_BOOTKEY3_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_6_RESET "-" +#define OTP_DATA_BOOTKEY3_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_6_MSB _u(15) +#define OTP_DATA_BOOTKEY3_6_LSB _u(0) +#define OTP_DATA_BOOTKEY3_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_7_ROW _u(0x000000b7) +#define OTP_DATA_BOOTKEY3_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_7_RESET "-" +#define OTP_DATA_BOOTKEY3_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_7_MSB _u(15) +#define OTP_DATA_BOOTKEY3_7_LSB _u(0) +#define OTP_DATA_BOOTKEY3_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_8_ROW _u(0x000000b8) +#define OTP_DATA_BOOTKEY3_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_8_RESET "-" +#define OTP_DATA_BOOTKEY3_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_8_MSB _u(15) +#define OTP_DATA_BOOTKEY3_8_LSB _u(0) +#define OTP_DATA_BOOTKEY3_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_9_ROW _u(0x000000b9) +#define OTP_DATA_BOOTKEY3_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_9_RESET "-" +#define OTP_DATA_BOOTKEY3_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_9_MSB _u(15) +#define OTP_DATA_BOOTKEY3_9_LSB _u(0) +#define OTP_DATA_BOOTKEY3_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_10_ROW _u(0x000000ba) +#define OTP_DATA_BOOTKEY3_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_10_RESET "-" +#define OTP_DATA_BOOTKEY3_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_10_MSB _u(15) +#define OTP_DATA_BOOTKEY3_10_LSB _u(0) +#define OTP_DATA_BOOTKEY3_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_11_ROW _u(0x000000bb) +#define OTP_DATA_BOOTKEY3_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_11_RESET "-" +#define OTP_DATA_BOOTKEY3_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_11_MSB _u(15) +#define OTP_DATA_BOOTKEY3_11_LSB _u(0) +#define OTP_DATA_BOOTKEY3_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_12_ROW _u(0x000000bc) +#define OTP_DATA_BOOTKEY3_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_12_RESET "-" +#define OTP_DATA_BOOTKEY3_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_12_MSB _u(15) +#define OTP_DATA_BOOTKEY3_12_LSB _u(0) +#define OTP_DATA_BOOTKEY3_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_13_ROW _u(0x000000bd) +#define OTP_DATA_BOOTKEY3_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_13_RESET "-" +#define OTP_DATA_BOOTKEY3_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_13_MSB _u(15) +#define OTP_DATA_BOOTKEY3_13_LSB _u(0) +#define OTP_DATA_BOOTKEY3_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_14_ROW _u(0x000000be) +#define OTP_DATA_BOOTKEY3_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_14_RESET "-" +#define OTP_DATA_BOOTKEY3_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_14_MSB _u(15) +#define OTP_DATA_BOOTKEY3_14_LSB _u(0) +#define OTP_DATA_BOOTKEY3_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_15_ROW _u(0x000000bf) +#define OTP_DATA_BOOTKEY3_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_15_RESET "-" +#define OTP_DATA_BOOTKEY3_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_15_MSB _u(15) +#define OTP_DATA_BOOTKEY3_15_LSB _u(0) +#define OTP_DATA_BOOTKEY3_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_0 +// Description : Bits 15:0 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_0_ROW _u(0x00000f48) +#define OTP_DATA_KEY1_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_0_RESET "-" +#define OTP_DATA_KEY1_0_WIDTH _u(16) +#define OTP_DATA_KEY1_0_MSB _u(15) +#define OTP_DATA_KEY1_0_LSB _u(0) +#define OTP_DATA_KEY1_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_1 +// Description : Bits 31:16 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_1_ROW _u(0x00000f49) +#define OTP_DATA_KEY1_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_1_RESET "-" +#define OTP_DATA_KEY1_1_WIDTH _u(16) +#define OTP_DATA_KEY1_1_MSB _u(15) +#define OTP_DATA_KEY1_1_LSB _u(0) +#define OTP_DATA_KEY1_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_2 +// Description : Bits 47:32 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_2_ROW _u(0x00000f4a) +#define OTP_DATA_KEY1_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_2_RESET "-" +#define OTP_DATA_KEY1_2_WIDTH _u(16) +#define OTP_DATA_KEY1_2_MSB _u(15) +#define OTP_DATA_KEY1_2_LSB _u(0) +#define OTP_DATA_KEY1_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_3 +// Description : Bits 63:48 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_3_ROW _u(0x00000f4b) +#define OTP_DATA_KEY1_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_3_RESET "-" +#define OTP_DATA_KEY1_3_WIDTH _u(16) +#define OTP_DATA_KEY1_3_MSB _u(15) +#define OTP_DATA_KEY1_3_LSB _u(0) +#define OTP_DATA_KEY1_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_4 +// Description : Bits 79:64 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_4_ROW _u(0x00000f4c) +#define OTP_DATA_KEY1_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_4_RESET "-" +#define OTP_DATA_KEY1_4_WIDTH _u(16) +#define OTP_DATA_KEY1_4_MSB _u(15) +#define OTP_DATA_KEY1_4_LSB _u(0) +#define OTP_DATA_KEY1_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_5 +// Description : Bits 95:80 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_5_ROW _u(0x00000f4d) +#define OTP_DATA_KEY1_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_5_RESET "-" +#define OTP_DATA_KEY1_5_WIDTH _u(16) +#define OTP_DATA_KEY1_5_MSB _u(15) +#define OTP_DATA_KEY1_5_LSB _u(0) +#define OTP_DATA_KEY1_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_6 +// Description : Bits 111:96 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_6_ROW _u(0x00000f4e) +#define OTP_DATA_KEY1_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_6_RESET "-" +#define OTP_DATA_KEY1_6_WIDTH _u(16) +#define OTP_DATA_KEY1_6_MSB _u(15) +#define OTP_DATA_KEY1_6_LSB _u(0) +#define OTP_DATA_KEY1_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_7 +// Description : Bits 127:112 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_7_ROW _u(0x00000f4f) +#define OTP_DATA_KEY1_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_7_RESET "-" +#define OTP_DATA_KEY1_7_WIDTH _u(16) +#define OTP_DATA_KEY1_7_MSB _u(15) +#define OTP_DATA_KEY1_7_LSB _u(0) +#define OTP_DATA_KEY1_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_0 +// Description : Bits 15:0 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_0_ROW _u(0x00000f50) +#define OTP_DATA_KEY2_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_0_RESET "-" +#define OTP_DATA_KEY2_0_WIDTH _u(16) +#define OTP_DATA_KEY2_0_MSB _u(15) +#define OTP_DATA_KEY2_0_LSB _u(0) +#define OTP_DATA_KEY2_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_1 +// Description : Bits 31:16 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_1_ROW _u(0x00000f51) +#define OTP_DATA_KEY2_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_1_RESET "-" +#define OTP_DATA_KEY2_1_WIDTH _u(16) +#define OTP_DATA_KEY2_1_MSB _u(15) +#define OTP_DATA_KEY2_1_LSB _u(0) +#define OTP_DATA_KEY2_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_2 +// Description : Bits 47:32 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_2_ROW _u(0x00000f52) +#define OTP_DATA_KEY2_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_2_RESET "-" +#define OTP_DATA_KEY2_2_WIDTH _u(16) +#define OTP_DATA_KEY2_2_MSB _u(15) +#define OTP_DATA_KEY2_2_LSB _u(0) +#define OTP_DATA_KEY2_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_3 +// Description : Bits 63:48 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_3_ROW _u(0x00000f53) +#define OTP_DATA_KEY2_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_3_RESET "-" +#define OTP_DATA_KEY2_3_WIDTH _u(16) +#define OTP_DATA_KEY2_3_MSB _u(15) +#define OTP_DATA_KEY2_3_LSB _u(0) +#define OTP_DATA_KEY2_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_4 +// Description : Bits 79:64 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_4_ROW _u(0x00000f54) +#define OTP_DATA_KEY2_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_4_RESET "-" +#define OTP_DATA_KEY2_4_WIDTH _u(16) +#define OTP_DATA_KEY2_4_MSB _u(15) +#define OTP_DATA_KEY2_4_LSB _u(0) +#define OTP_DATA_KEY2_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_5 +// Description : Bits 95:80 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_5_ROW _u(0x00000f55) +#define OTP_DATA_KEY2_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_5_RESET "-" +#define OTP_DATA_KEY2_5_WIDTH _u(16) +#define OTP_DATA_KEY2_5_MSB _u(15) +#define OTP_DATA_KEY2_5_LSB _u(0) +#define OTP_DATA_KEY2_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_6 +// Description : Bits 111:96 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_6_ROW _u(0x00000f56) +#define OTP_DATA_KEY2_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_6_RESET "-" +#define OTP_DATA_KEY2_6_WIDTH _u(16) +#define OTP_DATA_KEY2_6_MSB _u(15) +#define OTP_DATA_KEY2_6_LSB _u(0) +#define OTP_DATA_KEY2_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_7 +// Description : Bits 127:112 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_7_ROW _u(0x00000f57) +#define OTP_DATA_KEY2_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_7_RESET "-" +#define OTP_DATA_KEY2_7_WIDTH _u(16) +#define OTP_DATA_KEY2_7_MSB _u(15) +#define OTP_DATA_KEY2_7_LSB _u(0) +#define OTP_DATA_KEY2_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_0 +// Description : Bits 15:0 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_0_ROW _u(0x00000f58) +#define OTP_DATA_KEY3_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_0_RESET "-" +#define OTP_DATA_KEY3_0_WIDTH _u(16) +#define OTP_DATA_KEY3_0_MSB _u(15) +#define OTP_DATA_KEY3_0_LSB _u(0) +#define OTP_DATA_KEY3_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_1 +// Description : Bits 31:16 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_1_ROW _u(0x00000f59) +#define OTP_DATA_KEY3_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_1_RESET "-" +#define OTP_DATA_KEY3_1_WIDTH _u(16) +#define OTP_DATA_KEY3_1_MSB _u(15) +#define OTP_DATA_KEY3_1_LSB _u(0) +#define OTP_DATA_KEY3_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_2 +// Description : Bits 47:32 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_2_ROW _u(0x00000f5a) +#define OTP_DATA_KEY3_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_2_RESET "-" +#define OTP_DATA_KEY3_2_WIDTH _u(16) +#define OTP_DATA_KEY3_2_MSB _u(15) +#define OTP_DATA_KEY3_2_LSB _u(0) +#define OTP_DATA_KEY3_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_3 +// Description : Bits 63:48 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_3_ROW _u(0x00000f5b) +#define OTP_DATA_KEY3_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_3_RESET "-" +#define OTP_DATA_KEY3_3_WIDTH _u(16) +#define OTP_DATA_KEY3_3_MSB _u(15) +#define OTP_DATA_KEY3_3_LSB _u(0) +#define OTP_DATA_KEY3_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_4 +// Description : Bits 79:64 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_4_ROW _u(0x00000f5c) +#define OTP_DATA_KEY3_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_4_RESET "-" +#define OTP_DATA_KEY3_4_WIDTH _u(16) +#define OTP_DATA_KEY3_4_MSB _u(15) +#define OTP_DATA_KEY3_4_LSB _u(0) +#define OTP_DATA_KEY3_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_5 +// Description : Bits 95:80 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_5_ROW _u(0x00000f5d) +#define OTP_DATA_KEY3_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_5_RESET "-" +#define OTP_DATA_KEY3_5_WIDTH _u(16) +#define OTP_DATA_KEY3_5_MSB _u(15) +#define OTP_DATA_KEY3_5_LSB _u(0) +#define OTP_DATA_KEY3_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_6 +// Description : Bits 111:96 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_6_ROW _u(0x00000f5e) +#define OTP_DATA_KEY3_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_6_RESET "-" +#define OTP_DATA_KEY3_6_WIDTH _u(16) +#define OTP_DATA_KEY3_6_MSB _u(15) +#define OTP_DATA_KEY3_6_LSB _u(0) +#define OTP_DATA_KEY3_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_7 +// Description : Bits 127:112 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_7_ROW _u(0x00000f5f) +#define OTP_DATA_KEY3_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_7_RESET "-" +#define OTP_DATA_KEY3_7_WIDTH _u(16) +#define OTP_DATA_KEY3_7_MSB _u(15) +#define OTP_DATA_KEY3_7_LSB _u(0) +#define OTP_DATA_KEY3_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_0 +// Description : Bits 15:0 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_0_ROW _u(0x00000f60) +#define OTP_DATA_KEY4_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_0_RESET "-" +#define OTP_DATA_KEY4_0_WIDTH _u(16) +#define OTP_DATA_KEY4_0_MSB _u(15) +#define OTP_DATA_KEY4_0_LSB _u(0) +#define OTP_DATA_KEY4_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_1 +// Description : Bits 31:16 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_1_ROW _u(0x00000f61) +#define OTP_DATA_KEY4_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_1_RESET "-" +#define OTP_DATA_KEY4_1_WIDTH _u(16) +#define OTP_DATA_KEY4_1_MSB _u(15) +#define OTP_DATA_KEY4_1_LSB _u(0) +#define OTP_DATA_KEY4_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_2 +// Description : Bits 47:32 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_2_ROW _u(0x00000f62) +#define OTP_DATA_KEY4_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_2_RESET "-" +#define OTP_DATA_KEY4_2_WIDTH _u(16) +#define OTP_DATA_KEY4_2_MSB _u(15) +#define OTP_DATA_KEY4_2_LSB _u(0) +#define OTP_DATA_KEY4_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_3 +// Description : Bits 63:48 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_3_ROW _u(0x00000f63) +#define OTP_DATA_KEY4_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_3_RESET "-" +#define OTP_DATA_KEY4_3_WIDTH _u(16) +#define OTP_DATA_KEY4_3_MSB _u(15) +#define OTP_DATA_KEY4_3_LSB _u(0) +#define OTP_DATA_KEY4_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_4 +// Description : Bits 79:64 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_4_ROW _u(0x00000f64) +#define OTP_DATA_KEY4_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_4_RESET "-" +#define OTP_DATA_KEY4_4_WIDTH _u(16) +#define OTP_DATA_KEY4_4_MSB _u(15) +#define OTP_DATA_KEY4_4_LSB _u(0) +#define OTP_DATA_KEY4_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_5 +// Description : Bits 95:80 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_5_ROW _u(0x00000f65) +#define OTP_DATA_KEY4_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_5_RESET "-" +#define OTP_DATA_KEY4_5_WIDTH _u(16) +#define OTP_DATA_KEY4_5_MSB _u(15) +#define OTP_DATA_KEY4_5_LSB _u(0) +#define OTP_DATA_KEY4_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_6 +// Description : Bits 111:96 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_6_ROW _u(0x00000f66) +#define OTP_DATA_KEY4_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_6_RESET "-" +#define OTP_DATA_KEY4_6_WIDTH _u(16) +#define OTP_DATA_KEY4_6_MSB _u(15) +#define OTP_DATA_KEY4_6_LSB _u(0) +#define OTP_DATA_KEY4_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_7 +// Description : Bits 127:112 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_7_ROW _u(0x00000f67) +#define OTP_DATA_KEY4_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_7_RESET "-" +#define OTP_DATA_KEY4_7_WIDTH _u(16) +#define OTP_DATA_KEY4_7_MSB _u(15) +#define OTP_DATA_KEY4_7_LSB _u(0) +#define OTP_DATA_KEY4_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_0 +// Description : Bits 15:0 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_0_ROW _u(0x00000f68) +#define OTP_DATA_KEY5_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_0_RESET "-" +#define OTP_DATA_KEY5_0_WIDTH _u(16) +#define OTP_DATA_KEY5_0_MSB _u(15) +#define OTP_DATA_KEY5_0_LSB _u(0) +#define OTP_DATA_KEY5_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_1 +// Description : Bits 31:16 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_1_ROW _u(0x00000f69) +#define OTP_DATA_KEY5_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_1_RESET "-" +#define OTP_DATA_KEY5_1_WIDTH _u(16) +#define OTP_DATA_KEY5_1_MSB _u(15) +#define OTP_DATA_KEY5_1_LSB _u(0) +#define OTP_DATA_KEY5_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_2 +// Description : Bits 47:32 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_2_ROW _u(0x00000f6a) +#define OTP_DATA_KEY5_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_2_RESET "-" +#define OTP_DATA_KEY5_2_WIDTH _u(16) +#define OTP_DATA_KEY5_2_MSB _u(15) +#define OTP_DATA_KEY5_2_LSB _u(0) +#define OTP_DATA_KEY5_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_3 +// Description : Bits 63:48 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_3_ROW _u(0x00000f6b) +#define OTP_DATA_KEY5_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_3_RESET "-" +#define OTP_DATA_KEY5_3_WIDTH _u(16) +#define OTP_DATA_KEY5_3_MSB _u(15) +#define OTP_DATA_KEY5_3_LSB _u(0) +#define OTP_DATA_KEY5_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_4 +// Description : Bits 79:64 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_4_ROW _u(0x00000f6c) +#define OTP_DATA_KEY5_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_4_RESET "-" +#define OTP_DATA_KEY5_4_WIDTH _u(16) +#define OTP_DATA_KEY5_4_MSB _u(15) +#define OTP_DATA_KEY5_4_LSB _u(0) +#define OTP_DATA_KEY5_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_5 +// Description : Bits 95:80 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_5_ROW _u(0x00000f6d) +#define OTP_DATA_KEY5_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_5_RESET "-" +#define OTP_DATA_KEY5_5_WIDTH _u(16) +#define OTP_DATA_KEY5_5_MSB _u(15) +#define OTP_DATA_KEY5_5_LSB _u(0) +#define OTP_DATA_KEY5_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_6 +// Description : Bits 111:96 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_6_ROW _u(0x00000f6e) +#define OTP_DATA_KEY5_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_6_RESET "-" +#define OTP_DATA_KEY5_6_WIDTH _u(16) +#define OTP_DATA_KEY5_6_MSB _u(15) +#define OTP_DATA_KEY5_6_LSB _u(0) +#define OTP_DATA_KEY5_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_7 +// Description : Bits 127:112 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_7_ROW _u(0x00000f6f) +#define OTP_DATA_KEY5_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_7_RESET "-" +#define OTP_DATA_KEY5_7_WIDTH _u(16) +#define OTP_DATA_KEY5_7_MSB _u(15) +#define OTP_DATA_KEY5_7_LSB _u(0) +#define OTP_DATA_KEY5_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_0 +// Description : Bits 15:0 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_0_ROW _u(0x00000f70) +#define OTP_DATA_KEY6_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_0_RESET "-" +#define OTP_DATA_KEY6_0_WIDTH _u(16) +#define OTP_DATA_KEY6_0_MSB _u(15) +#define OTP_DATA_KEY6_0_LSB _u(0) +#define OTP_DATA_KEY6_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_1 +// Description : Bits 31:16 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_1_ROW _u(0x00000f71) +#define OTP_DATA_KEY6_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_1_RESET "-" +#define OTP_DATA_KEY6_1_WIDTH _u(16) +#define OTP_DATA_KEY6_1_MSB _u(15) +#define OTP_DATA_KEY6_1_LSB _u(0) +#define OTP_DATA_KEY6_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_2 +// Description : Bits 47:32 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_2_ROW _u(0x00000f72) +#define OTP_DATA_KEY6_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_2_RESET "-" +#define OTP_DATA_KEY6_2_WIDTH _u(16) +#define OTP_DATA_KEY6_2_MSB _u(15) +#define OTP_DATA_KEY6_2_LSB _u(0) +#define OTP_DATA_KEY6_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_3 +// Description : Bits 63:48 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_3_ROW _u(0x00000f73) +#define OTP_DATA_KEY6_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_3_RESET "-" +#define OTP_DATA_KEY6_3_WIDTH _u(16) +#define OTP_DATA_KEY6_3_MSB _u(15) +#define OTP_DATA_KEY6_3_LSB _u(0) +#define OTP_DATA_KEY6_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_4 +// Description : Bits 79:64 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_4_ROW _u(0x00000f74) +#define OTP_DATA_KEY6_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_4_RESET "-" +#define OTP_DATA_KEY6_4_WIDTH _u(16) +#define OTP_DATA_KEY6_4_MSB _u(15) +#define OTP_DATA_KEY6_4_LSB _u(0) +#define OTP_DATA_KEY6_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_5 +// Description : Bits 95:80 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_5_ROW _u(0x00000f75) +#define OTP_DATA_KEY6_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_5_RESET "-" +#define OTP_DATA_KEY6_5_WIDTH _u(16) +#define OTP_DATA_KEY6_5_MSB _u(15) +#define OTP_DATA_KEY6_5_LSB _u(0) +#define OTP_DATA_KEY6_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_6 +// Description : Bits 111:96 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_6_ROW _u(0x00000f76) +#define OTP_DATA_KEY6_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_6_RESET "-" +#define OTP_DATA_KEY6_6_WIDTH _u(16) +#define OTP_DATA_KEY6_6_MSB _u(15) +#define OTP_DATA_KEY6_6_LSB _u(0) +#define OTP_DATA_KEY6_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_7 +// Description : Bits 127:112 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_7_ROW _u(0x00000f77) +#define OTP_DATA_KEY6_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_7_RESET "-" +#define OTP_DATA_KEY6_7_WIDTH _u(16) +#define OTP_DATA_KEY6_7_MSB _u(15) +#define OTP_DATA_KEY6_7_LSB _u(0) +#define OTP_DATA_KEY6_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_VALID +// Description : Valid flag for key 1. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY1_VALID_ROW _u(0x00000f79) +#define OTP_DATA_KEY1_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY1_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY1_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY1_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY1_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY1_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY1_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY1_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY1_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY1_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY1_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY1_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY1_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY1_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY1_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY1_VALID_VALID +#define OTP_DATA_KEY1_VALID_VALID_RESET "-" +#define OTP_DATA_KEY1_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY1_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY1_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY1_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_VALID +// Description : Valid flag for key 2. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY2_VALID_ROW _u(0x00000f7a) +#define OTP_DATA_KEY2_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY2_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY2_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY2_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY2_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY2_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY2_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY2_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY2_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY2_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY2_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY2_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY2_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY2_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY2_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY2_VALID_VALID +#define OTP_DATA_KEY2_VALID_VALID_RESET "-" +#define OTP_DATA_KEY2_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY2_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY2_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY2_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_VALID +// Description : Valid flag for key 3. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY3_VALID_ROW _u(0x00000f7b) +#define OTP_DATA_KEY3_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY3_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY3_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY3_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY3_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY3_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY3_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY3_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY3_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY3_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY3_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY3_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY3_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY3_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY3_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY3_VALID_VALID +#define OTP_DATA_KEY3_VALID_VALID_RESET "-" +#define OTP_DATA_KEY3_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY3_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY3_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY3_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_VALID +// Description : Valid flag for key 4. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY4_VALID_ROW _u(0x00000f7c) +#define OTP_DATA_KEY4_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY4_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY4_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY4_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY4_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY4_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY4_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY4_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY4_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY4_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY4_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY4_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY4_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY4_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY4_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY4_VALID_VALID +#define OTP_DATA_KEY4_VALID_VALID_RESET "-" +#define OTP_DATA_KEY4_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY4_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY4_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY4_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_VALID +// Description : Valid flag for key 5. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY5_VALID_ROW _u(0x00000f7d) +#define OTP_DATA_KEY5_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY5_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY5_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY5_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY5_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY5_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY5_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY5_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY5_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY5_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY5_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY5_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY5_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY5_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY5_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY5_VALID_VALID +#define OTP_DATA_KEY5_VALID_VALID_RESET "-" +#define OTP_DATA_KEY5_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY5_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY5_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY5_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_VALID +// Description : Valid flag for key 6. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY6_VALID_ROW _u(0x00000f7e) +#define OTP_DATA_KEY6_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY6_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY6_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY6_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY6_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY6_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY6_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY6_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY6_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY6_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY6_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY6_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY6_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY6_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY6_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY6_VALID_VALID +#define OTP_DATA_KEY6_VALID_VALID_RESET "-" +#define OTP_DATA_KEY6_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY6_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY6_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY6_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE0_LOCK0 +// Description : Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE0_LOCK0_ROW _u(0x00000f80) +#define OTP_DATA_PAGE0_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE0_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE0_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE0_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE0_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE0_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE0_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE0_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE0_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE0_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE0_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE0_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE0_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE0_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE0_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE0_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE0_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE0_LOCK1 +// Description : Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE0_LOCK1_ROW _u(0x00000f81) +#define OTP_DATA_PAGE0_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE0_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE0_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE0_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE0_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE0_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE0_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE0_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE0_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE1_LOCK0 +// Description : Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE1_LOCK0_ROW _u(0x00000f82) +#define OTP_DATA_PAGE1_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE1_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE1_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE1_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE1_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE1_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE1_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE1_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE1_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE1_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE1_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE1_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE1_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE1_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE1_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE1_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE1_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE1_LOCK1 +// Description : Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE1_LOCK1_ROW _u(0x00000f83) +#define OTP_DATA_PAGE1_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE1_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE1_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE1_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE1_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE1_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE1_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE1_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE1_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE2_LOCK0 +// Description : Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE2_LOCK0_ROW _u(0x00000f84) +#define OTP_DATA_PAGE2_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE2_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE2_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE2_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE2_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE2_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE2_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE2_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE2_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE2_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE2_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE2_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE2_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE2_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE2_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE2_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE2_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE2_LOCK1 +// Description : Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE2_LOCK1_ROW _u(0x00000f85) +#define OTP_DATA_PAGE2_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE2_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE2_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE2_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE2_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE2_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE2_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE2_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE2_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE3_LOCK0 +// Description : Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE3_LOCK0_ROW _u(0x00000f86) +#define OTP_DATA_PAGE3_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE3_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE3_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE3_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE3_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE3_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE3_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE3_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE3_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE3_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE3_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE3_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE3_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE3_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE3_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE3_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE3_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE3_LOCK1 +// Description : Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE3_LOCK1_ROW _u(0x00000f87) +#define OTP_DATA_PAGE3_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE3_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE3_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE3_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE3_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE3_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE3_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE3_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE3_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE4_LOCK0 +// Description : Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE4_LOCK0_ROW _u(0x00000f88) +#define OTP_DATA_PAGE4_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE4_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE4_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE4_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE4_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE4_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE4_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE4_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE4_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE4_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE4_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE4_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE4_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE4_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE4_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE4_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE4_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE4_LOCK1 +// Description : Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE4_LOCK1_ROW _u(0x00000f89) +#define OTP_DATA_PAGE4_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE4_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE4_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE4_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE4_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE4_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE4_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE4_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE4_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE5_LOCK0 +// Description : Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE5_LOCK0_ROW _u(0x00000f8a) +#define OTP_DATA_PAGE5_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE5_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE5_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE5_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE5_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE5_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE5_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE5_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE5_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE5_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE5_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE5_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE5_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE5_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE5_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE5_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE5_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE5_LOCK1 +// Description : Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE5_LOCK1_ROW _u(0x00000f8b) +#define OTP_DATA_PAGE5_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE5_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE5_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE5_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE5_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE5_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE5_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE5_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE5_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE6_LOCK0 +// Description : Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE6_LOCK0_ROW _u(0x00000f8c) +#define OTP_DATA_PAGE6_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE6_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE6_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE6_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE6_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE6_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE6_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE6_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE6_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE6_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE6_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE6_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE6_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE6_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE6_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE6_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE6_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE6_LOCK1 +// Description : Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE6_LOCK1_ROW _u(0x00000f8d) +#define OTP_DATA_PAGE6_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE6_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE6_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE6_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE6_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE6_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE6_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE6_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE6_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE7_LOCK0 +// Description : Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE7_LOCK0_ROW _u(0x00000f8e) +#define OTP_DATA_PAGE7_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE7_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE7_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE7_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE7_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE7_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE7_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE7_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE7_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE7_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE7_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE7_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE7_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE7_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE7_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE7_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE7_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE7_LOCK1 +// Description : Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE7_LOCK1_ROW _u(0x00000f8f) +#define OTP_DATA_PAGE7_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE7_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE7_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE7_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE7_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE7_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE7_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE7_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE7_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE8_LOCK0 +// Description : Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE8_LOCK0_ROW _u(0x00000f90) +#define OTP_DATA_PAGE8_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE8_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE8_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE8_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE8_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE8_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE8_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE8_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE8_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE8_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE8_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE8_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE8_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE8_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE8_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE8_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE8_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE8_LOCK1 +// Description : Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE8_LOCK1_ROW _u(0x00000f91) +#define OTP_DATA_PAGE8_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE8_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE8_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE8_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE8_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE8_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE8_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE8_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE8_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE9_LOCK0 +// Description : Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE9_LOCK0_ROW _u(0x00000f92) +#define OTP_DATA_PAGE9_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE9_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE9_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE9_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE9_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE9_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE9_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE9_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE9_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE9_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE9_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE9_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE9_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE9_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE9_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE9_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE9_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE9_LOCK1 +// Description : Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE9_LOCK1_ROW _u(0x00000f93) +#define OTP_DATA_PAGE9_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE9_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE9_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE9_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE9_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE9_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE9_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE9_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE9_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE10_LOCK0 +// Description : Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE10_LOCK0_ROW _u(0x00000f94) +#define OTP_DATA_PAGE10_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE10_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE10_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE10_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE10_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE10_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE10_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE10_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE10_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE10_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE10_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE10_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE10_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE10_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE10_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE10_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE10_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE10_LOCK1 +// Description : Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE10_LOCK1_ROW _u(0x00000f95) +#define OTP_DATA_PAGE10_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE10_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE10_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE10_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE10_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE10_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE10_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE10_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE10_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE11_LOCK0 +// Description : Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE11_LOCK0_ROW _u(0x00000f96) +#define OTP_DATA_PAGE11_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE11_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE11_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE11_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE11_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE11_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE11_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE11_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE11_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE11_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE11_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE11_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE11_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE11_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE11_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE11_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE11_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE11_LOCK1 +// Description : Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE11_LOCK1_ROW _u(0x00000f97) +#define OTP_DATA_PAGE11_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE11_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE11_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE11_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE11_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE11_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE11_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE11_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE11_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE12_LOCK0 +// Description : Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE12_LOCK0_ROW _u(0x00000f98) +#define OTP_DATA_PAGE12_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE12_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE12_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE12_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE12_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE12_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE12_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE12_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE12_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE12_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE12_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE12_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE12_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE12_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE12_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE12_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE12_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE12_LOCK1 +// Description : Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE12_LOCK1_ROW _u(0x00000f99) +#define OTP_DATA_PAGE12_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE12_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE12_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE12_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE12_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE12_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE12_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE12_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE12_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE13_LOCK0 +// Description : Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE13_LOCK0_ROW _u(0x00000f9a) +#define OTP_DATA_PAGE13_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE13_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE13_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE13_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE13_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE13_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE13_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE13_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE13_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE13_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE13_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE13_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE13_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE13_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE13_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE13_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE13_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE13_LOCK1 +// Description : Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE13_LOCK1_ROW _u(0x00000f9b) +#define OTP_DATA_PAGE13_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE13_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE13_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE13_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE13_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE13_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE13_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE13_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE13_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE14_LOCK0 +// Description : Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE14_LOCK0_ROW _u(0x00000f9c) +#define OTP_DATA_PAGE14_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE14_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE14_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE14_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE14_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE14_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE14_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE14_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE14_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE14_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE14_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE14_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE14_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE14_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE14_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE14_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE14_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE14_LOCK1 +// Description : Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE14_LOCK1_ROW _u(0x00000f9d) +#define OTP_DATA_PAGE14_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE14_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE14_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE14_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE14_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE14_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE14_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE14_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE14_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE15_LOCK0 +// Description : Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE15_LOCK0_ROW _u(0x00000f9e) +#define OTP_DATA_PAGE15_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE15_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE15_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE15_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE15_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE15_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE15_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE15_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE15_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE15_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE15_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE15_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE15_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE15_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE15_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE15_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE15_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE15_LOCK1 +// Description : Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE15_LOCK1_ROW _u(0x00000f9f) +#define OTP_DATA_PAGE15_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE15_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE15_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE15_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE15_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE15_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE15_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE15_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE15_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE16_LOCK0 +// Description : Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE16_LOCK0_ROW _u(0x00000fa0) +#define OTP_DATA_PAGE16_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE16_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE16_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE16_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE16_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE16_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE16_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE16_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE16_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE16_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE16_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE16_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE16_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE16_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE16_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE16_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE16_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE16_LOCK1 +// Description : Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE16_LOCK1_ROW _u(0x00000fa1) +#define OTP_DATA_PAGE16_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE16_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE16_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE16_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE16_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE16_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE16_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE16_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE16_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE17_LOCK0 +// Description : Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE17_LOCK0_ROW _u(0x00000fa2) +#define OTP_DATA_PAGE17_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE17_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE17_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE17_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE17_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE17_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE17_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE17_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE17_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE17_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE17_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE17_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE17_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE17_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE17_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE17_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE17_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE17_LOCK1 +// Description : Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE17_LOCK1_ROW _u(0x00000fa3) +#define OTP_DATA_PAGE17_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE17_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE17_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE17_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE17_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE17_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE17_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE17_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE17_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE18_LOCK0 +// Description : Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE18_LOCK0_ROW _u(0x00000fa4) +#define OTP_DATA_PAGE18_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE18_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE18_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE18_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE18_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE18_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE18_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE18_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE18_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE18_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE18_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE18_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE18_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE18_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE18_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE18_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE18_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE18_LOCK1 +// Description : Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE18_LOCK1_ROW _u(0x00000fa5) +#define OTP_DATA_PAGE18_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE18_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE18_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE18_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE18_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE18_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE18_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE18_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE18_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE19_LOCK0 +// Description : Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE19_LOCK0_ROW _u(0x00000fa6) +#define OTP_DATA_PAGE19_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE19_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE19_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE19_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE19_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE19_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE19_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE19_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE19_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE19_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE19_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE19_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE19_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE19_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE19_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE19_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE19_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE19_LOCK1 +// Description : Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE19_LOCK1_ROW _u(0x00000fa7) +#define OTP_DATA_PAGE19_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE19_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE19_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE19_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE19_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE19_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE19_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE19_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE19_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE20_LOCK0 +// Description : Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE20_LOCK0_ROW _u(0x00000fa8) +#define OTP_DATA_PAGE20_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE20_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE20_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE20_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE20_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE20_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE20_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE20_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE20_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE20_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE20_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE20_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE20_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE20_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE20_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE20_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE20_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE20_LOCK1 +// Description : Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE20_LOCK1_ROW _u(0x00000fa9) +#define OTP_DATA_PAGE20_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE20_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE20_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE20_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE20_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE20_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE20_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE20_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE20_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE21_LOCK0 +// Description : Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE21_LOCK0_ROW _u(0x00000faa) +#define OTP_DATA_PAGE21_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE21_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE21_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE21_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE21_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE21_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE21_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE21_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE21_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE21_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE21_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE21_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE21_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE21_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE21_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE21_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE21_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE21_LOCK1 +// Description : Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE21_LOCK1_ROW _u(0x00000fab) +#define OTP_DATA_PAGE21_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE21_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE21_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE21_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE21_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE21_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE21_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE21_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE21_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE22_LOCK0 +// Description : Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE22_LOCK0_ROW _u(0x00000fac) +#define OTP_DATA_PAGE22_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE22_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE22_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE22_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE22_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE22_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE22_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE22_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE22_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE22_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE22_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE22_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE22_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE22_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE22_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE22_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE22_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE22_LOCK1 +// Description : Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE22_LOCK1_ROW _u(0x00000fad) +#define OTP_DATA_PAGE22_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE22_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE22_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE22_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE22_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE22_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE22_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE22_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE22_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE23_LOCK0 +// Description : Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE23_LOCK0_ROW _u(0x00000fae) +#define OTP_DATA_PAGE23_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE23_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE23_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE23_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE23_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE23_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE23_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE23_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE23_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE23_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE23_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE23_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE23_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE23_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE23_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE23_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE23_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE23_LOCK1 +// Description : Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE23_LOCK1_ROW _u(0x00000faf) +#define OTP_DATA_PAGE23_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE23_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE23_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE23_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE23_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE23_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE23_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE23_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE23_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE24_LOCK0 +// Description : Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE24_LOCK0_ROW _u(0x00000fb0) +#define OTP_DATA_PAGE24_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE24_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE24_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE24_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE24_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE24_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE24_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE24_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE24_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE24_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE24_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE24_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE24_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE24_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE24_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE24_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE24_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE24_LOCK1 +// Description : Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE24_LOCK1_ROW _u(0x00000fb1) +#define OTP_DATA_PAGE24_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE24_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE24_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE24_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE24_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE24_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE24_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE24_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE24_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE25_LOCK0 +// Description : Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE25_LOCK0_ROW _u(0x00000fb2) +#define OTP_DATA_PAGE25_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE25_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE25_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE25_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE25_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE25_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE25_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE25_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE25_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE25_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE25_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE25_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE25_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE25_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE25_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE25_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE25_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE25_LOCK1 +// Description : Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE25_LOCK1_ROW _u(0x00000fb3) +#define OTP_DATA_PAGE25_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE25_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE25_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE25_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE25_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE25_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE25_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE25_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE25_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE26_LOCK0 +// Description : Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE26_LOCK0_ROW _u(0x00000fb4) +#define OTP_DATA_PAGE26_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE26_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE26_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE26_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE26_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE26_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE26_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE26_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE26_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE26_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE26_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE26_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE26_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE26_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE26_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE26_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE26_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE26_LOCK1 +// Description : Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE26_LOCK1_ROW _u(0x00000fb5) +#define OTP_DATA_PAGE26_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE26_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE26_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE26_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE26_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE26_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE26_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE26_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE26_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE27_LOCK0 +// Description : Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE27_LOCK0_ROW _u(0x00000fb6) +#define OTP_DATA_PAGE27_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE27_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE27_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE27_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE27_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE27_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE27_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE27_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE27_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE27_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE27_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE27_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE27_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE27_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE27_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE27_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE27_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE27_LOCK1 +// Description : Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE27_LOCK1_ROW _u(0x00000fb7) +#define OTP_DATA_PAGE27_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE27_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE27_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE27_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE27_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE27_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE27_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE27_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE27_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE28_LOCK0 +// Description : Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE28_LOCK0_ROW _u(0x00000fb8) +#define OTP_DATA_PAGE28_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE28_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE28_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE28_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE28_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE28_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE28_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE28_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE28_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE28_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE28_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE28_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE28_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE28_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE28_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE28_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE28_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE28_LOCK1 +// Description : Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE28_LOCK1_ROW _u(0x00000fb9) +#define OTP_DATA_PAGE28_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE28_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE28_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE28_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE28_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE28_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE28_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE28_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE28_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE29_LOCK0 +// Description : Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE29_LOCK0_ROW _u(0x00000fba) +#define OTP_DATA_PAGE29_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE29_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE29_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE29_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE29_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE29_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE29_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE29_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE29_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE29_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE29_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE29_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE29_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE29_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE29_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE29_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE29_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE29_LOCK1 +// Description : Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE29_LOCK1_ROW _u(0x00000fbb) +#define OTP_DATA_PAGE29_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE29_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE29_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE29_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE29_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE29_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE29_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE29_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE29_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE30_LOCK0 +// Description : Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE30_LOCK0_ROW _u(0x00000fbc) +#define OTP_DATA_PAGE30_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE30_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE30_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE30_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE30_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE30_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE30_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE30_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE30_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE30_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE30_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE30_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE30_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE30_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE30_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE30_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE30_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE30_LOCK1 +// Description : Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE30_LOCK1_ROW _u(0x00000fbd) +#define OTP_DATA_PAGE30_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE30_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE30_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE30_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE30_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE30_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE30_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE30_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE30_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE31_LOCK0 +// Description : Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE31_LOCK0_ROW _u(0x00000fbe) +#define OTP_DATA_PAGE31_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE31_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE31_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE31_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE31_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE31_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE31_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE31_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE31_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE31_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE31_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE31_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE31_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE31_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE31_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE31_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE31_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE31_LOCK1 +// Description : Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE31_LOCK1_ROW _u(0x00000fbf) +#define OTP_DATA_PAGE31_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE31_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE31_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE31_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE31_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE31_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE31_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE31_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE31_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE32_LOCK0 +// Description : Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE32_LOCK0_ROW _u(0x00000fc0) +#define OTP_DATA_PAGE32_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE32_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE32_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE32_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE32_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE32_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE32_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE32_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE32_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE32_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE32_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE32_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE32_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE32_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE32_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE32_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE32_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE32_LOCK1 +// Description : Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE32_LOCK1_ROW _u(0x00000fc1) +#define OTP_DATA_PAGE32_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE32_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE32_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE32_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE32_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE32_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE32_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE32_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE32_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE33_LOCK0 +// Description : Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE33_LOCK0_ROW _u(0x00000fc2) +#define OTP_DATA_PAGE33_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE33_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE33_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE33_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE33_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE33_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE33_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE33_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE33_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE33_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE33_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE33_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE33_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE33_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE33_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE33_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE33_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE33_LOCK1 +// Description : Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE33_LOCK1_ROW _u(0x00000fc3) +#define OTP_DATA_PAGE33_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE33_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE33_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE33_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE33_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE33_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE33_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE33_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE33_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE34_LOCK0 +// Description : Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE34_LOCK0_ROW _u(0x00000fc4) +#define OTP_DATA_PAGE34_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE34_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE34_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE34_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE34_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE34_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE34_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE34_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE34_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE34_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE34_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE34_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE34_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE34_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE34_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE34_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE34_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE34_LOCK1 +// Description : Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE34_LOCK1_ROW _u(0x00000fc5) +#define OTP_DATA_PAGE34_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE34_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE34_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE34_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE34_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE34_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE34_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE34_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE34_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE35_LOCK0 +// Description : Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE35_LOCK0_ROW _u(0x00000fc6) +#define OTP_DATA_PAGE35_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE35_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE35_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE35_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE35_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE35_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE35_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE35_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE35_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE35_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE35_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE35_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE35_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE35_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE35_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE35_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE35_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE35_LOCK1 +// Description : Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE35_LOCK1_ROW _u(0x00000fc7) +#define OTP_DATA_PAGE35_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE35_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE35_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE35_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE35_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE35_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE35_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE35_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE35_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE36_LOCK0 +// Description : Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE36_LOCK0_ROW _u(0x00000fc8) +#define OTP_DATA_PAGE36_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE36_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE36_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE36_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE36_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE36_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE36_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE36_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE36_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE36_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE36_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE36_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE36_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE36_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE36_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE36_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE36_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE36_LOCK1 +// Description : Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE36_LOCK1_ROW _u(0x00000fc9) +#define OTP_DATA_PAGE36_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE36_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE36_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE36_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE36_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE36_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE36_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE36_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE36_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE37_LOCK0 +// Description : Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE37_LOCK0_ROW _u(0x00000fca) +#define OTP_DATA_PAGE37_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE37_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE37_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE37_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE37_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE37_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE37_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE37_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE37_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE37_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE37_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE37_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE37_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE37_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE37_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE37_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE37_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE37_LOCK1 +// Description : Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE37_LOCK1_ROW _u(0x00000fcb) +#define OTP_DATA_PAGE37_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE37_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE37_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE37_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE37_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE37_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE37_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE37_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE37_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE38_LOCK0 +// Description : Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE38_LOCK0_ROW _u(0x00000fcc) +#define OTP_DATA_PAGE38_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE38_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE38_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE38_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE38_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE38_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE38_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE38_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE38_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE38_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE38_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE38_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE38_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE38_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE38_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE38_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE38_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE38_LOCK1 +// Description : Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE38_LOCK1_ROW _u(0x00000fcd) +#define OTP_DATA_PAGE38_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE38_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE38_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE38_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE38_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE38_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE38_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE38_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE38_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE39_LOCK0 +// Description : Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE39_LOCK0_ROW _u(0x00000fce) +#define OTP_DATA_PAGE39_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE39_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE39_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE39_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE39_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE39_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE39_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE39_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE39_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE39_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE39_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE39_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE39_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE39_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE39_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE39_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE39_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE39_LOCK1 +// Description : Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE39_LOCK1_ROW _u(0x00000fcf) +#define OTP_DATA_PAGE39_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE39_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE39_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE39_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE39_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE39_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE39_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE39_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE39_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE40_LOCK0 +// Description : Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE40_LOCK0_ROW _u(0x00000fd0) +#define OTP_DATA_PAGE40_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE40_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE40_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE40_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE40_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE40_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE40_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE40_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE40_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE40_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE40_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE40_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE40_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE40_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE40_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE40_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE40_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE40_LOCK1 +// Description : Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE40_LOCK1_ROW _u(0x00000fd1) +#define OTP_DATA_PAGE40_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE40_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE40_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE40_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE40_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE40_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE40_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE40_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE40_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE41_LOCK0 +// Description : Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE41_LOCK0_ROW _u(0x00000fd2) +#define OTP_DATA_PAGE41_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE41_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE41_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE41_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE41_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE41_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE41_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE41_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE41_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE41_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE41_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE41_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE41_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE41_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE41_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE41_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE41_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE41_LOCK1 +// Description : Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE41_LOCK1_ROW _u(0x00000fd3) +#define OTP_DATA_PAGE41_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE41_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE41_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE41_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE41_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE41_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE41_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE41_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE41_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE42_LOCK0 +// Description : Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE42_LOCK0_ROW _u(0x00000fd4) +#define OTP_DATA_PAGE42_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE42_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE42_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE42_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE42_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE42_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE42_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE42_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE42_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE42_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE42_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE42_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE42_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE42_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE42_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE42_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE42_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE42_LOCK1 +// Description : Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE42_LOCK1_ROW _u(0x00000fd5) +#define OTP_DATA_PAGE42_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE42_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE42_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE42_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE42_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE42_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE42_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE42_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE42_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE43_LOCK0 +// Description : Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE43_LOCK0_ROW _u(0x00000fd6) +#define OTP_DATA_PAGE43_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE43_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE43_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE43_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE43_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE43_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE43_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE43_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE43_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE43_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE43_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE43_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE43_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE43_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE43_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE43_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE43_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE43_LOCK1 +// Description : Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE43_LOCK1_ROW _u(0x00000fd7) +#define OTP_DATA_PAGE43_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE43_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE43_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE43_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE43_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE43_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE43_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE43_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE43_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE44_LOCK0 +// Description : Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE44_LOCK0_ROW _u(0x00000fd8) +#define OTP_DATA_PAGE44_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE44_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE44_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE44_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE44_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE44_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE44_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE44_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE44_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE44_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE44_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE44_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE44_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE44_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE44_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE44_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE44_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE44_LOCK1 +// Description : Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE44_LOCK1_ROW _u(0x00000fd9) +#define OTP_DATA_PAGE44_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE44_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE44_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE44_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE44_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE44_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE44_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE44_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE44_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE45_LOCK0 +// Description : Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE45_LOCK0_ROW _u(0x00000fda) +#define OTP_DATA_PAGE45_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE45_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE45_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE45_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE45_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE45_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE45_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE45_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE45_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE45_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE45_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE45_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE45_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE45_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE45_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE45_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE45_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE45_LOCK1 +// Description : Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE45_LOCK1_ROW _u(0x00000fdb) +#define OTP_DATA_PAGE45_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE45_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE45_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE45_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE45_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE45_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE45_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE45_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE45_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE46_LOCK0 +// Description : Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE46_LOCK0_ROW _u(0x00000fdc) +#define OTP_DATA_PAGE46_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE46_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE46_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE46_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE46_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE46_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE46_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE46_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE46_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE46_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE46_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE46_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE46_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE46_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE46_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE46_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE46_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE46_LOCK1 +// Description : Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE46_LOCK1_ROW _u(0x00000fdd) +#define OTP_DATA_PAGE46_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE46_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE46_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE46_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE46_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE46_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE46_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE46_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE46_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE47_LOCK0 +// Description : Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE47_LOCK0_ROW _u(0x00000fde) +#define OTP_DATA_PAGE47_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE47_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE47_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE47_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE47_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE47_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE47_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE47_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE47_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE47_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE47_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE47_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE47_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE47_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE47_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE47_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE47_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE47_LOCK1 +// Description : Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE47_LOCK1_ROW _u(0x00000fdf) +#define OTP_DATA_PAGE47_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE47_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE47_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE47_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE47_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE47_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE47_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE47_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE47_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE48_LOCK0 +// Description : Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE48_LOCK0_ROW _u(0x00000fe0) +#define OTP_DATA_PAGE48_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE48_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE48_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE48_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE48_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE48_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE48_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE48_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE48_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE48_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE48_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE48_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE48_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE48_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE48_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE48_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE48_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE48_LOCK1 +// Description : Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE48_LOCK1_ROW _u(0x00000fe1) +#define OTP_DATA_PAGE48_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE48_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE48_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE48_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE48_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE48_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE48_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE48_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE48_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE49_LOCK0 +// Description : Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE49_LOCK0_ROW _u(0x00000fe2) +#define OTP_DATA_PAGE49_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE49_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE49_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE49_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE49_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE49_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE49_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE49_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE49_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE49_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE49_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE49_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE49_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE49_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE49_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE49_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE49_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE49_LOCK1 +// Description : Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE49_LOCK1_ROW _u(0x00000fe3) +#define OTP_DATA_PAGE49_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE49_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE49_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE49_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE49_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE49_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE49_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE49_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE49_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE50_LOCK0 +// Description : Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE50_LOCK0_ROW _u(0x00000fe4) +#define OTP_DATA_PAGE50_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE50_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE50_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE50_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE50_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE50_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE50_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE50_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE50_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE50_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE50_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE50_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE50_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE50_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE50_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE50_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE50_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE50_LOCK1 +// Description : Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE50_LOCK1_ROW _u(0x00000fe5) +#define OTP_DATA_PAGE50_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE50_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE50_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE50_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE50_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE50_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE50_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE50_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE50_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE51_LOCK0 +// Description : Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE51_LOCK0_ROW _u(0x00000fe6) +#define OTP_DATA_PAGE51_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE51_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE51_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE51_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE51_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE51_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE51_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE51_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE51_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE51_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE51_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE51_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE51_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE51_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE51_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE51_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE51_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE51_LOCK1 +// Description : Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE51_LOCK1_ROW _u(0x00000fe7) +#define OTP_DATA_PAGE51_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE51_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE51_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE51_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE51_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE51_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE51_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE51_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE51_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE52_LOCK0 +// Description : Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE52_LOCK0_ROW _u(0x00000fe8) +#define OTP_DATA_PAGE52_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE52_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE52_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE52_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE52_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE52_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE52_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE52_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE52_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE52_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE52_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE52_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE52_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE52_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE52_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE52_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE52_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE52_LOCK1 +// Description : Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE52_LOCK1_ROW _u(0x00000fe9) +#define OTP_DATA_PAGE52_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE52_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE52_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE52_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE52_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE52_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE52_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE52_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE52_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE53_LOCK0 +// Description : Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE53_LOCK0_ROW _u(0x00000fea) +#define OTP_DATA_PAGE53_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE53_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE53_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE53_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE53_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE53_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE53_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE53_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE53_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE53_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE53_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE53_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE53_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE53_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE53_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE53_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE53_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE53_LOCK1 +// Description : Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE53_LOCK1_ROW _u(0x00000feb) +#define OTP_DATA_PAGE53_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE53_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE53_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE53_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE53_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE53_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE53_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE53_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE53_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE54_LOCK0 +// Description : Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE54_LOCK0_ROW _u(0x00000fec) +#define OTP_DATA_PAGE54_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE54_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE54_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE54_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE54_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE54_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE54_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE54_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE54_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE54_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE54_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE54_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE54_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE54_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE54_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE54_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE54_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE54_LOCK1 +// Description : Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE54_LOCK1_ROW _u(0x00000fed) +#define OTP_DATA_PAGE54_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE54_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE54_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE54_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE54_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE54_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE54_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE54_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE54_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE55_LOCK0 +// Description : Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE55_LOCK0_ROW _u(0x00000fee) +#define OTP_DATA_PAGE55_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE55_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE55_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE55_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE55_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE55_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE55_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE55_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE55_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE55_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE55_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE55_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE55_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE55_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE55_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE55_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE55_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE55_LOCK1 +// Description : Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE55_LOCK1_ROW _u(0x00000fef) +#define OTP_DATA_PAGE55_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE55_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE55_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE55_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE55_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE55_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE55_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE55_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE55_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE56_LOCK0 +// Description : Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE56_LOCK0_ROW _u(0x00000ff0) +#define OTP_DATA_PAGE56_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE56_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE56_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE56_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE56_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE56_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE56_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE56_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE56_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE56_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE56_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE56_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE56_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE56_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE56_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE56_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE56_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE56_LOCK1 +// Description : Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE56_LOCK1_ROW _u(0x00000ff1) +#define OTP_DATA_PAGE56_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE56_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE56_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE56_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE56_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE56_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE56_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE56_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE56_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE57_LOCK0 +// Description : Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE57_LOCK0_ROW _u(0x00000ff2) +#define OTP_DATA_PAGE57_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE57_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE57_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE57_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE57_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE57_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE57_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE57_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE57_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE57_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE57_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE57_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE57_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE57_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE57_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE57_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE57_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE57_LOCK1 +// Description : Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE57_LOCK1_ROW _u(0x00000ff3) +#define OTP_DATA_PAGE57_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE57_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE57_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE57_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE57_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE57_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE57_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE57_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE57_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE58_LOCK0 +// Description : Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE58_LOCK0_ROW _u(0x00000ff4) +#define OTP_DATA_PAGE58_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE58_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE58_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE58_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE58_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE58_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE58_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE58_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE58_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE58_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE58_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE58_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE58_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE58_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE58_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE58_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE58_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE58_LOCK1 +// Description : Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE58_LOCK1_ROW _u(0x00000ff5) +#define OTP_DATA_PAGE58_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE58_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE58_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE58_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE58_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE58_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE58_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE58_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE58_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE59_LOCK0 +// Description : Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE59_LOCK0_ROW _u(0x00000ff6) +#define OTP_DATA_PAGE59_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE59_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE59_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE59_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE59_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE59_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE59_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE59_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE59_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE59_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE59_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE59_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE59_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE59_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE59_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE59_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE59_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE59_LOCK1 +// Description : Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE59_LOCK1_ROW _u(0x00000ff7) +#define OTP_DATA_PAGE59_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE59_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE59_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE59_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE59_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE59_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE59_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE59_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE59_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE60_LOCK0 +// Description : Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE60_LOCK0_ROW _u(0x00000ff8) +#define OTP_DATA_PAGE60_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE60_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE60_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE60_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE60_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE60_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE60_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE60_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE60_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE60_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE60_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE60_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE60_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE60_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE60_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE60_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE60_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE60_LOCK1 +// Description : Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE60_LOCK1_ROW _u(0x00000ff9) +#define OTP_DATA_PAGE60_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE60_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE60_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE60_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE60_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE60_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE60_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE60_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE60_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE61_LOCK0 +// Description : Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE61_LOCK0_ROW _u(0x00000ffa) +#define OTP_DATA_PAGE61_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE61_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE61_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE61_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE61_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE61_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE61_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE61_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE61_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE61_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE61_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE61_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE61_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE61_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE61_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE61_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE61_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE61_LOCK1 +// Description : Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE61_LOCK1_ROW _u(0x00000ffb) +#define OTP_DATA_PAGE61_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE61_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE61_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE61_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE61_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE61_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE61_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE61_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE61_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE62_LOCK0 +// Description : Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE62_LOCK0_ROW _u(0x00000ffc) +#define OTP_DATA_PAGE62_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE62_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE62_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE62_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE62_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE62_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE62_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE62_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE62_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE62_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE62_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE62_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE62_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE62_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE62_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE62_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE62_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE62_LOCK1 +// Description : Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE62_LOCK1_ROW _u(0x00000ffd) +#define OTP_DATA_PAGE62_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE62_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE62_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE62_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE62_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE62_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE62_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE62_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE62_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE63_LOCK0 +// Description : Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE63_LOCK0_ROW _u(0x00000ffe) +#define OTP_DATA_PAGE63_LOCK0_BITS _u(0x00ffffff) +#define OTP_DATA_PAGE63_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE63_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE63_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE63_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE63_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE63_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE63_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE63_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_RMA +// Description : Decommission for RMA of a suspected faulty device. This re- +// enables the factory test JTAG interface, and makes pages 3 +// through 61 of the OTP permanently inaccessible. +#define OTP_DATA_PAGE63_LOCK0_RMA_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_RMA_BITS _u(0x00000080) +#define OTP_DATA_PAGE63_LOCK0_RMA_MSB _u(7) +#define OTP_DATA_PAGE63_LOCK0_RMA_LSB _u(7) +#define OTP_DATA_PAGE63_LOCK0_RMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE63_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE63_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE63_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE63_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE63_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE63_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE63_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE63_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE63_LOCK1 +// Description : Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE63_LOCK1_ROW _u(0x00000fff) +#define OTP_DATA_PAGE63_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE63_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE63_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE63_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE63_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE63_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE63_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE63_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE63_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +#endif // _HARDWARE_REGS_OTP_DATA_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/pads_bank0.h b/src/rp2350/hardware_regs/include/hardware/regs/pads_bank0.h new file mode 100644 index 000000000..cf262054f --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/pads_bank0.h @@ -0,0 +1,3980 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_BANK0 +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PADS_BANK0_H +#define _HARDWARE_REGS_PADS_BANK0_H +// ============================================================================= +// Register : PADS_BANK0_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) +// ============================================================================= +// Register : PADS_BANK0_GPIO0 +#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) +#define PADS_BANK0_GPIO0_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO0_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO0_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO0_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO0_ISO_MSB _u(8) +#define PADS_BANK0_GPIO0_ISO_LSB _u(8) +#define PADS_BANK0_GPIO0_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO0_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO0_OD_MSB _u(7) +#define PADS_BANK0_GPIO0_OD_LSB _u(7) +#define PADS_BANK0_GPIO0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_IE +// Description : Input enable +#define PADS_BANK0_GPIO0_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO0_IE_MSB _u(6) +#define PADS_BANK0_GPIO0_IE_LSB _u(6) +#define PADS_BANK0_GPIO0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO0_PUE_MSB _u(3) +#define PADS_BANK0_GPIO0_PUE_LSB _u(3) +#define PADS_BANK0_GPIO0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO0_PDE_MSB _u(2) +#define PADS_BANK0_GPIO0_PDE_LSB _u(2) +#define PADS_BANK0_GPIO0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO1 +#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) +#define PADS_BANK0_GPIO1_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO1_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO1_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO1_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO1_ISO_MSB _u(8) +#define PADS_BANK0_GPIO1_ISO_LSB _u(8) +#define PADS_BANK0_GPIO1_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO1_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO1_OD_MSB _u(7) +#define PADS_BANK0_GPIO1_OD_LSB _u(7) +#define PADS_BANK0_GPIO1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_IE +// Description : Input enable +#define PADS_BANK0_GPIO1_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO1_IE_MSB _u(6) +#define PADS_BANK0_GPIO1_IE_LSB _u(6) +#define PADS_BANK0_GPIO1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO1_PUE_MSB _u(3) +#define PADS_BANK0_GPIO1_PUE_LSB _u(3) +#define PADS_BANK0_GPIO1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO1_PDE_MSB _u(2) +#define PADS_BANK0_GPIO1_PDE_LSB _u(2) +#define PADS_BANK0_GPIO1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO2 +#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) +#define PADS_BANK0_GPIO2_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO2_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO2_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO2_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO2_ISO_MSB _u(8) +#define PADS_BANK0_GPIO2_ISO_LSB _u(8) +#define PADS_BANK0_GPIO2_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO2_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO2_OD_MSB _u(7) +#define PADS_BANK0_GPIO2_OD_LSB _u(7) +#define PADS_BANK0_GPIO2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_IE +// Description : Input enable +#define PADS_BANK0_GPIO2_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO2_IE_MSB _u(6) +#define PADS_BANK0_GPIO2_IE_LSB _u(6) +#define PADS_BANK0_GPIO2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO2_PUE_MSB _u(3) +#define PADS_BANK0_GPIO2_PUE_LSB _u(3) +#define PADS_BANK0_GPIO2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO2_PDE_MSB _u(2) +#define PADS_BANK0_GPIO2_PDE_LSB _u(2) +#define PADS_BANK0_GPIO2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO3 +#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) +#define PADS_BANK0_GPIO3_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO3_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO3_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO3_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO3_ISO_MSB _u(8) +#define PADS_BANK0_GPIO3_ISO_LSB _u(8) +#define PADS_BANK0_GPIO3_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO3_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO3_OD_MSB _u(7) +#define PADS_BANK0_GPIO3_OD_LSB _u(7) +#define PADS_BANK0_GPIO3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_IE +// Description : Input enable +#define PADS_BANK0_GPIO3_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO3_IE_MSB _u(6) +#define PADS_BANK0_GPIO3_IE_LSB _u(6) +#define PADS_BANK0_GPIO3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO3_PUE_MSB _u(3) +#define PADS_BANK0_GPIO3_PUE_LSB _u(3) +#define PADS_BANK0_GPIO3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO3_PDE_MSB _u(2) +#define PADS_BANK0_GPIO3_PDE_LSB _u(2) +#define PADS_BANK0_GPIO3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO4 +#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) +#define PADS_BANK0_GPIO4_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO4_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO4_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO4_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO4_ISO_MSB _u(8) +#define PADS_BANK0_GPIO4_ISO_LSB _u(8) +#define PADS_BANK0_GPIO4_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO4_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO4_OD_MSB _u(7) +#define PADS_BANK0_GPIO4_OD_LSB _u(7) +#define PADS_BANK0_GPIO4_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_IE +// Description : Input enable +#define PADS_BANK0_GPIO4_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO4_IE_MSB _u(6) +#define PADS_BANK0_GPIO4_IE_LSB _u(6) +#define PADS_BANK0_GPIO4_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO4_PUE_MSB _u(3) +#define PADS_BANK0_GPIO4_PUE_LSB _u(3) +#define PADS_BANK0_GPIO4_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO4_PDE_MSB _u(2) +#define PADS_BANK0_GPIO4_PDE_LSB _u(2) +#define PADS_BANK0_GPIO4_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO5 +#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) +#define PADS_BANK0_GPIO5_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO5_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO5_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO5_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO5_ISO_MSB _u(8) +#define PADS_BANK0_GPIO5_ISO_LSB _u(8) +#define PADS_BANK0_GPIO5_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO5_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO5_OD_MSB _u(7) +#define PADS_BANK0_GPIO5_OD_LSB _u(7) +#define PADS_BANK0_GPIO5_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_IE +// Description : Input enable +#define PADS_BANK0_GPIO5_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO5_IE_MSB _u(6) +#define PADS_BANK0_GPIO5_IE_LSB _u(6) +#define PADS_BANK0_GPIO5_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO5_PUE_MSB _u(3) +#define PADS_BANK0_GPIO5_PUE_LSB _u(3) +#define PADS_BANK0_GPIO5_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO5_PDE_MSB _u(2) +#define PADS_BANK0_GPIO5_PDE_LSB _u(2) +#define PADS_BANK0_GPIO5_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO6 +#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) +#define PADS_BANK0_GPIO6_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO6_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO6_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO6_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO6_ISO_MSB _u(8) +#define PADS_BANK0_GPIO6_ISO_LSB _u(8) +#define PADS_BANK0_GPIO6_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO6_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO6_OD_MSB _u(7) +#define PADS_BANK0_GPIO6_OD_LSB _u(7) +#define PADS_BANK0_GPIO6_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_IE +// Description : Input enable +#define PADS_BANK0_GPIO6_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO6_IE_MSB _u(6) +#define PADS_BANK0_GPIO6_IE_LSB _u(6) +#define PADS_BANK0_GPIO6_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO6_PUE_MSB _u(3) +#define PADS_BANK0_GPIO6_PUE_LSB _u(3) +#define PADS_BANK0_GPIO6_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO6_PDE_MSB _u(2) +#define PADS_BANK0_GPIO6_PDE_LSB _u(2) +#define PADS_BANK0_GPIO6_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO7 +#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) +#define PADS_BANK0_GPIO7_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO7_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO7_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO7_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO7_ISO_MSB _u(8) +#define PADS_BANK0_GPIO7_ISO_LSB _u(8) +#define PADS_BANK0_GPIO7_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO7_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO7_OD_MSB _u(7) +#define PADS_BANK0_GPIO7_OD_LSB _u(7) +#define PADS_BANK0_GPIO7_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_IE +// Description : Input enable +#define PADS_BANK0_GPIO7_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO7_IE_MSB _u(6) +#define PADS_BANK0_GPIO7_IE_LSB _u(6) +#define PADS_BANK0_GPIO7_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO7_PUE_MSB _u(3) +#define PADS_BANK0_GPIO7_PUE_LSB _u(3) +#define PADS_BANK0_GPIO7_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO7_PDE_MSB _u(2) +#define PADS_BANK0_GPIO7_PDE_LSB _u(2) +#define PADS_BANK0_GPIO7_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO8 +#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) +#define PADS_BANK0_GPIO8_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO8_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO8_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO8_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO8_ISO_MSB _u(8) +#define PADS_BANK0_GPIO8_ISO_LSB _u(8) +#define PADS_BANK0_GPIO8_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO8_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO8_OD_MSB _u(7) +#define PADS_BANK0_GPIO8_OD_LSB _u(7) +#define PADS_BANK0_GPIO8_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_IE +// Description : Input enable +#define PADS_BANK0_GPIO8_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO8_IE_MSB _u(6) +#define PADS_BANK0_GPIO8_IE_LSB _u(6) +#define PADS_BANK0_GPIO8_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO8_PUE_MSB _u(3) +#define PADS_BANK0_GPIO8_PUE_LSB _u(3) +#define PADS_BANK0_GPIO8_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO8_PDE_MSB _u(2) +#define PADS_BANK0_GPIO8_PDE_LSB _u(2) +#define PADS_BANK0_GPIO8_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO9 +#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) +#define PADS_BANK0_GPIO9_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO9_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO9_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO9_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO9_ISO_MSB _u(8) +#define PADS_BANK0_GPIO9_ISO_LSB _u(8) +#define PADS_BANK0_GPIO9_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO9_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO9_OD_MSB _u(7) +#define PADS_BANK0_GPIO9_OD_LSB _u(7) +#define PADS_BANK0_GPIO9_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_IE +// Description : Input enable +#define PADS_BANK0_GPIO9_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO9_IE_MSB _u(6) +#define PADS_BANK0_GPIO9_IE_LSB _u(6) +#define PADS_BANK0_GPIO9_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO9_PUE_MSB _u(3) +#define PADS_BANK0_GPIO9_PUE_LSB _u(3) +#define PADS_BANK0_GPIO9_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO9_PDE_MSB _u(2) +#define PADS_BANK0_GPIO9_PDE_LSB _u(2) +#define PADS_BANK0_GPIO9_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO10 +#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) +#define PADS_BANK0_GPIO10_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO10_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO10_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO10_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO10_ISO_MSB _u(8) +#define PADS_BANK0_GPIO10_ISO_LSB _u(8) +#define PADS_BANK0_GPIO10_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO10_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO10_OD_MSB _u(7) +#define PADS_BANK0_GPIO10_OD_LSB _u(7) +#define PADS_BANK0_GPIO10_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_IE +// Description : Input enable +#define PADS_BANK0_GPIO10_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO10_IE_MSB _u(6) +#define PADS_BANK0_GPIO10_IE_LSB _u(6) +#define PADS_BANK0_GPIO10_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO10_PUE_MSB _u(3) +#define PADS_BANK0_GPIO10_PUE_LSB _u(3) +#define PADS_BANK0_GPIO10_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO10_PDE_MSB _u(2) +#define PADS_BANK0_GPIO10_PDE_LSB _u(2) +#define PADS_BANK0_GPIO10_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO11 +#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) +#define PADS_BANK0_GPIO11_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO11_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO11_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO11_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO11_ISO_MSB _u(8) +#define PADS_BANK0_GPIO11_ISO_LSB _u(8) +#define PADS_BANK0_GPIO11_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO11_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO11_OD_MSB _u(7) +#define PADS_BANK0_GPIO11_OD_LSB _u(7) +#define PADS_BANK0_GPIO11_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_IE +// Description : Input enable +#define PADS_BANK0_GPIO11_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO11_IE_MSB _u(6) +#define PADS_BANK0_GPIO11_IE_LSB _u(6) +#define PADS_BANK0_GPIO11_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO11_PUE_MSB _u(3) +#define PADS_BANK0_GPIO11_PUE_LSB _u(3) +#define PADS_BANK0_GPIO11_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO11_PDE_MSB _u(2) +#define PADS_BANK0_GPIO11_PDE_LSB _u(2) +#define PADS_BANK0_GPIO11_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO12 +#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) +#define PADS_BANK0_GPIO12_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO12_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO12_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO12_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO12_ISO_MSB _u(8) +#define PADS_BANK0_GPIO12_ISO_LSB _u(8) +#define PADS_BANK0_GPIO12_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO12_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO12_OD_MSB _u(7) +#define PADS_BANK0_GPIO12_OD_LSB _u(7) +#define PADS_BANK0_GPIO12_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_IE +// Description : Input enable +#define PADS_BANK0_GPIO12_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO12_IE_MSB _u(6) +#define PADS_BANK0_GPIO12_IE_LSB _u(6) +#define PADS_BANK0_GPIO12_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO12_PUE_MSB _u(3) +#define PADS_BANK0_GPIO12_PUE_LSB _u(3) +#define PADS_BANK0_GPIO12_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO12_PDE_MSB _u(2) +#define PADS_BANK0_GPIO12_PDE_LSB _u(2) +#define PADS_BANK0_GPIO12_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO13 +#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) +#define PADS_BANK0_GPIO13_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO13_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO13_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO13_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO13_ISO_MSB _u(8) +#define PADS_BANK0_GPIO13_ISO_LSB _u(8) +#define PADS_BANK0_GPIO13_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO13_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO13_OD_MSB _u(7) +#define PADS_BANK0_GPIO13_OD_LSB _u(7) +#define PADS_BANK0_GPIO13_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_IE +// Description : Input enable +#define PADS_BANK0_GPIO13_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO13_IE_MSB _u(6) +#define PADS_BANK0_GPIO13_IE_LSB _u(6) +#define PADS_BANK0_GPIO13_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO13_PUE_MSB _u(3) +#define PADS_BANK0_GPIO13_PUE_LSB _u(3) +#define PADS_BANK0_GPIO13_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO13_PDE_MSB _u(2) +#define PADS_BANK0_GPIO13_PDE_LSB _u(2) +#define PADS_BANK0_GPIO13_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO14 +#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) +#define PADS_BANK0_GPIO14_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO14_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO14_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO14_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO14_ISO_MSB _u(8) +#define PADS_BANK0_GPIO14_ISO_LSB _u(8) +#define PADS_BANK0_GPIO14_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO14_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO14_OD_MSB _u(7) +#define PADS_BANK0_GPIO14_OD_LSB _u(7) +#define PADS_BANK0_GPIO14_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_IE +// Description : Input enable +#define PADS_BANK0_GPIO14_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO14_IE_MSB _u(6) +#define PADS_BANK0_GPIO14_IE_LSB _u(6) +#define PADS_BANK0_GPIO14_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO14_PUE_MSB _u(3) +#define PADS_BANK0_GPIO14_PUE_LSB _u(3) +#define PADS_BANK0_GPIO14_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO14_PDE_MSB _u(2) +#define PADS_BANK0_GPIO14_PDE_LSB _u(2) +#define PADS_BANK0_GPIO14_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO15 +#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) +#define PADS_BANK0_GPIO15_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO15_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO15_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO15_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO15_ISO_MSB _u(8) +#define PADS_BANK0_GPIO15_ISO_LSB _u(8) +#define PADS_BANK0_GPIO15_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO15_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO15_OD_MSB _u(7) +#define PADS_BANK0_GPIO15_OD_LSB _u(7) +#define PADS_BANK0_GPIO15_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_IE +// Description : Input enable +#define PADS_BANK0_GPIO15_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO15_IE_MSB _u(6) +#define PADS_BANK0_GPIO15_IE_LSB _u(6) +#define PADS_BANK0_GPIO15_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO15_PUE_MSB _u(3) +#define PADS_BANK0_GPIO15_PUE_LSB _u(3) +#define PADS_BANK0_GPIO15_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO15_PDE_MSB _u(2) +#define PADS_BANK0_GPIO15_PDE_LSB _u(2) +#define PADS_BANK0_GPIO15_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO16 +#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) +#define PADS_BANK0_GPIO16_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO16_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO16_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO16_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO16_ISO_MSB _u(8) +#define PADS_BANK0_GPIO16_ISO_LSB _u(8) +#define PADS_BANK0_GPIO16_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO16_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO16_OD_MSB _u(7) +#define PADS_BANK0_GPIO16_OD_LSB _u(7) +#define PADS_BANK0_GPIO16_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_IE +// Description : Input enable +#define PADS_BANK0_GPIO16_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO16_IE_MSB _u(6) +#define PADS_BANK0_GPIO16_IE_LSB _u(6) +#define PADS_BANK0_GPIO16_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO16_PUE_MSB _u(3) +#define PADS_BANK0_GPIO16_PUE_LSB _u(3) +#define PADS_BANK0_GPIO16_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO16_PDE_MSB _u(2) +#define PADS_BANK0_GPIO16_PDE_LSB _u(2) +#define PADS_BANK0_GPIO16_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO17 +#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) +#define PADS_BANK0_GPIO17_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO17_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO17_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO17_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO17_ISO_MSB _u(8) +#define PADS_BANK0_GPIO17_ISO_LSB _u(8) +#define PADS_BANK0_GPIO17_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO17_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO17_OD_MSB _u(7) +#define PADS_BANK0_GPIO17_OD_LSB _u(7) +#define PADS_BANK0_GPIO17_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_IE +// Description : Input enable +#define PADS_BANK0_GPIO17_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO17_IE_MSB _u(6) +#define PADS_BANK0_GPIO17_IE_LSB _u(6) +#define PADS_BANK0_GPIO17_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO17_PUE_MSB _u(3) +#define PADS_BANK0_GPIO17_PUE_LSB _u(3) +#define PADS_BANK0_GPIO17_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO17_PDE_MSB _u(2) +#define PADS_BANK0_GPIO17_PDE_LSB _u(2) +#define PADS_BANK0_GPIO17_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO18 +#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) +#define PADS_BANK0_GPIO18_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO18_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO18_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO18_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO18_ISO_MSB _u(8) +#define PADS_BANK0_GPIO18_ISO_LSB _u(8) +#define PADS_BANK0_GPIO18_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO18_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO18_OD_MSB _u(7) +#define PADS_BANK0_GPIO18_OD_LSB _u(7) +#define PADS_BANK0_GPIO18_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_IE +// Description : Input enable +#define PADS_BANK0_GPIO18_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO18_IE_MSB _u(6) +#define PADS_BANK0_GPIO18_IE_LSB _u(6) +#define PADS_BANK0_GPIO18_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO18_PUE_MSB _u(3) +#define PADS_BANK0_GPIO18_PUE_LSB _u(3) +#define PADS_BANK0_GPIO18_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO18_PDE_MSB _u(2) +#define PADS_BANK0_GPIO18_PDE_LSB _u(2) +#define PADS_BANK0_GPIO18_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO19 +#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) +#define PADS_BANK0_GPIO19_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO19_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO19_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO19_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO19_ISO_MSB _u(8) +#define PADS_BANK0_GPIO19_ISO_LSB _u(8) +#define PADS_BANK0_GPIO19_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO19_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO19_OD_MSB _u(7) +#define PADS_BANK0_GPIO19_OD_LSB _u(7) +#define PADS_BANK0_GPIO19_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_IE +// Description : Input enable +#define PADS_BANK0_GPIO19_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO19_IE_MSB _u(6) +#define PADS_BANK0_GPIO19_IE_LSB _u(6) +#define PADS_BANK0_GPIO19_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO19_PUE_MSB _u(3) +#define PADS_BANK0_GPIO19_PUE_LSB _u(3) +#define PADS_BANK0_GPIO19_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO19_PDE_MSB _u(2) +#define PADS_BANK0_GPIO19_PDE_LSB _u(2) +#define PADS_BANK0_GPIO19_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO20 +#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) +#define PADS_BANK0_GPIO20_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO20_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO20_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO20_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO20_ISO_MSB _u(8) +#define PADS_BANK0_GPIO20_ISO_LSB _u(8) +#define PADS_BANK0_GPIO20_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO20_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO20_OD_MSB _u(7) +#define PADS_BANK0_GPIO20_OD_LSB _u(7) +#define PADS_BANK0_GPIO20_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_IE +// Description : Input enable +#define PADS_BANK0_GPIO20_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO20_IE_MSB _u(6) +#define PADS_BANK0_GPIO20_IE_LSB _u(6) +#define PADS_BANK0_GPIO20_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO20_PUE_MSB _u(3) +#define PADS_BANK0_GPIO20_PUE_LSB _u(3) +#define PADS_BANK0_GPIO20_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO20_PDE_MSB _u(2) +#define PADS_BANK0_GPIO20_PDE_LSB _u(2) +#define PADS_BANK0_GPIO20_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO21 +#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) +#define PADS_BANK0_GPIO21_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO21_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO21_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO21_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO21_ISO_MSB _u(8) +#define PADS_BANK0_GPIO21_ISO_LSB _u(8) +#define PADS_BANK0_GPIO21_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO21_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO21_OD_MSB _u(7) +#define PADS_BANK0_GPIO21_OD_LSB _u(7) +#define PADS_BANK0_GPIO21_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_IE +// Description : Input enable +#define PADS_BANK0_GPIO21_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO21_IE_MSB _u(6) +#define PADS_BANK0_GPIO21_IE_LSB _u(6) +#define PADS_BANK0_GPIO21_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO21_PUE_MSB _u(3) +#define PADS_BANK0_GPIO21_PUE_LSB _u(3) +#define PADS_BANK0_GPIO21_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO21_PDE_MSB _u(2) +#define PADS_BANK0_GPIO21_PDE_LSB _u(2) +#define PADS_BANK0_GPIO21_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO22 +#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) +#define PADS_BANK0_GPIO22_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO22_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO22_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO22_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO22_ISO_MSB _u(8) +#define PADS_BANK0_GPIO22_ISO_LSB _u(8) +#define PADS_BANK0_GPIO22_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO22_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO22_OD_MSB _u(7) +#define PADS_BANK0_GPIO22_OD_LSB _u(7) +#define PADS_BANK0_GPIO22_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_IE +// Description : Input enable +#define PADS_BANK0_GPIO22_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO22_IE_MSB _u(6) +#define PADS_BANK0_GPIO22_IE_LSB _u(6) +#define PADS_BANK0_GPIO22_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO22_PUE_MSB _u(3) +#define PADS_BANK0_GPIO22_PUE_LSB _u(3) +#define PADS_BANK0_GPIO22_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO22_PDE_MSB _u(2) +#define PADS_BANK0_GPIO22_PDE_LSB _u(2) +#define PADS_BANK0_GPIO22_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO23 +#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) +#define PADS_BANK0_GPIO23_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO23_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO23_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO23_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO23_ISO_MSB _u(8) +#define PADS_BANK0_GPIO23_ISO_LSB _u(8) +#define PADS_BANK0_GPIO23_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO23_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO23_OD_MSB _u(7) +#define PADS_BANK0_GPIO23_OD_LSB _u(7) +#define PADS_BANK0_GPIO23_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_IE +// Description : Input enable +#define PADS_BANK0_GPIO23_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO23_IE_MSB _u(6) +#define PADS_BANK0_GPIO23_IE_LSB _u(6) +#define PADS_BANK0_GPIO23_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO23_PUE_MSB _u(3) +#define PADS_BANK0_GPIO23_PUE_LSB _u(3) +#define PADS_BANK0_GPIO23_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO23_PDE_MSB _u(2) +#define PADS_BANK0_GPIO23_PDE_LSB _u(2) +#define PADS_BANK0_GPIO23_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO24 +#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) +#define PADS_BANK0_GPIO24_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO24_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO24_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO24_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO24_ISO_MSB _u(8) +#define PADS_BANK0_GPIO24_ISO_LSB _u(8) +#define PADS_BANK0_GPIO24_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO24_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO24_OD_MSB _u(7) +#define PADS_BANK0_GPIO24_OD_LSB _u(7) +#define PADS_BANK0_GPIO24_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_IE +// Description : Input enable +#define PADS_BANK0_GPIO24_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO24_IE_MSB _u(6) +#define PADS_BANK0_GPIO24_IE_LSB _u(6) +#define PADS_BANK0_GPIO24_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO24_PUE_MSB _u(3) +#define PADS_BANK0_GPIO24_PUE_LSB _u(3) +#define PADS_BANK0_GPIO24_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO24_PDE_MSB _u(2) +#define PADS_BANK0_GPIO24_PDE_LSB _u(2) +#define PADS_BANK0_GPIO24_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO25 +#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) +#define PADS_BANK0_GPIO25_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO25_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO25_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO25_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO25_ISO_MSB _u(8) +#define PADS_BANK0_GPIO25_ISO_LSB _u(8) +#define PADS_BANK0_GPIO25_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO25_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO25_OD_MSB _u(7) +#define PADS_BANK0_GPIO25_OD_LSB _u(7) +#define PADS_BANK0_GPIO25_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_IE +// Description : Input enable +#define PADS_BANK0_GPIO25_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO25_IE_MSB _u(6) +#define PADS_BANK0_GPIO25_IE_LSB _u(6) +#define PADS_BANK0_GPIO25_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO25_PUE_MSB _u(3) +#define PADS_BANK0_GPIO25_PUE_LSB _u(3) +#define PADS_BANK0_GPIO25_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO25_PDE_MSB _u(2) +#define PADS_BANK0_GPIO25_PDE_LSB _u(2) +#define PADS_BANK0_GPIO25_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO26 +#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) +#define PADS_BANK0_GPIO26_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO26_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO26_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO26_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO26_ISO_MSB _u(8) +#define PADS_BANK0_GPIO26_ISO_LSB _u(8) +#define PADS_BANK0_GPIO26_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO26_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO26_OD_MSB _u(7) +#define PADS_BANK0_GPIO26_OD_LSB _u(7) +#define PADS_BANK0_GPIO26_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_IE +// Description : Input enable +#define PADS_BANK0_GPIO26_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO26_IE_MSB _u(6) +#define PADS_BANK0_GPIO26_IE_LSB _u(6) +#define PADS_BANK0_GPIO26_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO26_PUE_MSB _u(3) +#define PADS_BANK0_GPIO26_PUE_LSB _u(3) +#define PADS_BANK0_GPIO26_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO26_PDE_MSB _u(2) +#define PADS_BANK0_GPIO26_PDE_LSB _u(2) +#define PADS_BANK0_GPIO26_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO27 +#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) +#define PADS_BANK0_GPIO27_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO27_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO27_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO27_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO27_ISO_MSB _u(8) +#define PADS_BANK0_GPIO27_ISO_LSB _u(8) +#define PADS_BANK0_GPIO27_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO27_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO27_OD_MSB _u(7) +#define PADS_BANK0_GPIO27_OD_LSB _u(7) +#define PADS_BANK0_GPIO27_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_IE +// Description : Input enable +#define PADS_BANK0_GPIO27_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO27_IE_MSB _u(6) +#define PADS_BANK0_GPIO27_IE_LSB _u(6) +#define PADS_BANK0_GPIO27_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO27_PUE_MSB _u(3) +#define PADS_BANK0_GPIO27_PUE_LSB _u(3) +#define PADS_BANK0_GPIO27_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO27_PDE_MSB _u(2) +#define PADS_BANK0_GPIO27_PDE_LSB _u(2) +#define PADS_BANK0_GPIO27_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO28 +#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) +#define PADS_BANK0_GPIO28_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO28_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO28_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO28_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO28_ISO_MSB _u(8) +#define PADS_BANK0_GPIO28_ISO_LSB _u(8) +#define PADS_BANK0_GPIO28_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO28_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO28_OD_MSB _u(7) +#define PADS_BANK0_GPIO28_OD_LSB _u(7) +#define PADS_BANK0_GPIO28_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_IE +// Description : Input enable +#define PADS_BANK0_GPIO28_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO28_IE_MSB _u(6) +#define PADS_BANK0_GPIO28_IE_LSB _u(6) +#define PADS_BANK0_GPIO28_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO28_PUE_MSB _u(3) +#define PADS_BANK0_GPIO28_PUE_LSB _u(3) +#define PADS_BANK0_GPIO28_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO28_PDE_MSB _u(2) +#define PADS_BANK0_GPIO28_PDE_LSB _u(2) +#define PADS_BANK0_GPIO28_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO29 +#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) +#define PADS_BANK0_GPIO29_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO29_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO29_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO29_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO29_ISO_MSB _u(8) +#define PADS_BANK0_GPIO29_ISO_LSB _u(8) +#define PADS_BANK0_GPIO29_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO29_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO29_OD_MSB _u(7) +#define PADS_BANK0_GPIO29_OD_LSB _u(7) +#define PADS_BANK0_GPIO29_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_IE +// Description : Input enable +#define PADS_BANK0_GPIO29_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO29_IE_MSB _u(6) +#define PADS_BANK0_GPIO29_IE_LSB _u(6) +#define PADS_BANK0_GPIO29_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO29_PUE_MSB _u(3) +#define PADS_BANK0_GPIO29_PUE_LSB _u(3) +#define PADS_BANK0_GPIO29_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO29_PDE_MSB _u(2) +#define PADS_BANK0_GPIO29_PDE_LSB _u(2) +#define PADS_BANK0_GPIO29_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO30 +#define PADS_BANK0_GPIO30_OFFSET _u(0x0000007c) +#define PADS_BANK0_GPIO30_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO30_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO30_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO30_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO30_ISO_MSB _u(8) +#define PADS_BANK0_GPIO30_ISO_LSB _u(8) +#define PADS_BANK0_GPIO30_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO30_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO30_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO30_OD_MSB _u(7) +#define PADS_BANK0_GPIO30_OD_LSB _u(7) +#define PADS_BANK0_GPIO30_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_IE +// Description : Input enable +#define PADS_BANK0_GPIO30_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO30_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO30_IE_MSB _u(6) +#define PADS_BANK0_GPIO30_IE_LSB _u(6) +#define PADS_BANK0_GPIO30_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO30_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO30_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO30_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO30_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO30_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO30_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO30_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO30_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO30_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO30_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO30_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO30_PUE_MSB _u(3) +#define PADS_BANK0_GPIO30_PUE_LSB _u(3) +#define PADS_BANK0_GPIO30_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO30_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO30_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO30_PDE_MSB _u(2) +#define PADS_BANK0_GPIO30_PDE_LSB _u(2) +#define PADS_BANK0_GPIO30_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO30_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO30_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO30_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO30_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO30_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO30_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO30_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO30_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO30_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO30_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO31 +#define PADS_BANK0_GPIO31_OFFSET _u(0x00000080) +#define PADS_BANK0_GPIO31_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO31_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO31_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO31_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO31_ISO_MSB _u(8) +#define PADS_BANK0_GPIO31_ISO_LSB _u(8) +#define PADS_BANK0_GPIO31_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO31_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO31_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO31_OD_MSB _u(7) +#define PADS_BANK0_GPIO31_OD_LSB _u(7) +#define PADS_BANK0_GPIO31_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_IE +// Description : Input enable +#define PADS_BANK0_GPIO31_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO31_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO31_IE_MSB _u(6) +#define PADS_BANK0_GPIO31_IE_LSB _u(6) +#define PADS_BANK0_GPIO31_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO31_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO31_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO31_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO31_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO31_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO31_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO31_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO31_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO31_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO31_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO31_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO31_PUE_MSB _u(3) +#define PADS_BANK0_GPIO31_PUE_LSB _u(3) +#define PADS_BANK0_GPIO31_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO31_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO31_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO31_PDE_MSB _u(2) +#define PADS_BANK0_GPIO31_PDE_LSB _u(2) +#define PADS_BANK0_GPIO31_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO31_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO31_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO31_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO31_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO31_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO31_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO31_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO31_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO31_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO31_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO32 +#define PADS_BANK0_GPIO32_OFFSET _u(0x00000084) +#define PADS_BANK0_GPIO32_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO32_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO32_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO32_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO32_ISO_MSB _u(8) +#define PADS_BANK0_GPIO32_ISO_LSB _u(8) +#define PADS_BANK0_GPIO32_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO32_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO32_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO32_OD_MSB _u(7) +#define PADS_BANK0_GPIO32_OD_LSB _u(7) +#define PADS_BANK0_GPIO32_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_IE +// Description : Input enable +#define PADS_BANK0_GPIO32_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO32_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO32_IE_MSB _u(6) +#define PADS_BANK0_GPIO32_IE_LSB _u(6) +#define PADS_BANK0_GPIO32_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO32_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO32_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO32_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO32_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO32_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO32_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO32_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO32_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO32_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO32_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO32_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO32_PUE_MSB _u(3) +#define PADS_BANK0_GPIO32_PUE_LSB _u(3) +#define PADS_BANK0_GPIO32_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO32_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO32_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO32_PDE_MSB _u(2) +#define PADS_BANK0_GPIO32_PDE_LSB _u(2) +#define PADS_BANK0_GPIO32_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO32_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO32_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO32_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO32_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO32_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO32_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO32_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO32_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO32_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO32_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO33 +#define PADS_BANK0_GPIO33_OFFSET _u(0x00000088) +#define PADS_BANK0_GPIO33_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO33_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO33_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO33_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO33_ISO_MSB _u(8) +#define PADS_BANK0_GPIO33_ISO_LSB _u(8) +#define PADS_BANK0_GPIO33_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO33_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO33_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO33_OD_MSB _u(7) +#define PADS_BANK0_GPIO33_OD_LSB _u(7) +#define PADS_BANK0_GPIO33_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_IE +// Description : Input enable +#define PADS_BANK0_GPIO33_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO33_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO33_IE_MSB _u(6) +#define PADS_BANK0_GPIO33_IE_LSB _u(6) +#define PADS_BANK0_GPIO33_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO33_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO33_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO33_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO33_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO33_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO33_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO33_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO33_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO33_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO33_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO33_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO33_PUE_MSB _u(3) +#define PADS_BANK0_GPIO33_PUE_LSB _u(3) +#define PADS_BANK0_GPIO33_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO33_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO33_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO33_PDE_MSB _u(2) +#define PADS_BANK0_GPIO33_PDE_LSB _u(2) +#define PADS_BANK0_GPIO33_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO33_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO33_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO33_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO33_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO33_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO33_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO33_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO33_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO33_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO33_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO34 +#define PADS_BANK0_GPIO34_OFFSET _u(0x0000008c) +#define PADS_BANK0_GPIO34_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO34_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO34_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO34_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO34_ISO_MSB _u(8) +#define PADS_BANK0_GPIO34_ISO_LSB _u(8) +#define PADS_BANK0_GPIO34_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO34_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO34_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO34_OD_MSB _u(7) +#define PADS_BANK0_GPIO34_OD_LSB _u(7) +#define PADS_BANK0_GPIO34_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_IE +// Description : Input enable +#define PADS_BANK0_GPIO34_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO34_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO34_IE_MSB _u(6) +#define PADS_BANK0_GPIO34_IE_LSB _u(6) +#define PADS_BANK0_GPIO34_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO34_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO34_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO34_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO34_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO34_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO34_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO34_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO34_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO34_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO34_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO34_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO34_PUE_MSB _u(3) +#define PADS_BANK0_GPIO34_PUE_LSB _u(3) +#define PADS_BANK0_GPIO34_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO34_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO34_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO34_PDE_MSB _u(2) +#define PADS_BANK0_GPIO34_PDE_LSB _u(2) +#define PADS_BANK0_GPIO34_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO34_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO34_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO34_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO34_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO34_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO34_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO34_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO34_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO34_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO34_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO35 +#define PADS_BANK0_GPIO35_OFFSET _u(0x00000090) +#define PADS_BANK0_GPIO35_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO35_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO35_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO35_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO35_ISO_MSB _u(8) +#define PADS_BANK0_GPIO35_ISO_LSB _u(8) +#define PADS_BANK0_GPIO35_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO35_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO35_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO35_OD_MSB _u(7) +#define PADS_BANK0_GPIO35_OD_LSB _u(7) +#define PADS_BANK0_GPIO35_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_IE +// Description : Input enable +#define PADS_BANK0_GPIO35_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO35_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO35_IE_MSB _u(6) +#define PADS_BANK0_GPIO35_IE_LSB _u(6) +#define PADS_BANK0_GPIO35_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO35_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO35_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO35_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO35_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO35_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO35_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO35_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO35_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO35_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO35_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO35_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO35_PUE_MSB _u(3) +#define PADS_BANK0_GPIO35_PUE_LSB _u(3) +#define PADS_BANK0_GPIO35_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO35_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO35_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO35_PDE_MSB _u(2) +#define PADS_BANK0_GPIO35_PDE_LSB _u(2) +#define PADS_BANK0_GPIO35_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO35_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO35_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO35_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO35_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO35_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO35_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO35_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO35_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO35_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO35_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO36 +#define PADS_BANK0_GPIO36_OFFSET _u(0x00000094) +#define PADS_BANK0_GPIO36_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO36_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO36_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO36_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO36_ISO_MSB _u(8) +#define PADS_BANK0_GPIO36_ISO_LSB _u(8) +#define PADS_BANK0_GPIO36_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO36_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO36_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO36_OD_MSB _u(7) +#define PADS_BANK0_GPIO36_OD_LSB _u(7) +#define PADS_BANK0_GPIO36_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_IE +// Description : Input enable +#define PADS_BANK0_GPIO36_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO36_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO36_IE_MSB _u(6) +#define PADS_BANK0_GPIO36_IE_LSB _u(6) +#define PADS_BANK0_GPIO36_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO36_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO36_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO36_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO36_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO36_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO36_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO36_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO36_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO36_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO36_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO36_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO36_PUE_MSB _u(3) +#define PADS_BANK0_GPIO36_PUE_LSB _u(3) +#define PADS_BANK0_GPIO36_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO36_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO36_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO36_PDE_MSB _u(2) +#define PADS_BANK0_GPIO36_PDE_LSB _u(2) +#define PADS_BANK0_GPIO36_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO36_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO36_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO36_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO36_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO36_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO36_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO36_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO36_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO36_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO36_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO37 +#define PADS_BANK0_GPIO37_OFFSET _u(0x00000098) +#define PADS_BANK0_GPIO37_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO37_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO37_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO37_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO37_ISO_MSB _u(8) +#define PADS_BANK0_GPIO37_ISO_LSB _u(8) +#define PADS_BANK0_GPIO37_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO37_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO37_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO37_OD_MSB _u(7) +#define PADS_BANK0_GPIO37_OD_LSB _u(7) +#define PADS_BANK0_GPIO37_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_IE +// Description : Input enable +#define PADS_BANK0_GPIO37_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO37_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO37_IE_MSB _u(6) +#define PADS_BANK0_GPIO37_IE_LSB _u(6) +#define PADS_BANK0_GPIO37_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO37_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO37_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO37_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO37_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO37_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO37_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO37_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO37_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO37_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO37_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO37_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO37_PUE_MSB _u(3) +#define PADS_BANK0_GPIO37_PUE_LSB _u(3) +#define PADS_BANK0_GPIO37_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO37_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO37_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO37_PDE_MSB _u(2) +#define PADS_BANK0_GPIO37_PDE_LSB _u(2) +#define PADS_BANK0_GPIO37_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO37_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO37_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO37_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO37_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO37_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO37_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO37_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO37_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO37_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO37_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO38 +#define PADS_BANK0_GPIO38_OFFSET _u(0x0000009c) +#define PADS_BANK0_GPIO38_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO38_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO38_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO38_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO38_ISO_MSB _u(8) +#define PADS_BANK0_GPIO38_ISO_LSB _u(8) +#define PADS_BANK0_GPIO38_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO38_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO38_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO38_OD_MSB _u(7) +#define PADS_BANK0_GPIO38_OD_LSB _u(7) +#define PADS_BANK0_GPIO38_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_IE +// Description : Input enable +#define PADS_BANK0_GPIO38_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO38_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO38_IE_MSB _u(6) +#define PADS_BANK0_GPIO38_IE_LSB _u(6) +#define PADS_BANK0_GPIO38_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO38_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO38_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO38_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO38_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO38_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO38_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO38_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO38_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO38_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO38_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO38_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO38_PUE_MSB _u(3) +#define PADS_BANK0_GPIO38_PUE_LSB _u(3) +#define PADS_BANK0_GPIO38_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO38_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO38_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO38_PDE_MSB _u(2) +#define PADS_BANK0_GPIO38_PDE_LSB _u(2) +#define PADS_BANK0_GPIO38_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO38_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO38_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO38_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO38_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO38_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO38_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO38_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO38_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO38_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO38_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO39 +#define PADS_BANK0_GPIO39_OFFSET _u(0x000000a0) +#define PADS_BANK0_GPIO39_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO39_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO39_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO39_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO39_ISO_MSB _u(8) +#define PADS_BANK0_GPIO39_ISO_LSB _u(8) +#define PADS_BANK0_GPIO39_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO39_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO39_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO39_OD_MSB _u(7) +#define PADS_BANK0_GPIO39_OD_LSB _u(7) +#define PADS_BANK0_GPIO39_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_IE +// Description : Input enable +#define PADS_BANK0_GPIO39_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO39_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO39_IE_MSB _u(6) +#define PADS_BANK0_GPIO39_IE_LSB _u(6) +#define PADS_BANK0_GPIO39_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO39_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO39_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO39_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO39_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO39_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO39_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO39_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO39_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO39_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO39_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO39_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO39_PUE_MSB _u(3) +#define PADS_BANK0_GPIO39_PUE_LSB _u(3) +#define PADS_BANK0_GPIO39_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO39_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO39_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO39_PDE_MSB _u(2) +#define PADS_BANK0_GPIO39_PDE_LSB _u(2) +#define PADS_BANK0_GPIO39_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO39_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO39_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO39_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO39_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO39_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO39_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO39_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO39_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO39_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO39_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO40 +#define PADS_BANK0_GPIO40_OFFSET _u(0x000000a4) +#define PADS_BANK0_GPIO40_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO40_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO40_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO40_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO40_ISO_MSB _u(8) +#define PADS_BANK0_GPIO40_ISO_LSB _u(8) +#define PADS_BANK0_GPIO40_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO40_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO40_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO40_OD_MSB _u(7) +#define PADS_BANK0_GPIO40_OD_LSB _u(7) +#define PADS_BANK0_GPIO40_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_IE +// Description : Input enable +#define PADS_BANK0_GPIO40_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO40_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO40_IE_MSB _u(6) +#define PADS_BANK0_GPIO40_IE_LSB _u(6) +#define PADS_BANK0_GPIO40_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO40_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO40_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO40_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO40_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO40_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO40_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO40_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO40_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO40_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO40_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO40_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO40_PUE_MSB _u(3) +#define PADS_BANK0_GPIO40_PUE_LSB _u(3) +#define PADS_BANK0_GPIO40_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO40_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO40_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO40_PDE_MSB _u(2) +#define PADS_BANK0_GPIO40_PDE_LSB _u(2) +#define PADS_BANK0_GPIO40_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO40_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO40_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO40_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO40_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO40_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO40_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO40_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO40_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO40_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO40_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO41 +#define PADS_BANK0_GPIO41_OFFSET _u(0x000000a8) +#define PADS_BANK0_GPIO41_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO41_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO41_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO41_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO41_ISO_MSB _u(8) +#define PADS_BANK0_GPIO41_ISO_LSB _u(8) +#define PADS_BANK0_GPIO41_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO41_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO41_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO41_OD_MSB _u(7) +#define PADS_BANK0_GPIO41_OD_LSB _u(7) +#define PADS_BANK0_GPIO41_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_IE +// Description : Input enable +#define PADS_BANK0_GPIO41_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO41_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO41_IE_MSB _u(6) +#define PADS_BANK0_GPIO41_IE_LSB _u(6) +#define PADS_BANK0_GPIO41_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO41_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO41_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO41_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO41_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO41_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO41_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO41_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO41_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO41_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO41_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO41_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO41_PUE_MSB _u(3) +#define PADS_BANK0_GPIO41_PUE_LSB _u(3) +#define PADS_BANK0_GPIO41_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO41_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO41_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO41_PDE_MSB _u(2) +#define PADS_BANK0_GPIO41_PDE_LSB _u(2) +#define PADS_BANK0_GPIO41_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO41_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO41_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO41_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO41_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO41_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO41_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO41_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO41_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO41_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO41_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO42 +#define PADS_BANK0_GPIO42_OFFSET _u(0x000000ac) +#define PADS_BANK0_GPIO42_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO42_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO42_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO42_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO42_ISO_MSB _u(8) +#define PADS_BANK0_GPIO42_ISO_LSB _u(8) +#define PADS_BANK0_GPIO42_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO42_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO42_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO42_OD_MSB _u(7) +#define PADS_BANK0_GPIO42_OD_LSB _u(7) +#define PADS_BANK0_GPIO42_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_IE +// Description : Input enable +#define PADS_BANK0_GPIO42_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO42_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO42_IE_MSB _u(6) +#define PADS_BANK0_GPIO42_IE_LSB _u(6) +#define PADS_BANK0_GPIO42_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO42_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO42_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO42_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO42_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO42_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO42_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO42_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO42_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO42_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO42_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO42_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO42_PUE_MSB _u(3) +#define PADS_BANK0_GPIO42_PUE_LSB _u(3) +#define PADS_BANK0_GPIO42_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO42_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO42_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO42_PDE_MSB _u(2) +#define PADS_BANK0_GPIO42_PDE_LSB _u(2) +#define PADS_BANK0_GPIO42_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO42_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO42_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO42_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO42_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO42_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO42_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO42_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO42_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO42_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO42_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO43 +#define PADS_BANK0_GPIO43_OFFSET _u(0x000000b0) +#define PADS_BANK0_GPIO43_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO43_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO43_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO43_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO43_ISO_MSB _u(8) +#define PADS_BANK0_GPIO43_ISO_LSB _u(8) +#define PADS_BANK0_GPIO43_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO43_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO43_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO43_OD_MSB _u(7) +#define PADS_BANK0_GPIO43_OD_LSB _u(7) +#define PADS_BANK0_GPIO43_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_IE +// Description : Input enable +#define PADS_BANK0_GPIO43_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO43_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO43_IE_MSB _u(6) +#define PADS_BANK0_GPIO43_IE_LSB _u(6) +#define PADS_BANK0_GPIO43_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO43_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO43_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO43_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO43_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO43_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO43_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO43_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO43_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO43_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO43_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO43_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO43_PUE_MSB _u(3) +#define PADS_BANK0_GPIO43_PUE_LSB _u(3) +#define PADS_BANK0_GPIO43_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO43_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO43_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO43_PDE_MSB _u(2) +#define PADS_BANK0_GPIO43_PDE_LSB _u(2) +#define PADS_BANK0_GPIO43_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO43_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO43_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO43_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO43_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO43_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO43_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO43_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO43_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO43_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO43_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO44 +#define PADS_BANK0_GPIO44_OFFSET _u(0x000000b4) +#define PADS_BANK0_GPIO44_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO44_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO44_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO44_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO44_ISO_MSB _u(8) +#define PADS_BANK0_GPIO44_ISO_LSB _u(8) +#define PADS_BANK0_GPIO44_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO44_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO44_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO44_OD_MSB _u(7) +#define PADS_BANK0_GPIO44_OD_LSB _u(7) +#define PADS_BANK0_GPIO44_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_IE +// Description : Input enable +#define PADS_BANK0_GPIO44_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO44_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO44_IE_MSB _u(6) +#define PADS_BANK0_GPIO44_IE_LSB _u(6) +#define PADS_BANK0_GPIO44_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO44_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO44_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO44_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO44_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO44_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO44_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO44_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO44_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO44_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO44_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO44_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO44_PUE_MSB _u(3) +#define PADS_BANK0_GPIO44_PUE_LSB _u(3) +#define PADS_BANK0_GPIO44_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO44_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO44_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO44_PDE_MSB _u(2) +#define PADS_BANK0_GPIO44_PDE_LSB _u(2) +#define PADS_BANK0_GPIO44_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO44_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO44_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO44_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO44_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO44_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO44_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO44_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO44_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO44_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO44_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO45 +#define PADS_BANK0_GPIO45_OFFSET _u(0x000000b8) +#define PADS_BANK0_GPIO45_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO45_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO45_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO45_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO45_ISO_MSB _u(8) +#define PADS_BANK0_GPIO45_ISO_LSB _u(8) +#define PADS_BANK0_GPIO45_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO45_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO45_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO45_OD_MSB _u(7) +#define PADS_BANK0_GPIO45_OD_LSB _u(7) +#define PADS_BANK0_GPIO45_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_IE +// Description : Input enable +#define PADS_BANK0_GPIO45_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO45_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO45_IE_MSB _u(6) +#define PADS_BANK0_GPIO45_IE_LSB _u(6) +#define PADS_BANK0_GPIO45_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO45_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO45_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO45_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO45_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO45_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO45_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO45_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO45_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO45_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO45_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO45_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO45_PUE_MSB _u(3) +#define PADS_BANK0_GPIO45_PUE_LSB _u(3) +#define PADS_BANK0_GPIO45_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO45_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO45_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO45_PDE_MSB _u(2) +#define PADS_BANK0_GPIO45_PDE_LSB _u(2) +#define PADS_BANK0_GPIO45_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO45_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO45_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO45_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO45_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO45_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO45_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO45_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO45_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO45_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO45_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO46 +#define PADS_BANK0_GPIO46_OFFSET _u(0x000000bc) +#define PADS_BANK0_GPIO46_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO46_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO46_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO46_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO46_ISO_MSB _u(8) +#define PADS_BANK0_GPIO46_ISO_LSB _u(8) +#define PADS_BANK0_GPIO46_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO46_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO46_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO46_OD_MSB _u(7) +#define PADS_BANK0_GPIO46_OD_LSB _u(7) +#define PADS_BANK0_GPIO46_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_IE +// Description : Input enable +#define PADS_BANK0_GPIO46_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO46_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO46_IE_MSB _u(6) +#define PADS_BANK0_GPIO46_IE_LSB _u(6) +#define PADS_BANK0_GPIO46_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO46_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO46_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO46_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO46_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO46_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO46_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO46_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO46_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO46_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO46_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO46_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO46_PUE_MSB _u(3) +#define PADS_BANK0_GPIO46_PUE_LSB _u(3) +#define PADS_BANK0_GPIO46_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO46_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO46_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO46_PDE_MSB _u(2) +#define PADS_BANK0_GPIO46_PDE_LSB _u(2) +#define PADS_BANK0_GPIO46_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO46_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO46_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO46_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO46_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO46_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO46_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO46_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO46_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO46_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO46_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO47 +#define PADS_BANK0_GPIO47_OFFSET _u(0x000000c0) +#define PADS_BANK0_GPIO47_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO47_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO47_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO47_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO47_ISO_MSB _u(8) +#define PADS_BANK0_GPIO47_ISO_LSB _u(8) +#define PADS_BANK0_GPIO47_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO47_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO47_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO47_OD_MSB _u(7) +#define PADS_BANK0_GPIO47_OD_LSB _u(7) +#define PADS_BANK0_GPIO47_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_IE +// Description : Input enable +#define PADS_BANK0_GPIO47_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO47_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO47_IE_MSB _u(6) +#define PADS_BANK0_GPIO47_IE_LSB _u(6) +#define PADS_BANK0_GPIO47_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO47_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO47_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO47_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO47_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO47_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO47_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO47_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO47_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO47_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO47_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO47_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO47_PUE_MSB _u(3) +#define PADS_BANK0_GPIO47_PUE_LSB _u(3) +#define PADS_BANK0_GPIO47_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO47_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO47_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO47_PDE_MSB _u(2) +#define PADS_BANK0_GPIO47_PDE_LSB _u(2) +#define PADS_BANK0_GPIO47_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO47_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO47_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO47_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO47_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO47_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO47_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO47_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO47_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO47_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO47_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWCLK +#define PADS_BANK0_SWCLK_OFFSET _u(0x000000c4) +#define PADS_BANK0_SWCLK_BITS _u(0x000001ff) +#define PADS_BANK0_SWCLK_RESET _u(0x0000005a) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_SWCLK_ISO_RESET _u(0x0) +#define PADS_BANK0_SWCLK_ISO_BITS _u(0x00000100) +#define PADS_BANK0_SWCLK_ISO_MSB _u(8) +#define PADS_BANK0_SWCLK_ISO_LSB _u(8) +#define PADS_BANK0_SWCLK_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWCLK_OD_RESET _u(0x0) +#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWCLK_OD_MSB _u(7) +#define PADS_BANK0_SWCLK_OD_LSB _u(7) +#define PADS_BANK0_SWCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_IE +// Description : Input enable +#define PADS_BANK0_SWCLK_IE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWCLK_IE_MSB _u(6) +#define PADS_BANK0_SWCLK_IE_LSB _u(6) +#define PADS_BANK0_SWCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) +#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) +#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PUE +// Description : Pull up enable +#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWCLK_PUE_MSB _u(3) +#define PADS_BANK0_SWCLK_PUE_LSB _u(3) +#define PADS_BANK0_SWCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PDE +// Description : Pull down enable +#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) +#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWCLK_PDE_MSB _u(2) +#define PADS_BANK0_SWCLK_PDE_LSB _u(2) +#define PADS_BANK0_SWCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) +#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) +#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWD +#define PADS_BANK0_SWD_OFFSET _u(0x000000c8) +#define PADS_BANK0_SWD_BITS _u(0x000001ff) +#define PADS_BANK0_SWD_RESET _u(0x0000005a) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_SWD_ISO_RESET _u(0x0) +#define PADS_BANK0_SWD_ISO_BITS _u(0x00000100) +#define PADS_BANK0_SWD_ISO_MSB _u(8) +#define PADS_BANK0_SWD_ISO_LSB _u(8) +#define PADS_BANK0_SWD_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWD_OD_RESET _u(0x0) +#define PADS_BANK0_SWD_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWD_OD_MSB _u(7) +#define PADS_BANK0_SWD_OD_LSB _u(7) +#define PADS_BANK0_SWD_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_IE +// Description : Input enable +#define PADS_BANK0_SWD_IE_RESET _u(0x1) +#define PADS_BANK0_SWD_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWD_IE_MSB _u(6) +#define PADS_BANK0_SWD_IE_LSB _u(6) +#define PADS_BANK0_SWD_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWD_DRIVE_MSB _u(5) +#define PADS_BANK0_SWD_DRIVE_LSB _u(4) +#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PUE +// Description : Pull up enable +#define PADS_BANK0_SWD_PUE_RESET _u(0x1) +#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWD_PUE_MSB _u(3) +#define PADS_BANK0_SWD_PUE_LSB _u(3) +#define PADS_BANK0_SWD_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PDE +// Description : Pull down enable +#define PADS_BANK0_SWD_PDE_RESET _u(0x0) +#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWD_PDE_MSB _u(2) +#define PADS_BANK0_SWD_PDE_LSB _u(2) +#define PADS_BANK0_SWD_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWD_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWD_SCHMITT_LSB _u(1) +#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) +#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_PADS_BANK0_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/pads_qspi.h b/src/rp2350/hardware_regs/include/hardware/regs/pads_qspi.h new file mode 100644 index 000000000..5e31fd042 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/pads_qspi.h @@ -0,0 +1,504 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_QSPI +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PADS_QSPI_H +#define _HARDWARE_REGS_PADS_QSPI_H +// ============================================================================= +// Register : PADS_QSPI_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SCLK +#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000156) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD0 +#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000156) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD1 +#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c) +#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000156) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD2 +#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010) +#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x0000015a) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD3 +#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014) +#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x0000015a) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SS +#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018) +#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000015a) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SS_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_PADS_QSPI_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/pio.h b/src/rp2350/hardware_regs/include/hardware/regs/pio.h new file mode 100644 index 000000000..4a18b5c6f --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/pio.h @@ -0,0 +1,3417 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PIO +// Version : 1 +// Bus type : ahbl +// Description : Programmable IO block +// ============================================================================= +#ifndef _HARDWARE_REGS_PIO_H +#define _HARDWARE_REGS_PIO_H +// ============================================================================= +// Register : PIO_CTRL +// Description : PIO control register +#define PIO_CTRL_OFFSET _u(0x00000000) +#define PIO_CTRL_BITS _u(0x07ff0fff) +#define PIO_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXTPREV_CLKDIV_RESTART +// Description : Write 1 to restart the clock dividers of state machines in +// neighbouring PIO blocks, as specified by NEXT_PIO_MASK and +// PREV_PIO_MASK in the same write. +// +// This is equivalent to writing 1 to the corresponding +// CLKDIV_RESTART bits in those PIOs' CTRL registers. +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_RESET _u(0x0) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS _u(0x04000000) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_MSB _u(26) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_LSB _u(26) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXTPREV_SM_DISABLE +// Description : Write 1 to disable state machines in neighbouring PIO blocks, +// as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same +// write. +// +// This is equivalent to clearing the corresponding SM_ENABLE bits +// in those PIOs' CTRL registers. +#define PIO_CTRL_NEXTPREV_SM_DISABLE_RESET _u(0x0) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_BITS _u(0x02000000) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_MSB _u(25) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_LSB _u(25) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXTPREV_SM_ENABLE +// Description : Write 1 to enable state machines in neighbouring PIO blocks, as +// specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. +// +// This is equivalent to setting the corresponding SM_ENABLE bits +// in those PIOs' CTRL registers. +// +// If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the +// disable takes precedence. +#define PIO_CTRL_NEXTPREV_SM_ENABLE_RESET _u(0x0) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_BITS _u(0x01000000) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_MSB _u(24) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_LSB _u(24) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXT_PIO_MASK +// Description : A mask of state machines in the neighbouring higher-numbered +// PIO block in the system (or PIO block 0 if this is the highest- +// numbered PIO block) to which to apply the operations specified +// by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and +// NEXTPREV_SM_DISABLE in the same write. +// +// This allows state machines in a neighbouring PIO block to be +// started/stopped/clock-synced exactly simultaneously with a +// write to this PIO block's CTRL register. +// +// Note that in a system with two PIOs, NEXT_PIO_MASK and +// PREV_PIO_MASK actually indicate the same PIO block. In this +// case the effects are applied cumulatively (as though the masks +// were OR'd together). +// +// Neighbouring PIO blocks are disconnected (status signals tied +// to 0 and control signals ignored) if one block is accessible to +// NonSecure code, and one is not. +#define PIO_CTRL_NEXT_PIO_MASK_RESET _u(0x0) +#define PIO_CTRL_NEXT_PIO_MASK_BITS _u(0x00f00000) +#define PIO_CTRL_NEXT_PIO_MASK_MSB _u(23) +#define PIO_CTRL_NEXT_PIO_MASK_LSB _u(20) +#define PIO_CTRL_NEXT_PIO_MASK_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_PREV_PIO_MASK +// Description : A mask of state machines in the neighbouring lower-numbered PIO +// block in the system (or the highest-numbered PIO block if this +// is PIO block 0) to which to apply the operations specified by +// OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. +// +// This allows state machines in a neighbouring PIO block to be +// started/stopped/clock-synced exactly simultaneously with a +// write to this PIO block's CTRL register. +// +// Neighbouring PIO blocks are disconnected (status signals tied +// to 0 and control signals ignored) if one block is accessible to +// NonSecure code, and one is not. +#define PIO_CTRL_PREV_PIO_MASK_RESET _u(0x0) +#define PIO_CTRL_PREV_PIO_MASK_BITS _u(0x000f0000) +#define PIO_CTRL_PREV_PIO_MASK_MSB _u(19) +#define PIO_CTRL_PREV_PIO_MASK_LSB _u(16) +#define PIO_CTRL_PREV_PIO_MASK_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_CLKDIV_RESTART +// Description : Restart a state machine's clock divider from an initial phase +// of 0. Clock dividers are free-running, so once started, their +// output (including fractional jitter) is completely determined +// by the integer/fractional divisor configured in SMx_CLKDIV. +// This means that, if multiple clock dividers with the same +// divisor are restarted simultaneously, by writing multiple 1 +// bits to this field, the execution clocks of those state +// machines will run in precise lockstep. +// +// Note that setting/clearing SM_ENABLE does not stop the clock +// divider from running, so once multiple state machines' clocks +// are synchronised, it is safe to disable/reenable a state +// machine, whilst keeping the clock dividers in sync. +// +// Note also that CLKDIV_RESTART can be written to whilst the +// state machine is running, and this is useful to resynchronise +// clock dividers after the divisors (SMx_CLKDIV) have been +// changed on-the-fly. +#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) +#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) +#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11) +#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8) +#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_RESTART +// Description : Write 1 to instantly clear internal SM state which may be +// otherwise difficult to access and will affect future execution. +// +// Specifically, the following are cleared: input and output shift +// counters; the contents of the input shift register; the delay +// counter; the waiting-on-IRQ state; any stalled instruction +// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left +// asserted due to OUT_STICKY. +// +// The contents of the output shift register and the X/Y scratch +// registers are not affected. +#define PIO_CTRL_SM_RESTART_RESET _u(0x0) +#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) +#define PIO_CTRL_SM_RESTART_MSB _u(7) +#define PIO_CTRL_SM_RESTART_LSB _u(4) +#define PIO_CTRL_SM_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_ENABLE +// Description : Enable/disable each of the four state machines by writing 1/0 +// to each of these four bits. When disabled, a state machine will +// cease executing instructions, except those written directly to +// SMx_INSTR by the system. Multiple bits can be set/cleared at +// once to run/halt multiple state machines simultaneously. +#define PIO_CTRL_SM_ENABLE_RESET _u(0x0) +#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) +#define PIO_CTRL_SM_ENABLE_MSB _u(3) +#define PIO_CTRL_SM_ENABLE_LSB _u(0) +#define PIO_CTRL_SM_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : PIO_FSTAT +// Description : FIFO status register +#define PIO_FSTAT_OFFSET _u(0x00000004) +#define PIO_FSTAT_BITS _u(0x0f0f0f0f) +#define PIO_FSTAT_RESET _u(0x0f000f00) +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXEMPTY +// Description : State machine TX FIFO is empty +#define PIO_FSTAT_TXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) +#define PIO_FSTAT_TXEMPTY_MSB _u(27) +#define PIO_FSTAT_TXEMPTY_LSB _u(24) +#define PIO_FSTAT_TXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXFULL +// Description : State machine TX FIFO is full +#define PIO_FSTAT_TXFULL_RESET _u(0x0) +#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000) +#define PIO_FSTAT_TXFULL_MSB _u(19) +#define PIO_FSTAT_TXFULL_LSB _u(16) +#define PIO_FSTAT_TXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXEMPTY +// Description : State machine RX FIFO is empty +#define PIO_FSTAT_RXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) +#define PIO_FSTAT_RXEMPTY_MSB _u(11) +#define PIO_FSTAT_RXEMPTY_LSB _u(8) +#define PIO_FSTAT_RXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXFULL +// Description : State machine RX FIFO is full +#define PIO_FSTAT_RXFULL_RESET _u(0x0) +#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f) +#define PIO_FSTAT_RXFULL_MSB _u(3) +#define PIO_FSTAT_RXFULL_LSB _u(0) +#define PIO_FSTAT_RXFULL_ACCESS "RO" +// ============================================================================= +// Register : PIO_FDEBUG +// Description : FIFO debug register +#define PIO_FDEBUG_OFFSET _u(0x00000008) +#define PIO_FDEBUG_BITS _u(0x0f0f0f0f) +#define PIO_FDEBUG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXSTALL +// Description : State machine has stalled on empty TX FIFO during a blocking +// PULL, or an OUT with autopull enabled. Write 1 to clear. +#define PIO_FDEBUG_TXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) +#define PIO_FDEBUG_TXSTALL_MSB _u(27) +#define PIO_FDEBUG_TXSTALL_LSB _u(24) +#define PIO_FDEBUG_TXSTALL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXOVER +// Description : TX FIFO overflow (i.e. write-on-full by the system) has +// occurred. Write 1 to clear. Note that write-on-full does not +// alter the state or contents of the FIFO in any way, but the +// data that the system attempted to write is dropped, so if this +// flag is set, your software has quite likely dropped some data +// on the floor. +#define PIO_FDEBUG_TXOVER_RESET _u(0x0) +#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) +#define PIO_FDEBUG_TXOVER_MSB _u(19) +#define PIO_FDEBUG_TXOVER_LSB _u(16) +#define PIO_FDEBUG_TXOVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXUNDER +// Description : RX FIFO underflow (i.e. read-on-empty by the system) has +// occurred. Write 1 to clear. Note that read-on-empty does not +// perturb the state of the FIFO in any way, but the data returned +// by reading from an empty FIFO is undefined, so this flag +// generally only becomes set due to some kind of software error. +#define PIO_FDEBUG_RXUNDER_RESET _u(0x0) +#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) +#define PIO_FDEBUG_RXUNDER_MSB _u(11) +#define PIO_FDEBUG_RXUNDER_LSB _u(8) +#define PIO_FDEBUG_RXUNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXSTALL +// Description : State machine has stalled on full RX FIFO during a blocking +// PUSH, or an IN with autopush enabled. This flag is also set +// when a nonblocking PUSH to a full FIFO took place, in which +// case the state machine has dropped data. Write 1 to clear. +#define PIO_FDEBUG_RXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) +#define PIO_FDEBUG_RXSTALL_MSB _u(3) +#define PIO_FDEBUG_RXSTALL_LSB _u(0) +#define PIO_FDEBUG_RXSTALL_ACCESS "WC" +// ============================================================================= +// Register : PIO_FLEVEL +// Description : FIFO levels +#define PIO_FLEVEL_OFFSET _u(0x0000000c) +#define PIO_FLEVEL_BITS _u(0xffffffff) +#define PIO_FLEVEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX3 +#define PIO_FLEVEL_RX3_RESET _u(0x0) +#define PIO_FLEVEL_RX3_BITS _u(0xf0000000) +#define PIO_FLEVEL_RX3_MSB _u(31) +#define PIO_FLEVEL_RX3_LSB _u(28) +#define PIO_FLEVEL_RX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX3 +#define PIO_FLEVEL_TX3_RESET _u(0x0) +#define PIO_FLEVEL_TX3_BITS _u(0x0f000000) +#define PIO_FLEVEL_TX3_MSB _u(27) +#define PIO_FLEVEL_TX3_LSB _u(24) +#define PIO_FLEVEL_TX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX2 +#define PIO_FLEVEL_RX2_RESET _u(0x0) +#define PIO_FLEVEL_RX2_BITS _u(0x00f00000) +#define PIO_FLEVEL_RX2_MSB _u(23) +#define PIO_FLEVEL_RX2_LSB _u(20) +#define PIO_FLEVEL_RX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX2 +#define PIO_FLEVEL_TX2_RESET _u(0x0) +#define PIO_FLEVEL_TX2_BITS _u(0x000f0000) +#define PIO_FLEVEL_TX2_MSB _u(19) +#define PIO_FLEVEL_TX2_LSB _u(16) +#define PIO_FLEVEL_TX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX1 +#define PIO_FLEVEL_RX1_RESET _u(0x0) +#define PIO_FLEVEL_RX1_BITS _u(0x0000f000) +#define PIO_FLEVEL_RX1_MSB _u(15) +#define PIO_FLEVEL_RX1_LSB _u(12) +#define PIO_FLEVEL_RX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX1 +#define PIO_FLEVEL_TX1_RESET _u(0x0) +#define PIO_FLEVEL_TX1_BITS _u(0x00000f00) +#define PIO_FLEVEL_TX1_MSB _u(11) +#define PIO_FLEVEL_TX1_LSB _u(8) +#define PIO_FLEVEL_TX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX0 +#define PIO_FLEVEL_RX0_RESET _u(0x0) +#define PIO_FLEVEL_RX0_BITS _u(0x000000f0) +#define PIO_FLEVEL_RX0_MSB _u(7) +#define PIO_FLEVEL_RX0_LSB _u(4) +#define PIO_FLEVEL_RX0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX0 +#define PIO_FLEVEL_TX0_RESET _u(0x0) +#define PIO_FLEVEL_TX0_BITS _u(0x0000000f) +#define PIO_FLEVEL_TX0_MSB _u(3) +#define PIO_FLEVEL_TX0_LSB _u(0) +#define PIO_FLEVEL_TX0_ACCESS "RO" +// ============================================================================= +// Register : PIO_TXF0 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF0_OFFSET _u(0x00000010) +#define PIO_TXF0_BITS _u(0xffffffff) +#define PIO_TXF0_RESET _u(0x00000000) +#define PIO_TXF0_MSB _u(31) +#define PIO_TXF0_LSB _u(0) +#define PIO_TXF0_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF1 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF1_OFFSET _u(0x00000014) +#define PIO_TXF1_BITS _u(0xffffffff) +#define PIO_TXF1_RESET _u(0x00000000) +#define PIO_TXF1_MSB _u(31) +#define PIO_TXF1_LSB _u(0) +#define PIO_TXF1_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF2 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF2_OFFSET _u(0x00000018) +#define PIO_TXF2_BITS _u(0xffffffff) +#define PIO_TXF2_RESET _u(0x00000000) +#define PIO_TXF2_MSB _u(31) +#define PIO_TXF2_LSB _u(0) +#define PIO_TXF2_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF3 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF3_OFFSET _u(0x0000001c) +#define PIO_TXF3_BITS _u(0xffffffff) +#define PIO_TXF3_RESET _u(0x00000000) +#define PIO_TXF3_MSB _u(31) +#define PIO_TXF3_LSB _u(0) +#define PIO_TXF3_ACCESS "WF" +// ============================================================================= +// Register : PIO_RXF0 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF0_OFFSET _u(0x00000020) +#define PIO_RXF0_BITS _u(0xffffffff) +#define PIO_RXF0_RESET "-" +#define PIO_RXF0_MSB _u(31) +#define PIO_RXF0_LSB _u(0) +#define PIO_RXF0_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF1 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF1_OFFSET _u(0x00000024) +#define PIO_RXF1_BITS _u(0xffffffff) +#define PIO_RXF1_RESET "-" +#define PIO_RXF1_MSB _u(31) +#define PIO_RXF1_LSB _u(0) +#define PIO_RXF1_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF2 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF2_OFFSET _u(0x00000028) +#define PIO_RXF2_BITS _u(0xffffffff) +#define PIO_RXF2_RESET "-" +#define PIO_RXF2_MSB _u(31) +#define PIO_RXF2_LSB _u(0) +#define PIO_RXF2_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF3 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF3_OFFSET _u(0x0000002c) +#define PIO_RXF3_BITS _u(0xffffffff) +#define PIO_RXF3_RESET "-" +#define PIO_RXF3_MSB _u(31) +#define PIO_RXF3_LSB _u(0) +#define PIO_RXF3_ACCESS "RF" +// ============================================================================= +// Register : PIO_IRQ +// Description : State machine IRQ flags register. Write 1 to clear. There are +// eight state machine IRQ flags, which can be set, cleared, and +// waited on by the state machines. There's no fixed association +// between flags and state machines -- any state machine can use +// any flag. +// +// Any of the eight flags can be used for timing synchronisation +// between state machines, using IRQ and WAIT instructions. Any +// combination of the eight flags can also routed out to either of +// the two system-level interrupt requests, alongside FIFO status +// interrupts -- see e.g. IRQ0_INTE. +#define PIO_IRQ_OFFSET _u(0x00000030) +#define PIO_IRQ_BITS _u(0x000000ff) +#define PIO_IRQ_RESET _u(0x00000000) +#define PIO_IRQ_MSB _u(7) +#define PIO_IRQ_LSB _u(0) +#define PIO_IRQ_ACCESS "WC" +// ============================================================================= +// Register : PIO_IRQ_FORCE +// Description : Writing a 1 to each of these bits will forcibly assert the +// corresponding IRQ. Note this is different to the INTF register: +// writing here affects PIO internal state. INTF just asserts the +// processor-facing IRQ signal for testing ISRs, and is not +// visible to the state machines. +#define PIO_IRQ_FORCE_OFFSET _u(0x00000034) +#define PIO_IRQ_FORCE_BITS _u(0x000000ff) +#define PIO_IRQ_FORCE_RESET _u(0x00000000) +#define PIO_IRQ_FORCE_MSB _u(7) +#define PIO_IRQ_FORCE_LSB _u(0) +#define PIO_IRQ_FORCE_ACCESS "WF" +// ============================================================================= +// Register : PIO_INPUT_SYNC_BYPASS +// Description : There is a 2-flipflop synchronizer on each GPIO input, which +// protects PIO logic from metastabilities. This increases input +// delay, and for fast synchronous IO (e.g. SPI) these +// synchronizers may need to be bypassed. Each bit in this +// register corresponds to one GPIO. +// 0 -> input is synchronized (default) +// 1 -> synchronizer is bypassed +// If in doubt, leave this register as all zeroes. +#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038) +#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) +#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) +#define PIO_INPUT_SYNC_BYPASS_MSB _u(31) +#define PIO_INPUT_SYNC_BYPASS_LSB _u(0) +#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" +// ============================================================================= +// Register : PIO_DBG_PADOUT +// Description : Read to sample the pad output values PIO is currently driving +// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most +// significant bits are hardwired to 0. +#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c) +#define PIO_DBG_PADOUT_BITS _u(0xffffffff) +#define PIO_DBG_PADOUT_RESET _u(0x00000000) +#define PIO_DBG_PADOUT_MSB _u(31) +#define PIO_DBG_PADOUT_LSB _u(0) +#define PIO_DBG_PADOUT_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_PADOE +// Description : Read to sample the pad output enables (direction) PIO is +// currently driving to the GPIOs. On RP2040 there are 30 GPIOs, +// so the two most significant bits are hardwired to 0. +#define PIO_DBG_PADOE_OFFSET _u(0x00000040) +#define PIO_DBG_PADOE_BITS _u(0xffffffff) +#define PIO_DBG_PADOE_RESET _u(0x00000000) +#define PIO_DBG_PADOE_MSB _u(31) +#define PIO_DBG_PADOE_LSB _u(0) +#define PIO_DBG_PADOE_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_CFGINFO +// Description : The PIO hardware has some free parameters that may vary between +// chip products. +// These should be provided in the chip datasheet, but are also +// exposed here. +#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044) +#define PIO_DBG_CFGINFO_BITS _u(0xf03f0f3f) +#define PIO_DBG_CFGINFO_RESET _u(0x10000000) +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_VERSION +// Description : Version of the core PIO hardware. +// 0x0 -> Version 0 (RP2040) +// 0x1 -> Version 1 (RP2350) +#define PIO_DBG_CFGINFO_VERSION_RESET _u(0x1) +#define PIO_DBG_CFGINFO_VERSION_BITS _u(0xf0000000) +#define PIO_DBG_CFGINFO_VERSION_MSB _u(31) +#define PIO_DBG_CFGINFO_VERSION_LSB _u(28) +#define PIO_DBG_CFGINFO_VERSION_ACCESS "RO" +#define PIO_DBG_CFGINFO_VERSION_VALUE_V0 _u(0x0) +#define PIO_DBG_CFGINFO_VERSION_VALUE_V1 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_IMEM_SIZE +// Description : The size of the instruction memory, measured in units of one +// instruction +#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" +#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) +#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) +#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) +#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_SM_COUNT +// Description : The number of state machines this PIO instance is equipped +// with. +#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" +#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) +#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) +#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) +#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_FIFO_DEPTH +// Description : The depth of the state machine TX/RX FIFOs, measured in words. +// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double +// this depth. +#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" +#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" +// ============================================================================= +// Register : PIO_INSTR_MEM0 +// Description : Write-only access to instruction memory location 0 +#define PIO_INSTR_MEM0_OFFSET _u(0x00000048) +#define PIO_INSTR_MEM0_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM0_RESET _u(0x00000000) +#define PIO_INSTR_MEM0_MSB _u(15) +#define PIO_INSTR_MEM0_LSB _u(0) +#define PIO_INSTR_MEM0_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM1 +// Description : Write-only access to instruction memory location 1 +#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c) +#define PIO_INSTR_MEM1_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM1_RESET _u(0x00000000) +#define PIO_INSTR_MEM1_MSB _u(15) +#define PIO_INSTR_MEM1_LSB _u(0) +#define PIO_INSTR_MEM1_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM2 +// Description : Write-only access to instruction memory location 2 +#define PIO_INSTR_MEM2_OFFSET _u(0x00000050) +#define PIO_INSTR_MEM2_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM2_RESET _u(0x00000000) +#define PIO_INSTR_MEM2_MSB _u(15) +#define PIO_INSTR_MEM2_LSB _u(0) +#define PIO_INSTR_MEM2_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM3 +// Description : Write-only access to instruction memory location 3 +#define PIO_INSTR_MEM3_OFFSET _u(0x00000054) +#define PIO_INSTR_MEM3_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM3_RESET _u(0x00000000) +#define PIO_INSTR_MEM3_MSB _u(15) +#define PIO_INSTR_MEM3_LSB _u(0) +#define PIO_INSTR_MEM3_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM4 +// Description : Write-only access to instruction memory location 4 +#define PIO_INSTR_MEM4_OFFSET _u(0x00000058) +#define PIO_INSTR_MEM4_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM4_RESET _u(0x00000000) +#define PIO_INSTR_MEM4_MSB _u(15) +#define PIO_INSTR_MEM4_LSB _u(0) +#define PIO_INSTR_MEM4_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM5 +// Description : Write-only access to instruction memory location 5 +#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c) +#define PIO_INSTR_MEM5_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM5_RESET _u(0x00000000) +#define PIO_INSTR_MEM5_MSB _u(15) +#define PIO_INSTR_MEM5_LSB _u(0) +#define PIO_INSTR_MEM5_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM6 +// Description : Write-only access to instruction memory location 6 +#define PIO_INSTR_MEM6_OFFSET _u(0x00000060) +#define PIO_INSTR_MEM6_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM6_RESET _u(0x00000000) +#define PIO_INSTR_MEM6_MSB _u(15) +#define PIO_INSTR_MEM6_LSB _u(0) +#define PIO_INSTR_MEM6_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM7 +// Description : Write-only access to instruction memory location 7 +#define PIO_INSTR_MEM7_OFFSET _u(0x00000064) +#define PIO_INSTR_MEM7_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM7_RESET _u(0x00000000) +#define PIO_INSTR_MEM7_MSB _u(15) +#define PIO_INSTR_MEM7_LSB _u(0) +#define PIO_INSTR_MEM7_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM8 +// Description : Write-only access to instruction memory location 8 +#define PIO_INSTR_MEM8_OFFSET _u(0x00000068) +#define PIO_INSTR_MEM8_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM8_RESET _u(0x00000000) +#define PIO_INSTR_MEM8_MSB _u(15) +#define PIO_INSTR_MEM8_LSB _u(0) +#define PIO_INSTR_MEM8_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM9 +// Description : Write-only access to instruction memory location 9 +#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c) +#define PIO_INSTR_MEM9_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM9_RESET _u(0x00000000) +#define PIO_INSTR_MEM9_MSB _u(15) +#define PIO_INSTR_MEM9_LSB _u(0) +#define PIO_INSTR_MEM9_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM10 +// Description : Write-only access to instruction memory location 10 +#define PIO_INSTR_MEM10_OFFSET _u(0x00000070) +#define PIO_INSTR_MEM10_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM10_RESET _u(0x00000000) +#define PIO_INSTR_MEM10_MSB _u(15) +#define PIO_INSTR_MEM10_LSB _u(0) +#define PIO_INSTR_MEM10_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM11 +// Description : Write-only access to instruction memory location 11 +#define PIO_INSTR_MEM11_OFFSET _u(0x00000074) +#define PIO_INSTR_MEM11_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM11_RESET _u(0x00000000) +#define PIO_INSTR_MEM11_MSB _u(15) +#define PIO_INSTR_MEM11_LSB _u(0) +#define PIO_INSTR_MEM11_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM12 +// Description : Write-only access to instruction memory location 12 +#define PIO_INSTR_MEM12_OFFSET _u(0x00000078) +#define PIO_INSTR_MEM12_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM12_RESET _u(0x00000000) +#define PIO_INSTR_MEM12_MSB _u(15) +#define PIO_INSTR_MEM12_LSB _u(0) +#define PIO_INSTR_MEM12_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM13 +// Description : Write-only access to instruction memory location 13 +#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c) +#define PIO_INSTR_MEM13_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM13_RESET _u(0x00000000) +#define PIO_INSTR_MEM13_MSB _u(15) +#define PIO_INSTR_MEM13_LSB _u(0) +#define PIO_INSTR_MEM13_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM14 +// Description : Write-only access to instruction memory location 14 +#define PIO_INSTR_MEM14_OFFSET _u(0x00000080) +#define PIO_INSTR_MEM14_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM14_RESET _u(0x00000000) +#define PIO_INSTR_MEM14_MSB _u(15) +#define PIO_INSTR_MEM14_LSB _u(0) +#define PIO_INSTR_MEM14_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM15 +// Description : Write-only access to instruction memory location 15 +#define PIO_INSTR_MEM15_OFFSET _u(0x00000084) +#define PIO_INSTR_MEM15_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM15_RESET _u(0x00000000) +#define PIO_INSTR_MEM15_MSB _u(15) +#define PIO_INSTR_MEM15_LSB _u(0) +#define PIO_INSTR_MEM15_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM16 +// Description : Write-only access to instruction memory location 16 +#define PIO_INSTR_MEM16_OFFSET _u(0x00000088) +#define PIO_INSTR_MEM16_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM16_RESET _u(0x00000000) +#define PIO_INSTR_MEM16_MSB _u(15) +#define PIO_INSTR_MEM16_LSB _u(0) +#define PIO_INSTR_MEM16_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM17 +// Description : Write-only access to instruction memory location 17 +#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c) +#define PIO_INSTR_MEM17_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM17_RESET _u(0x00000000) +#define PIO_INSTR_MEM17_MSB _u(15) +#define PIO_INSTR_MEM17_LSB _u(0) +#define PIO_INSTR_MEM17_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM18 +// Description : Write-only access to instruction memory location 18 +#define PIO_INSTR_MEM18_OFFSET _u(0x00000090) +#define PIO_INSTR_MEM18_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM18_RESET _u(0x00000000) +#define PIO_INSTR_MEM18_MSB _u(15) +#define PIO_INSTR_MEM18_LSB _u(0) +#define PIO_INSTR_MEM18_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM19 +// Description : Write-only access to instruction memory location 19 +#define PIO_INSTR_MEM19_OFFSET _u(0x00000094) +#define PIO_INSTR_MEM19_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM19_RESET _u(0x00000000) +#define PIO_INSTR_MEM19_MSB _u(15) +#define PIO_INSTR_MEM19_LSB _u(0) +#define PIO_INSTR_MEM19_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM20 +// Description : Write-only access to instruction memory location 20 +#define PIO_INSTR_MEM20_OFFSET _u(0x00000098) +#define PIO_INSTR_MEM20_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM20_RESET _u(0x00000000) +#define PIO_INSTR_MEM20_MSB _u(15) +#define PIO_INSTR_MEM20_LSB _u(0) +#define PIO_INSTR_MEM20_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM21 +// Description : Write-only access to instruction memory location 21 +#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c) +#define PIO_INSTR_MEM21_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM21_RESET _u(0x00000000) +#define PIO_INSTR_MEM21_MSB _u(15) +#define PIO_INSTR_MEM21_LSB _u(0) +#define PIO_INSTR_MEM21_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM22 +// Description : Write-only access to instruction memory location 22 +#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0) +#define PIO_INSTR_MEM22_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM22_RESET _u(0x00000000) +#define PIO_INSTR_MEM22_MSB _u(15) +#define PIO_INSTR_MEM22_LSB _u(0) +#define PIO_INSTR_MEM22_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM23 +// Description : Write-only access to instruction memory location 23 +#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4) +#define PIO_INSTR_MEM23_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM23_RESET _u(0x00000000) +#define PIO_INSTR_MEM23_MSB _u(15) +#define PIO_INSTR_MEM23_LSB _u(0) +#define PIO_INSTR_MEM23_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM24 +// Description : Write-only access to instruction memory location 24 +#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8) +#define PIO_INSTR_MEM24_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM24_RESET _u(0x00000000) +#define PIO_INSTR_MEM24_MSB _u(15) +#define PIO_INSTR_MEM24_LSB _u(0) +#define PIO_INSTR_MEM24_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM25 +// Description : Write-only access to instruction memory location 25 +#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac) +#define PIO_INSTR_MEM25_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM25_RESET _u(0x00000000) +#define PIO_INSTR_MEM25_MSB _u(15) +#define PIO_INSTR_MEM25_LSB _u(0) +#define PIO_INSTR_MEM25_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM26 +// Description : Write-only access to instruction memory location 26 +#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0) +#define PIO_INSTR_MEM26_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM26_RESET _u(0x00000000) +#define PIO_INSTR_MEM26_MSB _u(15) +#define PIO_INSTR_MEM26_LSB _u(0) +#define PIO_INSTR_MEM26_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM27 +// Description : Write-only access to instruction memory location 27 +#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4) +#define PIO_INSTR_MEM27_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM27_RESET _u(0x00000000) +#define PIO_INSTR_MEM27_MSB _u(15) +#define PIO_INSTR_MEM27_LSB _u(0) +#define PIO_INSTR_MEM27_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM28 +// Description : Write-only access to instruction memory location 28 +#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8) +#define PIO_INSTR_MEM28_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM28_RESET _u(0x00000000) +#define PIO_INSTR_MEM28_MSB _u(15) +#define PIO_INSTR_MEM28_LSB _u(0) +#define PIO_INSTR_MEM28_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM29 +// Description : Write-only access to instruction memory location 29 +#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc) +#define PIO_INSTR_MEM29_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM29_RESET _u(0x00000000) +#define PIO_INSTR_MEM29_MSB _u(15) +#define PIO_INSTR_MEM29_LSB _u(0) +#define PIO_INSTR_MEM29_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM30 +// Description : Write-only access to instruction memory location 30 +#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0) +#define PIO_INSTR_MEM30_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM30_RESET _u(0x00000000) +#define PIO_INSTR_MEM30_MSB _u(15) +#define PIO_INSTR_MEM30_LSB _u(0) +#define PIO_INSTR_MEM30_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM31 +// Description : Write-only access to instruction memory location 31 +#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4) +#define PIO_INSTR_MEM31_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM31_RESET _u(0x00000000) +#define PIO_INSTR_MEM31_MSB _u(15) +#define PIO_INSTR_MEM31_LSB _u(0) +#define PIO_INSTR_MEM31_ACCESS "WO" +// ============================================================================= +// Register : PIO_SM0_CLKDIV +// Description : Clock divisor register for state machine 0 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8) +#define PIO_SM0_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM0_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM0_CLKDIV_INT_MSB _u(31) +#define PIO_SM0_CLKDIV_INT_LSB _u(16) +#define PIO_SM0_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM0_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM0_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_EXECCTRL +// Description : Execution/behavioural settings for state machine 0 +#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc) +#define PIO_SM0_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM0_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 0 +#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0) +#define PIO_SM0_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM0_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_ADDR +// Description : Current instruction address of state machine 0 +#define PIO_SM0_ADDR_OFFSET _u(0x000000d4) +#define PIO_SM0_ADDR_BITS _u(0x0000001f) +#define PIO_SM0_ADDR_RESET _u(0x00000000) +#define PIO_SM0_ADDR_MSB _u(4) +#define PIO_SM0_ADDR_LSB _u(0) +#define PIO_SM0_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM0_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 0's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM0_INSTR_OFFSET _u(0x000000d8) +#define PIO_SM0_INSTR_BITS _u(0x0000ffff) +#define PIO_SM0_INSTR_RESET "-" +#define PIO_SM0_INSTR_MSB _u(15) +#define PIO_SM0_INSTR_LSB _u(0) +#define PIO_SM0_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_PINCTRL +// Description : State machine pin control +#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc) +#define PIO_SM0_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM0_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_CLKDIV +// Description : Clock divisor register for state machine 1 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0) +#define PIO_SM1_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM1_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM1_CLKDIV_INT_MSB _u(31) +#define PIO_SM1_CLKDIV_INT_LSB _u(16) +#define PIO_SM1_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM1_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM1_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_EXECCTRL +// Description : Execution/behavioural settings for state machine 1 +#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4) +#define PIO_SM1_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM1_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 1 +#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8) +#define PIO_SM1_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM1_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_ADDR +// Description : Current instruction address of state machine 1 +#define PIO_SM1_ADDR_OFFSET _u(0x000000ec) +#define PIO_SM1_ADDR_BITS _u(0x0000001f) +#define PIO_SM1_ADDR_RESET _u(0x00000000) +#define PIO_SM1_ADDR_MSB _u(4) +#define PIO_SM1_ADDR_LSB _u(0) +#define PIO_SM1_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM1_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 1's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM1_INSTR_OFFSET _u(0x000000f0) +#define PIO_SM1_INSTR_BITS _u(0x0000ffff) +#define PIO_SM1_INSTR_RESET "-" +#define PIO_SM1_INSTR_MSB _u(15) +#define PIO_SM1_INSTR_LSB _u(0) +#define PIO_SM1_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_PINCTRL +// Description : State machine pin control +#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4) +#define PIO_SM1_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM1_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_CLKDIV +// Description : Clock divisor register for state machine 2 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8) +#define PIO_SM2_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM2_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM2_CLKDIV_INT_MSB _u(31) +#define PIO_SM2_CLKDIV_INT_LSB _u(16) +#define PIO_SM2_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM2_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM2_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_EXECCTRL +// Description : Execution/behavioural settings for state machine 2 +#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc) +#define PIO_SM2_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM2_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 2 +#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100) +#define PIO_SM2_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM2_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_ADDR +// Description : Current instruction address of state machine 2 +#define PIO_SM2_ADDR_OFFSET _u(0x00000104) +#define PIO_SM2_ADDR_BITS _u(0x0000001f) +#define PIO_SM2_ADDR_RESET _u(0x00000000) +#define PIO_SM2_ADDR_MSB _u(4) +#define PIO_SM2_ADDR_LSB _u(0) +#define PIO_SM2_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM2_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 2's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM2_INSTR_OFFSET _u(0x00000108) +#define PIO_SM2_INSTR_BITS _u(0x0000ffff) +#define PIO_SM2_INSTR_RESET "-" +#define PIO_SM2_INSTR_MSB _u(15) +#define PIO_SM2_INSTR_LSB _u(0) +#define PIO_SM2_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_PINCTRL +// Description : State machine pin control +#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c) +#define PIO_SM2_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM2_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_CLKDIV +// Description : Clock divisor register for state machine 3 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110) +#define PIO_SM3_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM3_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM3_CLKDIV_INT_MSB _u(31) +#define PIO_SM3_CLKDIV_INT_LSB _u(16) +#define PIO_SM3_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM3_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM3_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_EXECCTRL +// Description : Execution/behavioural settings for state machine 3 +#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114) +#define PIO_SM3_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM3_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 3 +#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118) +#define PIO_SM3_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM3_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_ADDR +// Description : Current instruction address of state machine 3 +#define PIO_SM3_ADDR_OFFSET _u(0x0000011c) +#define PIO_SM3_ADDR_BITS _u(0x0000001f) +#define PIO_SM3_ADDR_RESET _u(0x00000000) +#define PIO_SM3_ADDR_MSB _u(4) +#define PIO_SM3_ADDR_LSB _u(0) +#define PIO_SM3_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM3_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 3's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM3_INSTR_OFFSET _u(0x00000120) +#define PIO_SM3_INSTR_BITS _u(0x0000ffff) +#define PIO_SM3_INSTR_RESET "-" +#define PIO_SM3_INSTR_MSB _u(15) +#define PIO_SM3_INSTR_LSB _u(0) +#define PIO_SM3_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_PINCTRL +// Description : State machine pin control +#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124) +#define PIO_SM3_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM3_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET0 +// Description : Direct read/write access to entry 0 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET0_OFFSET _u(0x00000128) +#define PIO_RXF0_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET0_MSB _u(31) +#define PIO_RXF0_PUTGET0_LSB _u(0) +#define PIO_RXF0_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET1 +// Description : Direct read/write access to entry 1 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET1_OFFSET _u(0x0000012c) +#define PIO_RXF0_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET1_MSB _u(31) +#define PIO_RXF0_PUTGET1_LSB _u(0) +#define PIO_RXF0_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET2 +// Description : Direct read/write access to entry 2 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET2_OFFSET _u(0x00000130) +#define PIO_RXF0_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET2_MSB _u(31) +#define PIO_RXF0_PUTGET2_LSB _u(0) +#define PIO_RXF0_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET3 +// Description : Direct read/write access to entry 3 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET3_OFFSET _u(0x00000134) +#define PIO_RXF0_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET3_MSB _u(31) +#define PIO_RXF0_PUTGET3_LSB _u(0) +#define PIO_RXF0_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET0 +// Description : Direct read/write access to entry 0 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET0_OFFSET _u(0x00000138) +#define PIO_RXF1_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET0_MSB _u(31) +#define PIO_RXF1_PUTGET0_LSB _u(0) +#define PIO_RXF1_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET1 +// Description : Direct read/write access to entry 1 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET1_OFFSET _u(0x0000013c) +#define PIO_RXF1_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET1_MSB _u(31) +#define PIO_RXF1_PUTGET1_LSB _u(0) +#define PIO_RXF1_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET2 +// Description : Direct read/write access to entry 2 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET2_OFFSET _u(0x00000140) +#define PIO_RXF1_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET2_MSB _u(31) +#define PIO_RXF1_PUTGET2_LSB _u(0) +#define PIO_RXF1_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET3 +// Description : Direct read/write access to entry 3 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET3_OFFSET _u(0x00000144) +#define PIO_RXF1_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET3_MSB _u(31) +#define PIO_RXF1_PUTGET3_LSB _u(0) +#define PIO_RXF1_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET0 +// Description : Direct read/write access to entry 0 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET0_OFFSET _u(0x00000148) +#define PIO_RXF2_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET0_MSB _u(31) +#define PIO_RXF2_PUTGET0_LSB _u(0) +#define PIO_RXF2_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET1 +// Description : Direct read/write access to entry 1 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET1_OFFSET _u(0x0000014c) +#define PIO_RXF2_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET1_MSB _u(31) +#define PIO_RXF2_PUTGET1_LSB _u(0) +#define PIO_RXF2_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET2 +// Description : Direct read/write access to entry 2 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET2_OFFSET _u(0x00000150) +#define PIO_RXF2_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET2_MSB _u(31) +#define PIO_RXF2_PUTGET2_LSB _u(0) +#define PIO_RXF2_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET3 +// Description : Direct read/write access to entry 3 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET3_OFFSET _u(0x00000154) +#define PIO_RXF2_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET3_MSB _u(31) +#define PIO_RXF2_PUTGET3_LSB _u(0) +#define PIO_RXF2_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET0 +// Description : Direct read/write access to entry 0 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET0_OFFSET _u(0x00000158) +#define PIO_RXF3_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET0_MSB _u(31) +#define PIO_RXF3_PUTGET0_LSB _u(0) +#define PIO_RXF3_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET1 +// Description : Direct read/write access to entry 1 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET1_OFFSET _u(0x0000015c) +#define PIO_RXF3_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET1_MSB _u(31) +#define PIO_RXF3_PUTGET1_LSB _u(0) +#define PIO_RXF3_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET2 +// Description : Direct read/write access to entry 2 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET2_OFFSET _u(0x00000160) +#define PIO_RXF3_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET2_MSB _u(31) +#define PIO_RXF3_PUTGET2_LSB _u(0) +#define PIO_RXF3_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET3 +// Description : Direct read/write access to entry 3 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET3_OFFSET _u(0x00000164) +#define PIO_RXF3_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET3_MSB _u(31) +#define PIO_RXF3_PUTGET3_LSB _u(0) +#define PIO_RXF3_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_GPIOBASE +// Description : Relocate GPIO 0 (from PIO's point of view) in the system GPIO +// numbering, to access more than 32 GPIOs from PIO. +// +// Only the values 0 and 16 are supported (only bit 4 is +// writable). +#define PIO_GPIOBASE_OFFSET _u(0x00000168) +#define PIO_GPIOBASE_BITS _u(0x00000010) +#define PIO_GPIOBASE_RESET _u(0x00000000) +#define PIO_GPIOBASE_MSB _u(4) +#define PIO_GPIOBASE_LSB _u(4) +#define PIO_GPIOBASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_INTR +// Description : Raw Interrupts +#define PIO_INTR_OFFSET _u(0x0000016c) +#define PIO_INTR_BITS _u(0x0000ffff) +#define PIO_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM7 +#define PIO_INTR_SM7_RESET _u(0x0) +#define PIO_INTR_SM7_BITS _u(0x00008000) +#define PIO_INTR_SM7_MSB _u(15) +#define PIO_INTR_SM7_LSB _u(15) +#define PIO_INTR_SM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM6 +#define PIO_INTR_SM6_RESET _u(0x0) +#define PIO_INTR_SM6_BITS _u(0x00004000) +#define PIO_INTR_SM6_MSB _u(14) +#define PIO_INTR_SM6_LSB _u(14) +#define PIO_INTR_SM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM5 +#define PIO_INTR_SM5_RESET _u(0x0) +#define PIO_INTR_SM5_BITS _u(0x00002000) +#define PIO_INTR_SM5_MSB _u(13) +#define PIO_INTR_SM5_LSB _u(13) +#define PIO_INTR_SM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM4 +#define PIO_INTR_SM4_RESET _u(0x0) +#define PIO_INTR_SM4_BITS _u(0x00001000) +#define PIO_INTR_SM4_MSB _u(12) +#define PIO_INTR_SM4_LSB _u(12) +#define PIO_INTR_SM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3 +#define PIO_INTR_SM3_RESET _u(0x0) +#define PIO_INTR_SM3_BITS _u(0x00000800) +#define PIO_INTR_SM3_MSB _u(11) +#define PIO_INTR_SM3_LSB _u(11) +#define PIO_INTR_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2 +#define PIO_INTR_SM2_RESET _u(0x0) +#define PIO_INTR_SM2_BITS _u(0x00000400) +#define PIO_INTR_SM2_MSB _u(10) +#define PIO_INTR_SM2_LSB _u(10) +#define PIO_INTR_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1 +#define PIO_INTR_SM1_RESET _u(0x0) +#define PIO_INTR_SM1_BITS _u(0x00000200) +#define PIO_INTR_SM1_MSB _u(9) +#define PIO_INTR_SM1_LSB _u(9) +#define PIO_INTR_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0 +#define PIO_INTR_SM0_RESET _u(0x0) +#define PIO_INTR_SM0_BITS _u(0x00000100) +#define PIO_INTR_SM0_MSB _u(8) +#define PIO_INTR_SM0_LSB _u(8) +#define PIO_INTR_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_TXNFULL +#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_INTR_SM3_TXNFULL_MSB _u(7) +#define PIO_INTR_SM3_TXNFULL_LSB _u(7) +#define PIO_INTR_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_TXNFULL +#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_INTR_SM2_TXNFULL_MSB _u(6) +#define PIO_INTR_SM2_TXNFULL_LSB _u(6) +#define PIO_INTR_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_TXNFULL +#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_INTR_SM1_TXNFULL_MSB _u(5) +#define PIO_INTR_SM1_TXNFULL_LSB _u(5) +#define PIO_INTR_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_TXNFULL +#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_INTR_SM0_TXNFULL_MSB _u(4) +#define PIO_INTR_SM0_TXNFULL_LSB _u(4) +#define PIO_INTR_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_RXNEMPTY +#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) +#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3) +#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_RXNEMPTY +#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) +#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2) +#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_RXNEMPTY +#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) +#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1) +#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_RXNEMPTY +#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) +#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0) +#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ0_INTE +// Description : Interrupt Enable for irq0 +#define PIO_IRQ0_INTE_OFFSET _u(0x00000170) +#define PIO_IRQ0_INTE_BITS _u(0x0000ffff) +#define PIO_IRQ0_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM7 +#define PIO_IRQ0_INTE_SM7_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM7_BITS _u(0x00008000) +#define PIO_IRQ0_INTE_SM7_MSB _u(15) +#define PIO_IRQ0_INTE_SM7_LSB _u(15) +#define PIO_IRQ0_INTE_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM6 +#define PIO_IRQ0_INTE_SM6_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM6_BITS _u(0x00004000) +#define PIO_IRQ0_INTE_SM6_MSB _u(14) +#define PIO_IRQ0_INTE_SM6_LSB _u(14) +#define PIO_IRQ0_INTE_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM5 +#define PIO_IRQ0_INTE_SM5_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM5_BITS _u(0x00002000) +#define PIO_IRQ0_INTE_SM5_MSB _u(13) +#define PIO_IRQ0_INTE_SM5_LSB _u(13) +#define PIO_IRQ0_INTE_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM4 +#define PIO_IRQ0_INTE_SM4_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM4_BITS _u(0x00001000) +#define PIO_IRQ0_INTE_SM4_MSB _u(12) +#define PIO_IRQ0_INTE_SM4_LSB _u(12) +#define PIO_IRQ0_INTE_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3 +#define PIO_IRQ0_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTE_SM3_MSB _u(11) +#define PIO_IRQ0_INTE_SM3_LSB _u(11) +#define PIO_IRQ0_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2 +#define PIO_IRQ0_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTE_SM2_MSB _u(10) +#define PIO_IRQ0_INTE_SM2_LSB _u(10) +#define PIO_IRQ0_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1 +#define PIO_IRQ0_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTE_SM1_MSB _u(9) +#define PIO_IRQ0_INTE_SM1_LSB _u(9) +#define PIO_IRQ0_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0 +#define PIO_IRQ0_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTE_SM0_MSB _u(8) +#define PIO_IRQ0_INTE_SM0_LSB _u(8) +#define PIO_IRQ0_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_TXNFULL +#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_TXNFULL +#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_TXNFULL +#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_TXNFULL +#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTF +// Description : Interrupt Force for irq0 +#define PIO_IRQ0_INTF_OFFSET _u(0x00000174) +#define PIO_IRQ0_INTF_BITS _u(0x0000ffff) +#define PIO_IRQ0_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM7 +#define PIO_IRQ0_INTF_SM7_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM7_BITS _u(0x00008000) +#define PIO_IRQ0_INTF_SM7_MSB _u(15) +#define PIO_IRQ0_INTF_SM7_LSB _u(15) +#define PIO_IRQ0_INTF_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM6 +#define PIO_IRQ0_INTF_SM6_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM6_BITS _u(0x00004000) +#define PIO_IRQ0_INTF_SM6_MSB _u(14) +#define PIO_IRQ0_INTF_SM6_LSB _u(14) +#define PIO_IRQ0_INTF_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM5 +#define PIO_IRQ0_INTF_SM5_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM5_BITS _u(0x00002000) +#define PIO_IRQ0_INTF_SM5_MSB _u(13) +#define PIO_IRQ0_INTF_SM5_LSB _u(13) +#define PIO_IRQ0_INTF_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM4 +#define PIO_IRQ0_INTF_SM4_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM4_BITS _u(0x00001000) +#define PIO_IRQ0_INTF_SM4_MSB _u(12) +#define PIO_IRQ0_INTF_SM4_LSB _u(12) +#define PIO_IRQ0_INTF_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3 +#define PIO_IRQ0_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTF_SM3_MSB _u(11) +#define PIO_IRQ0_INTF_SM3_LSB _u(11) +#define PIO_IRQ0_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2 +#define PIO_IRQ0_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTF_SM2_MSB _u(10) +#define PIO_IRQ0_INTF_SM2_LSB _u(10) +#define PIO_IRQ0_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1 +#define PIO_IRQ0_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTF_SM1_MSB _u(9) +#define PIO_IRQ0_INTF_SM1_LSB _u(9) +#define PIO_IRQ0_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0 +#define PIO_IRQ0_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTF_SM0_MSB _u(8) +#define PIO_IRQ0_INTF_SM0_LSB _u(8) +#define PIO_IRQ0_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_TXNFULL +#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_TXNFULL +#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_TXNFULL +#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_TXNFULL +#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTS +// Description : Interrupt status after masking & forcing for irq0 +#define PIO_IRQ0_INTS_OFFSET _u(0x00000178) +#define PIO_IRQ0_INTS_BITS _u(0x0000ffff) +#define PIO_IRQ0_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM7 +#define PIO_IRQ0_INTS_SM7_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM7_BITS _u(0x00008000) +#define PIO_IRQ0_INTS_SM7_MSB _u(15) +#define PIO_IRQ0_INTS_SM7_LSB _u(15) +#define PIO_IRQ0_INTS_SM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM6 +#define PIO_IRQ0_INTS_SM6_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM6_BITS _u(0x00004000) +#define PIO_IRQ0_INTS_SM6_MSB _u(14) +#define PIO_IRQ0_INTS_SM6_LSB _u(14) +#define PIO_IRQ0_INTS_SM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM5 +#define PIO_IRQ0_INTS_SM5_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM5_BITS _u(0x00002000) +#define PIO_IRQ0_INTS_SM5_MSB _u(13) +#define PIO_IRQ0_INTS_SM5_LSB _u(13) +#define PIO_IRQ0_INTS_SM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM4 +#define PIO_IRQ0_INTS_SM4_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM4_BITS _u(0x00001000) +#define PIO_IRQ0_INTS_SM4_MSB _u(12) +#define PIO_IRQ0_INTS_SM4_LSB _u(12) +#define PIO_IRQ0_INTS_SM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3 +#define PIO_IRQ0_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTS_SM3_MSB _u(11) +#define PIO_IRQ0_INTS_SM3_LSB _u(11) +#define PIO_IRQ0_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2 +#define PIO_IRQ0_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTS_SM2_MSB _u(10) +#define PIO_IRQ0_INTS_SM2_LSB _u(10) +#define PIO_IRQ0_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1 +#define PIO_IRQ0_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTS_SM1_MSB _u(9) +#define PIO_IRQ0_INTS_SM1_LSB _u(9) +#define PIO_IRQ0_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0 +#define PIO_IRQ0_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTS_SM0_MSB _u(8) +#define PIO_IRQ0_INTS_SM0_LSB _u(8) +#define PIO_IRQ0_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_TXNFULL +#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_TXNFULL +#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_TXNFULL +#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_TXNFULL +#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ1_INTE +// Description : Interrupt Enable for irq1 +#define PIO_IRQ1_INTE_OFFSET _u(0x0000017c) +#define PIO_IRQ1_INTE_BITS _u(0x0000ffff) +#define PIO_IRQ1_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM7 +#define PIO_IRQ1_INTE_SM7_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM7_BITS _u(0x00008000) +#define PIO_IRQ1_INTE_SM7_MSB _u(15) +#define PIO_IRQ1_INTE_SM7_LSB _u(15) +#define PIO_IRQ1_INTE_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM6 +#define PIO_IRQ1_INTE_SM6_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM6_BITS _u(0x00004000) +#define PIO_IRQ1_INTE_SM6_MSB _u(14) +#define PIO_IRQ1_INTE_SM6_LSB _u(14) +#define PIO_IRQ1_INTE_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM5 +#define PIO_IRQ1_INTE_SM5_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM5_BITS _u(0x00002000) +#define PIO_IRQ1_INTE_SM5_MSB _u(13) +#define PIO_IRQ1_INTE_SM5_LSB _u(13) +#define PIO_IRQ1_INTE_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM4 +#define PIO_IRQ1_INTE_SM4_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM4_BITS _u(0x00001000) +#define PIO_IRQ1_INTE_SM4_MSB _u(12) +#define PIO_IRQ1_INTE_SM4_LSB _u(12) +#define PIO_IRQ1_INTE_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3 +#define PIO_IRQ1_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTE_SM3_MSB _u(11) +#define PIO_IRQ1_INTE_SM3_LSB _u(11) +#define PIO_IRQ1_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2 +#define PIO_IRQ1_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTE_SM2_MSB _u(10) +#define PIO_IRQ1_INTE_SM2_LSB _u(10) +#define PIO_IRQ1_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1 +#define PIO_IRQ1_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTE_SM1_MSB _u(9) +#define PIO_IRQ1_INTE_SM1_LSB _u(9) +#define PIO_IRQ1_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0 +#define PIO_IRQ1_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTE_SM0_MSB _u(8) +#define PIO_IRQ1_INTE_SM0_LSB _u(8) +#define PIO_IRQ1_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_TXNFULL +#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_TXNFULL +#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_TXNFULL +#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_TXNFULL +#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTF +// Description : Interrupt Force for irq1 +#define PIO_IRQ1_INTF_OFFSET _u(0x00000180) +#define PIO_IRQ1_INTF_BITS _u(0x0000ffff) +#define PIO_IRQ1_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM7 +#define PIO_IRQ1_INTF_SM7_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM7_BITS _u(0x00008000) +#define PIO_IRQ1_INTF_SM7_MSB _u(15) +#define PIO_IRQ1_INTF_SM7_LSB _u(15) +#define PIO_IRQ1_INTF_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM6 +#define PIO_IRQ1_INTF_SM6_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM6_BITS _u(0x00004000) +#define PIO_IRQ1_INTF_SM6_MSB _u(14) +#define PIO_IRQ1_INTF_SM6_LSB _u(14) +#define PIO_IRQ1_INTF_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM5 +#define PIO_IRQ1_INTF_SM5_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM5_BITS _u(0x00002000) +#define PIO_IRQ1_INTF_SM5_MSB _u(13) +#define PIO_IRQ1_INTF_SM5_LSB _u(13) +#define PIO_IRQ1_INTF_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM4 +#define PIO_IRQ1_INTF_SM4_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM4_BITS _u(0x00001000) +#define PIO_IRQ1_INTF_SM4_MSB _u(12) +#define PIO_IRQ1_INTF_SM4_LSB _u(12) +#define PIO_IRQ1_INTF_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3 +#define PIO_IRQ1_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTF_SM3_MSB _u(11) +#define PIO_IRQ1_INTF_SM3_LSB _u(11) +#define PIO_IRQ1_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2 +#define PIO_IRQ1_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTF_SM2_MSB _u(10) +#define PIO_IRQ1_INTF_SM2_LSB _u(10) +#define PIO_IRQ1_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1 +#define PIO_IRQ1_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTF_SM1_MSB _u(9) +#define PIO_IRQ1_INTF_SM1_LSB _u(9) +#define PIO_IRQ1_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0 +#define PIO_IRQ1_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTF_SM0_MSB _u(8) +#define PIO_IRQ1_INTF_SM0_LSB _u(8) +#define PIO_IRQ1_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_TXNFULL +#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_TXNFULL +#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_TXNFULL +#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_TXNFULL +#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTS +// Description : Interrupt status after masking & forcing for irq1 +#define PIO_IRQ1_INTS_OFFSET _u(0x00000184) +#define PIO_IRQ1_INTS_BITS _u(0x0000ffff) +#define PIO_IRQ1_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM7 +#define PIO_IRQ1_INTS_SM7_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM7_BITS _u(0x00008000) +#define PIO_IRQ1_INTS_SM7_MSB _u(15) +#define PIO_IRQ1_INTS_SM7_LSB _u(15) +#define PIO_IRQ1_INTS_SM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM6 +#define PIO_IRQ1_INTS_SM6_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM6_BITS _u(0x00004000) +#define PIO_IRQ1_INTS_SM6_MSB _u(14) +#define PIO_IRQ1_INTS_SM6_LSB _u(14) +#define PIO_IRQ1_INTS_SM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM5 +#define PIO_IRQ1_INTS_SM5_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM5_BITS _u(0x00002000) +#define PIO_IRQ1_INTS_SM5_MSB _u(13) +#define PIO_IRQ1_INTS_SM5_LSB _u(13) +#define PIO_IRQ1_INTS_SM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM4 +#define PIO_IRQ1_INTS_SM4_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM4_BITS _u(0x00001000) +#define PIO_IRQ1_INTS_SM4_MSB _u(12) +#define PIO_IRQ1_INTS_SM4_LSB _u(12) +#define PIO_IRQ1_INTS_SM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3 +#define PIO_IRQ1_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTS_SM3_MSB _u(11) +#define PIO_IRQ1_INTS_SM3_LSB _u(11) +#define PIO_IRQ1_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2 +#define PIO_IRQ1_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTS_SM2_MSB _u(10) +#define PIO_IRQ1_INTS_SM2_LSB _u(10) +#define PIO_IRQ1_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1 +#define PIO_IRQ1_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTS_SM1_MSB _u(9) +#define PIO_IRQ1_INTS_SM1_LSB _u(9) +#define PIO_IRQ1_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0 +#define PIO_IRQ1_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTS_SM0_MSB _u(8) +#define PIO_IRQ1_INTS_SM0_LSB _u(8) +#define PIO_IRQ1_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_TXNFULL +#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_TXNFULL +#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_TXNFULL +#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_TXNFULL +#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PIO_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/pll.h b/src/rp2350/hardware_regs/include/hardware/regs/pll.h new file mode 100644 index 000000000..fdf254d15 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/pll.h @@ -0,0 +1,199 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PLL +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PLL_H +#define _HARDWARE_REGS_PLL_H +// ============================================================================= +// Register : PLL_CS +// Description : Control and Status +// GENERAL CONSTRAINTS: +// Reference clock frequency min=5MHz, max=800MHz +// Feedback divider min=16, max=320 +// VCO frequency min=750MHz, max=1600MHz +#define PLL_CS_OFFSET _u(0x00000000) +#define PLL_CS_BITS _u(0xc000013f) +#define PLL_CS_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : PLL_CS_LOCK +// Description : PLL is locked +#define PLL_CS_LOCK_RESET _u(0x0) +#define PLL_CS_LOCK_BITS _u(0x80000000) +#define PLL_CS_LOCK_MSB _u(31) +#define PLL_CS_LOCK_LSB _u(31) +#define PLL_CS_LOCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_LOCK_N +// Description : PLL is not locked +// Ideally this is cleared when PLL lock is seen and this should +// never normally be set +#define PLL_CS_LOCK_N_RESET _u(0x0) +#define PLL_CS_LOCK_N_BITS _u(0x40000000) +#define PLL_CS_LOCK_N_MSB _u(30) +#define PLL_CS_LOCK_N_LSB _u(30) +#define PLL_CS_LOCK_N_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_BYPASS +// Description : Passes the reference clock to the output instead of the divided +// VCO. The VCO continues to run so the user can switch between +// the reference clock and the divided VCO but the output will +// glitch when doing so. +#define PLL_CS_BYPASS_RESET _u(0x0) +#define PLL_CS_BYPASS_BITS _u(0x00000100) +#define PLL_CS_BYPASS_MSB _u(8) +#define PLL_CS_BYPASS_LSB _u(8) +#define PLL_CS_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_REFDIV +// Description : Divides the PLL input reference clock. +// Behaviour is undefined for div=0. +// PLL output will be unpredictable during refdiv changes, wait +// for lock=1 before using it. +#define PLL_CS_REFDIV_RESET _u(0x01) +#define PLL_CS_REFDIV_BITS _u(0x0000003f) +#define PLL_CS_REFDIV_MSB _u(5) +#define PLL_CS_REFDIV_LSB _u(0) +#define PLL_CS_REFDIV_ACCESS "RW" +// ============================================================================= +// Register : PLL_PWR +// Description : Controls the PLL power modes. +#define PLL_PWR_OFFSET _u(0x00000004) +#define PLL_PWR_BITS _u(0x0000002d) +#define PLL_PWR_RESET _u(0x0000002d) +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_VCOPD +// Description : PLL VCO powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_VCOPD_RESET _u(0x1) +#define PLL_PWR_VCOPD_BITS _u(0x00000020) +#define PLL_PWR_VCOPD_MSB _u(5) +#define PLL_PWR_VCOPD_LSB _u(5) +#define PLL_PWR_VCOPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_POSTDIVPD +// Description : PLL post divider powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_POSTDIVPD_RESET _u(0x1) +#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008) +#define PLL_PWR_POSTDIVPD_MSB _u(3) +#define PLL_PWR_POSTDIVPD_LSB _u(3) +#define PLL_PWR_POSTDIVPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_DSMPD +// Description : PLL DSM powerdown +// Nothing is achieved by setting this low. +#define PLL_PWR_DSMPD_RESET _u(0x1) +#define PLL_PWR_DSMPD_BITS _u(0x00000004) +#define PLL_PWR_DSMPD_MSB _u(2) +#define PLL_PWR_DSMPD_LSB _u(2) +#define PLL_PWR_DSMPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_PD +// Description : PLL powerdown +// To save power set high when PLL output not required. +#define PLL_PWR_PD_RESET _u(0x1) +#define PLL_PWR_PD_BITS _u(0x00000001) +#define PLL_PWR_PD_MSB _u(0) +#define PLL_PWR_PD_LSB _u(0) +#define PLL_PWR_PD_ACCESS "RW" +// ============================================================================= +// Register : PLL_FBDIV_INT +// Description : Feedback divisor +// (note: this PLL does not support fractional division) +// see ctrl reg description for constraints +#define PLL_FBDIV_INT_OFFSET _u(0x00000008) +#define PLL_FBDIV_INT_BITS _u(0x00000fff) +#define PLL_FBDIV_INT_RESET _u(0x00000000) +#define PLL_FBDIV_INT_MSB _u(11) +#define PLL_FBDIV_INT_LSB _u(0) +#define PLL_FBDIV_INT_ACCESS "RW" +// ============================================================================= +// Register : PLL_PRIM +// Description : Controls the PLL post dividers for the primary output +// (note: this PLL does not have a secondary output) +// the primary output is driven from VCO divided by +// postdiv1*postdiv2 +#define PLL_PRIM_OFFSET _u(0x0000000c) +#define PLL_PRIM_BITS _u(0x00077000) +#define PLL_PRIM_RESET _u(0x00077000) +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV1 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV1_RESET _u(0x7) +#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000) +#define PLL_PRIM_POSTDIV1_MSB _u(18) +#define PLL_PRIM_POSTDIV1_LSB _u(16) +#define PLL_PRIM_POSTDIV1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV2 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV2_RESET _u(0x7) +#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000) +#define PLL_PRIM_POSTDIV2_MSB _u(14) +#define PLL_PRIM_POSTDIV2_LSB _u(12) +#define PLL_PRIM_POSTDIV2_ACCESS "RW" +// ============================================================================= +// Register : PLL_INTR +// Description : Raw Interrupts +#define PLL_INTR_OFFSET _u(0x00000010) +#define PLL_INTR_BITS _u(0x00000001) +#define PLL_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTR_LOCK_N_STICKY +#define PLL_INTR_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTR_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTR_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTR_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTR_LOCK_N_STICKY_ACCESS "WC" +// ============================================================================= +// Register : PLL_INTE +// Description : Interrupt Enable +#define PLL_INTE_OFFSET _u(0x00000014) +#define PLL_INTE_BITS _u(0x00000001) +#define PLL_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTE_LOCK_N_STICKY +#define PLL_INTE_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTE_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTE_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTE_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTE_LOCK_N_STICKY_ACCESS "RW" +// ============================================================================= +// Register : PLL_INTF +// Description : Interrupt Force +#define PLL_INTF_OFFSET _u(0x00000018) +#define PLL_INTF_BITS _u(0x00000001) +#define PLL_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTF_LOCK_N_STICKY +#define PLL_INTF_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTF_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTF_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTF_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTF_LOCK_N_STICKY_ACCESS "RW" +// ============================================================================= +// Register : PLL_INTS +// Description : Interrupt status after masking & forcing +#define PLL_INTS_OFFSET _u(0x0000001c) +#define PLL_INTS_BITS _u(0x00000001) +#define PLL_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTS_LOCK_N_STICKY +#define PLL_INTS_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTS_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTS_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTS_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTS_LOCK_N_STICKY_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PLL_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/powman.h b/src/rp2350/hardware_regs/include/hardware/regs/powman.h new file mode 100644 index 000000000..edfbabbcc --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/powman.h @@ -0,0 +1,2194 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : POWMAN +// Version : 1 +// Bus type : apb +// Description : Controls vreg, bor, lposc, chip resets & xosc startup, +// powman and provides scratch register for general use and for +// bootcode use +// ============================================================================= +#ifndef _HARDWARE_REGS_POWMAN_H +#define _HARDWARE_REGS_POWMAN_H +// ============================================================================= +// Register : POWMAN_BADPASSWD +// Description : Indicates a bad password has been used +#define POWMAN_BADPASSWD_OFFSET _u(0x00000000) +#define POWMAN_BADPASSWD_BITS _u(0x00000001) +#define POWMAN_BADPASSWD_RESET _u(0x00000000) +#define POWMAN_BADPASSWD_MSB _u(0) +#define POWMAN_BADPASSWD_LSB _u(0) +#define POWMAN_BADPASSWD_ACCESS "WC" +// ============================================================================= +// Register : POWMAN_VREG_CTRL +// Description : Voltage Regulator Control +#define POWMAN_VREG_CTRL_OFFSET _u(0x00000004) +#define POWMAN_VREG_CTRL_BITS _u(0x0000b170) +#define POWMAN_VREG_CTRL_RESET _u(0x00008050) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_RST_N +// Description : returns the regulator to its startup settings +// 0 - reset +// 1 - not reset (default) +#define POWMAN_VREG_CTRL_RST_N_RESET _u(0x1) +#define POWMAN_VREG_CTRL_RST_N_BITS _u(0x00008000) +#define POWMAN_VREG_CTRL_RST_N_MSB _u(15) +#define POWMAN_VREG_CTRL_RST_N_LSB _u(15) +#define POWMAN_VREG_CTRL_RST_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_UNLOCK +// Description : unlocks the VREG control interface after power up +// 0 - Locked (default) +// 1 - Unlocked +// It cannot be relocked when it is unlocked. +#define POWMAN_VREG_CTRL_UNLOCK_RESET _u(0x0) +#define POWMAN_VREG_CTRL_UNLOCK_BITS _u(0x00002000) +#define POWMAN_VREG_CTRL_UNLOCK_MSB _u(13) +#define POWMAN_VREG_CTRL_UNLOCK_LSB _u(13) +#define POWMAN_VREG_CTRL_UNLOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_ISOLATE +// Description : isolates the VREG control interface +// 0 - not isolated (default) +// 1 - isolated +#define POWMAN_VREG_CTRL_ISOLATE_RESET _u(0x0) +#define POWMAN_VREG_CTRL_ISOLATE_BITS _u(0x00001000) +#define POWMAN_VREG_CTRL_ISOLATE_MSB _u(12) +#define POWMAN_VREG_CTRL_ISOLATE_LSB _u(12) +#define POWMAN_VREG_CTRL_ISOLATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT +// Description : 0=not disabled, 1=enabled +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_RESET _u(0x0) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_BITS _u(0x00000100) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_MSB _u(8) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_LSB _u(8) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_HT_TH +// Description : high temperature protection threshold +// regulator power transistors are disabled when junction +// temperature exceeds threshold +// 000 - 100C +// 001 - 105C +// 010 - 110C +// 011 - 115C +// 100 - 120C +// 101 - 125C +// 110 - 135C +// 111 - 150C +#define POWMAN_VREG_CTRL_HT_TH_RESET _u(0x5) +#define POWMAN_VREG_CTRL_HT_TH_BITS _u(0x00000070) +#define POWMAN_VREG_CTRL_HT_TH_MSB _u(6) +#define POWMAN_VREG_CTRL_HT_TH_LSB _u(4) +#define POWMAN_VREG_CTRL_HT_TH_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_VREG_STS +// Description : Voltage Regulator Status +#define POWMAN_VREG_STS_OFFSET _u(0x00000008) +#define POWMAN_VREG_STS_BITS _u(0x00000011) +#define POWMAN_VREG_STS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_STS_VOUT_OK +// Description : output regulation status +// 0=not in regulation, 1=in regulation +#define POWMAN_VREG_STS_VOUT_OK_RESET _u(0x0) +#define POWMAN_VREG_STS_VOUT_OK_BITS _u(0x00000010) +#define POWMAN_VREG_STS_VOUT_OK_MSB _u(4) +#define POWMAN_VREG_STS_VOUT_OK_LSB _u(4) +#define POWMAN_VREG_STS_VOUT_OK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_STS_STARTUP +// Description : startup status +// 0=startup complete, 1=starting up +#define POWMAN_VREG_STS_STARTUP_RESET _u(0x0) +#define POWMAN_VREG_STS_STARTUP_BITS _u(0x00000001) +#define POWMAN_VREG_STS_STARTUP_MSB _u(0) +#define POWMAN_VREG_STS_STARTUP_LSB _u(0) +#define POWMAN_VREG_STS_STARTUP_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_VREG +// Description : Voltage Regulator Settings +#define POWMAN_VREG_OFFSET _u(0x0000000c) +#define POWMAN_VREG_BITS _u(0x000081f2) +#define POWMAN_VREG_RESET _u(0x000000b0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_UPDATE_IN_PROGRESS +// Description : regulator state is being updated +// writes to the vreg register will be ignored when this field is +// set +#define POWMAN_VREG_UPDATE_IN_PROGRESS_RESET _u(0x0) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_BITS _u(0x00008000) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_MSB _u(15) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_LSB _u(15) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_VSEL +// Description : output voltage select +// the regulator output voltage is limited to 1.3V unless the +// voltage limit +// is disabled using the disable_voltage_limit field in the +// vreg_ctrl register +// 00000 - 0.55V +// 00001 - 0.60V +// 00010 - 0.65V +// 00011 - 0.70V +// 00100 - 0.75V +// 00101 - 0.80V +// 00110 - 0.85V +// 00111 - 0.90V +// 01000 - 0.95V +// 01001 - 1.00V +// 01010 - 1.05V +// 01011 - 1.10V (default) +// 01100 - 1.15V +// 01101 - 1.20V +// 01110 - 1.25V +// 01111 - 1.30V +// 10000 - 1.35V +// 10001 - 1.40V +// 10010 - 1.50V +// 10011 - 1.60V +// 10100 - 1.65V +// 10101 - 1.70V +// 10110 - 1.80V +// 10111 - 1.90V +// 11000 - 2.00V +// 11001 - 2.35V +// 11010 - 2.50V +// 11011 - 2.65V +// 11100 - 2.80V +// 11101 - 3.00V +// 11110 - 3.15V +// 11111 - 3.30V +#define POWMAN_VREG_VSEL_RESET _u(0x0b) +#define POWMAN_VREG_VSEL_BITS _u(0x000001f0) +#define POWMAN_VREG_VSEL_MSB _u(8) +#define POWMAN_VREG_VSEL_LSB _u(4) +#define POWMAN_VREG_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define POWMAN_VREG_HIZ_RESET _u(0x0) +#define POWMAN_VREG_HIZ_BITS _u(0x00000002) +#define POWMAN_VREG_HIZ_MSB _u(1) +#define POWMAN_VREG_HIZ_LSB _u(1) +#define POWMAN_VREG_HIZ_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_VREG_LP_ENTRY +// Description : Voltage Regulator Low Power Entry Settings +#define POWMAN_VREG_LP_ENTRY_OFFSET _u(0x00000010) +#define POWMAN_VREG_LP_ENTRY_BITS _u(0x000001f6) +#define POWMAN_VREG_LP_ENTRY_RESET _u(0x000000b4) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_ENTRY_VSEL +// Description : output voltage select +// the regulator output voltage is limited to 1.3V unless the +// voltage limit +// is disabled using the disable_voltage_limit field in the +// vreg_ctrl register +// 00000 - 0.55V +// 00001 - 0.60V +// 00010 - 0.65V +// 00011 - 0.70V +// 00100 - 0.75V +// 00101 - 0.80V +// 00110 - 0.85V +// 00111 - 0.90V +// 01000 - 0.95V +// 01001 - 1.00V +// 01010 - 1.05V +// 01011 - 1.10V (default) +// 01100 - 1.15V +// 01101 - 1.20V +// 01110 - 1.25V +// 01111 - 1.30V +// 10000 - 1.35V +// 10001 - 1.40V +// 10010 - 1.50V +// 10011 - 1.60V +// 10100 - 1.65V +// 10101 - 1.70V +// 10110 - 1.80V +// 10111 - 1.90V +// 11000 - 2.00V +// 11001 - 2.35V +// 11010 - 2.50V +// 11011 - 2.65V +// 11100 - 2.80V +// 11101 - 3.00V +// 11110 - 3.15V +// 11111 - 3.30V +#define POWMAN_VREG_LP_ENTRY_VSEL_RESET _u(0x0b) +#define POWMAN_VREG_LP_ENTRY_VSEL_BITS _u(0x000001f0) +#define POWMAN_VREG_LP_ENTRY_VSEL_MSB _u(8) +#define POWMAN_VREG_LP_ENTRY_VSEL_LSB _u(4) +#define POWMAN_VREG_LP_ENTRY_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_ENTRY_MODE +// Description : selects either normal (switching) mode or low power (linear) +// mode +// low power mode can only be selected for output voltages up to +// 1.3V +// 0 = normal mode (switching) +// 1 = low power mode (linear) +#define POWMAN_VREG_LP_ENTRY_MODE_RESET _u(0x1) +#define POWMAN_VREG_LP_ENTRY_MODE_BITS _u(0x00000004) +#define POWMAN_VREG_LP_ENTRY_MODE_MSB _u(2) +#define POWMAN_VREG_LP_ENTRY_MODE_LSB _u(2) +#define POWMAN_VREG_LP_ENTRY_MODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_ENTRY_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define POWMAN_VREG_LP_ENTRY_HIZ_RESET _u(0x0) +#define POWMAN_VREG_LP_ENTRY_HIZ_BITS _u(0x00000002) +#define POWMAN_VREG_LP_ENTRY_HIZ_MSB _u(1) +#define POWMAN_VREG_LP_ENTRY_HIZ_LSB _u(1) +#define POWMAN_VREG_LP_ENTRY_HIZ_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_VREG_LP_EXIT +// Description : Voltage Regulator Low Power Exit Settings +#define POWMAN_VREG_LP_EXIT_OFFSET _u(0x00000014) +#define POWMAN_VREG_LP_EXIT_BITS _u(0x000001f6) +#define POWMAN_VREG_LP_EXIT_RESET _u(0x000000b0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_EXIT_VSEL +// Description : output voltage select +// the regulator output voltage is limited to 1.3V unless the +// voltage limit +// is disabled using the disable_voltage_limit field in the +// vreg_ctrl register +// 00000 - 0.55V +// 00001 - 0.60V +// 00010 - 0.65V +// 00011 - 0.70V +// 00100 - 0.75V +// 00101 - 0.80V +// 00110 - 0.85V +// 00111 - 0.90V +// 01000 - 0.95V +// 01001 - 1.00V +// 01010 - 1.05V +// 01011 - 1.10V (default) +// 01100 - 1.15V +// 01101 - 1.20V +// 01110 - 1.25V +// 01111 - 1.30V +// 10000 - 1.35V +// 10001 - 1.40V +// 10010 - 1.50V +// 10011 - 1.60V +// 10100 - 1.65V +// 10101 - 1.70V +// 10110 - 1.80V +// 10111 - 1.90V +// 11000 - 2.00V +// 11001 - 2.35V +// 11010 - 2.50V +// 11011 - 2.65V +// 11100 - 2.80V +// 11101 - 3.00V +// 11110 - 3.15V +// 11111 - 3.30V +#define POWMAN_VREG_LP_EXIT_VSEL_RESET _u(0x0b) +#define POWMAN_VREG_LP_EXIT_VSEL_BITS _u(0x000001f0) +#define POWMAN_VREG_LP_EXIT_VSEL_MSB _u(8) +#define POWMAN_VREG_LP_EXIT_VSEL_LSB _u(4) +#define POWMAN_VREG_LP_EXIT_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_EXIT_MODE +// Description : selects either normal (switching) mode or low power (linear) +// mode +// low power mode can only be selected for output voltages up to +// 1.3V +// 0 = normal mode (switching) +// 1 = low power mode (linear) +#define POWMAN_VREG_LP_EXIT_MODE_RESET _u(0x0) +#define POWMAN_VREG_LP_EXIT_MODE_BITS _u(0x00000004) +#define POWMAN_VREG_LP_EXIT_MODE_MSB _u(2) +#define POWMAN_VREG_LP_EXIT_MODE_LSB _u(2) +#define POWMAN_VREG_LP_EXIT_MODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_EXIT_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define POWMAN_VREG_LP_EXIT_HIZ_RESET _u(0x0) +#define POWMAN_VREG_LP_EXIT_HIZ_BITS _u(0x00000002) +#define POWMAN_VREG_LP_EXIT_HIZ_MSB _u(1) +#define POWMAN_VREG_LP_EXIT_HIZ_LSB _u(1) +#define POWMAN_VREG_LP_EXIT_HIZ_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD_CTRL +// Description : Brown-out Detection Control +#define POWMAN_BOD_CTRL_OFFSET _u(0x00000018) +#define POWMAN_BOD_CTRL_BITS _u(0x00001000) +#define POWMAN_BOD_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_CTRL_ISOLATE +// Description : isolates the brown-out detection control interface +// 0 - not isolated (default) +// 1 - isolated +#define POWMAN_BOD_CTRL_ISOLATE_RESET _u(0x0) +#define POWMAN_BOD_CTRL_ISOLATE_BITS _u(0x00001000) +#define POWMAN_BOD_CTRL_ISOLATE_MSB _u(12) +#define POWMAN_BOD_CTRL_ISOLATE_LSB _u(12) +#define POWMAN_BOD_CTRL_ISOLATE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD +// Description : Brown-out Detection Settings +#define POWMAN_BOD_OFFSET _u(0x0000001c) +#define POWMAN_BOD_BITS _u(0x000001f1) +#define POWMAN_BOD_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_VSEL +// Description : threshold select +// 00000 - 0.473V +// 00001 - 0.516V +// 00010 - 0.559V +// 00011 - 0.602V +// 00100 - 0.645VS +// 00101 - 0.688V +// 00110 - 0.731V +// 00111 - 0.774V +// 01000 - 0.817V +// 01001 - 0.860V (default) +// 01010 - 0.903V +// 01011 - 0.946V +// 01100 - 0.989V +// 01101 - 1.032V +// 01110 - 1.075V +// 01111 - 1.118V +// 10000 - 1.161 +// 10001 - 1.204V +#define POWMAN_BOD_VSEL_RESET _u(0x0b) +#define POWMAN_BOD_VSEL_BITS _u(0x000001f0) +#define POWMAN_BOD_VSEL_MSB _u(8) +#define POWMAN_BOD_VSEL_LSB _u(4) +#define POWMAN_BOD_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_EN +// Description : enable brown-out detection +// 0=not enabled, 1=enabled +#define POWMAN_BOD_EN_RESET _u(0x1) +#define POWMAN_BOD_EN_BITS _u(0x00000001) +#define POWMAN_BOD_EN_MSB _u(0) +#define POWMAN_BOD_EN_LSB _u(0) +#define POWMAN_BOD_EN_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD_LP_ENTRY +// Description : Brown-out Detection Low Power Entry Settings +#define POWMAN_BOD_LP_ENTRY_OFFSET _u(0x00000020) +#define POWMAN_BOD_LP_ENTRY_BITS _u(0x000001f1) +#define POWMAN_BOD_LP_ENTRY_RESET _u(0x000000b0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_ENTRY_VSEL +// Description : threshold select +// 00000 - 0.473V +// 00001 - 0.516V +// 00010 - 0.559V +// 00011 - 0.602V +// 00100 - 0.645VS +// 00101 - 0.688V +// 00110 - 0.731V +// 00111 - 0.774V +// 01000 - 0.817V +// 01001 - 0.860V (default) +// 01010 - 0.903V +// 01011 - 0.946V +// 01100 - 0.989V +// 01101 - 1.032V +// 01110 - 1.075V +// 01111 - 1.118V +// 10000 - 1.161 +// 10001 - 1.204V +#define POWMAN_BOD_LP_ENTRY_VSEL_RESET _u(0x0b) +#define POWMAN_BOD_LP_ENTRY_VSEL_BITS _u(0x000001f0) +#define POWMAN_BOD_LP_ENTRY_VSEL_MSB _u(8) +#define POWMAN_BOD_LP_ENTRY_VSEL_LSB _u(4) +#define POWMAN_BOD_LP_ENTRY_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_ENTRY_EN +// Description : enable brown-out detection +// 0=not enabled, 1=enabled +#define POWMAN_BOD_LP_ENTRY_EN_RESET _u(0x0) +#define POWMAN_BOD_LP_ENTRY_EN_BITS _u(0x00000001) +#define POWMAN_BOD_LP_ENTRY_EN_MSB _u(0) +#define POWMAN_BOD_LP_ENTRY_EN_LSB _u(0) +#define POWMAN_BOD_LP_ENTRY_EN_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD_LP_EXIT +// Description : Brown-out Detection Low Power Exit Settings +#define POWMAN_BOD_LP_EXIT_OFFSET _u(0x00000024) +#define POWMAN_BOD_LP_EXIT_BITS _u(0x000001f1) +#define POWMAN_BOD_LP_EXIT_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_EXIT_VSEL +// Description : threshold select +// 00000 - 0.473V +// 00001 - 0.516V +// 00010 - 0.559V +// 00011 - 0.602V +// 00100 - 0.645VS +// 00101 - 0.688V +// 00110 - 0.731V +// 00111 - 0.774V +// 01000 - 0.817V +// 01001 - 0.860V (default) +// 01010 - 0.903V +// 01011 - 0.946V +// 01100 - 0.989V +// 01101 - 1.032V +// 01110 - 1.075V +// 01111 - 1.118V +// 10000 - 1.161 +// 10001 - 1.204V +#define POWMAN_BOD_LP_EXIT_VSEL_RESET _u(0x0b) +#define POWMAN_BOD_LP_EXIT_VSEL_BITS _u(0x000001f0) +#define POWMAN_BOD_LP_EXIT_VSEL_MSB _u(8) +#define POWMAN_BOD_LP_EXIT_VSEL_LSB _u(4) +#define POWMAN_BOD_LP_EXIT_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_EXIT_EN +// Description : enable brown-out detection +// 0=not enabled, 1=enabled +#define POWMAN_BOD_LP_EXIT_EN_RESET _u(0x1) +#define POWMAN_BOD_LP_EXIT_EN_BITS _u(0x00000001) +#define POWMAN_BOD_LP_EXIT_EN_MSB _u(0) +#define POWMAN_BOD_LP_EXIT_EN_LSB _u(0) +#define POWMAN_BOD_LP_EXIT_EN_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_LPOSC +// Description : Low power oscillator control register. +#define POWMAN_LPOSC_OFFSET _u(0x00000028) +#define POWMAN_LPOSC_BITS _u(0x000003f3) +#define POWMAN_LPOSC_RESET _u(0x00000203) +// ----------------------------------------------------------------------------- +// Field : POWMAN_LPOSC_TRIM +// Description : Frequency trim - the trim step is typically 1% of the reset +// frequency, but can be up to 3% +#define POWMAN_LPOSC_TRIM_RESET _u(0x20) +#define POWMAN_LPOSC_TRIM_BITS _u(0x000003f0) +#define POWMAN_LPOSC_TRIM_MSB _u(9) +#define POWMAN_LPOSC_TRIM_LSB _u(4) +#define POWMAN_LPOSC_TRIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_LPOSC_MODE +// Description : This feature has been removed +#define POWMAN_LPOSC_MODE_RESET _u(0x3) +#define POWMAN_LPOSC_MODE_BITS _u(0x00000003) +#define POWMAN_LPOSC_MODE_MSB _u(1) +#define POWMAN_LPOSC_MODE_LSB _u(0) +#define POWMAN_LPOSC_MODE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_CHIP_RESET +// Description : Chip reset control and status +#define POWMAN_CHIP_RESET_OFFSET _u(0x0000002c) +#define POWMAN_CHIP_RESET_BITS _u(0x1fef0011) +#define POWMAN_CHIP_RESET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM +// Description : Last reset was a watchdog timeout which was configured to reset +// the power-on state machine +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore no +// psm yes +// and does not change the power state +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS _u(0x10000000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_MSB _u(28) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_LSB _u(28) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ +// Description : Last reset was a system reset from the hazard debugger +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore no +// psm yes +// and does not change the power state +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_BITS _u(0x08000000) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_MSB _u(27) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_LSB _u(27) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_GLITCH_DETECT +// Description : Last reset was due to a power supply glitch +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore no +// psm yes +// and does not change the power state +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_BITS _u(0x04000000) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_MSB _u(26) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_LSB _u(26) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_SWCORE_PD +// Description : Last reset was a switched core powerdown +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_BITS _u(0x02000000) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_MSB _u(25) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_LSB _u(25) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE +// Description : Last reset was a watchdog timeout which was configured to reset +// the switched-core +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS _u(0x01000000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_MSB _u(24) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_LSB _u(24) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN +// Description : Last reset was a watchdog timeout which was configured to reset +// the power manager +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS _u(0x00800000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_MSB _u(23) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_LSB _u(23) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC +// Description : Last reset was a watchdog timeout which was configured to reset +// the power manager asynchronously +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS _u(0x00400000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_MSB _u(22) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_LSB _u(22) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_RESCUE +// Description : Last reset was a rescue reset from the debugger +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no, it sets this flag +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_RESCUE_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_RESCUE_BITS _u(0x00200000) +#define POWMAN_CHIP_RESET_HAD_RESCUE_MSB _u(21) +#define POWMAN_CHIP_RESET_HAD_RESCUE_LSB _u(21) +#define POWMAN_CHIP_RESET_HAD_RESCUE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_DP_RESET_REQ +// Description : Last reset was an reset request from the arm debugger +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_BITS _u(0x00080000) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_MSB _u(19) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB _u(19) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_RUN_LOW +// Description : Last reset was from the RUN pin +// This resets: +// double_tap flag no +// DP yes +// RPAP yes +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_BITS _u(0x00040000) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_MSB _u(18) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB _u(18) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_BOR +// Description : Last reset was from the brown-out detection block +// This resets: +// double_tap flag yes +// DP yes +// RPAP yes +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_BOR_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_BOR_BITS _u(0x00020000) +#define POWMAN_CHIP_RESET_HAD_BOR_MSB _u(17) +#define POWMAN_CHIP_RESET_HAD_BOR_LSB _u(17) +#define POWMAN_CHIP_RESET_HAD_BOR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_POR +// Description : Last reset was from the power-on reset +// This resets: +// double_tap flag yes +// DP yes +// RPAP yes +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_POR_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_POR_BITS _u(0x00010000) +#define POWMAN_CHIP_RESET_HAD_POR_MSB _u(16) +#define POWMAN_CHIP_RESET_HAD_POR_LSB _u(16) +#define POWMAN_CHIP_RESET_HAD_POR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_RESCUE_FLAG +// Description : This is set by a rescue reset from the RP-AP. +// Its purpose is to halt before the bootrom before booting from +// flash in order to recover from a boot lock-up. +// The debugger can then attach once the bootrom has been halted +// and flash some working code that does not lock up. +#define POWMAN_CHIP_RESET_RESCUE_FLAG_RESET _u(0x0) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_BITS _u(0x00000010) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_MSB _u(4) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_LSB _u(4) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_DOUBLE_TAP +// Description : This flag is set by double-tapping RUN. It tells bootcode to go +// into the bootloader. +#define POWMAN_CHIP_RESET_DOUBLE_TAP_RESET _u(0x0) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_BITS _u(0x00000001) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_MSB _u(0) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_LSB _u(0) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_WDSEL +// Description : Allows a watchdog reset to reset the internal state of powman +// in addition to the power-on state machine (PSM). +// Note that powman ignores watchdog resets that do not select at +// least the CLOCKS stage or earlier stages in the PSM. If using +// these bits, it's recommended to set PSM_WDSEL to all-ones in +// addition to the desired bits in this register. Failing to +// select CLOCKS or earlier will result in the POWMAN_WDSEL +// register having no effect. +#define POWMAN_WDSEL_OFFSET _u(0x00000030) +#define POWMAN_WDSEL_BITS _u(0x00001111) +#define POWMAN_WDSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_RSM +// Description : If set to 1, a watchdog reset will run the full power-on state +// machine (PSM) sequence +// From a user perspective it is the same as setting +// RSM_WDSEL_PROC_COLD +// From a hardware debug perspective it has the same effect as a +// reset from a glitch detector +#define POWMAN_WDSEL_RESET_RSM_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_RSM_BITS _u(0x00001000) +#define POWMAN_WDSEL_RESET_RSM_MSB _u(12) +#define POWMAN_WDSEL_RESET_RSM_LSB _u(12) +#define POWMAN_WDSEL_RESET_RSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_SWCORE +// Description : If set to 1, a watchdog reset will reset the switched core +// power domain and run the full power-on state machine (PSM) +// sequence +// From a user perspective it is the same as setting +// RSM_WDSEL_PROC_COLD +// From a hardware debug perspective it has the same effect as a +// power-on reset for the switched core power domain +#define POWMAN_WDSEL_RESET_SWCORE_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_SWCORE_BITS _u(0x00000100) +#define POWMAN_WDSEL_RESET_SWCORE_MSB _u(8) +#define POWMAN_WDSEL_RESET_SWCORE_LSB _u(8) +#define POWMAN_WDSEL_RESET_SWCORE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_POWMAN +// Description : If set to 1, a watchdog reset will restore powman defaults, +// reset the timer, reset the switched core power domain +// and run the full power-on state machine (PSM) sequence +// This relies on clk_ref running. Use reset_powman_async if that +// may not be true +#define POWMAN_WDSEL_RESET_POWMAN_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_POWMAN_BITS _u(0x00000010) +#define POWMAN_WDSEL_RESET_POWMAN_MSB _u(4) +#define POWMAN_WDSEL_RESET_POWMAN_LSB _u(4) +#define POWMAN_WDSEL_RESET_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_POWMAN_ASYNC +// Description : If set to 1, a watchdog reset will restore powman defaults, +// reset the timer, +// reset the switched core domain and run the full power-on state +// machine (PSM) sequence +// This does not rely on clk_ref running +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_BITS _u(0x00000001) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_MSB _u(0) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_LSB _u(0) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SEQ_CFG +// Description : For configuration of the power sequencer +// Writes are ignored while POWMAN_STATE_CHANGING=1 +#define POWMAN_SEQ_CFG_OFFSET _u(0x00000034) +#define POWMAN_SEQ_CFG_BITS _u(0x001311f3) +#define POWMAN_SEQ_CFG_RESET _u(0x001011f0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USING_FAST_POWCK +// Description : 0 indicates the POWMAN clock is running from the low power +// oscillator (32kHz) +// 1 indicates the POWMAN clock is running from the reference +// clock (2-50MHz) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_BITS _u(0x00100000) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_MSB _u(20) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_LSB _u(20) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USING_BOD_LP +// Description : Indicates the brown-out detector (BOD) mode +// 0 = BOD high power mode which is the default +// 1 = BOD low power mode +#define POWMAN_SEQ_CFG_USING_BOD_LP_RESET _u(0x0) +#define POWMAN_SEQ_CFG_USING_BOD_LP_BITS _u(0x00020000) +#define POWMAN_SEQ_CFG_USING_BOD_LP_MSB _u(17) +#define POWMAN_SEQ_CFG_USING_BOD_LP_LSB _u(17) +#define POWMAN_SEQ_CFG_USING_BOD_LP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USING_VREG_LP +// Description : Indicates the voltage regulator (VREG) mode +// 0 = VREG high power mode which is the default +// 1 = VREG low power mode +#define POWMAN_SEQ_CFG_USING_VREG_LP_RESET _u(0x0) +#define POWMAN_SEQ_CFG_USING_VREG_LP_BITS _u(0x00010000) +#define POWMAN_SEQ_CFG_USING_VREG_LP_MSB _u(16) +#define POWMAN_SEQ_CFG_USING_VREG_LP_LSB _u(16) +#define POWMAN_SEQ_CFG_USING_VREG_LP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_FAST_POWCK +// Description : selects the reference clock (clk_ref) as the source of the +// POWMAN clock when switched-core is powered. The POWMAN clock +// always switches to the slow clock (lposc) when switched-core is +// powered down because the fast clock stops running. +// 0 always run the POWMAN clock from the slow clock (lposc) +// 1 run the POWMAN clock from the fast clock when available +// This setting takes effect when a power up sequence is next run +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_BITS _u(0x00001000) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_MSB _u(12) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_LSB _u(12) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP +// Description : Set to 0 to stop the low power osc when the switched-core is +// powered down, which is unwise if using it to clock the timer +// This setting takes effect when the swcore is next powered down +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_BITS _u(0x00000100) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_MSB _u(8) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_LSB _u(8) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_BOD_HP +// Description : Set to 0 to prevent automatic switching to bod high power mode +// when switched-core is powered up +// This setting takes effect when the swcore is next powered up +#define POWMAN_SEQ_CFG_USE_BOD_HP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_BOD_HP_BITS _u(0x00000080) +#define POWMAN_SEQ_CFG_USE_BOD_HP_MSB _u(7) +#define POWMAN_SEQ_CFG_USE_BOD_HP_LSB _u(7) +#define POWMAN_SEQ_CFG_USE_BOD_HP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_BOD_LP +// Description : Set to 0 to prevent automatic switching to bod low power mode +// when switched-core is powered down +// This setting takes effect when the swcore is next powered down +#define POWMAN_SEQ_CFG_USE_BOD_LP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_BOD_LP_BITS _u(0x00000040) +#define POWMAN_SEQ_CFG_USE_BOD_LP_MSB _u(6) +#define POWMAN_SEQ_CFG_USE_BOD_LP_LSB _u(6) +#define POWMAN_SEQ_CFG_USE_BOD_LP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_VREG_HP +// Description : Set to 0 to prevent automatic switching to vreg high power mode +// when switched-core is powered up +// This setting takes effect when the swcore is next powered up +#define POWMAN_SEQ_CFG_USE_VREG_HP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_VREG_HP_BITS _u(0x00000020) +#define POWMAN_SEQ_CFG_USE_VREG_HP_MSB _u(5) +#define POWMAN_SEQ_CFG_USE_VREG_HP_LSB _u(5) +#define POWMAN_SEQ_CFG_USE_VREG_HP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_VREG_LP +// Description : Set to 0 to prevent automatic switching to vreg low power mode +// when switched-core is powered down +// This setting takes effect when the swcore is next powered down +#define POWMAN_SEQ_CFG_USE_VREG_LP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_VREG_LP_BITS _u(0x00000010) +#define POWMAN_SEQ_CFG_USE_VREG_LP_MSB _u(4) +#define POWMAN_SEQ_CFG_USE_VREG_LP_LSB _u(4) +#define POWMAN_SEQ_CFG_USE_VREG_LP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM0 +// Description : Specifies the power state of SRAM0 when powering up swcore from +// a low power state (P1.xxx) to a high power state (P0.0xx). +// 0=power-up +// 1=no change +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_RESET _u(0x0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS _u(0x00000002) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_MSB _u(1) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_LSB _u(1) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM1 +// Description : Specifies the power state of SRAM1 when powering up swcore from +// a low power state (P1.xxx) to a high power state (P0.0xx). +// 0=power-up +// 1=no change +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_RESET _u(0x0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS _u(0x00000001) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_MSB _u(0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_LSB _u(0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_STATE +// Description : This register controls the power state of the 4 power domains. +// The current power state is indicated in POWMAN_STATE_CURRENT +// which is read-only. +// To change the state, write to POWMAN_STATE_REQ. +// The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ +// corresponds to the power states +// defined in the datasheet: +// bit 3 = SWCORE +// bit 2 = XIP cache +// bit 1 = SRAM0 +// bit 0 = SRAM1 +// 0 = powered up +// 1 = powered down +// When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag +// is set while the Power Manager determines what is required. If +// an invalid transition is requested the Power Manager will still +// register the request in POWMAN_STATE_REQ but will also set the +// POWMAN_BAD_REQ flag. It will then implement the power-up +// requests and ignore the power down requests. To do nothing +// would risk entering an unrecoverable lock-up state. Invalid +// requests are: any combination of power up and power down +// requests any request that results in swcore boing powered and +// xip unpowered If the request is to power down the switched-core +// domain then POWMAN_STATE_WAITING stays active until the +// processors halt. During this time the POWMAN_STATE_REQ field +// can be re-written to change or cancel the request. When the +// power state transition begins the POWMAN_STATE_WAITING_flag is +// cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN +// register writes are ignored until the transition completes. +#define POWMAN_STATE_OFFSET _u(0x00000038) +#define POWMAN_STATE_BITS _u(0x00003fff) +#define POWMAN_STATE_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_CHANGING +#define POWMAN_STATE_CHANGING_RESET _u(0x0) +#define POWMAN_STATE_CHANGING_BITS _u(0x00002000) +#define POWMAN_STATE_CHANGING_MSB _u(13) +#define POWMAN_STATE_CHANGING_LSB _u(13) +#define POWMAN_STATE_CHANGING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_WAITING +#define POWMAN_STATE_WAITING_RESET _u(0x0) +#define POWMAN_STATE_WAITING_BITS _u(0x00001000) +#define POWMAN_STATE_WAITING_MSB _u(12) +#define POWMAN_STATE_WAITING_LSB _u(12) +#define POWMAN_STATE_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_BAD_HW_REQ +// Description : Bad hardware initiated state request. Went back to state 0 +// (i.e. everything powered up) +#define POWMAN_STATE_BAD_HW_REQ_RESET _u(0x0) +#define POWMAN_STATE_BAD_HW_REQ_BITS _u(0x00000800) +#define POWMAN_STATE_BAD_HW_REQ_MSB _u(11) +#define POWMAN_STATE_BAD_HW_REQ_LSB _u(11) +#define POWMAN_STATE_BAD_HW_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_BAD_SW_REQ +// Description : Bad software initiated state request. No action taken. +#define POWMAN_STATE_BAD_SW_REQ_RESET _u(0x0) +#define POWMAN_STATE_BAD_SW_REQ_BITS _u(0x00000400) +#define POWMAN_STATE_BAD_SW_REQ_MSB _u(10) +#define POWMAN_STATE_BAD_SW_REQ_LSB _u(10) +#define POWMAN_STATE_BAD_SW_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_PWRUP_WHILE_WAITING +// Description : Request ignored because of a pending pwrup request. See +// current_pwrup_req. Note this blocks powering up AND powering +// down. +#define POWMAN_STATE_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_BITS _u(0x00000200) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_MSB _u(9) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_LSB _u(9) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_REQ_IGNORED +#define POWMAN_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_STATE_REQ_IGNORED_BITS _u(0x00000100) +#define POWMAN_STATE_REQ_IGNORED_MSB _u(8) +#define POWMAN_STATE_REQ_IGNORED_LSB _u(8) +#define POWMAN_STATE_REQ_IGNORED_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_REQ +#define POWMAN_STATE_REQ_RESET _u(0x0) +#define POWMAN_STATE_REQ_BITS _u(0x000000f0) +#define POWMAN_STATE_REQ_MSB _u(7) +#define POWMAN_STATE_REQ_LSB _u(4) +#define POWMAN_STATE_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_CURRENT +#define POWMAN_STATE_CURRENT_RESET _u(0xf) +#define POWMAN_STATE_CURRENT_BITS _u(0x0000000f) +#define POWMAN_STATE_CURRENT_MSB _u(3) +#define POWMAN_STATE_CURRENT_LSB _u(0) +#define POWMAN_STATE_CURRENT_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_POW_FASTDIV +// Description : None +// divides the POWMAN clock to provide a tick for the delay module +// and state machines +// when clk_pow is running from the slow clock it is not divided +// when clk_pow is running from the fast clock it is divided by +// tick_div +#define POWMAN_POW_FASTDIV_OFFSET _u(0x0000003c) +#define POWMAN_POW_FASTDIV_BITS _u(0x000007ff) +#define POWMAN_POW_FASTDIV_RESET _u(0x00000040) +#define POWMAN_POW_FASTDIV_MSB _u(10) +#define POWMAN_POW_FASTDIV_LSB _u(0) +#define POWMAN_POW_FASTDIV_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_POW_DELAY +// Description : power state machine delays +#define POWMAN_POW_DELAY_OFFSET _u(0x00000040) +#define POWMAN_POW_DELAY_BITS _u(0x0000ffff) +#define POWMAN_POW_DELAY_RESET _u(0x00002011) +// ----------------------------------------------------------------------------- +// Field : POWMAN_POW_DELAY_SRAM_STEP +// Description : timing between the sram0 and sram1 power state machine steps +// measured in units of the powman tick period (>=1us), 0 gives a +// delay of 1 unit +#define POWMAN_POW_DELAY_SRAM_STEP_RESET _u(0x20) +#define POWMAN_POW_DELAY_SRAM_STEP_BITS _u(0x0000ff00) +#define POWMAN_POW_DELAY_SRAM_STEP_MSB _u(15) +#define POWMAN_POW_DELAY_SRAM_STEP_LSB _u(8) +#define POWMAN_POW_DELAY_SRAM_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_POW_DELAY_XIP_STEP +// Description : timing between the xip power state machine steps +// measured in units of the lposc period, 0 gives a delay of 1 +// unit +#define POWMAN_POW_DELAY_XIP_STEP_RESET _u(0x1) +#define POWMAN_POW_DELAY_XIP_STEP_BITS _u(0x000000f0) +#define POWMAN_POW_DELAY_XIP_STEP_MSB _u(7) +#define POWMAN_POW_DELAY_XIP_STEP_LSB _u(4) +#define POWMAN_POW_DELAY_XIP_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_POW_DELAY_SWCORE_STEP +// Description : timing between the swcore power state machine steps +// measured in units of the lposc period, 0 gives a delay of 1 +// unit +#define POWMAN_POW_DELAY_SWCORE_STEP_RESET _u(0x1) +#define POWMAN_POW_DELAY_SWCORE_STEP_BITS _u(0x0000000f) +#define POWMAN_POW_DELAY_SWCORE_STEP_MSB _u(3) +#define POWMAN_POW_DELAY_SWCORE_STEP_LSB _u(0) +#define POWMAN_POW_DELAY_SWCORE_STEP_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_EXT_CTRL0 +// Description : Configures a gpio as a power mode aware control output +#define POWMAN_EXT_CTRL0_OFFSET _u(0x00000044) +#define POWMAN_EXT_CTRL0_BITS _u(0x0000713f) +#define POWMAN_EXT_CTRL0_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_LP_EXIT_STATE +// Description : output level when exiting the low power state +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_BITS _u(0x00004000) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_MSB _u(14) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_LSB _u(14) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_LP_ENTRY_STATE +// Description : output level when entering the low power state +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_BITS _u(0x00002000) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_MSB _u(13) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_LSB _u(13) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_INIT_STATE +#define POWMAN_EXT_CTRL0_INIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_INIT_STATE_BITS _u(0x00001000) +#define POWMAN_EXT_CTRL0_INIT_STATE_MSB _u(12) +#define POWMAN_EXT_CTRL0_INIT_STATE_LSB _u(12) +#define POWMAN_EXT_CTRL0_INIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_INIT +#define POWMAN_EXT_CTRL0_INIT_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_INIT_BITS _u(0x00000100) +#define POWMAN_EXT_CTRL0_INIT_MSB _u(8) +#define POWMAN_EXT_CTRL0_INIT_LSB _u(8) +#define POWMAN_EXT_CTRL0_INIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_GPIO_SELECT +// Description : selects from gpio 0->30 +// set to 31 to disable this feature +#define POWMAN_EXT_CTRL0_GPIO_SELECT_RESET _u(0x3f) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_BITS _u(0x0000003f) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_MSB _u(5) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_LSB _u(0) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_EXT_CTRL1 +// Description : Configures a gpio as a power mode aware control output +#define POWMAN_EXT_CTRL1_OFFSET _u(0x00000048) +#define POWMAN_EXT_CTRL1_BITS _u(0x0000713f) +#define POWMAN_EXT_CTRL1_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_LP_EXIT_STATE +// Description : output level when exiting the low power state +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_BITS _u(0x00004000) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_MSB _u(14) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_LSB _u(14) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_LP_ENTRY_STATE +// Description : output level when entering the low power state +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_BITS _u(0x00002000) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_MSB _u(13) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_LSB _u(13) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_INIT_STATE +#define POWMAN_EXT_CTRL1_INIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_INIT_STATE_BITS _u(0x00001000) +#define POWMAN_EXT_CTRL1_INIT_STATE_MSB _u(12) +#define POWMAN_EXT_CTRL1_INIT_STATE_LSB _u(12) +#define POWMAN_EXT_CTRL1_INIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_INIT +#define POWMAN_EXT_CTRL1_INIT_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_INIT_BITS _u(0x00000100) +#define POWMAN_EXT_CTRL1_INIT_MSB _u(8) +#define POWMAN_EXT_CTRL1_INIT_LSB _u(8) +#define POWMAN_EXT_CTRL1_INIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_GPIO_SELECT +// Description : selects from gpio 0->30 +// set to 31 to disable this feature +#define POWMAN_EXT_CTRL1_GPIO_SELECT_RESET _u(0x3f) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_BITS _u(0x0000003f) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_MSB _u(5) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_LSB _u(0) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_EXT_TIME_REF +// Description : Select a GPIO to use as a time reference, the source can be +// used to drive the low power clock at 32kHz, or to provide a 1ms +// tick to the timer, or provide a 1Hz tick to the timer. The tick +// selection is controlled by the POWMAN_TIMER register. +#define POWMAN_EXT_TIME_REF_OFFSET _u(0x0000004c) +#define POWMAN_EXT_TIME_REF_BITS _u(0x00000013) +#define POWMAN_EXT_TIME_REF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_TIME_REF_DRIVE_LPCK +// Description : Use the selected GPIO to drive the 32kHz low power clock, in +// place of LPOSC. This field must only be written when +// POWMAN_TIMER_RUN=0 +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_RESET _u(0x0) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_BITS _u(0x00000010) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_MSB _u(4) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_LSB _u(4) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_TIME_REF_SOURCE_SEL +// Description : 0 -> gpio12 +// 1 -> gpio20 +// 2 -> gpio14 +// 3 -> gpio22 +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_RESET _u(0x0) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_BITS _u(0x00000003) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_MSB _u(1) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_LSB _u(0) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_LPOSC_FREQ_KHZ_INT +// Description : Informs the AON Timer of the integer component of the clock +// frequency when running off the LPOSC. +// Integer component of the LPOSC or GPIO clock source frequency +// in kHz. Default = 32 This field must only be written when +// POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 +#define POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET _u(0x00000050) +#define POWMAN_LPOSC_FREQ_KHZ_INT_BITS _u(0x0000003f) +#define POWMAN_LPOSC_FREQ_KHZ_INT_RESET _u(0x00000020) +#define POWMAN_LPOSC_FREQ_KHZ_INT_MSB _u(5) +#define POWMAN_LPOSC_FREQ_KHZ_INT_LSB _u(0) +#define POWMAN_LPOSC_FREQ_KHZ_INT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_LPOSC_FREQ_KHZ_FRAC +// Description : Informs the AON Timer of the fractional component of the clock +// frequency when running off the LPOSC. +// Fractional component of the LPOSC or GPIO clock source +// frequency in kHz. Default = 0.768 This field must only be +// written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET _u(0x00000054) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_RESET _u(0x0000c49c) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_MSB _u(15) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_LSB _u(0) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_XOSC_FREQ_KHZ_INT +// Description : Informs the AON Timer of the integer component of the clock +// frequency when running off the XOSC. +// Integer component of the XOSC frequency in kHz. Default = 12000 +// Must be >1 This field must only be written when +// POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 +#define POWMAN_XOSC_FREQ_KHZ_INT_OFFSET _u(0x00000058) +#define POWMAN_XOSC_FREQ_KHZ_INT_BITS _u(0x0000ffff) +#define POWMAN_XOSC_FREQ_KHZ_INT_RESET _u(0x00002ee0) +#define POWMAN_XOSC_FREQ_KHZ_INT_MSB _u(15) +#define POWMAN_XOSC_FREQ_KHZ_INT_LSB _u(0) +#define POWMAN_XOSC_FREQ_KHZ_INT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_XOSC_FREQ_KHZ_FRAC +// Description : Informs the AON Timer of the fractional component of the clock +// frequency when running off the XOSC. +// Fractional component of the XOSC frequency in kHz. This field +// must only be written when POWMAN_TIMER_RUN=0 or +// POWMAN_TIMER_USING_XOSC=0 +#define POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET _u(0x0000005c) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_RESET _u(0x00000000) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_MSB _u(15) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_LSB _u(0) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_63TO48 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_63TO48_OFFSET _u(0x00000060) +#define POWMAN_SET_TIME_63TO48_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_63TO48_RESET _u(0x00000000) +#define POWMAN_SET_TIME_63TO48_MSB _u(15) +#define POWMAN_SET_TIME_63TO48_LSB _u(0) +#define POWMAN_SET_TIME_63TO48_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_47TO32 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_47TO32_OFFSET _u(0x00000064) +#define POWMAN_SET_TIME_47TO32_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_47TO32_RESET _u(0x00000000) +#define POWMAN_SET_TIME_47TO32_MSB _u(15) +#define POWMAN_SET_TIME_47TO32_LSB _u(0) +#define POWMAN_SET_TIME_47TO32_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_31TO16 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_31TO16_OFFSET _u(0x00000068) +#define POWMAN_SET_TIME_31TO16_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_31TO16_RESET _u(0x00000000) +#define POWMAN_SET_TIME_31TO16_MSB _u(15) +#define POWMAN_SET_TIME_31TO16_LSB _u(0) +#define POWMAN_SET_TIME_31TO16_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_15TO0 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_15TO0_OFFSET _u(0x0000006c) +#define POWMAN_SET_TIME_15TO0_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_15TO0_RESET _u(0x00000000) +#define POWMAN_SET_TIME_15TO0_MSB _u(15) +#define POWMAN_SET_TIME_15TO0_LSB _u(0) +#define POWMAN_SET_TIME_15TO0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_READ_TIME_UPPER +// Description : None +// For reading bits 63:32 of the timer. When reading all 64 bits +// it is possible for the LOWER count to rollover during the read. +// It is recommended to read UPPER, then LOWER, then re-read UPPER +// and, if it has changed, re-read LOWER. +#define POWMAN_READ_TIME_UPPER_OFFSET _u(0x00000070) +#define POWMAN_READ_TIME_UPPER_BITS _u(0xffffffff) +#define POWMAN_READ_TIME_UPPER_RESET _u(0x00000000) +#define POWMAN_READ_TIME_UPPER_MSB _u(31) +#define POWMAN_READ_TIME_UPPER_LSB _u(0) +#define POWMAN_READ_TIME_UPPER_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_READ_TIME_LOWER +// Description : None +// For reading bits 31:0 of the timer. +#define POWMAN_READ_TIME_LOWER_OFFSET _u(0x00000074) +#define POWMAN_READ_TIME_LOWER_BITS _u(0xffffffff) +#define POWMAN_READ_TIME_LOWER_RESET _u(0x00000000) +#define POWMAN_READ_TIME_LOWER_MSB _u(31) +#define POWMAN_READ_TIME_LOWER_LSB _u(0) +#define POWMAN_READ_TIME_LOWER_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_63TO48 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_63TO48_OFFSET _u(0x00000078) +#define POWMAN_ALARM_TIME_63TO48_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_63TO48_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_63TO48_MSB _u(15) +#define POWMAN_ALARM_TIME_63TO48_LSB _u(0) +#define POWMAN_ALARM_TIME_63TO48_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_47TO32 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_47TO32_OFFSET _u(0x0000007c) +#define POWMAN_ALARM_TIME_47TO32_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_47TO32_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_47TO32_MSB _u(15) +#define POWMAN_ALARM_TIME_47TO32_LSB _u(0) +#define POWMAN_ALARM_TIME_47TO32_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_31TO16 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_31TO16_OFFSET _u(0x00000080) +#define POWMAN_ALARM_TIME_31TO16_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_31TO16_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_31TO16_MSB _u(15) +#define POWMAN_ALARM_TIME_31TO16_LSB _u(0) +#define POWMAN_ALARM_TIME_31TO16_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_15TO0 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_15TO0_OFFSET _u(0x00000084) +#define POWMAN_ALARM_TIME_15TO0_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_15TO0_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_15TO0_MSB _u(15) +#define POWMAN_ALARM_TIME_15TO0_LSB _u(0) +#define POWMAN_ALARM_TIME_15TO0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_TIMER +#define POWMAN_TIMER_OFFSET _u(0x00000088) +#define POWMAN_TIMER_BITS _u(0x000f2777) +#define POWMAN_TIMER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_GPIO_1HZ +// Description : Timer is synchronised to a 1hz gpio source +#define POWMAN_TIMER_USING_GPIO_1HZ_RESET _u(0x0) +#define POWMAN_TIMER_USING_GPIO_1HZ_BITS _u(0x00080000) +#define POWMAN_TIMER_USING_GPIO_1HZ_MSB _u(19) +#define POWMAN_TIMER_USING_GPIO_1HZ_LSB _u(19) +#define POWMAN_TIMER_USING_GPIO_1HZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_GPIO_1KHZ +// Description : Timer is running from a 1khz gpio source +#define POWMAN_TIMER_USING_GPIO_1KHZ_RESET _u(0x0) +#define POWMAN_TIMER_USING_GPIO_1KHZ_BITS _u(0x00040000) +#define POWMAN_TIMER_USING_GPIO_1KHZ_MSB _u(18) +#define POWMAN_TIMER_USING_GPIO_1KHZ_LSB _u(18) +#define POWMAN_TIMER_USING_GPIO_1KHZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_LPOSC +// Description : Timer is running from lposc +#define POWMAN_TIMER_USING_LPOSC_RESET _u(0x0) +#define POWMAN_TIMER_USING_LPOSC_BITS _u(0x00020000) +#define POWMAN_TIMER_USING_LPOSC_MSB _u(17) +#define POWMAN_TIMER_USING_LPOSC_LSB _u(17) +#define POWMAN_TIMER_USING_LPOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_XOSC +// Description : Timer is running from xosc +#define POWMAN_TIMER_USING_XOSC_RESET _u(0x0) +#define POWMAN_TIMER_USING_XOSC_BITS _u(0x00010000) +#define POWMAN_TIMER_USING_XOSC_MSB _u(16) +#define POWMAN_TIMER_USING_XOSC_LSB _u(16) +#define POWMAN_TIMER_USING_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_GPIO_1HZ +// Description : Selects the gpio source as the reference for the sec counter. +// The msec counter will continue to use the lposc or xosc +// reference. +#define POWMAN_TIMER_USE_GPIO_1HZ_RESET _u(0x0) +#define POWMAN_TIMER_USE_GPIO_1HZ_BITS _u(0x00002000) +#define POWMAN_TIMER_USE_GPIO_1HZ_MSB _u(13) +#define POWMAN_TIMER_USE_GPIO_1HZ_LSB _u(13) +#define POWMAN_TIMER_USE_GPIO_1HZ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_GPIO_1KHZ +// Description : switch to gpio as the source of the 1kHz timer tick +#define POWMAN_TIMER_USE_GPIO_1KHZ_RESET _u(0x0) +#define POWMAN_TIMER_USE_GPIO_1KHZ_BITS _u(0x00000400) +#define POWMAN_TIMER_USE_GPIO_1KHZ_MSB _u(10) +#define POWMAN_TIMER_USE_GPIO_1KHZ_LSB _u(10) +#define POWMAN_TIMER_USE_GPIO_1KHZ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_XOSC +// Description : switch to xosc as the source of the 1kHz timer tick +#define POWMAN_TIMER_USE_XOSC_RESET _u(0x0) +#define POWMAN_TIMER_USE_XOSC_BITS _u(0x00000200) +#define POWMAN_TIMER_USE_XOSC_MSB _u(9) +#define POWMAN_TIMER_USE_XOSC_LSB _u(9) +#define POWMAN_TIMER_USE_XOSC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_LPOSC +// Description : Switch to lposc as the source of the 1kHz timer tick +#define POWMAN_TIMER_USE_LPOSC_RESET _u(0x0) +#define POWMAN_TIMER_USE_LPOSC_BITS _u(0x00000100) +#define POWMAN_TIMER_USE_LPOSC_MSB _u(8) +#define POWMAN_TIMER_USE_LPOSC_LSB _u(8) +#define POWMAN_TIMER_USE_LPOSC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_ALARM +// Description : Alarm has fired. Write to 1 to clear the alarm. +#define POWMAN_TIMER_ALARM_RESET _u(0x0) +#define POWMAN_TIMER_ALARM_BITS _u(0x00000040) +#define POWMAN_TIMER_ALARM_MSB _u(6) +#define POWMAN_TIMER_ALARM_LSB _u(6) +#define POWMAN_TIMER_ALARM_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_PWRUP_ON_ALARM +// Description : Alarm wakes the chip from low power mode +#define POWMAN_TIMER_PWRUP_ON_ALARM_RESET _u(0x0) +#define POWMAN_TIMER_PWRUP_ON_ALARM_BITS _u(0x00000020) +#define POWMAN_TIMER_PWRUP_ON_ALARM_MSB _u(5) +#define POWMAN_TIMER_PWRUP_ON_ALARM_LSB _u(5) +#define POWMAN_TIMER_PWRUP_ON_ALARM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_ALARM_ENAB +// Description : Enables the alarm. The alarm must be disabled while writing the +// alarm time. +#define POWMAN_TIMER_ALARM_ENAB_RESET _u(0x0) +#define POWMAN_TIMER_ALARM_ENAB_BITS _u(0x00000010) +#define POWMAN_TIMER_ALARM_ENAB_MSB _u(4) +#define POWMAN_TIMER_ALARM_ENAB_LSB _u(4) +#define POWMAN_TIMER_ALARM_ENAB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_CLEAR +// Description : Clears the timer, does not disable the timer and does not +// affect the alarm. This control can be written at any time. +#define POWMAN_TIMER_CLEAR_RESET _u(0x0) +#define POWMAN_TIMER_CLEAR_BITS _u(0x00000004) +#define POWMAN_TIMER_CLEAR_MSB _u(2) +#define POWMAN_TIMER_CLEAR_LSB _u(2) +#define POWMAN_TIMER_CLEAR_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_RUN +// Description : Timer enable. Setting this bit causes the timer to begin +// counting up from its current value. Clearing this bit stops the +// timer from counting. +// +// Before enabling the timer, set the POWMAN_LPOSC_FREQ* and +// POWMAN_XOSC_FREQ* registers to configure the count rate, and +// initialise the current time by writing to SET_TIME_63TO48 +// through SET_TIME_15TO0. You must not write to the SET_TIME_x +// registers when the timer is running. +// +// Once configured, start the timer by setting POWMAN_TIMER_RUN=1. +// This will start the timer running from the LPOSC. When the XOSC +// is available switch the reference clock to XOSC then select it +// as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 +#define POWMAN_TIMER_RUN_RESET _u(0x0) +#define POWMAN_TIMER_RUN_BITS _u(0x00000002) +#define POWMAN_TIMER_RUN_MSB _u(1) +#define POWMAN_TIMER_RUN_LSB _u(1) +#define POWMAN_TIMER_RUN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_NONSEC_WRITE +// Description : Control whether Non-secure software can write to the timer +// registers. All other registers are hardwired to be inaccessible +// to Non-secure. +#define POWMAN_TIMER_NONSEC_WRITE_RESET _u(0x0) +#define POWMAN_TIMER_NONSEC_WRITE_BITS _u(0x00000001) +#define POWMAN_TIMER_NONSEC_WRITE_MSB _u(0) +#define POWMAN_TIMER_NONSEC_WRITE_LSB _u(0) +#define POWMAN_TIMER_NONSEC_WRITE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP0 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP0_OFFSET _u(0x0000008c) +#define POWMAN_PWRUP0_BITS _u(0x000007ff) +#define POWMAN_PWRUP0_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP0_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP0_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP0_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP0_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP0_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP0_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP0_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP0_STATUS_MSB _u(9) +#define POWMAN_PWRUP0_STATUS_LSB _u(9) +#define POWMAN_PWRUP0_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP0_MODE_RESET _u(0x0) +#define POWMAN_PWRUP0_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP0_MODE_MSB _u(8) +#define POWMAN_PWRUP0_MODE_LSB _u(8) +#define POWMAN_PWRUP0_MODE_ACCESS "RW" +#define POWMAN_PWRUP0_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP0_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP0_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP0_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP0_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP0_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP0_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP0_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP0_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP0_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP0_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP0_ENABLE_MSB _u(6) +#define POWMAN_PWRUP0_ENABLE_LSB _u(6) +#define POWMAN_PWRUP0_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_SOURCE +#define POWMAN_PWRUP0_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP0_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP0_SOURCE_MSB _u(5) +#define POWMAN_PWRUP0_SOURCE_LSB _u(0) +#define POWMAN_PWRUP0_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP1 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP1_OFFSET _u(0x00000090) +#define POWMAN_PWRUP1_BITS _u(0x000007ff) +#define POWMAN_PWRUP1_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP1_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP1_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP1_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP1_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP1_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP1_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP1_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP1_STATUS_MSB _u(9) +#define POWMAN_PWRUP1_STATUS_LSB _u(9) +#define POWMAN_PWRUP1_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP1_MODE_RESET _u(0x0) +#define POWMAN_PWRUP1_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP1_MODE_MSB _u(8) +#define POWMAN_PWRUP1_MODE_LSB _u(8) +#define POWMAN_PWRUP1_MODE_ACCESS "RW" +#define POWMAN_PWRUP1_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP1_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP1_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP1_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP1_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP1_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP1_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP1_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP1_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP1_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP1_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP1_ENABLE_MSB _u(6) +#define POWMAN_PWRUP1_ENABLE_LSB _u(6) +#define POWMAN_PWRUP1_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_SOURCE +#define POWMAN_PWRUP1_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP1_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP1_SOURCE_MSB _u(5) +#define POWMAN_PWRUP1_SOURCE_LSB _u(0) +#define POWMAN_PWRUP1_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP2 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP2_OFFSET _u(0x00000094) +#define POWMAN_PWRUP2_BITS _u(0x000007ff) +#define POWMAN_PWRUP2_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP2_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP2_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP2_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP2_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP2_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP2_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP2_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP2_STATUS_MSB _u(9) +#define POWMAN_PWRUP2_STATUS_LSB _u(9) +#define POWMAN_PWRUP2_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP2_MODE_RESET _u(0x0) +#define POWMAN_PWRUP2_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP2_MODE_MSB _u(8) +#define POWMAN_PWRUP2_MODE_LSB _u(8) +#define POWMAN_PWRUP2_MODE_ACCESS "RW" +#define POWMAN_PWRUP2_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP2_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP2_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP2_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP2_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP2_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP2_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP2_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP2_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP2_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP2_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP2_ENABLE_MSB _u(6) +#define POWMAN_PWRUP2_ENABLE_LSB _u(6) +#define POWMAN_PWRUP2_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_SOURCE +#define POWMAN_PWRUP2_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP2_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP2_SOURCE_MSB _u(5) +#define POWMAN_PWRUP2_SOURCE_LSB _u(0) +#define POWMAN_PWRUP2_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP3 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP3_OFFSET _u(0x00000098) +#define POWMAN_PWRUP3_BITS _u(0x000007ff) +#define POWMAN_PWRUP3_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP3_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP3_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP3_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP3_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP3_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP3_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP3_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP3_STATUS_MSB _u(9) +#define POWMAN_PWRUP3_STATUS_LSB _u(9) +#define POWMAN_PWRUP3_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP3_MODE_RESET _u(0x0) +#define POWMAN_PWRUP3_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP3_MODE_MSB _u(8) +#define POWMAN_PWRUP3_MODE_LSB _u(8) +#define POWMAN_PWRUP3_MODE_ACCESS "RW" +#define POWMAN_PWRUP3_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP3_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP3_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP3_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP3_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP3_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP3_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP3_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP3_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP3_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP3_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP3_ENABLE_MSB _u(6) +#define POWMAN_PWRUP3_ENABLE_LSB _u(6) +#define POWMAN_PWRUP3_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_SOURCE +#define POWMAN_PWRUP3_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP3_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP3_SOURCE_MSB _u(5) +#define POWMAN_PWRUP3_SOURCE_LSB _u(0) +#define POWMAN_PWRUP3_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_CURRENT_PWRUP_REQ +// Description : Indicates current powerup request state +// pwrup events can be cleared by removing the enable from the +// pwrup register. The alarm pwrup req can be cleared by clearing +// timer.alarm_enab +// 0 = chip reset, for the source of the last reset see +// POWMAN_CHIP_RESET +// 1 = pwrup0 +// 2 = pwrup1 +// 3 = pwrup2 +// 4 = pwrup3 +// 5 = coresight_pwrup +// 6 = alarm_pwrup +#define POWMAN_CURRENT_PWRUP_REQ_OFFSET _u(0x0000009c) +#define POWMAN_CURRENT_PWRUP_REQ_BITS _u(0x0000007f) +#define POWMAN_CURRENT_PWRUP_REQ_RESET _u(0x00000000) +#define POWMAN_CURRENT_PWRUP_REQ_MSB _u(6) +#define POWMAN_CURRENT_PWRUP_REQ_LSB _u(0) +#define POWMAN_CURRENT_PWRUP_REQ_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_LAST_SWCORE_PWRUP +// Description : Indicates which pwrup source triggered the last switched-core +// power up +// 0 = chip reset, for the source of the last reset see +// POWMAN_CHIP_RESET +// 1 = pwrup0 +// 2 = pwrup1 +// 3 = pwrup2 +// 4 = pwrup3 +// 5 = coresight_pwrup +// 6 = alarm_pwrup +#define POWMAN_LAST_SWCORE_PWRUP_OFFSET _u(0x000000a0) +#define POWMAN_LAST_SWCORE_PWRUP_BITS _u(0x0000007f) +#define POWMAN_LAST_SWCORE_PWRUP_RESET _u(0x00000000) +#define POWMAN_LAST_SWCORE_PWRUP_MSB _u(6) +#define POWMAN_LAST_SWCORE_PWRUP_LSB _u(0) +#define POWMAN_LAST_SWCORE_PWRUP_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_DBG_PWRCFG +#define POWMAN_DBG_PWRCFG_OFFSET _u(0x000000a4) +#define POWMAN_DBG_PWRCFG_BITS _u(0x00000001) +#define POWMAN_DBG_PWRCFG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_DBG_PWRCFG_IGNORE +// Description : Ignore pwrup req from debugger. If pwrup req is asserted then +// this will prevent power down and set powerdown blocked. Set +// ignore to stop paying attention to pwrup_req +#define POWMAN_DBG_PWRCFG_IGNORE_RESET _u(0x0) +#define POWMAN_DBG_PWRCFG_IGNORE_BITS _u(0x00000001) +#define POWMAN_DBG_PWRCFG_IGNORE_MSB _u(0) +#define POWMAN_DBG_PWRCFG_IGNORE_LSB _u(0) +#define POWMAN_DBG_PWRCFG_IGNORE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOTDIS +// Description : Tell the bootrom to ignore the BOOT0..3 registers following the +// next RSM reset (e.g. the next core power down/up). +// +// If an early boot stage has soft-locked some OTP pages in order +// to protect their contents from later stages, there is a risk +// that Secure code running at a later stage can unlock the pages +// by powering the core up and down. +// +// This register can be used to ensure that the bootloader runs as +// normal on the next power up, preventing Secure code at a later +// stage from accessing OTP in its unlocked state. +// +// Should be used in conjunction with the OTP BOOTDIS register. +#define POWMAN_BOOTDIS_OFFSET _u(0x000000a8) +#define POWMAN_BOOTDIS_BITS _u(0x00000003) +#define POWMAN_BOOTDIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOOTDIS_NEXT +// Description : This flag always ORs writes into its current contents. It can +// be set but not cleared by software. +// +// The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the +// core is powered down. Simultaneously, the BOOTDIS_NEXT bit is +// cleared. Setting this bit means that the BOOT0..3 registers +// will be ignored following the next reset of the RSM by powman. +// +// This flag should be set by an early boot stage that has soft- +// locked OTP pages, to prevent later stages from unlocking it by +// power cycling. +#define POWMAN_BOOTDIS_NEXT_RESET _u(0x0) +#define POWMAN_BOOTDIS_NEXT_BITS _u(0x00000002) +#define POWMAN_BOOTDIS_NEXT_MSB _u(1) +#define POWMAN_BOOTDIS_NEXT_LSB _u(1) +#define POWMAN_BOOTDIS_NEXT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOOTDIS_NOW +// Description : When powman resets the RSM, the current value of BOOTDIS_NEXT +// is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. +// +// The bootrom checks this flag before reading the BOOT0..3 +// registers. If it is set, the bootrom clears it, and ignores the +// BOOT registers. This prevents Secure software from diverting +// the boot path before a bootloader has had the chance to soft +// lock OTP pages containing sensitive data. +#define POWMAN_BOOTDIS_NOW_RESET _u(0x0) +#define POWMAN_BOOTDIS_NOW_BITS _u(0x00000001) +#define POWMAN_BOOTDIS_NOW_MSB _u(0) +#define POWMAN_BOOTDIS_NOW_LSB _u(0) +#define POWMAN_BOOTDIS_NOW_ACCESS "WC" +// ============================================================================= +// Register : POWMAN_DBGCONFIG +#define POWMAN_DBGCONFIG_OFFSET _u(0x000000ac) +#define POWMAN_DBGCONFIG_BITS _u(0x0000000f) +#define POWMAN_DBGCONFIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_DBGCONFIG_DP_INSTID +// Description : Configure DP instance ID for SWD multidrop selection. +// Recommend that this is NOT changed until you require debug +// access in multi-chip environment +#define POWMAN_DBGCONFIG_DP_INSTID_RESET _u(0x0) +#define POWMAN_DBGCONFIG_DP_INSTID_BITS _u(0x0000000f) +#define POWMAN_DBGCONFIG_DP_INSTID_MSB _u(3) +#define POWMAN_DBGCONFIG_DP_INSTID_LSB _u(0) +#define POWMAN_DBGCONFIG_DP_INSTID_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH0 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH0_OFFSET _u(0x000000b0) +#define POWMAN_SCRATCH0_BITS _u(0xffffffff) +#define POWMAN_SCRATCH0_RESET _u(0x00000000) +#define POWMAN_SCRATCH0_MSB _u(31) +#define POWMAN_SCRATCH0_LSB _u(0) +#define POWMAN_SCRATCH0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH1 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH1_OFFSET _u(0x000000b4) +#define POWMAN_SCRATCH1_BITS _u(0xffffffff) +#define POWMAN_SCRATCH1_RESET _u(0x00000000) +#define POWMAN_SCRATCH1_MSB _u(31) +#define POWMAN_SCRATCH1_LSB _u(0) +#define POWMAN_SCRATCH1_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH2 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH2_OFFSET _u(0x000000b8) +#define POWMAN_SCRATCH2_BITS _u(0xffffffff) +#define POWMAN_SCRATCH2_RESET _u(0x00000000) +#define POWMAN_SCRATCH2_MSB _u(31) +#define POWMAN_SCRATCH2_LSB _u(0) +#define POWMAN_SCRATCH2_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH3 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH3_OFFSET _u(0x000000bc) +#define POWMAN_SCRATCH3_BITS _u(0xffffffff) +#define POWMAN_SCRATCH3_RESET _u(0x00000000) +#define POWMAN_SCRATCH3_MSB _u(31) +#define POWMAN_SCRATCH3_LSB _u(0) +#define POWMAN_SCRATCH3_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH4 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH4_OFFSET _u(0x000000c0) +#define POWMAN_SCRATCH4_BITS _u(0xffffffff) +#define POWMAN_SCRATCH4_RESET _u(0x00000000) +#define POWMAN_SCRATCH4_MSB _u(31) +#define POWMAN_SCRATCH4_LSB _u(0) +#define POWMAN_SCRATCH4_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH5 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH5_OFFSET _u(0x000000c4) +#define POWMAN_SCRATCH5_BITS _u(0xffffffff) +#define POWMAN_SCRATCH5_RESET _u(0x00000000) +#define POWMAN_SCRATCH5_MSB _u(31) +#define POWMAN_SCRATCH5_LSB _u(0) +#define POWMAN_SCRATCH5_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH6 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH6_OFFSET _u(0x000000c8) +#define POWMAN_SCRATCH6_BITS _u(0xffffffff) +#define POWMAN_SCRATCH6_RESET _u(0x00000000) +#define POWMAN_SCRATCH6_MSB _u(31) +#define POWMAN_SCRATCH6_LSB _u(0) +#define POWMAN_SCRATCH6_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH7 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH7_OFFSET _u(0x000000cc) +#define POWMAN_SCRATCH7_BITS _u(0xffffffff) +#define POWMAN_SCRATCH7_RESET _u(0x00000000) +#define POWMAN_SCRATCH7_MSB _u(31) +#define POWMAN_SCRATCH7_LSB _u(0) +#define POWMAN_SCRATCH7_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT0 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT0_OFFSET _u(0x000000d0) +#define POWMAN_BOOT0_BITS _u(0xffffffff) +#define POWMAN_BOOT0_RESET _u(0x00000000) +#define POWMAN_BOOT0_MSB _u(31) +#define POWMAN_BOOT0_LSB _u(0) +#define POWMAN_BOOT0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT1 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT1_OFFSET _u(0x000000d4) +#define POWMAN_BOOT1_BITS _u(0xffffffff) +#define POWMAN_BOOT1_RESET _u(0x00000000) +#define POWMAN_BOOT1_MSB _u(31) +#define POWMAN_BOOT1_LSB _u(0) +#define POWMAN_BOOT1_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT2 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT2_OFFSET _u(0x000000d8) +#define POWMAN_BOOT2_BITS _u(0xffffffff) +#define POWMAN_BOOT2_RESET _u(0x00000000) +#define POWMAN_BOOT2_MSB _u(31) +#define POWMAN_BOOT2_LSB _u(0) +#define POWMAN_BOOT2_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT3 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT3_OFFSET _u(0x000000dc) +#define POWMAN_BOOT3_BITS _u(0xffffffff) +#define POWMAN_BOOT3_RESET _u(0x00000000) +#define POWMAN_BOOT3_MSB _u(31) +#define POWMAN_BOOT3_LSB _u(0) +#define POWMAN_BOOT3_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_INTR +// Description : Raw Interrupts +#define POWMAN_INTR_OFFSET _u(0x000000e0) +#define POWMAN_INTR_BITS _u(0x0000000f) +#define POWMAN_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTR_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTR_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTR_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTR_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTR_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTR_STATE_REQ_IGNORED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_TIMER +#define POWMAN_INTR_TIMER_RESET _u(0x0) +#define POWMAN_INTR_TIMER_BITS _u(0x00000002) +#define POWMAN_INTR_TIMER_MSB _u(1) +#define POWMAN_INTR_TIMER_LSB _u(1) +#define POWMAN_INTR_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_VREG_OUTPUT_LOW +#define POWMAN_INTR_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTR_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTR_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTR_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTR_VREG_OUTPUT_LOW_ACCESS "WC" +// ============================================================================= +// Register : POWMAN_INTE +// Description : Interrupt Enable +#define POWMAN_INTE_OFFSET _u(0x000000e4) +#define POWMAN_INTE_BITS _u(0x0000000f) +#define POWMAN_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTE_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTE_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTE_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTE_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTE_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTE_STATE_REQ_IGNORED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_TIMER +#define POWMAN_INTE_TIMER_RESET _u(0x0) +#define POWMAN_INTE_TIMER_BITS _u(0x00000002) +#define POWMAN_INTE_TIMER_MSB _u(1) +#define POWMAN_INTE_TIMER_LSB _u(1) +#define POWMAN_INTE_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_VREG_OUTPUT_LOW +#define POWMAN_INTE_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTE_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTE_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTE_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTE_VREG_OUTPUT_LOW_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_INTF +// Description : Interrupt Force +#define POWMAN_INTF_OFFSET _u(0x000000e8) +#define POWMAN_INTF_BITS _u(0x0000000f) +#define POWMAN_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTF_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTF_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTF_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTF_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTF_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTF_STATE_REQ_IGNORED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_TIMER +#define POWMAN_INTF_TIMER_RESET _u(0x0) +#define POWMAN_INTF_TIMER_BITS _u(0x00000002) +#define POWMAN_INTF_TIMER_MSB _u(1) +#define POWMAN_INTF_TIMER_LSB _u(1) +#define POWMAN_INTF_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_VREG_OUTPUT_LOW +#define POWMAN_INTF_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTF_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTF_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTF_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTF_VREG_OUTPUT_LOW_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_INTS +// Description : Interrupt status after masking & forcing +#define POWMAN_INTS_OFFSET _u(0x000000ec) +#define POWMAN_INTS_BITS _u(0x0000000f) +#define POWMAN_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTS_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTS_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTS_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTS_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTS_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTS_STATE_REQ_IGNORED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_TIMER +#define POWMAN_INTS_TIMER_RESET _u(0x0) +#define POWMAN_INTS_TIMER_BITS _u(0x00000002) +#define POWMAN_INTS_TIMER_MSB _u(1) +#define POWMAN_INTS_TIMER_LSB _u(1) +#define POWMAN_INTS_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_VREG_OUTPUT_LOW +#define POWMAN_INTS_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTS_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTS_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTS_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTS_VREG_OUTPUT_LOW_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_POWMAN_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/psm.h b/src/rp2350/hardware_regs/include/hardware/regs/psm.h new file mode 100644 index 000000000..cad268a36 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/psm.h @@ -0,0 +1,741 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PSM +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PSM_H +#define _HARDWARE_REGS_PSM_H +// ============================================================================= +// Register : PSM_FRCE_ON +// Description : Force block out of reset (i.e. power it on) +#define PSM_FRCE_ON_OFFSET _u(0x00000000) +#define PSM_FRCE_ON_BITS _u(0x01ffffff) +#define PSM_FRCE_ON_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC1 +#define PSM_FRCE_ON_PROC1_RESET _u(0x0) +#define PSM_FRCE_ON_PROC1_BITS _u(0x01000000) +#define PSM_FRCE_ON_PROC1_MSB _u(24) +#define PSM_FRCE_ON_PROC1_LSB _u(24) +#define PSM_FRCE_ON_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC0 +#define PSM_FRCE_ON_PROC0_RESET _u(0x0) +#define PSM_FRCE_ON_PROC0_BITS _u(0x00800000) +#define PSM_FRCE_ON_PROC0_MSB _u(23) +#define PSM_FRCE_ON_PROC0_LSB _u(23) +#define PSM_FRCE_ON_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ACCESSCTRL +#define PSM_FRCE_ON_ACCESSCTRL_RESET _u(0x0) +#define PSM_FRCE_ON_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_FRCE_ON_ACCESSCTRL_MSB _u(22) +#define PSM_FRCE_ON_ACCESSCTRL_LSB _u(22) +#define PSM_FRCE_ON_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SIO +#define PSM_FRCE_ON_SIO_RESET _u(0x0) +#define PSM_FRCE_ON_SIO_BITS _u(0x00200000) +#define PSM_FRCE_ON_SIO_MSB _u(21) +#define PSM_FRCE_ON_SIO_LSB _u(21) +#define PSM_FRCE_ON_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XIP +#define PSM_FRCE_ON_XIP_RESET _u(0x0) +#define PSM_FRCE_ON_XIP_BITS _u(0x00100000) +#define PSM_FRCE_ON_XIP_MSB _u(20) +#define PSM_FRCE_ON_XIP_LSB _u(20) +#define PSM_FRCE_ON_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM9 +#define PSM_FRCE_ON_SRAM9_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM9_BITS _u(0x00080000) +#define PSM_FRCE_ON_SRAM9_MSB _u(19) +#define PSM_FRCE_ON_SRAM9_LSB _u(19) +#define PSM_FRCE_ON_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM8 +#define PSM_FRCE_ON_SRAM8_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM8_BITS _u(0x00040000) +#define PSM_FRCE_ON_SRAM8_MSB _u(18) +#define PSM_FRCE_ON_SRAM8_LSB _u(18) +#define PSM_FRCE_ON_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM7 +#define PSM_FRCE_ON_SRAM7_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM7_BITS _u(0x00020000) +#define PSM_FRCE_ON_SRAM7_MSB _u(17) +#define PSM_FRCE_ON_SRAM7_LSB _u(17) +#define PSM_FRCE_ON_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM6 +#define PSM_FRCE_ON_SRAM6_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM6_BITS _u(0x00010000) +#define PSM_FRCE_ON_SRAM6_MSB _u(16) +#define PSM_FRCE_ON_SRAM6_LSB _u(16) +#define PSM_FRCE_ON_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM5 +#define PSM_FRCE_ON_SRAM5_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM5_BITS _u(0x00008000) +#define PSM_FRCE_ON_SRAM5_MSB _u(15) +#define PSM_FRCE_ON_SRAM5_LSB _u(15) +#define PSM_FRCE_ON_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM4 +#define PSM_FRCE_ON_SRAM4_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM4_BITS _u(0x00004000) +#define PSM_FRCE_ON_SRAM4_MSB _u(14) +#define PSM_FRCE_ON_SRAM4_LSB _u(14) +#define PSM_FRCE_ON_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM3 +#define PSM_FRCE_ON_SRAM3_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM3_BITS _u(0x00002000) +#define PSM_FRCE_ON_SRAM3_MSB _u(13) +#define PSM_FRCE_ON_SRAM3_LSB _u(13) +#define PSM_FRCE_ON_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM2 +#define PSM_FRCE_ON_SRAM2_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM2_BITS _u(0x00001000) +#define PSM_FRCE_ON_SRAM2_MSB _u(12) +#define PSM_FRCE_ON_SRAM2_LSB _u(12) +#define PSM_FRCE_ON_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM1 +#define PSM_FRCE_ON_SRAM1_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000800) +#define PSM_FRCE_ON_SRAM1_MSB _u(11) +#define PSM_FRCE_ON_SRAM1_LSB _u(11) +#define PSM_FRCE_ON_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM0 +#define PSM_FRCE_ON_SRAM0_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000400) +#define PSM_FRCE_ON_SRAM0_MSB _u(10) +#define PSM_FRCE_ON_SRAM0_LSB _u(10) +#define PSM_FRCE_ON_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_BOOTRAM +#define PSM_FRCE_ON_BOOTRAM_RESET _u(0x0) +#define PSM_FRCE_ON_BOOTRAM_BITS _u(0x00000200) +#define PSM_FRCE_ON_BOOTRAM_MSB _u(9) +#define PSM_FRCE_ON_BOOTRAM_LSB _u(9) +#define PSM_FRCE_ON_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROM +#define PSM_FRCE_ON_ROM_RESET _u(0x0) +#define PSM_FRCE_ON_ROM_BITS _u(0x00000100) +#define PSM_FRCE_ON_ROM_MSB _u(8) +#define PSM_FRCE_ON_ROM_LSB _u(8) +#define PSM_FRCE_ON_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_BUSFABRIC +#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000080) +#define PSM_FRCE_ON_BUSFABRIC_MSB _u(7) +#define PSM_FRCE_ON_BUSFABRIC_LSB _u(7) +#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PSM_READY +#define PSM_FRCE_ON_PSM_READY_RESET _u(0x0) +#define PSM_FRCE_ON_PSM_READY_BITS _u(0x00000040) +#define PSM_FRCE_ON_PSM_READY_MSB _u(6) +#define PSM_FRCE_ON_PSM_READY_LSB _u(6) +#define PSM_FRCE_ON_PSM_READY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_CLOCKS +#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000020) +#define PSM_FRCE_ON_CLOCKS_MSB _u(5) +#define PSM_FRCE_ON_CLOCKS_LSB _u(5) +#define PSM_FRCE_ON_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_RESETS +#define PSM_FRCE_ON_RESETS_RESET _u(0x0) +#define PSM_FRCE_ON_RESETS_BITS _u(0x00000010) +#define PSM_FRCE_ON_RESETS_MSB _u(4) +#define PSM_FRCE_ON_RESETS_LSB _u(4) +#define PSM_FRCE_ON_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XOSC +#define PSM_FRCE_ON_XOSC_RESET _u(0x0) +#define PSM_FRCE_ON_XOSC_BITS _u(0x00000008) +#define PSM_FRCE_ON_XOSC_MSB _u(3) +#define PSM_FRCE_ON_XOSC_LSB _u(3) +#define PSM_FRCE_ON_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROSC +#define PSM_FRCE_ON_ROSC_RESET _u(0x0) +#define PSM_FRCE_ON_ROSC_BITS _u(0x00000004) +#define PSM_FRCE_ON_ROSC_MSB _u(2) +#define PSM_FRCE_ON_ROSC_LSB _u(2) +#define PSM_FRCE_ON_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_OTP +#define PSM_FRCE_ON_OTP_RESET _u(0x0) +#define PSM_FRCE_ON_OTP_BITS _u(0x00000002) +#define PSM_FRCE_ON_OTP_MSB _u(1) +#define PSM_FRCE_ON_OTP_LSB _u(1) +#define PSM_FRCE_ON_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC_COLD +#define PSM_FRCE_ON_PROC_COLD_RESET _u(0x0) +#define PSM_FRCE_ON_PROC_COLD_BITS _u(0x00000001) +#define PSM_FRCE_ON_PROC_COLD_MSB _u(0) +#define PSM_FRCE_ON_PROC_COLD_LSB _u(0) +#define PSM_FRCE_ON_PROC_COLD_ACCESS "RW" +// ============================================================================= +// Register : PSM_FRCE_OFF +// Description : Force into reset (i.e. power it off) +#define PSM_FRCE_OFF_OFFSET _u(0x00000004) +#define PSM_FRCE_OFF_BITS _u(0x01ffffff) +#define PSM_FRCE_OFF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC1 +#define PSM_FRCE_OFF_PROC1_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC1_BITS _u(0x01000000) +#define PSM_FRCE_OFF_PROC1_MSB _u(24) +#define PSM_FRCE_OFF_PROC1_LSB _u(24) +#define PSM_FRCE_OFF_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC0 +#define PSM_FRCE_OFF_PROC0_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC0_BITS _u(0x00800000) +#define PSM_FRCE_OFF_PROC0_MSB _u(23) +#define PSM_FRCE_OFF_PROC0_LSB _u(23) +#define PSM_FRCE_OFF_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ACCESSCTRL +#define PSM_FRCE_OFF_ACCESSCTRL_RESET _u(0x0) +#define PSM_FRCE_OFF_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_FRCE_OFF_ACCESSCTRL_MSB _u(22) +#define PSM_FRCE_OFF_ACCESSCTRL_LSB _u(22) +#define PSM_FRCE_OFF_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SIO +#define PSM_FRCE_OFF_SIO_RESET _u(0x0) +#define PSM_FRCE_OFF_SIO_BITS _u(0x00200000) +#define PSM_FRCE_OFF_SIO_MSB _u(21) +#define PSM_FRCE_OFF_SIO_LSB _u(21) +#define PSM_FRCE_OFF_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XIP +#define PSM_FRCE_OFF_XIP_RESET _u(0x0) +#define PSM_FRCE_OFF_XIP_BITS _u(0x00100000) +#define PSM_FRCE_OFF_XIP_MSB _u(20) +#define PSM_FRCE_OFF_XIP_LSB _u(20) +#define PSM_FRCE_OFF_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM9 +#define PSM_FRCE_OFF_SRAM9_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM9_BITS _u(0x00080000) +#define PSM_FRCE_OFF_SRAM9_MSB _u(19) +#define PSM_FRCE_OFF_SRAM9_LSB _u(19) +#define PSM_FRCE_OFF_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM8 +#define PSM_FRCE_OFF_SRAM8_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM8_BITS _u(0x00040000) +#define PSM_FRCE_OFF_SRAM8_MSB _u(18) +#define PSM_FRCE_OFF_SRAM8_LSB _u(18) +#define PSM_FRCE_OFF_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM7 +#define PSM_FRCE_OFF_SRAM7_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM7_BITS _u(0x00020000) +#define PSM_FRCE_OFF_SRAM7_MSB _u(17) +#define PSM_FRCE_OFF_SRAM7_LSB _u(17) +#define PSM_FRCE_OFF_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM6 +#define PSM_FRCE_OFF_SRAM6_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM6_BITS _u(0x00010000) +#define PSM_FRCE_OFF_SRAM6_MSB _u(16) +#define PSM_FRCE_OFF_SRAM6_LSB _u(16) +#define PSM_FRCE_OFF_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM5 +#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00008000) +#define PSM_FRCE_OFF_SRAM5_MSB _u(15) +#define PSM_FRCE_OFF_SRAM5_LSB _u(15) +#define PSM_FRCE_OFF_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM4 +#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00004000) +#define PSM_FRCE_OFF_SRAM4_MSB _u(14) +#define PSM_FRCE_OFF_SRAM4_LSB _u(14) +#define PSM_FRCE_OFF_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM3 +#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00002000) +#define PSM_FRCE_OFF_SRAM3_MSB _u(13) +#define PSM_FRCE_OFF_SRAM3_LSB _u(13) +#define PSM_FRCE_OFF_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM2 +#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00001000) +#define PSM_FRCE_OFF_SRAM2_MSB _u(12) +#define PSM_FRCE_OFF_SRAM2_LSB _u(12) +#define PSM_FRCE_OFF_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM1 +#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000800) +#define PSM_FRCE_OFF_SRAM1_MSB _u(11) +#define PSM_FRCE_OFF_SRAM1_LSB _u(11) +#define PSM_FRCE_OFF_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM0 +#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000400) +#define PSM_FRCE_OFF_SRAM0_MSB _u(10) +#define PSM_FRCE_OFF_SRAM0_LSB _u(10) +#define PSM_FRCE_OFF_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_BOOTRAM +#define PSM_FRCE_OFF_BOOTRAM_RESET _u(0x0) +#define PSM_FRCE_OFF_BOOTRAM_BITS _u(0x00000200) +#define PSM_FRCE_OFF_BOOTRAM_MSB _u(9) +#define PSM_FRCE_OFF_BOOTRAM_LSB _u(9) +#define PSM_FRCE_OFF_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROM +#define PSM_FRCE_OFF_ROM_RESET _u(0x0) +#define PSM_FRCE_OFF_ROM_BITS _u(0x00000100) +#define PSM_FRCE_OFF_ROM_MSB _u(8) +#define PSM_FRCE_OFF_ROM_LSB _u(8) +#define PSM_FRCE_OFF_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_BUSFABRIC +#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000080) +#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(7) +#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(7) +#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PSM_READY +#define PSM_FRCE_OFF_PSM_READY_RESET _u(0x0) +#define PSM_FRCE_OFF_PSM_READY_BITS _u(0x00000040) +#define PSM_FRCE_OFF_PSM_READY_MSB _u(6) +#define PSM_FRCE_OFF_PSM_READY_LSB _u(6) +#define PSM_FRCE_OFF_PSM_READY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_CLOCKS +#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000020) +#define PSM_FRCE_OFF_CLOCKS_MSB _u(5) +#define PSM_FRCE_OFF_CLOCKS_LSB _u(5) +#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_RESETS +#define PSM_FRCE_OFF_RESETS_RESET _u(0x0) +#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000010) +#define PSM_FRCE_OFF_RESETS_MSB _u(4) +#define PSM_FRCE_OFF_RESETS_LSB _u(4) +#define PSM_FRCE_OFF_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XOSC +#define PSM_FRCE_OFF_XOSC_RESET _u(0x0) +#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000008) +#define PSM_FRCE_OFF_XOSC_MSB _u(3) +#define PSM_FRCE_OFF_XOSC_LSB _u(3) +#define PSM_FRCE_OFF_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROSC +#define PSM_FRCE_OFF_ROSC_RESET _u(0x0) +#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000004) +#define PSM_FRCE_OFF_ROSC_MSB _u(2) +#define PSM_FRCE_OFF_ROSC_LSB _u(2) +#define PSM_FRCE_OFF_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_OTP +#define PSM_FRCE_OFF_OTP_RESET _u(0x0) +#define PSM_FRCE_OFF_OTP_BITS _u(0x00000002) +#define PSM_FRCE_OFF_OTP_MSB _u(1) +#define PSM_FRCE_OFF_OTP_LSB _u(1) +#define PSM_FRCE_OFF_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC_COLD +#define PSM_FRCE_OFF_PROC_COLD_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC_COLD_BITS _u(0x00000001) +#define PSM_FRCE_OFF_PROC_COLD_MSB _u(0) +#define PSM_FRCE_OFF_PROC_COLD_LSB _u(0) +#define PSM_FRCE_OFF_PROC_COLD_ACCESS "RW" +// ============================================================================= +// Register : PSM_WDSEL +// Description : Set to 1 if the watchdog should reset this +#define PSM_WDSEL_OFFSET _u(0x00000008) +#define PSM_WDSEL_BITS _u(0x01ffffff) +#define PSM_WDSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC1 +#define PSM_WDSEL_PROC1_RESET _u(0x0) +#define PSM_WDSEL_PROC1_BITS _u(0x01000000) +#define PSM_WDSEL_PROC1_MSB _u(24) +#define PSM_WDSEL_PROC1_LSB _u(24) +#define PSM_WDSEL_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC0 +#define PSM_WDSEL_PROC0_RESET _u(0x0) +#define PSM_WDSEL_PROC0_BITS _u(0x00800000) +#define PSM_WDSEL_PROC0_MSB _u(23) +#define PSM_WDSEL_PROC0_LSB _u(23) +#define PSM_WDSEL_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ACCESSCTRL +#define PSM_WDSEL_ACCESSCTRL_RESET _u(0x0) +#define PSM_WDSEL_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_WDSEL_ACCESSCTRL_MSB _u(22) +#define PSM_WDSEL_ACCESSCTRL_LSB _u(22) +#define PSM_WDSEL_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SIO +#define PSM_WDSEL_SIO_RESET _u(0x0) +#define PSM_WDSEL_SIO_BITS _u(0x00200000) +#define PSM_WDSEL_SIO_MSB _u(21) +#define PSM_WDSEL_SIO_LSB _u(21) +#define PSM_WDSEL_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XIP +#define PSM_WDSEL_XIP_RESET _u(0x0) +#define PSM_WDSEL_XIP_BITS _u(0x00100000) +#define PSM_WDSEL_XIP_MSB _u(20) +#define PSM_WDSEL_XIP_LSB _u(20) +#define PSM_WDSEL_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM9 +#define PSM_WDSEL_SRAM9_RESET _u(0x0) +#define PSM_WDSEL_SRAM9_BITS _u(0x00080000) +#define PSM_WDSEL_SRAM9_MSB _u(19) +#define PSM_WDSEL_SRAM9_LSB _u(19) +#define PSM_WDSEL_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM8 +#define PSM_WDSEL_SRAM8_RESET _u(0x0) +#define PSM_WDSEL_SRAM8_BITS _u(0x00040000) +#define PSM_WDSEL_SRAM8_MSB _u(18) +#define PSM_WDSEL_SRAM8_LSB _u(18) +#define PSM_WDSEL_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM7 +#define PSM_WDSEL_SRAM7_RESET _u(0x0) +#define PSM_WDSEL_SRAM7_BITS _u(0x00020000) +#define PSM_WDSEL_SRAM7_MSB _u(17) +#define PSM_WDSEL_SRAM7_LSB _u(17) +#define PSM_WDSEL_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM6 +#define PSM_WDSEL_SRAM6_RESET _u(0x0) +#define PSM_WDSEL_SRAM6_BITS _u(0x00010000) +#define PSM_WDSEL_SRAM6_MSB _u(16) +#define PSM_WDSEL_SRAM6_LSB _u(16) +#define PSM_WDSEL_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM5 +#define PSM_WDSEL_SRAM5_RESET _u(0x0) +#define PSM_WDSEL_SRAM5_BITS _u(0x00008000) +#define PSM_WDSEL_SRAM5_MSB _u(15) +#define PSM_WDSEL_SRAM5_LSB _u(15) +#define PSM_WDSEL_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM4 +#define PSM_WDSEL_SRAM4_RESET _u(0x0) +#define PSM_WDSEL_SRAM4_BITS _u(0x00004000) +#define PSM_WDSEL_SRAM4_MSB _u(14) +#define PSM_WDSEL_SRAM4_LSB _u(14) +#define PSM_WDSEL_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM3 +#define PSM_WDSEL_SRAM3_RESET _u(0x0) +#define PSM_WDSEL_SRAM3_BITS _u(0x00002000) +#define PSM_WDSEL_SRAM3_MSB _u(13) +#define PSM_WDSEL_SRAM3_LSB _u(13) +#define PSM_WDSEL_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM2 +#define PSM_WDSEL_SRAM2_RESET _u(0x0) +#define PSM_WDSEL_SRAM2_BITS _u(0x00001000) +#define PSM_WDSEL_SRAM2_MSB _u(12) +#define PSM_WDSEL_SRAM2_LSB _u(12) +#define PSM_WDSEL_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM1 +#define PSM_WDSEL_SRAM1_RESET _u(0x0) +#define PSM_WDSEL_SRAM1_BITS _u(0x00000800) +#define PSM_WDSEL_SRAM1_MSB _u(11) +#define PSM_WDSEL_SRAM1_LSB _u(11) +#define PSM_WDSEL_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM0 +#define PSM_WDSEL_SRAM0_RESET _u(0x0) +#define PSM_WDSEL_SRAM0_BITS _u(0x00000400) +#define PSM_WDSEL_SRAM0_MSB _u(10) +#define PSM_WDSEL_SRAM0_LSB _u(10) +#define PSM_WDSEL_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_BOOTRAM +#define PSM_WDSEL_BOOTRAM_RESET _u(0x0) +#define PSM_WDSEL_BOOTRAM_BITS _u(0x00000200) +#define PSM_WDSEL_BOOTRAM_MSB _u(9) +#define PSM_WDSEL_BOOTRAM_LSB _u(9) +#define PSM_WDSEL_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROM +#define PSM_WDSEL_ROM_RESET _u(0x0) +#define PSM_WDSEL_ROM_BITS _u(0x00000100) +#define PSM_WDSEL_ROM_MSB _u(8) +#define PSM_WDSEL_ROM_LSB _u(8) +#define PSM_WDSEL_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_BUSFABRIC +#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) +#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000080) +#define PSM_WDSEL_BUSFABRIC_MSB _u(7) +#define PSM_WDSEL_BUSFABRIC_LSB _u(7) +#define PSM_WDSEL_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PSM_READY +#define PSM_WDSEL_PSM_READY_RESET _u(0x0) +#define PSM_WDSEL_PSM_READY_BITS _u(0x00000040) +#define PSM_WDSEL_PSM_READY_MSB _u(6) +#define PSM_WDSEL_PSM_READY_LSB _u(6) +#define PSM_WDSEL_PSM_READY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_CLOCKS +#define PSM_WDSEL_CLOCKS_RESET _u(0x0) +#define PSM_WDSEL_CLOCKS_BITS _u(0x00000020) +#define PSM_WDSEL_CLOCKS_MSB _u(5) +#define PSM_WDSEL_CLOCKS_LSB _u(5) +#define PSM_WDSEL_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_RESETS +#define PSM_WDSEL_RESETS_RESET _u(0x0) +#define PSM_WDSEL_RESETS_BITS _u(0x00000010) +#define PSM_WDSEL_RESETS_MSB _u(4) +#define PSM_WDSEL_RESETS_LSB _u(4) +#define PSM_WDSEL_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XOSC +#define PSM_WDSEL_XOSC_RESET _u(0x0) +#define PSM_WDSEL_XOSC_BITS _u(0x00000008) +#define PSM_WDSEL_XOSC_MSB _u(3) +#define PSM_WDSEL_XOSC_LSB _u(3) +#define PSM_WDSEL_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROSC +#define PSM_WDSEL_ROSC_RESET _u(0x0) +#define PSM_WDSEL_ROSC_BITS _u(0x00000004) +#define PSM_WDSEL_ROSC_MSB _u(2) +#define PSM_WDSEL_ROSC_LSB _u(2) +#define PSM_WDSEL_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_OTP +#define PSM_WDSEL_OTP_RESET _u(0x0) +#define PSM_WDSEL_OTP_BITS _u(0x00000002) +#define PSM_WDSEL_OTP_MSB _u(1) +#define PSM_WDSEL_OTP_LSB _u(1) +#define PSM_WDSEL_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC_COLD +#define PSM_WDSEL_PROC_COLD_RESET _u(0x0) +#define PSM_WDSEL_PROC_COLD_BITS _u(0x00000001) +#define PSM_WDSEL_PROC_COLD_MSB _u(0) +#define PSM_WDSEL_PROC_COLD_LSB _u(0) +#define PSM_WDSEL_PROC_COLD_ACCESS "RW" +// ============================================================================= +// Register : PSM_DONE +// Description : Is the subsystem ready? +#define PSM_DONE_OFFSET _u(0x0000000c) +#define PSM_DONE_BITS _u(0x01ffffff) +#define PSM_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC1 +#define PSM_DONE_PROC1_RESET _u(0x0) +#define PSM_DONE_PROC1_BITS _u(0x01000000) +#define PSM_DONE_PROC1_MSB _u(24) +#define PSM_DONE_PROC1_LSB _u(24) +#define PSM_DONE_PROC1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC0 +#define PSM_DONE_PROC0_RESET _u(0x0) +#define PSM_DONE_PROC0_BITS _u(0x00800000) +#define PSM_DONE_PROC0_MSB _u(23) +#define PSM_DONE_PROC0_LSB _u(23) +#define PSM_DONE_PROC0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ACCESSCTRL +#define PSM_DONE_ACCESSCTRL_RESET _u(0x0) +#define PSM_DONE_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_DONE_ACCESSCTRL_MSB _u(22) +#define PSM_DONE_ACCESSCTRL_LSB _u(22) +#define PSM_DONE_ACCESSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SIO +#define PSM_DONE_SIO_RESET _u(0x0) +#define PSM_DONE_SIO_BITS _u(0x00200000) +#define PSM_DONE_SIO_MSB _u(21) +#define PSM_DONE_SIO_LSB _u(21) +#define PSM_DONE_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XIP +#define PSM_DONE_XIP_RESET _u(0x0) +#define PSM_DONE_XIP_BITS _u(0x00100000) +#define PSM_DONE_XIP_MSB _u(20) +#define PSM_DONE_XIP_LSB _u(20) +#define PSM_DONE_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM9 +#define PSM_DONE_SRAM9_RESET _u(0x0) +#define PSM_DONE_SRAM9_BITS _u(0x00080000) +#define PSM_DONE_SRAM9_MSB _u(19) +#define PSM_DONE_SRAM9_LSB _u(19) +#define PSM_DONE_SRAM9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM8 +#define PSM_DONE_SRAM8_RESET _u(0x0) +#define PSM_DONE_SRAM8_BITS _u(0x00040000) +#define PSM_DONE_SRAM8_MSB _u(18) +#define PSM_DONE_SRAM8_LSB _u(18) +#define PSM_DONE_SRAM8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM7 +#define PSM_DONE_SRAM7_RESET _u(0x0) +#define PSM_DONE_SRAM7_BITS _u(0x00020000) +#define PSM_DONE_SRAM7_MSB _u(17) +#define PSM_DONE_SRAM7_LSB _u(17) +#define PSM_DONE_SRAM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM6 +#define PSM_DONE_SRAM6_RESET _u(0x0) +#define PSM_DONE_SRAM6_BITS _u(0x00010000) +#define PSM_DONE_SRAM6_MSB _u(16) +#define PSM_DONE_SRAM6_LSB _u(16) +#define PSM_DONE_SRAM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM5 +#define PSM_DONE_SRAM5_RESET _u(0x0) +#define PSM_DONE_SRAM5_BITS _u(0x00008000) +#define PSM_DONE_SRAM5_MSB _u(15) +#define PSM_DONE_SRAM5_LSB _u(15) +#define PSM_DONE_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM4 +#define PSM_DONE_SRAM4_RESET _u(0x0) +#define PSM_DONE_SRAM4_BITS _u(0x00004000) +#define PSM_DONE_SRAM4_MSB _u(14) +#define PSM_DONE_SRAM4_LSB _u(14) +#define PSM_DONE_SRAM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM3 +#define PSM_DONE_SRAM3_RESET _u(0x0) +#define PSM_DONE_SRAM3_BITS _u(0x00002000) +#define PSM_DONE_SRAM3_MSB _u(13) +#define PSM_DONE_SRAM3_LSB _u(13) +#define PSM_DONE_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM2 +#define PSM_DONE_SRAM2_RESET _u(0x0) +#define PSM_DONE_SRAM2_BITS _u(0x00001000) +#define PSM_DONE_SRAM2_MSB _u(12) +#define PSM_DONE_SRAM2_LSB _u(12) +#define PSM_DONE_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM1 +#define PSM_DONE_SRAM1_RESET _u(0x0) +#define PSM_DONE_SRAM1_BITS _u(0x00000800) +#define PSM_DONE_SRAM1_MSB _u(11) +#define PSM_DONE_SRAM1_LSB _u(11) +#define PSM_DONE_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM0 +#define PSM_DONE_SRAM0_RESET _u(0x0) +#define PSM_DONE_SRAM0_BITS _u(0x00000400) +#define PSM_DONE_SRAM0_MSB _u(10) +#define PSM_DONE_SRAM0_LSB _u(10) +#define PSM_DONE_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_BOOTRAM +#define PSM_DONE_BOOTRAM_RESET _u(0x0) +#define PSM_DONE_BOOTRAM_BITS _u(0x00000200) +#define PSM_DONE_BOOTRAM_MSB _u(9) +#define PSM_DONE_BOOTRAM_LSB _u(9) +#define PSM_DONE_BOOTRAM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROM +#define PSM_DONE_ROM_RESET _u(0x0) +#define PSM_DONE_ROM_BITS _u(0x00000100) +#define PSM_DONE_ROM_MSB _u(8) +#define PSM_DONE_ROM_LSB _u(8) +#define PSM_DONE_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_BUSFABRIC +#define PSM_DONE_BUSFABRIC_RESET _u(0x0) +#define PSM_DONE_BUSFABRIC_BITS _u(0x00000080) +#define PSM_DONE_BUSFABRIC_MSB _u(7) +#define PSM_DONE_BUSFABRIC_LSB _u(7) +#define PSM_DONE_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PSM_READY +#define PSM_DONE_PSM_READY_RESET _u(0x0) +#define PSM_DONE_PSM_READY_BITS _u(0x00000040) +#define PSM_DONE_PSM_READY_MSB _u(6) +#define PSM_DONE_PSM_READY_LSB _u(6) +#define PSM_DONE_PSM_READY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_CLOCKS +#define PSM_DONE_CLOCKS_RESET _u(0x0) +#define PSM_DONE_CLOCKS_BITS _u(0x00000020) +#define PSM_DONE_CLOCKS_MSB _u(5) +#define PSM_DONE_CLOCKS_LSB _u(5) +#define PSM_DONE_CLOCKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_RESETS +#define PSM_DONE_RESETS_RESET _u(0x0) +#define PSM_DONE_RESETS_BITS _u(0x00000010) +#define PSM_DONE_RESETS_MSB _u(4) +#define PSM_DONE_RESETS_LSB _u(4) +#define PSM_DONE_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XOSC +#define PSM_DONE_XOSC_RESET _u(0x0) +#define PSM_DONE_XOSC_BITS _u(0x00000008) +#define PSM_DONE_XOSC_MSB _u(3) +#define PSM_DONE_XOSC_LSB _u(3) +#define PSM_DONE_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROSC +#define PSM_DONE_ROSC_RESET _u(0x0) +#define PSM_DONE_ROSC_BITS _u(0x00000004) +#define PSM_DONE_ROSC_MSB _u(2) +#define PSM_DONE_ROSC_LSB _u(2) +#define PSM_DONE_ROSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_OTP +#define PSM_DONE_OTP_RESET _u(0x0) +#define PSM_DONE_OTP_BITS _u(0x00000002) +#define PSM_DONE_OTP_MSB _u(1) +#define PSM_DONE_OTP_LSB _u(1) +#define PSM_DONE_OTP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC_COLD +#define PSM_DONE_PROC_COLD_RESET _u(0x0) +#define PSM_DONE_PROC_COLD_BITS _u(0x00000001) +#define PSM_DONE_PROC_COLD_MSB _u(0) +#define PSM_DONE_PROC_COLD_LSB _u(0) +#define PSM_DONE_PROC_COLD_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PSM_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/pwm.h b/src/rp2350/hardware_regs/include/hardware/regs/pwm.h new file mode 100644 index 000000000..629ee8a65 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/pwm.h @@ -0,0 +1,2374 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PWM +// Version : 1 +// Bus type : apb +// Description : Simple PWM +// ============================================================================= +#ifndef _HARDWARE_REGS_PWM_H +#define _HARDWARE_REGS_PWM_H +// ============================================================================= +// Register : PWM_CH0_CSR +// Description : Control and status register +#define PWM_CH0_CSR_OFFSET _u(0x00000000) +#define PWM_CH0_CSR_BITS _u(0x000000ff) +#define PWM_CH0_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH0_CSR_PH_ADV_MSB _u(7) +#define PWM_CH0_CSR_PH_ADV_LSB _u(7) +#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH0_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH0_CSR_PH_RET_MSB _u(6) +#define PWM_CH0_CSR_PH_RET_LSB _u(6) +#define PWM_CH0_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH0_CSR_DIVMODE_MSB _u(5) +#define PWM_CH0_CSR_DIVMODE_LSB _u(4) +#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_B_INV +// Description : Invert output B +#define PWM_CH0_CSR_B_INV_RESET _u(0x0) +#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH0_CSR_B_INV_MSB _u(3) +#define PWM_CH0_CSR_B_INV_LSB _u(3) +#define PWM_CH0_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_A_INV +// Description : Invert output A +#define PWM_CH0_CSR_A_INV_RESET _u(0x0) +#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH0_CSR_A_INV_MSB _u(2) +#define PWM_CH0_CSR_A_INV_LSB _u(2) +#define PWM_CH0_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH0_CSR_EN_RESET _u(0x0) +#define PWM_CH0_CSR_EN_BITS _u(0x00000001) +#define PWM_CH0_CSR_EN_MSB _u(0) +#define PWM_CH0_CSR_EN_LSB _u(0) +#define PWM_CH0_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH0_DIV_OFFSET _u(0x00000004) +#define PWM_CH0_DIV_BITS _u(0x00000fff) +#define PWM_CH0_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_INT +#define PWM_CH0_DIV_INT_RESET _u(0x01) +#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH0_DIV_INT_MSB _u(11) +#define PWM_CH0_DIV_INT_LSB _u(4) +#define PWM_CH0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_FRAC +#define PWM_CH0_DIV_FRAC_RESET _u(0x0) +#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH0_DIV_FRAC_MSB _u(3) +#define PWM_CH0_DIV_FRAC_LSB _u(0) +#define PWM_CH0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CTR +// Description : Direct access to the PWM counter +#define PWM_CH0_CTR_OFFSET _u(0x00000008) +#define PWM_CH0_CTR_BITS _u(0x0000ffff) +#define PWM_CH0_CTR_RESET _u(0x00000000) +#define PWM_CH0_CTR_MSB _u(15) +#define PWM_CH0_CTR_LSB _u(0) +#define PWM_CH0_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CC +// Description : Counter compare values +#define PWM_CH0_CC_OFFSET _u(0x0000000c) +#define PWM_CH0_CC_BITS _u(0xffffffff) +#define PWM_CH0_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_B +#define PWM_CH0_CC_B_RESET _u(0x0000) +#define PWM_CH0_CC_B_BITS _u(0xffff0000) +#define PWM_CH0_CC_B_MSB _u(31) +#define PWM_CH0_CC_B_LSB _u(16) +#define PWM_CH0_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_A +#define PWM_CH0_CC_A_RESET _u(0x0000) +#define PWM_CH0_CC_A_BITS _u(0x0000ffff) +#define PWM_CH0_CC_A_MSB _u(15) +#define PWM_CH0_CC_A_LSB _u(0) +#define PWM_CH0_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_TOP +// Description : Counter wrap value +#define PWM_CH0_TOP_OFFSET _u(0x00000010) +#define PWM_CH0_TOP_BITS _u(0x0000ffff) +#define PWM_CH0_TOP_RESET _u(0x0000ffff) +#define PWM_CH0_TOP_MSB _u(15) +#define PWM_CH0_TOP_LSB _u(0) +#define PWM_CH0_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CSR +// Description : Control and status register +#define PWM_CH1_CSR_OFFSET _u(0x00000014) +#define PWM_CH1_CSR_BITS _u(0x000000ff) +#define PWM_CH1_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH1_CSR_PH_ADV_MSB _u(7) +#define PWM_CH1_CSR_PH_ADV_LSB _u(7) +#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH1_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH1_CSR_PH_RET_MSB _u(6) +#define PWM_CH1_CSR_PH_RET_LSB _u(6) +#define PWM_CH1_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH1_CSR_DIVMODE_MSB _u(5) +#define PWM_CH1_CSR_DIVMODE_LSB _u(4) +#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_B_INV +// Description : Invert output B +#define PWM_CH1_CSR_B_INV_RESET _u(0x0) +#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH1_CSR_B_INV_MSB _u(3) +#define PWM_CH1_CSR_B_INV_LSB _u(3) +#define PWM_CH1_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_A_INV +// Description : Invert output A +#define PWM_CH1_CSR_A_INV_RESET _u(0x0) +#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH1_CSR_A_INV_MSB _u(2) +#define PWM_CH1_CSR_A_INV_LSB _u(2) +#define PWM_CH1_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH1_CSR_EN_RESET _u(0x0) +#define PWM_CH1_CSR_EN_BITS _u(0x00000001) +#define PWM_CH1_CSR_EN_MSB _u(0) +#define PWM_CH1_CSR_EN_LSB _u(0) +#define PWM_CH1_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH1_DIV_OFFSET _u(0x00000018) +#define PWM_CH1_DIV_BITS _u(0x00000fff) +#define PWM_CH1_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_INT +#define PWM_CH1_DIV_INT_RESET _u(0x01) +#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH1_DIV_INT_MSB _u(11) +#define PWM_CH1_DIV_INT_LSB _u(4) +#define PWM_CH1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_FRAC +#define PWM_CH1_DIV_FRAC_RESET _u(0x0) +#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH1_DIV_FRAC_MSB _u(3) +#define PWM_CH1_DIV_FRAC_LSB _u(0) +#define PWM_CH1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CTR +// Description : Direct access to the PWM counter +#define PWM_CH1_CTR_OFFSET _u(0x0000001c) +#define PWM_CH1_CTR_BITS _u(0x0000ffff) +#define PWM_CH1_CTR_RESET _u(0x00000000) +#define PWM_CH1_CTR_MSB _u(15) +#define PWM_CH1_CTR_LSB _u(0) +#define PWM_CH1_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CC +// Description : Counter compare values +#define PWM_CH1_CC_OFFSET _u(0x00000020) +#define PWM_CH1_CC_BITS _u(0xffffffff) +#define PWM_CH1_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_B +#define PWM_CH1_CC_B_RESET _u(0x0000) +#define PWM_CH1_CC_B_BITS _u(0xffff0000) +#define PWM_CH1_CC_B_MSB _u(31) +#define PWM_CH1_CC_B_LSB _u(16) +#define PWM_CH1_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_A +#define PWM_CH1_CC_A_RESET _u(0x0000) +#define PWM_CH1_CC_A_BITS _u(0x0000ffff) +#define PWM_CH1_CC_A_MSB _u(15) +#define PWM_CH1_CC_A_LSB _u(0) +#define PWM_CH1_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_TOP +// Description : Counter wrap value +#define PWM_CH1_TOP_OFFSET _u(0x00000024) +#define PWM_CH1_TOP_BITS _u(0x0000ffff) +#define PWM_CH1_TOP_RESET _u(0x0000ffff) +#define PWM_CH1_TOP_MSB _u(15) +#define PWM_CH1_TOP_LSB _u(0) +#define PWM_CH1_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CSR +// Description : Control and status register +#define PWM_CH2_CSR_OFFSET _u(0x00000028) +#define PWM_CH2_CSR_BITS _u(0x000000ff) +#define PWM_CH2_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH2_CSR_PH_ADV_MSB _u(7) +#define PWM_CH2_CSR_PH_ADV_LSB _u(7) +#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH2_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH2_CSR_PH_RET_MSB _u(6) +#define PWM_CH2_CSR_PH_RET_LSB _u(6) +#define PWM_CH2_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH2_CSR_DIVMODE_MSB _u(5) +#define PWM_CH2_CSR_DIVMODE_LSB _u(4) +#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_B_INV +// Description : Invert output B +#define PWM_CH2_CSR_B_INV_RESET _u(0x0) +#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH2_CSR_B_INV_MSB _u(3) +#define PWM_CH2_CSR_B_INV_LSB _u(3) +#define PWM_CH2_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_A_INV +// Description : Invert output A +#define PWM_CH2_CSR_A_INV_RESET _u(0x0) +#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH2_CSR_A_INV_MSB _u(2) +#define PWM_CH2_CSR_A_INV_LSB _u(2) +#define PWM_CH2_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH2_CSR_EN_RESET _u(0x0) +#define PWM_CH2_CSR_EN_BITS _u(0x00000001) +#define PWM_CH2_CSR_EN_MSB _u(0) +#define PWM_CH2_CSR_EN_LSB _u(0) +#define PWM_CH2_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH2_DIV_OFFSET _u(0x0000002c) +#define PWM_CH2_DIV_BITS _u(0x00000fff) +#define PWM_CH2_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_INT +#define PWM_CH2_DIV_INT_RESET _u(0x01) +#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH2_DIV_INT_MSB _u(11) +#define PWM_CH2_DIV_INT_LSB _u(4) +#define PWM_CH2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_FRAC +#define PWM_CH2_DIV_FRAC_RESET _u(0x0) +#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH2_DIV_FRAC_MSB _u(3) +#define PWM_CH2_DIV_FRAC_LSB _u(0) +#define PWM_CH2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CTR +// Description : Direct access to the PWM counter +#define PWM_CH2_CTR_OFFSET _u(0x00000030) +#define PWM_CH2_CTR_BITS _u(0x0000ffff) +#define PWM_CH2_CTR_RESET _u(0x00000000) +#define PWM_CH2_CTR_MSB _u(15) +#define PWM_CH2_CTR_LSB _u(0) +#define PWM_CH2_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CC +// Description : Counter compare values +#define PWM_CH2_CC_OFFSET _u(0x00000034) +#define PWM_CH2_CC_BITS _u(0xffffffff) +#define PWM_CH2_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_B +#define PWM_CH2_CC_B_RESET _u(0x0000) +#define PWM_CH2_CC_B_BITS _u(0xffff0000) +#define PWM_CH2_CC_B_MSB _u(31) +#define PWM_CH2_CC_B_LSB _u(16) +#define PWM_CH2_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_A +#define PWM_CH2_CC_A_RESET _u(0x0000) +#define PWM_CH2_CC_A_BITS _u(0x0000ffff) +#define PWM_CH2_CC_A_MSB _u(15) +#define PWM_CH2_CC_A_LSB _u(0) +#define PWM_CH2_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_TOP +// Description : Counter wrap value +#define PWM_CH2_TOP_OFFSET _u(0x00000038) +#define PWM_CH2_TOP_BITS _u(0x0000ffff) +#define PWM_CH2_TOP_RESET _u(0x0000ffff) +#define PWM_CH2_TOP_MSB _u(15) +#define PWM_CH2_TOP_LSB _u(0) +#define PWM_CH2_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CSR +// Description : Control and status register +#define PWM_CH3_CSR_OFFSET _u(0x0000003c) +#define PWM_CH3_CSR_BITS _u(0x000000ff) +#define PWM_CH3_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH3_CSR_PH_ADV_MSB _u(7) +#define PWM_CH3_CSR_PH_ADV_LSB _u(7) +#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH3_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH3_CSR_PH_RET_MSB _u(6) +#define PWM_CH3_CSR_PH_RET_LSB _u(6) +#define PWM_CH3_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH3_CSR_DIVMODE_MSB _u(5) +#define PWM_CH3_CSR_DIVMODE_LSB _u(4) +#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_B_INV +// Description : Invert output B +#define PWM_CH3_CSR_B_INV_RESET _u(0x0) +#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH3_CSR_B_INV_MSB _u(3) +#define PWM_CH3_CSR_B_INV_LSB _u(3) +#define PWM_CH3_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_A_INV +// Description : Invert output A +#define PWM_CH3_CSR_A_INV_RESET _u(0x0) +#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH3_CSR_A_INV_MSB _u(2) +#define PWM_CH3_CSR_A_INV_LSB _u(2) +#define PWM_CH3_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH3_CSR_EN_RESET _u(0x0) +#define PWM_CH3_CSR_EN_BITS _u(0x00000001) +#define PWM_CH3_CSR_EN_MSB _u(0) +#define PWM_CH3_CSR_EN_LSB _u(0) +#define PWM_CH3_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH3_DIV_OFFSET _u(0x00000040) +#define PWM_CH3_DIV_BITS _u(0x00000fff) +#define PWM_CH3_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_INT +#define PWM_CH3_DIV_INT_RESET _u(0x01) +#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH3_DIV_INT_MSB _u(11) +#define PWM_CH3_DIV_INT_LSB _u(4) +#define PWM_CH3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_FRAC +#define PWM_CH3_DIV_FRAC_RESET _u(0x0) +#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH3_DIV_FRAC_MSB _u(3) +#define PWM_CH3_DIV_FRAC_LSB _u(0) +#define PWM_CH3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CTR +// Description : Direct access to the PWM counter +#define PWM_CH3_CTR_OFFSET _u(0x00000044) +#define PWM_CH3_CTR_BITS _u(0x0000ffff) +#define PWM_CH3_CTR_RESET _u(0x00000000) +#define PWM_CH3_CTR_MSB _u(15) +#define PWM_CH3_CTR_LSB _u(0) +#define PWM_CH3_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CC +// Description : Counter compare values +#define PWM_CH3_CC_OFFSET _u(0x00000048) +#define PWM_CH3_CC_BITS _u(0xffffffff) +#define PWM_CH3_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_B +#define PWM_CH3_CC_B_RESET _u(0x0000) +#define PWM_CH3_CC_B_BITS _u(0xffff0000) +#define PWM_CH3_CC_B_MSB _u(31) +#define PWM_CH3_CC_B_LSB _u(16) +#define PWM_CH3_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_A +#define PWM_CH3_CC_A_RESET _u(0x0000) +#define PWM_CH3_CC_A_BITS _u(0x0000ffff) +#define PWM_CH3_CC_A_MSB _u(15) +#define PWM_CH3_CC_A_LSB _u(0) +#define PWM_CH3_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_TOP +// Description : Counter wrap value +#define PWM_CH3_TOP_OFFSET _u(0x0000004c) +#define PWM_CH3_TOP_BITS _u(0x0000ffff) +#define PWM_CH3_TOP_RESET _u(0x0000ffff) +#define PWM_CH3_TOP_MSB _u(15) +#define PWM_CH3_TOP_LSB _u(0) +#define PWM_CH3_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CSR +// Description : Control and status register +#define PWM_CH4_CSR_OFFSET _u(0x00000050) +#define PWM_CH4_CSR_BITS _u(0x000000ff) +#define PWM_CH4_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH4_CSR_PH_ADV_MSB _u(7) +#define PWM_CH4_CSR_PH_ADV_LSB _u(7) +#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH4_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH4_CSR_PH_RET_MSB _u(6) +#define PWM_CH4_CSR_PH_RET_LSB _u(6) +#define PWM_CH4_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH4_CSR_DIVMODE_MSB _u(5) +#define PWM_CH4_CSR_DIVMODE_LSB _u(4) +#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_B_INV +// Description : Invert output B +#define PWM_CH4_CSR_B_INV_RESET _u(0x0) +#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH4_CSR_B_INV_MSB _u(3) +#define PWM_CH4_CSR_B_INV_LSB _u(3) +#define PWM_CH4_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_A_INV +// Description : Invert output A +#define PWM_CH4_CSR_A_INV_RESET _u(0x0) +#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH4_CSR_A_INV_MSB _u(2) +#define PWM_CH4_CSR_A_INV_LSB _u(2) +#define PWM_CH4_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH4_CSR_EN_RESET _u(0x0) +#define PWM_CH4_CSR_EN_BITS _u(0x00000001) +#define PWM_CH4_CSR_EN_MSB _u(0) +#define PWM_CH4_CSR_EN_LSB _u(0) +#define PWM_CH4_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH4_DIV_OFFSET _u(0x00000054) +#define PWM_CH4_DIV_BITS _u(0x00000fff) +#define PWM_CH4_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_INT +#define PWM_CH4_DIV_INT_RESET _u(0x01) +#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH4_DIV_INT_MSB _u(11) +#define PWM_CH4_DIV_INT_LSB _u(4) +#define PWM_CH4_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_FRAC +#define PWM_CH4_DIV_FRAC_RESET _u(0x0) +#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH4_DIV_FRAC_MSB _u(3) +#define PWM_CH4_DIV_FRAC_LSB _u(0) +#define PWM_CH4_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CTR +// Description : Direct access to the PWM counter +#define PWM_CH4_CTR_OFFSET _u(0x00000058) +#define PWM_CH4_CTR_BITS _u(0x0000ffff) +#define PWM_CH4_CTR_RESET _u(0x00000000) +#define PWM_CH4_CTR_MSB _u(15) +#define PWM_CH4_CTR_LSB _u(0) +#define PWM_CH4_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CC +// Description : Counter compare values +#define PWM_CH4_CC_OFFSET _u(0x0000005c) +#define PWM_CH4_CC_BITS _u(0xffffffff) +#define PWM_CH4_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_B +#define PWM_CH4_CC_B_RESET _u(0x0000) +#define PWM_CH4_CC_B_BITS _u(0xffff0000) +#define PWM_CH4_CC_B_MSB _u(31) +#define PWM_CH4_CC_B_LSB _u(16) +#define PWM_CH4_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_A +#define PWM_CH4_CC_A_RESET _u(0x0000) +#define PWM_CH4_CC_A_BITS _u(0x0000ffff) +#define PWM_CH4_CC_A_MSB _u(15) +#define PWM_CH4_CC_A_LSB _u(0) +#define PWM_CH4_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_TOP +// Description : Counter wrap value +#define PWM_CH4_TOP_OFFSET _u(0x00000060) +#define PWM_CH4_TOP_BITS _u(0x0000ffff) +#define PWM_CH4_TOP_RESET _u(0x0000ffff) +#define PWM_CH4_TOP_MSB _u(15) +#define PWM_CH4_TOP_LSB _u(0) +#define PWM_CH4_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CSR +// Description : Control and status register +#define PWM_CH5_CSR_OFFSET _u(0x00000064) +#define PWM_CH5_CSR_BITS _u(0x000000ff) +#define PWM_CH5_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH5_CSR_PH_ADV_MSB _u(7) +#define PWM_CH5_CSR_PH_ADV_LSB _u(7) +#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH5_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH5_CSR_PH_RET_MSB _u(6) +#define PWM_CH5_CSR_PH_RET_LSB _u(6) +#define PWM_CH5_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH5_CSR_DIVMODE_MSB _u(5) +#define PWM_CH5_CSR_DIVMODE_LSB _u(4) +#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_B_INV +// Description : Invert output B +#define PWM_CH5_CSR_B_INV_RESET _u(0x0) +#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH5_CSR_B_INV_MSB _u(3) +#define PWM_CH5_CSR_B_INV_LSB _u(3) +#define PWM_CH5_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_A_INV +// Description : Invert output A +#define PWM_CH5_CSR_A_INV_RESET _u(0x0) +#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH5_CSR_A_INV_MSB _u(2) +#define PWM_CH5_CSR_A_INV_LSB _u(2) +#define PWM_CH5_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH5_CSR_EN_RESET _u(0x0) +#define PWM_CH5_CSR_EN_BITS _u(0x00000001) +#define PWM_CH5_CSR_EN_MSB _u(0) +#define PWM_CH5_CSR_EN_LSB _u(0) +#define PWM_CH5_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH5_DIV_OFFSET _u(0x00000068) +#define PWM_CH5_DIV_BITS _u(0x00000fff) +#define PWM_CH5_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_INT +#define PWM_CH5_DIV_INT_RESET _u(0x01) +#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH5_DIV_INT_MSB _u(11) +#define PWM_CH5_DIV_INT_LSB _u(4) +#define PWM_CH5_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_FRAC +#define PWM_CH5_DIV_FRAC_RESET _u(0x0) +#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH5_DIV_FRAC_MSB _u(3) +#define PWM_CH5_DIV_FRAC_LSB _u(0) +#define PWM_CH5_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CTR +// Description : Direct access to the PWM counter +#define PWM_CH5_CTR_OFFSET _u(0x0000006c) +#define PWM_CH5_CTR_BITS _u(0x0000ffff) +#define PWM_CH5_CTR_RESET _u(0x00000000) +#define PWM_CH5_CTR_MSB _u(15) +#define PWM_CH5_CTR_LSB _u(0) +#define PWM_CH5_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CC +// Description : Counter compare values +#define PWM_CH5_CC_OFFSET _u(0x00000070) +#define PWM_CH5_CC_BITS _u(0xffffffff) +#define PWM_CH5_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_B +#define PWM_CH5_CC_B_RESET _u(0x0000) +#define PWM_CH5_CC_B_BITS _u(0xffff0000) +#define PWM_CH5_CC_B_MSB _u(31) +#define PWM_CH5_CC_B_LSB _u(16) +#define PWM_CH5_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_A +#define PWM_CH5_CC_A_RESET _u(0x0000) +#define PWM_CH5_CC_A_BITS _u(0x0000ffff) +#define PWM_CH5_CC_A_MSB _u(15) +#define PWM_CH5_CC_A_LSB _u(0) +#define PWM_CH5_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_TOP +// Description : Counter wrap value +#define PWM_CH5_TOP_OFFSET _u(0x00000074) +#define PWM_CH5_TOP_BITS _u(0x0000ffff) +#define PWM_CH5_TOP_RESET _u(0x0000ffff) +#define PWM_CH5_TOP_MSB _u(15) +#define PWM_CH5_TOP_LSB _u(0) +#define PWM_CH5_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CSR +// Description : Control and status register +#define PWM_CH6_CSR_OFFSET _u(0x00000078) +#define PWM_CH6_CSR_BITS _u(0x000000ff) +#define PWM_CH6_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH6_CSR_PH_ADV_MSB _u(7) +#define PWM_CH6_CSR_PH_ADV_LSB _u(7) +#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH6_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH6_CSR_PH_RET_MSB _u(6) +#define PWM_CH6_CSR_PH_RET_LSB _u(6) +#define PWM_CH6_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH6_CSR_DIVMODE_MSB _u(5) +#define PWM_CH6_CSR_DIVMODE_LSB _u(4) +#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_B_INV +// Description : Invert output B +#define PWM_CH6_CSR_B_INV_RESET _u(0x0) +#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH6_CSR_B_INV_MSB _u(3) +#define PWM_CH6_CSR_B_INV_LSB _u(3) +#define PWM_CH6_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_A_INV +// Description : Invert output A +#define PWM_CH6_CSR_A_INV_RESET _u(0x0) +#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH6_CSR_A_INV_MSB _u(2) +#define PWM_CH6_CSR_A_INV_LSB _u(2) +#define PWM_CH6_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH6_CSR_EN_RESET _u(0x0) +#define PWM_CH6_CSR_EN_BITS _u(0x00000001) +#define PWM_CH6_CSR_EN_MSB _u(0) +#define PWM_CH6_CSR_EN_LSB _u(0) +#define PWM_CH6_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH6_DIV_OFFSET _u(0x0000007c) +#define PWM_CH6_DIV_BITS _u(0x00000fff) +#define PWM_CH6_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_INT +#define PWM_CH6_DIV_INT_RESET _u(0x01) +#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH6_DIV_INT_MSB _u(11) +#define PWM_CH6_DIV_INT_LSB _u(4) +#define PWM_CH6_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_FRAC +#define PWM_CH6_DIV_FRAC_RESET _u(0x0) +#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH6_DIV_FRAC_MSB _u(3) +#define PWM_CH6_DIV_FRAC_LSB _u(0) +#define PWM_CH6_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CTR +// Description : Direct access to the PWM counter +#define PWM_CH6_CTR_OFFSET _u(0x00000080) +#define PWM_CH6_CTR_BITS _u(0x0000ffff) +#define PWM_CH6_CTR_RESET _u(0x00000000) +#define PWM_CH6_CTR_MSB _u(15) +#define PWM_CH6_CTR_LSB _u(0) +#define PWM_CH6_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CC +// Description : Counter compare values +#define PWM_CH6_CC_OFFSET _u(0x00000084) +#define PWM_CH6_CC_BITS _u(0xffffffff) +#define PWM_CH6_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_B +#define PWM_CH6_CC_B_RESET _u(0x0000) +#define PWM_CH6_CC_B_BITS _u(0xffff0000) +#define PWM_CH6_CC_B_MSB _u(31) +#define PWM_CH6_CC_B_LSB _u(16) +#define PWM_CH6_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_A +#define PWM_CH6_CC_A_RESET _u(0x0000) +#define PWM_CH6_CC_A_BITS _u(0x0000ffff) +#define PWM_CH6_CC_A_MSB _u(15) +#define PWM_CH6_CC_A_LSB _u(0) +#define PWM_CH6_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_TOP +// Description : Counter wrap value +#define PWM_CH6_TOP_OFFSET _u(0x00000088) +#define PWM_CH6_TOP_BITS _u(0x0000ffff) +#define PWM_CH6_TOP_RESET _u(0x0000ffff) +#define PWM_CH6_TOP_MSB _u(15) +#define PWM_CH6_TOP_LSB _u(0) +#define PWM_CH6_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CSR +// Description : Control and status register +#define PWM_CH7_CSR_OFFSET _u(0x0000008c) +#define PWM_CH7_CSR_BITS _u(0x000000ff) +#define PWM_CH7_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH7_CSR_PH_ADV_MSB _u(7) +#define PWM_CH7_CSR_PH_ADV_LSB _u(7) +#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH7_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH7_CSR_PH_RET_MSB _u(6) +#define PWM_CH7_CSR_PH_RET_LSB _u(6) +#define PWM_CH7_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH7_CSR_DIVMODE_MSB _u(5) +#define PWM_CH7_CSR_DIVMODE_LSB _u(4) +#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_B_INV +// Description : Invert output B +#define PWM_CH7_CSR_B_INV_RESET _u(0x0) +#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH7_CSR_B_INV_MSB _u(3) +#define PWM_CH7_CSR_B_INV_LSB _u(3) +#define PWM_CH7_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_A_INV +// Description : Invert output A +#define PWM_CH7_CSR_A_INV_RESET _u(0x0) +#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH7_CSR_A_INV_MSB _u(2) +#define PWM_CH7_CSR_A_INV_LSB _u(2) +#define PWM_CH7_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH7_CSR_EN_RESET _u(0x0) +#define PWM_CH7_CSR_EN_BITS _u(0x00000001) +#define PWM_CH7_CSR_EN_MSB _u(0) +#define PWM_CH7_CSR_EN_LSB _u(0) +#define PWM_CH7_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH7_DIV_OFFSET _u(0x00000090) +#define PWM_CH7_DIV_BITS _u(0x00000fff) +#define PWM_CH7_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_INT +#define PWM_CH7_DIV_INT_RESET _u(0x01) +#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH7_DIV_INT_MSB _u(11) +#define PWM_CH7_DIV_INT_LSB _u(4) +#define PWM_CH7_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_FRAC +#define PWM_CH7_DIV_FRAC_RESET _u(0x0) +#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH7_DIV_FRAC_MSB _u(3) +#define PWM_CH7_DIV_FRAC_LSB _u(0) +#define PWM_CH7_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CTR +// Description : Direct access to the PWM counter +#define PWM_CH7_CTR_OFFSET _u(0x00000094) +#define PWM_CH7_CTR_BITS _u(0x0000ffff) +#define PWM_CH7_CTR_RESET _u(0x00000000) +#define PWM_CH7_CTR_MSB _u(15) +#define PWM_CH7_CTR_LSB _u(0) +#define PWM_CH7_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CC +// Description : Counter compare values +#define PWM_CH7_CC_OFFSET _u(0x00000098) +#define PWM_CH7_CC_BITS _u(0xffffffff) +#define PWM_CH7_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_B +#define PWM_CH7_CC_B_RESET _u(0x0000) +#define PWM_CH7_CC_B_BITS _u(0xffff0000) +#define PWM_CH7_CC_B_MSB _u(31) +#define PWM_CH7_CC_B_LSB _u(16) +#define PWM_CH7_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_A +#define PWM_CH7_CC_A_RESET _u(0x0000) +#define PWM_CH7_CC_A_BITS _u(0x0000ffff) +#define PWM_CH7_CC_A_MSB _u(15) +#define PWM_CH7_CC_A_LSB _u(0) +#define PWM_CH7_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_TOP +// Description : Counter wrap value +#define PWM_CH7_TOP_OFFSET _u(0x0000009c) +#define PWM_CH7_TOP_BITS _u(0x0000ffff) +#define PWM_CH7_TOP_RESET _u(0x0000ffff) +#define PWM_CH7_TOP_MSB _u(15) +#define PWM_CH7_TOP_LSB _u(0) +#define PWM_CH7_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_CSR +// Description : Control and status register +#define PWM_CH8_CSR_OFFSET _u(0x000000a0) +#define PWM_CH8_CSR_BITS _u(0x000000ff) +#define PWM_CH8_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH8_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH8_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH8_CSR_PH_ADV_MSB _u(7) +#define PWM_CH8_CSR_PH_ADV_LSB _u(7) +#define PWM_CH8_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH8_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH8_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH8_CSR_PH_RET_MSB _u(6) +#define PWM_CH8_CSR_PH_RET_LSB _u(6) +#define PWM_CH8_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH8_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH8_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH8_CSR_DIVMODE_MSB _u(5) +#define PWM_CH8_CSR_DIVMODE_LSB _u(4) +#define PWM_CH8_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH8_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH8_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH8_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH8_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_B_INV +// Description : Invert output B +#define PWM_CH8_CSR_B_INV_RESET _u(0x0) +#define PWM_CH8_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH8_CSR_B_INV_MSB _u(3) +#define PWM_CH8_CSR_B_INV_LSB _u(3) +#define PWM_CH8_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_A_INV +// Description : Invert output A +#define PWM_CH8_CSR_A_INV_RESET _u(0x0) +#define PWM_CH8_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH8_CSR_A_INV_MSB _u(2) +#define PWM_CH8_CSR_A_INV_LSB _u(2) +#define PWM_CH8_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH8_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH8_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH8_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH8_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH8_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH8_CSR_EN_RESET _u(0x0) +#define PWM_CH8_CSR_EN_BITS _u(0x00000001) +#define PWM_CH8_CSR_EN_MSB _u(0) +#define PWM_CH8_CSR_EN_LSB _u(0) +#define PWM_CH8_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH8_DIV_OFFSET _u(0x000000a4) +#define PWM_CH8_DIV_BITS _u(0x00000fff) +#define PWM_CH8_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_DIV_INT +#define PWM_CH8_DIV_INT_RESET _u(0x01) +#define PWM_CH8_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH8_DIV_INT_MSB _u(11) +#define PWM_CH8_DIV_INT_LSB _u(4) +#define PWM_CH8_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_DIV_FRAC +#define PWM_CH8_DIV_FRAC_RESET _u(0x0) +#define PWM_CH8_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH8_DIV_FRAC_MSB _u(3) +#define PWM_CH8_DIV_FRAC_LSB _u(0) +#define PWM_CH8_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_CTR +// Description : Direct access to the PWM counter +#define PWM_CH8_CTR_OFFSET _u(0x000000a8) +#define PWM_CH8_CTR_BITS _u(0x0000ffff) +#define PWM_CH8_CTR_RESET _u(0x00000000) +#define PWM_CH8_CTR_MSB _u(15) +#define PWM_CH8_CTR_LSB _u(0) +#define PWM_CH8_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_CC +// Description : Counter compare values +#define PWM_CH8_CC_OFFSET _u(0x000000ac) +#define PWM_CH8_CC_BITS _u(0xffffffff) +#define PWM_CH8_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CC_B +#define PWM_CH8_CC_B_RESET _u(0x0000) +#define PWM_CH8_CC_B_BITS _u(0xffff0000) +#define PWM_CH8_CC_B_MSB _u(31) +#define PWM_CH8_CC_B_LSB _u(16) +#define PWM_CH8_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CC_A +#define PWM_CH8_CC_A_RESET _u(0x0000) +#define PWM_CH8_CC_A_BITS _u(0x0000ffff) +#define PWM_CH8_CC_A_MSB _u(15) +#define PWM_CH8_CC_A_LSB _u(0) +#define PWM_CH8_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_TOP +// Description : Counter wrap value +#define PWM_CH8_TOP_OFFSET _u(0x000000b0) +#define PWM_CH8_TOP_BITS _u(0x0000ffff) +#define PWM_CH8_TOP_RESET _u(0x0000ffff) +#define PWM_CH8_TOP_MSB _u(15) +#define PWM_CH8_TOP_LSB _u(0) +#define PWM_CH8_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_CSR +// Description : Control and status register +#define PWM_CH9_CSR_OFFSET _u(0x000000b4) +#define PWM_CH9_CSR_BITS _u(0x000000ff) +#define PWM_CH9_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH9_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH9_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH9_CSR_PH_ADV_MSB _u(7) +#define PWM_CH9_CSR_PH_ADV_LSB _u(7) +#define PWM_CH9_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH9_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH9_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH9_CSR_PH_RET_MSB _u(6) +#define PWM_CH9_CSR_PH_RET_LSB _u(6) +#define PWM_CH9_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH9_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH9_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH9_CSR_DIVMODE_MSB _u(5) +#define PWM_CH9_CSR_DIVMODE_LSB _u(4) +#define PWM_CH9_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH9_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH9_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH9_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH9_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_B_INV +// Description : Invert output B +#define PWM_CH9_CSR_B_INV_RESET _u(0x0) +#define PWM_CH9_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH9_CSR_B_INV_MSB _u(3) +#define PWM_CH9_CSR_B_INV_LSB _u(3) +#define PWM_CH9_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_A_INV +// Description : Invert output A +#define PWM_CH9_CSR_A_INV_RESET _u(0x0) +#define PWM_CH9_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH9_CSR_A_INV_MSB _u(2) +#define PWM_CH9_CSR_A_INV_LSB _u(2) +#define PWM_CH9_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH9_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH9_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH9_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH9_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH9_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH9_CSR_EN_RESET _u(0x0) +#define PWM_CH9_CSR_EN_BITS _u(0x00000001) +#define PWM_CH9_CSR_EN_MSB _u(0) +#define PWM_CH9_CSR_EN_LSB _u(0) +#define PWM_CH9_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH9_DIV_OFFSET _u(0x000000b8) +#define PWM_CH9_DIV_BITS _u(0x00000fff) +#define PWM_CH9_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_DIV_INT +#define PWM_CH9_DIV_INT_RESET _u(0x01) +#define PWM_CH9_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH9_DIV_INT_MSB _u(11) +#define PWM_CH9_DIV_INT_LSB _u(4) +#define PWM_CH9_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_DIV_FRAC +#define PWM_CH9_DIV_FRAC_RESET _u(0x0) +#define PWM_CH9_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH9_DIV_FRAC_MSB _u(3) +#define PWM_CH9_DIV_FRAC_LSB _u(0) +#define PWM_CH9_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_CTR +// Description : Direct access to the PWM counter +#define PWM_CH9_CTR_OFFSET _u(0x000000bc) +#define PWM_CH9_CTR_BITS _u(0x0000ffff) +#define PWM_CH9_CTR_RESET _u(0x00000000) +#define PWM_CH9_CTR_MSB _u(15) +#define PWM_CH9_CTR_LSB _u(0) +#define PWM_CH9_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_CC +// Description : Counter compare values +#define PWM_CH9_CC_OFFSET _u(0x000000c0) +#define PWM_CH9_CC_BITS _u(0xffffffff) +#define PWM_CH9_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CC_B +#define PWM_CH9_CC_B_RESET _u(0x0000) +#define PWM_CH9_CC_B_BITS _u(0xffff0000) +#define PWM_CH9_CC_B_MSB _u(31) +#define PWM_CH9_CC_B_LSB _u(16) +#define PWM_CH9_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CC_A +#define PWM_CH9_CC_A_RESET _u(0x0000) +#define PWM_CH9_CC_A_BITS _u(0x0000ffff) +#define PWM_CH9_CC_A_MSB _u(15) +#define PWM_CH9_CC_A_LSB _u(0) +#define PWM_CH9_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_TOP +// Description : Counter wrap value +#define PWM_CH9_TOP_OFFSET _u(0x000000c4) +#define PWM_CH9_TOP_BITS _u(0x0000ffff) +#define PWM_CH9_TOP_RESET _u(0x0000ffff) +#define PWM_CH9_TOP_MSB _u(15) +#define PWM_CH9_TOP_LSB _u(0) +#define PWM_CH9_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_CSR +// Description : Control and status register +#define PWM_CH10_CSR_OFFSET _u(0x000000c8) +#define PWM_CH10_CSR_BITS _u(0x000000ff) +#define PWM_CH10_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH10_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH10_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH10_CSR_PH_ADV_MSB _u(7) +#define PWM_CH10_CSR_PH_ADV_LSB _u(7) +#define PWM_CH10_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH10_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH10_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH10_CSR_PH_RET_MSB _u(6) +#define PWM_CH10_CSR_PH_RET_LSB _u(6) +#define PWM_CH10_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH10_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH10_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH10_CSR_DIVMODE_MSB _u(5) +#define PWM_CH10_CSR_DIVMODE_LSB _u(4) +#define PWM_CH10_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH10_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH10_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH10_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH10_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_B_INV +// Description : Invert output B +#define PWM_CH10_CSR_B_INV_RESET _u(0x0) +#define PWM_CH10_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH10_CSR_B_INV_MSB _u(3) +#define PWM_CH10_CSR_B_INV_LSB _u(3) +#define PWM_CH10_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_A_INV +// Description : Invert output A +#define PWM_CH10_CSR_A_INV_RESET _u(0x0) +#define PWM_CH10_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH10_CSR_A_INV_MSB _u(2) +#define PWM_CH10_CSR_A_INV_LSB _u(2) +#define PWM_CH10_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH10_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH10_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH10_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH10_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH10_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH10_CSR_EN_RESET _u(0x0) +#define PWM_CH10_CSR_EN_BITS _u(0x00000001) +#define PWM_CH10_CSR_EN_MSB _u(0) +#define PWM_CH10_CSR_EN_LSB _u(0) +#define PWM_CH10_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH10_DIV_OFFSET _u(0x000000cc) +#define PWM_CH10_DIV_BITS _u(0x00000fff) +#define PWM_CH10_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_DIV_INT +#define PWM_CH10_DIV_INT_RESET _u(0x01) +#define PWM_CH10_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH10_DIV_INT_MSB _u(11) +#define PWM_CH10_DIV_INT_LSB _u(4) +#define PWM_CH10_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_DIV_FRAC +#define PWM_CH10_DIV_FRAC_RESET _u(0x0) +#define PWM_CH10_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH10_DIV_FRAC_MSB _u(3) +#define PWM_CH10_DIV_FRAC_LSB _u(0) +#define PWM_CH10_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_CTR +// Description : Direct access to the PWM counter +#define PWM_CH10_CTR_OFFSET _u(0x000000d0) +#define PWM_CH10_CTR_BITS _u(0x0000ffff) +#define PWM_CH10_CTR_RESET _u(0x00000000) +#define PWM_CH10_CTR_MSB _u(15) +#define PWM_CH10_CTR_LSB _u(0) +#define PWM_CH10_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_CC +// Description : Counter compare values +#define PWM_CH10_CC_OFFSET _u(0x000000d4) +#define PWM_CH10_CC_BITS _u(0xffffffff) +#define PWM_CH10_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CC_B +#define PWM_CH10_CC_B_RESET _u(0x0000) +#define PWM_CH10_CC_B_BITS _u(0xffff0000) +#define PWM_CH10_CC_B_MSB _u(31) +#define PWM_CH10_CC_B_LSB _u(16) +#define PWM_CH10_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CC_A +#define PWM_CH10_CC_A_RESET _u(0x0000) +#define PWM_CH10_CC_A_BITS _u(0x0000ffff) +#define PWM_CH10_CC_A_MSB _u(15) +#define PWM_CH10_CC_A_LSB _u(0) +#define PWM_CH10_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_TOP +// Description : Counter wrap value +#define PWM_CH10_TOP_OFFSET _u(0x000000d8) +#define PWM_CH10_TOP_BITS _u(0x0000ffff) +#define PWM_CH10_TOP_RESET _u(0x0000ffff) +#define PWM_CH10_TOP_MSB _u(15) +#define PWM_CH10_TOP_LSB _u(0) +#define PWM_CH10_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_CSR +// Description : Control and status register +#define PWM_CH11_CSR_OFFSET _u(0x000000dc) +#define PWM_CH11_CSR_BITS _u(0x000000ff) +#define PWM_CH11_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH11_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH11_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH11_CSR_PH_ADV_MSB _u(7) +#define PWM_CH11_CSR_PH_ADV_LSB _u(7) +#define PWM_CH11_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH11_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH11_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH11_CSR_PH_RET_MSB _u(6) +#define PWM_CH11_CSR_PH_RET_LSB _u(6) +#define PWM_CH11_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH11_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH11_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH11_CSR_DIVMODE_MSB _u(5) +#define PWM_CH11_CSR_DIVMODE_LSB _u(4) +#define PWM_CH11_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH11_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH11_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH11_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH11_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_B_INV +// Description : Invert output B +#define PWM_CH11_CSR_B_INV_RESET _u(0x0) +#define PWM_CH11_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH11_CSR_B_INV_MSB _u(3) +#define PWM_CH11_CSR_B_INV_LSB _u(3) +#define PWM_CH11_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_A_INV +// Description : Invert output A +#define PWM_CH11_CSR_A_INV_RESET _u(0x0) +#define PWM_CH11_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH11_CSR_A_INV_MSB _u(2) +#define PWM_CH11_CSR_A_INV_LSB _u(2) +#define PWM_CH11_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH11_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH11_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH11_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH11_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH11_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH11_CSR_EN_RESET _u(0x0) +#define PWM_CH11_CSR_EN_BITS _u(0x00000001) +#define PWM_CH11_CSR_EN_MSB _u(0) +#define PWM_CH11_CSR_EN_LSB _u(0) +#define PWM_CH11_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH11_DIV_OFFSET _u(0x000000e0) +#define PWM_CH11_DIV_BITS _u(0x00000fff) +#define PWM_CH11_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_DIV_INT +#define PWM_CH11_DIV_INT_RESET _u(0x01) +#define PWM_CH11_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH11_DIV_INT_MSB _u(11) +#define PWM_CH11_DIV_INT_LSB _u(4) +#define PWM_CH11_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_DIV_FRAC +#define PWM_CH11_DIV_FRAC_RESET _u(0x0) +#define PWM_CH11_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH11_DIV_FRAC_MSB _u(3) +#define PWM_CH11_DIV_FRAC_LSB _u(0) +#define PWM_CH11_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_CTR +// Description : Direct access to the PWM counter +#define PWM_CH11_CTR_OFFSET _u(0x000000e4) +#define PWM_CH11_CTR_BITS _u(0x0000ffff) +#define PWM_CH11_CTR_RESET _u(0x00000000) +#define PWM_CH11_CTR_MSB _u(15) +#define PWM_CH11_CTR_LSB _u(0) +#define PWM_CH11_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_CC +// Description : Counter compare values +#define PWM_CH11_CC_OFFSET _u(0x000000e8) +#define PWM_CH11_CC_BITS _u(0xffffffff) +#define PWM_CH11_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CC_B +#define PWM_CH11_CC_B_RESET _u(0x0000) +#define PWM_CH11_CC_B_BITS _u(0xffff0000) +#define PWM_CH11_CC_B_MSB _u(31) +#define PWM_CH11_CC_B_LSB _u(16) +#define PWM_CH11_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CC_A +#define PWM_CH11_CC_A_RESET _u(0x0000) +#define PWM_CH11_CC_A_BITS _u(0x0000ffff) +#define PWM_CH11_CC_A_MSB _u(15) +#define PWM_CH11_CC_A_LSB _u(0) +#define PWM_CH11_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_TOP +// Description : Counter wrap value +#define PWM_CH11_TOP_OFFSET _u(0x000000ec) +#define PWM_CH11_TOP_BITS _u(0x0000ffff) +#define PWM_CH11_TOP_RESET _u(0x0000ffff) +#define PWM_CH11_TOP_MSB _u(15) +#define PWM_CH11_TOP_LSB _u(0) +#define PWM_CH11_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_EN +// Description : This register aliases the CSR_EN bits for all channels. +// Writing to this register allows multiple channels to be enabled +// or disabled simultaneously, so they can run in perfect sync. +// For each channel, there is only one physical EN register bit, +// which can be accessed through here or CHx_CSR. +#define PWM_EN_OFFSET _u(0x000000f0) +#define PWM_EN_BITS _u(0x00000fff) +#define PWM_EN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH11 +#define PWM_EN_CH11_RESET _u(0x0) +#define PWM_EN_CH11_BITS _u(0x00000800) +#define PWM_EN_CH11_MSB _u(11) +#define PWM_EN_CH11_LSB _u(11) +#define PWM_EN_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH10 +#define PWM_EN_CH10_RESET _u(0x0) +#define PWM_EN_CH10_BITS _u(0x00000400) +#define PWM_EN_CH10_MSB _u(10) +#define PWM_EN_CH10_LSB _u(10) +#define PWM_EN_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH9 +#define PWM_EN_CH9_RESET _u(0x0) +#define PWM_EN_CH9_BITS _u(0x00000200) +#define PWM_EN_CH9_MSB _u(9) +#define PWM_EN_CH9_LSB _u(9) +#define PWM_EN_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH8 +#define PWM_EN_CH8_RESET _u(0x0) +#define PWM_EN_CH8_BITS _u(0x00000100) +#define PWM_EN_CH8_MSB _u(8) +#define PWM_EN_CH8_LSB _u(8) +#define PWM_EN_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH7 +#define PWM_EN_CH7_RESET _u(0x0) +#define PWM_EN_CH7_BITS _u(0x00000080) +#define PWM_EN_CH7_MSB _u(7) +#define PWM_EN_CH7_LSB _u(7) +#define PWM_EN_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH6 +#define PWM_EN_CH6_RESET _u(0x0) +#define PWM_EN_CH6_BITS _u(0x00000040) +#define PWM_EN_CH6_MSB _u(6) +#define PWM_EN_CH6_LSB _u(6) +#define PWM_EN_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH5 +#define PWM_EN_CH5_RESET _u(0x0) +#define PWM_EN_CH5_BITS _u(0x00000020) +#define PWM_EN_CH5_MSB _u(5) +#define PWM_EN_CH5_LSB _u(5) +#define PWM_EN_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH4 +#define PWM_EN_CH4_RESET _u(0x0) +#define PWM_EN_CH4_BITS _u(0x00000010) +#define PWM_EN_CH4_MSB _u(4) +#define PWM_EN_CH4_LSB _u(4) +#define PWM_EN_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH3 +#define PWM_EN_CH3_RESET _u(0x0) +#define PWM_EN_CH3_BITS _u(0x00000008) +#define PWM_EN_CH3_MSB _u(3) +#define PWM_EN_CH3_LSB _u(3) +#define PWM_EN_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH2 +#define PWM_EN_CH2_RESET _u(0x0) +#define PWM_EN_CH2_BITS _u(0x00000004) +#define PWM_EN_CH2_MSB _u(2) +#define PWM_EN_CH2_LSB _u(2) +#define PWM_EN_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH1 +#define PWM_EN_CH1_RESET _u(0x0) +#define PWM_EN_CH1_BITS _u(0x00000002) +#define PWM_EN_CH1_MSB _u(1) +#define PWM_EN_CH1_LSB _u(1) +#define PWM_EN_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH0 +#define PWM_EN_CH0_RESET _u(0x0) +#define PWM_EN_CH0_BITS _u(0x00000001) +#define PWM_EN_CH0_MSB _u(0) +#define PWM_EN_CH0_LSB _u(0) +#define PWM_EN_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTR +// Description : Raw Interrupts +#define PWM_INTR_OFFSET _u(0x000000f4) +#define PWM_INTR_BITS _u(0x00000fff) +#define PWM_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH11 +#define PWM_INTR_CH11_RESET _u(0x0) +#define PWM_INTR_CH11_BITS _u(0x00000800) +#define PWM_INTR_CH11_MSB _u(11) +#define PWM_INTR_CH11_LSB _u(11) +#define PWM_INTR_CH11_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH10 +#define PWM_INTR_CH10_RESET _u(0x0) +#define PWM_INTR_CH10_BITS _u(0x00000400) +#define PWM_INTR_CH10_MSB _u(10) +#define PWM_INTR_CH10_LSB _u(10) +#define PWM_INTR_CH10_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH9 +#define PWM_INTR_CH9_RESET _u(0x0) +#define PWM_INTR_CH9_BITS _u(0x00000200) +#define PWM_INTR_CH9_MSB _u(9) +#define PWM_INTR_CH9_LSB _u(9) +#define PWM_INTR_CH9_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH8 +#define PWM_INTR_CH8_RESET _u(0x0) +#define PWM_INTR_CH8_BITS _u(0x00000100) +#define PWM_INTR_CH8_MSB _u(8) +#define PWM_INTR_CH8_LSB _u(8) +#define PWM_INTR_CH8_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH7 +#define PWM_INTR_CH7_RESET _u(0x0) +#define PWM_INTR_CH7_BITS _u(0x00000080) +#define PWM_INTR_CH7_MSB _u(7) +#define PWM_INTR_CH7_LSB _u(7) +#define PWM_INTR_CH7_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH6 +#define PWM_INTR_CH6_RESET _u(0x0) +#define PWM_INTR_CH6_BITS _u(0x00000040) +#define PWM_INTR_CH6_MSB _u(6) +#define PWM_INTR_CH6_LSB _u(6) +#define PWM_INTR_CH6_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH5 +#define PWM_INTR_CH5_RESET _u(0x0) +#define PWM_INTR_CH5_BITS _u(0x00000020) +#define PWM_INTR_CH5_MSB _u(5) +#define PWM_INTR_CH5_LSB _u(5) +#define PWM_INTR_CH5_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH4 +#define PWM_INTR_CH4_RESET _u(0x0) +#define PWM_INTR_CH4_BITS _u(0x00000010) +#define PWM_INTR_CH4_MSB _u(4) +#define PWM_INTR_CH4_LSB _u(4) +#define PWM_INTR_CH4_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH3 +#define PWM_INTR_CH3_RESET _u(0x0) +#define PWM_INTR_CH3_BITS _u(0x00000008) +#define PWM_INTR_CH3_MSB _u(3) +#define PWM_INTR_CH3_LSB _u(3) +#define PWM_INTR_CH3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH2 +#define PWM_INTR_CH2_RESET _u(0x0) +#define PWM_INTR_CH2_BITS _u(0x00000004) +#define PWM_INTR_CH2_MSB _u(2) +#define PWM_INTR_CH2_LSB _u(2) +#define PWM_INTR_CH2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH1 +#define PWM_INTR_CH1_RESET _u(0x0) +#define PWM_INTR_CH1_BITS _u(0x00000002) +#define PWM_INTR_CH1_MSB _u(1) +#define PWM_INTR_CH1_LSB _u(1) +#define PWM_INTR_CH1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH0 +#define PWM_INTR_CH0_RESET _u(0x0) +#define PWM_INTR_CH0_BITS _u(0x00000001) +#define PWM_INTR_CH0_MSB _u(0) +#define PWM_INTR_CH0_LSB _u(0) +#define PWM_INTR_CH0_ACCESS "WC" +// ============================================================================= +// Register : PWM_IRQ0_INTE +// Description : Interrupt Enable for irq0 +#define PWM_IRQ0_INTE_OFFSET _u(0x000000f8) +#define PWM_IRQ0_INTE_BITS _u(0x00000fff) +#define PWM_IRQ0_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH11 +#define PWM_IRQ0_INTE_CH11_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH11_BITS _u(0x00000800) +#define PWM_IRQ0_INTE_CH11_MSB _u(11) +#define PWM_IRQ0_INTE_CH11_LSB _u(11) +#define PWM_IRQ0_INTE_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH10 +#define PWM_IRQ0_INTE_CH10_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH10_BITS _u(0x00000400) +#define PWM_IRQ0_INTE_CH10_MSB _u(10) +#define PWM_IRQ0_INTE_CH10_LSB _u(10) +#define PWM_IRQ0_INTE_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH9 +#define PWM_IRQ0_INTE_CH9_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH9_BITS _u(0x00000200) +#define PWM_IRQ0_INTE_CH9_MSB _u(9) +#define PWM_IRQ0_INTE_CH9_LSB _u(9) +#define PWM_IRQ0_INTE_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH8 +#define PWM_IRQ0_INTE_CH8_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH8_BITS _u(0x00000100) +#define PWM_IRQ0_INTE_CH8_MSB _u(8) +#define PWM_IRQ0_INTE_CH8_LSB _u(8) +#define PWM_IRQ0_INTE_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH7 +#define PWM_IRQ0_INTE_CH7_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH7_BITS _u(0x00000080) +#define PWM_IRQ0_INTE_CH7_MSB _u(7) +#define PWM_IRQ0_INTE_CH7_LSB _u(7) +#define PWM_IRQ0_INTE_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH6 +#define PWM_IRQ0_INTE_CH6_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH6_BITS _u(0x00000040) +#define PWM_IRQ0_INTE_CH6_MSB _u(6) +#define PWM_IRQ0_INTE_CH6_LSB _u(6) +#define PWM_IRQ0_INTE_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH5 +#define PWM_IRQ0_INTE_CH5_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH5_BITS _u(0x00000020) +#define PWM_IRQ0_INTE_CH5_MSB _u(5) +#define PWM_IRQ0_INTE_CH5_LSB _u(5) +#define PWM_IRQ0_INTE_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH4 +#define PWM_IRQ0_INTE_CH4_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH4_BITS _u(0x00000010) +#define PWM_IRQ0_INTE_CH4_MSB _u(4) +#define PWM_IRQ0_INTE_CH4_LSB _u(4) +#define PWM_IRQ0_INTE_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH3 +#define PWM_IRQ0_INTE_CH3_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH3_BITS _u(0x00000008) +#define PWM_IRQ0_INTE_CH3_MSB _u(3) +#define PWM_IRQ0_INTE_CH3_LSB _u(3) +#define PWM_IRQ0_INTE_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH2 +#define PWM_IRQ0_INTE_CH2_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH2_BITS _u(0x00000004) +#define PWM_IRQ0_INTE_CH2_MSB _u(2) +#define PWM_IRQ0_INTE_CH2_LSB _u(2) +#define PWM_IRQ0_INTE_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH1 +#define PWM_IRQ0_INTE_CH1_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH1_BITS _u(0x00000002) +#define PWM_IRQ0_INTE_CH1_MSB _u(1) +#define PWM_IRQ0_INTE_CH1_LSB _u(1) +#define PWM_IRQ0_INTE_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH0 +#define PWM_IRQ0_INTE_CH0_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH0_BITS _u(0x00000001) +#define PWM_IRQ0_INTE_CH0_MSB _u(0) +#define PWM_IRQ0_INTE_CH0_LSB _u(0) +#define PWM_IRQ0_INTE_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ0_INTF +// Description : Interrupt Force for irq0 +#define PWM_IRQ0_INTF_OFFSET _u(0x000000fc) +#define PWM_IRQ0_INTF_BITS _u(0x00000fff) +#define PWM_IRQ0_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH11 +#define PWM_IRQ0_INTF_CH11_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH11_BITS _u(0x00000800) +#define PWM_IRQ0_INTF_CH11_MSB _u(11) +#define PWM_IRQ0_INTF_CH11_LSB _u(11) +#define PWM_IRQ0_INTF_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH10 +#define PWM_IRQ0_INTF_CH10_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH10_BITS _u(0x00000400) +#define PWM_IRQ0_INTF_CH10_MSB _u(10) +#define PWM_IRQ0_INTF_CH10_LSB _u(10) +#define PWM_IRQ0_INTF_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH9 +#define PWM_IRQ0_INTF_CH9_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH9_BITS _u(0x00000200) +#define PWM_IRQ0_INTF_CH9_MSB _u(9) +#define PWM_IRQ0_INTF_CH9_LSB _u(9) +#define PWM_IRQ0_INTF_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH8 +#define PWM_IRQ0_INTF_CH8_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH8_BITS _u(0x00000100) +#define PWM_IRQ0_INTF_CH8_MSB _u(8) +#define PWM_IRQ0_INTF_CH8_LSB _u(8) +#define PWM_IRQ0_INTF_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH7 +#define PWM_IRQ0_INTF_CH7_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH7_BITS _u(0x00000080) +#define PWM_IRQ0_INTF_CH7_MSB _u(7) +#define PWM_IRQ0_INTF_CH7_LSB _u(7) +#define PWM_IRQ0_INTF_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH6 +#define PWM_IRQ0_INTF_CH6_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH6_BITS _u(0x00000040) +#define PWM_IRQ0_INTF_CH6_MSB _u(6) +#define PWM_IRQ0_INTF_CH6_LSB _u(6) +#define PWM_IRQ0_INTF_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH5 +#define PWM_IRQ0_INTF_CH5_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH5_BITS _u(0x00000020) +#define PWM_IRQ0_INTF_CH5_MSB _u(5) +#define PWM_IRQ0_INTF_CH5_LSB _u(5) +#define PWM_IRQ0_INTF_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH4 +#define PWM_IRQ0_INTF_CH4_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH4_BITS _u(0x00000010) +#define PWM_IRQ0_INTF_CH4_MSB _u(4) +#define PWM_IRQ0_INTF_CH4_LSB _u(4) +#define PWM_IRQ0_INTF_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH3 +#define PWM_IRQ0_INTF_CH3_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH3_BITS _u(0x00000008) +#define PWM_IRQ0_INTF_CH3_MSB _u(3) +#define PWM_IRQ0_INTF_CH3_LSB _u(3) +#define PWM_IRQ0_INTF_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH2 +#define PWM_IRQ0_INTF_CH2_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH2_BITS _u(0x00000004) +#define PWM_IRQ0_INTF_CH2_MSB _u(2) +#define PWM_IRQ0_INTF_CH2_LSB _u(2) +#define PWM_IRQ0_INTF_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH1 +#define PWM_IRQ0_INTF_CH1_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH1_BITS _u(0x00000002) +#define PWM_IRQ0_INTF_CH1_MSB _u(1) +#define PWM_IRQ0_INTF_CH1_LSB _u(1) +#define PWM_IRQ0_INTF_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH0 +#define PWM_IRQ0_INTF_CH0_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH0_BITS _u(0x00000001) +#define PWM_IRQ0_INTF_CH0_MSB _u(0) +#define PWM_IRQ0_INTF_CH0_LSB _u(0) +#define PWM_IRQ0_INTF_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ0_INTS +// Description : Interrupt status after masking & forcing for irq0 +#define PWM_IRQ0_INTS_OFFSET _u(0x00000100) +#define PWM_IRQ0_INTS_BITS _u(0x00000fff) +#define PWM_IRQ0_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH11 +#define PWM_IRQ0_INTS_CH11_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH11_BITS _u(0x00000800) +#define PWM_IRQ0_INTS_CH11_MSB _u(11) +#define PWM_IRQ0_INTS_CH11_LSB _u(11) +#define PWM_IRQ0_INTS_CH11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH10 +#define PWM_IRQ0_INTS_CH10_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH10_BITS _u(0x00000400) +#define PWM_IRQ0_INTS_CH10_MSB _u(10) +#define PWM_IRQ0_INTS_CH10_LSB _u(10) +#define PWM_IRQ0_INTS_CH10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH9 +#define PWM_IRQ0_INTS_CH9_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH9_BITS _u(0x00000200) +#define PWM_IRQ0_INTS_CH9_MSB _u(9) +#define PWM_IRQ0_INTS_CH9_LSB _u(9) +#define PWM_IRQ0_INTS_CH9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH8 +#define PWM_IRQ0_INTS_CH8_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH8_BITS _u(0x00000100) +#define PWM_IRQ0_INTS_CH8_MSB _u(8) +#define PWM_IRQ0_INTS_CH8_LSB _u(8) +#define PWM_IRQ0_INTS_CH8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH7 +#define PWM_IRQ0_INTS_CH7_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH7_BITS _u(0x00000080) +#define PWM_IRQ0_INTS_CH7_MSB _u(7) +#define PWM_IRQ0_INTS_CH7_LSB _u(7) +#define PWM_IRQ0_INTS_CH7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH6 +#define PWM_IRQ0_INTS_CH6_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH6_BITS _u(0x00000040) +#define PWM_IRQ0_INTS_CH6_MSB _u(6) +#define PWM_IRQ0_INTS_CH6_LSB _u(6) +#define PWM_IRQ0_INTS_CH6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH5 +#define PWM_IRQ0_INTS_CH5_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH5_BITS _u(0x00000020) +#define PWM_IRQ0_INTS_CH5_MSB _u(5) +#define PWM_IRQ0_INTS_CH5_LSB _u(5) +#define PWM_IRQ0_INTS_CH5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH4 +#define PWM_IRQ0_INTS_CH4_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH4_BITS _u(0x00000010) +#define PWM_IRQ0_INTS_CH4_MSB _u(4) +#define PWM_IRQ0_INTS_CH4_LSB _u(4) +#define PWM_IRQ0_INTS_CH4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH3 +#define PWM_IRQ0_INTS_CH3_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH3_BITS _u(0x00000008) +#define PWM_IRQ0_INTS_CH3_MSB _u(3) +#define PWM_IRQ0_INTS_CH3_LSB _u(3) +#define PWM_IRQ0_INTS_CH3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH2 +#define PWM_IRQ0_INTS_CH2_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH2_BITS _u(0x00000004) +#define PWM_IRQ0_INTS_CH2_MSB _u(2) +#define PWM_IRQ0_INTS_CH2_LSB _u(2) +#define PWM_IRQ0_INTS_CH2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH1 +#define PWM_IRQ0_INTS_CH1_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH1_BITS _u(0x00000002) +#define PWM_IRQ0_INTS_CH1_MSB _u(1) +#define PWM_IRQ0_INTS_CH1_LSB _u(1) +#define PWM_IRQ0_INTS_CH1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH0 +#define PWM_IRQ0_INTS_CH0_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH0_BITS _u(0x00000001) +#define PWM_IRQ0_INTS_CH0_MSB _u(0) +#define PWM_IRQ0_INTS_CH0_LSB _u(0) +#define PWM_IRQ0_INTS_CH0_ACCESS "RO" +// ============================================================================= +// Register : PWM_IRQ1_INTE +// Description : Interrupt Enable for irq1 +#define PWM_IRQ1_INTE_OFFSET _u(0x00000104) +#define PWM_IRQ1_INTE_BITS _u(0x00000fff) +#define PWM_IRQ1_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH11 +#define PWM_IRQ1_INTE_CH11_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH11_BITS _u(0x00000800) +#define PWM_IRQ1_INTE_CH11_MSB _u(11) +#define PWM_IRQ1_INTE_CH11_LSB _u(11) +#define PWM_IRQ1_INTE_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH10 +#define PWM_IRQ1_INTE_CH10_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH10_BITS _u(0x00000400) +#define PWM_IRQ1_INTE_CH10_MSB _u(10) +#define PWM_IRQ1_INTE_CH10_LSB _u(10) +#define PWM_IRQ1_INTE_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH9 +#define PWM_IRQ1_INTE_CH9_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH9_BITS _u(0x00000200) +#define PWM_IRQ1_INTE_CH9_MSB _u(9) +#define PWM_IRQ1_INTE_CH9_LSB _u(9) +#define PWM_IRQ1_INTE_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH8 +#define PWM_IRQ1_INTE_CH8_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH8_BITS _u(0x00000100) +#define PWM_IRQ1_INTE_CH8_MSB _u(8) +#define PWM_IRQ1_INTE_CH8_LSB _u(8) +#define PWM_IRQ1_INTE_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH7 +#define PWM_IRQ1_INTE_CH7_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH7_BITS _u(0x00000080) +#define PWM_IRQ1_INTE_CH7_MSB _u(7) +#define PWM_IRQ1_INTE_CH7_LSB _u(7) +#define PWM_IRQ1_INTE_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH6 +#define PWM_IRQ1_INTE_CH6_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH6_BITS _u(0x00000040) +#define PWM_IRQ1_INTE_CH6_MSB _u(6) +#define PWM_IRQ1_INTE_CH6_LSB _u(6) +#define PWM_IRQ1_INTE_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH5 +#define PWM_IRQ1_INTE_CH5_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH5_BITS _u(0x00000020) +#define PWM_IRQ1_INTE_CH5_MSB _u(5) +#define PWM_IRQ1_INTE_CH5_LSB _u(5) +#define PWM_IRQ1_INTE_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH4 +#define PWM_IRQ1_INTE_CH4_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH4_BITS _u(0x00000010) +#define PWM_IRQ1_INTE_CH4_MSB _u(4) +#define PWM_IRQ1_INTE_CH4_LSB _u(4) +#define PWM_IRQ1_INTE_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH3 +#define PWM_IRQ1_INTE_CH3_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH3_BITS _u(0x00000008) +#define PWM_IRQ1_INTE_CH3_MSB _u(3) +#define PWM_IRQ1_INTE_CH3_LSB _u(3) +#define PWM_IRQ1_INTE_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH2 +#define PWM_IRQ1_INTE_CH2_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH2_BITS _u(0x00000004) +#define PWM_IRQ1_INTE_CH2_MSB _u(2) +#define PWM_IRQ1_INTE_CH2_LSB _u(2) +#define PWM_IRQ1_INTE_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH1 +#define PWM_IRQ1_INTE_CH1_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH1_BITS _u(0x00000002) +#define PWM_IRQ1_INTE_CH1_MSB _u(1) +#define PWM_IRQ1_INTE_CH1_LSB _u(1) +#define PWM_IRQ1_INTE_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH0 +#define PWM_IRQ1_INTE_CH0_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH0_BITS _u(0x00000001) +#define PWM_IRQ1_INTE_CH0_MSB _u(0) +#define PWM_IRQ1_INTE_CH0_LSB _u(0) +#define PWM_IRQ1_INTE_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ1_INTF +// Description : Interrupt Force for irq1 +#define PWM_IRQ1_INTF_OFFSET _u(0x00000108) +#define PWM_IRQ1_INTF_BITS _u(0x00000fff) +#define PWM_IRQ1_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH11 +#define PWM_IRQ1_INTF_CH11_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH11_BITS _u(0x00000800) +#define PWM_IRQ1_INTF_CH11_MSB _u(11) +#define PWM_IRQ1_INTF_CH11_LSB _u(11) +#define PWM_IRQ1_INTF_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH10 +#define PWM_IRQ1_INTF_CH10_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH10_BITS _u(0x00000400) +#define PWM_IRQ1_INTF_CH10_MSB _u(10) +#define PWM_IRQ1_INTF_CH10_LSB _u(10) +#define PWM_IRQ1_INTF_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH9 +#define PWM_IRQ1_INTF_CH9_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH9_BITS _u(0x00000200) +#define PWM_IRQ1_INTF_CH9_MSB _u(9) +#define PWM_IRQ1_INTF_CH9_LSB _u(9) +#define PWM_IRQ1_INTF_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH8 +#define PWM_IRQ1_INTF_CH8_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH8_BITS _u(0x00000100) +#define PWM_IRQ1_INTF_CH8_MSB _u(8) +#define PWM_IRQ1_INTF_CH8_LSB _u(8) +#define PWM_IRQ1_INTF_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH7 +#define PWM_IRQ1_INTF_CH7_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH7_BITS _u(0x00000080) +#define PWM_IRQ1_INTF_CH7_MSB _u(7) +#define PWM_IRQ1_INTF_CH7_LSB _u(7) +#define PWM_IRQ1_INTF_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH6 +#define PWM_IRQ1_INTF_CH6_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH6_BITS _u(0x00000040) +#define PWM_IRQ1_INTF_CH6_MSB _u(6) +#define PWM_IRQ1_INTF_CH6_LSB _u(6) +#define PWM_IRQ1_INTF_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH5 +#define PWM_IRQ1_INTF_CH5_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH5_BITS _u(0x00000020) +#define PWM_IRQ1_INTF_CH5_MSB _u(5) +#define PWM_IRQ1_INTF_CH5_LSB _u(5) +#define PWM_IRQ1_INTF_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH4 +#define PWM_IRQ1_INTF_CH4_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH4_BITS _u(0x00000010) +#define PWM_IRQ1_INTF_CH4_MSB _u(4) +#define PWM_IRQ1_INTF_CH4_LSB _u(4) +#define PWM_IRQ1_INTF_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH3 +#define PWM_IRQ1_INTF_CH3_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH3_BITS _u(0x00000008) +#define PWM_IRQ1_INTF_CH3_MSB _u(3) +#define PWM_IRQ1_INTF_CH3_LSB _u(3) +#define PWM_IRQ1_INTF_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH2 +#define PWM_IRQ1_INTF_CH2_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH2_BITS _u(0x00000004) +#define PWM_IRQ1_INTF_CH2_MSB _u(2) +#define PWM_IRQ1_INTF_CH2_LSB _u(2) +#define PWM_IRQ1_INTF_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH1 +#define PWM_IRQ1_INTF_CH1_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH1_BITS _u(0x00000002) +#define PWM_IRQ1_INTF_CH1_MSB _u(1) +#define PWM_IRQ1_INTF_CH1_LSB _u(1) +#define PWM_IRQ1_INTF_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH0 +#define PWM_IRQ1_INTF_CH0_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH0_BITS _u(0x00000001) +#define PWM_IRQ1_INTF_CH0_MSB _u(0) +#define PWM_IRQ1_INTF_CH0_LSB _u(0) +#define PWM_IRQ1_INTF_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ1_INTS +// Description : Interrupt status after masking & forcing for irq1 +#define PWM_IRQ1_INTS_OFFSET _u(0x0000010c) +#define PWM_IRQ1_INTS_BITS _u(0x00000fff) +#define PWM_IRQ1_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH11 +#define PWM_IRQ1_INTS_CH11_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH11_BITS _u(0x00000800) +#define PWM_IRQ1_INTS_CH11_MSB _u(11) +#define PWM_IRQ1_INTS_CH11_LSB _u(11) +#define PWM_IRQ1_INTS_CH11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH10 +#define PWM_IRQ1_INTS_CH10_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH10_BITS _u(0x00000400) +#define PWM_IRQ1_INTS_CH10_MSB _u(10) +#define PWM_IRQ1_INTS_CH10_LSB _u(10) +#define PWM_IRQ1_INTS_CH10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH9 +#define PWM_IRQ1_INTS_CH9_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH9_BITS _u(0x00000200) +#define PWM_IRQ1_INTS_CH9_MSB _u(9) +#define PWM_IRQ1_INTS_CH9_LSB _u(9) +#define PWM_IRQ1_INTS_CH9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH8 +#define PWM_IRQ1_INTS_CH8_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH8_BITS _u(0x00000100) +#define PWM_IRQ1_INTS_CH8_MSB _u(8) +#define PWM_IRQ1_INTS_CH8_LSB _u(8) +#define PWM_IRQ1_INTS_CH8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH7 +#define PWM_IRQ1_INTS_CH7_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH7_BITS _u(0x00000080) +#define PWM_IRQ1_INTS_CH7_MSB _u(7) +#define PWM_IRQ1_INTS_CH7_LSB _u(7) +#define PWM_IRQ1_INTS_CH7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH6 +#define PWM_IRQ1_INTS_CH6_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH6_BITS _u(0x00000040) +#define PWM_IRQ1_INTS_CH6_MSB _u(6) +#define PWM_IRQ1_INTS_CH6_LSB _u(6) +#define PWM_IRQ1_INTS_CH6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH5 +#define PWM_IRQ1_INTS_CH5_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH5_BITS _u(0x00000020) +#define PWM_IRQ1_INTS_CH5_MSB _u(5) +#define PWM_IRQ1_INTS_CH5_LSB _u(5) +#define PWM_IRQ1_INTS_CH5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH4 +#define PWM_IRQ1_INTS_CH4_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH4_BITS _u(0x00000010) +#define PWM_IRQ1_INTS_CH4_MSB _u(4) +#define PWM_IRQ1_INTS_CH4_LSB _u(4) +#define PWM_IRQ1_INTS_CH4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH3 +#define PWM_IRQ1_INTS_CH3_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH3_BITS _u(0x00000008) +#define PWM_IRQ1_INTS_CH3_MSB _u(3) +#define PWM_IRQ1_INTS_CH3_LSB _u(3) +#define PWM_IRQ1_INTS_CH3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH2 +#define PWM_IRQ1_INTS_CH2_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH2_BITS _u(0x00000004) +#define PWM_IRQ1_INTS_CH2_MSB _u(2) +#define PWM_IRQ1_INTS_CH2_LSB _u(2) +#define PWM_IRQ1_INTS_CH2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH1 +#define PWM_IRQ1_INTS_CH1_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH1_BITS _u(0x00000002) +#define PWM_IRQ1_INTS_CH1_MSB _u(1) +#define PWM_IRQ1_INTS_CH1_LSB _u(1) +#define PWM_IRQ1_INTS_CH1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH0 +#define PWM_IRQ1_INTS_CH0_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH0_BITS _u(0x00000001) +#define PWM_IRQ1_INTS_CH0_MSB _u(0) +#define PWM_IRQ1_INTS_CH0_LSB _u(0) +#define PWM_IRQ1_INTS_CH0_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PWM_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/qmi.h b/src/rp2350/hardware_regs/include/hardware/regs/qmi.h new file mode 100644 index 000000000..3efebc13f --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/qmi.h @@ -0,0 +1,1781 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : QMI +// Version : 1 +// Bus type : apb +// Description : QSPI Memory Interface. +// +// Provides a memory-mapped interface to up to two +// SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial +// interface for programming and configuration of the external +// device. +// ============================================================================= +#ifndef _HARDWARE_REGS_QMI_H +#define _HARDWARE_REGS_QMI_H +// ============================================================================= +// Register : QMI_DIRECT_CSR +// Description : Control and status for direct serial mode +// +// Direct serial mode allows the processor to send and receive raw +// serial frames, for programming, configuration and control of +// the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is +// supported. +#define QMI_DIRECT_CSR_OFFSET _u(0x00000000) +#define QMI_DIRECT_CSR_BITS _u(0xffdf7ccf) +#define QMI_DIRECT_CSR_RESET _u(0x01800000) +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXDELAY +// Description : Delay the read data sample timing, in units of one half of a +// system clock cycle. (Not necessarily half of an SCK cycle.) +#define QMI_DIRECT_CSR_RXDELAY_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXDELAY_BITS _u(0xc0000000) +#define QMI_DIRECT_CSR_RXDELAY_MSB _u(31) +#define QMI_DIRECT_CSR_RXDELAY_LSB _u(30) +#define QMI_DIRECT_CSR_RXDELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_CLKDIV +// Description : Clock divisor for direct serial mode. Divisors of 1..255 are +// encoded directly, and the maximum divisor of 256 is encoded by +// a value of CLKDIV=0. +// +// The clock divisor can be changed on-the-fly by software, +// without halting or otherwise coordinating with the serial +// interface. The serial interface will sample the latest clock +// divisor each time it begins the transmission of a new byte. +#define QMI_DIRECT_CSR_CLKDIV_RESET _u(0x06) +#define QMI_DIRECT_CSR_CLKDIV_BITS _u(0x3fc00000) +#define QMI_DIRECT_CSR_CLKDIV_MSB _u(29) +#define QMI_DIRECT_CSR_CLKDIV_LSB _u(22) +#define QMI_DIRECT_CSR_CLKDIV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXLEVEL +// Description : Current level of DIRECT_RX FIFO +#define QMI_DIRECT_CSR_RXLEVEL_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXLEVEL_BITS _u(0x001c0000) +#define QMI_DIRECT_CSR_RXLEVEL_MSB _u(20) +#define QMI_DIRECT_CSR_RXLEVEL_LSB _u(18) +#define QMI_DIRECT_CSR_RXLEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXFULL +// Description : When 1, the DIRECT_RX FIFO is currently full. The serial +// interface will be stalled until data is popped; the interface +// will not begin a new serial frame when the DIRECT_TX FIFO is +// empty or the DIRECT_RX FIFO is full. +#define QMI_DIRECT_CSR_RXFULL_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXFULL_BITS _u(0x00020000) +#define QMI_DIRECT_CSR_RXFULL_MSB _u(17) +#define QMI_DIRECT_CSR_RXFULL_LSB _u(17) +#define QMI_DIRECT_CSR_RXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXEMPTY +// Description : When 1, the DIRECT_RX FIFO is currently empty. If the processor +// attempts to read more data, the FIFO state is not affected, but +// the value returned to the processor is undefined. +#define QMI_DIRECT_CSR_RXEMPTY_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXEMPTY_BITS _u(0x00010000) +#define QMI_DIRECT_CSR_RXEMPTY_MSB _u(16) +#define QMI_DIRECT_CSR_RXEMPTY_LSB _u(16) +#define QMI_DIRECT_CSR_RXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_TXLEVEL +// Description : Current level of DIRECT_TX FIFO +#define QMI_DIRECT_CSR_TXLEVEL_RESET _u(0x0) +#define QMI_DIRECT_CSR_TXLEVEL_BITS _u(0x00007000) +#define QMI_DIRECT_CSR_TXLEVEL_MSB _u(14) +#define QMI_DIRECT_CSR_TXLEVEL_LSB _u(12) +#define QMI_DIRECT_CSR_TXLEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_TXEMPTY +// Description : When 1, the DIRECT_TX FIFO is currently empty. Unless the +// processor pushes more data, transmission will stop and BUSY +// will go low once the current 8-bit serial frame completes. +#define QMI_DIRECT_CSR_TXEMPTY_RESET _u(0x0) +#define QMI_DIRECT_CSR_TXEMPTY_BITS _u(0x00000800) +#define QMI_DIRECT_CSR_TXEMPTY_MSB _u(11) +#define QMI_DIRECT_CSR_TXEMPTY_LSB _u(11) +#define QMI_DIRECT_CSR_TXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_TXFULL +// Description : When 1, the DIRECT_TX FIFO is currently full. If the processor +// tries to write more data, that data will be ignored. +#define QMI_DIRECT_CSR_TXFULL_RESET _u(0x0) +#define QMI_DIRECT_CSR_TXFULL_BITS _u(0x00000400) +#define QMI_DIRECT_CSR_TXFULL_MSB _u(10) +#define QMI_DIRECT_CSR_TXFULL_LSB _u(10) +#define QMI_DIRECT_CSR_TXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_AUTO_CS1N +// Description : When 1, automatically assert the CS1n chip select line whenever +// the BUSY flag is set. +#define QMI_DIRECT_CSR_AUTO_CS1N_RESET _u(0x0) +#define QMI_DIRECT_CSR_AUTO_CS1N_BITS _u(0x00000080) +#define QMI_DIRECT_CSR_AUTO_CS1N_MSB _u(7) +#define QMI_DIRECT_CSR_AUTO_CS1N_LSB _u(7) +#define QMI_DIRECT_CSR_AUTO_CS1N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_AUTO_CS0N +// Description : When 1, automatically assert the CS0n chip select line whenever +// the BUSY flag is set. +#define QMI_DIRECT_CSR_AUTO_CS0N_RESET _u(0x0) +#define QMI_DIRECT_CSR_AUTO_CS0N_BITS _u(0x00000040) +#define QMI_DIRECT_CSR_AUTO_CS0N_MSB _u(6) +#define QMI_DIRECT_CSR_AUTO_CS0N_LSB _u(6) +#define QMI_DIRECT_CSR_AUTO_CS0N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_ASSERT_CS1N +// Description : When 1, assert (i.e. drive low) the CS1n chip select line. +// +// Note that this applies even when DIRECT_CSR_EN is 0. +#define QMI_DIRECT_CSR_ASSERT_CS1N_RESET _u(0x0) +#define QMI_DIRECT_CSR_ASSERT_CS1N_BITS _u(0x00000008) +#define QMI_DIRECT_CSR_ASSERT_CS1N_MSB _u(3) +#define QMI_DIRECT_CSR_ASSERT_CS1N_LSB _u(3) +#define QMI_DIRECT_CSR_ASSERT_CS1N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_ASSERT_CS0N +// Description : When 1, assert (i.e. drive low) the CS0n chip select line. +// +// Note that this applies even when DIRECT_CSR_EN is 0. +#define QMI_DIRECT_CSR_ASSERT_CS0N_RESET _u(0x0) +#define QMI_DIRECT_CSR_ASSERT_CS0N_BITS _u(0x00000004) +#define QMI_DIRECT_CSR_ASSERT_CS0N_MSB _u(2) +#define QMI_DIRECT_CSR_ASSERT_CS0N_LSB _u(2) +#define QMI_DIRECT_CSR_ASSERT_CS0N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_BUSY +// Description : Direct mode busy flag. If 1, data is currently being shifted +// in/out (or would be if the interface were not stalled on the RX +// FIFO), and the chip select must not yet be deasserted. +// +// The busy flag will also be set to 1 if a memory-mapped transfer +// is still in progress when direct mode is enabled. Direct mode +// blocks new memory-mapped transfers, but can't halt a transfer +// that is already in progress. If there is a chance that memory- +// mapped transfers may be in progress, the busy flag should be +// polled for 0 before asserting the chip select. +// +// (In practice you will usually discover this timing condition +// through other means, because any subsequent memory-mapped +// transfers when direct mode is enabled will return bus errors, +// which are difficult to ignore.) +#define QMI_DIRECT_CSR_BUSY_RESET _u(0x0) +#define QMI_DIRECT_CSR_BUSY_BITS _u(0x00000002) +#define QMI_DIRECT_CSR_BUSY_MSB _u(1) +#define QMI_DIRECT_CSR_BUSY_LSB _u(1) +#define QMI_DIRECT_CSR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_EN +// Description : Enable direct mode. +// +// In direct mode, software controls the chip select lines, and +// can perform direct SPI transfers by pushing data to the +// DIRECT_TX FIFO, and popping the same amount of data from the +// DIRECT_RX FIFO. +// +// Memory-mapped accesses will generate bus errors when direct +// serial mode is enabled. +#define QMI_DIRECT_CSR_EN_RESET _u(0x0) +#define QMI_DIRECT_CSR_EN_BITS _u(0x00000001) +#define QMI_DIRECT_CSR_EN_MSB _u(0) +#define QMI_DIRECT_CSR_EN_LSB _u(0) +#define QMI_DIRECT_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : QMI_DIRECT_TX +// Description : Transmit FIFO for direct mode +#define QMI_DIRECT_TX_OFFSET _u(0x00000004) +#define QMI_DIRECT_TX_BITS _u(0x001fffff) +#define QMI_DIRECT_TX_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_NOPUSH +// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO +// entry. +// +// Useful to avoid garbage appearing in the RX FIFO when pushing +// the command at the beginning of a SPI transfer. +#define QMI_DIRECT_TX_NOPUSH_RESET _u(0x0) +#define QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000) +#define QMI_DIRECT_TX_NOPUSH_MSB _u(20) +#define QMI_DIRECT_TX_NOPUSH_LSB _u(20) +#define QMI_DIRECT_TX_NOPUSH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_OE +// Description : Output enable (active-high). For single width (SPI), this field +// is ignored, and SD0 is always set to output, with SD1 always +// set to input. +// +// For dual and quad width (DSPI/QSPI), this sets whether the +// relevant SDx pads are set to output whilst transferring this +// FIFO record. In this case the command/address should have OE +// set, and the data transfer should have OE set or clear +// depending on the direction of the transfer. +#define QMI_DIRECT_TX_OE_RESET _u(0x0) +#define QMI_DIRECT_TX_OE_BITS _u(0x00080000) +#define QMI_DIRECT_TX_OE_MSB _u(19) +#define QMI_DIRECT_TX_OE_LSB _u(19) +#define QMI_DIRECT_TX_OE_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_DWIDTH +// Description : Data width. If 0, hardware will transmit the 8 LSBs of the +// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs +// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and +// 16-bit transfers can be mixed freely. +#define QMI_DIRECT_TX_DWIDTH_RESET _u(0x0) +#define QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000) +#define QMI_DIRECT_TX_DWIDTH_MSB _u(18) +#define QMI_DIRECT_TX_DWIDTH_LSB _u(18) +#define QMI_DIRECT_TX_DWIDTH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_IWIDTH +// Description : Configure whether this FIFO record is transferred with +// single/dual/quad interface width (0/1/2). Different widths can +// be mixed freely. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_DIRECT_TX_IWIDTH_RESET _u(0x0) +#define QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000) +#define QMI_DIRECT_TX_IWIDTH_MSB _u(17) +#define QMI_DIRECT_TX_IWIDTH_LSB _u(16) +#define QMI_DIRECT_TX_IWIDTH_ACCESS "WF" +#define QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0) +#define QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1) +#define QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_DATA +// Description : Data pushed here will be clocked out falling edges of SCK (or +// before the very first rising edge of SCK, if this is the first +// pulse). For each byte clocked out, the interface will +// simultaneously sample one byte, on rising edges of SCK, and +// push this to the DIRECT_RX FIFO. +// +// For 16-bit data, the least-significant byte is transmitted +// first. +#define QMI_DIRECT_TX_DATA_RESET _u(0x0000) +#define QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff) +#define QMI_DIRECT_TX_DATA_MSB _u(15) +#define QMI_DIRECT_TX_DATA_LSB _u(0) +#define QMI_DIRECT_TX_DATA_ACCESS "WF" +// ============================================================================= +// Register : QMI_DIRECT_RX +// Description : Receive FIFO for direct mode +// With each byte clocked out on the serial interface, one byte +// will simultaneously be clocked in, and will appear in this +// FIFO. The serial interface will stall when this FIFO is full, +// to avoid dropping data. +// +// When 16-bit data is pushed into the TX FIFO, the corresponding +// RX FIFO push will also contain 16 bits of data. The least- +// significant byte is the first one received. +#define QMI_DIRECT_RX_OFFSET _u(0x00000008) +#define QMI_DIRECT_RX_BITS _u(0x0000ffff) +#define QMI_DIRECT_RX_RESET _u(0x00000000) +#define QMI_DIRECT_RX_MSB _u(15) +#define QMI_DIRECT_RX_LSB _u(0) +#define QMI_DIRECT_RX_ACCESS "RF" +// ============================================================================= +// Register : QMI_M0_TIMING +// Description : Timing configuration register for memory address window 0. +#define QMI_M0_TIMING_OFFSET _u(0x0000000c) +#define QMI_M0_TIMING_BITS _u(0xf3fff7ff) +#define QMI_M0_TIMING_RESET _u(0x40000004) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_COOLDOWN +// Description : Chip select cooldown period. When a memory transfer finishes, +// the chip select remains asserted for 64 x COOLDOWN system clock +// cycles, plus half an SCK clock period (rounded up for odd SCK +// divisors). After this cooldown expires, the chip select is +// always deasserted to save power. +// +// If the next memory access arrives within the cooldown period, +// the QMI may be able to append more SCK cycles to the currently +// ongoing SPI transfer, rather than starting a new transfer. This +// reduces access latency and increases bus throughput. +// +// Specifically, the next access must be in the same direction +// (read/write), access the same memory window (chip select 0/1), +// and follow sequentially the address of the last transfer. If +// any of these are false, the new access will first deassert the +// chip select, then begin a new transfer. +// +// If COOLDOWN is 0, the address alignment configured by PAGEBREAK +// has been reached, or the total chip select assertion limit +// MAX_SELECT has been reached, the cooldown period is skipped, +// and the chip select will always be deasserted one half SCK +// period after the transfer finishes. +#define QMI_M0_TIMING_COOLDOWN_RESET _u(0x1) +#define QMI_M0_TIMING_COOLDOWN_BITS _u(0xc0000000) +#define QMI_M0_TIMING_COOLDOWN_MSB _u(31) +#define QMI_M0_TIMING_COOLDOWN_LSB _u(30) +#define QMI_M0_TIMING_COOLDOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_PAGEBREAK +// Description : When page break is enabled, chip select will automatically +// deassert when crossing certain power-of-2-aligned address +// boundaries. The next access will always begin a new read/write +// SPI burst, even if the address of the next access follows in +// sequence with the last access before the page boundary. +// +// Some flash and PSRAM devices forbid crossing page boundaries +// with a single read/write transfer, or restrict the operating +// frequency for transfers that do cross page a boundary. This +// option allows the QMI to safely support those devices. +// +// This field has no effect when COOLDOWN is disabled. +// 0x0 -> No page boundary is enforced +// 0x1 -> Break bursts crossing a 256-byte page boundary +// 0x2 -> Break bursts crossing a 1024-byte quad-page boundary +// 0x3 -> Break bursts crossing a 4096-byte sector boundary +#define QMI_M0_TIMING_PAGEBREAK_RESET _u(0x0) +#define QMI_M0_TIMING_PAGEBREAK_BITS _u(0x30000000) +#define QMI_M0_TIMING_PAGEBREAK_MSB _u(29) +#define QMI_M0_TIMING_PAGEBREAK_LSB _u(28) +#define QMI_M0_TIMING_PAGEBREAK_ACCESS "RW" +#define QMI_M0_TIMING_PAGEBREAK_VALUE_NONE _u(0x0) +#define QMI_M0_TIMING_PAGEBREAK_VALUE_256 _u(0x1) +#define QMI_M0_TIMING_PAGEBREAK_VALUE_1024 _u(0x2) +#define QMI_M0_TIMING_PAGEBREAK_VALUE_4096 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_SELECT_SETUP +// Description : Add up to one additional system clock cycle of setup between +// chip select assertion and the first rising edge of SCK. +// +// The default setup time is one half SCK period, which is usually +// sufficient except for very high SCK frequencies with some flash +// devices. +#define QMI_M0_TIMING_SELECT_SETUP_RESET _u(0x0) +#define QMI_M0_TIMING_SELECT_SETUP_BITS _u(0x02000000) +#define QMI_M0_TIMING_SELECT_SETUP_MSB _u(25) +#define QMI_M0_TIMING_SELECT_SETUP_LSB _u(25) +#define QMI_M0_TIMING_SELECT_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_SELECT_HOLD +// Description : Add up to three additional system clock cycles of active hold +// between the last falling edge of SCK and the deassertion of +// this window's chip select. +// +// The default hold time is one system clock cycle. Note that +// flash datasheets usually give chip select active hold time from +// the last *rising* edge of SCK, and so even zero hold from the +// last falling edge would be safe. +// +// Note that this is a minimum hold time guaranteed by the QMI: +// the actual chip select active hold may be slightly longer for +// read transfers with low clock divisors and/or high sample +// delays. Specifically, if the point two cycles after the last RX +// data sample is later than the last SCK falling edge, then the +// hold time is measured from *this* point. +// +// Note also that, in case the final SCK pulse is masked to save +// energy (true for non-DTR reads when COOLDOWN is disabled or +// PAGE_BREAK is reached), all of QMI's timing logic behaves as +// though the clock pulse were still present. The SELECT_HOLD time +// is applied from the point where the last SCK falling edge would +// be if the clock pulse were not masked. +#define QMI_M0_TIMING_SELECT_HOLD_RESET _u(0x0) +#define QMI_M0_TIMING_SELECT_HOLD_BITS _u(0x01800000) +#define QMI_M0_TIMING_SELECT_HOLD_MSB _u(24) +#define QMI_M0_TIMING_SELECT_HOLD_LSB _u(23) +#define QMI_M0_TIMING_SELECT_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_MAX_SELECT +// Description : Enforce a maximum assertion duration for this window's chip +// select, in units of 64 system clock cycles. If 0, the QMI is +// permitted to keep the chip select asserted indefinitely when +// servicing sequential memory accesses (see COOLDOWN). +// +// This feature is required to meet timing constraints of PSRAM +// devices, which specify a maximum chip select assertion so they +// can perform DRAM refresh cycles. See also MIN_DESELECT, which +// can enforce a minimum deselect time. +// +// If a memory access is in progress at the time MAX_SELECT is +// reached, the QMI will wait for the access to complete before +// deasserting the chip select. This additional time must be +// accounted for to calculate a safe MAX_SELECT value. In the +// worst case, this may be a fully-formed serial transfer, +// including command prefix and address, with a data payload as +// large as one cache line. +#define QMI_M0_TIMING_MAX_SELECT_RESET _u(0x00) +#define QMI_M0_TIMING_MAX_SELECT_BITS _u(0x007e0000) +#define QMI_M0_TIMING_MAX_SELECT_MSB _u(22) +#define QMI_M0_TIMING_MAX_SELECT_LSB _u(17) +#define QMI_M0_TIMING_MAX_SELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_MIN_DESELECT +// Description : After this window's chip select is deasserted, it remains +// deasserted for half an SCK cycle (rounded up to an integer +// number of system clock cycles), plus MIN_DESELECT additional +// system clock cycles, before the QMI reasserts either chip +// select pin. +// +// Nonzero values may be required for PSRAM devices which enforce +// a longer minimum CS deselect time, so that they can perform +// internal DRAM refresh cycles whilst deselected. +#define QMI_M0_TIMING_MIN_DESELECT_RESET _u(0x00) +#define QMI_M0_TIMING_MIN_DESELECT_BITS _u(0x0001f000) +#define QMI_M0_TIMING_MIN_DESELECT_MSB _u(16) +#define QMI_M0_TIMING_MIN_DESELECT_LSB _u(12) +#define QMI_M0_TIMING_MIN_DESELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_RXDELAY +// Description : Delay the read data sample timing, in units of one half of a +// system clock cycle. (Not necessarily half of an SCK cycle.) An +// RXDELAY of 0 means the sample is captured at the SDI input +// registers simultaneously with the rising edge of SCK launched +// from the SCK output register. +// +// At higher SCK frequencies, RXDELAY may need to be increased to +// account for the round trip delay of the pads, and the clock- +// to-Q delay of the QSPI memory device. +#define QMI_M0_TIMING_RXDELAY_RESET _u(0x0) +#define QMI_M0_TIMING_RXDELAY_BITS _u(0x00000700) +#define QMI_M0_TIMING_RXDELAY_MSB _u(10) +#define QMI_M0_TIMING_RXDELAY_LSB _u(8) +#define QMI_M0_TIMING_RXDELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_CLKDIV +// Description : Clock divisor. Odd and even divisors are supported. Defines the +// SCK clock period in units of 1 system clock cycle. Divisors +// 1..255 are encoded directly, and a divisor of 256 is encoded +// with a value of CLKDIV=0. +// +// The clock divisor can be changed on-the-fly, even when the QMI +// is currently accessing memory in this address window. All other +// parameters must only be changed when the QMI is idle. +// +// If software is increasing CLKDIV in anticipation of an increase +// in the system clock frequency, a dummy access to either memory +// window (and appropriate processor barriers/fences) must be +// inserted after the Mx_TIMING write to ensure the SCK divisor +// change is in effect _before_ the system clock is changed. +#define QMI_M0_TIMING_CLKDIV_RESET _u(0x04) +#define QMI_M0_TIMING_CLKDIV_BITS _u(0x000000ff) +#define QMI_M0_TIMING_CLKDIV_MSB _u(7) +#define QMI_M0_TIMING_CLKDIV_LSB _u(0) +#define QMI_M0_TIMING_CLKDIV_ACCESS "RW" +// ============================================================================= +// Register : QMI_M0_RFMT +// Description : Read transfer format configuration for memory address window 0. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M0_RFMT register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M0_RFMT_OFFSET _u(0x00000010) +#define QMI_M0_RFMT_BITS _u(0x1007d3ff) +#define QMI_M0_RFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DTR +// Description : Enable double transfer rate (DTR) for read commands: address, +// suffix and read data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M0_RFMT_DTR_RESET _u(0x0) +#define QMI_M0_RFMT_DTR_BITS _u(0x10000000) +#define QMI_M0_RFMT_DTR_MSB _u(28) +#define QMI_M0_RFMT_DTR_LSB _u(28) +#define QMI_M0_RFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M0_RFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M0_RFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M0_RFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M0_RFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M0_RFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M0_RFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M0_RFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M0_RFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M0_RFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M0_RFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M0_RFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_RFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M0_RFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M0_RFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M0_RFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M0_RFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M0_RFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M0_RFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_RFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M0_RFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M0_RFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M0_RFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M0_RFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M0_RFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M0_RFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M0_RFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M0_RFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M0_RFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M0_RFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M0_RFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M0_RFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M0_RFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M0_RFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M0_RFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M0_RCMD +// Description : Command constants used for reads from memory address window 0. +// +// The reset value of the M0_RCMD register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M0_RCMD_OFFSET _u(0x00000014) +#define QMI_M0_RCMD_BITS _u(0x0000ffff) +#define QMI_M0_RCMD_RESET _u(0x0000a003) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_RFMT_SUFFIX_LEN is nonzero. +#define QMI_M0_RCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M0_RCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M0_RCMD_SUFFIX_MSB _u(15) +#define QMI_M0_RCMD_SUFFIX_LSB _u(8) +#define QMI_M0_RCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_RFMT_PREFIX_LEN is nonzero. +#define QMI_M0_RCMD_PREFIX_RESET _u(0x03) +#define QMI_M0_RCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M0_RCMD_PREFIX_MSB _u(7) +#define QMI_M0_RCMD_PREFIX_LSB _u(0) +#define QMI_M0_RCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_M0_WFMT +// Description : Write transfer format configuration for memory address window +// 0. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M0_WFMT register is configured to +// support a basic 02h serial write transfer. However, writes to +// this window must first be enabled via the XIP_CTRL_WRITABLE_M0 +// bit, as XIP memory is read-only by default. +#define QMI_M0_WFMT_OFFSET _u(0x00000018) +#define QMI_M0_WFMT_BITS _u(0x1007d3ff) +#define QMI_M0_WFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DTR +// Description : Enable double transfer rate (DTR) for write commands: address, +// suffix and write data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M0_WFMT_DTR_RESET _u(0x0) +#define QMI_M0_WFMT_DTR_BITS _u(0x10000000) +#define QMI_M0_WFMT_DTR_MSB _u(28) +#define QMI_M0_WFMT_DTR_LSB _u(28) +#define QMI_M0_WFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M0_WFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M0_WFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M0_WFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M0_WFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M0_WFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M0_WFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M0_WFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M0_WFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M0_WFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M0_WFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M0_WFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_WFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M0_WFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M0_WFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M0_WFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M0_WFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M0_WFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M0_WFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_WFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M0_WFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M0_WFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M0_WFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M0_WFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M0_WFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M0_WFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M0_WFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M0_WFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M0_WFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M0_WFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M0_WFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M0_WFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M0_WFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M0_WFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M0_WFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M0_WCMD +// Description : Command constants used for writes to memory address window 0. +// +// The reset value of the M0_WCMD register is configured to +// support a basic 02h serial write transfer with no additional +// configuration. +#define QMI_M0_WCMD_OFFSET _u(0x0000001c) +#define QMI_M0_WCMD_BITS _u(0x0000ffff) +#define QMI_M0_WCMD_RESET _u(0x0000a002) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_WFMT_SUFFIX_LEN is nonzero. +#define QMI_M0_WCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M0_WCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M0_WCMD_SUFFIX_MSB _u(15) +#define QMI_M0_WCMD_SUFFIX_LSB _u(8) +#define QMI_M0_WCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_WFMT_PREFIX_LEN is nonzero. +#define QMI_M0_WCMD_PREFIX_RESET _u(0x02) +#define QMI_M0_WCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M0_WCMD_PREFIX_MSB _u(7) +#define QMI_M0_WCMD_PREFIX_LSB _u(0) +#define QMI_M0_WCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_M1_TIMING +// Description : Timing configuration register for memory address window 1. +#define QMI_M1_TIMING_OFFSET _u(0x00000020) +#define QMI_M1_TIMING_BITS _u(0xf3fff7ff) +#define QMI_M1_TIMING_RESET _u(0x40000004) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_COOLDOWN +// Description : Chip select cooldown period. When a memory transfer finishes, +// the chip select remains asserted for 64 x COOLDOWN system clock +// cycles, plus half an SCK clock period (rounded up for odd SCK +// divisors). After this cooldown expires, the chip select is +// always deasserted to save power. +// +// If the next memory access arrives within the cooldown period, +// the QMI may be able to append more SCK cycles to the currently +// ongoing SPI transfer, rather than starting a new transfer. This +// reduces access latency and increases bus throughput. +// +// Specifically, the next access must be in the same direction +// (read/write), access the same memory window (chip select 0/1), +// and follow sequentially the address of the last transfer. If +// any of these are false, the new access will first deassert the +// chip select, then begin a new transfer. +// +// If COOLDOWN is 0, the address alignment configured by PAGEBREAK +// has been reached, or the total chip select assertion limit +// MAX_SELECT has been reached, the cooldown period is skipped, +// and the chip select will always be deasserted one half SCK +// period after the transfer finishes. +#define QMI_M1_TIMING_COOLDOWN_RESET _u(0x1) +#define QMI_M1_TIMING_COOLDOWN_BITS _u(0xc0000000) +#define QMI_M1_TIMING_COOLDOWN_MSB _u(31) +#define QMI_M1_TIMING_COOLDOWN_LSB _u(30) +#define QMI_M1_TIMING_COOLDOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_PAGEBREAK +// Description : When page break is enabled, chip select will automatically +// deassert when crossing certain power-of-2-aligned address +// boundaries. The next access will always begin a new read/write +// SPI burst, even if the address of the next access follows in +// sequence with the last access before the page boundary. +// +// Some flash and PSRAM devices forbid crossing page boundaries +// with a single read/write transfer, or restrict the operating +// frequency for transfers that do cross page a boundary. This +// option allows the QMI to safely support those devices. +// +// This field has no effect when COOLDOWN is disabled. +// 0x0 -> No page boundary is enforced +// 0x1 -> Break bursts crossing a 256-byte page boundary +// 0x2 -> Break bursts crossing a 1024-byte quad-page boundary +// 0x3 -> Break bursts crossing a 4096-byte sector boundary +#define QMI_M1_TIMING_PAGEBREAK_RESET _u(0x0) +#define QMI_M1_TIMING_PAGEBREAK_BITS _u(0x30000000) +#define QMI_M1_TIMING_PAGEBREAK_MSB _u(29) +#define QMI_M1_TIMING_PAGEBREAK_LSB _u(28) +#define QMI_M1_TIMING_PAGEBREAK_ACCESS "RW" +#define QMI_M1_TIMING_PAGEBREAK_VALUE_NONE _u(0x0) +#define QMI_M1_TIMING_PAGEBREAK_VALUE_256 _u(0x1) +#define QMI_M1_TIMING_PAGEBREAK_VALUE_1024 _u(0x2) +#define QMI_M1_TIMING_PAGEBREAK_VALUE_4096 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_SELECT_SETUP +// Description : Add up to one additional system clock cycle of setup between +// chip select assertion and the first rising edge of SCK. +// +// The default setup time is one half SCK period, which is usually +// sufficient except for very high SCK frequencies with some flash +// devices. +#define QMI_M1_TIMING_SELECT_SETUP_RESET _u(0x0) +#define QMI_M1_TIMING_SELECT_SETUP_BITS _u(0x02000000) +#define QMI_M1_TIMING_SELECT_SETUP_MSB _u(25) +#define QMI_M1_TIMING_SELECT_SETUP_LSB _u(25) +#define QMI_M1_TIMING_SELECT_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_SELECT_HOLD +// Description : Add up to three additional system clock cycles of active hold +// between the last falling edge of SCK and the deassertion of +// this window's chip select. +// +// The default hold time is one system clock cycle. Note that +// flash datasheets usually give chip select active hold time from +// the last *rising* edge of SCK, and so even zero hold from the +// last falling edge would be safe. +// +// Note that this is a minimum hold time guaranteed by the QMI: +// the actual chip select active hold may be slightly longer for +// read transfers with low clock divisors and/or high sample +// delays. Specifically, if the point two cycles after the last RX +// data sample is later than the last SCK falling edge, then the +// hold time is measured from *this* point. +// +// Note also that, in case the final SCK pulse is masked to save +// energy (true for non-DTR reads when COOLDOWN is disabled or +// PAGE_BREAK is reached), all of QMI's timing logic behaves as +// though the clock pulse were still present. The SELECT_HOLD time +// is applied from the point where the last SCK falling edge would +// be if the clock pulse were not masked. +#define QMI_M1_TIMING_SELECT_HOLD_RESET _u(0x0) +#define QMI_M1_TIMING_SELECT_HOLD_BITS _u(0x01800000) +#define QMI_M1_TIMING_SELECT_HOLD_MSB _u(24) +#define QMI_M1_TIMING_SELECT_HOLD_LSB _u(23) +#define QMI_M1_TIMING_SELECT_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_MAX_SELECT +// Description : Enforce a maximum assertion duration for this window's chip +// select, in units of 64 system clock cycles. If 0, the QMI is +// permitted to keep the chip select asserted indefinitely when +// servicing sequential memory accesses (see COOLDOWN). +// +// This feature is required to meet timing constraints of PSRAM +// devices, which specify a maximum chip select assertion so they +// can perform DRAM refresh cycles. See also MIN_DESELECT, which +// can enforce a minimum deselect time. +// +// If a memory access is in progress at the time MAX_SELECT is +// reached, the QMI will wait for the access to complete before +// deasserting the chip select. This additional time must be +// accounted for to calculate a safe MAX_SELECT value. In the +// worst case, this may be a fully-formed serial transfer, +// including command prefix and address, with a data payload as +// large as one cache line. +#define QMI_M1_TIMING_MAX_SELECT_RESET _u(0x00) +#define QMI_M1_TIMING_MAX_SELECT_BITS _u(0x007e0000) +#define QMI_M1_TIMING_MAX_SELECT_MSB _u(22) +#define QMI_M1_TIMING_MAX_SELECT_LSB _u(17) +#define QMI_M1_TIMING_MAX_SELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_MIN_DESELECT +// Description : After this window's chip select is deasserted, it remains +// deasserted for half an SCK cycle (rounded up to an integer +// number of system clock cycles), plus MIN_DESELECT additional +// system clock cycles, before the QMI reasserts either chip +// select pin. +// +// Nonzero values may be required for PSRAM devices which enforce +// a longer minimum CS deselect time, so that they can perform +// internal DRAM refresh cycles whilst deselected. +#define QMI_M1_TIMING_MIN_DESELECT_RESET _u(0x00) +#define QMI_M1_TIMING_MIN_DESELECT_BITS _u(0x0001f000) +#define QMI_M1_TIMING_MIN_DESELECT_MSB _u(16) +#define QMI_M1_TIMING_MIN_DESELECT_LSB _u(12) +#define QMI_M1_TIMING_MIN_DESELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_RXDELAY +// Description : Delay the read data sample timing, in units of one half of a +// system clock cycle. (Not necessarily half of an SCK cycle.) An +// RXDELAY of 0 means the sample is captured at the SDI input +// registers simultaneously with the rising edge of SCK launched +// from the SCK output register. +// +// At higher SCK frequencies, RXDELAY may need to be increased to +// account for the round trip delay of the pads, and the clock- +// to-Q delay of the QSPI memory device. +#define QMI_M1_TIMING_RXDELAY_RESET _u(0x0) +#define QMI_M1_TIMING_RXDELAY_BITS _u(0x00000700) +#define QMI_M1_TIMING_RXDELAY_MSB _u(10) +#define QMI_M1_TIMING_RXDELAY_LSB _u(8) +#define QMI_M1_TIMING_RXDELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_CLKDIV +// Description : Clock divisor. Odd and even divisors are supported. Defines the +// SCK clock period in units of 1 system clock cycle. Divisors +// 1..255 are encoded directly, and a divisor of 256 is encoded +// with a value of CLKDIV=0. +// +// The clock divisor can be changed on-the-fly, even when the QMI +// is currently accessing memory in this address window. All other +// parameters must only be changed when the QMI is idle. +// +// If software is increasing CLKDIV in anticipation of an increase +// in the system clock frequency, a dummy access to either memory +// window (and appropriate processor barriers/fences) must be +// inserted after the Mx_TIMING write to ensure the SCK divisor +// change is in effect _before_ the system clock is changed. +#define QMI_M1_TIMING_CLKDIV_RESET _u(0x04) +#define QMI_M1_TIMING_CLKDIV_BITS _u(0x000000ff) +#define QMI_M1_TIMING_CLKDIV_MSB _u(7) +#define QMI_M1_TIMING_CLKDIV_LSB _u(0) +#define QMI_M1_TIMING_CLKDIV_ACCESS "RW" +// ============================================================================= +// Register : QMI_M1_RFMT +// Description : Read transfer format configuration for memory address window 1. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M1_RFMT register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M1_RFMT_OFFSET _u(0x00000024) +#define QMI_M1_RFMT_BITS _u(0x1007d3ff) +#define QMI_M1_RFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DTR +// Description : Enable double transfer rate (DTR) for read commands: address, +// suffix and read data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M1_RFMT_DTR_RESET _u(0x0) +#define QMI_M1_RFMT_DTR_BITS _u(0x10000000) +#define QMI_M1_RFMT_DTR_MSB _u(28) +#define QMI_M1_RFMT_DTR_LSB _u(28) +#define QMI_M1_RFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M1_RFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M1_RFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M1_RFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M1_RFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M1_RFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M1_RFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M1_RFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M1_RFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M1_RFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M1_RFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M1_RFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_RFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M1_RFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M1_RFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M1_RFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M1_RFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M1_RFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M1_RFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_RFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M1_RFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M1_RFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M1_RFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M1_RFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M1_RFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M1_RFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M1_RFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M1_RFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M1_RFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M1_RFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M1_RFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M1_RFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M1_RFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M1_RFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M1_RFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M1_RCMD +// Description : Command constants used for reads from memory address window 1. +// +// The reset value of the M1_RCMD register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M1_RCMD_OFFSET _u(0x00000028) +#define QMI_M1_RCMD_BITS _u(0x0000ffff) +#define QMI_M1_RCMD_RESET _u(0x0000a003) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_RFMT_SUFFIX_LEN is nonzero. +#define QMI_M1_RCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M1_RCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M1_RCMD_SUFFIX_MSB _u(15) +#define QMI_M1_RCMD_SUFFIX_LSB _u(8) +#define QMI_M1_RCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_RFMT_PREFIX_LEN is nonzero. +#define QMI_M1_RCMD_PREFIX_RESET _u(0x03) +#define QMI_M1_RCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M1_RCMD_PREFIX_MSB _u(7) +#define QMI_M1_RCMD_PREFIX_LSB _u(0) +#define QMI_M1_RCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_M1_WFMT +// Description : Write transfer format configuration for memory address window +// 1. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M1_WFMT register is configured to +// support a basic 02h serial write transfer. However, writes to +// this window must first be enabled via the XIP_CTRL_WRITABLE_M1 +// bit, as XIP memory is read-only by default. +#define QMI_M1_WFMT_OFFSET _u(0x0000002c) +#define QMI_M1_WFMT_BITS _u(0x1007d3ff) +#define QMI_M1_WFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DTR +// Description : Enable double transfer rate (DTR) for write commands: address, +// suffix and write data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M1_WFMT_DTR_RESET _u(0x0) +#define QMI_M1_WFMT_DTR_BITS _u(0x10000000) +#define QMI_M1_WFMT_DTR_MSB _u(28) +#define QMI_M1_WFMT_DTR_LSB _u(28) +#define QMI_M1_WFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M1_WFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M1_WFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M1_WFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M1_WFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M1_WFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M1_WFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M1_WFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M1_WFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M1_WFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M1_WFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M1_WFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_WFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M1_WFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M1_WFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M1_WFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M1_WFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M1_WFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M1_WFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_WFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M1_WFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M1_WFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M1_WFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M1_WFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M1_WFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M1_WFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M1_WFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M1_WFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M1_WFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M1_WFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M1_WFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M1_WFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M1_WFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M1_WFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M1_WFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M1_WCMD +// Description : Command constants used for writes to memory address window 1. +// +// The reset value of the M1_WCMD register is configured to +// support a basic 02h serial write transfer with no additional +// configuration. +#define QMI_M1_WCMD_OFFSET _u(0x00000030) +#define QMI_M1_WCMD_BITS _u(0x0000ffff) +#define QMI_M1_WCMD_RESET _u(0x0000a002) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_WFMT_SUFFIX_LEN is nonzero. +#define QMI_M1_WCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M1_WCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M1_WCMD_SUFFIX_MSB _u(15) +#define QMI_M1_WCMD_SUFFIX_LSB _u(8) +#define QMI_M1_WCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_WFMT_PREFIX_LEN is nonzero. +#define QMI_M1_WCMD_PREFIX_RESET _u(0x02) +#define QMI_M1_WCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M1_WCMD_PREFIX_MSB _u(7) +#define QMI_M1_WCMD_PREFIX_LSB _u(0) +#define QMI_M1_WCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS0 +// Description : Configure address translation for XIP virtual addresses +// 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS0_OFFSET _u(0x00000034) +#define QMI_ATRANS0_BITS _u(0x07ff0fff) +#define QMI_ATRANS0_RESET _u(0x04000000) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS0_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS0_SIZE_RESET _u(0x400) +#define QMI_ATRANS0_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS0_SIZE_MSB _u(26) +#define QMI_ATRANS0_SIZE_LSB _u(16) +#define QMI_ATRANS0_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS0_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS0_BASE_RESET _u(0x000) +#define QMI_ATRANS0_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS0_BASE_MSB _u(11) +#define QMI_ATRANS0_BASE_LSB _u(0) +#define QMI_ATRANS0_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS1 +// Description : Configure address translation for XIP virtual addresses +// 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS1_OFFSET _u(0x00000038) +#define QMI_ATRANS1_BITS _u(0x07ff0fff) +#define QMI_ATRANS1_RESET _u(0x04000400) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS1_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS1_SIZE_RESET _u(0x400) +#define QMI_ATRANS1_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS1_SIZE_MSB _u(26) +#define QMI_ATRANS1_SIZE_LSB _u(16) +#define QMI_ATRANS1_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS1_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS1_BASE_RESET _u(0x400) +#define QMI_ATRANS1_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS1_BASE_MSB _u(11) +#define QMI_ATRANS1_BASE_LSB _u(0) +#define QMI_ATRANS1_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS2 +// Description : Configure address translation for XIP virtual addresses +// 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS2_OFFSET _u(0x0000003c) +#define QMI_ATRANS2_BITS _u(0x07ff0fff) +#define QMI_ATRANS2_RESET _u(0x04000800) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS2_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS2_SIZE_RESET _u(0x400) +#define QMI_ATRANS2_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS2_SIZE_MSB _u(26) +#define QMI_ATRANS2_SIZE_LSB _u(16) +#define QMI_ATRANS2_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS2_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS2_BASE_RESET _u(0x800) +#define QMI_ATRANS2_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS2_BASE_MSB _u(11) +#define QMI_ATRANS2_BASE_LSB _u(0) +#define QMI_ATRANS2_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS3 +// Description : Configure address translation for XIP virtual addresses +// 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS3_OFFSET _u(0x00000040) +#define QMI_ATRANS3_BITS _u(0x07ff0fff) +#define QMI_ATRANS3_RESET _u(0x04000c00) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS3_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS3_SIZE_RESET _u(0x400) +#define QMI_ATRANS3_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS3_SIZE_MSB _u(26) +#define QMI_ATRANS3_SIZE_LSB _u(16) +#define QMI_ATRANS3_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS3_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS3_BASE_RESET _u(0xc00) +#define QMI_ATRANS3_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS3_BASE_MSB _u(11) +#define QMI_ATRANS3_BASE_LSB _u(0) +#define QMI_ATRANS3_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS4 +// Description : Configure address translation for XIP virtual addresses +// 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS4_OFFSET _u(0x00000044) +#define QMI_ATRANS4_BITS _u(0x07ff0fff) +#define QMI_ATRANS4_RESET _u(0x04000000) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS4_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS4_SIZE_RESET _u(0x400) +#define QMI_ATRANS4_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS4_SIZE_MSB _u(26) +#define QMI_ATRANS4_SIZE_LSB _u(16) +#define QMI_ATRANS4_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS4_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS4_BASE_RESET _u(0x000) +#define QMI_ATRANS4_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS4_BASE_MSB _u(11) +#define QMI_ATRANS4_BASE_LSB _u(0) +#define QMI_ATRANS4_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS5 +// Description : Configure address translation for XIP virtual addresses +// 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS5_OFFSET _u(0x00000048) +#define QMI_ATRANS5_BITS _u(0x07ff0fff) +#define QMI_ATRANS5_RESET _u(0x04000400) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS5_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS5_SIZE_RESET _u(0x400) +#define QMI_ATRANS5_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS5_SIZE_MSB _u(26) +#define QMI_ATRANS5_SIZE_LSB _u(16) +#define QMI_ATRANS5_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS5_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS5_BASE_RESET _u(0x400) +#define QMI_ATRANS5_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS5_BASE_MSB _u(11) +#define QMI_ATRANS5_BASE_LSB _u(0) +#define QMI_ATRANS5_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS6 +// Description : Configure address translation for XIP virtual addresses +// 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS6_OFFSET _u(0x0000004c) +#define QMI_ATRANS6_BITS _u(0x07ff0fff) +#define QMI_ATRANS6_RESET _u(0x04000800) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS6_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS6_SIZE_RESET _u(0x400) +#define QMI_ATRANS6_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS6_SIZE_MSB _u(26) +#define QMI_ATRANS6_SIZE_LSB _u(16) +#define QMI_ATRANS6_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS6_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS6_BASE_RESET _u(0x800) +#define QMI_ATRANS6_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS6_BASE_MSB _u(11) +#define QMI_ATRANS6_BASE_LSB _u(0) +#define QMI_ATRANS6_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS7 +// Description : Configure address translation for XIP virtual addresses +// 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS7_OFFSET _u(0x00000050) +#define QMI_ATRANS7_BITS _u(0x07ff0fff) +#define QMI_ATRANS7_RESET _u(0x04000c00) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS7_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS7_SIZE_RESET _u(0x400) +#define QMI_ATRANS7_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS7_SIZE_MSB _u(26) +#define QMI_ATRANS7_SIZE_LSB _u(16) +#define QMI_ATRANS7_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS7_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS7_BASE_RESET _u(0xc00) +#define QMI_ATRANS7_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS7_BASE_MSB _u(11) +#define QMI_ATRANS7_BASE_LSB _u(0) +#define QMI_ATRANS7_BASE_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_QMI_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/resets.h b/src/rp2350/hardware_regs/include/hardware/regs/resets.h new file mode 100644 index 000000000..459f24e9e --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/resets.h @@ -0,0 +1,641 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RESETS +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_RESETS_H +#define _HARDWARE_REGS_RESETS_H +// ============================================================================= +// Register : RESETS_RESET +#define RESETS_RESET_OFFSET _u(0x00000000) +#define RESETS_RESET_BITS _u(0x1fffffff) +#define RESETS_RESET_RESET _u(0x1fffffff) +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_USBCTRL +#define RESETS_RESET_USBCTRL_RESET _u(0x1) +#define RESETS_RESET_USBCTRL_BITS _u(0x10000000) +#define RESETS_RESET_USBCTRL_MSB _u(28) +#define RESETS_RESET_USBCTRL_LSB _u(28) +#define RESETS_RESET_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART1 +#define RESETS_RESET_UART1_RESET _u(0x1) +#define RESETS_RESET_UART1_BITS _u(0x08000000) +#define RESETS_RESET_UART1_MSB _u(27) +#define RESETS_RESET_UART1_LSB _u(27) +#define RESETS_RESET_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART0 +#define RESETS_RESET_UART0_RESET _u(0x1) +#define RESETS_RESET_UART0_BITS _u(0x04000000) +#define RESETS_RESET_UART0_MSB _u(26) +#define RESETS_RESET_UART0_LSB _u(26) +#define RESETS_RESET_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TRNG +#define RESETS_RESET_TRNG_RESET _u(0x1) +#define RESETS_RESET_TRNG_BITS _u(0x02000000) +#define RESETS_RESET_TRNG_MSB _u(25) +#define RESETS_RESET_TRNG_LSB _u(25) +#define RESETS_RESET_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TIMER1 +#define RESETS_RESET_TIMER1_RESET _u(0x1) +#define RESETS_RESET_TIMER1_BITS _u(0x01000000) +#define RESETS_RESET_TIMER1_MSB _u(24) +#define RESETS_RESET_TIMER1_LSB _u(24) +#define RESETS_RESET_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TIMER0 +#define RESETS_RESET_TIMER0_RESET _u(0x1) +#define RESETS_RESET_TIMER0_BITS _u(0x00800000) +#define RESETS_RESET_TIMER0_MSB _u(23) +#define RESETS_RESET_TIMER0_LSB _u(23) +#define RESETS_RESET_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TBMAN +#define RESETS_RESET_TBMAN_RESET _u(0x1) +#define RESETS_RESET_TBMAN_BITS _u(0x00400000) +#define RESETS_RESET_TBMAN_MSB _u(22) +#define RESETS_RESET_TBMAN_LSB _u(22) +#define RESETS_RESET_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSINFO +#define RESETS_RESET_SYSINFO_RESET _u(0x1) +#define RESETS_RESET_SYSINFO_BITS _u(0x00200000) +#define RESETS_RESET_SYSINFO_MSB _u(21) +#define RESETS_RESET_SYSINFO_LSB _u(21) +#define RESETS_RESET_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSCFG +#define RESETS_RESET_SYSCFG_RESET _u(0x1) +#define RESETS_RESET_SYSCFG_BITS _u(0x00100000) +#define RESETS_RESET_SYSCFG_MSB _u(20) +#define RESETS_RESET_SYSCFG_LSB _u(20) +#define RESETS_RESET_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI1 +#define RESETS_RESET_SPI1_RESET _u(0x1) +#define RESETS_RESET_SPI1_BITS _u(0x00080000) +#define RESETS_RESET_SPI1_MSB _u(19) +#define RESETS_RESET_SPI1_LSB _u(19) +#define RESETS_RESET_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI0 +#define RESETS_RESET_SPI0_RESET _u(0x1) +#define RESETS_RESET_SPI0_BITS _u(0x00040000) +#define RESETS_RESET_SPI0_MSB _u(18) +#define RESETS_RESET_SPI0_LSB _u(18) +#define RESETS_RESET_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SHA256 +#define RESETS_RESET_SHA256_RESET _u(0x1) +#define RESETS_RESET_SHA256_BITS _u(0x00020000) +#define RESETS_RESET_SHA256_MSB _u(17) +#define RESETS_RESET_SHA256_LSB _u(17) +#define RESETS_RESET_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PWM +#define RESETS_RESET_PWM_RESET _u(0x1) +#define RESETS_RESET_PWM_BITS _u(0x00010000) +#define RESETS_RESET_PWM_MSB _u(16) +#define RESETS_RESET_PWM_LSB _u(16) +#define RESETS_RESET_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_USB +#define RESETS_RESET_PLL_USB_RESET _u(0x1) +#define RESETS_RESET_PLL_USB_BITS _u(0x00008000) +#define RESETS_RESET_PLL_USB_MSB _u(15) +#define RESETS_RESET_PLL_USB_LSB _u(15) +#define RESETS_RESET_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_SYS +#define RESETS_RESET_PLL_SYS_RESET _u(0x1) +#define RESETS_RESET_PLL_SYS_BITS _u(0x00004000) +#define RESETS_RESET_PLL_SYS_MSB _u(14) +#define RESETS_RESET_PLL_SYS_LSB _u(14) +#define RESETS_RESET_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO2 +#define RESETS_RESET_PIO2_RESET _u(0x1) +#define RESETS_RESET_PIO2_BITS _u(0x00002000) +#define RESETS_RESET_PIO2_MSB _u(13) +#define RESETS_RESET_PIO2_LSB _u(13) +#define RESETS_RESET_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO1 +#define RESETS_RESET_PIO1_RESET _u(0x1) +#define RESETS_RESET_PIO1_BITS _u(0x00001000) +#define RESETS_RESET_PIO1_MSB _u(12) +#define RESETS_RESET_PIO1_LSB _u(12) +#define RESETS_RESET_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO0 +#define RESETS_RESET_PIO0_RESET _u(0x1) +#define RESETS_RESET_PIO0_BITS _u(0x00000800) +#define RESETS_RESET_PIO0_MSB _u(11) +#define RESETS_RESET_PIO0_LSB _u(11) +#define RESETS_RESET_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_QSPI +#define RESETS_RESET_PADS_QSPI_RESET _u(0x1) +#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000400) +#define RESETS_RESET_PADS_QSPI_MSB _u(10) +#define RESETS_RESET_PADS_QSPI_LSB _u(10) +#define RESETS_RESET_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_BANK0 +#define RESETS_RESET_PADS_BANK0_RESET _u(0x1) +#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000200) +#define RESETS_RESET_PADS_BANK0_MSB _u(9) +#define RESETS_RESET_PADS_BANK0_LSB _u(9) +#define RESETS_RESET_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_JTAG +#define RESETS_RESET_JTAG_RESET _u(0x1) +#define RESETS_RESET_JTAG_BITS _u(0x00000100) +#define RESETS_RESET_JTAG_MSB _u(8) +#define RESETS_RESET_JTAG_LSB _u(8) +#define RESETS_RESET_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_QSPI +#define RESETS_RESET_IO_QSPI_RESET _u(0x1) +#define RESETS_RESET_IO_QSPI_BITS _u(0x00000080) +#define RESETS_RESET_IO_QSPI_MSB _u(7) +#define RESETS_RESET_IO_QSPI_LSB _u(7) +#define RESETS_RESET_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_BANK0 +#define RESETS_RESET_IO_BANK0_RESET _u(0x1) +#define RESETS_RESET_IO_BANK0_BITS _u(0x00000040) +#define RESETS_RESET_IO_BANK0_MSB _u(6) +#define RESETS_RESET_IO_BANK0_LSB _u(6) +#define RESETS_RESET_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C1 +#define RESETS_RESET_I2C1_RESET _u(0x1) +#define RESETS_RESET_I2C1_BITS _u(0x00000020) +#define RESETS_RESET_I2C1_MSB _u(5) +#define RESETS_RESET_I2C1_LSB _u(5) +#define RESETS_RESET_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C0 +#define RESETS_RESET_I2C0_RESET _u(0x1) +#define RESETS_RESET_I2C0_BITS _u(0x00000010) +#define RESETS_RESET_I2C0_MSB _u(4) +#define RESETS_RESET_I2C0_LSB _u(4) +#define RESETS_RESET_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_HSTX +#define RESETS_RESET_HSTX_RESET _u(0x1) +#define RESETS_RESET_HSTX_BITS _u(0x00000008) +#define RESETS_RESET_HSTX_MSB _u(3) +#define RESETS_RESET_HSTX_LSB _u(3) +#define RESETS_RESET_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DMA +#define RESETS_RESET_DMA_RESET _u(0x1) +#define RESETS_RESET_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DMA_MSB _u(2) +#define RESETS_RESET_DMA_LSB _u(2) +#define RESETS_RESET_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_BUSCTRL +#define RESETS_RESET_BUSCTRL_RESET _u(0x1) +#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_BUSCTRL_MSB _u(1) +#define RESETS_RESET_BUSCTRL_LSB _u(1) +#define RESETS_RESET_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_ADC +#define RESETS_RESET_ADC_RESET _u(0x1) +#define RESETS_RESET_ADC_BITS _u(0x00000001) +#define RESETS_RESET_ADC_MSB _u(0) +#define RESETS_RESET_ADC_LSB _u(0) +#define RESETS_RESET_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_WDSEL +#define RESETS_WDSEL_OFFSET _u(0x00000004) +#define RESETS_WDSEL_BITS _u(0x1fffffff) +#define RESETS_WDSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_USBCTRL +#define RESETS_WDSEL_USBCTRL_RESET _u(0x0) +#define RESETS_WDSEL_USBCTRL_BITS _u(0x10000000) +#define RESETS_WDSEL_USBCTRL_MSB _u(28) +#define RESETS_WDSEL_USBCTRL_LSB _u(28) +#define RESETS_WDSEL_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART1 +#define RESETS_WDSEL_UART1_RESET _u(0x0) +#define RESETS_WDSEL_UART1_BITS _u(0x08000000) +#define RESETS_WDSEL_UART1_MSB _u(27) +#define RESETS_WDSEL_UART1_LSB _u(27) +#define RESETS_WDSEL_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART0 +#define RESETS_WDSEL_UART0_RESET _u(0x0) +#define RESETS_WDSEL_UART0_BITS _u(0x04000000) +#define RESETS_WDSEL_UART0_MSB _u(26) +#define RESETS_WDSEL_UART0_LSB _u(26) +#define RESETS_WDSEL_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TRNG +#define RESETS_WDSEL_TRNG_RESET _u(0x0) +#define RESETS_WDSEL_TRNG_BITS _u(0x02000000) +#define RESETS_WDSEL_TRNG_MSB _u(25) +#define RESETS_WDSEL_TRNG_LSB _u(25) +#define RESETS_WDSEL_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TIMER1 +#define RESETS_WDSEL_TIMER1_RESET _u(0x0) +#define RESETS_WDSEL_TIMER1_BITS _u(0x01000000) +#define RESETS_WDSEL_TIMER1_MSB _u(24) +#define RESETS_WDSEL_TIMER1_LSB _u(24) +#define RESETS_WDSEL_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TIMER0 +#define RESETS_WDSEL_TIMER0_RESET _u(0x0) +#define RESETS_WDSEL_TIMER0_BITS _u(0x00800000) +#define RESETS_WDSEL_TIMER0_MSB _u(23) +#define RESETS_WDSEL_TIMER0_LSB _u(23) +#define RESETS_WDSEL_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TBMAN +#define RESETS_WDSEL_TBMAN_RESET _u(0x0) +#define RESETS_WDSEL_TBMAN_BITS _u(0x00400000) +#define RESETS_WDSEL_TBMAN_MSB _u(22) +#define RESETS_WDSEL_TBMAN_LSB _u(22) +#define RESETS_WDSEL_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSINFO +#define RESETS_WDSEL_SYSINFO_RESET _u(0x0) +#define RESETS_WDSEL_SYSINFO_BITS _u(0x00200000) +#define RESETS_WDSEL_SYSINFO_MSB _u(21) +#define RESETS_WDSEL_SYSINFO_LSB _u(21) +#define RESETS_WDSEL_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSCFG +#define RESETS_WDSEL_SYSCFG_RESET _u(0x0) +#define RESETS_WDSEL_SYSCFG_BITS _u(0x00100000) +#define RESETS_WDSEL_SYSCFG_MSB _u(20) +#define RESETS_WDSEL_SYSCFG_LSB _u(20) +#define RESETS_WDSEL_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI1 +#define RESETS_WDSEL_SPI1_RESET _u(0x0) +#define RESETS_WDSEL_SPI1_BITS _u(0x00080000) +#define RESETS_WDSEL_SPI1_MSB _u(19) +#define RESETS_WDSEL_SPI1_LSB _u(19) +#define RESETS_WDSEL_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI0 +#define RESETS_WDSEL_SPI0_RESET _u(0x0) +#define RESETS_WDSEL_SPI0_BITS _u(0x00040000) +#define RESETS_WDSEL_SPI0_MSB _u(18) +#define RESETS_WDSEL_SPI0_LSB _u(18) +#define RESETS_WDSEL_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SHA256 +#define RESETS_WDSEL_SHA256_RESET _u(0x0) +#define RESETS_WDSEL_SHA256_BITS _u(0x00020000) +#define RESETS_WDSEL_SHA256_MSB _u(17) +#define RESETS_WDSEL_SHA256_LSB _u(17) +#define RESETS_WDSEL_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PWM +#define RESETS_WDSEL_PWM_RESET _u(0x0) +#define RESETS_WDSEL_PWM_BITS _u(0x00010000) +#define RESETS_WDSEL_PWM_MSB _u(16) +#define RESETS_WDSEL_PWM_LSB _u(16) +#define RESETS_WDSEL_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_USB +#define RESETS_WDSEL_PLL_USB_RESET _u(0x0) +#define RESETS_WDSEL_PLL_USB_BITS _u(0x00008000) +#define RESETS_WDSEL_PLL_USB_MSB _u(15) +#define RESETS_WDSEL_PLL_USB_LSB _u(15) +#define RESETS_WDSEL_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_SYS +#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) +#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00004000) +#define RESETS_WDSEL_PLL_SYS_MSB _u(14) +#define RESETS_WDSEL_PLL_SYS_LSB _u(14) +#define RESETS_WDSEL_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO2 +#define RESETS_WDSEL_PIO2_RESET _u(0x0) +#define RESETS_WDSEL_PIO2_BITS _u(0x00002000) +#define RESETS_WDSEL_PIO2_MSB _u(13) +#define RESETS_WDSEL_PIO2_LSB _u(13) +#define RESETS_WDSEL_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO1 +#define RESETS_WDSEL_PIO1_RESET _u(0x0) +#define RESETS_WDSEL_PIO1_BITS _u(0x00001000) +#define RESETS_WDSEL_PIO1_MSB _u(12) +#define RESETS_WDSEL_PIO1_LSB _u(12) +#define RESETS_WDSEL_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO0 +#define RESETS_WDSEL_PIO0_RESET _u(0x0) +#define RESETS_WDSEL_PIO0_BITS _u(0x00000800) +#define RESETS_WDSEL_PIO0_MSB _u(11) +#define RESETS_WDSEL_PIO0_LSB _u(11) +#define RESETS_WDSEL_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_QSPI +#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000400) +#define RESETS_WDSEL_PADS_QSPI_MSB _u(10) +#define RESETS_WDSEL_PADS_QSPI_LSB _u(10) +#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_BANK0 +#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000200) +#define RESETS_WDSEL_PADS_BANK0_MSB _u(9) +#define RESETS_WDSEL_PADS_BANK0_LSB _u(9) +#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_JTAG +#define RESETS_WDSEL_JTAG_RESET _u(0x0) +#define RESETS_WDSEL_JTAG_BITS _u(0x00000100) +#define RESETS_WDSEL_JTAG_MSB _u(8) +#define RESETS_WDSEL_JTAG_LSB _u(8) +#define RESETS_WDSEL_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_QSPI +#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000080) +#define RESETS_WDSEL_IO_QSPI_MSB _u(7) +#define RESETS_WDSEL_IO_QSPI_LSB _u(7) +#define RESETS_WDSEL_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_BANK0 +#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000040) +#define RESETS_WDSEL_IO_BANK0_MSB _u(6) +#define RESETS_WDSEL_IO_BANK0_LSB _u(6) +#define RESETS_WDSEL_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C1 +#define RESETS_WDSEL_I2C1_RESET _u(0x0) +#define RESETS_WDSEL_I2C1_BITS _u(0x00000020) +#define RESETS_WDSEL_I2C1_MSB _u(5) +#define RESETS_WDSEL_I2C1_LSB _u(5) +#define RESETS_WDSEL_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C0 +#define RESETS_WDSEL_I2C0_RESET _u(0x0) +#define RESETS_WDSEL_I2C0_BITS _u(0x00000010) +#define RESETS_WDSEL_I2C0_MSB _u(4) +#define RESETS_WDSEL_I2C0_LSB _u(4) +#define RESETS_WDSEL_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_HSTX +#define RESETS_WDSEL_HSTX_RESET _u(0x0) +#define RESETS_WDSEL_HSTX_BITS _u(0x00000008) +#define RESETS_WDSEL_HSTX_MSB _u(3) +#define RESETS_WDSEL_HSTX_LSB _u(3) +#define RESETS_WDSEL_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_DMA +#define RESETS_WDSEL_DMA_RESET _u(0x0) +#define RESETS_WDSEL_DMA_BITS _u(0x00000004) +#define RESETS_WDSEL_DMA_MSB _u(2) +#define RESETS_WDSEL_DMA_LSB _u(2) +#define RESETS_WDSEL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_BUSCTRL +#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) +#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) +#define RESETS_WDSEL_BUSCTRL_MSB _u(1) +#define RESETS_WDSEL_BUSCTRL_LSB _u(1) +#define RESETS_WDSEL_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_ADC +#define RESETS_WDSEL_ADC_RESET _u(0x0) +#define RESETS_WDSEL_ADC_BITS _u(0x00000001) +#define RESETS_WDSEL_ADC_MSB _u(0) +#define RESETS_WDSEL_ADC_LSB _u(0) +#define RESETS_WDSEL_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_RESET_DONE +#define RESETS_RESET_DONE_OFFSET _u(0x00000008) +#define RESETS_RESET_DONE_BITS _u(0x1fffffff) +#define RESETS_RESET_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_USBCTRL +#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x10000000) +#define RESETS_RESET_DONE_USBCTRL_MSB _u(28) +#define RESETS_RESET_DONE_USBCTRL_LSB _u(28) +#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART1 +#define RESETS_RESET_DONE_UART1_RESET _u(0x0) +#define RESETS_RESET_DONE_UART1_BITS _u(0x08000000) +#define RESETS_RESET_DONE_UART1_MSB _u(27) +#define RESETS_RESET_DONE_UART1_LSB _u(27) +#define RESETS_RESET_DONE_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART0 +#define RESETS_RESET_DONE_UART0_RESET _u(0x0) +#define RESETS_RESET_DONE_UART0_BITS _u(0x04000000) +#define RESETS_RESET_DONE_UART0_MSB _u(26) +#define RESETS_RESET_DONE_UART0_LSB _u(26) +#define RESETS_RESET_DONE_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TRNG +#define RESETS_RESET_DONE_TRNG_RESET _u(0x0) +#define RESETS_RESET_DONE_TRNG_BITS _u(0x02000000) +#define RESETS_RESET_DONE_TRNG_MSB _u(25) +#define RESETS_RESET_DONE_TRNG_LSB _u(25) +#define RESETS_RESET_DONE_TRNG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TIMER1 +#define RESETS_RESET_DONE_TIMER1_RESET _u(0x0) +#define RESETS_RESET_DONE_TIMER1_BITS _u(0x01000000) +#define RESETS_RESET_DONE_TIMER1_MSB _u(24) +#define RESETS_RESET_DONE_TIMER1_LSB _u(24) +#define RESETS_RESET_DONE_TIMER1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TIMER0 +#define RESETS_RESET_DONE_TIMER0_RESET _u(0x0) +#define RESETS_RESET_DONE_TIMER0_BITS _u(0x00800000) +#define RESETS_RESET_DONE_TIMER0_MSB _u(23) +#define RESETS_RESET_DONE_TIMER0_LSB _u(23) +#define RESETS_RESET_DONE_TIMER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TBMAN +#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) +#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00400000) +#define RESETS_RESET_DONE_TBMAN_MSB _u(22) +#define RESETS_RESET_DONE_TBMAN_LSB _u(22) +#define RESETS_RESET_DONE_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSINFO +#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00200000) +#define RESETS_RESET_DONE_SYSINFO_MSB _u(21) +#define RESETS_RESET_DONE_SYSINFO_LSB _u(21) +#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSCFG +#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00100000) +#define RESETS_RESET_DONE_SYSCFG_MSB _u(20) +#define RESETS_RESET_DONE_SYSCFG_LSB _u(20) +#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI1 +#define RESETS_RESET_DONE_SPI1_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI1_BITS _u(0x00080000) +#define RESETS_RESET_DONE_SPI1_MSB _u(19) +#define RESETS_RESET_DONE_SPI1_LSB _u(19) +#define RESETS_RESET_DONE_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI0 +#define RESETS_RESET_DONE_SPI0_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI0_BITS _u(0x00040000) +#define RESETS_RESET_DONE_SPI0_MSB _u(18) +#define RESETS_RESET_DONE_SPI0_LSB _u(18) +#define RESETS_RESET_DONE_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SHA256 +#define RESETS_RESET_DONE_SHA256_RESET _u(0x0) +#define RESETS_RESET_DONE_SHA256_BITS _u(0x00020000) +#define RESETS_RESET_DONE_SHA256_MSB _u(17) +#define RESETS_RESET_DONE_SHA256_LSB _u(17) +#define RESETS_RESET_DONE_SHA256_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PWM +#define RESETS_RESET_DONE_PWM_RESET _u(0x0) +#define RESETS_RESET_DONE_PWM_BITS _u(0x00010000) +#define RESETS_RESET_DONE_PWM_MSB _u(16) +#define RESETS_RESET_DONE_PWM_LSB _u(16) +#define RESETS_RESET_DONE_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_USB +#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00008000) +#define RESETS_RESET_DONE_PLL_USB_MSB _u(15) +#define RESETS_RESET_DONE_PLL_USB_LSB _u(15) +#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_SYS +#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00004000) +#define RESETS_RESET_DONE_PLL_SYS_MSB _u(14) +#define RESETS_RESET_DONE_PLL_SYS_LSB _u(14) +#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO2 +#define RESETS_RESET_DONE_PIO2_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO2_BITS _u(0x00002000) +#define RESETS_RESET_DONE_PIO2_MSB _u(13) +#define RESETS_RESET_DONE_PIO2_LSB _u(13) +#define RESETS_RESET_DONE_PIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO1 +#define RESETS_RESET_DONE_PIO1_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO1_BITS _u(0x00001000) +#define RESETS_RESET_DONE_PIO1_MSB _u(12) +#define RESETS_RESET_DONE_PIO1_LSB _u(12) +#define RESETS_RESET_DONE_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO0 +#define RESETS_RESET_DONE_PIO0_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000800) +#define RESETS_RESET_DONE_PIO0_MSB _u(11) +#define RESETS_RESET_DONE_PIO0_LSB _u(11) +#define RESETS_RESET_DONE_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_QSPI +#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000400) +#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(10) +#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(10) +#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_BANK0 +#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000200) +#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(9) +#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(9) +#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_JTAG +#define RESETS_RESET_DONE_JTAG_RESET _u(0x0) +#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000100) +#define RESETS_RESET_DONE_JTAG_MSB _u(8) +#define RESETS_RESET_DONE_JTAG_LSB _u(8) +#define RESETS_RESET_DONE_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_QSPI +#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000080) +#define RESETS_RESET_DONE_IO_QSPI_MSB _u(7) +#define RESETS_RESET_DONE_IO_QSPI_LSB _u(7) +#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_BANK0 +#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000040) +#define RESETS_RESET_DONE_IO_BANK0_MSB _u(6) +#define RESETS_RESET_DONE_IO_BANK0_LSB _u(6) +#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C1 +#define RESETS_RESET_DONE_I2C1_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000020) +#define RESETS_RESET_DONE_I2C1_MSB _u(5) +#define RESETS_RESET_DONE_I2C1_LSB _u(5) +#define RESETS_RESET_DONE_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C0 +#define RESETS_RESET_DONE_I2C0_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000010) +#define RESETS_RESET_DONE_I2C0_MSB _u(4) +#define RESETS_RESET_DONE_I2C0_LSB _u(4) +#define RESETS_RESET_DONE_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_HSTX +#define RESETS_RESET_DONE_HSTX_RESET _u(0x0) +#define RESETS_RESET_DONE_HSTX_BITS _u(0x00000008) +#define RESETS_RESET_DONE_HSTX_MSB _u(3) +#define RESETS_RESET_DONE_HSTX_LSB _u(3) +#define RESETS_RESET_DONE_HSTX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_DMA +#define RESETS_RESET_DONE_DMA_RESET _u(0x0) +#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DONE_DMA_MSB _u(2) +#define RESETS_RESET_DONE_DMA_LSB _u(2) +#define RESETS_RESET_DONE_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_BUSCTRL +#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) +#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) +#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_ADC +#define RESETS_RESET_DONE_ADC_RESET _u(0x0) +#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) +#define RESETS_RESET_DONE_ADC_MSB _u(0) +#define RESETS_RESET_DONE_ADC_LSB _u(0) +#define RESETS_RESET_DONE_ADC_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RESETS_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/riscv_dm.h b/src/rp2350/hardware_regs/include/hardware/regs/riscv_dm.h new file mode 100644 index 000000000..bbf64a296 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/riscv_dm.h @@ -0,0 +1,1025 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RISCV_DM +// Version : 1 +// Bus type : apb +// Description : RISC-V Debug module registers (Hazard3 subset only). Read- +// only information fields (such as dmstatus.version) are +// listed here with the values they have on the RP2350 +// instantiation of Hazard3. +// ============================================================================= +#ifndef _HARDWARE_REGS_RISCV_DM_H +#define _HARDWARE_REGS_RISCV_DM_H +// ============================================================================= +// Register : RISCV_DM_DATA0 +// Description : data0 through data11 are basic read/write registers that may be +// read or changed by abstract commands. abstractcs.datacount +// indicates how many of them are implemented, starting at data0, +// counting up. +// +// Accessing these registers while an abstract command is +// executing causes abstractcs.cmderr to be set to 1 (busy) if it +// is 0. +// +// Attempts to write them while abstractcs.busy is set does not +// change their value. +// +// The values in these registers may not be preserved after an +// abstract command is executed. The only guarantees on their +// contents are the ones offered by the command in question. If +// the command fails, no assumptions can be made about the +// contents of these registers. +// +// (Note: Hazard3 implements data0 only.) +#define RISCV_DM_DATA0_OFFSET _u(0x00000010) +#define RISCV_DM_DATA0_BITS _u(0xffffffff) +#define RISCV_DM_DATA0_RESET _u(0x00000000) +#define RISCV_DM_DATA0_MSB _u(31) +#define RISCV_DM_DATA0_LSB _u(0) +#define RISCV_DM_DATA0_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_DMCONTROL +// Description : This register controls the overall Debug Module as well as the +// currently selected harts, as defined in hasel. +#define RISCV_DM_DMCONTROL_OFFSET _u(0x00000040) +#define RISCV_DM_DMCONTROL_BITS _u(0xf7ffffcf) +#define RISCV_DM_DMCONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HALTREQ +// Description : Writing 0 clears the halt request bit for all currently +// selected harts. This may cancel outstanding halt requests for +// those harts. +// +// Writing 1 sets the halt request bit for all currently selected +// harts. Running harts will halt whenever their halt request bit +// is set. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_HALTREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_HALTREQ_BITS _u(0x80000000) +#define RISCV_DM_DMCONTROL_HALTREQ_MSB _u(31) +#define RISCV_DM_DMCONTROL_HALTREQ_LSB _u(31) +#define RISCV_DM_DMCONTROL_HALTREQ_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_RESUMEREQ +// Description : Writing 1 causes the currently selected harts to resume once, +// if they are halted when the write occurs. It also clears the +// resume ack bit for those harts. +// +// resumereq is ignored if haltreq is set. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_RESUMEREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_RESUMEREQ_BITS _u(0x40000000) +#define RISCV_DM_DMCONTROL_RESUMEREQ_MSB _u(30) +#define RISCV_DM_DMCONTROL_RESUMEREQ_LSB _u(30) +#define RISCV_DM_DMCONTROL_RESUMEREQ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HARTRESET +// Description : This optional field writes the reset bit for all the currently +// selected harts. To perform a reset the debugger writes 1, and +// then writes 0 to deassert the reset signal. +// +// While this bit is 1, the debugger must not change which harts +// are selected. +// +// Writes apply to the new value of hartsel and hasel. +// +// (The exact behaviour of this field is implementation-defined: +// on RP2350 it (triggers a local reset of the selected core(s) +// only.) +#define RISCV_DM_DMCONTROL_HARTRESET_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_HARTRESET_BITS _u(0x20000000) +#define RISCV_DM_DMCONTROL_HARTRESET_MSB _u(29) +#define RISCV_DM_DMCONTROL_HARTRESET_LSB _u(29) +#define RISCV_DM_DMCONTROL_HARTRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_ACKHAVERESET +// Description : 0: No effect. +// +// 1: Clears havereset for any selected harts. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_ACKHAVERESET_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_BITS _u(0x10000000) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_MSB _u(28) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_LSB _u(28) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HASEL +// Description : Selects the definition of currently selected harts. +// +// 0: There is a single currently selected hart, that is selected +// by hartsel. +// +// 1: There may be multiple currently selected harts – the hart +// selected by hartsel, plus those selected by the hart array mask +// register. +// +// Hazard3 does support the hart array mask. +#define RISCV_DM_DMCONTROL_HASEL_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_HASEL_BITS _u(0x04000000) +#define RISCV_DM_DMCONTROL_HASEL_MSB _u(26) +#define RISCV_DM_DMCONTROL_HASEL_LSB _u(26) +#define RISCV_DM_DMCONTROL_HASEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HARTSELLO +// Description : The low 10 bits of hartsel: the DM-specific index of the hart +// to select. This hart is always part of the currently selected +// harts. +// +// On RP2350, since there are only two cores (with one hart each), +// only the least-significant bit is writable. The others are tied +// to 0. +#define RISCV_DM_DMCONTROL_HARTSELLO_RESET _u(0x000) +#define RISCV_DM_DMCONTROL_HARTSELLO_BITS _u(0x03ff0000) +#define RISCV_DM_DMCONTROL_HARTSELLO_MSB _u(25) +#define RISCV_DM_DMCONTROL_HARTSELLO_LSB _u(16) +#define RISCV_DM_DMCONTROL_HARTSELLO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HARTSELHI +// Description : The high 10 bits of hartsel: the DM-specific index of the hart +// to select. This hart is always part of the currently selected +// harts. +// +// On Hazard3 this field is always tied to all-zeroes. +#define RISCV_DM_DMCONTROL_HARTSELHI_RESET _u(0x000) +#define RISCV_DM_DMCONTROL_HARTSELHI_BITS _u(0x0000ffc0) +#define RISCV_DM_DMCONTROL_HARTSELHI_MSB _u(15) +#define RISCV_DM_DMCONTROL_HARTSELHI_LSB _u(6) +#define RISCV_DM_DMCONTROL_HARTSELHI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_SETRESETHALTREQ +// Description : This optional field writes the halt-on-reset request bit for +// all currently selected harts, unless clrresethaltreq is +// simultaneously set to 1. +// +// When set to 1, each selected hart will halt upon the next +// deassertion of its reset. The halt-on-reset request bit is not +// automatically cleared. The debugger must write to +// clrresethaltreq to clear it. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_BITS _u(0x00000008) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_MSB _u(3) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_LSB _u(3) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_CLRRESETHALTREQ +// Description : This optional field clears the halt-on-reset request bit for +// all currently selected harts. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_BITS _u(0x00000004) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_MSB _u(2) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_LSB _u(2) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_NDMRESET +// Description : This bit controls the reset signal from the DM to the rest of +// the system. The signal should reset every part of the system, +// including every hart, except for the DM and any logic required +// to access the DM. To perform a system reset the debugger writes +// 1, and then writes 0 to deassert the reset. +// +// On RP2350 this performs a cold reset, the equivalent of a +// watchdog reset with all WDSEL bits set. This includes both +// cores and all peripherals. +#define RISCV_DM_DMCONTROL_NDMRESET_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_NDMRESET_BITS _u(0x00000002) +#define RISCV_DM_DMCONTROL_NDMRESET_MSB _u(1) +#define RISCV_DM_DMCONTROL_NDMRESET_LSB _u(1) +#define RISCV_DM_DMCONTROL_NDMRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_DMACTIVE +// Description : This bit serves as a reset signal for the Debug Module itself. +// +// 0: The module’s state, including authentication mechanism, +// takes its reset values (the dmactive bit is the only bit which +// can be written to something other than its reset value). +// +// 1: The module functions normally. +// +// No other mechanism should exist that may result in resetting +// the Debug Module after power up, with the possible (but not +// recommended) exception of a global reset signal that resets the +// entire platform. +// +// (On RP2350, the Debug Module is reset by a power-on reset, a +// brownout reset, the RUN pin, and a rescue reset.) +// +// A debugger may pulse this bit low to get the Debug Module into +// a known state. +#define RISCV_DM_DMCONTROL_DMACTIVE_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_DMACTIVE_BITS _u(0x00000001) +#define RISCV_DM_DMCONTROL_DMACTIVE_MSB _u(0) +#define RISCV_DM_DMCONTROL_DMACTIVE_LSB _u(0) +#define RISCV_DM_DMCONTROL_DMACTIVE_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_DMSTATUS +// Description : This register reports status for the overall Debug Module as +// well as the currently selected harts, as defined in hasel. Its +// address will not change in the future, because it contains +// version. +// +// This entire register is read-only. +#define RISCV_DM_DMSTATUS_OFFSET _u(0x00000044) +#define RISCV_DM_DMSTATUS_BITS _u(0x004fffff) +#define RISCV_DM_DMSTATUS_RESET _u(0x004000a2) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_IMPEBREAK +// Description : If 1, then there is an implicit ebreak instruction at the non- +// existent word immediately after the Program Buffer. This saves +// the debugger from having to write the ebreak itself, and allows +// the Program Buffer to be one word smaller. +#define RISCV_DM_DMSTATUS_IMPEBREAK_RESET _u(0x1) +#define RISCV_DM_DMSTATUS_IMPEBREAK_BITS _u(0x00400000) +#define RISCV_DM_DMSTATUS_IMPEBREAK_MSB _u(22) +#define RISCV_DM_DMSTATUS_IMPEBREAK_LSB _u(22) +#define RISCV_DM_DMSTATUS_IMPEBREAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLHAVERESET +// Description : This field is 1 when all currently selected harts have been +// reset and reset has not been acknowledged for any of them. +#define RISCV_DM_DMSTATUS_ALLHAVERESET_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_BITS _u(0x00080000) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_MSB _u(19) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_LSB _u(19) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYHAVERESET +// Description : This field is 1 when at least one currently selected hart has +// been reset and reset has not been acknowledged for that hart. +#define RISCV_DM_DMSTATUS_ANYHAVERESET_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_BITS _u(0x00040000) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_MSB _u(18) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_LSB _u(18) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLRESUMEACK +// Description : This field is 1 when all currently selected harts have +// acknowledged their last resume request. +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_BITS _u(0x00020000) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_MSB _u(17) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_LSB _u(17) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYRESUMEACK +// Description : This field is 1 when any currently selected hart has +// acknowledged its last resume request. +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_BITS _u(0x00010000) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_MSB _u(16) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_LSB _u(16) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLNONEXISTENT +// Description : This field is 1 when all currently selected harts do not exist +// on this platform. +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_RESET "-" +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_BITS _u(0x00008000) +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_MSB _u(15) +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_LSB _u(15) +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYNONEXISTENT +// Description : This field is 1 when any currently selected hart does not exist +// in this platform. +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_RESET "-" +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_BITS _u(0x00004000) +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_MSB _u(14) +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_LSB _u(14) +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLUNAVAIL +// Description : This field is 1 when all currently selected harts are +// unavailable. +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_RESET "-" +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_BITS _u(0x00002000) +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_MSB _u(13) +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_LSB _u(13) +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYUNAVAIL +// Description : This field is 1 when any currently selected hart is +// unavailable. +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_RESET "-" +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_BITS _u(0x00001000) +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_MSB _u(12) +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_LSB _u(12) +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLRUNNING +// Description : This field is 1 when all currently selected harts are running. +#define RISCV_DM_DMSTATUS_ALLRUNNING_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLRUNNING_BITS _u(0x00000800) +#define RISCV_DM_DMSTATUS_ALLRUNNING_MSB _u(11) +#define RISCV_DM_DMSTATUS_ALLRUNNING_LSB _u(11) +#define RISCV_DM_DMSTATUS_ALLRUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYRUNNING +// Description : This field is 1 when any currently selected hart is running. +#define RISCV_DM_DMSTATUS_ANYRUNNING_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYRUNNING_BITS _u(0x00000400) +#define RISCV_DM_DMSTATUS_ANYRUNNING_MSB _u(10) +#define RISCV_DM_DMSTATUS_ANYRUNNING_LSB _u(10) +#define RISCV_DM_DMSTATUS_ANYRUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLHALTED +// Description : This field is 1 when all currently selected harts are halted. +#define RISCV_DM_DMSTATUS_ALLHALTED_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLHALTED_BITS _u(0x00000200) +#define RISCV_DM_DMSTATUS_ALLHALTED_MSB _u(9) +#define RISCV_DM_DMSTATUS_ALLHALTED_LSB _u(9) +#define RISCV_DM_DMSTATUS_ALLHALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYHALTED +// Description : This field is 1 when any currently selected hart is halted. +#define RISCV_DM_DMSTATUS_ANYHALTED_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYHALTED_BITS _u(0x00000100) +#define RISCV_DM_DMSTATUS_ANYHALTED_MSB _u(8) +#define RISCV_DM_DMSTATUS_ANYHALTED_LSB _u(8) +#define RISCV_DM_DMSTATUS_ANYHALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_AUTHENTICATED +// Description : 0: Authentication is required before using the DM. +// +// 1: The authentication check has passed. +// +// On components that don’t implement authentication, this bit +// must be preset as 1. (Note: the version of Hazard3 on RP2350 +// does not implement authentication.) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_RESET _u(0x1) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_BITS _u(0x00000080) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_MSB _u(7) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_LSB _u(7) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_AUTHBUSY +// Description : 0: The authentication module is ready to process the next +// read/write to authdata. +// +// 1: The authentication module is busy. Accessing authdata +// results in unspecified behavior. authbusy only becomes set in +// immediate response to an access to authdata. +#define RISCV_DM_DMSTATUS_AUTHBUSY_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_AUTHBUSY_BITS _u(0x00000040) +#define RISCV_DM_DMSTATUS_AUTHBUSY_MSB _u(6) +#define RISCV_DM_DMSTATUS_AUTHBUSY_LSB _u(6) +#define RISCV_DM_DMSTATUS_AUTHBUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_HASRESETHALTREQ +// Description : 1 if this Debug Module supports halt-on-reset functionality +// controllable by the setresethaltreq and clrresethaltreq bits. 0 +// otherwise. +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_RESET _u(0x1) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_BITS _u(0x00000020) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_MSB _u(5) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_LSB _u(5) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_CONFSTPTRVALID +// Description : 0: confstrptr0–confstrptr3 hold information which is not +// relevant to the configuration string. +// +// 1: confstrptr0–confstrptr3 hold the address of the +// configuration string. +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_BITS _u(0x00000010) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_MSB _u(4) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_LSB _u(4) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_VERSION +// Description : 0: There is no Debug Module present. 1: There is a Debug Module +// and it conforms to version 0.11 of the RISC-V debug +// specification. +// +// 2: There is a Debug Module and it conforms to version 0.13 of +// the RISC-V debug specification. +// +// 15: There is a Debug Module but it does not con- form to any +// available version of the RISC-V debug spec. +#define RISCV_DM_DMSTATUS_VERSION_RESET _u(0x2) +#define RISCV_DM_DMSTATUS_VERSION_BITS _u(0x0000000f) +#define RISCV_DM_DMSTATUS_VERSION_MSB _u(3) +#define RISCV_DM_DMSTATUS_VERSION_LSB _u(0) +#define RISCV_DM_DMSTATUS_VERSION_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_HARTINFO +// Description : This register gives information about the hart currently +// selected by hartsel. +// +// This entire register is read-only. +#define RISCV_DM_HARTINFO_OFFSET _u(0x00000048) +#define RISCV_DM_HARTINFO_BITS _u(0x00f1ffff) +#define RISCV_DM_HARTINFO_RESET _u(0x00001bff) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_NSCRATCH +// Description : Number of dscratch registers available for the debugger to use +// during program buffer execution, starting from dscratch0. The +// debugger can make no assumptions about the contents of these +// registers between commands. +#define RISCV_DM_HARTINFO_NSCRATCH_RESET _u(0x0) +#define RISCV_DM_HARTINFO_NSCRATCH_BITS _u(0x00f00000) +#define RISCV_DM_HARTINFO_NSCRATCH_MSB _u(23) +#define RISCV_DM_HARTINFO_NSCRATCH_LSB _u(20) +#define RISCV_DM_HARTINFO_NSCRATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_DATAACCESS +// Description : 0: The data registers are shadowed in the hart by CSRs. Each +// CSR is DXLEN bits in size, and corresponds to a single +// argument. +// +// 1: The data registers are shadowed in the hart’s memory map. +// Each register takes up 4 bytes in the memory map. +#define RISCV_DM_HARTINFO_DATAACCESS_RESET _u(0x0) +#define RISCV_DM_HARTINFO_DATAACCESS_BITS _u(0x00010000) +#define RISCV_DM_HARTINFO_DATAACCESS_MSB _u(16) +#define RISCV_DM_HARTINFO_DATAACCESS_LSB _u(16) +#define RISCV_DM_HARTINFO_DATAACCESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_DATASIZE +// Description : If dataaccess is 0: Number of CSRs dedicated to shadowing the +// data registers. +// +// If dataaccess is 1: Number of 32-bit words in the memory map +// dedicated to shadowing the data registers. +#define RISCV_DM_HARTINFO_DATASIZE_RESET _u(0x1) +#define RISCV_DM_HARTINFO_DATASIZE_BITS _u(0x0000f000) +#define RISCV_DM_HARTINFO_DATASIZE_MSB _u(15) +#define RISCV_DM_HARTINFO_DATASIZE_LSB _u(12) +#define RISCV_DM_HARTINFO_DATASIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_DATAADDR +// Description : If dataaccess is 0: The number of the first CSR dedicated to +// shadowing the data registers. +// +// If dataaccess is 1: Signed address of RAM where the data +// registers are shadowed, to be used to access relative to zero +// +// On Hazard3 this indicates the single data register mapped as +// dmdata0. There is actually only a single shared register, +// internal to the Debug Module, and mirrored in each core's CSR +// space. +#define RISCV_DM_HARTINFO_DATAADDR_RESET _u(0xbff) +#define RISCV_DM_HARTINFO_DATAADDR_BITS _u(0x00000fff) +#define RISCV_DM_HARTINFO_DATAADDR_MSB _u(11) +#define RISCV_DM_HARTINFO_DATAADDR_LSB _u(0) +#define RISCV_DM_HARTINFO_DATAADDR_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_HALTSUM1 +// Description : Each bit in this read-only register indicates whether any of a +// group of harts is halted or not. Unavailable/nonexistent harts +// are not considered to be halted. +// +// Each bit in haltsum1 is an OR reduction of 32 bits' worth of +// haltsum0. On RP2350, only the LSB is implemented. +#define RISCV_DM_HALTSUM1_OFFSET _u(0x0000004c) +#define RISCV_DM_HALTSUM1_BITS _u(0x00000001) +#define RISCV_DM_HALTSUM1_RESET _u(0x00000000) +#define RISCV_DM_HALTSUM1_MSB _u(0) +#define RISCV_DM_HALTSUM1_LSB _u(0) +#define RISCV_DM_HALTSUM1_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_HAWINDOWSEL +// Description : This register selects which of the 32-bit portion of the hart +// array mask register is accessible in hawindow. +#define RISCV_DM_HAWINDOWSEL_OFFSET _u(0x00000050) +#define RISCV_DM_HAWINDOWSEL_BITS _u(0x00007fff) +#define RISCV_DM_HAWINDOWSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HAWINDOWSEL_HAWINDOWSEL +// Description : On Hazard3 this register is entirely hardwired to 0. +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_RESET _u(0x0000) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_BITS _u(0x00007fff) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_MSB _u(14) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_LSB _u(0) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_HAWINDOW +// Description : This register provides R/W access to a 32-bit portion of the +// hart array mask register. The position of the window is +// determined by hawindowsel. I.e. bit 0 refers to hart +// hawindowsel ∗ 32, while bit 31 refers to hart hawindowsel ∗ 32 +// + 31. +// +// On RP2350 only the two least-significant bits of this register +// are implemented, since there are only two cores. This is still +// useful to run/halt/reset both cores exactly simultaneously. +#define RISCV_DM_HAWINDOW_OFFSET _u(0x00000054) +#define RISCV_DM_HAWINDOW_BITS _u(0x00000003) +#define RISCV_DM_HAWINDOW_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HAWINDOW_MASKDATA +#define RISCV_DM_HAWINDOW_MASKDATA_RESET _u(0x0) +#define RISCV_DM_HAWINDOW_MASKDATA_BITS _u(0x00000003) +#define RISCV_DM_HAWINDOW_MASKDATA_MSB _u(1) +#define RISCV_DM_HAWINDOW_MASKDATA_LSB _u(0) +#define RISCV_DM_HAWINDOW_MASKDATA_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_ABSTRACTS +// Description : Abstract Control and Status. Writing this register while an +// abstract command is executing causes cmderr to be set to 1 +// (busy) if it is 0. +#define RISCV_DM_ABSTRACTS_OFFSET _u(0x00000058) +#define RISCV_DM_ABSTRACTS_BITS _u(0x1f00170f) +#define RISCV_DM_ABSTRACTS_RESET _u(0x02000001) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_PROGBUFSIZE +// Description : Size of the Program Buffer, in 32-bit words. +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_RESET _u(0x02) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_BITS _u(0x1f000000) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_MSB _u(28) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_LSB _u(24) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_BUSY +// Description : 1: An abstract command is currently being executed. +// +// This bit is set as soon as command is written, and is not +// cleared until that command has completed. +#define RISCV_DM_ABSTRACTS_BUSY_RESET _u(0x0) +#define RISCV_DM_ABSTRACTS_BUSY_BITS _u(0x00001000) +#define RISCV_DM_ABSTRACTS_BUSY_MSB _u(12) +#define RISCV_DM_ABSTRACTS_BUSY_LSB _u(12) +#define RISCV_DM_ABSTRACTS_BUSY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_CMDERR +// Description : Gets set if an abstract command fails. The bits in this field +// remain set until they are cleared by writing 1 to them. No +// abstract command is started until the value is reset to 0. +// +// This field only contains a valid value if busy is 0. +// +// 0 (none): No error. +// +// 1 (busy): An abstract command was executing while command, +// abstractcs, or abstractauto was written, or when one of the +// data or progbuf registers was read or written. This status is +// only written if cmderr contains 0. +// +// 2 (not supported): The requested command is not supported, +// regardless of whether the hart is running or not. +// +// 3 (exception): An exception occurred while executing the +// command (e.g. while executing the Program Buffer). +// +// 4 (halt/resume): The abstract command couldn’t execute because +// the hart wasn’t in the required state (running/halted), or +// unavailable. +// +// 5 (bus): The abstract command failed due to a bus error (e.g. +// alignment, access size, or timeout). +// +// 7 (other): The command failed for another reason. +// +// Note: Hazard3 does not set values 5 or 7. Load/store +// instructions in the program buffer raise an exception when they +// encounter a bus fault, setting cmderr=3. +#define RISCV_DM_ABSTRACTS_CMDERR_RESET _u(0x0) +#define RISCV_DM_ABSTRACTS_CMDERR_BITS _u(0x00000700) +#define RISCV_DM_ABSTRACTS_CMDERR_MSB _u(10) +#define RISCV_DM_ABSTRACTS_CMDERR_LSB _u(8) +#define RISCV_DM_ABSTRACTS_CMDERR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_DATACOUNT +// Description : Number of data registers that are implemented as part of the +// abstract command interface. +#define RISCV_DM_ABSTRACTS_DATACOUNT_RESET _u(0x1) +#define RISCV_DM_ABSTRACTS_DATACOUNT_BITS _u(0x0000000f) +#define RISCV_DM_ABSTRACTS_DATACOUNT_MSB _u(3) +#define RISCV_DM_ABSTRACTS_DATACOUNT_LSB _u(0) +#define RISCV_DM_ABSTRACTS_DATACOUNT_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_COMMAND +// Description : Writes to this register cause the corresponding abstract +// command to be executed. +// +// Writing this register while an abstract command is executing +// causes cmderr to be set to 1 (busy) if it is 0. +// +// If cmderr is non-zero, writes to this register are ignored. +#define RISCV_DM_COMMAND_OFFSET _u(0x0000005c) +#define RISCV_DM_COMMAND_BITS _u(0xff7fffff) +#define RISCV_DM_COMMAND_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_CMDTYPE +// Description : On Hazard3 this field must be 0 (Access Register) +#define RISCV_DM_COMMAND_CMDTYPE_RESET _u(0x00) +#define RISCV_DM_COMMAND_CMDTYPE_BITS _u(0xff000000) +#define RISCV_DM_COMMAND_CMDTYPE_MSB _u(31) +#define RISCV_DM_COMMAND_CMDTYPE_LSB _u(24) +#define RISCV_DM_COMMAND_CMDTYPE_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_AARSIZE +// Description : On Hazard3 this field must be 2 (32-bit register access) +#define RISCV_DM_COMMAND_AARSIZE_RESET _u(0x0) +#define RISCV_DM_COMMAND_AARSIZE_BITS _u(0x00700000) +#define RISCV_DM_COMMAND_AARSIZE_MSB _u(22) +#define RISCV_DM_COMMAND_AARSIZE_LSB _u(20) +#define RISCV_DM_COMMAND_AARSIZE_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_AARPOSTINCREMENT +// Description : On Hazard3 this field must be 0 (no post-increment of regno) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_RESET _u(0x0) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_BITS _u(0x00080000) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_MSB _u(19) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_LSB _u(19) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_POSTEXEC +// Description : 0: No effect. +// +// 1: Execute the program in the Program Buffer exactly once after +// performing the transfer, if any. +#define RISCV_DM_COMMAND_POSTEXEC_RESET _u(0x0) +#define RISCV_DM_COMMAND_POSTEXEC_BITS _u(0x00040000) +#define RISCV_DM_COMMAND_POSTEXEC_MSB _u(18) +#define RISCV_DM_COMMAND_POSTEXEC_LSB _u(18) +#define RISCV_DM_COMMAND_POSTEXEC_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_TRANSFER +// Description : 0: Don’t do the operation specified by write. +// +// 1: Do the operation specified by write. +// +// This bit can be used to just execute the Program Buffer without +// having to worry about placing valid values into aarsize or +// regno. +#define RISCV_DM_COMMAND_TRANSFER_RESET _u(0x0) +#define RISCV_DM_COMMAND_TRANSFER_BITS _u(0x00020000) +#define RISCV_DM_COMMAND_TRANSFER_MSB _u(17) +#define RISCV_DM_COMMAND_TRANSFER_LSB _u(17) +#define RISCV_DM_COMMAND_TRANSFER_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_WRITE +// Description : When transfer is set: +// +// 0: Copy data from the specified register into data0. +// +// 1: Copy data from data0 into the specified register. +#define RISCV_DM_COMMAND_WRITE_RESET _u(0x0) +#define RISCV_DM_COMMAND_WRITE_BITS _u(0x00010000) +#define RISCV_DM_COMMAND_WRITE_MSB _u(16) +#define RISCV_DM_COMMAND_WRITE_LSB _u(16) +#define RISCV_DM_COMMAND_WRITE_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_REGNO +// Description : Number of the register to access. +// +// On Hazard3 this must be in the range 0x1000 through 0x101f +// inclusive, referring to GPRs x0 through x31. +#define RISCV_DM_COMMAND_REGNO_RESET _u(0x0000) +#define RISCV_DM_COMMAND_REGNO_BITS _u(0x0000ffff) +#define RISCV_DM_COMMAND_REGNO_MSB _u(15) +#define RISCV_DM_COMMAND_REGNO_LSB _u(0) +#define RISCV_DM_COMMAND_REGNO_ACCESS "WO" +// ============================================================================= +// Register : RISCV_DM_ABSTRACTAUTO +// Description : Abstract Command Autoexec. Writing this register while an +// abstract command is executing causes cmderr to be set to 1 +// (busy) if it is 0. +#define RISCV_DM_ABSTRACTAUTO_OFFSET _u(0x00000060) +#define RISCV_DM_ABSTRACTAUTO_BITS _u(0xffff8fff) +#define RISCV_DM_ABSTRACTAUTO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF +// Description : When a bit in this field is 1, read or write accesses to the +// corresponding progbuf word cause the command in command to be +// executed again. +// +// Hazard3 implements only the two least-significant bits of this +// field (for the two-entry progbuf) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_RESET _u(0x00000) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_BITS _u(0xffff8000) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_MSB _u(31) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LSB _u(15) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA +// Description : When a bit in this field is 1, read or write accesses to the +// corresponding data word cause the command in command to be +// executed again. +// +// Hazard3 implements only the least-significant bit of this +// field. +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_RESET _u(0x000) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_BITS _u(0x00000fff) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_MSB _u(11) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_LSB _u(0) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_NEXTDM +// Description : If there is more than one DM accessible on this DMI, this +// register contains the base address of thenext one in the chain, +// or 0 if this is the last one in the chain. +#define RISCV_DM_NEXTDM_OFFSET _u(0x00000074) +#define RISCV_DM_NEXTDM_BITS _u(0xffffffff) +#define RISCV_DM_NEXTDM_RESET _u(0x00000000) +#define RISCV_DM_NEXTDM_MSB _u(31) +#define RISCV_DM_NEXTDM_LSB _u(0) +#define RISCV_DM_NEXTDM_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_PROGBUF0 +// Description : progbuf0 through progbuf15 provide read/write access to the +// program buffer. abstractcs.progbufsize indicates how many of +// them are implemented starting at progbuf0, counting up. +// +// (Hazard3 implements a 2-word program buffer.) +#define RISCV_DM_PROGBUF0_OFFSET _u(0x00000080) +#define RISCV_DM_PROGBUF0_BITS _u(0xffffffff) +#define RISCV_DM_PROGBUF0_RESET _u(0x00000000) +#define RISCV_DM_PROGBUF0_MSB _u(31) +#define RISCV_DM_PROGBUF0_LSB _u(0) +#define RISCV_DM_PROGBUF0_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_PROGBUF1 +// Description : progbuf0 through progbuf15 provide read/write access to the +// program buffer. abstractcs.progbufsize indicates how many of +// them are implemented starting at progbuf0, counting up. +// +// (Hazard3 implements a 2-word program buffer.) +#define RISCV_DM_PROGBUF1_OFFSET _u(0x00000084) +#define RISCV_DM_PROGBUF1_BITS _u(0xffffffff) +#define RISCV_DM_PROGBUF1_RESET _u(0x00000000) +#define RISCV_DM_PROGBUF1_MSB _u(31) +#define RISCV_DM_PROGBUF1_LSB _u(0) +#define RISCV_DM_PROGBUF1_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_SBCS +// Description : System Bus Access Control and Status +#define RISCV_DM_SBCS_OFFSET _u(0x000000e0) +#define RISCV_DM_SBCS_BITS _u(0xe07fffff) +#define RISCV_DM_SBCS_RESET _u(0x20000407) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBVERSION +// Description : 1: The System Bus interface conforms to version 0.13.2 of the +// RISC-V debug spec. +#define RISCV_DM_SBCS_SBVERSION_RESET _u(0x1) +#define RISCV_DM_SBCS_SBVERSION_BITS _u(0xe0000000) +#define RISCV_DM_SBCS_SBVERSION_MSB _u(31) +#define RISCV_DM_SBCS_SBVERSION_LSB _u(29) +#define RISCV_DM_SBCS_SBVERSION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBBUSYERROR +// Description : Set when the debugger attempts to read data while a read is in +// progress, or when the debugger initiates a new access while one +// is already in progress (while sbbusy is set). It remains set +// until it’s explicitly cleared by the debugger. +// +// While this field is set, no more system bus accesses can be +// initiated by the Debug Module. +#define RISCV_DM_SBCS_SBBUSYERROR_RESET _u(0x0) +#define RISCV_DM_SBCS_SBBUSYERROR_BITS _u(0x00400000) +#define RISCV_DM_SBCS_SBBUSYERROR_MSB _u(22) +#define RISCV_DM_SBCS_SBBUSYERROR_LSB _u(22) +#define RISCV_DM_SBCS_SBBUSYERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBBUSY +// Description : When 1, indicates the system bus master is busy. (Whether the +// system bus itself is busy is related, but not the same thing.) +// This bit goes high immediately when a read or write is +// requested for any reason, and does not go low until the access +// is fully completed. +// +// Writes to sbcs while sbbusy is high result in undefined +// behavior. A debugger must not write to sbcs until it reads +// sbbusy as 0. +#define RISCV_DM_SBCS_SBBUSY_RESET _u(0x0) +#define RISCV_DM_SBCS_SBBUSY_BITS _u(0x00200000) +#define RISCV_DM_SBCS_SBBUSY_MSB _u(21) +#define RISCV_DM_SBCS_SBBUSY_LSB _u(21) +#define RISCV_DM_SBCS_SBBUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBREADONADDR +// Description : When 1, every write to sbaddress0 automatically triggers a +// system bus read at the new address. +#define RISCV_DM_SBCS_SBREADONADDR_RESET _u(0x0) +#define RISCV_DM_SBCS_SBREADONADDR_BITS _u(0x00100000) +#define RISCV_DM_SBCS_SBREADONADDR_MSB _u(20) +#define RISCV_DM_SBCS_SBREADONADDR_LSB _u(20) +#define RISCV_DM_SBCS_SBREADONADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS +// Description : Select the access size to use for system bus accesses. +// +// 0: 8-bit +// +// 1: 16-bit +// +// 2: 32-bit +// +// 3: 64-bit +// +// 4: 128-bit +// +// If sbaccess has an unsupported value when the DM starts a bus +// access, the access is not per formed and sberror is set to 4. +// (On Hazard3 the supported values are 8-bit, 16-bit and 32-bit.) +#define RISCV_DM_SBCS_SBACCESS_RESET _u(0x0) +#define RISCV_DM_SBCS_SBACCESS_BITS _u(0x000e0000) +#define RISCV_DM_SBCS_SBACCESS_MSB _u(19) +#define RISCV_DM_SBCS_SBACCESS_LSB _u(17) +#define RISCV_DM_SBCS_SBACCESS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBAUTOINCREMENT +// Description : When 1, sbaddress is incremented by the access size (in bytes) +// selected in sbaccess after every system bus access. +#define RISCV_DM_SBCS_SBAUTOINCREMENT_RESET _u(0x0) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_BITS _u(0x00010000) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_MSB _u(16) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_LSB _u(16) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBREADONDATA +// Description : When 1, every read from sbdata0 automatically triggers a system +// bus read at the (possibly auto- incremented) address. +#define RISCV_DM_SBCS_SBREADONDATA_RESET _u(0x0) +#define RISCV_DM_SBCS_SBREADONDATA_BITS _u(0x00008000) +#define RISCV_DM_SBCS_SBREADONDATA_MSB _u(15) +#define RISCV_DM_SBCS_SBREADONDATA_LSB _u(15) +#define RISCV_DM_SBCS_SBREADONDATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBERROR +// Description : When the Debug Module’s system bus master encounters an error, +// this field gets set. The bits in this field remain set until +// they are cleared by writing 1 to them. While this field is non- +// zero, no more system bus accesses can be initiated by the Debug +// Module. +// +// An implementation may report “Other” (7) for any error +// condition. (Hazard3 does not use this value for any errors.) +// +// 0: There was no bus error. +// +// 1: There was a timeout. +// +// 2: A bad address was accessed. +// +// 3: There was an alignment error. +// +// 4: An access of unsupported size was requested. +// +// 7: Other. +// +// Hazard3 raises an alignment error for any non-naturally-aligned +// bus transfer which would otherwise be a valid transfer. +#define RISCV_DM_SBCS_SBERROR_RESET _u(0x0) +#define RISCV_DM_SBCS_SBERROR_BITS _u(0x00007000) +#define RISCV_DM_SBCS_SBERROR_MSB _u(14) +#define RISCV_DM_SBCS_SBERROR_LSB _u(12) +#define RISCV_DM_SBCS_SBERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBASIZE +// Description : Width of system bus addresses in bits. (0 indicates there is no +// bus access support.) +#define RISCV_DM_SBCS_SBASIZE_RESET _u(0x20) +#define RISCV_DM_SBCS_SBASIZE_BITS _u(0x00000fe0) +#define RISCV_DM_SBCS_SBASIZE_MSB _u(11) +#define RISCV_DM_SBCS_SBASIZE_LSB _u(5) +#define RISCV_DM_SBCS_SBASIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS128 +// Description : 1 when 128-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS128_RESET _u(0x0) +#define RISCV_DM_SBCS_SBACCESS128_BITS _u(0x00000010) +#define RISCV_DM_SBCS_SBACCESS128_MSB _u(4) +#define RISCV_DM_SBCS_SBACCESS128_LSB _u(4) +#define RISCV_DM_SBCS_SBACCESS128_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS64 +// Description : 1 when 64-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS64_RESET _u(0x0) +#define RISCV_DM_SBCS_SBACCESS64_BITS _u(0x00000008) +#define RISCV_DM_SBCS_SBACCESS64_MSB _u(3) +#define RISCV_DM_SBCS_SBACCESS64_LSB _u(3) +#define RISCV_DM_SBCS_SBACCESS64_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS32 +// Description : 1 when 32-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS32_RESET _u(0x1) +#define RISCV_DM_SBCS_SBACCESS32_BITS _u(0x00000004) +#define RISCV_DM_SBCS_SBACCESS32_MSB _u(2) +#define RISCV_DM_SBCS_SBACCESS32_LSB _u(2) +#define RISCV_DM_SBCS_SBACCESS32_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS16 +// Description : 1 when 16-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS16_RESET _u(0x1) +#define RISCV_DM_SBCS_SBACCESS16_BITS _u(0x00000002) +#define RISCV_DM_SBCS_SBACCESS16_MSB _u(1) +#define RISCV_DM_SBCS_SBACCESS16_LSB _u(1) +#define RISCV_DM_SBCS_SBACCESS16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS8 +// Description : 1 when 8-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS8_RESET _u(0x1) +#define RISCV_DM_SBCS_SBACCESS8_BITS _u(0x00000001) +#define RISCV_DM_SBCS_SBACCESS8_MSB _u(0) +#define RISCV_DM_SBCS_SBACCESS8_LSB _u(0) +#define RISCV_DM_SBCS_SBACCESS8_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_SBADDRESS0 +// Description : System Bus Address 31:0 +// +// When the system bus master is busy, writes to this register +// will set sbbusyerror and don’t do anything else. +// +// If sberror is 0, sbbusyerror is 0, and sbreadonaddr is set then +// writes to this register start the following: +// +// 1. Set sbbusy. +// +// 2. Perform a bus read from the new value of sbaddress. +// +// 3. If the read succeeded and sbautoincrement is set, increment +// sbaddress. +// +// 4. Clear sbbusy. +#define RISCV_DM_SBADDRESS0_OFFSET _u(0x000000e4) +#define RISCV_DM_SBADDRESS0_BITS _u(0xffffffff) +#define RISCV_DM_SBADDRESS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBADDRESS0_ADDRESS +// Description : Accesses bits 31:0 of the physical address in sbaddress. +#define RISCV_DM_SBADDRESS0_ADDRESS_RESET _u(0x00000000) +#define RISCV_DM_SBADDRESS0_ADDRESS_BITS _u(0xffffffff) +#define RISCV_DM_SBADDRESS0_ADDRESS_MSB _u(31) +#define RISCV_DM_SBADDRESS0_ADDRESS_LSB _u(0) +#define RISCV_DM_SBADDRESS0_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_SBDATA0 +// Description : System Bus Data 31:0 +// +// Any successful system bus read updates sbdata. If the width of +// the read access is less than the width of sbdata, the contents +// of the remaining high bits may take on any value. +// +// If sberror or sbbusyerror both aren’t 0 then accesses do +// nothing. +// +// If the bus master is busy then accesses set sbbusyerror, and +// don’t do anything else. Writes to this register start the +// following: +// +// 1. Set sbbusy. +// +// 2. Perform a bus write of the new value of sbdata to sbaddress. +// +// 3. If the write succeeded and sbautoincrement is set, increment +// sbaddress. +// +// 4. Clear sbbusy. +// +// Reads from this register start the following: +// +// 1. “Return” the data. +// +// 2. Set sbbusy. +// +// 3. If sbreadondata is set, perform a system bus read from the +// address contained in sbaddress, placing the result in sbdata. +// +// 4. If the read was successful, and sbautoincrement is set, +// increment sbaddress. +// +// 5. Clear sbbusy. +#define RISCV_DM_SBDATA0_OFFSET _u(0x000000f0) +#define RISCV_DM_SBDATA0_BITS _u(0xffffffff) +#define RISCV_DM_SBDATA0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBDATA0_DATA +#define RISCV_DM_SBDATA0_DATA_RESET _u(0x00000000) +#define RISCV_DM_SBDATA0_DATA_BITS _u(0xffffffff) +#define RISCV_DM_SBDATA0_DATA_MSB _u(31) +#define RISCV_DM_SBDATA0_DATA_LSB _u(0) +#define RISCV_DM_SBDATA0_DATA_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_HALTSUM0 +// Description : Each bit in this read-only register indicates whether one +// specific hart is halted or not. Unavailable/nonexistent harts +// are not considered to be halted. +// +// On RP2350, only the two LSBs of this register are implemented, +// one for each core/hart. +// +// This entire register is read-only. +#define RISCV_DM_HALTSUM0_OFFSET _u(0x00000100) +#define RISCV_DM_HALTSUM0_BITS _u(0xffffffff) +#define RISCV_DM_HALTSUM0_RESET _u(0x00000000) +#define RISCV_DM_HALTSUM0_MSB _u(31) +#define RISCV_DM_HALTSUM0_LSB _u(0) +#define RISCV_DM_HALTSUM0_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RISCV_DM_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/rosc.h b/src/rp2350/hardware_regs/include/hardware/regs/rosc.h new file mode 100644 index 000000000..4865c2ee3 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/rosc.h @@ -0,0 +1,345 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ROSC +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_ROSC_H +#define _HARDWARE_REGS_ROSC_H +// ============================================================================= +// Register : ROSC_CTRL +// Description : Ring Oscillator control +#define ROSC_CTRL_OFFSET _u(0x00000000) +#define ROSC_CTRL_BITS _u(0x00ffffff) +#define ROSC_CTRL_RESET _u(0x00000aa0) +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_ENABLE +// Description : On power-up this field is initialised to ENABLE +// The system clock must be switched to another source before +// setting this field to DISABLE otherwise the chip will lock up +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will enable the +// oscillator. +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define ROSC_CTRL_ENABLE_RESET "-" +#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define ROSC_CTRL_ENABLE_MSB _u(23) +#define ROSC_CTRL_ENABLE_LSB _u(12) +#define ROSC_CTRL_ENABLE_ACCESS "RW" +#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_FREQ_RANGE +// Description : Controls the number of delay stages in the ROSC ring +// LOW uses stages 0 to 7 +// MEDIUM uses stages 2 to 7 +// HIGH uses stages 4 to 7 +// TOOHIGH uses stages 6 to 7 and should not be used because its +// frequency exceeds design specifications +// The clock output will not glitch when changing the range up one +// step at a time +// The clock output will glitch when changing the range down +// Note: the values here are gray coded which is why HIGH comes +// before TOOHIGH +// 0xfa4 -> LOW +// 0xfa5 -> MEDIUM +// 0xfa7 -> HIGH +// 0xfa6 -> TOOHIGH +#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) +#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) +#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) +#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) +#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) +// ============================================================================= +// Register : ROSC_FREQA +// Description : The FREQA & FREQB registers control the frequency by +// controlling the drive strength of each stage +// The drive strength has 4 levels determined by the number of +// bits set +// Increasing the number of bits set increases the drive strength +// and increases the oscillation frequency +// 0 bits set is the default drive strength +// 1 bit set doubles the drive strength +// 2 bits set triples drive strength +// 3 bits set quadruples drive strength +// For frequency randomisation set both DS0_RANDOM=1 & +// DS1_RANDOM=1 +#define ROSC_FREQA_OFFSET _u(0x00000004) +#define ROSC_FREQA_BITS _u(0xffff77ff) +#define ROSC_FREQA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQA_PASSWD_RESET _u(0x0000) +#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQA_PASSWD_MSB _u(31) +#define ROSC_FREQA_PASSWD_LSB _u(16) +#define ROSC_FREQA_PASSWD_ACCESS "RW" +#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS3 +// Description : Stage 3 drive strength +#define ROSC_FREQA_DS3_RESET _u(0x0) +#define ROSC_FREQA_DS3_BITS _u(0x00007000) +#define ROSC_FREQA_DS3_MSB _u(14) +#define ROSC_FREQA_DS3_LSB _u(12) +#define ROSC_FREQA_DS3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS2 +// Description : Stage 2 drive strength +#define ROSC_FREQA_DS2_RESET _u(0x0) +#define ROSC_FREQA_DS2_BITS _u(0x00000700) +#define ROSC_FREQA_DS2_MSB _u(10) +#define ROSC_FREQA_DS2_LSB _u(8) +#define ROSC_FREQA_DS2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS1_RANDOM +// Description : Randomises the stage 1 drive strength +#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x0) +#define ROSC_FREQA_DS1_RANDOM_BITS _u(0x00000080) +#define ROSC_FREQA_DS1_RANDOM_MSB _u(7) +#define ROSC_FREQA_DS1_RANDOM_LSB _u(7) +#define ROSC_FREQA_DS1_RANDOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS1 +// Description : Stage 1 drive strength +#define ROSC_FREQA_DS1_RESET _u(0x0) +#define ROSC_FREQA_DS1_BITS _u(0x00000070) +#define ROSC_FREQA_DS1_MSB _u(6) +#define ROSC_FREQA_DS1_LSB _u(4) +#define ROSC_FREQA_DS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS0_RANDOM +// Description : Randomises the stage 0 drive strength +#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x0) +#define ROSC_FREQA_DS0_RANDOM_BITS _u(0x00000008) +#define ROSC_FREQA_DS0_RANDOM_MSB _u(3) +#define ROSC_FREQA_DS0_RANDOM_LSB _u(3) +#define ROSC_FREQA_DS0_RANDOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS0 +// Description : Stage 0 drive strength +#define ROSC_FREQA_DS0_RESET _u(0x0) +#define ROSC_FREQA_DS0_BITS _u(0x00000007) +#define ROSC_FREQA_DS0_MSB _u(2) +#define ROSC_FREQA_DS0_LSB _u(0) +#define ROSC_FREQA_DS0_ACCESS "RW" +// ============================================================================= +// Register : ROSC_FREQB +// Description : For a detailed description see freqa register +#define ROSC_FREQB_OFFSET _u(0x00000008) +#define ROSC_FREQB_BITS _u(0xffff7777) +#define ROSC_FREQB_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQB_PASSWD_RESET _u(0x0000) +#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQB_PASSWD_MSB _u(31) +#define ROSC_FREQB_PASSWD_LSB _u(16) +#define ROSC_FREQB_PASSWD_ACCESS "RW" +#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS7 +// Description : Stage 7 drive strength +#define ROSC_FREQB_DS7_RESET _u(0x0) +#define ROSC_FREQB_DS7_BITS _u(0x00007000) +#define ROSC_FREQB_DS7_MSB _u(14) +#define ROSC_FREQB_DS7_LSB _u(12) +#define ROSC_FREQB_DS7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS6 +// Description : Stage 6 drive strength +#define ROSC_FREQB_DS6_RESET _u(0x0) +#define ROSC_FREQB_DS6_BITS _u(0x00000700) +#define ROSC_FREQB_DS6_MSB _u(10) +#define ROSC_FREQB_DS6_LSB _u(8) +#define ROSC_FREQB_DS6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS5 +// Description : Stage 5 drive strength +#define ROSC_FREQB_DS5_RESET _u(0x0) +#define ROSC_FREQB_DS5_BITS _u(0x00000070) +#define ROSC_FREQB_DS5_MSB _u(6) +#define ROSC_FREQB_DS5_LSB _u(4) +#define ROSC_FREQB_DS5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS4 +// Description : Stage 4 drive strength +#define ROSC_FREQB_DS4_RESET _u(0x0) +#define ROSC_FREQB_DS4_BITS _u(0x00000007) +#define ROSC_FREQB_DS4_MSB _u(2) +#define ROSC_FREQB_DS4_LSB _u(0) +#define ROSC_FREQB_DS4_ACCESS "RW" +// ============================================================================= +// Register : ROSC_RANDOM +// Description : Loads a value to the LFSR randomiser +#define ROSC_RANDOM_OFFSET _u(0x0000000c) +#define ROSC_RANDOM_BITS _u(0xffffffff) +#define ROSC_RANDOM_RESET _u(0x3f04b16d) +// ----------------------------------------------------------------------------- +// Field : ROSC_RANDOM_SEED +#define ROSC_RANDOM_SEED_RESET _u(0x3f04b16d) +#define ROSC_RANDOM_SEED_BITS _u(0xffffffff) +#define ROSC_RANDOM_SEED_MSB _u(31) +#define ROSC_RANDOM_SEED_LSB _u(0) +#define ROSC_RANDOM_SEED_ACCESS "RW" +// ============================================================================= +// Register : ROSC_DORMANT +// Description : Ring Oscillator pause control +// This is used to save power by pausing the ROSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> dormant +// 0x77616b65 -> WAKE +#define ROSC_DORMANT_OFFSET _u(0x00000010) +#define ROSC_DORMANT_BITS _u(0xffffffff) +#define ROSC_DORMANT_RESET "-" +#define ROSC_DORMANT_MSB _u(31) +#define ROSC_DORMANT_LSB _u(0) +#define ROSC_DORMANT_ACCESS "RW" +#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) +// ============================================================================= +// Register : ROSC_DIV +// Description : Controls the output divider +// set to 0xaa00 + div where +// div = 0 divides by 128 +// div = 1-127 divides by div +// any other value sets div=128 +// this register resets to div=32 +// 0xaa00 -> PASS +#define ROSC_DIV_OFFSET _u(0x00000014) +#define ROSC_DIV_BITS _u(0x0000ffff) +#define ROSC_DIV_RESET "-" +#define ROSC_DIV_MSB _u(15) +#define ROSC_DIV_LSB _u(0) +#define ROSC_DIV_ACCESS "RW" +#define ROSC_DIV_VALUE_PASS _u(0xaa00) +// ============================================================================= +// Register : ROSC_PHASE +// Description : Controls the phase shifted output +#define ROSC_PHASE_OFFSET _u(0x00000018) +#define ROSC_PHASE_BITS _u(0x00000fff) +#define ROSC_PHASE_RESET _u(0x00000008) +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_PASSWD +// Description : set to 0xaa +// any other value enables the output with shift=0 +#define ROSC_PHASE_PASSWD_RESET _u(0x00) +#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0) +#define ROSC_PHASE_PASSWD_MSB _u(11) +#define ROSC_PHASE_PASSWD_LSB _u(4) +#define ROSC_PHASE_PASSWD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_ENABLE +// Description : enable the phase-shifted output +// this can be changed on-the-fly +#define ROSC_PHASE_ENABLE_RESET _u(0x1) +#define ROSC_PHASE_ENABLE_BITS _u(0x00000008) +#define ROSC_PHASE_ENABLE_MSB _u(3) +#define ROSC_PHASE_ENABLE_LSB _u(3) +#define ROSC_PHASE_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_FLIP +// Description : invert the phase-shifted output +// this is ignored when div=1 +#define ROSC_PHASE_FLIP_RESET _u(0x0) +#define ROSC_PHASE_FLIP_BITS _u(0x00000004) +#define ROSC_PHASE_FLIP_MSB _u(2) +#define ROSC_PHASE_FLIP_LSB _u(2) +#define ROSC_PHASE_FLIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_SHIFT +// Description : phase shift the phase-shifted output by SHIFT input clocks +// this can be changed on-the-fly +// must be set to 0 before setting div=1 +#define ROSC_PHASE_SHIFT_RESET _u(0x0) +#define ROSC_PHASE_SHIFT_BITS _u(0x00000003) +#define ROSC_PHASE_SHIFT_MSB _u(1) +#define ROSC_PHASE_SHIFT_LSB _u(0) +#define ROSC_PHASE_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : ROSC_STATUS +// Description : Ring Oscillator Status +#define ROSC_STATUS_OFFSET _u(0x0000001c) +#define ROSC_STATUS_BITS _u(0x81011000) +#define ROSC_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define ROSC_STATUS_STABLE_RESET _u(0x0) +#define ROSC_STATUS_STABLE_BITS _u(0x80000000) +#define ROSC_STATUS_STABLE_MSB _u(31) +#define ROSC_STATUS_STABLE_LSB _u(31) +#define ROSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT +#define ROSC_STATUS_BADWRITE_RESET _u(0x0) +#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define ROSC_STATUS_BADWRITE_MSB _u(24) +#define ROSC_STATUS_BADWRITE_LSB _u(24) +#define ROSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_DIV_RUNNING +// Description : post-divider is running +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_DIV_RUNNING_RESET "-" +#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000) +#define ROSC_STATUS_DIV_RUNNING_MSB _u(16) +#define ROSC_STATUS_DIV_RUNNING_LSB _u(16) +#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_ENABLED_RESET "-" +#define ROSC_STATUS_ENABLED_BITS _u(0x00001000) +#define ROSC_STATUS_ENABLED_MSB _u(12) +#define ROSC_STATUS_ENABLED_LSB _u(12) +#define ROSC_STATUS_ENABLED_ACCESS "RO" +// ============================================================================= +// Register : ROSC_RANDOMBIT +// Description : This just reads the state of the oscillator output so +// randomness is compromised if the ring oscillator is stopped or +// run at a harmonic of the bus frequency +#define ROSC_RANDOMBIT_OFFSET _u(0x00000020) +#define ROSC_RANDOMBIT_BITS _u(0x00000001) +#define ROSC_RANDOMBIT_RESET _u(0x00000001) +#define ROSC_RANDOMBIT_MSB _u(0) +#define ROSC_RANDOMBIT_LSB _u(0) +#define ROSC_RANDOMBIT_ACCESS "RO" +// ============================================================================= +// Register : ROSC_COUNT +// Description : A down counter running at the ROSC frequency which counts to +// zero and stops. +// To start the counter write a non-zero value. +// Can be used for short software pauses when setting up time +// sensitive hardware. +#define ROSC_COUNT_OFFSET _u(0x00000024) +#define ROSC_COUNT_BITS _u(0x0000ffff) +#define ROSC_COUNT_RESET _u(0x00000000) +#define ROSC_COUNT_MSB _u(15) +#define ROSC_COUNT_LSB _u(0) +#define ROSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_ROSC_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/rp_ap.h b/src/rp2350/hardware_regs/include/hardware/regs/rp_ap.h new file mode 100644 index 000000000..ff45438c1 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/rp_ap.h @@ -0,0 +1,729 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RP_AP +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_RP_AP_H +#define _HARDWARE_REGS_RP_AP_H +// ============================================================================= +// Register : RP_AP_CTRL +// Description : This register is primarily used for DFT but can also be used to +// overcome some power up problems. However, it should not be used +// to force power up of domains. Use DBG_POW_OVRD for that. +#define RP_AP_CTRL_OFFSET _u(0x00000000) +#define RP_AP_CTRL_BITS _u(0xc000007f) +#define RP_AP_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_RESCUE_RESTART +// Description : Allows debug of boot problems by restarting the chip with +// minimal boot code execution. Write to 1 to put the chip in +// reset then write to 0 to restart the chip with the rescue flag +// set. The rescue flag is in the POWMAN_CHIP_RESET register and +// is read by boot code. The rescue flag is cleared by writing 0 +// to POWMAN_CHIP_RESET_RESCUE_FLAG or by resetting the chip by +// any means other than RESCUE_RESTART. +#define RP_AP_CTRL_RESCUE_RESTART_RESET _u(0x0) +#define RP_AP_CTRL_RESCUE_RESTART_BITS _u(0x80000000) +#define RP_AP_CTRL_RESCUE_RESTART_MSB _u(31) +#define RP_AP_CTRL_RESCUE_RESTART_LSB _u(31) +#define RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_SPARE +// Description : Unused +#define RP_AP_CTRL_SPARE_RESET _u(0x0) +#define RP_AP_CTRL_SPARE_BITS _u(0x40000000) +#define RP_AP_CTRL_SPARE_MSB _u(30) +#define RP_AP_CTRL_SPARE_LSB _u(30) +#define RP_AP_CTRL_SPARE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_DBG_FRCE_GPIO_LPCK +// Description : Allows chip start-up when the Low Power Oscillator (LPOSC) is +// inoperative or malfunctioning and also allows the initial power +// sequencing rate to be adjusted. Write to 1 to force the LPOSC +// output to be driven from a GPIO (gpio20 on 80-pin package, +// gpio34 on the 60-pin package). If the LPOSC is inoperative or +// malfunctioning it may also be necessary to set the +// LPOSC_STABLE_FRCE bit in this register. The user must provide a +// clock on the GPIO. For normal operation use a clock running at +// around 32kHz. Adjusting the frequency will speed up or slow +// down the initial power-up sequence. +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET _u(0x0) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS _u(0x00000040) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB _u(6) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB _u(6) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_LPOSC_STABLE_FRCE +// Description : Allows the chip to start-up even though the Low Power +// Oscillator (LPOSC) is failing to set its stable flag. Initial +// power sequencing is clocked by LPOSC at around 32kHz but does +// not start until the LPOSC declares itself to be stable. If the +// LPOSC is otherwise working correctly the chip will boot when +// this bit is set. If the LPOSC is not working then +// DBG_FRCE_GPIO_LPCK must be set and an external clock provided. +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET _u(0x0) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS _u(0x00000020) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB _u(5) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB _u(5) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_POWMAN_DFT_ISO_OFF +// Description : Holds the isolation gates between power domains in the open +// state. This is intended to hold the gates open for DFT and +// power manager debug. It is not intended to force the isolation +// gates open. Use the overrides in DBG_POW_OVRD to force the +// isolation gates open or closed. +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET _u(0x0) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS _u(0x00000010) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB _u(4) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB _u(4) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_POWMAN_DFT_PWRON +// Description : Holds the power switches on for all domains. This is intended +// to keep the power on for DFT and debug, rather than for +// switching the power on. The power switches are not sequenced +// and the sudden demand for current could cause the always-on +// power domain to brown out. This register is in the always-on +// domain therefore chaos could ensue. It is recommended to use +// the DBG_POW_OVRD controls instead. +#define RP_AP_CTRL_POWMAN_DFT_PWRON_RESET _u(0x0) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_BITS _u(0x00000008) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_MSB _u(3) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_LSB _u(3) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_POWMAN_DBGMODE +// Description : This prevents the power manager from powering down and +// resetting the switched-core power domain. It is intended for +// DFT and for debugging the power manager after the chip has +// booted. It cannot be used to force initial power on because it +// simultaneously deasserts the reset. +#define RP_AP_CTRL_POWMAN_DBGMODE_RESET _u(0x0) +#define RP_AP_CTRL_POWMAN_DBGMODE_BITS _u(0x00000004) +#define RP_AP_CTRL_POWMAN_DBGMODE_MSB _u(2) +#define RP_AP_CTRL_POWMAN_DBGMODE_LSB _u(2) +#define RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_JTAG_FUNCSEL +// Description : Multiplexes the JTAG ports onto GPIO0-3 +#define RP_AP_CTRL_JTAG_FUNCSEL_RESET _u(0x0) +#define RP_AP_CTRL_JTAG_FUNCSEL_BITS _u(0x00000002) +#define RP_AP_CTRL_JTAG_FUNCSEL_MSB _u(1) +#define RP_AP_CTRL_JTAG_FUNCSEL_LSB _u(1) +#define RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_JTAG_TRSTN +// Description : Resets the JTAG module. Active low. +#define RP_AP_CTRL_JTAG_TRSTN_RESET _u(0x0) +#define RP_AP_CTRL_JTAG_TRSTN_BITS _u(0x00000001) +#define RP_AP_CTRL_JTAG_TRSTN_MSB _u(0) +#define RP_AP_CTRL_JTAG_TRSTN_LSB _u(0) +#define RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_DBGKEY +// Description : Serial key load interface (write-only) +#define RP_AP_DBGKEY_OFFSET _u(0x00000004) +#define RP_AP_DBGKEY_BITS _u(0x00000007) +#define RP_AP_DBGKEY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBGKEY_RESET +// Description : Reset (before sending a new key) +#define RP_AP_DBGKEY_RESET_RESET _u(0x0) +#define RP_AP_DBGKEY_RESET_BITS _u(0x00000004) +#define RP_AP_DBGKEY_RESET_MSB _u(2) +#define RP_AP_DBGKEY_RESET_LSB _u(2) +#define RP_AP_DBGKEY_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBGKEY_PUSH +#define RP_AP_DBGKEY_PUSH_RESET _u(0x0) +#define RP_AP_DBGKEY_PUSH_BITS _u(0x00000002) +#define RP_AP_DBGKEY_PUSH_MSB _u(1) +#define RP_AP_DBGKEY_PUSH_LSB _u(1) +#define RP_AP_DBGKEY_PUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBGKEY_DATA +#define RP_AP_DBGKEY_DATA_RESET _u(0x0) +#define RP_AP_DBGKEY_DATA_BITS _u(0x00000001) +#define RP_AP_DBGKEY_DATA_MSB _u(0) +#define RP_AP_DBGKEY_DATA_LSB _u(0) +#define RP_AP_DBGKEY_DATA_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_SWCORE +// Description : This register indicates the state of the power sequencer for +// the switched-core domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +// Bits 9-11 describe the states of the power manager clocks which +// change as clock generators in the switched-core become +// available following switched-core power up. +// This bus can be sent to GPIO for debug. See +// DBG_POW_OUTPUT_TO_GPIO in the DBG_POW_OVRD register. +#define RP_AP_DBG_POW_STATE_SWCORE_OFFSET _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SWCORE_BITS _u(0x00000fff) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK +// Description : Indicates the source of the power manager clock. On switched- +// core power up the clock switches from the LPOSC to clk_ref and +// this flag will be set. clk_ref will be running from the ROSC +// initially but will switch to XOSC when it comes available. On +// switched-core power down the clock switches to LPOSC and this +// flag will be cleared. +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS _u(0x00000800) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB _u(11) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB _u(11) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK +// Description : Indicates the switched-core power sequencer is waiting for the +// power manager clock to update. On switched-core power up the +// clock switches from the LPOSC to clk_ref. clk_ref will be +// running from the ROSC initially but will switch to XOSC when it +// comes available. On switched-core power down the clock switches +// to LPOSC. +// If the switched-core power up sequence stalls with this flag +// active then it means clk_ref is not running which indicates a +// problem with the ROSC. If that happens then set +// DBG_POW_RESTART_FROM_XOSC in the DBG_POW_OVRD register to avoid +// using the ROSC. +// If the switched-core power down sequence stalls with this flag +// active then it means LPOSC is not running. The solution is to +// not stop LPOSC when the switched-core power domain is powered. +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS _u(0x00000400) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB _u(10) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB _u(10) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK +// Description : Indicates that the switched-core power sequencer is waiting for +// the AON-Timer to update. On switched-core power-up there is +// nothing to be done. The AON-Timer continues to run from the +// LPOSC so this flag will not be set. Software decides whether to +// switch the AON-Timer clock to XOSC (via clk_ref). On switched- +// core power-down the sequencer will switch the AON-Timer back to +// LPOSC if software switched it to XOSC. During the switchover +// the WAITING_TIMCK flag will be set. If the switched-core power +// down sequence stalls with this flag active then the only +// recourse is to reset the chip and change software to not select +// XOSC as the AON-Timer source. +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS _u(0x00000200) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB _u(9) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB _u(9) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_XIP +// Description : This register indicates the state of the power sequencer for +// the XIP domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +#define RP_AP_DBG_POW_STATE_XIP_OFFSET _u(0x0000000c) +#define RP_AP_DBG_POW_STATE_XIP_BITS _u(0x000001ff) +#define RP_AP_DBG_POW_STATE_XIP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_SRAM0 +// Description : This register indicates the state of the power sequencer for +// the SRAM0 domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +#define RP_AP_DBG_POW_STATE_SRAM0_OFFSET _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SRAM0_BITS _u(0x000001ff) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_SRAM1 +// Description : This register indicates the state of the power sequencer for +// the SRAM1 domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +#define RP_AP_DBG_POW_STATE_SRAM1_OFFSET _u(0x00000014) +#define RP_AP_DBG_POW_STATE_SRAM1_BITS _u(0x000001ff) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_OVRD +// Description : This register allows external control of the power sequencer +// outputs for all the switched power domains. If any of the power +// sequencers stall at any stage then force power up operation of +// all domains by running this sequence: +// - set DBG_POW_OVRD = 0x3b to force small power switches on, +// large power switches off, resets on and isolation on +// - allow time for the domain power supplies to reach full rail +// - set DBG_POW_OVRD = 0x3b to force large power switches on +// - set DBG_POW_OVRD = 0x37 to remove isolation +// - set DBG_POW_OVRD = 0x17 to remove resets +#define RP_AP_DBG_POW_OVRD_OFFSET _u(0x00000018) +#define RP_AP_DBG_POW_OVRD_BITS _u(0x0000007f) +#define RP_AP_DBG_POW_OVRD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC +// Description : By default the system begins boot as soon as a clock is +// available from the ROSC, then it switches to the XOSC when it +// is available. This is done because the XOSC takes several ms to +// start up. If there is a problem with the ROSC then the default +// behaviour can be changed to not use the ROSC and wait for XOSC. +// However, this requires a mask change to modify the reset value +// of the Power Manager START_FROM_XOSC register. To allow +// experimentation the default can be temporarily changed by +// setting this register bit to 1. After setting this bit the core +// must be reset by a Coresight dprst or a rescue reset (see +// RESCUE_RESTART in the RP_AP_CTRL register above). A power-on +// reset, brown-out reset or RUN pin reset will reset this control +// and revert to the default behaviour. +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS _u(0x00000040) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB _u(6) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB _u(6) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESET +// Description : When DBG_POW_OVRD_RESET=1 this register bit controls the resets +// for all domains. 1 = reset. 0 = not reset. +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS _u(0x00000020) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB _u(5) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB _u(5) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET +// Description : Enables DBG_POW_RESET to control the resets for the power +// manager and the switched-core. Essentially that is everythjing +// except the Coresight 2-wire interface and the RP_AP registers. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS _u(0x00000010) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB _u(4) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB _u(4) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_ISO +// Description : When DBG_POW_OVRD_ISO=1 this register bit controls the +// isolation gates for all domains. 1 = isolated. 0 = not +// isolated. +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS _u(0x00000008) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB _u(3) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB _u(3) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO +// Description : Enables DBG_POW_ISO to control the isolation gates between +// domains. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS _u(0x00000004) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB _u(2) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB _u(2) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ +// Description : Turn on the large power switches for all domains. This should +// not be done until sufficient time has been allowed for the +// small switches to bring the supplies up. Switching the large +// switches on too soon risks browning out the always-on domain +// and corrupting these very registers. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS _u(0x00000002) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB _u(1) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB _u(1) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ +// Description : Turn on the small power switches for all domains. This switches +// on chain 0 for each domain and switches off chains 2 & 3 and +// the large power switch chain. This will bring the power up for +// all domains without browning out the always-on power domain. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS _u(0x00000001) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB _u(0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB _u(0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_DBG_POW_OUTPUT_TO_GPIO +// Description : Send some, or all, bits of DBG_POW_STATE_SWCORE to gpios. +// Bit 0 sends bit 0 of DBG_POW_STATE_SWCORE to GPIO 34 +// Bit 1 sends bit 1 of DBG_POW_STATE_SWCORE to GPIO 35 +// Bit 2 sends bit 2 of DBG_POW_STATE_SWCORE to GPIO 36 +// . +// . +// Bit 11 sends bit 11 of DBG_POW_STATE_SWCORE to GPIO 45 +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET _u(0x0000001c) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS _u(0x00000fff) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET _u(0x000) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS _u(0x00000fff) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB _u(11) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB _u(0) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_IDR +// Description : Standard Coresight ID Register +#define RP_AP_IDR_OFFSET _u(0x00000dfc) +#define RP_AP_IDR_BITS _u(0xffffffff) +#define RP_AP_IDR_RESET "-" +#define RP_AP_IDR_MSB _u(31) +#define RP_AP_IDR_LSB _u(0) +#define RP_AP_IDR_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RP_AP_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/rvcsr.h b/src/rp2350/hardware_regs/include/hardware/regs/rvcsr.h new file mode 100644 index 000000000..f5ff378ab --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/rvcsr.h @@ -0,0 +1,3154 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RVCSR +// Version : 1 +// Bus type : apb +// Description : CSR listing for Hazard3 +// ============================================================================= +#ifndef _HARDWARE_REGS_RVCSR_H +#define _HARDWARE_REGS_RVCSR_H +// ============================================================================= +// Register : RVCSR_MSTATUS +// Description : Machine status register +#define RVCSR_MSTATUS_OFFSET _u(0x00000300) +#define RVCSR_MSTATUS_BITS _u(0x00221888) +#define RVCSR_MSTATUS_RESET _u(0x00001800) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_TW +// Description : Timeout wait. When 1, attempting to execute a WFI instruction +// in U-mode will instantly cause an illegal instruction +// exception. +#define RVCSR_MSTATUS_TW_RESET _u(0x0) +#define RVCSR_MSTATUS_TW_BITS _u(0x00200000) +#define RVCSR_MSTATUS_TW_MSB _u(21) +#define RVCSR_MSTATUS_TW_LSB _u(21) +#define RVCSR_MSTATUS_TW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MPRV +// Description : Modify privilege. If 1, loads and stores behave as though the +// current privilege level were `mpp`. This includes physical +// memory protection checks, and the privilege level asserted on +// the system bus alongside the load/store address. +#define RVCSR_MSTATUS_MPRV_RESET _u(0x0) +#define RVCSR_MSTATUS_MPRV_BITS _u(0x00020000) +#define RVCSR_MSTATUS_MPRV_MSB _u(17) +#define RVCSR_MSTATUS_MPRV_LSB _u(17) +#define RVCSR_MSTATUS_MPRV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MPP +// Description : Previous privilege level. Can store the values 3 (M-mode) or 0 +// (U-mode). If another value is written, hardware rounds to the +// nearest supported mode. +#define RVCSR_MSTATUS_MPP_RESET _u(0x3) +#define RVCSR_MSTATUS_MPP_BITS _u(0x00001800) +#define RVCSR_MSTATUS_MPP_MSB _u(12) +#define RVCSR_MSTATUS_MPP_LSB _u(11) +#define RVCSR_MSTATUS_MPP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MPIE +// Description : Previous interrupt enable. Readable and writable. Is set to the +// current value of `mstatus.mie` on trap entry. Is set to 1 on +// trap return. +#define RVCSR_MSTATUS_MPIE_RESET _u(0x0) +#define RVCSR_MSTATUS_MPIE_BITS _u(0x00000080) +#define RVCSR_MSTATUS_MPIE_MSB _u(7) +#define RVCSR_MSTATUS_MPIE_LSB _u(7) +#define RVCSR_MSTATUS_MPIE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MIE +// Description : Interrupt enable. Readable and writable. Is set to 0 on trap +// entry. Is set to the current value of `mstatus.mpie` on trap +// return. +#define RVCSR_MSTATUS_MIE_RESET _u(0x0) +#define RVCSR_MSTATUS_MIE_BITS _u(0x00000008) +#define RVCSR_MSTATUS_MIE_MSB _u(3) +#define RVCSR_MSTATUS_MIE_LSB _u(3) +#define RVCSR_MSTATUS_MIE_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MISA +// Description : Summary of ISA extension support +// +// On RP2350, Hazard3's full `-march` string is: +// `rv32ima_zicsr_zifencei_zba_zbb_zbs_zbkb_zca_zcb_zcmp` +// +// Note Zca is equivalent to the C extension in this case; all +// instructions from the RISC-V C extension relevant to a 32-bit +// non-floating-point processor are supported. On older toolchains +// which do not support the Zc extensions, the appropriate +// `-march` string is: `rv32imac_zicsr_zifencei_zba_zbb_zbs_zbkb` +// +// In addition the following custom extensions are configured: +// Xh3bm, Xh3power, Xh3irq, Xh3pmpm +#define RVCSR_MISA_OFFSET _u(0x00000301) +#define RVCSR_MISA_BITS _u(0xc0901107) +#define RVCSR_MISA_RESET _u(0x40901105) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_MXL +// Description : Value of 0x1 indicates this is a 32-bit processor. +#define RVCSR_MISA_MXL_RESET _u(0x1) +#define RVCSR_MISA_MXL_BITS _u(0xc0000000) +#define RVCSR_MISA_MXL_MSB _u(31) +#define RVCSR_MISA_MXL_LSB _u(30) +#define RVCSR_MISA_MXL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_X +// Description : Value of 1 indicates nonstandard extensions are present. (Xh3b +// bit manipulation, and custom sleep and interrupt control CSRs) +#define RVCSR_MISA_X_RESET _u(0x1) +#define RVCSR_MISA_X_BITS _u(0x00800000) +#define RVCSR_MISA_X_MSB _u(23) +#define RVCSR_MISA_X_LSB _u(23) +#define RVCSR_MISA_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_U +// Description : Value of 1 indicates U-mode is implemented. +#define RVCSR_MISA_U_RESET _u(0x1) +#define RVCSR_MISA_U_BITS _u(0x00100000) +#define RVCSR_MISA_U_MSB _u(20) +#define RVCSR_MISA_U_LSB _u(20) +#define RVCSR_MISA_U_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_M +// Description : Value of 1 indicates the M extension (integer multiply/divide) +// is implemented. +#define RVCSR_MISA_M_RESET _u(0x1) +#define RVCSR_MISA_M_BITS _u(0x00001000) +#define RVCSR_MISA_M_MSB _u(12) +#define RVCSR_MISA_M_LSB _u(12) +#define RVCSR_MISA_M_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_I +// Description : Value of 1 indicates the RVI base ISA is implemented (as +// opposed to RVE) +#define RVCSR_MISA_I_RESET _u(0x1) +#define RVCSR_MISA_I_BITS _u(0x00000100) +#define RVCSR_MISA_I_MSB _u(8) +#define RVCSR_MISA_I_LSB _u(8) +#define RVCSR_MISA_I_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_C +// Description : Value of 1 indicates the C extension (compressed instructions) +// is implemented. +#define RVCSR_MISA_C_RESET _u(0x1) +#define RVCSR_MISA_C_BITS _u(0x00000004) +#define RVCSR_MISA_C_MSB _u(2) +#define RVCSR_MISA_C_LSB _u(2) +#define RVCSR_MISA_C_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_B +// Description : Value of 1 indicates the B extension (bit manipulation) is +// implemented. B is the combination of Zba, Zbb and Zbs. +// +// Hazard3 implements all of these extensions, but the definition +// of B as ZbaZbbZbs did not exist at the point this version of +// Hazard3 was taped out. This bit was reserved-0 at that point. +// Therefore this bit reads as 0. +#define RVCSR_MISA_B_RESET _u(0x0) +#define RVCSR_MISA_B_BITS _u(0x00000002) +#define RVCSR_MISA_B_MSB _u(1) +#define RVCSR_MISA_B_LSB _u(1) +#define RVCSR_MISA_B_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_A +// Description : Value of 1 indicates the A extension (atomics) is implemented. +#define RVCSR_MISA_A_RESET _u(0x1) +#define RVCSR_MISA_A_BITS _u(0x00000001) +#define RVCSR_MISA_A_MSB _u(0) +#define RVCSR_MISA_A_LSB _u(0) +#define RVCSR_MISA_A_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MEDELEG +// Description : Machine exception delegation register. Not implemented, as no +// S-mode support. +#define RVCSR_MEDELEG_OFFSET _u(0x00000302) +#define RVCSR_MEDELEG_BITS _u(0xffffffff) +#define RVCSR_MEDELEG_RESET "-" +#define RVCSR_MEDELEG_MSB _u(31) +#define RVCSR_MEDELEG_LSB _u(0) +#define RVCSR_MEDELEG_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MIDELEG +// Description : Machine interrupt delegation register. Not implemented, as no +// S-mode support. +#define RVCSR_MIDELEG_OFFSET _u(0x00000303) +#define RVCSR_MIDELEG_BITS _u(0xffffffff) +#define RVCSR_MIDELEG_RESET "-" +#define RVCSR_MIDELEG_MSB _u(31) +#define RVCSR_MIDELEG_LSB _u(0) +#define RVCSR_MIDELEG_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MIE +// Description : Machine interrupt enable register +#define RVCSR_MIE_OFFSET _u(0x00000304) +#define RVCSR_MIE_BITS _u(0x00000888) +#define RVCSR_MIE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIE_MEIE +// Description : External interrupt enable. The processor transfers to the +// external interrupt vector when `mie.meie`, `mip.meip` and +// `mstatus.mie` are all 1. +// +// Hazard3 has internal registers to individually filter external +// interrupts (see `meiea`), but this standard control can be used +// to mask all external interrupts at once. +#define RVCSR_MIE_MEIE_RESET _u(0x0) +#define RVCSR_MIE_MEIE_BITS _u(0x00000800) +#define RVCSR_MIE_MEIE_MSB _u(11) +#define RVCSR_MIE_MEIE_LSB _u(11) +#define RVCSR_MIE_MEIE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIE_MTIE +// Description : Timer interrupt enable. The processor transfers to the timer +// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` +// are all 1, unless a software or external interrupt request is +// also valid at this time. +#define RVCSR_MIE_MTIE_RESET _u(0x0) +#define RVCSR_MIE_MTIE_BITS _u(0x00000080) +#define RVCSR_MIE_MTIE_MSB _u(7) +#define RVCSR_MIE_MTIE_LSB _u(7) +#define RVCSR_MIE_MTIE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIE_MSIE +// Description : Software interrupt enable. The processor transfers to the +// software interrupt vector `mie.msie`, `mip.msip` and +// `mstatus.mie` are all 1, unless an external interrupt request +// is also valid at this time. +#define RVCSR_MIE_MSIE_RESET _u(0x0) +#define RVCSR_MIE_MSIE_BITS _u(0x00000008) +#define RVCSR_MIE_MSIE_MSB _u(3) +#define RVCSR_MIE_MSIE_LSB _u(3) +#define RVCSR_MIE_MSIE_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MTVEC +// Description : Machine trap handler base address. +#define RVCSR_MTVEC_OFFSET _u(0x00000305) +#define RVCSR_MTVEC_BITS _u(0xffffffff) +#define RVCSR_MTVEC_RESET _u(0x00007ffc) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MTVEC_BASE +// Description : The upper 30 bits of the trap vector address (2 LSBs are +// implicitly 0). Must be 64-byte-aligned if vectoring is enabled. +// Otherwise, must be 4-byte-aligned. +#define RVCSR_MTVEC_BASE_RESET _u(0x00001fff) +#define RVCSR_MTVEC_BASE_BITS _u(0xfffffffc) +#define RVCSR_MTVEC_BASE_MSB _u(31) +#define RVCSR_MTVEC_BASE_LSB _u(2) +#define RVCSR_MTVEC_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MTVEC_MODE +// Description : If 0 (direct mode), all traps set pc to the trap vector base. +// If 1 (vectored), exceptions set pc to the trap vector base, and +// interrupts set pc to 4 times the interrupt cause (3=soft IRQ, +// 7=timer IRQ, 11=external IRQ). +// +// The upper bit is hardwired to zero, so attempting to set mode +// to 2 or 3 will result in a value of 0 or 1 respectively. +// 0x0 -> Direct entry to mtvec +// 0x1 -> Vectored entry to a 16-entry jump table starting at mtvec +#define RVCSR_MTVEC_MODE_RESET _u(0x0) +#define RVCSR_MTVEC_MODE_BITS _u(0x00000003) +#define RVCSR_MTVEC_MODE_MSB _u(1) +#define RVCSR_MTVEC_MODE_LSB _u(0) +#define RVCSR_MTVEC_MODE_ACCESS "RW" +#define RVCSR_MTVEC_MODE_VALUE_DIRECT _u(0x0) +#define RVCSR_MTVEC_MODE_VALUE_VECTORED _u(0x1) +// ============================================================================= +// Register : RVCSR_MCOUNTEREN +// Description : Counter enable. Control access to counters from U-mode. Not to +// be confused with mcountinhibit. +#define RVCSR_MCOUNTEREN_OFFSET _u(0x00000306) +#define RVCSR_MCOUNTEREN_BITS _u(0x00000007) +#define RVCSR_MCOUNTEREN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTEREN_IR +// Description : If 1, U-mode is permitted to access the `instret`/`instreth` +// instruction retire counter CSRs. Otherwise, U-mode accesses to +// these CSRs will trap. +#define RVCSR_MCOUNTEREN_IR_RESET _u(0x0) +#define RVCSR_MCOUNTEREN_IR_BITS _u(0x00000004) +#define RVCSR_MCOUNTEREN_IR_MSB _u(2) +#define RVCSR_MCOUNTEREN_IR_LSB _u(2) +#define RVCSR_MCOUNTEREN_IR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTEREN_TM +// Description : No hardware effect, as the `time`/`timeh` CSRs are not +// implemented. However, this field still exists, as M-mode +// software can use it to track whether it should emulate U-mode +// attempts to access those CSRs. +#define RVCSR_MCOUNTEREN_TM_RESET _u(0x0) +#define RVCSR_MCOUNTEREN_TM_BITS _u(0x00000002) +#define RVCSR_MCOUNTEREN_TM_MSB _u(1) +#define RVCSR_MCOUNTEREN_TM_LSB _u(1) +#define RVCSR_MCOUNTEREN_TM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTEREN_CY +// Description : If 1, U-mode is permitted to access the `cycle`/`cycleh` cycle +// counter CSRs. Otherwise, U-mode accesses to these CSRs will +// trap. +#define RVCSR_MCOUNTEREN_CY_RESET _u(0x0) +#define RVCSR_MCOUNTEREN_CY_BITS _u(0x00000001) +#define RVCSR_MCOUNTEREN_CY_MSB _u(0) +#define RVCSR_MCOUNTEREN_CY_LSB _u(0) +#define RVCSR_MCOUNTEREN_CY_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MENVCFG +// Description : Machine environment configuration register, low half +#define RVCSR_MENVCFG_OFFSET _u(0x0000030a) +#define RVCSR_MENVCFG_BITS _u(0x00000001) +#define RVCSR_MENVCFG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MENVCFG_FIOM +// Description : When set, fence instructions in modes less privileged than +// M-mode which specify that IO memory accesses are ordered will +// also cause ordering of main memory accesses. +// +// FIOM is hardwired to zero on Hazard3, because S-mode is not +// supported, and because fence instructions execute as NOPs (with +// the exception of `fence.i`) +#define RVCSR_MENVCFG_FIOM_RESET _u(0x0) +#define RVCSR_MENVCFG_FIOM_BITS _u(0x00000001) +#define RVCSR_MENVCFG_FIOM_MSB _u(0) +#define RVCSR_MENVCFG_FIOM_LSB _u(0) +#define RVCSR_MENVCFG_FIOM_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MSTATUSH +// Description : High half of mstatus, hardwired to 0. +#define RVCSR_MSTATUSH_OFFSET _u(0x00000310) +#define RVCSR_MSTATUSH_BITS _u(0xffffffff) +#define RVCSR_MSTATUSH_RESET _u(0x00000000) +#define RVCSR_MSTATUSH_MSB _u(31) +#define RVCSR_MSTATUSH_LSB _u(0) +#define RVCSR_MSTATUSH_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MENVCFGH +// Description : Machine environment configuration register, high half +// +// This register is fully reserved, as Hazard3 does not implement +// the relevant extensions. It is implemented as hardwired-0. +#define RVCSR_MENVCFGH_OFFSET _u(0x0000031a) +#define RVCSR_MENVCFGH_BITS _u(0x00000000) +#define RVCSR_MENVCFGH_RESET _u(0x00000000) +#define RVCSR_MENVCFGH_MSB _u(31) +#define RVCSR_MENVCFGH_LSB _u(0) +#define RVCSR_MENVCFGH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MCOUNTINHIBIT +// Description : Count inhibit register for `mcycle`/`minstret` +#define RVCSR_MCOUNTINHIBIT_OFFSET _u(0x00000320) +#define RVCSR_MCOUNTINHIBIT_BITS _u(0x00000005) +#define RVCSR_MCOUNTINHIBIT_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTINHIBIT_IR +// Description : Inhibit counting of the `minstret` and `minstreth` registers. +// Set by default to save power. +#define RVCSR_MCOUNTINHIBIT_IR_RESET _u(0x1) +#define RVCSR_MCOUNTINHIBIT_IR_BITS _u(0x00000004) +#define RVCSR_MCOUNTINHIBIT_IR_MSB _u(2) +#define RVCSR_MCOUNTINHIBIT_IR_LSB _u(2) +#define RVCSR_MCOUNTINHIBIT_IR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTINHIBIT_CY +// Description : Inhibit counting of the `mcycle` and `mcycleh` registers. Set +// by default to save power. +#define RVCSR_MCOUNTINHIBIT_CY_RESET _u(0x1) +#define RVCSR_MCOUNTINHIBIT_CY_BITS _u(0x00000001) +#define RVCSR_MCOUNTINHIBIT_CY_MSB _u(0) +#define RVCSR_MCOUNTINHIBIT_CY_LSB _u(0) +#define RVCSR_MCOUNTINHIBIT_CY_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MHPMEVENT3 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT3_OFFSET _u(0x00000323) +#define RVCSR_MHPMEVENT3_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT3_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT3_MSB _u(31) +#define RVCSR_MHPMEVENT3_LSB _u(0) +#define RVCSR_MHPMEVENT3_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT4 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT4_OFFSET _u(0x00000324) +#define RVCSR_MHPMEVENT4_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT4_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT4_MSB _u(31) +#define RVCSR_MHPMEVENT4_LSB _u(0) +#define RVCSR_MHPMEVENT4_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT5 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT5_OFFSET _u(0x00000325) +#define RVCSR_MHPMEVENT5_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT5_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT5_MSB _u(31) +#define RVCSR_MHPMEVENT5_LSB _u(0) +#define RVCSR_MHPMEVENT5_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT6 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT6_OFFSET _u(0x00000326) +#define RVCSR_MHPMEVENT6_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT6_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT6_MSB _u(31) +#define RVCSR_MHPMEVENT6_LSB _u(0) +#define RVCSR_MHPMEVENT6_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT7 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT7_OFFSET _u(0x00000327) +#define RVCSR_MHPMEVENT7_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT7_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT7_MSB _u(31) +#define RVCSR_MHPMEVENT7_LSB _u(0) +#define RVCSR_MHPMEVENT7_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT8 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT8_OFFSET _u(0x00000328) +#define RVCSR_MHPMEVENT8_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT8_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT8_MSB _u(31) +#define RVCSR_MHPMEVENT8_LSB _u(0) +#define RVCSR_MHPMEVENT8_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT9 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT9_OFFSET _u(0x00000329) +#define RVCSR_MHPMEVENT9_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT9_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT9_MSB _u(31) +#define RVCSR_MHPMEVENT9_LSB _u(0) +#define RVCSR_MHPMEVENT9_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT10 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT10_OFFSET _u(0x0000032a) +#define RVCSR_MHPMEVENT10_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT10_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT10_MSB _u(31) +#define RVCSR_MHPMEVENT10_LSB _u(0) +#define RVCSR_MHPMEVENT10_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT11 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT11_OFFSET _u(0x0000032b) +#define RVCSR_MHPMEVENT11_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT11_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT11_MSB _u(31) +#define RVCSR_MHPMEVENT11_LSB _u(0) +#define RVCSR_MHPMEVENT11_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT12 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT12_OFFSET _u(0x0000032c) +#define RVCSR_MHPMEVENT12_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT12_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT12_MSB _u(31) +#define RVCSR_MHPMEVENT12_LSB _u(0) +#define RVCSR_MHPMEVENT12_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT13 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT13_OFFSET _u(0x0000032d) +#define RVCSR_MHPMEVENT13_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT13_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT13_MSB _u(31) +#define RVCSR_MHPMEVENT13_LSB _u(0) +#define RVCSR_MHPMEVENT13_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT14 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT14_OFFSET _u(0x0000032e) +#define RVCSR_MHPMEVENT14_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT14_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT14_MSB _u(31) +#define RVCSR_MHPMEVENT14_LSB _u(0) +#define RVCSR_MHPMEVENT14_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT15 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT15_OFFSET _u(0x0000032f) +#define RVCSR_MHPMEVENT15_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT15_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT15_MSB _u(31) +#define RVCSR_MHPMEVENT15_LSB _u(0) +#define RVCSR_MHPMEVENT15_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT16 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT16_OFFSET _u(0x00000330) +#define RVCSR_MHPMEVENT16_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT16_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT16_MSB _u(31) +#define RVCSR_MHPMEVENT16_LSB _u(0) +#define RVCSR_MHPMEVENT16_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT17 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT17_OFFSET _u(0x00000331) +#define RVCSR_MHPMEVENT17_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT17_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT17_MSB _u(31) +#define RVCSR_MHPMEVENT17_LSB _u(0) +#define RVCSR_MHPMEVENT17_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT18 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT18_OFFSET _u(0x00000332) +#define RVCSR_MHPMEVENT18_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT18_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT18_MSB _u(31) +#define RVCSR_MHPMEVENT18_LSB _u(0) +#define RVCSR_MHPMEVENT18_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT19 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT19_OFFSET _u(0x00000333) +#define RVCSR_MHPMEVENT19_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT19_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT19_MSB _u(31) +#define RVCSR_MHPMEVENT19_LSB _u(0) +#define RVCSR_MHPMEVENT19_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT20 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT20_OFFSET _u(0x00000334) +#define RVCSR_MHPMEVENT20_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT20_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT20_MSB _u(31) +#define RVCSR_MHPMEVENT20_LSB _u(0) +#define RVCSR_MHPMEVENT20_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT21 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT21_OFFSET _u(0x00000335) +#define RVCSR_MHPMEVENT21_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT21_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT21_MSB _u(31) +#define RVCSR_MHPMEVENT21_LSB _u(0) +#define RVCSR_MHPMEVENT21_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT22 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT22_OFFSET _u(0x00000336) +#define RVCSR_MHPMEVENT22_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT22_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT22_MSB _u(31) +#define RVCSR_MHPMEVENT22_LSB _u(0) +#define RVCSR_MHPMEVENT22_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT23 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT23_OFFSET _u(0x00000337) +#define RVCSR_MHPMEVENT23_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT23_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT23_MSB _u(31) +#define RVCSR_MHPMEVENT23_LSB _u(0) +#define RVCSR_MHPMEVENT23_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT24 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT24_OFFSET _u(0x00000338) +#define RVCSR_MHPMEVENT24_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT24_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT24_MSB _u(31) +#define RVCSR_MHPMEVENT24_LSB _u(0) +#define RVCSR_MHPMEVENT24_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT25 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT25_OFFSET _u(0x00000339) +#define RVCSR_MHPMEVENT25_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT25_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT25_MSB _u(31) +#define RVCSR_MHPMEVENT25_LSB _u(0) +#define RVCSR_MHPMEVENT25_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT26 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT26_OFFSET _u(0x0000033a) +#define RVCSR_MHPMEVENT26_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT26_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT26_MSB _u(31) +#define RVCSR_MHPMEVENT26_LSB _u(0) +#define RVCSR_MHPMEVENT26_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT27 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT27_OFFSET _u(0x0000033b) +#define RVCSR_MHPMEVENT27_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT27_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT27_MSB _u(31) +#define RVCSR_MHPMEVENT27_LSB _u(0) +#define RVCSR_MHPMEVENT27_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT28 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT28_OFFSET _u(0x0000033c) +#define RVCSR_MHPMEVENT28_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT28_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT28_MSB _u(31) +#define RVCSR_MHPMEVENT28_LSB _u(0) +#define RVCSR_MHPMEVENT28_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT29 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT29_OFFSET _u(0x0000033d) +#define RVCSR_MHPMEVENT29_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT29_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT29_MSB _u(31) +#define RVCSR_MHPMEVENT29_LSB _u(0) +#define RVCSR_MHPMEVENT29_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT30 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT30_OFFSET _u(0x0000033e) +#define RVCSR_MHPMEVENT30_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT30_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT30_MSB _u(31) +#define RVCSR_MHPMEVENT30_LSB _u(0) +#define RVCSR_MHPMEVENT30_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT31 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT31_OFFSET _u(0x0000033f) +#define RVCSR_MHPMEVENT31_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT31_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT31_MSB _u(31) +#define RVCSR_MHPMEVENT31_LSB _u(0) +#define RVCSR_MHPMEVENT31_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MSCRATCH +// Description : Scratch register for machine trap handlers. +// +// 32-bit read/write register with no specific hardware function. +// Software may use this to do a fast save/restore of a core +// register in a trap handler. +#define RVCSR_MSCRATCH_OFFSET _u(0x00000340) +#define RVCSR_MSCRATCH_BITS _u(0xffffffff) +#define RVCSR_MSCRATCH_RESET _u(0x00000000) +#define RVCSR_MSCRATCH_MSB _u(31) +#define RVCSR_MSCRATCH_LSB _u(0) +#define RVCSR_MSCRATCH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MEPC +// Description : Machine exception program counter. +// +// When entering a trap, the current value of the program counter +// is recorded here. When executing an `mret`, the processor jumps +// to `mepc`. Can also be read and written by software. +#define RVCSR_MEPC_OFFSET _u(0x00000341) +#define RVCSR_MEPC_BITS _u(0xfffffffc) +#define RVCSR_MEPC_RESET _u(0x00000000) +#define RVCSR_MEPC_MSB _u(31) +#define RVCSR_MEPC_LSB _u(2) +#define RVCSR_MEPC_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MCAUSE +// Description : Machine trap cause. Set when entering a trap to indicate the +// reason for the trap. Readable and writable by software. +#define RVCSR_MCAUSE_OFFSET _u(0x00000342) +#define RVCSR_MCAUSE_BITS _u(0x8000000f) +#define RVCSR_MCAUSE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCAUSE_INTERRUPT +// Description : If 1, the trap was caused by an interrupt. If 0, it was caused +// by an exception. +#define RVCSR_MCAUSE_INTERRUPT_RESET _u(0x0) +#define RVCSR_MCAUSE_INTERRUPT_BITS _u(0x80000000) +#define RVCSR_MCAUSE_INTERRUPT_MSB _u(31) +#define RVCSR_MCAUSE_INTERRUPT_LSB _u(31) +#define RVCSR_MCAUSE_INTERRUPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCAUSE_CODE +// Description : If `interrupt` is set, `code` indicates the index of the bit in +// mip that caused the trap (3=soft IRQ, 7=timer IRQ, 11=external +// IRQ). Otherwise, `code` is set according to the cause of the +// exception. +// 0x0 -> Instruction fetch was misaligned. Will never fire on RP2350, since the C extension is enabled. +// 0x1 -> Instruction access fault. Instruction fetch failed a PMP check, or encountered a downstream bus fault, and then passed the point of no speculation. +// 0x2 -> Illegal instruction was executed (including illegal CSR accesses) +// 0x3 -> Breakpoint. An ebreak instruction was executed when the relevant dcsr.ebreak bit was clear. +// 0x4 -> Load address misaligned. Hazard3 requires natural alignment of all accesses. +// 0x5 -> Load access fault. A load failed a PMP check, or encountered a downstream bus error. +// 0x6 -> Store/AMO address misaligned. Hazard3 requires natural alignment of all accesses. +// 0x7 -> Store/AMO access fault. A store/AMO failed a PMP check, or encountered a downstream bus error. Also set if an AMO is attempted on a region that does not support atomics (on RP2350, anything but SRAM). +// 0x8 -> Environment call from U-mode. +// 0xb -> Environment call from M-mode. +#define RVCSR_MCAUSE_CODE_RESET _u(0x0) +#define RVCSR_MCAUSE_CODE_BITS _u(0x0000000f) +#define RVCSR_MCAUSE_CODE_MSB _u(3) +#define RVCSR_MCAUSE_CODE_LSB _u(0) +#define RVCSR_MCAUSE_CODE_ACCESS "RW" +#define RVCSR_MCAUSE_CODE_VALUE_INSTR_ALIGN _u(0x0) +#define RVCSR_MCAUSE_CODE_VALUE_INSTR_FAULT _u(0x1) +#define RVCSR_MCAUSE_CODE_VALUE_ILLEGAL_INSTR _u(0x2) +#define RVCSR_MCAUSE_CODE_VALUE_BREAKPOINT _u(0x3) +#define RVCSR_MCAUSE_CODE_VALUE_LOAD_ALIGN _u(0x4) +#define RVCSR_MCAUSE_CODE_VALUE_LOAD_FAULT _u(0x5) +#define RVCSR_MCAUSE_CODE_VALUE_STORE_ALIGN _u(0x6) +#define RVCSR_MCAUSE_CODE_VALUE_STORE_FAULT _u(0x7) +#define RVCSR_MCAUSE_CODE_VALUE_U_ECALL _u(0x8) +#define RVCSR_MCAUSE_CODE_VALUE_M_ECALL _u(0xb) +// ============================================================================= +// Register : RVCSR_MTVAL +// Description : Machine bad address or instruction. Hardwired to zero. +#define RVCSR_MTVAL_OFFSET _u(0x00000343) +#define RVCSR_MTVAL_BITS _u(0xffffffff) +#define RVCSR_MTVAL_RESET _u(0x00000000) +#define RVCSR_MTVAL_MSB _u(31) +#define RVCSR_MTVAL_LSB _u(0) +#define RVCSR_MTVAL_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MIP +// Description : Machine interrupt pending +#define RVCSR_MIP_OFFSET _u(0x00000344) +#define RVCSR_MIP_BITS _u(0x00000888) +#define RVCSR_MIP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIP_MEIP +// Description : External interrupt pending. The processor transfers to the +// external interrupt vector when `mie.meie`, `mip.meip` and +// `mstatus.mie` are all 1. +// +// Hazard3 has internal registers to individually filter which +// external IRQs appear in `meip`. When `meip` is 1, this +// indicates there is at least one external interrupt which is +// asserted (hence pending in `mieipa`), enabled in `meiea`, and +// of priority greater than or equal to the current preemption +// level in `meicontext.preempt`. +#define RVCSR_MIP_MEIP_RESET _u(0x0) +#define RVCSR_MIP_MEIP_BITS _u(0x00000800) +#define RVCSR_MIP_MEIP_MSB _u(11) +#define RVCSR_MIP_MEIP_LSB _u(11) +#define RVCSR_MIP_MEIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIP_MTIP +// Description : Timer interrupt pending. The processor transfers to the timer +// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` +// are all 1, unless a software or external interrupt request is +// also valid at this time. +#define RVCSR_MIP_MTIP_RESET _u(0x0) +#define RVCSR_MIP_MTIP_BITS _u(0x00000080) +#define RVCSR_MIP_MTIP_MSB _u(7) +#define RVCSR_MIP_MTIP_LSB _u(7) +#define RVCSR_MIP_MTIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIP_MSIP +// Description : Software interrupt pending. The processor transfers to the +// software interrupt vector `mie.msie`, `mip.msip` and +// `mstatus.mie` are all 1, unless an external interrupt request +// is also valid at this time. +#define RVCSR_MIP_MSIP_RESET _u(0x0) +#define RVCSR_MIP_MSIP_BITS _u(0x00000008) +#define RVCSR_MIP_MSIP_MSB _u(3) +#define RVCSR_MIP_MSIP_LSB _u(3) +#define RVCSR_MIP_MSIP_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPCFG0 +// Description : Physical memory protection configuration for regions 0 through +// 3 +#define RVCSR_PMPCFG0_OFFSET _u(0x000003a0) +#define RVCSR_PMPCFG0_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_L +// Description : Lock region 3, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R3_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG0_R3_L_MSB _u(31) +#define RVCSR_PMPCFG0_R3_L_LSB _u(31) +#define RVCSR_PMPCFG0_R3_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_A +// Description : Address matching type for region 3. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R3_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG0_R3_A_MSB _u(28) +#define RVCSR_PMPCFG0_R3_A_LSB _u(27) +#define RVCSR_PMPCFG0_R3_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R3_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R3_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R3_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_R +// Description : Read permission for region 3. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R3_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG0_R3_R_MSB _u(26) +#define RVCSR_PMPCFG0_R3_R_LSB _u(26) +#define RVCSR_PMPCFG0_R3_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_W +// Description : Write permission for region 3 +#define RVCSR_PMPCFG0_R3_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG0_R3_W_MSB _u(25) +#define RVCSR_PMPCFG0_R3_W_LSB _u(25) +#define RVCSR_PMPCFG0_R3_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_X +// Description : Execute permission for region 3. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R3_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG0_R3_X_MSB _u(24) +#define RVCSR_PMPCFG0_R3_X_LSB _u(24) +#define RVCSR_PMPCFG0_R3_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_L +// Description : Lock region 2, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R2_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG0_R2_L_MSB _u(23) +#define RVCSR_PMPCFG0_R2_L_LSB _u(23) +#define RVCSR_PMPCFG0_R2_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_A +// Description : Address matching type for region 2. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R2_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG0_R2_A_MSB _u(20) +#define RVCSR_PMPCFG0_R2_A_LSB _u(19) +#define RVCSR_PMPCFG0_R2_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R2_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R2_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R2_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_R +// Description : Read permission for region 2. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R2_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG0_R2_R_MSB _u(18) +#define RVCSR_PMPCFG0_R2_R_LSB _u(18) +#define RVCSR_PMPCFG0_R2_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_W +// Description : Write permission for region 2 +#define RVCSR_PMPCFG0_R2_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG0_R2_W_MSB _u(17) +#define RVCSR_PMPCFG0_R2_W_LSB _u(17) +#define RVCSR_PMPCFG0_R2_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_X +// Description : Execute permission for region 2. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R2_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG0_R2_X_MSB _u(16) +#define RVCSR_PMPCFG0_R2_X_LSB _u(16) +#define RVCSR_PMPCFG0_R2_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_L +// Description : Lock region 1, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R1_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG0_R1_L_MSB _u(15) +#define RVCSR_PMPCFG0_R1_L_LSB _u(15) +#define RVCSR_PMPCFG0_R1_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_A +// Description : Address matching type for region 1. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R1_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG0_R1_A_MSB _u(12) +#define RVCSR_PMPCFG0_R1_A_LSB _u(11) +#define RVCSR_PMPCFG0_R1_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R1_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R1_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R1_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_R +// Description : Read permission for region 1. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R1_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG0_R1_R_MSB _u(10) +#define RVCSR_PMPCFG0_R1_R_LSB _u(10) +#define RVCSR_PMPCFG0_R1_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_W +// Description : Write permission for region 1 +#define RVCSR_PMPCFG0_R1_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG0_R1_W_MSB _u(9) +#define RVCSR_PMPCFG0_R1_W_LSB _u(9) +#define RVCSR_PMPCFG0_R1_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_X +// Description : Execute permission for region 1. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R1_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG0_R1_X_MSB _u(8) +#define RVCSR_PMPCFG0_R1_X_LSB _u(8) +#define RVCSR_PMPCFG0_R1_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_L +// Description : Lock region 0, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R0_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG0_R0_L_MSB _u(7) +#define RVCSR_PMPCFG0_R0_L_LSB _u(7) +#define RVCSR_PMPCFG0_R0_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_A +// Description : Address matching type for region 0. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R0_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG0_R0_A_MSB _u(4) +#define RVCSR_PMPCFG0_R0_A_LSB _u(3) +#define RVCSR_PMPCFG0_R0_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R0_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R0_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R0_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_R +// Description : Read permission for region 0. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R0_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG0_R0_R_MSB _u(2) +#define RVCSR_PMPCFG0_R0_R_LSB _u(2) +#define RVCSR_PMPCFG0_R0_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_W +// Description : Write permission for region 0 +#define RVCSR_PMPCFG0_R0_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG0_R0_W_MSB _u(1) +#define RVCSR_PMPCFG0_R0_W_LSB _u(1) +#define RVCSR_PMPCFG0_R0_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_X +// Description : Execute permission for region 0. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R0_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG0_R0_X_MSB _u(0) +#define RVCSR_PMPCFG0_R0_X_LSB _u(0) +#define RVCSR_PMPCFG0_R0_X_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPCFG1 +// Description : Physical memory protection configuration for regions 4 through +// 7 +#define RVCSR_PMPCFG1_OFFSET _u(0x000003a1) +#define RVCSR_PMPCFG1_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_L +// Description : Lock region 7, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R7_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG1_R7_L_MSB _u(31) +#define RVCSR_PMPCFG1_R7_L_LSB _u(31) +#define RVCSR_PMPCFG1_R7_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_A +// Description : Address matching type for region 7. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R7_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG1_R7_A_MSB _u(28) +#define RVCSR_PMPCFG1_R7_A_LSB _u(27) +#define RVCSR_PMPCFG1_R7_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R7_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R7_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R7_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_R +// Description : Read permission for region 7. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R7_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG1_R7_R_MSB _u(26) +#define RVCSR_PMPCFG1_R7_R_LSB _u(26) +#define RVCSR_PMPCFG1_R7_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_W +// Description : Write permission for region 7 +#define RVCSR_PMPCFG1_R7_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG1_R7_W_MSB _u(25) +#define RVCSR_PMPCFG1_R7_W_LSB _u(25) +#define RVCSR_PMPCFG1_R7_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_X +// Description : Execute permission for region 7. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R7_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG1_R7_X_MSB _u(24) +#define RVCSR_PMPCFG1_R7_X_LSB _u(24) +#define RVCSR_PMPCFG1_R7_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_L +// Description : Lock region 6, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R6_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG1_R6_L_MSB _u(23) +#define RVCSR_PMPCFG1_R6_L_LSB _u(23) +#define RVCSR_PMPCFG1_R6_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_A +// Description : Address matching type for region 6. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R6_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG1_R6_A_MSB _u(20) +#define RVCSR_PMPCFG1_R6_A_LSB _u(19) +#define RVCSR_PMPCFG1_R6_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R6_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R6_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R6_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_R +// Description : Read permission for region 6. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R6_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG1_R6_R_MSB _u(18) +#define RVCSR_PMPCFG1_R6_R_LSB _u(18) +#define RVCSR_PMPCFG1_R6_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_W +// Description : Write permission for region 6 +#define RVCSR_PMPCFG1_R6_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG1_R6_W_MSB _u(17) +#define RVCSR_PMPCFG1_R6_W_LSB _u(17) +#define RVCSR_PMPCFG1_R6_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_X +// Description : Execute permission for region 6. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R6_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG1_R6_X_MSB _u(16) +#define RVCSR_PMPCFG1_R6_X_LSB _u(16) +#define RVCSR_PMPCFG1_R6_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_L +// Description : Lock region 5, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R5_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG1_R5_L_MSB _u(15) +#define RVCSR_PMPCFG1_R5_L_LSB _u(15) +#define RVCSR_PMPCFG1_R5_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_A +// Description : Address matching type for region 5. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R5_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG1_R5_A_MSB _u(12) +#define RVCSR_PMPCFG1_R5_A_LSB _u(11) +#define RVCSR_PMPCFG1_R5_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R5_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R5_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R5_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_R +// Description : Read permission for region 5. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R5_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG1_R5_R_MSB _u(10) +#define RVCSR_PMPCFG1_R5_R_LSB _u(10) +#define RVCSR_PMPCFG1_R5_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_W +// Description : Write permission for region 5 +#define RVCSR_PMPCFG1_R5_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG1_R5_W_MSB _u(9) +#define RVCSR_PMPCFG1_R5_W_LSB _u(9) +#define RVCSR_PMPCFG1_R5_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_X +// Description : Execute permission for region 5. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R5_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG1_R5_X_MSB _u(8) +#define RVCSR_PMPCFG1_R5_X_LSB _u(8) +#define RVCSR_PMPCFG1_R5_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_L +// Description : Lock region 4, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R4_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG1_R4_L_MSB _u(7) +#define RVCSR_PMPCFG1_R4_L_LSB _u(7) +#define RVCSR_PMPCFG1_R4_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_A +// Description : Address matching type for region 4. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R4_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG1_R4_A_MSB _u(4) +#define RVCSR_PMPCFG1_R4_A_LSB _u(3) +#define RVCSR_PMPCFG1_R4_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R4_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R4_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R4_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_R +// Description : Read permission for region 4. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R4_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG1_R4_R_MSB _u(2) +#define RVCSR_PMPCFG1_R4_R_LSB _u(2) +#define RVCSR_PMPCFG1_R4_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_W +// Description : Write permission for region 4 +#define RVCSR_PMPCFG1_R4_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG1_R4_W_MSB _u(1) +#define RVCSR_PMPCFG1_R4_W_LSB _u(1) +#define RVCSR_PMPCFG1_R4_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_X +// Description : Execute permission for region 4. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R4_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG1_R4_X_MSB _u(0) +#define RVCSR_PMPCFG1_R4_X_LSB _u(0) +#define RVCSR_PMPCFG1_R4_X_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPCFG2 +// Description : Physical memory protection configuration for regions 8 through +// 11 +#define RVCSR_PMPCFG2_OFFSET _u(0x000003a2) +#define RVCSR_PMPCFG2_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG2_RESET _u(0x001f1f1f) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_L +// Description : Lock region 11, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R11_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG2_R11_L_MSB _u(31) +#define RVCSR_PMPCFG2_R11_L_LSB _u(31) +#define RVCSR_PMPCFG2_R11_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_A +// Description : Address matching type for region 11. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R11_A_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG2_R11_A_MSB _u(28) +#define RVCSR_PMPCFG2_R11_A_LSB _u(27) +#define RVCSR_PMPCFG2_R11_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R11_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R11_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R11_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_R +// Description : Read permission for region 11. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R11_R_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG2_R11_R_MSB _u(26) +#define RVCSR_PMPCFG2_R11_R_LSB _u(26) +#define RVCSR_PMPCFG2_R11_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_W +// Description : Write permission for region 11 +#define RVCSR_PMPCFG2_R11_W_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG2_R11_W_MSB _u(25) +#define RVCSR_PMPCFG2_R11_W_LSB _u(25) +#define RVCSR_PMPCFG2_R11_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_X +// Description : Execute permission for region 11. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R11_X_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG2_R11_X_MSB _u(24) +#define RVCSR_PMPCFG2_R11_X_LSB _u(24) +#define RVCSR_PMPCFG2_R11_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_L +// Description : Lock region 10, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R10_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R10_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG2_R10_L_MSB _u(23) +#define RVCSR_PMPCFG2_R10_L_LSB _u(23) +#define RVCSR_PMPCFG2_R10_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_A +// Description : Address matching type for region 10. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R10_A_RESET _u(0x3) +#define RVCSR_PMPCFG2_R10_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG2_R10_A_MSB _u(20) +#define RVCSR_PMPCFG2_R10_A_LSB _u(19) +#define RVCSR_PMPCFG2_R10_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R10_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R10_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R10_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_R +// Description : Read permission for region 10. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R10_R_RESET _u(0x1) +#define RVCSR_PMPCFG2_R10_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG2_R10_R_MSB _u(18) +#define RVCSR_PMPCFG2_R10_R_LSB _u(18) +#define RVCSR_PMPCFG2_R10_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_W +// Description : Write permission for region 10 +#define RVCSR_PMPCFG2_R10_W_RESET _u(0x1) +#define RVCSR_PMPCFG2_R10_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG2_R10_W_MSB _u(17) +#define RVCSR_PMPCFG2_R10_W_LSB _u(17) +#define RVCSR_PMPCFG2_R10_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_X +// Description : Execute permission for region 10. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R10_X_RESET _u(0x1) +#define RVCSR_PMPCFG2_R10_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG2_R10_X_MSB _u(16) +#define RVCSR_PMPCFG2_R10_X_LSB _u(16) +#define RVCSR_PMPCFG2_R10_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_L +// Description : Lock region 9, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R9_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R9_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG2_R9_L_MSB _u(15) +#define RVCSR_PMPCFG2_R9_L_LSB _u(15) +#define RVCSR_PMPCFG2_R9_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_A +// Description : Address matching type for region 9. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R9_A_RESET _u(0x3) +#define RVCSR_PMPCFG2_R9_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG2_R9_A_MSB _u(12) +#define RVCSR_PMPCFG2_R9_A_LSB _u(11) +#define RVCSR_PMPCFG2_R9_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R9_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R9_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R9_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_R +// Description : Read permission for region 9. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R9_R_RESET _u(0x1) +#define RVCSR_PMPCFG2_R9_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG2_R9_R_MSB _u(10) +#define RVCSR_PMPCFG2_R9_R_LSB _u(10) +#define RVCSR_PMPCFG2_R9_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_W +// Description : Write permission for region 9 +#define RVCSR_PMPCFG2_R9_W_RESET _u(0x1) +#define RVCSR_PMPCFG2_R9_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG2_R9_W_MSB _u(9) +#define RVCSR_PMPCFG2_R9_W_LSB _u(9) +#define RVCSR_PMPCFG2_R9_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_X +// Description : Execute permission for region 9. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R9_X_RESET _u(0x1) +#define RVCSR_PMPCFG2_R9_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG2_R9_X_MSB _u(8) +#define RVCSR_PMPCFG2_R9_X_LSB _u(8) +#define RVCSR_PMPCFG2_R9_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_L +// Description : Lock region 8, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R8_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R8_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG2_R8_L_MSB _u(7) +#define RVCSR_PMPCFG2_R8_L_LSB _u(7) +#define RVCSR_PMPCFG2_R8_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_A +// Description : Address matching type for region 8. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R8_A_RESET _u(0x3) +#define RVCSR_PMPCFG2_R8_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG2_R8_A_MSB _u(4) +#define RVCSR_PMPCFG2_R8_A_LSB _u(3) +#define RVCSR_PMPCFG2_R8_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R8_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R8_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R8_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_R +// Description : Read permission for region 8. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R8_R_RESET _u(0x1) +#define RVCSR_PMPCFG2_R8_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG2_R8_R_MSB _u(2) +#define RVCSR_PMPCFG2_R8_R_LSB _u(2) +#define RVCSR_PMPCFG2_R8_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_W +// Description : Write permission for region 8 +#define RVCSR_PMPCFG2_R8_W_RESET _u(0x1) +#define RVCSR_PMPCFG2_R8_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG2_R8_W_MSB _u(1) +#define RVCSR_PMPCFG2_R8_W_LSB _u(1) +#define RVCSR_PMPCFG2_R8_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_X +// Description : Execute permission for region 8. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R8_X_RESET _u(0x1) +#define RVCSR_PMPCFG2_R8_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG2_R8_X_MSB _u(0) +#define RVCSR_PMPCFG2_R8_X_LSB _u(0) +#define RVCSR_PMPCFG2_R8_X_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPCFG3 +// Description : Physical memory protection configuration for regions 12 through +// 15 +#define RVCSR_PMPCFG3_OFFSET _u(0x000003a3) +#define RVCSR_PMPCFG3_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_L +// Description : Lock region 15, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R15_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG3_R15_L_MSB _u(31) +#define RVCSR_PMPCFG3_R15_L_LSB _u(31) +#define RVCSR_PMPCFG3_R15_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_A +// Description : Address matching type for region 15. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R15_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG3_R15_A_MSB _u(28) +#define RVCSR_PMPCFG3_R15_A_LSB _u(27) +#define RVCSR_PMPCFG3_R15_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R15_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R15_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R15_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_R +// Description : Read permission for region 15. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R15_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG3_R15_R_MSB _u(26) +#define RVCSR_PMPCFG3_R15_R_LSB _u(26) +#define RVCSR_PMPCFG3_R15_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_W +// Description : Write permission for region 15 +#define RVCSR_PMPCFG3_R15_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG3_R15_W_MSB _u(25) +#define RVCSR_PMPCFG3_R15_W_LSB _u(25) +#define RVCSR_PMPCFG3_R15_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_X +// Description : Execute permission for region 15. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R15_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG3_R15_X_MSB _u(24) +#define RVCSR_PMPCFG3_R15_X_LSB _u(24) +#define RVCSR_PMPCFG3_R15_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_L +// Description : Lock region 14, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R14_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG3_R14_L_MSB _u(23) +#define RVCSR_PMPCFG3_R14_L_LSB _u(23) +#define RVCSR_PMPCFG3_R14_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_A +// Description : Address matching type for region 14. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R14_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG3_R14_A_MSB _u(20) +#define RVCSR_PMPCFG3_R14_A_LSB _u(19) +#define RVCSR_PMPCFG3_R14_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R14_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R14_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R14_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_R +// Description : Read permission for region 14. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R14_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG3_R14_R_MSB _u(18) +#define RVCSR_PMPCFG3_R14_R_LSB _u(18) +#define RVCSR_PMPCFG3_R14_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_W +// Description : Write permission for region 14 +#define RVCSR_PMPCFG3_R14_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG3_R14_W_MSB _u(17) +#define RVCSR_PMPCFG3_R14_W_LSB _u(17) +#define RVCSR_PMPCFG3_R14_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_X +// Description : Execute permission for region 14. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R14_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG3_R14_X_MSB _u(16) +#define RVCSR_PMPCFG3_R14_X_LSB _u(16) +#define RVCSR_PMPCFG3_R14_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_L +// Description : Lock region 13, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R13_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG3_R13_L_MSB _u(15) +#define RVCSR_PMPCFG3_R13_L_LSB _u(15) +#define RVCSR_PMPCFG3_R13_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_A +// Description : Address matching type for region 13. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R13_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG3_R13_A_MSB _u(12) +#define RVCSR_PMPCFG3_R13_A_LSB _u(11) +#define RVCSR_PMPCFG3_R13_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R13_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R13_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R13_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_R +// Description : Read permission for region 13. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R13_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG3_R13_R_MSB _u(10) +#define RVCSR_PMPCFG3_R13_R_LSB _u(10) +#define RVCSR_PMPCFG3_R13_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_W +// Description : Write permission for region 13 +#define RVCSR_PMPCFG3_R13_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG3_R13_W_MSB _u(9) +#define RVCSR_PMPCFG3_R13_W_LSB _u(9) +#define RVCSR_PMPCFG3_R13_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_X +// Description : Execute permission for region 13. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R13_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG3_R13_X_MSB _u(8) +#define RVCSR_PMPCFG3_R13_X_LSB _u(8) +#define RVCSR_PMPCFG3_R13_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_L +// Description : Lock region 12, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R12_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG3_R12_L_MSB _u(7) +#define RVCSR_PMPCFG3_R12_L_LSB _u(7) +#define RVCSR_PMPCFG3_R12_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_A +// Description : Address matching type for region 12. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R12_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG3_R12_A_MSB _u(4) +#define RVCSR_PMPCFG3_R12_A_LSB _u(3) +#define RVCSR_PMPCFG3_R12_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R12_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R12_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R12_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_R +// Description : Read permission for region 12. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R12_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG3_R12_R_MSB _u(2) +#define RVCSR_PMPCFG3_R12_R_LSB _u(2) +#define RVCSR_PMPCFG3_R12_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_W +// Description : Write permission for region 12 +#define RVCSR_PMPCFG3_R12_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG3_R12_W_MSB _u(1) +#define RVCSR_PMPCFG3_R12_W_LSB _u(1) +#define RVCSR_PMPCFG3_R12_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_X +// Description : Execute permission for region 12. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R12_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG3_R12_X_MSB _u(0) +#define RVCSR_PMPCFG3_R12_X_LSB _u(0) +#define RVCSR_PMPCFG3_R12_X_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR0 +// Description : Physical memory protection address for region 0. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR0_OFFSET _u(0x000003b0) +#define RVCSR_PMPADDR0_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR0_RESET _u(0x00000000) +#define RVCSR_PMPADDR0_MSB _u(29) +#define RVCSR_PMPADDR0_LSB _u(0) +#define RVCSR_PMPADDR0_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR1 +// Description : Physical memory protection address for region 1. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR1_OFFSET _u(0x000003b1) +#define RVCSR_PMPADDR1_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR1_RESET _u(0x00000000) +#define RVCSR_PMPADDR1_MSB _u(29) +#define RVCSR_PMPADDR1_LSB _u(0) +#define RVCSR_PMPADDR1_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR2 +// Description : Physical memory protection address for region 2. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR2_OFFSET _u(0x000003b2) +#define RVCSR_PMPADDR2_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR2_RESET _u(0x00000000) +#define RVCSR_PMPADDR2_MSB _u(29) +#define RVCSR_PMPADDR2_LSB _u(0) +#define RVCSR_PMPADDR2_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR3 +// Description : Physical memory protection address for region 3. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR3_OFFSET _u(0x000003b3) +#define RVCSR_PMPADDR3_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR3_RESET _u(0x00000000) +#define RVCSR_PMPADDR3_MSB _u(29) +#define RVCSR_PMPADDR3_LSB _u(0) +#define RVCSR_PMPADDR3_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR4 +// Description : Physical memory protection address for region 4. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR4_OFFSET _u(0x000003b4) +#define RVCSR_PMPADDR4_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR4_RESET _u(0x00000000) +#define RVCSR_PMPADDR4_MSB _u(29) +#define RVCSR_PMPADDR4_LSB _u(0) +#define RVCSR_PMPADDR4_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR5 +// Description : Physical memory protection address for region 5. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR5_OFFSET _u(0x000003b5) +#define RVCSR_PMPADDR5_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR5_RESET _u(0x00000000) +#define RVCSR_PMPADDR5_MSB _u(29) +#define RVCSR_PMPADDR5_LSB _u(0) +#define RVCSR_PMPADDR5_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR6 +// Description : Physical memory protection address for region 6. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR6_OFFSET _u(0x000003b6) +#define RVCSR_PMPADDR6_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR6_RESET _u(0x00000000) +#define RVCSR_PMPADDR6_MSB _u(29) +#define RVCSR_PMPADDR6_LSB _u(0) +#define RVCSR_PMPADDR6_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR7 +// Description : Physical memory protection address for region 7. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR7_OFFSET _u(0x000003b7) +#define RVCSR_PMPADDR7_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR7_RESET _u(0x00000000) +#define RVCSR_PMPADDR7_MSB _u(29) +#define RVCSR_PMPADDR7_LSB _u(0) +#define RVCSR_PMPADDR7_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR8 +// Description : Physical memory protection address for region 8. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to the address range `0x00000000` through +// `0x0fffffff`, which contains the boot ROM. This range is made +// accessible to User mode by default. User mode access to this +// range can be disabled using one of the dynamically configurable +// PMP regions, or using the permission registers in ACCESSCTRL. +#define RVCSR_PMPADDR8_OFFSET _u(0x000003b8) +#define RVCSR_PMPADDR8_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR8_RESET _u(0x01ffffff) +#define RVCSR_PMPADDR8_MSB _u(29) +#define RVCSR_PMPADDR8_LSB _u(0) +#define RVCSR_PMPADDR8_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR9 +// Description : Physical memory protection address for region 9. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to the address range `0x40000000` through +// `0x5fffffff`, which contains the system peripherals. This range +// is made accessible to User mode by default. User mode access to +// this range can be disabled using one of the dynamically +// configurable PMP regions, or using the permission registers in +// ACCESSCTRL. +#define RVCSR_PMPADDR9_OFFSET _u(0x000003b9) +#define RVCSR_PMPADDR9_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR9_RESET _u(0x13ffffff) +#define RVCSR_PMPADDR9_MSB _u(29) +#define RVCSR_PMPADDR9_LSB _u(0) +#define RVCSR_PMPADDR9_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR10 +// Description : Physical memory protection address for region 10. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to the address range `0xd0000000` through +// `0xdfffffff`, which contains the core-local peripherals (SIO). +// This range is made accessible to User mode by default. User +// mode access to this range can be disabled using one of the +// dynamically configurable PMP regions, or using the permission +// registers in ACCESSCTRL. +#define RVCSR_PMPADDR10_OFFSET _u(0x000003ba) +#define RVCSR_PMPADDR10_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR10_RESET _u(0x35ffffff) +#define RVCSR_PMPADDR10_MSB _u(29) +#define RVCSR_PMPADDR10_LSB _u(0) +#define RVCSR_PMPADDR10_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR11 +// Description : Physical memory protection address for region 11. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR11_OFFSET _u(0x000003bb) +#define RVCSR_PMPADDR11_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR11_RESET _u(0x00000000) +#define RVCSR_PMPADDR11_MSB _u(29) +#define RVCSR_PMPADDR11_LSB _u(0) +#define RVCSR_PMPADDR11_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR12 +// Description : Physical memory protection address for region 12. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR12_OFFSET _u(0x000003bc) +#define RVCSR_PMPADDR12_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR12_RESET _u(0x00000000) +#define RVCSR_PMPADDR12_MSB _u(29) +#define RVCSR_PMPADDR12_LSB _u(0) +#define RVCSR_PMPADDR12_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR13 +// Description : Physical memory protection address for region 13. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR13_OFFSET _u(0x000003bd) +#define RVCSR_PMPADDR13_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR13_RESET _u(0x00000000) +#define RVCSR_PMPADDR13_MSB _u(29) +#define RVCSR_PMPADDR13_LSB _u(0) +#define RVCSR_PMPADDR13_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR14 +// Description : Physical memory protection address for region 14. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR14_OFFSET _u(0x000003be) +#define RVCSR_PMPADDR14_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR14_RESET _u(0x00000000) +#define RVCSR_PMPADDR14_MSB _u(29) +#define RVCSR_PMPADDR14_LSB _u(0) +#define RVCSR_PMPADDR14_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR15 +// Description : Physical memory protection address for region 15. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR15_OFFSET _u(0x000003bf) +#define RVCSR_PMPADDR15_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR15_RESET _u(0x00000000) +#define RVCSR_PMPADDR15_MSB _u(29) +#define RVCSR_PMPADDR15_LSB _u(0) +#define RVCSR_PMPADDR15_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_TSELECT +// Description : Select trigger to be configured via `tdata1`/`tdata2` +// +// On RP2350, four instruction address triggers are implemented, +// so only the two LSBs of this register are writable. +#define RVCSR_TSELECT_OFFSET _u(0x000007a0) +#define RVCSR_TSELECT_BITS _u(0x00000003) +#define RVCSR_TSELECT_RESET _u(0x00000000) +#define RVCSR_TSELECT_MSB _u(1) +#define RVCSR_TSELECT_LSB _u(0) +#define RVCSR_TSELECT_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_TDATA1 +// Description : Trigger configuration data 1 +// +// Hazard 3 only supports address/data match triggers (type=2) so +// this register description includes the `mcontrol` fields for +// this type. +// +// More precisely, Hazard3 only supports exact instruction address +// match triggers (hardware breakpoints) so many of this +// register's fields are hardwired. +#define RVCSR_TDATA1_OFFSET _u(0x000007a1) +#define RVCSR_TDATA1_BITS _u(0xffffffcf) +#define RVCSR_TDATA1_RESET _u(0x20000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_TYPE +// Description : Trigger type. Hardwired to type=2, meaning an address/data +// match trigger +#define RVCSR_TDATA1_TYPE_RESET _u(0x2) +#define RVCSR_TDATA1_TYPE_BITS _u(0xf0000000) +#define RVCSR_TDATA1_TYPE_MSB _u(31) +#define RVCSR_TDATA1_TYPE_LSB _u(28) +#define RVCSR_TDATA1_TYPE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_DMODE +// Description : If 0, both Debug and M-mode can write the `tdata` registers at +// the selected `tselect`. +// +// If 1, only Debug Mode can write the `tdata` registers at the +// selected `tselect`. Writes from other modes are ignored. +// +// This bit is only writable from Debug Mode +#define RVCSR_TDATA1_DMODE_RESET _u(0x0) +#define RVCSR_TDATA1_DMODE_BITS _u(0x08000000) +#define RVCSR_TDATA1_DMODE_MSB _u(27) +#define RVCSR_TDATA1_DMODE_LSB _u(27) +#define RVCSR_TDATA1_DMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_MASKMAX +// Description : Value of 0 indicates only exact address matches are supported +#define RVCSR_TDATA1_MASKMAX_RESET _u(0x00) +#define RVCSR_TDATA1_MASKMAX_BITS _u(0x07e00000) +#define RVCSR_TDATA1_MASKMAX_MSB _u(26) +#define RVCSR_TDATA1_MASKMAX_LSB _u(21) +#define RVCSR_TDATA1_MASKMAX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_HIT +// Description : Trigger hit flag. Not implemented, hardwired to 0. +#define RVCSR_TDATA1_HIT_RESET _u(0x0) +#define RVCSR_TDATA1_HIT_BITS _u(0x00100000) +#define RVCSR_TDATA1_HIT_MSB _u(20) +#define RVCSR_TDATA1_HIT_LSB _u(20) +#define RVCSR_TDATA1_HIT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_SELECT +// Description : Hardwired value of 0 indicates that only address matches are +// supported, not data matches +#define RVCSR_TDATA1_SELECT_RESET _u(0x0) +#define RVCSR_TDATA1_SELECT_BITS _u(0x00080000) +#define RVCSR_TDATA1_SELECT_MSB _u(19) +#define RVCSR_TDATA1_SELECT_LSB _u(19) +#define RVCSR_TDATA1_SELECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_TIMING +// Description : Hardwired value of 0 indicates that trigger fires before the +// triggering instruction executes, not afterward +#define RVCSR_TDATA1_TIMING_RESET _u(0x0) +#define RVCSR_TDATA1_TIMING_BITS _u(0x00040000) +#define RVCSR_TDATA1_TIMING_MSB _u(18) +#define RVCSR_TDATA1_TIMING_LSB _u(18) +#define RVCSR_TDATA1_TIMING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_SIZELO +// Description : Hardwired value of 0 indicates that access size matching is not +// supported +#define RVCSR_TDATA1_SIZELO_RESET _u(0x0) +#define RVCSR_TDATA1_SIZELO_BITS _u(0x00030000) +#define RVCSR_TDATA1_SIZELO_MSB _u(17) +#define RVCSR_TDATA1_SIZELO_LSB _u(16) +#define RVCSR_TDATA1_SIZELO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_ACTION +// Description : Select action to be taken when the trigger fires. +// 0x0 -> Raise a breakpoint exception, which can be handled by the M-mode exception handler +// 0x1 -> Enter debug mode. This action is only selectable when `tdata1.dmode` is 1. +#define RVCSR_TDATA1_ACTION_RESET _u(0x0) +#define RVCSR_TDATA1_ACTION_BITS _u(0x0000f000) +#define RVCSR_TDATA1_ACTION_MSB _u(15) +#define RVCSR_TDATA1_ACTION_LSB _u(12) +#define RVCSR_TDATA1_ACTION_ACCESS "RW" +#define RVCSR_TDATA1_ACTION_VALUE_EBREAK _u(0x0) +#define RVCSR_TDATA1_ACTION_VALUE_DEBUG _u(0x1) +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_CHAIN +// Description : Hardwired to 0 to indicate trigger chaining is not supported. +#define RVCSR_TDATA1_CHAIN_RESET _u(0x0) +#define RVCSR_TDATA1_CHAIN_BITS _u(0x00000800) +#define RVCSR_TDATA1_CHAIN_MSB _u(11) +#define RVCSR_TDATA1_CHAIN_LSB _u(11) +#define RVCSR_TDATA1_CHAIN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_MATCH +// Description : Hardwired to 0 to indicate match is always on the full address +// specified by `tdata2` +#define RVCSR_TDATA1_MATCH_RESET _u(0x0) +#define RVCSR_TDATA1_MATCH_BITS _u(0x00000780) +#define RVCSR_TDATA1_MATCH_MSB _u(10) +#define RVCSR_TDATA1_MATCH_LSB _u(7) +#define RVCSR_TDATA1_MATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_M +// Description : When set, enable this trigger in M-mode +#define RVCSR_TDATA1_M_RESET _u(0x0) +#define RVCSR_TDATA1_M_BITS _u(0x00000040) +#define RVCSR_TDATA1_M_MSB _u(6) +#define RVCSR_TDATA1_M_LSB _u(6) +#define RVCSR_TDATA1_M_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_U +// Description : When set, enable this trigger in U-mode +#define RVCSR_TDATA1_U_RESET _u(0x0) +#define RVCSR_TDATA1_U_BITS _u(0x00000008) +#define RVCSR_TDATA1_U_MSB _u(3) +#define RVCSR_TDATA1_U_LSB _u(3) +#define RVCSR_TDATA1_U_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_EXECUTE +// Description : When set, the trigger fires on the address of an instruction +// that is executed. +#define RVCSR_TDATA1_EXECUTE_RESET _u(0x0) +#define RVCSR_TDATA1_EXECUTE_BITS _u(0x00000004) +#define RVCSR_TDATA1_EXECUTE_MSB _u(2) +#define RVCSR_TDATA1_EXECUTE_LSB _u(2) +#define RVCSR_TDATA1_EXECUTE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_STORE +// Description : Hardwired to 0 to indicate store address/data triggers are not +// supported +#define RVCSR_TDATA1_STORE_RESET _u(0x0) +#define RVCSR_TDATA1_STORE_BITS _u(0x00000002) +#define RVCSR_TDATA1_STORE_MSB _u(1) +#define RVCSR_TDATA1_STORE_LSB _u(1) +#define RVCSR_TDATA1_STORE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_LOAD +// Description : Hardwired to 0 to indicate load address/data triggers are not +// supported +#define RVCSR_TDATA1_LOAD_RESET _u(0x0) +#define RVCSR_TDATA1_LOAD_BITS _u(0x00000001) +#define RVCSR_TDATA1_LOAD_MSB _u(0) +#define RVCSR_TDATA1_LOAD_LSB _u(0) +#define RVCSR_TDATA1_LOAD_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_TDATA2 +// Description : Trigger configuration data 2 +// +// Contains the address for instruction address triggers (hardware +// breakpoints) +#define RVCSR_TDATA2_OFFSET _u(0x000007a2) +#define RVCSR_TDATA2_BITS _u(0xffffffff) +#define RVCSR_TDATA2_RESET _u(0x00000000) +#define RVCSR_TDATA2_MSB _u(31) +#define RVCSR_TDATA2_LSB _u(0) +#define RVCSR_TDATA2_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_DCSR +// Description : Debug control and status register. Access outside of Debug Mode +// will cause an illegal instruction exception. +#define RVCSR_DCSR_OFFSET _u(0x000007b0) +#define RVCSR_DCSR_BITS _u(0xf0009fc7) +#define RVCSR_DCSR_RESET _u(0x40000603) +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_XDEBUGVER +// Description : Hardwired to 4: external debug support as per RISC-V 0.13.2 +// debug specification. +#define RVCSR_DCSR_XDEBUGVER_RESET _u(0x4) +#define RVCSR_DCSR_XDEBUGVER_BITS _u(0xf0000000) +#define RVCSR_DCSR_XDEBUGVER_MSB _u(31) +#define RVCSR_DCSR_XDEBUGVER_LSB _u(28) +#define RVCSR_DCSR_XDEBUGVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_EBREAKM +// Description : When 1, `ebreak` instructions executed in M-mode will break to +// Debug Mode instead of trapping +#define RVCSR_DCSR_EBREAKM_RESET _u(0x0) +#define RVCSR_DCSR_EBREAKM_BITS _u(0x00008000) +#define RVCSR_DCSR_EBREAKM_MSB _u(15) +#define RVCSR_DCSR_EBREAKM_LSB _u(15) +#define RVCSR_DCSR_EBREAKM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_EBREAKU +// Description : When 1, `ebreak` instructions executed in U-mode will break to +// Debug Mode instead of trapping. +#define RVCSR_DCSR_EBREAKU_RESET _u(0x0) +#define RVCSR_DCSR_EBREAKU_BITS _u(0x00001000) +#define RVCSR_DCSR_EBREAKU_MSB _u(12) +#define RVCSR_DCSR_EBREAKU_LSB _u(12) +#define RVCSR_DCSR_EBREAKU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STEPIE +// Description : Hardwired to 0: no interrupts are taken during hardware single- +// stepping. +#define RVCSR_DCSR_STEPIE_RESET _u(0x0) +#define RVCSR_DCSR_STEPIE_BITS _u(0x00000800) +#define RVCSR_DCSR_STEPIE_MSB _u(11) +#define RVCSR_DCSR_STEPIE_LSB _u(11) +#define RVCSR_DCSR_STEPIE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STOPCOUNT +// Description : Hardwired to 1: `mcycle`/`mcycleh` and `minstret`/`minstreth` +// do not increment in Debug Mode. +#define RVCSR_DCSR_STOPCOUNT_RESET _u(0x1) +#define RVCSR_DCSR_STOPCOUNT_BITS _u(0x00000400) +#define RVCSR_DCSR_STOPCOUNT_MSB _u(10) +#define RVCSR_DCSR_STOPCOUNT_LSB _u(10) +#define RVCSR_DCSR_STOPCOUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STOPTIME +// Description : Hardwired to 1: core-local timers don't increment in debug +// mode. External timers (e.g. hart-shared) may be configured to +// ignore this. +#define RVCSR_DCSR_STOPTIME_RESET _u(0x1) +#define RVCSR_DCSR_STOPTIME_BITS _u(0x00000200) +#define RVCSR_DCSR_STOPTIME_MSB _u(9) +#define RVCSR_DCSR_STOPTIME_LSB _u(9) +#define RVCSR_DCSR_STOPTIME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_CAUSE +// Description : Set by hardware when entering debug mode. +// 0x1 -> An ebreak instruction was executed when the relevant `dcsr.ebreakx` bit was set. +// 0x2 -> The trigger module caused a breakpoint exception. +// 0x3 -> Processor entered Debug Mode due to a halt request, or a reset-halt request present when the core reset was released. +// 0x4 -> Processor entered Debug Mode after executing one instruction with single-stepping enabled. +#define RVCSR_DCSR_CAUSE_RESET _u(0x0) +#define RVCSR_DCSR_CAUSE_BITS _u(0x000001c0) +#define RVCSR_DCSR_CAUSE_MSB _u(8) +#define RVCSR_DCSR_CAUSE_LSB _u(6) +#define RVCSR_DCSR_CAUSE_ACCESS "RO" +#define RVCSR_DCSR_CAUSE_VALUE_EBREAK _u(0x1) +#define RVCSR_DCSR_CAUSE_VALUE_TRIGGER _u(0x2) +#define RVCSR_DCSR_CAUSE_VALUE_HALTREQ _u(0x3) +#define RVCSR_DCSR_CAUSE_VALUE_STEP _u(0x4) +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STEP +// Description : When 1, re-enter Debug Mode after each instruction executed in +// M-mode or U-mode. +#define RVCSR_DCSR_STEP_RESET _u(0x0) +#define RVCSR_DCSR_STEP_BITS _u(0x00000004) +#define RVCSR_DCSR_STEP_MSB _u(2) +#define RVCSR_DCSR_STEP_LSB _u(2) +#define RVCSR_DCSR_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_PRV +// Description : Read the privilege mode the core was in when entering Debug +// Mode, and set the privilege mode the core will execute in when +// returning from Debug Mode. +#define RVCSR_DCSR_PRV_RESET _u(0x3) +#define RVCSR_DCSR_PRV_BITS _u(0x00000003) +#define RVCSR_DCSR_PRV_MSB _u(1) +#define RVCSR_DCSR_PRV_LSB _u(0) +#define RVCSR_DCSR_PRV_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_DPC +// Description : Debug program counter. When entering Debug Mode, `dpc` samples +// the current program counter, e.g. the address of an `ebreak` +// which caused Debug Mode entry. When leaving debug mode, the +// processor jumps to `dpc`. The host may read/write this register +// whilst in Debug Mode. +#define RVCSR_DPC_OFFSET _u(0x000007b1) +#define RVCSR_DPC_BITS _u(0xfffffffe) +#define RVCSR_DPC_RESET _u(0x00000000) +#define RVCSR_DPC_MSB _u(31) +#define RVCSR_DPC_LSB _u(1) +#define RVCSR_DPC_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MCYCLE +// Description : Machine-mode cycle counter, low half +// Counts up once per cycle, when `mcountinhibit.cy` is 0. +// Disabled by default to save power. +#define RVCSR_MCYCLE_OFFSET _u(0x00000b00) +#define RVCSR_MCYCLE_BITS _u(0xffffffff) +#define RVCSR_MCYCLE_RESET _u(0x00000000) +#define RVCSR_MCYCLE_MSB _u(31) +#define RVCSR_MCYCLE_LSB _u(0) +#define RVCSR_MCYCLE_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MINSTRET +// Description : Machine-mode instruction retire counter, low half +// Counts up once per instruction, when `mcountinhibit.ir` is 0. +// Disabled by default to save power. +#define RVCSR_MINSTRET_OFFSET _u(0x00000b02) +#define RVCSR_MINSTRET_BITS _u(0xffffffff) +#define RVCSR_MINSTRET_RESET _u(0x00000000) +#define RVCSR_MINSTRET_MSB _u(31) +#define RVCSR_MINSTRET_LSB _u(0) +#define RVCSR_MINSTRET_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER3 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER3_OFFSET _u(0x00000b03) +#define RVCSR_MHPMCOUNTER3_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER3_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER3_MSB _u(31) +#define RVCSR_MHPMCOUNTER3_LSB _u(0) +#define RVCSR_MHPMCOUNTER3_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER4 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER4_OFFSET _u(0x00000b04) +#define RVCSR_MHPMCOUNTER4_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER4_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER4_MSB _u(31) +#define RVCSR_MHPMCOUNTER4_LSB _u(0) +#define RVCSR_MHPMCOUNTER4_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER5 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER5_OFFSET _u(0x00000b05) +#define RVCSR_MHPMCOUNTER5_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER5_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER5_MSB _u(31) +#define RVCSR_MHPMCOUNTER5_LSB _u(0) +#define RVCSR_MHPMCOUNTER5_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER6 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER6_OFFSET _u(0x00000b06) +#define RVCSR_MHPMCOUNTER6_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER6_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER6_MSB _u(31) +#define RVCSR_MHPMCOUNTER6_LSB _u(0) +#define RVCSR_MHPMCOUNTER6_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER7 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER7_OFFSET _u(0x00000b07) +#define RVCSR_MHPMCOUNTER7_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER7_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER7_MSB _u(31) +#define RVCSR_MHPMCOUNTER7_LSB _u(0) +#define RVCSR_MHPMCOUNTER7_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER8 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER8_OFFSET _u(0x00000b08) +#define RVCSR_MHPMCOUNTER8_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER8_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER8_MSB _u(31) +#define RVCSR_MHPMCOUNTER8_LSB _u(0) +#define RVCSR_MHPMCOUNTER8_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER9 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER9_OFFSET _u(0x00000b09) +#define RVCSR_MHPMCOUNTER9_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER9_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER9_MSB _u(31) +#define RVCSR_MHPMCOUNTER9_LSB _u(0) +#define RVCSR_MHPMCOUNTER9_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER10 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER10_OFFSET _u(0x00000b0a) +#define RVCSR_MHPMCOUNTER10_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER10_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER10_MSB _u(31) +#define RVCSR_MHPMCOUNTER10_LSB _u(0) +#define RVCSR_MHPMCOUNTER10_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER11 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER11_OFFSET _u(0x00000b0b) +#define RVCSR_MHPMCOUNTER11_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER11_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER11_MSB _u(31) +#define RVCSR_MHPMCOUNTER11_LSB _u(0) +#define RVCSR_MHPMCOUNTER11_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER12 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER12_OFFSET _u(0x00000b0c) +#define RVCSR_MHPMCOUNTER12_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER12_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER12_MSB _u(31) +#define RVCSR_MHPMCOUNTER12_LSB _u(0) +#define RVCSR_MHPMCOUNTER12_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER13 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER13_OFFSET _u(0x00000b0d) +#define RVCSR_MHPMCOUNTER13_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER13_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER13_MSB _u(31) +#define RVCSR_MHPMCOUNTER13_LSB _u(0) +#define RVCSR_MHPMCOUNTER13_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER14 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER14_OFFSET _u(0x00000b0e) +#define RVCSR_MHPMCOUNTER14_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER14_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER14_MSB _u(31) +#define RVCSR_MHPMCOUNTER14_LSB _u(0) +#define RVCSR_MHPMCOUNTER14_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER15 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER15_OFFSET _u(0x00000b0f) +#define RVCSR_MHPMCOUNTER15_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER15_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER15_MSB _u(31) +#define RVCSR_MHPMCOUNTER15_LSB _u(0) +#define RVCSR_MHPMCOUNTER15_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER16 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER16_OFFSET _u(0x00000b10) +#define RVCSR_MHPMCOUNTER16_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER16_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER16_MSB _u(31) +#define RVCSR_MHPMCOUNTER16_LSB _u(0) +#define RVCSR_MHPMCOUNTER16_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER17 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER17_OFFSET _u(0x00000b11) +#define RVCSR_MHPMCOUNTER17_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER17_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER17_MSB _u(31) +#define RVCSR_MHPMCOUNTER17_LSB _u(0) +#define RVCSR_MHPMCOUNTER17_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER18 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER18_OFFSET _u(0x00000b12) +#define RVCSR_MHPMCOUNTER18_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER18_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER18_MSB _u(31) +#define RVCSR_MHPMCOUNTER18_LSB _u(0) +#define RVCSR_MHPMCOUNTER18_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER19 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER19_OFFSET _u(0x00000b13) +#define RVCSR_MHPMCOUNTER19_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER19_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER19_MSB _u(31) +#define RVCSR_MHPMCOUNTER19_LSB _u(0) +#define RVCSR_MHPMCOUNTER19_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER20 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER20_OFFSET _u(0x00000b14) +#define RVCSR_MHPMCOUNTER20_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER20_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER20_MSB _u(31) +#define RVCSR_MHPMCOUNTER20_LSB _u(0) +#define RVCSR_MHPMCOUNTER20_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER21 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER21_OFFSET _u(0x00000b15) +#define RVCSR_MHPMCOUNTER21_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER21_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER21_MSB _u(31) +#define RVCSR_MHPMCOUNTER21_LSB _u(0) +#define RVCSR_MHPMCOUNTER21_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER22 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER22_OFFSET _u(0x00000b16) +#define RVCSR_MHPMCOUNTER22_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER22_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER22_MSB _u(31) +#define RVCSR_MHPMCOUNTER22_LSB _u(0) +#define RVCSR_MHPMCOUNTER22_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER23 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER23_OFFSET _u(0x00000b17) +#define RVCSR_MHPMCOUNTER23_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER23_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER23_MSB _u(31) +#define RVCSR_MHPMCOUNTER23_LSB _u(0) +#define RVCSR_MHPMCOUNTER23_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER24 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER24_OFFSET _u(0x00000b18) +#define RVCSR_MHPMCOUNTER24_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER24_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER24_MSB _u(31) +#define RVCSR_MHPMCOUNTER24_LSB _u(0) +#define RVCSR_MHPMCOUNTER24_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER25 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER25_OFFSET _u(0x00000b19) +#define RVCSR_MHPMCOUNTER25_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER25_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER25_MSB _u(31) +#define RVCSR_MHPMCOUNTER25_LSB _u(0) +#define RVCSR_MHPMCOUNTER25_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER26 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER26_OFFSET _u(0x00000b1a) +#define RVCSR_MHPMCOUNTER26_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER26_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER26_MSB _u(31) +#define RVCSR_MHPMCOUNTER26_LSB _u(0) +#define RVCSR_MHPMCOUNTER26_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER27 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER27_OFFSET _u(0x00000b1b) +#define RVCSR_MHPMCOUNTER27_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER27_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER27_MSB _u(31) +#define RVCSR_MHPMCOUNTER27_LSB _u(0) +#define RVCSR_MHPMCOUNTER27_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER28 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER28_OFFSET _u(0x00000b1c) +#define RVCSR_MHPMCOUNTER28_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER28_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER28_MSB _u(31) +#define RVCSR_MHPMCOUNTER28_LSB _u(0) +#define RVCSR_MHPMCOUNTER28_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER29 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER29_OFFSET _u(0x00000b1d) +#define RVCSR_MHPMCOUNTER29_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER29_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER29_MSB _u(31) +#define RVCSR_MHPMCOUNTER29_LSB _u(0) +#define RVCSR_MHPMCOUNTER29_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER30 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER30_OFFSET _u(0x00000b1e) +#define RVCSR_MHPMCOUNTER30_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER30_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER30_MSB _u(31) +#define RVCSR_MHPMCOUNTER30_LSB _u(0) +#define RVCSR_MHPMCOUNTER30_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER31 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER31_OFFSET _u(0x00000b1f) +#define RVCSR_MHPMCOUNTER31_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER31_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER31_MSB _u(31) +#define RVCSR_MHPMCOUNTER31_LSB _u(0) +#define RVCSR_MHPMCOUNTER31_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MCYCLEH +// Description : Machine-mode cycle counter, high half +// Counts up once per 1 << 32 cycles, when `mcountinhibit.cy` is +// 0. Disabled by default to save power. +#define RVCSR_MCYCLEH_OFFSET _u(0x00000b80) +#define RVCSR_MCYCLEH_BITS _u(0xffffffff) +#define RVCSR_MCYCLEH_RESET _u(0x00000000) +#define RVCSR_MCYCLEH_MSB _u(31) +#define RVCSR_MCYCLEH_LSB _u(0) +#define RVCSR_MCYCLEH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MINSTRETH +// Description : Machine-mode instruction retire counter, low half +// Counts up once per 1 << 32 instructions, when +// `mcountinhibit.ir` is 0. Disabled by default to save power. +#define RVCSR_MINSTRETH_OFFSET _u(0x00000b82) +#define RVCSR_MINSTRETH_BITS _u(0xffffffff) +#define RVCSR_MINSTRETH_RESET _u(0x00000000) +#define RVCSR_MINSTRETH_MSB _u(31) +#define RVCSR_MINSTRETH_LSB _u(0) +#define RVCSR_MINSTRETH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER3H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER3H_OFFSET _u(0x00000b83) +#define RVCSR_MHPMCOUNTER3H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER3H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER3H_MSB _u(31) +#define RVCSR_MHPMCOUNTER3H_LSB _u(0) +#define RVCSR_MHPMCOUNTER3H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER4H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER4H_OFFSET _u(0x00000b84) +#define RVCSR_MHPMCOUNTER4H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER4H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER4H_MSB _u(31) +#define RVCSR_MHPMCOUNTER4H_LSB _u(0) +#define RVCSR_MHPMCOUNTER4H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER5H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER5H_OFFSET _u(0x00000b85) +#define RVCSR_MHPMCOUNTER5H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER5H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER5H_MSB _u(31) +#define RVCSR_MHPMCOUNTER5H_LSB _u(0) +#define RVCSR_MHPMCOUNTER5H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER6H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER6H_OFFSET _u(0x00000b86) +#define RVCSR_MHPMCOUNTER6H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER6H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER6H_MSB _u(31) +#define RVCSR_MHPMCOUNTER6H_LSB _u(0) +#define RVCSR_MHPMCOUNTER6H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER7H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER7H_OFFSET _u(0x00000b87) +#define RVCSR_MHPMCOUNTER7H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER7H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER7H_MSB _u(31) +#define RVCSR_MHPMCOUNTER7H_LSB _u(0) +#define RVCSR_MHPMCOUNTER7H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER8H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER8H_OFFSET _u(0x00000b88) +#define RVCSR_MHPMCOUNTER8H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER8H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER8H_MSB _u(31) +#define RVCSR_MHPMCOUNTER8H_LSB _u(0) +#define RVCSR_MHPMCOUNTER8H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER9H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER9H_OFFSET _u(0x00000b89) +#define RVCSR_MHPMCOUNTER9H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER9H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER9H_MSB _u(31) +#define RVCSR_MHPMCOUNTER9H_LSB _u(0) +#define RVCSR_MHPMCOUNTER9H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER10H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER10H_OFFSET _u(0x00000b8a) +#define RVCSR_MHPMCOUNTER10H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER10H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER10H_MSB _u(31) +#define RVCSR_MHPMCOUNTER10H_LSB _u(0) +#define RVCSR_MHPMCOUNTER10H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER11H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER11H_OFFSET _u(0x00000b8b) +#define RVCSR_MHPMCOUNTER11H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER11H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER11H_MSB _u(31) +#define RVCSR_MHPMCOUNTER11H_LSB _u(0) +#define RVCSR_MHPMCOUNTER11H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER12H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER12H_OFFSET _u(0x00000b8c) +#define RVCSR_MHPMCOUNTER12H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER12H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER12H_MSB _u(31) +#define RVCSR_MHPMCOUNTER12H_LSB _u(0) +#define RVCSR_MHPMCOUNTER12H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER13H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER13H_OFFSET _u(0x00000b8d) +#define RVCSR_MHPMCOUNTER13H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER13H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER13H_MSB _u(31) +#define RVCSR_MHPMCOUNTER13H_LSB _u(0) +#define RVCSR_MHPMCOUNTER13H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER14H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER14H_OFFSET _u(0x00000b8e) +#define RVCSR_MHPMCOUNTER14H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER14H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER14H_MSB _u(31) +#define RVCSR_MHPMCOUNTER14H_LSB _u(0) +#define RVCSR_MHPMCOUNTER14H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER15H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER15H_OFFSET _u(0x00000b8f) +#define RVCSR_MHPMCOUNTER15H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER15H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER15H_MSB _u(31) +#define RVCSR_MHPMCOUNTER15H_LSB _u(0) +#define RVCSR_MHPMCOUNTER15H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER16H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER16H_OFFSET _u(0x00000b90) +#define RVCSR_MHPMCOUNTER16H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER16H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER16H_MSB _u(31) +#define RVCSR_MHPMCOUNTER16H_LSB _u(0) +#define RVCSR_MHPMCOUNTER16H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER17H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER17H_OFFSET _u(0x00000b91) +#define RVCSR_MHPMCOUNTER17H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER17H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER17H_MSB _u(31) +#define RVCSR_MHPMCOUNTER17H_LSB _u(0) +#define RVCSR_MHPMCOUNTER17H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER18H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER18H_OFFSET _u(0x00000b92) +#define RVCSR_MHPMCOUNTER18H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER18H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER18H_MSB _u(31) +#define RVCSR_MHPMCOUNTER18H_LSB _u(0) +#define RVCSR_MHPMCOUNTER18H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER19H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER19H_OFFSET _u(0x00000b93) +#define RVCSR_MHPMCOUNTER19H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER19H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER19H_MSB _u(31) +#define RVCSR_MHPMCOUNTER19H_LSB _u(0) +#define RVCSR_MHPMCOUNTER19H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER20H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER20H_OFFSET _u(0x00000b94) +#define RVCSR_MHPMCOUNTER20H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER20H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER20H_MSB _u(31) +#define RVCSR_MHPMCOUNTER20H_LSB _u(0) +#define RVCSR_MHPMCOUNTER20H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER21H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER21H_OFFSET _u(0x00000b95) +#define RVCSR_MHPMCOUNTER21H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER21H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER21H_MSB _u(31) +#define RVCSR_MHPMCOUNTER21H_LSB _u(0) +#define RVCSR_MHPMCOUNTER21H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER22H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER22H_OFFSET _u(0x00000b96) +#define RVCSR_MHPMCOUNTER22H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER22H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER22H_MSB _u(31) +#define RVCSR_MHPMCOUNTER22H_LSB _u(0) +#define RVCSR_MHPMCOUNTER22H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER23H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER23H_OFFSET _u(0x00000b97) +#define RVCSR_MHPMCOUNTER23H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER23H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER23H_MSB _u(31) +#define RVCSR_MHPMCOUNTER23H_LSB _u(0) +#define RVCSR_MHPMCOUNTER23H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER24H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER24H_OFFSET _u(0x00000b98) +#define RVCSR_MHPMCOUNTER24H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER24H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER24H_MSB _u(31) +#define RVCSR_MHPMCOUNTER24H_LSB _u(0) +#define RVCSR_MHPMCOUNTER24H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER25H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER25H_OFFSET _u(0x00000b99) +#define RVCSR_MHPMCOUNTER25H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER25H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER25H_MSB _u(31) +#define RVCSR_MHPMCOUNTER25H_LSB _u(0) +#define RVCSR_MHPMCOUNTER25H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER26H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER26H_OFFSET _u(0x00000b9a) +#define RVCSR_MHPMCOUNTER26H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER26H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER26H_MSB _u(31) +#define RVCSR_MHPMCOUNTER26H_LSB _u(0) +#define RVCSR_MHPMCOUNTER26H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER27H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER27H_OFFSET _u(0x00000b9b) +#define RVCSR_MHPMCOUNTER27H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER27H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER27H_MSB _u(31) +#define RVCSR_MHPMCOUNTER27H_LSB _u(0) +#define RVCSR_MHPMCOUNTER27H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER28H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER28H_OFFSET _u(0x00000b9c) +#define RVCSR_MHPMCOUNTER28H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER28H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER28H_MSB _u(31) +#define RVCSR_MHPMCOUNTER28H_LSB _u(0) +#define RVCSR_MHPMCOUNTER28H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER29H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER29H_OFFSET _u(0x00000b9d) +#define RVCSR_MHPMCOUNTER29H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER29H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER29H_MSB _u(31) +#define RVCSR_MHPMCOUNTER29H_LSB _u(0) +#define RVCSR_MHPMCOUNTER29H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER30H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER30H_OFFSET _u(0x00000b9e) +#define RVCSR_MHPMCOUNTER30H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER30H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER30H_MSB _u(31) +#define RVCSR_MHPMCOUNTER30H_LSB _u(0) +#define RVCSR_MHPMCOUNTER30H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER31H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER31H_OFFSET _u(0x00000b9f) +#define RVCSR_MHPMCOUNTER31H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER31H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER31H_MSB _u(31) +#define RVCSR_MHPMCOUNTER31H_LSB _u(0) +#define RVCSR_MHPMCOUNTER31H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPCFGM0 +// Description : PMP M-mode configuration. One bit per PMP region. Setting a bit +// makes the corresponding region apply to M-mode (like the +// `pmpcfg.L` bit) but does not lock the region. +// +// PMP is useful for non-security-related purposes, such as stack +// guarding and peripheral emulation. This extension allows M-mode +// to freely use any currently unlocked regions for its own +// purposes, without the inconvenience of having to lock them. +// +// Note that this does not grant any new capabilities to M-mode, +// since in the base standard it is already possible to apply +// unlocked regions to M-mode by locking them. In general, PMP +// regions should be locked in ascending region number order so +// they can't be subsequently overridden by currently unlocked +// regions. +// +// Note also that this is not the same as the rule locking bypass +// bit in the ePMP extension, which does not permit locked and +// unlocked M-mode regions to coexist. +// +// This is a Hazard3 custom CSR. +#define RVCSR_PMPCFGM0_OFFSET _u(0x00000bd0) +#define RVCSR_PMPCFGM0_BITS _u(0x0000ffff) +#define RVCSR_PMPCFGM0_RESET _u(0x00000000) +#define RVCSR_PMPCFGM0_MSB _u(15) +#define RVCSR_PMPCFGM0_LSB _u(0) +#define RVCSR_PMPCFGM0_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MEIEA +// Description : External interrupt enable array. +// +// The array contains a read-write bit for each external interrupt +// request: a `1` bit indicates that interrupt is currently +// enabled. At reset, all external interrupts are disabled. +// +// If enabled, an external interrupt can cause assertion of the +// standard RISC-V machine external interrupt pending flag +// (`mip.meip`), and therefore cause the processor to enter the +// external interrupt vector. See `meipa`. +// +// There are up to 512 external interrupts. The upper half of this +// register contains a 16-bit window into the full 512-bit vector. +// The window is indexed by the 5 LSBs of the write data. +#define RVCSR_MEIEA_OFFSET _u(0x00000be0) +#define RVCSR_MEIEA_BITS _u(0xffff001f) +#define RVCSR_MEIEA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIEA_WINDOW +// Description : 16-bit read/write window into the external interrupt enable +// array +#define RVCSR_MEIEA_WINDOW_RESET _u(0x0000) +#define RVCSR_MEIEA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIEA_WINDOW_MSB _u(31) +#define RVCSR_MEIEA_WINDOW_LSB _u(16) +#define RVCSR_MEIEA_WINDOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIEA_INDEX +// Description : Write-only self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIEA_INDEX_RESET _u(0x00) +#define RVCSR_MEIEA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIEA_INDEX_MSB _u(4) +#define RVCSR_MEIEA_INDEX_LSB _u(0) +#define RVCSR_MEIEA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEIPA +// Description : External interrupt pending array +// +// Contains a read-only bit for each external interrupt request. +// Similarly to `meiea`, this register is a window into an array +// of up to 512 external interrupt flags. The status appears in +// the upper 16 bits of the value read from `meipa`, and the lower +// 5 bits of the value _written_ by the same CSR instruction (or 0 +// if no write takes place) select a 16-bit window of the full +// interrupt pending array. +// +// A `1` bit indicates that interrupt is currently asserted. IRQs +// are assumed to be level-sensitive, and the relevant `meipa` bit +// is cleared by servicing the requestor so that it deasserts its +// interrupt request. +// +// When any interrupt of sufficient priority is both set in +// `meipa` and enabled in `meiea`, the standard RISC-V external +// interrupt pending bit `mip.meip` is asserted. In other words, +// `meipa` is filtered by `meiea` to generate the standard +// `mip.meip` flag. +#define RVCSR_MEIPA_OFFSET _u(0x00000be1) +#define RVCSR_MEIPA_BITS _u(0xffff001f) +#define RVCSR_MEIPA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPA_WINDOW +// Description : 16-bit read-only window into the external interrupt pending +// array +#define RVCSR_MEIPA_WINDOW_RESET "-" +#define RVCSR_MEIPA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIPA_WINDOW_MSB _u(31) +#define RVCSR_MEIPA_WINDOW_LSB _u(16) +#define RVCSR_MEIPA_WINDOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPA_INDEX +// Description : Write-only, self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIPA_INDEX_RESET _u(0x00) +#define RVCSR_MEIPA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIPA_INDEX_MSB _u(4) +#define RVCSR_MEIPA_INDEX_LSB _u(0) +#define RVCSR_MEIPA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEIFA +// Description : External interrupt force array +// +// Contains a read-write bit for every interrupt request. Writing +// a 1 to a bit in the interrupt force array causes the +// corresponding bit to become pending in `meipa`. Software can +// use this feature to manually trigger a particular interrupt. +// +// There are no restrictions on using `meifa` inside of an +// interrupt. The more useful case here is to schedule some lower- +// priority handler from within a high-priority interrupt, so that +// it will execute before the core returns to the foreground code. +// Implementers may wish to reserve some external IRQs with their +// external inputs tied to 0 for this purpose. +// +// Bits can be cleared by software, and are cleared automatically +// by hardware upon a read of `meinext` which returns the +// corresponding IRQ number in `meinext.irq` with `mienext.noirq` +// clear (no matter whether `meinext.update` is written). +// +// `meifa` implements the same array window indexing scheme as +// `meiea` and `meipa`. +#define RVCSR_MEIFA_OFFSET _u(0x00000be2) +#define RVCSR_MEIFA_BITS _u(0xffff001f) +#define RVCSR_MEIFA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIFA_WINDOW +// Description : 16-bit read/write window into the external interrupt force +// array +#define RVCSR_MEIFA_WINDOW_RESET _u(0x0000) +#define RVCSR_MEIFA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIFA_WINDOW_MSB _u(31) +#define RVCSR_MEIFA_WINDOW_LSB _u(16) +#define RVCSR_MEIFA_WINDOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIFA_INDEX +// Description : Write-only, self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIFA_INDEX_RESET _u(0x00) +#define RVCSR_MEIFA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIFA_INDEX_MSB _u(4) +#define RVCSR_MEIFA_INDEX_LSB _u(0) +#define RVCSR_MEIFA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEIPRA +// Description : External interrupt priority array +// +// Each interrupt has an (up to) 4-bit priority value associated +// with it, and each access to this register reads and/or writes a +// 16-bit window containing four such priority values. When less +// than 16 priority levels are available, the LSBs of the priority +// fields are hardwired to 0. +// +// When an interrupt's priority is lower than the current +// preemption priority `meicontext.preempt`, it is treated as not +// being pending for the purposes of `mip.meip`. The pending bit +// in `meipa` will still assert, but the machine external +// interrupt pending bit `mip.meip` will not, so the processor +// will ignore this interrupt. See `meicontext`. +#define RVCSR_MEIPRA_OFFSET _u(0x00000be3) +#define RVCSR_MEIPRA_BITS _u(0xffff001f) +#define RVCSR_MEIPRA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPRA_WINDOW +// Description : 16-bit read/write window into the external interrupt priority +// array, containing four 4-bit priority values. +#define RVCSR_MEIPRA_WINDOW_RESET _u(0x0000) +#define RVCSR_MEIPRA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIPRA_WINDOW_MSB _u(31) +#define RVCSR_MEIPRA_WINDOW_LSB _u(16) +#define RVCSR_MEIPRA_WINDOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPRA_INDEX +// Description : Write-only, self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIPRA_INDEX_RESET _u(0x00) +#define RVCSR_MEIPRA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIPRA_INDEX_MSB _u(4) +#define RVCSR_MEIPRA_INDEX_LSB _u(0) +#define RVCSR_MEIPRA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEINEXT +// Description : Get next external interrupt +// +// Contains the index of the highest-priority external interrupt +// which is both asserted in `meipa` and enabled in `meiea`, left- +// shifted by 2 so that it can be used to index an array of 32-bit +// function pointers. If there is no such interrupt, the MSB is +// set. +// +// When multiple interrupts of the same priority are both pending +// and enabled, the lowest-numbered wins. Interrupts with priority +// less than `meicontext.ppreempt` -- the _previous_ preemption +// priority -- are treated as though they are not pending. This is +// to ensure that a preempting interrupt frame does not service +// interrupts which may be in progress in the frame that was +// preempted. +#define RVCSR_MEINEXT_OFFSET _u(0x00000be4) +#define RVCSR_MEINEXT_BITS _u(0x800007fd) +#define RVCSR_MEINEXT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEINEXT_NOIRQ +// Description : Set when there is no external interrupt which is enabled, +// pending, and has priority greater than or equal to +// `meicontext.ppreempt`. Can be efficiently tested with a `bltz` +// or `bgez` instruction. +#define RVCSR_MEINEXT_NOIRQ_RESET _u(0x0) +#define RVCSR_MEINEXT_NOIRQ_BITS _u(0x80000000) +#define RVCSR_MEINEXT_NOIRQ_MSB _u(31) +#define RVCSR_MEINEXT_NOIRQ_LSB _u(31) +#define RVCSR_MEINEXT_NOIRQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEINEXT_IRQ +// Description : Index of the highest-priority active external interrupt. Zero +// when no external interrupts with sufficient priority are both +// pending and enabled. +#define RVCSR_MEINEXT_IRQ_RESET _u(0x000) +#define RVCSR_MEINEXT_IRQ_BITS _u(0x000007fc) +#define RVCSR_MEINEXT_IRQ_MSB _u(10) +#define RVCSR_MEINEXT_IRQ_LSB _u(2) +#define RVCSR_MEINEXT_IRQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEINEXT_UPDATE +// Description : Writing 1 (self-clearing) causes hardware to update +// `meicontext` according to the IRQ number and preemption +// priority of the interrupt indicated in `noirq`/`irq`. This +// should be done in a single atomic operation, i.e. `csrrsi a0, +// meinext, 0x1`. +#define RVCSR_MEINEXT_UPDATE_RESET _u(0x0) +#define RVCSR_MEINEXT_UPDATE_BITS _u(0x00000001) +#define RVCSR_MEINEXT_UPDATE_MSB _u(0) +#define RVCSR_MEINEXT_UPDATE_LSB _u(0) +#define RVCSR_MEINEXT_UPDATE_ACCESS "SC" +// ============================================================================= +// Register : RVCSR_MEICONTEXT +// Description : External interrupt context register +// +// Configures the priority level for interrupt preemption, and +// helps software track which interrupt it is currently in. The +// latter is useful when a common interrupt service routine +// handles interrupt requests from multiple instances of the same +// peripheral. +// +// A three-level stack of preemption priorities is maintained in +// the `preempt`, `ppreempt` and `pppreempt` fields. The priority +// stack is saved when hardware enters the external interrupt +// vector, and restored by an `mret` instruction if +// `meicontext.mreteirq` is set. +// +// The top entry of the priority stack, `preempt`, is used by +// hardware to ensure that only higher-priority interrupts can +// preempt the current interrupt. The next entry, `ppreempt`, is +// used to avoid servicing interrupts which may already be in +// progress in a frame that was preempted. The third entry, +// `pppreempt`, has no hardware effect, but ensures that `preempt` +// and `ppreempt` can be correctly saved/restored across arbitrary +// levels of preemption. +#define RVCSR_MEICONTEXT_OFFSET _u(0x00000be5) +#define RVCSR_MEICONTEXT_BITS _u(0xff1f9fff) +#define RVCSR_MEICONTEXT_RESET _u(0x00008000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_PPPREEMPT +// Description : Previous `ppreempt`. Set to `ppreempt` on priority save, set to +// zero on priority restore. Has no hardware effect, but ensures +// that when `meicontext` is saved/restored correctly, `preempt` +// and `ppreempt` stack correctly through arbitrarily many +// preemption frames. +#define RVCSR_MEICONTEXT_PPPREEMPT_RESET _u(0x0) +#define RVCSR_MEICONTEXT_PPPREEMPT_BITS _u(0xf0000000) +#define RVCSR_MEICONTEXT_PPPREEMPT_MSB _u(31) +#define RVCSR_MEICONTEXT_PPPREEMPT_LSB _u(28) +#define RVCSR_MEICONTEXT_PPPREEMPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_PPREEMPT +// Description : Previous `preempt`. Set to `preempt` on priority save, restored +// to to `pppreempt` on priority restore. +// +// IRQs of lower priority than `ppreempt` are not visible in +// `meinext`, so that a preemptee is not re-taken in the +// preempting frame. +#define RVCSR_MEICONTEXT_PPREEMPT_RESET _u(0x0) +#define RVCSR_MEICONTEXT_PPREEMPT_BITS _u(0x0f000000) +#define RVCSR_MEICONTEXT_PPREEMPT_MSB _u(27) +#define RVCSR_MEICONTEXT_PPREEMPT_LSB _u(24) +#define RVCSR_MEICONTEXT_PPREEMPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_PREEMPT +// Description : Minimum interrupt priority to preempt the current interrupt. +// Interrupts with lower priority than `preempt` do not cause the +// core to transfer to an interrupt handler. Updated by hardware +// when when `meinext.update` is written, or when hardware enters +// the external interrupt vector. +// +// If an interrupt is present in `meinext` when this field is +// updated, then `preempt` is set to one level greater than that +// interrupt's priority. Otherwise, `ppreempt` is set to one level +// greater than the maximum interrupt priority, disabling +// preemption. +#define RVCSR_MEICONTEXT_PREEMPT_RESET _u(0x00) +#define RVCSR_MEICONTEXT_PREEMPT_BITS _u(0x001f0000) +#define RVCSR_MEICONTEXT_PREEMPT_MSB _u(20) +#define RVCSR_MEICONTEXT_PREEMPT_LSB _u(16) +#define RVCSR_MEICONTEXT_PREEMPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_NOIRQ +// Description : Not in interrupt (read/write). Set to 1 at reset. Set to +// `meinext.noirq` when `meinext.update` is written. No hardware +// effect. +#define RVCSR_MEICONTEXT_NOIRQ_RESET _u(0x1) +#define RVCSR_MEICONTEXT_NOIRQ_BITS _u(0x00008000) +#define RVCSR_MEICONTEXT_NOIRQ_MSB _u(15) +#define RVCSR_MEICONTEXT_NOIRQ_LSB _u(15) +#define RVCSR_MEICONTEXT_NOIRQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_IRQ +// Description : Current IRQ number (read/write). Set to `meinext.irq` when +// `meinext.update` is written. No hardware effect. +#define RVCSR_MEICONTEXT_IRQ_RESET _u(0x000) +#define RVCSR_MEICONTEXT_IRQ_BITS _u(0x00001ff0) +#define RVCSR_MEICONTEXT_IRQ_MSB _u(12) +#define RVCSR_MEICONTEXT_IRQ_LSB _u(4) +#define RVCSR_MEICONTEXT_IRQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_MTIESAVE +// Description : Reads as the current value of `mie.mtie`, if `clearts` is set +// by the same CSR access instruction. Otherwise reads as 0. +// Writes are ORed into `mie.mtie`. +#define RVCSR_MEICONTEXT_MTIESAVE_RESET _u(0x0) +#define RVCSR_MEICONTEXT_MTIESAVE_BITS _u(0x00000008) +#define RVCSR_MEICONTEXT_MTIESAVE_MSB _u(3) +#define RVCSR_MEICONTEXT_MTIESAVE_LSB _u(3) +#define RVCSR_MEICONTEXT_MTIESAVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_MSIESAVE +// Description : Reads as the current value of `mie.msie`, if `clearts` is set +// by the same CSR access instruction. Otherwise reads as 0. +// Writes are ORed into `mie.msie`. +#define RVCSR_MEICONTEXT_MSIESAVE_RESET _u(0x0) +#define RVCSR_MEICONTEXT_MSIESAVE_BITS _u(0x00000004) +#define RVCSR_MEICONTEXT_MSIESAVE_MSB _u(2) +#define RVCSR_MEICONTEXT_MSIESAVE_LSB _u(2) +#define RVCSR_MEICONTEXT_MSIESAVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_CLEARTS +// Description : Write-1 self-clearing field. Writing 1 will clear `mie.mtie` +// and `mie.msie`, and present their prior values in the +// `mtiesave` and `msiesave` of this register. This makes it safe +// to re-enable IRQs (via `mstatus.mie`) without the possibility +// of being preempted by the standard timer and soft interrupt +// handlers, which may not be aware of Hazard3's interrupt +// hardware. +// +// The clear due to `clearts` takes precedence over the set due to +// `mtiesave`/`msiesave`, although it would be unusual for +// software to write both on the same cycle. +#define RVCSR_MEICONTEXT_CLEARTS_RESET _u(0x0) +#define RVCSR_MEICONTEXT_CLEARTS_BITS _u(0x00000002) +#define RVCSR_MEICONTEXT_CLEARTS_MSB _u(1) +#define RVCSR_MEICONTEXT_CLEARTS_LSB _u(1) +#define RVCSR_MEICONTEXT_CLEARTS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_MRETEIRQ +// Description : If 1, enable restore of the preemption priority stack on +// `mret`. This bit is set on entering the external interrupt +// vector, cleared by `mret`, and cleared upon taking any trap +// other than an external interrupt. +// +// Provided `meicontext` is saved on entry to the external +// interrupt vector (before enabling preemption), is restored +// before exiting, and the standard software/timer IRQs are +// prevented from preempting (e.g. by using `clearts`), this flag +// allows the hardware to safely manage the preemption priority +// stack even when an external interrupt handler may take +// exceptions. +#define RVCSR_MEICONTEXT_MRETEIRQ_RESET _u(0x0) +#define RVCSR_MEICONTEXT_MRETEIRQ_BITS _u(0x00000001) +#define RVCSR_MEICONTEXT_MRETEIRQ_MSB _u(0) +#define RVCSR_MEICONTEXT_MRETEIRQ_LSB _u(0) +#define RVCSR_MEICONTEXT_MRETEIRQ_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MSLEEP +// Description : M-mode sleep control register +#define RVCSR_MSLEEP_OFFSET _u(0x00000bf0) +#define RVCSR_MSLEEP_BITS _u(0x00000007) +#define RVCSR_MSLEEP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSLEEP_SLEEPONBLOCK +// Description : Enter the deep sleep state configured by +// msleep.deepsleep/msleep.powerdown on a `h3.block` instruction, +// as well as a standard `wfi`. If this bit is clear, a `h3.block` +// is always implemented as a simple pipeline stall. +#define RVCSR_MSLEEP_SLEEPONBLOCK_RESET _u(0x0) +#define RVCSR_MSLEEP_SLEEPONBLOCK_BITS _u(0x00000004) +#define RVCSR_MSLEEP_SLEEPONBLOCK_MSB _u(2) +#define RVCSR_MSLEEP_SLEEPONBLOCK_LSB _u(2) +#define RVCSR_MSLEEP_SLEEPONBLOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSLEEP_POWERDOWN +// Description : Release the external power request when going to sleep. The +// function of this is platform-defined -- it may do nothing, it +// may do something simple like clock-gating the fabric, or it may +// be tied to some complex system-level power controller. +// +// When waking, the processor reasserts its external power-up +// request, and will not fetch any instructions until the request +// is acknowledged. This may add considerable latency to the +// wakeup. +#define RVCSR_MSLEEP_POWERDOWN_RESET _u(0x0) +#define RVCSR_MSLEEP_POWERDOWN_BITS _u(0x00000002) +#define RVCSR_MSLEEP_POWERDOWN_MSB _u(1) +#define RVCSR_MSLEEP_POWERDOWN_LSB _u(1) +#define RVCSR_MSLEEP_POWERDOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSLEEP_DEEPSLEEP +// Description : Deassert the processor clock enable when entering the sleep +// state. If a clock gate is instantiated, this allows most of the +// processor (everything except the power state machine and the +// interrupt and halt input registers) to be clock gated whilst +// asleep, which may reduce the sleep current. This adds one cycle +// to the wakeup latency. +#define RVCSR_MSLEEP_DEEPSLEEP_RESET _u(0x0) +#define RVCSR_MSLEEP_DEEPSLEEP_BITS _u(0x00000001) +#define RVCSR_MSLEEP_DEEPSLEEP_MSB _u(0) +#define RVCSR_MSLEEP_DEEPSLEEP_LSB _u(0) +#define RVCSR_MSLEEP_DEEPSLEEP_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_DMDATA0 +// Description : The Debug Module's DATA0 register is mapped into Hazard3's CSR +// space so that the Debug Module can exchange data with the core +// by executing CSR access instructions (this is used to implement +// the Abstract Access Register command). Only accessible in Debug +// Mode. +#define RVCSR_DMDATA0_OFFSET _u(0x00000bff) +#define RVCSR_DMDATA0_BITS _u(0xffffffff) +#define RVCSR_DMDATA0_RESET _u(0x00000000) +#define RVCSR_DMDATA0_MSB _u(31) +#define RVCSR_DMDATA0_LSB _u(0) +#define RVCSR_DMDATA0_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_CYCLE +// Description : Read-only U-mode alias of mcycle, accessible when +// `mcounteren.cy` is set +#define RVCSR_CYCLE_OFFSET _u(0x00000c00) +#define RVCSR_CYCLE_BITS _u(0xffffffff) +#define RVCSR_CYCLE_RESET _u(0x00000000) +#define RVCSR_CYCLE_MSB _u(31) +#define RVCSR_CYCLE_LSB _u(0) +#define RVCSR_CYCLE_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_INSTRET +// Description : Read-only U-mode alias of minstret, accessible when +// `mcounteren.ir` is set +#define RVCSR_INSTRET_OFFSET _u(0x00000c02) +#define RVCSR_INSTRET_BITS _u(0xffffffff) +#define RVCSR_INSTRET_RESET _u(0x00000000) +#define RVCSR_INSTRET_MSB _u(31) +#define RVCSR_INSTRET_LSB _u(0) +#define RVCSR_INSTRET_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_CYCLEH +// Description : Read-only U-mode alias of mcycleh, accessible when +// `mcounteren.cy` is set +#define RVCSR_CYCLEH_OFFSET _u(0x00000c80) +#define RVCSR_CYCLEH_BITS _u(0xffffffff) +#define RVCSR_CYCLEH_RESET _u(0x00000000) +#define RVCSR_CYCLEH_MSB _u(31) +#define RVCSR_CYCLEH_LSB _u(0) +#define RVCSR_CYCLEH_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_INSTRETH +// Description : Read-only U-mode alias of minstreth, accessible when +// `mcounteren.ir` is set +#define RVCSR_INSTRETH_OFFSET _u(0x00000c82) +#define RVCSR_INSTRETH_BITS _u(0xffffffff) +#define RVCSR_INSTRETH_RESET _u(0x00000000) +#define RVCSR_INSTRETH_MSB _u(31) +#define RVCSR_INSTRETH_LSB _u(0) +#define RVCSR_INSTRETH_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MVENDORID +// Description : Vendor ID +#define RVCSR_MVENDORID_OFFSET _u(0x00000f11) +#define RVCSR_MVENDORID_BITS _u(0xffffffff) +#define RVCSR_MVENDORID_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MVENDORID_BANK +#define RVCSR_MVENDORID_BANK_RESET "-" +#define RVCSR_MVENDORID_BANK_BITS _u(0xffffff80) +#define RVCSR_MVENDORID_BANK_MSB _u(31) +#define RVCSR_MVENDORID_BANK_LSB _u(7) +#define RVCSR_MVENDORID_BANK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MVENDORID_OFFSET +#define RVCSR_MVENDORID_OFFSET_RESET "-" +#define RVCSR_MVENDORID_OFFSET_BITS _u(0x0000007f) +#define RVCSR_MVENDORID_OFFSET_MSB _u(6) +#define RVCSR_MVENDORID_OFFSET_LSB _u(0) +#define RVCSR_MVENDORID_OFFSET_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MARCHID +// Description : Architecture ID (Hazard3) +#define RVCSR_MARCHID_OFFSET _u(0x00000f12) +#define RVCSR_MARCHID_BITS _u(0xffffffff) +#define RVCSR_MARCHID_RESET _u(0x0000001b) +#define RVCSR_MARCHID_MSB _u(31) +#define RVCSR_MARCHID_LSB _u(0) +#define RVCSR_MARCHID_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MIMPID +// Description : Implementation ID +#define RVCSR_MIMPID_OFFSET _u(0x00000f13) +#define RVCSR_MIMPID_BITS _u(0xffffffff) +#define RVCSR_MIMPID_RESET "-" +#define RVCSR_MIMPID_MSB _u(31) +#define RVCSR_MIMPID_LSB _u(0) +#define RVCSR_MIMPID_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHARTID +// Description : Hardware thread ID +// On RP2350, core 0 has a hart ID of 0, and core 1 has a hart ID +// of 1. +#define RVCSR_MHARTID_OFFSET _u(0x00000f14) +#define RVCSR_MHARTID_BITS _u(0xffffffff) +#define RVCSR_MHARTID_RESET "-" +#define RVCSR_MHARTID_MSB _u(31) +#define RVCSR_MHARTID_LSB _u(0) +#define RVCSR_MHARTID_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MCONFIGPTR +// Description : Pointer to configuration data structure (hardwired to 0) +#define RVCSR_MCONFIGPTR_OFFSET _u(0x00000f15) +#define RVCSR_MCONFIGPTR_BITS _u(0xffffffff) +#define RVCSR_MCONFIGPTR_RESET _u(0x00000000) +#define RVCSR_MCONFIGPTR_MSB _u(31) +#define RVCSR_MCONFIGPTR_LSB _u(0) +#define RVCSR_MCONFIGPTR_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RVCSR_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/sha256.h b/src/rp2350/hardware_regs/include/hardware/regs/sha256.h new file mode 100644 index 000000000..112963c08 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/sha256.h @@ -0,0 +1,228 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SHA256 +// Version : 1 +// Bus type : apb +// Description : SHA-256 hash function implementation +// ============================================================================= +#ifndef _HARDWARE_REGS_SHA256_H +#define _HARDWARE_REGS_SHA256_H +// ============================================================================= +// Register : SHA256_CSR +// Description : Control and status register +#define SHA256_CSR_OFFSET _u(0x00000000) +#define SHA256_CSR_BITS _u(0x00001317) +#define SHA256_CSR_RESET _u(0x00001206) +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_BSWAP +// Description : Enable byte swapping of 32-bit values at the point they are +// committed to the SHA message scheduler. +// +// This block's bus interface assembles byte/halfword data into +// message words in little-endian order, so that DMAing the same +// buffer with different transfer sizes always gives the same +// result on a little-endian system like RP2350. +// +// However, when marshalling bytes into blocks, SHA expects that +// the first byte is the *most significant* in each message word. +// To resolve this, once the bus interface has accumulated 32 bits +// of data (either a word write, two halfword writes in little- +// endian order, or four byte writes in little-endian order) the +// final value can be byte-swapped before passing to the actual +// SHA core. +// +// This feature is enabled by default because using the SHA core +// to checksum byte buffers is expected to be more common than +// having preformatted SHA message words lying around. +#define SHA256_CSR_BSWAP_RESET _u(0x1) +#define SHA256_CSR_BSWAP_BITS _u(0x00001000) +#define SHA256_CSR_BSWAP_MSB _u(12) +#define SHA256_CSR_BSWAP_LSB _u(12) +#define SHA256_CSR_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_DMA_SIZE +// Description : Configure DREQ logic for the correct DMA data size. Must be +// configured before the DMA channel is triggered. +// +// The SHA-256 core's DREQ logic requests one entire block of data +// at once, since there is no FIFO, and data goes straight into +// the core's message schedule and digest hardware. Therefore, +// when transferring data with DMA, CSR_DMA_SIZE must be +// configured in advance so that the correct number of transfers +// can be requested per block. +// 0x0 -> 8bit +// 0x1 -> 16bit +// 0x2 -> 32bit +#define SHA256_CSR_DMA_SIZE_RESET _u(0x2) +#define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300) +#define SHA256_CSR_DMA_SIZE_MSB _u(9) +#define SHA256_CSR_DMA_SIZE_LSB _u(8) +#define SHA256_CSR_DMA_SIZE_ACCESS "RW" +#define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0) +#define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1) +#define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2) +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_ERR_WDATA_NOT_RDY +// Description : Set when a write occurs whilst the SHA-256 core is not ready +// for data (WDATA_RDY is low). Write one to clear. +#define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_SUM_VLD +// Description : If 1, the SHA-256 checksum presented in registers SUM0 through +// SUM7 is currently valid. +// +// Goes low when WDATA is first written, then returns high once 16 +// words have been written and the digest of the current 512-bit +// block has subsequently completed. +#define SHA256_CSR_SUM_VLD_RESET _u(0x1) +#define SHA256_CSR_SUM_VLD_BITS _u(0x00000004) +#define SHA256_CSR_SUM_VLD_MSB _u(2) +#define SHA256_CSR_SUM_VLD_LSB _u(2) +#define SHA256_CSR_SUM_VLD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_WDATA_RDY +// Description : If 1, the SHA-256 core is ready to accept more data through the +// WDATA register. +// +// After writing 16 words, this flag will go low for 57 cycles +// whilst the core completes its digest. +#define SHA256_CSR_WDATA_RDY_RESET _u(0x1) +#define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002) +#define SHA256_CSR_WDATA_RDY_MSB _u(1) +#define SHA256_CSR_WDATA_RDY_LSB _u(1) +#define SHA256_CSR_WDATA_RDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_START +// Description : Write 1 to prepare the SHA-256 core for a new checksum. +// +// The SUMx registers are initialised to the proper values +// (fractional bits of square roots of first 8 primes) and +// internal counters are cleared. This immediately forces +// WDATA_RDY and SUM_VLD high. +// +// START must be written before initiating a DMA transfer to the +// SHA-256 core, because the core will always request 16 transfers +// at a time (1 512-bit block). Additionally, the DMA channel +// should be configured for a multiple of 16 32-bit transfers. +#define SHA256_CSR_START_RESET _u(0x0) +#define SHA256_CSR_START_BITS _u(0x00000001) +#define SHA256_CSR_START_MSB _u(0) +#define SHA256_CSR_START_LSB _u(0) +#define SHA256_CSR_START_ACCESS "SC" +// ============================================================================= +// Register : SHA256_WDATA +// Description : Write data register +// After pulsing START and writing 16 words of data to this +// register, WDATA_RDY will go low and the SHA-256 core will +// complete the digest of the current 512-bit block. +// +// Software is responsible for ensuring the data is correctly +// padded and terminated to a whole number of 512-bit blocks. +// +// After this, WDATA_RDY will return high, and more data can be +// written (if any). +// +// This register supports word, halfword and byte writes, so that +// DMA from non-word-aligned buffers can be supported. The total +// amount of data per block remains the same (16 words, 32 +// halfwords or 64 bytes) and byte/halfword transfers must not be +// mixed within a block. +#define SHA256_WDATA_OFFSET _u(0x00000004) +#define SHA256_WDATA_BITS _u(0xffffffff) +#define SHA256_WDATA_RESET _u(0x00000000) +#define SHA256_WDATA_MSB _u(31) +#define SHA256_WDATA_LSB _u(0) +#define SHA256_WDATA_ACCESS "WF" +// ============================================================================= +// Register : SHA256_SUM0 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM0_OFFSET _u(0x00000008) +#define SHA256_SUM0_BITS _u(0xffffffff) +#define SHA256_SUM0_RESET _u(0x00000000) +#define SHA256_SUM0_MSB _u(31) +#define SHA256_SUM0_LSB _u(0) +#define SHA256_SUM0_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM1 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM1_OFFSET _u(0x0000000c) +#define SHA256_SUM1_BITS _u(0xffffffff) +#define SHA256_SUM1_RESET _u(0x00000000) +#define SHA256_SUM1_MSB _u(31) +#define SHA256_SUM1_LSB _u(0) +#define SHA256_SUM1_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM2 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM2_OFFSET _u(0x00000010) +#define SHA256_SUM2_BITS _u(0xffffffff) +#define SHA256_SUM2_RESET _u(0x00000000) +#define SHA256_SUM2_MSB _u(31) +#define SHA256_SUM2_LSB _u(0) +#define SHA256_SUM2_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM3 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM3_OFFSET _u(0x00000014) +#define SHA256_SUM3_BITS _u(0xffffffff) +#define SHA256_SUM3_RESET _u(0x00000000) +#define SHA256_SUM3_MSB _u(31) +#define SHA256_SUM3_LSB _u(0) +#define SHA256_SUM3_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM4 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM4_OFFSET _u(0x00000018) +#define SHA256_SUM4_BITS _u(0xffffffff) +#define SHA256_SUM4_RESET _u(0x00000000) +#define SHA256_SUM4_MSB _u(31) +#define SHA256_SUM4_LSB _u(0) +#define SHA256_SUM4_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM5 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM5_OFFSET _u(0x0000001c) +#define SHA256_SUM5_BITS _u(0xffffffff) +#define SHA256_SUM5_RESET _u(0x00000000) +#define SHA256_SUM5_MSB _u(31) +#define SHA256_SUM5_LSB _u(0) +#define SHA256_SUM5_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM6 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM6_OFFSET _u(0x00000020) +#define SHA256_SUM6_BITS _u(0xffffffff) +#define SHA256_SUM6_RESET _u(0x00000000) +#define SHA256_SUM6_MSB _u(31) +#define SHA256_SUM6_LSB _u(0) +#define SHA256_SUM6_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM7 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM7_OFFSET _u(0x00000024) +#define SHA256_SUM7_BITS _u(0xffffffff) +#define SHA256_SUM7_RESET _u(0x00000000) +#define SHA256_SUM7_MSB _u(31) +#define SHA256_SUM7_LSB _u(0) +#define SHA256_SUM7_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_SHA256_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/sio.h b/src/rp2350/hardware_regs/include/hardware/regs/sio.h new file mode 100644 index 000000000..c4cb29042 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/sio.h @@ -0,0 +1,2461 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SIO +// Version : 1 +// Bus type : apb +// Description : Single-cycle IO block +// Provides core-local and inter-core hardware for the two +// processors, with single-cycle access. +// ============================================================================= +#ifndef _HARDWARE_REGS_SIO_H +#define _HARDWARE_REGS_SIO_H +// ============================================================================= +// Register : SIO_CPUID +// Description : Processor core identifier +// Value is 0 when read from processor core 0, and 1 when read +// from processor core 1. +#define SIO_CPUID_OFFSET _u(0x00000000) +#define SIO_CPUID_BITS _u(0xffffffff) +#define SIO_CPUID_RESET "-" +#define SIO_CPUID_MSB _u(31) +#define SIO_CPUID_LSB _u(0) +#define SIO_CPUID_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_IN +// Description : Input value for GPIO0...31. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// appear as zero. +#define SIO_GPIO_IN_OFFSET _u(0x00000004) +#define SIO_GPIO_IN_BITS _u(0xffffffff) +#define SIO_GPIO_IN_RESET _u(0x00000000) +#define SIO_GPIO_IN_MSB _u(31) +#define SIO_GPIO_IN_LSB _u(0) +#define SIO_GPIO_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_HI_IN +// Description : Input value on GPIO32...47, QSPI IOs and USB pins +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// appear as zero. +#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) +#define SIO_GPIO_HI_IN_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_IN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_QSPI_SD +// Description : Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins +#define SIO_GPIO_HI_IN_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_IN_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_IN_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_IN_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_IN_QSPI_SD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_QSPI_CSN +// Description : Input value on QSPI CSn pin +#define SIO_GPIO_HI_IN_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_IN_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_IN_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_IN_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_IN_QSPI_CSN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_QSPI_SCK +// Description : Input value on QSPI SCK pin +#define SIO_GPIO_HI_IN_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_IN_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_IN_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_IN_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_IN_QSPI_SCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_USB_DM +// Description : Input value on USB D- pin +#define SIO_GPIO_HI_IN_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_IN_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_IN_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_IN_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_IN_USB_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_USB_DP +// Description : Input value on USB D+ pin +#define SIO_GPIO_HI_IN_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_IN_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_IN_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_IN_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_IN_USB_DP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_GPIO +// Description : Input value on GPIO32...47 +#define SIO_GPIO_HI_IN_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_IN_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_IN_GPIO_MSB _u(15) +#define SIO_GPIO_HI_IN_GPIO_LSB _u(0) +#define SIO_GPIO_HI_IN_GPIO_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_OUT +// Description : GPIO0...31 output value +// Set output level (1/0 -> high/low) for GPIO0...31. Reading back +// gives the last value written, NOT the input value from the +// pins. +// +// If core 0 and core 1 both write to GPIO_OUT simultaneously (or +// to a SET/CLR/XOR alias), the result is as though the write from +// core 0 took place first, and the write from core 1 was then +// applied to that intermediate result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_OUT_OFFSET _u(0x00000010) +#define SIO_GPIO_OUT_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_RESET _u(0x00000000) +#define SIO_GPIO_OUT_MSB _u(31) +#define SIO_GPIO_OUT_LSB _u(0) +#define SIO_GPIO_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT +// Description : Output value for GPIO32...47, QSPI IOs and USB pins. +// +// Write to set output level (1/0 -> high/low). Reading back gives +// the last value written, NOT the input value from the pins. If +// core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or +// to a SET/CLR/XOR alias), the result is as though the write from +// core 0 took place first, and the write from core 1 was then +// applied to that intermediate result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000014) +#define SIO_GPIO_HI_OUT_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_QSPI_SD +// Description : Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins +#define SIO_GPIO_HI_OUT_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_QSPI_CSN +// Description : Output value for QSPI CSn pin +#define SIO_GPIO_HI_OUT_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_QSPI_SCK +// Description : Output value for QSPI SCK pin +#define SIO_GPIO_HI_OUT_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_USB_DM +// Description : Output value for USB D- pin +#define SIO_GPIO_HI_OUT_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_USB_DP +// Description : Output value for USB D+ pin +#define SIO_GPIO_HI_OUT_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_GPIO +// Description : Output value for GPIO32...47 +#define SIO_GPIO_HI_OUT_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_SET +// Description : GPIO0...31 output value set +// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` +#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000018) +#define SIO_GPIO_OUT_SET_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_OUT_SET_MSB _u(31) +#define SIO_GPIO_OUT_SET_LSB _u(0) +#define SIO_GPIO_OUT_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_SET +// Description : Output value set for GPIO32..47, QSPI IOs and USB pins. +// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= +// wdata` +#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x0000001c) +#define SIO_GPIO_HI_OUT_SET_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_QSPI_SD +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_QSPI_CSN +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_QSPI_SCK +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_USB_DM +#define SIO_GPIO_HI_OUT_SET_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_SET_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_SET_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_SET_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_USB_DP +#define SIO_GPIO_HI_OUT_SET_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_SET_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_SET_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_SET_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_GPIO +#define SIO_GPIO_HI_OUT_SET_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_SET_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_SET_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_SET_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_SET_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OUT_CLR +// Description : GPIO0...31 output value clear +// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= +// ~wdata` +#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000020) +#define SIO_GPIO_OUT_CLR_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_CLR_MSB _u(31) +#define SIO_GPIO_OUT_CLR_LSB _u(0) +#define SIO_GPIO_OUT_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_CLR +// Description : Output value clear for GPIO32..47, QSPI IOs and USB pins. +// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// &= ~wdata` +#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000024) +#define SIO_GPIO_HI_OUT_CLR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_QSPI_SD +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_QSPI_CSN +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_QSPI_SCK +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_USB_DM +#define SIO_GPIO_HI_OUT_CLR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_USB_DP +#define SIO_GPIO_HI_OUT_CLR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_GPIO +#define SIO_GPIO_HI_OUT_CLR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_CLR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_CLR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_CLR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_CLR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OUT_XOR +// Description : GPIO0...31 output value XOR +// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= +// wdata` +#define SIO_GPIO_OUT_XOR_OFFSET _u(0x00000028) +#define SIO_GPIO_OUT_XOR_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_XOR_MSB _u(31) +#define SIO_GPIO_OUT_XOR_LSB _u(0) +#define SIO_GPIO_OUT_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_XOR +// Description : Output value XOR for GPIO32..47, QSPI IOs and USB pins. +// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// ^= wdata` +#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000002c) +#define SIO_GPIO_HI_OUT_XOR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_QSPI_SD +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_QSPI_CSN +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_QSPI_SCK +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_USB_DM +#define SIO_GPIO_HI_OUT_XOR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_USB_DP +#define SIO_GPIO_HI_OUT_XOR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_GPIO +#define SIO_GPIO_HI_OUT_XOR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_XOR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_XOR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_XOR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_XOR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE +// Description : GPIO0...31 output enable +// Set output enable (1/0 -> output/input) for GPIO0...31. Reading +// back gives the last value written. +// +// If core 0 and core 1 both write to GPIO_OE simultaneously (or +// to a SET/CLR/XOR alias), the result is as though the write from +// core 0 took place first, and the write from core 1 was then +// applied to that intermediate result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_OE_OFFSET _u(0x00000030) +#define SIO_GPIO_OE_BITS _u(0xffffffff) +#define SIO_GPIO_OE_RESET _u(0x00000000) +#define SIO_GPIO_OE_MSB _u(31) +#define SIO_GPIO_OE_LSB _u(0) +#define SIO_GPIO_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE +// Description : Output enable value for GPIO32...47, QSPI IOs and USB pins. +// +// Write output enable (1/0 -> output/input). Reading back gives +// the last value written. If core 0 and core 1 both write to +// GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the +// result is as though the write from core 0 took place first, and +// the write from core 1 was then applied to that intermediate +// result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_HI_OE_OFFSET _u(0x00000034) +#define SIO_GPIO_HI_OE_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_QSPI_SD +// Description : Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and +// SD3 pins +#define SIO_GPIO_HI_OE_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_QSPI_CSN +// Description : Output enable value for QSPI CSn pin +#define SIO_GPIO_HI_OE_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_QSPI_SCK +// Description : Output enable value for QSPI SCK pin +#define SIO_GPIO_HI_OE_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_USB_DM +// Description : Output enable value for USB D- pin +#define SIO_GPIO_HI_OE_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_USB_DP +// Description : Output enable value for USB D+ pin +#define SIO_GPIO_HI_OE_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_GPIO +// Description : Output enable value for GPIO32...47 +#define SIO_GPIO_HI_OE_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_SET +// Description : GPIO0...31 output enable set +// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` +#define SIO_GPIO_OE_SET_OFFSET _u(0x00000038) +#define SIO_GPIO_OE_SET_BITS _u(0xffffffff) +#define SIO_GPIO_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_OE_SET_MSB _u(31) +#define SIO_GPIO_OE_SET_LSB _u(0) +#define SIO_GPIO_OE_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_SET +// Description : Output enable set for GPIO32...47, QSPI IOs and USB pins. +// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= +// wdata` +#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x0000003c) +#define SIO_GPIO_HI_OE_SET_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_QSPI_SD +#define SIO_GPIO_HI_OE_SET_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_QSPI_CSN +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_QSPI_SCK +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_USB_DM +#define SIO_GPIO_HI_OE_SET_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_SET_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_SET_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_SET_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_USB_DP +#define SIO_GPIO_HI_OE_SET_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_SET_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_SET_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_SET_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_GPIO +#define SIO_GPIO_HI_OE_SET_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_SET_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_SET_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_SET_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_SET_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE_CLR +// Description : GPIO0...31 output enable clear +// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= +// ~wdata` +#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000040) +#define SIO_GPIO_OE_CLR_BITS _u(0xffffffff) +#define SIO_GPIO_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OE_CLR_MSB _u(31) +#define SIO_GPIO_OE_CLR_LSB _u(0) +#define SIO_GPIO_OE_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_CLR +// Description : Output enable clear for GPIO32...47, QSPI IOs and USB pins. +// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= +// ~wdata` +#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000044) +#define SIO_GPIO_HI_OE_CLR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_QSPI_SD +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_QSPI_CSN +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_QSPI_SCK +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_USB_DM +#define SIO_GPIO_HI_OE_CLR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_CLR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_CLR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_CLR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_USB_DP +#define SIO_GPIO_HI_OE_CLR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_CLR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_CLR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_CLR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_GPIO +#define SIO_GPIO_HI_OE_CLR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_CLR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_CLR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_CLR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_CLR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE_XOR +// Description : GPIO0...31 output enable XOR +// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= +// wdata` +#define SIO_GPIO_OE_XOR_OFFSET _u(0x00000048) +#define SIO_GPIO_OE_XOR_BITS _u(0xffffffff) +#define SIO_GPIO_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OE_XOR_MSB _u(31) +#define SIO_GPIO_OE_XOR_LSB _u(0) +#define SIO_GPIO_OE_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_XOR +// Description : Output enable XOR for GPIO32...47, QSPI IOs and USB pins. +// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE +// ^= wdata` +#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) +#define SIO_GPIO_HI_OE_XOR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_QSPI_SD +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_QSPI_CSN +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_QSPI_SCK +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_USB_DM +#define SIO_GPIO_HI_OE_XOR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_XOR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_XOR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_XOR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_USB_DP +#define SIO_GPIO_HI_OE_XOR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_XOR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_XOR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_XOR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_GPIO +#define SIO_GPIO_HI_OE_XOR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_XOR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_XOR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_XOR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_XOR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_FIFO_ST +// Description : Status register for inter-core FIFOs (mailboxes). +// There is one FIFO in the core 0 -> core 1 direction, and one +// core 1 -> core 0. Both are 32 bits wide and 8 words deep. +// Core 0 can see the read side of the 1->0 FIFO (RX), and the +// write side of 0->1 FIFO (TX). +// Core 1 can see the read side of the 0->1 FIFO (RX), and the +// write side of 1->0 FIFO (TX). +// The SIO IRQ for each core is the logical OR of the VLD, WOF and +// ROE fields of its FIFO_ST register. +#define SIO_FIFO_ST_OFFSET _u(0x00000050) +#define SIO_FIFO_ST_BITS _u(0x0000000f) +#define SIO_FIFO_ST_RESET _u(0x00000002) +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_ROE +// Description : Sticky flag indicating the RX FIFO was read when empty. This +// read was ignored by the FIFO. +#define SIO_FIFO_ST_ROE_RESET _u(0x0) +#define SIO_FIFO_ST_ROE_BITS _u(0x00000008) +#define SIO_FIFO_ST_ROE_MSB _u(3) +#define SIO_FIFO_ST_ROE_LSB _u(3) +#define SIO_FIFO_ST_ROE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_WOF +// Description : Sticky flag indicating the TX FIFO was written when full. This +// write was ignored by the FIFO. +#define SIO_FIFO_ST_WOF_RESET _u(0x0) +#define SIO_FIFO_ST_WOF_BITS _u(0x00000004) +#define SIO_FIFO_ST_WOF_MSB _u(2) +#define SIO_FIFO_ST_WOF_LSB _u(2) +#define SIO_FIFO_ST_WOF_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_RDY +// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR +// is ready for more data) +#define SIO_FIFO_ST_RDY_RESET _u(0x1) +#define SIO_FIFO_ST_RDY_BITS _u(0x00000002) +#define SIO_FIFO_ST_RDY_MSB _u(1) +#define SIO_FIFO_ST_RDY_LSB _u(1) +#define SIO_FIFO_ST_RDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_VLD +// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD +// is valid) +#define SIO_FIFO_ST_VLD_RESET _u(0x0) +#define SIO_FIFO_ST_VLD_BITS _u(0x00000001) +#define SIO_FIFO_ST_VLD_MSB _u(0) +#define SIO_FIFO_ST_VLD_LSB _u(0) +#define SIO_FIFO_ST_VLD_ACCESS "RO" +// ============================================================================= +// Register : SIO_FIFO_WR +// Description : Write access to this core's TX FIFO +#define SIO_FIFO_WR_OFFSET _u(0x00000054) +#define SIO_FIFO_WR_BITS _u(0xffffffff) +#define SIO_FIFO_WR_RESET _u(0x00000000) +#define SIO_FIFO_WR_MSB _u(31) +#define SIO_FIFO_WR_LSB _u(0) +#define SIO_FIFO_WR_ACCESS "WF" +// ============================================================================= +// Register : SIO_FIFO_RD +// Description : Read access to this core's RX FIFO +#define SIO_FIFO_RD_OFFSET _u(0x00000058) +#define SIO_FIFO_RD_BITS _u(0xffffffff) +#define SIO_FIFO_RD_RESET "-" +#define SIO_FIFO_RD_MSB _u(31) +#define SIO_FIFO_RD_LSB _u(0) +#define SIO_FIFO_RD_ACCESS "RF" +// ============================================================================= +// Register : SIO_SPINLOCK_ST +// Description : Spinlock state +// A bitmap containing the state of all 32 spinlocks (1=locked). +// Mainly intended for debugging. +#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) +#define SIO_SPINLOCK_ST_BITS _u(0xffffffff) +#define SIO_SPINLOCK_ST_RESET _u(0x00000000) +#define SIO_SPINLOCK_ST_MSB _u(31) +#define SIO_SPINLOCK_ST_LSB _u(0) +#define SIO_SPINLOCK_ST_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) +#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_MSB _u(31) +#define SIO_INTERP0_ACCUM0_LSB _u(0) +#define SIO_INTERP0_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) +#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_MSB _u(31) +#define SIO_INTERP0_ACCUM1_LSB _u(0) +#define SIO_INTERP0_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) +#define SIO_INTERP0_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE0_MSB _u(31) +#define SIO_INTERP0_BASE0_LSB _u(0) +#define SIO_INTERP0_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) +#define SIO_INTERP0_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE1_RESET _u(0x00000000) +#define SIO_INTERP0_BASE1_MSB _u(31) +#define SIO_INTERP0_BASE1_LSB _u(0) +#define SIO_INTERP0_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) +#define SIO_INTERP0_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE2_RESET _u(0x00000000) +#define SIO_INTERP0_BASE2_MSB _u(31) +#define SIO_INTERP0_BASE2_LSB _u(0) +#define SIO_INTERP0_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) +#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE0_MSB _u(31) +#define SIO_INTERP0_POP_LANE0_LSB _u(0) +#define SIO_INTERP0_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) +#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE1_MSB _u(31) +#define SIO_INTERP0_POP_LANE1_LSB _u(0) +#define SIO_INTERP0_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) +#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_POP_FULL_MSB _u(31) +#define SIO_INTERP0_POP_FULL_LSB _u(0) +#define SIO_INTERP0_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) +#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE0_LSB _u(0) +#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) +#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE1_LSB _u(0) +#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) +#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_FULL_MSB _u(31) +#define SIO_INTERP0_PEEK_FULL_LSB _u(0) +#define SIO_INTERP0_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) +#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) +#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_BLEND +// Description : Only present on INTERP0 on each core. If BLEND mode is enabled: +// - LANE1 result is a linear interpolation between BASE0 and +// BASE1, controlled +// by the 8 LSBs of lane 1 shift and mask value (a fractional +// number between +// 0 and 255/256ths) +// - LANE0 result does not have BASE0 added (yields only the 8 +// LSBs of lane 1 shift+mask value) +// - FULL result does not have lane 1 shift+mask value added +// (BASE2 + lane 0 shift+mask) +// LANE1 SIGNED flag controls whether the interpolation is signed +// or unsigned. +#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) +#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) +#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) +#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) +#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) +#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) +#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) +#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE_1AND0_MSB _u(31) +#define SIO_INTERP0_BASE_1AND0_LSB _u(0) +#define SIO_INTERP0_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) +#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_MSB _u(31) +#define SIO_INTERP1_ACCUM0_LSB _u(0) +#define SIO_INTERP1_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) +#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_MSB _u(31) +#define SIO_INTERP1_ACCUM1_LSB _u(0) +#define SIO_INTERP1_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) +#define SIO_INTERP1_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE0_MSB _u(31) +#define SIO_INTERP1_BASE0_LSB _u(0) +#define SIO_INTERP1_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) +#define SIO_INTERP1_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE1_RESET _u(0x00000000) +#define SIO_INTERP1_BASE1_MSB _u(31) +#define SIO_INTERP1_BASE1_LSB _u(0) +#define SIO_INTERP1_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) +#define SIO_INTERP1_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE2_RESET _u(0x00000000) +#define SIO_INTERP1_BASE2_MSB _u(31) +#define SIO_INTERP1_BASE2_LSB _u(0) +#define SIO_INTERP1_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) +#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE0_MSB _u(31) +#define SIO_INTERP1_POP_LANE0_LSB _u(0) +#define SIO_INTERP1_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) +#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE1_MSB _u(31) +#define SIO_INTERP1_POP_LANE1_LSB _u(0) +#define SIO_INTERP1_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) +#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_POP_FULL_MSB _u(31) +#define SIO_INTERP1_POP_FULL_LSB _u(0) +#define SIO_INTERP1_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) +#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE0_LSB _u(0) +#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) +#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE1_LSB _u(0) +#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) +#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_FULL_MSB _u(31) +#define SIO_INTERP1_PEEK_FULL_LSB _u(0) +#define SIO_INTERP1_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) +#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) +#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CLAMP +// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: +// - LANE0 result is shifted and masked ACCUM0, clamped by a lower +// bound of +// BASE0 and an upper bound of BASE1. +// - Signedness of these comparisons is determined by +// LANE0_CTRL_SIGNED +#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) +#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) +#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) +#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) +#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) +#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) +#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE_1AND0_MSB _u(31) +#define SIO_INTERP1_BASE_1AND0_LSB _u(0) +#define SIO_INTERP1_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_SPINLOCK0 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK0_OFFSET _u(0x00000100) +#define SIO_SPINLOCK0_BITS _u(0xffffffff) +#define SIO_SPINLOCK0_RESET _u(0x00000000) +#define SIO_SPINLOCK0_MSB _u(31) +#define SIO_SPINLOCK0_LSB _u(0) +#define SIO_SPINLOCK0_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK1 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK1_OFFSET _u(0x00000104) +#define SIO_SPINLOCK1_BITS _u(0xffffffff) +#define SIO_SPINLOCK1_RESET _u(0x00000000) +#define SIO_SPINLOCK1_MSB _u(31) +#define SIO_SPINLOCK1_LSB _u(0) +#define SIO_SPINLOCK1_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK2 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK2_OFFSET _u(0x00000108) +#define SIO_SPINLOCK2_BITS _u(0xffffffff) +#define SIO_SPINLOCK2_RESET _u(0x00000000) +#define SIO_SPINLOCK2_MSB _u(31) +#define SIO_SPINLOCK2_LSB _u(0) +#define SIO_SPINLOCK2_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK3 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK3_OFFSET _u(0x0000010c) +#define SIO_SPINLOCK3_BITS _u(0xffffffff) +#define SIO_SPINLOCK3_RESET _u(0x00000000) +#define SIO_SPINLOCK3_MSB _u(31) +#define SIO_SPINLOCK3_LSB _u(0) +#define SIO_SPINLOCK3_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK4 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK4_OFFSET _u(0x00000110) +#define SIO_SPINLOCK4_BITS _u(0xffffffff) +#define SIO_SPINLOCK4_RESET _u(0x00000000) +#define SIO_SPINLOCK4_MSB _u(31) +#define SIO_SPINLOCK4_LSB _u(0) +#define SIO_SPINLOCK4_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK5 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK5_OFFSET _u(0x00000114) +#define SIO_SPINLOCK5_BITS _u(0xffffffff) +#define SIO_SPINLOCK5_RESET _u(0x00000000) +#define SIO_SPINLOCK5_MSB _u(31) +#define SIO_SPINLOCK5_LSB _u(0) +#define SIO_SPINLOCK5_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK6 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK6_OFFSET _u(0x00000118) +#define SIO_SPINLOCK6_BITS _u(0xffffffff) +#define SIO_SPINLOCK6_RESET _u(0x00000000) +#define SIO_SPINLOCK6_MSB _u(31) +#define SIO_SPINLOCK6_LSB _u(0) +#define SIO_SPINLOCK6_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK7 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK7_OFFSET _u(0x0000011c) +#define SIO_SPINLOCK7_BITS _u(0xffffffff) +#define SIO_SPINLOCK7_RESET _u(0x00000000) +#define SIO_SPINLOCK7_MSB _u(31) +#define SIO_SPINLOCK7_LSB _u(0) +#define SIO_SPINLOCK7_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK8 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK8_OFFSET _u(0x00000120) +#define SIO_SPINLOCK8_BITS _u(0xffffffff) +#define SIO_SPINLOCK8_RESET _u(0x00000000) +#define SIO_SPINLOCK8_MSB _u(31) +#define SIO_SPINLOCK8_LSB _u(0) +#define SIO_SPINLOCK8_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK9 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK9_OFFSET _u(0x00000124) +#define SIO_SPINLOCK9_BITS _u(0xffffffff) +#define SIO_SPINLOCK9_RESET _u(0x00000000) +#define SIO_SPINLOCK9_MSB _u(31) +#define SIO_SPINLOCK9_LSB _u(0) +#define SIO_SPINLOCK9_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK10 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK10_OFFSET _u(0x00000128) +#define SIO_SPINLOCK10_BITS _u(0xffffffff) +#define SIO_SPINLOCK10_RESET _u(0x00000000) +#define SIO_SPINLOCK10_MSB _u(31) +#define SIO_SPINLOCK10_LSB _u(0) +#define SIO_SPINLOCK10_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK11 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK11_OFFSET _u(0x0000012c) +#define SIO_SPINLOCK11_BITS _u(0xffffffff) +#define SIO_SPINLOCK11_RESET _u(0x00000000) +#define SIO_SPINLOCK11_MSB _u(31) +#define SIO_SPINLOCK11_LSB _u(0) +#define SIO_SPINLOCK11_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK12 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK12_OFFSET _u(0x00000130) +#define SIO_SPINLOCK12_BITS _u(0xffffffff) +#define SIO_SPINLOCK12_RESET _u(0x00000000) +#define SIO_SPINLOCK12_MSB _u(31) +#define SIO_SPINLOCK12_LSB _u(0) +#define SIO_SPINLOCK12_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK13 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK13_OFFSET _u(0x00000134) +#define SIO_SPINLOCK13_BITS _u(0xffffffff) +#define SIO_SPINLOCK13_RESET _u(0x00000000) +#define SIO_SPINLOCK13_MSB _u(31) +#define SIO_SPINLOCK13_LSB _u(0) +#define SIO_SPINLOCK13_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK14 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK14_OFFSET _u(0x00000138) +#define SIO_SPINLOCK14_BITS _u(0xffffffff) +#define SIO_SPINLOCK14_RESET _u(0x00000000) +#define SIO_SPINLOCK14_MSB _u(31) +#define SIO_SPINLOCK14_LSB _u(0) +#define SIO_SPINLOCK14_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK15 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK15_OFFSET _u(0x0000013c) +#define SIO_SPINLOCK15_BITS _u(0xffffffff) +#define SIO_SPINLOCK15_RESET _u(0x00000000) +#define SIO_SPINLOCK15_MSB _u(31) +#define SIO_SPINLOCK15_LSB _u(0) +#define SIO_SPINLOCK15_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK16 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK16_OFFSET _u(0x00000140) +#define SIO_SPINLOCK16_BITS _u(0xffffffff) +#define SIO_SPINLOCK16_RESET _u(0x00000000) +#define SIO_SPINLOCK16_MSB _u(31) +#define SIO_SPINLOCK16_LSB _u(0) +#define SIO_SPINLOCK16_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK17 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK17_OFFSET _u(0x00000144) +#define SIO_SPINLOCK17_BITS _u(0xffffffff) +#define SIO_SPINLOCK17_RESET _u(0x00000000) +#define SIO_SPINLOCK17_MSB _u(31) +#define SIO_SPINLOCK17_LSB _u(0) +#define SIO_SPINLOCK17_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK18 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK18_OFFSET _u(0x00000148) +#define SIO_SPINLOCK18_BITS _u(0xffffffff) +#define SIO_SPINLOCK18_RESET _u(0x00000000) +#define SIO_SPINLOCK18_MSB _u(31) +#define SIO_SPINLOCK18_LSB _u(0) +#define SIO_SPINLOCK18_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK19 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK19_OFFSET _u(0x0000014c) +#define SIO_SPINLOCK19_BITS _u(0xffffffff) +#define SIO_SPINLOCK19_RESET _u(0x00000000) +#define SIO_SPINLOCK19_MSB _u(31) +#define SIO_SPINLOCK19_LSB _u(0) +#define SIO_SPINLOCK19_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK20 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK20_OFFSET _u(0x00000150) +#define SIO_SPINLOCK20_BITS _u(0xffffffff) +#define SIO_SPINLOCK20_RESET _u(0x00000000) +#define SIO_SPINLOCK20_MSB _u(31) +#define SIO_SPINLOCK20_LSB _u(0) +#define SIO_SPINLOCK20_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK21 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK21_OFFSET _u(0x00000154) +#define SIO_SPINLOCK21_BITS _u(0xffffffff) +#define SIO_SPINLOCK21_RESET _u(0x00000000) +#define SIO_SPINLOCK21_MSB _u(31) +#define SIO_SPINLOCK21_LSB _u(0) +#define SIO_SPINLOCK21_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK22 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK22_OFFSET _u(0x00000158) +#define SIO_SPINLOCK22_BITS _u(0xffffffff) +#define SIO_SPINLOCK22_RESET _u(0x00000000) +#define SIO_SPINLOCK22_MSB _u(31) +#define SIO_SPINLOCK22_LSB _u(0) +#define SIO_SPINLOCK22_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK23 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK23_OFFSET _u(0x0000015c) +#define SIO_SPINLOCK23_BITS _u(0xffffffff) +#define SIO_SPINLOCK23_RESET _u(0x00000000) +#define SIO_SPINLOCK23_MSB _u(31) +#define SIO_SPINLOCK23_LSB _u(0) +#define SIO_SPINLOCK23_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK24 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK24_OFFSET _u(0x00000160) +#define SIO_SPINLOCK24_BITS _u(0xffffffff) +#define SIO_SPINLOCK24_RESET _u(0x00000000) +#define SIO_SPINLOCK24_MSB _u(31) +#define SIO_SPINLOCK24_LSB _u(0) +#define SIO_SPINLOCK24_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK25 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK25_OFFSET _u(0x00000164) +#define SIO_SPINLOCK25_BITS _u(0xffffffff) +#define SIO_SPINLOCK25_RESET _u(0x00000000) +#define SIO_SPINLOCK25_MSB _u(31) +#define SIO_SPINLOCK25_LSB _u(0) +#define SIO_SPINLOCK25_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK26 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK26_OFFSET _u(0x00000168) +#define SIO_SPINLOCK26_BITS _u(0xffffffff) +#define SIO_SPINLOCK26_RESET _u(0x00000000) +#define SIO_SPINLOCK26_MSB _u(31) +#define SIO_SPINLOCK26_LSB _u(0) +#define SIO_SPINLOCK26_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK27 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK27_OFFSET _u(0x0000016c) +#define SIO_SPINLOCK27_BITS _u(0xffffffff) +#define SIO_SPINLOCK27_RESET _u(0x00000000) +#define SIO_SPINLOCK27_MSB _u(31) +#define SIO_SPINLOCK27_LSB _u(0) +#define SIO_SPINLOCK27_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK28 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK28_OFFSET _u(0x00000170) +#define SIO_SPINLOCK28_BITS _u(0xffffffff) +#define SIO_SPINLOCK28_RESET _u(0x00000000) +#define SIO_SPINLOCK28_MSB _u(31) +#define SIO_SPINLOCK28_LSB _u(0) +#define SIO_SPINLOCK28_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK29 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK29_OFFSET _u(0x00000174) +#define SIO_SPINLOCK29_BITS _u(0xffffffff) +#define SIO_SPINLOCK29_RESET _u(0x00000000) +#define SIO_SPINLOCK29_MSB _u(31) +#define SIO_SPINLOCK29_LSB _u(0) +#define SIO_SPINLOCK29_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK30 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK30_OFFSET _u(0x00000178) +#define SIO_SPINLOCK30_BITS _u(0xffffffff) +#define SIO_SPINLOCK30_RESET _u(0x00000000) +#define SIO_SPINLOCK30_MSB _u(31) +#define SIO_SPINLOCK30_LSB _u(0) +#define SIO_SPINLOCK30_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK31 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK31_OFFSET _u(0x0000017c) +#define SIO_SPINLOCK31_BITS _u(0xffffffff) +#define SIO_SPINLOCK31_RESET _u(0x00000000) +#define SIO_SPINLOCK31_MSB _u(31) +#define SIO_SPINLOCK31_LSB _u(0) +#define SIO_SPINLOCK31_ACCESS "RW" +// ============================================================================= +// Register : SIO_DOORBELL_OUT_SET +// Description : Trigger a doorbell interrupt on the opposite core. +// +// Write 1 to a bit to set the corresponding bit in DOORBELL_IN on +// the opposite core. This raises the opposite core's doorbell +// interrupt. +// +// Read to get the status of the doorbells currently asserted on +// the opposite core. This is equivalent to that core reading its +// own DOORBELL_IN status. +#define SIO_DOORBELL_OUT_SET_OFFSET _u(0x00000180) +#define SIO_DOORBELL_OUT_SET_BITS _u(0x000000ff) +#define SIO_DOORBELL_OUT_SET_RESET _u(0x00000000) +#define SIO_DOORBELL_OUT_SET_MSB _u(7) +#define SIO_DOORBELL_OUT_SET_LSB _u(0) +#define SIO_DOORBELL_OUT_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_DOORBELL_OUT_CLR +// Description : Clear doorbells which have been posted to the opposite core. +// This register is intended for debugging and initialisation +// purposes. +// +// Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding +// bit in DOORBELL_IN on the opposite core. Clearing all bits will +// cause that core's doorbell interrupt to deassert. Since the +// usual order of events is for software to send events using +// DOORBELL_OUT_SET, and acknowledge incoming events by writing to +// DOORBELL_IN_CLR, this register should be used with caution to +// avoid race conditions. +// +// Reading returns the status of the doorbells currently asserted +// on the other core, i.e. is equivalent to that core reading its +// own DOORBELL_IN status. +#define SIO_DOORBELL_OUT_CLR_OFFSET _u(0x00000184) +#define SIO_DOORBELL_OUT_CLR_BITS _u(0x000000ff) +#define SIO_DOORBELL_OUT_CLR_RESET _u(0x00000000) +#define SIO_DOORBELL_OUT_CLR_MSB _u(7) +#define SIO_DOORBELL_OUT_CLR_LSB _u(0) +#define SIO_DOORBELL_OUT_CLR_ACCESS "WC" +// ============================================================================= +// Register : SIO_DOORBELL_IN_SET +// Description : Write 1s to trigger doorbell interrupts on this core. Read to +// get status of doorbells currently asserted on this core. +#define SIO_DOORBELL_IN_SET_OFFSET _u(0x00000188) +#define SIO_DOORBELL_IN_SET_BITS _u(0x000000ff) +#define SIO_DOORBELL_IN_SET_RESET _u(0x00000000) +#define SIO_DOORBELL_IN_SET_MSB _u(7) +#define SIO_DOORBELL_IN_SET_LSB _u(0) +#define SIO_DOORBELL_IN_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_DOORBELL_IN_CLR +// Description : Check and acknowledge doorbells posted to this core. This +// core's doorbell interrupt is asserted when any bit in this +// register is 1. +// +// Write 1 to each bit to clear that bit. The doorbell interrupt +// deasserts once all bits are cleared. Read to get status of +// doorbells currently asserted on this core. +#define SIO_DOORBELL_IN_CLR_OFFSET _u(0x0000018c) +#define SIO_DOORBELL_IN_CLR_BITS _u(0x000000ff) +#define SIO_DOORBELL_IN_CLR_RESET _u(0x00000000) +#define SIO_DOORBELL_IN_CLR_MSB _u(7) +#define SIO_DOORBELL_IN_CLR_LSB _u(0) +#define SIO_DOORBELL_IN_CLR_ACCESS "WC" +// ============================================================================= +// Register : SIO_PERI_NONSEC +// Description : Detach certain core-local peripherals from Secure SIO, and +// attach them to Non-secure SIO, so that Non-secure software can +// use them. Attempting to access one of these peripherals from +// the Secure SIO when it is attached to the Non-secure SIO, or +// vice versa, will generate a bus error. +// +// This register is per-core, and is only present on the Secure +// SIO. +// +// Most SIO hardware is duplicated across the Secure and Non- +// secure SIO, so is not listed in this register. +#define SIO_PERI_NONSEC_OFFSET _u(0x00000190) +#define SIO_PERI_NONSEC_BITS _u(0x00000023) +#define SIO_PERI_NONSEC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_PERI_NONSEC_TMDS +// Description : IF 1, detach TMDS encoder (of this core) from the Secure SIO, +// and attach to the Non-secure SIO. +#define SIO_PERI_NONSEC_TMDS_RESET _u(0x0) +#define SIO_PERI_NONSEC_TMDS_BITS _u(0x00000020) +#define SIO_PERI_NONSEC_TMDS_MSB _u(5) +#define SIO_PERI_NONSEC_TMDS_LSB _u(5) +#define SIO_PERI_NONSEC_TMDS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_PERI_NONSEC_INTERP1 +// Description : If 1, detach interpolator 1 (of this core) from the Secure SIO, +// and attach to the Non-secure SIO. +#define SIO_PERI_NONSEC_INTERP1_RESET _u(0x0) +#define SIO_PERI_NONSEC_INTERP1_BITS _u(0x00000002) +#define SIO_PERI_NONSEC_INTERP1_MSB _u(1) +#define SIO_PERI_NONSEC_INTERP1_LSB _u(1) +#define SIO_PERI_NONSEC_INTERP1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_PERI_NONSEC_INTERP0 +// Description : If 1, detach interpolator 0 (of this core) from the Secure SIO, +// and attach to the Non-secure SIO. +#define SIO_PERI_NONSEC_INTERP0_RESET _u(0x0) +#define SIO_PERI_NONSEC_INTERP0_BITS _u(0x00000001) +#define SIO_PERI_NONSEC_INTERP0_MSB _u(0) +#define SIO_PERI_NONSEC_INTERP0_LSB _u(0) +#define SIO_PERI_NONSEC_INTERP0_ACCESS "RW" +// ============================================================================= +// Register : SIO_RISCV_SOFTIRQ +// Description : Control the assertion of the standard software interrupt +// (MIP.MSIP) on the RISC-V cores. +// +// Unlike the RISC-V timer, this interrupt is not routed to a +// normal system-level interrupt line, so can not be used by the +// Arm cores. +// +// It is safe for both cores to write to this register on the same +// cycle. The set/clear effect is accumulated across both cores, +// and then applied. If a flag is both set and cleared on the same +// cycle, only the set takes effect. +#define SIO_RISCV_SOFTIRQ_OFFSET _u(0x000001a0) +#define SIO_RISCV_SOFTIRQ_BITS _u(0x00000303) +#define SIO_RISCV_SOFTIRQ_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE1_CLR +// Description : Write 1 to atomically clear the core 1 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_BITS _u(0x00000200) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_MSB _u(9) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_LSB _u(9) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE0_CLR +// Description : Write 1 to atomically clear the core 0 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_BITS _u(0x00000100) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_MSB _u(8) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_LSB _u(8) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE1_SET +// Description : Write 1 to atomically set the core 1 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE1_SET_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_BITS _u(0x00000002) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_MSB _u(1) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_LSB _u(1) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE0_SET +// Description : Write 1 to atomically set the core 0 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE0_SET_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_BITS _u(0x00000001) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_MSB _u(0) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_LSB _u(0) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIME_CTRL +// Description : Control register for the RISC-V 64-bit Machine-mode timer. This +// timer is only present in the Secure SIO, so is only accessible +// to an Arm core in Secure mode or a RISC-V core in Machine mode. +// +// Note whilst this timer follows the RISC-V privileged +// specification, it is equally usable by the Arm cores. The +// interrupts are routed to normal system-level interrupt lines as +// well as to the MIP.MTIP inputs on the RISC-V cores. +#define SIO_MTIME_CTRL_OFFSET _u(0x000001a4) +#define SIO_MTIME_CTRL_BITS _u(0x0000000f) +#define SIO_MTIME_CTRL_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_DBGPAUSE_CORE1 +// Description : If 1, the timer pauses when core 1 is in the debug halt state. +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_RESET _u(0x1) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_BITS _u(0x00000008) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_MSB _u(3) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_LSB _u(3) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_DBGPAUSE_CORE0 +// Description : If 1, the timer pauses when core 0 is in the debug halt state. +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_RESET _u(0x1) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_BITS _u(0x00000004) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_MSB _u(2) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_LSB _u(2) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_FULLSPEED +// Description : If 1, increment the timer every cycle (i.e. run directly from +// the system clock), rather than incrementing on the system-level +// timer tick input. +#define SIO_MTIME_CTRL_FULLSPEED_RESET _u(0x0) +#define SIO_MTIME_CTRL_FULLSPEED_BITS _u(0x00000002) +#define SIO_MTIME_CTRL_FULLSPEED_MSB _u(1) +#define SIO_MTIME_CTRL_FULLSPEED_LSB _u(1) +#define SIO_MTIME_CTRL_FULLSPEED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_EN +// Description : Timer enable bit. When 0, the timer will not increment +// automatically. +#define SIO_MTIME_CTRL_EN_RESET _u(0x1) +#define SIO_MTIME_CTRL_EN_BITS _u(0x00000001) +#define SIO_MTIME_CTRL_EN_MSB _u(0) +#define SIO_MTIME_CTRL_EN_LSB _u(0) +#define SIO_MTIME_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIME +// Description : Read/write access to the high half of RISC-V Machine-mode +// timer. This register is shared between both cores. If both +// cores write on the same cycle, core 1 takes precedence. +#define SIO_MTIME_OFFSET _u(0x000001b0) +#define SIO_MTIME_BITS _u(0xffffffff) +#define SIO_MTIME_RESET _u(0x00000000) +#define SIO_MTIME_MSB _u(31) +#define SIO_MTIME_LSB _u(0) +#define SIO_MTIME_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIMEH +// Description : Read/write access to the high half of RISC-V Machine-mode +// timer. This register is shared between both cores. If both +// cores write on the same cycle, core 1 takes precedence. +#define SIO_MTIMEH_OFFSET _u(0x000001b4) +#define SIO_MTIMEH_BITS _u(0xffffffff) +#define SIO_MTIMEH_RESET _u(0x00000000) +#define SIO_MTIMEH_MSB _u(31) +#define SIO_MTIMEH_LSB _u(0) +#define SIO_MTIMEH_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIMECMP +// Description : Low half of RISC-V Machine-mode timer comparator. This register +// is core-local, i.e., each core gets a copy of this register, +// with the comparison result routed to its own interrupt line. +// +// The timer interrupt is asserted whenever MTIME is greater than +// or equal to MTIMECMP. This comparison is unsigned, and +// performed on the full 64-bit values. +#define SIO_MTIMECMP_OFFSET _u(0x000001b8) +#define SIO_MTIMECMP_BITS _u(0xffffffff) +#define SIO_MTIMECMP_RESET _u(0xffffffff) +#define SIO_MTIMECMP_MSB _u(31) +#define SIO_MTIMECMP_LSB _u(0) +#define SIO_MTIMECMP_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIMECMPH +// Description : High half of RISC-V Machine-mode timer comparator. This +// register is core-local. +// +// The timer interrupt is asserted whenever MTIME is greater than +// or equal to MTIMECMP. This comparison is unsigned, and +// performed on the full 64-bit values. +#define SIO_MTIMECMPH_OFFSET _u(0x000001bc) +#define SIO_MTIMECMPH_BITS _u(0xffffffff) +#define SIO_MTIMECMPH_RESET _u(0xffffffff) +#define SIO_MTIMECMPH_MSB _u(31) +#define SIO_MTIMECMPH_LSB _u(0) +#define SIO_MTIMECMPH_ACCESS "RW" +// ============================================================================= +// Register : SIO_TMDS_CTRL +// Description : Control register for TMDS encoder. +#define SIO_TMDS_CTRL_OFFSET _u(0x000001c0) +#define SIO_TMDS_CTRL_BITS _u(0x1f9fffff) +#define SIO_TMDS_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_CLEAR_BALANCE +// Description : Clear the running DC balance state of the TMDS encoders. This +// bit should be written once at the beginning of each scanline. +#define SIO_TMDS_CTRL_CLEAR_BALANCE_RESET _u(0x0) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_BITS _u(0x10000000) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_MSB _u(28) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_LSB _u(28) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_PIX2_NOSHIFT +// Description : When encoding two pixels's worth of symbols in one cycle (a +// read of a PEEK/POP_DOUBLE register), the second encoder sees a +// shifted version of the colour data register. +// +// This control disables that shift, so that both encoder layers +// see the same pixel data. This is used for pixel doubling. +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_RESET _u(0x0) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_BITS _u(0x08000000) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_MSB _u(27) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_LSB _u(27) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_PIX_SHIFT +// Description : Shift applied to the colour data register with each read of a +// POP alias register. +// +// Reading from the POP_SINGLE register, or reading from the +// POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), +// shifts by the indicated amount. +// +// Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear +// will shift by double the indicated amount. (Shift by 32 means +// no shift.) +// 0x0 -> Do not shift the colour data register. +// 0x1 -> Shift the colour data register by 1 bit +// 0x2 -> Shift the colour data register by 2 bits +// 0x3 -> Shift the colour data register by 4 bits +// 0x4 -> Shift the colour data register by 8 bits +// 0x5 -> Shift the colour data register by 16 bits +#define SIO_TMDS_CTRL_PIX_SHIFT_RESET _u(0x0) +#define SIO_TMDS_CTRL_PIX_SHIFT_BITS _u(0x07000000) +#define SIO_TMDS_CTRL_PIX_SHIFT_MSB _u(26) +#define SIO_TMDS_CTRL_PIX_SHIFT_LSB _u(24) +#define SIO_TMDS_CTRL_PIX_SHIFT_ACCESS "RW" +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_0 _u(0x0) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_1 _u(0x1) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_2 _u(0x2) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_4 _u(0x3) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_8 _u(0x4) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_16 _u(0x5) +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_INTERLEAVE +// Description : Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. +// +// When interleaving is disabled, each of the 3 symbols appears as +// a contiguous 10-bit field, with lane 0 being the least- +// significant and starting at bit 0 of the register. +// +// When interleaving is enabled, the symbols are packed into 5 +// chunks of 3 lanes times 2 bits (30 bits total). Each chunk +// contains two bits of a TMDS symbol per lane, with lane 0 being +// the least significant. +#define SIO_TMDS_CTRL_INTERLEAVE_RESET _u(0x0) +#define SIO_TMDS_CTRL_INTERLEAVE_BITS _u(0x00800000) +#define SIO_TMDS_CTRL_INTERLEAVE_MSB _u(23) +#define SIO_TMDS_CTRL_INTERLEAVE_LSB _u(23) +#define SIO_TMDS_CTRL_INTERLEAVE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L2_NBITS +// Description : Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 +// through 7). Remaining LSBs are masked to 0 after the rotate. +#define SIO_TMDS_CTRL_L2_NBITS_RESET _u(0x0) +#define SIO_TMDS_CTRL_L2_NBITS_BITS _u(0x001c0000) +#define SIO_TMDS_CTRL_L2_NBITS_MSB _u(20) +#define SIO_TMDS_CTRL_L2_NBITS_LSB _u(18) +#define SIO_TMDS_CTRL_L2_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L1_NBITS +// Description : Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 +// through 7). Remaining LSBs are masked to 0 after the rotate. +#define SIO_TMDS_CTRL_L1_NBITS_RESET _u(0x0) +#define SIO_TMDS_CTRL_L1_NBITS_BITS _u(0x00038000) +#define SIO_TMDS_CTRL_L1_NBITS_MSB _u(17) +#define SIO_TMDS_CTRL_L1_NBITS_LSB _u(15) +#define SIO_TMDS_CTRL_L1_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L0_NBITS +// Description : Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 +// through 7). Remaining LSBs are masked to 0 after the rotate. +#define SIO_TMDS_CTRL_L0_NBITS_RESET _u(0x0) +#define SIO_TMDS_CTRL_L0_NBITS_BITS _u(0x00007000) +#define SIO_TMDS_CTRL_L0_NBITS_MSB _u(14) +#define SIO_TMDS_CTRL_L0_NBITS_LSB _u(12) +#define SIO_TMDS_CTRL_L0_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L2_ROT +// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 +// bits, in order to get the MSB of the lane 2 (red) colour data +// aligned with the MSB of the 8-bit encoder input. +// +// For example, for RGB565 (red most significant), red is bits +// 15:11, so should be right-rotated by 8 bits to align with bits +// 7:3 of the encoder input. +#define SIO_TMDS_CTRL_L2_ROT_RESET _u(0x0) +#define SIO_TMDS_CTRL_L2_ROT_BITS _u(0x00000f00) +#define SIO_TMDS_CTRL_L2_ROT_MSB _u(11) +#define SIO_TMDS_CTRL_L2_ROT_LSB _u(8) +#define SIO_TMDS_CTRL_L2_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L1_ROT +// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 +// bits, in order to get the MSB of the lane 1 (green) colour data +// aligned with the MSB of the 8-bit encoder input. +// +// For example, for RGB565, green is bits 10:5, so should be +// right-rotated by 3 bits to align with bits 7:2 of the encoder +// input. +#define SIO_TMDS_CTRL_L1_ROT_RESET _u(0x0) +#define SIO_TMDS_CTRL_L1_ROT_BITS _u(0x000000f0) +#define SIO_TMDS_CTRL_L1_ROT_MSB _u(7) +#define SIO_TMDS_CTRL_L1_ROT_LSB _u(4) +#define SIO_TMDS_CTRL_L1_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L0_ROT +// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 +// bits, in order to get the MSB of the lane 0 (blue) colour data +// aligned with the MSB of the 8-bit encoder input. +// +// For example, for RGB565 (red most significant), blue is bits +// 4:0, so should be right-rotated by 13 to align with bits 7:3 of +// the encoder input. +#define SIO_TMDS_CTRL_L0_ROT_RESET _u(0x0) +#define SIO_TMDS_CTRL_L0_ROT_BITS _u(0x0000000f) +#define SIO_TMDS_CTRL_L0_ROT_MSB _u(3) +#define SIO_TMDS_CTRL_L0_ROT_LSB _u(0) +#define SIO_TMDS_CTRL_L0_ROT_ACCESS "RW" +// ============================================================================= +// Register : SIO_TMDS_WDATA +// Description : Write-only access to the TMDS colour data register. +#define SIO_TMDS_WDATA_OFFSET _u(0x000001c4) +#define SIO_TMDS_WDATA_BITS _u(0xffffffff) +#define SIO_TMDS_WDATA_RESET _u(0x00000000) +#define SIO_TMDS_WDATA_MSB _u(31) +#define SIO_TMDS_WDATA_LSB _u(0) +#define SIO_TMDS_WDATA_ACCESS "WO" +// ============================================================================= +// Register : SIO_TMDS_PEEK_SINGLE +// Description : Get the encoding of one pixel's worth of colour data, packed +// into a 32-bit value (3x10-bit symbols). +// +// The PEEK alias does not shift the colour register when read, +// but still advances the running DC balance state of each +// encoder. This is useful for pixel doubling. +#define SIO_TMDS_PEEK_SINGLE_OFFSET _u(0x000001c8) +#define SIO_TMDS_PEEK_SINGLE_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_SINGLE_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_SINGLE_MSB _u(31) +#define SIO_TMDS_PEEK_SINGLE_LSB _u(0) +#define SIO_TMDS_PEEK_SINGLE_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_SINGLE +// Description : Get the encoding of one pixel's worth of colour data, packed +// into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 +// bits (30 bits total). Each chunk contains two bits of a TMDS +// symbol per lane. This format is intended for shifting out with +// the HSTX peripheral on RP2350. +// +// The POP alias shifts the colour register when read, as well as +// advancing the running DC balance state of each encoder. +#define SIO_TMDS_POP_SINGLE_OFFSET _u(0x000001cc) +#define SIO_TMDS_POP_SINGLE_BITS _u(0xffffffff) +#define SIO_TMDS_POP_SINGLE_RESET _u(0x00000000) +#define SIO_TMDS_POP_SINGLE_MSB _u(31) +#define SIO_TMDS_POP_SINGLE_LSB _u(0) +#define SIO_TMDS_POP_SINGLE_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_PEEK_DOUBLE_L0 +// Description : Get lane 0 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The PEEK alias does not shift the colour register when read, +// but still advances the lane 0 DC balance state. This is useful +// if all 3 lanes' worth of encode are to be read at once, rather +// than processing the entire scanline for one lane before moving +// to the next lane. +#define SIO_TMDS_PEEK_DOUBLE_L0_OFFSET _u(0x000001d0) +#define SIO_TMDS_PEEK_DOUBLE_L0_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_DOUBLE_L0_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_DOUBLE_L0_MSB _u(31) +#define SIO_TMDS_PEEK_DOUBLE_L0_LSB _u(0) +#define SIO_TMDS_PEEK_DOUBLE_L0_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_DOUBLE_L0 +// Description : Get lane 0 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The POP alias shifts the colour register when read, according +// to the values of PIX_SHIFT and PIX2_NOSHIFT. +#define SIO_TMDS_POP_DOUBLE_L0_OFFSET _u(0x000001d4) +#define SIO_TMDS_POP_DOUBLE_L0_BITS _u(0xffffffff) +#define SIO_TMDS_POP_DOUBLE_L0_RESET _u(0x00000000) +#define SIO_TMDS_POP_DOUBLE_L0_MSB _u(31) +#define SIO_TMDS_POP_DOUBLE_L0_LSB _u(0) +#define SIO_TMDS_POP_DOUBLE_L0_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_PEEK_DOUBLE_L1 +// Description : Get lane 1 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The PEEK alias does not shift the colour register when read, +// but still advances the lane 1 DC balance state. This is useful +// if all 3 lanes' worth of encode are to be read at once, rather +// than processing the entire scanline for one lane before moving +// to the next lane. +#define SIO_TMDS_PEEK_DOUBLE_L1_OFFSET _u(0x000001d8) +#define SIO_TMDS_PEEK_DOUBLE_L1_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_DOUBLE_L1_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_DOUBLE_L1_MSB _u(31) +#define SIO_TMDS_PEEK_DOUBLE_L1_LSB _u(0) +#define SIO_TMDS_PEEK_DOUBLE_L1_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_DOUBLE_L1 +// Description : Get lane 1 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The POP alias shifts the colour register when read, according +// to the values of PIX_SHIFT and PIX2_NOSHIFT. +#define SIO_TMDS_POP_DOUBLE_L1_OFFSET _u(0x000001dc) +#define SIO_TMDS_POP_DOUBLE_L1_BITS _u(0xffffffff) +#define SIO_TMDS_POP_DOUBLE_L1_RESET _u(0x00000000) +#define SIO_TMDS_POP_DOUBLE_L1_MSB _u(31) +#define SIO_TMDS_POP_DOUBLE_L1_LSB _u(0) +#define SIO_TMDS_POP_DOUBLE_L1_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_PEEK_DOUBLE_L2 +// Description : Get lane 2 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The PEEK alias does not shift the colour register when read, +// but still advances the lane 2 DC balance state. This is useful +// if all 3 lanes' worth of encode are to be read at once, rather +// than processing the entire scanline for one lane before moving +// to the next lane. +#define SIO_TMDS_PEEK_DOUBLE_L2_OFFSET _u(0x000001e0) +#define SIO_TMDS_PEEK_DOUBLE_L2_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_DOUBLE_L2_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_DOUBLE_L2_MSB _u(31) +#define SIO_TMDS_PEEK_DOUBLE_L2_LSB _u(0) +#define SIO_TMDS_PEEK_DOUBLE_L2_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_DOUBLE_L2 +// Description : Get lane 2 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The POP alias shifts the colour register when read, according +// to the values of PIX_SHIFT and PIX2_NOSHIFT. +#define SIO_TMDS_POP_DOUBLE_L2_OFFSET _u(0x000001e4) +#define SIO_TMDS_POP_DOUBLE_L2_BITS _u(0xffffffff) +#define SIO_TMDS_POP_DOUBLE_L2_RESET _u(0x00000000) +#define SIO_TMDS_POP_DOUBLE_L2_MSB _u(31) +#define SIO_TMDS_POP_DOUBLE_L2_LSB _u(0) +#define SIO_TMDS_POP_DOUBLE_L2_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_SIO_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/spi.h b/src/rp2350/hardware_regs/include/hardware/regs/spi.h new file mode 100644 index 000000000..d9d3b14df --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/spi.h @@ -0,0 +1,523 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SPI +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_SPI_H +#define _HARDWARE_REGS_SPI_H +// ============================================================================= +// Register : SPI_SSPCR0 +// Description : Control register 0, SSPCR0 on page 3-4 +#define SPI_SSPCR0_OFFSET _u(0x00000000) +#define SPI_SSPCR0_BITS _u(0x0000ffff) +#define SPI_SSPCR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SCR +// Description : Serial clock rate. The value SCR is used to generate the +// transmit and receive bit rate of the PrimeCell SSP. The bit +// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even +// value from 2-254, programmed through the SSPCPSR register and +// SCR is a value from 0-255. +#define SPI_SSPCR0_SCR_RESET _u(0x00) +#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00) +#define SPI_SSPCR0_SCR_MSB _u(15) +#define SPI_SSPCR0_SCR_LSB _u(8) +#define SPI_SSPCR0_SCR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPH +// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. +// See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPH_RESET _u(0x0) +#define SPI_SSPCR0_SPH_BITS _u(0x00000080) +#define SPI_SSPCR0_SPH_MSB _u(7) +#define SPI_SSPCR0_SPH_LSB _u(7) +#define SPI_SSPCR0_SPH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPO +// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format +// only. See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPO_RESET _u(0x0) +#define SPI_SSPCR0_SPO_BITS _u(0x00000040) +#define SPI_SSPCR0_SPO_MSB _u(6) +#define SPI_SSPCR0_SPO_LSB _u(6) +#define SPI_SSPCR0_SPO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_FRF +// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous +// serial frame format. 10 National Microwire frame format. 11 +// Reserved, undefined operation. +#define SPI_SSPCR0_FRF_RESET _u(0x0) +#define SPI_SSPCR0_FRF_BITS _u(0x00000030) +#define SPI_SSPCR0_FRF_MSB _u(5) +#define SPI_SSPCR0_FRF_LSB _u(4) +#define SPI_SSPCR0_FRF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_DSS +// Description : Data Size Select: 0000 Reserved, undefined operation. 0001 +// Reserved, undefined operation. 0010 Reserved, undefined +// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. +// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit +// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. +// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. +#define SPI_SSPCR0_DSS_RESET _u(0x0) +#define SPI_SSPCR0_DSS_BITS _u(0x0000000f) +#define SPI_SSPCR0_DSS_MSB _u(3) +#define SPI_SSPCR0_DSS_LSB _u(0) +#define SPI_SSPCR0_DSS_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPCR1 +// Description : Control register 1, SSPCR1 on page 3-5 +#define SPI_SSPCR1_OFFSET _u(0x00000004) +#define SPI_SSPCR1_BITS _u(0x0000000f) +#define SPI_SSPCR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SOD +// Description : Slave-mode output disable. This bit is relevant only in the +// slave mode, MS=1. In multiple-slave systems, it is possible for +// an PrimeCell SSP master to broadcast a message to all slaves in +// the system while ensuring that only one slave drives data onto +// its serial output line. In such systems the RXD lines from +// multiple slaves could be tied together. To operate in such +// systems, the SOD bit can be set if the PrimeCell SSP slave is +// not supposed to drive the SSPTXD line: 0 SSP can drive the +// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD +// output in slave mode. +#define SPI_SSPCR1_SOD_RESET _u(0x0) +#define SPI_SSPCR1_SOD_BITS _u(0x00000008) +#define SPI_SSPCR1_SOD_MSB _u(3) +#define SPI_SSPCR1_SOD_LSB _u(3) +#define SPI_SSPCR1_SOD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_MS +// Description : Master or slave mode select. This bit can be modified only when +// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as +// master, default. 1 Device configured as slave. +#define SPI_SSPCR1_MS_RESET _u(0x0) +#define SPI_SSPCR1_MS_BITS _u(0x00000004) +#define SPI_SSPCR1_MS_MSB _u(2) +#define SPI_SSPCR1_MS_LSB _u(2) +#define SPI_SSPCR1_MS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SSE +// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP +// operation enabled. +#define SPI_SSPCR1_SSE_RESET _u(0x0) +#define SPI_SSPCR1_SSE_BITS _u(0x00000002) +#define SPI_SSPCR1_SSE_MSB _u(1) +#define SPI_SSPCR1_SSE_LSB _u(1) +#define SPI_SSPCR1_SSE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_LBM +// Description : Loop back mode: 0 Normal serial port operation enabled. 1 +// Output of transmit serial shifter is connected to input of +// receive serial shifter internally. +#define SPI_SSPCR1_LBM_RESET _u(0x0) +#define SPI_SSPCR1_LBM_BITS _u(0x00000001) +#define SPI_SSPCR1_LBM_MSB _u(0) +#define SPI_SSPCR1_LBM_LSB _u(0) +#define SPI_SSPCR1_LBM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPDR +// Description : Data register, SSPDR on page 3-6 +#define SPI_SSPDR_OFFSET _u(0x00000008) +#define SPI_SSPDR_BITS _u(0x0000ffff) +#define SPI_SSPDR_RESET "-" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDR_DATA +// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. +// You must right-justify data when the PrimeCell SSP is +// programmed for a data size that is less than 16 bits. Unused +// bits at the top are ignored by transmit logic. The receive +// logic automatically right-justifies. +#define SPI_SSPDR_DATA_RESET "-" +#define SPI_SSPDR_DATA_BITS _u(0x0000ffff) +#define SPI_SSPDR_DATA_MSB _u(15) +#define SPI_SSPDR_DATA_LSB _u(0) +#define SPI_SSPDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : SPI_SSPSR +// Description : Status register, SSPSR on page 3-7 +#define SPI_SSPSR_OFFSET _u(0x0000000c) +#define SPI_SSPSR_BITS _u(0x0000001f) +#define SPI_SSPSR_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_BSY +// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently +// transmitting and/or receiving a frame or the transmit FIFO is +// not empty. +#define SPI_SSPSR_BSY_RESET _u(0x0) +#define SPI_SSPSR_BSY_BITS _u(0x00000010) +#define SPI_SSPSR_BSY_MSB _u(4) +#define SPI_SSPSR_BSY_LSB _u(4) +#define SPI_SSPSR_BSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RFF +// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive +// FIFO is full. +#define SPI_SSPSR_RFF_RESET _u(0x0) +#define SPI_SSPSR_RFF_BITS _u(0x00000008) +#define SPI_SSPSR_RFF_MSB _u(3) +#define SPI_SSPSR_RFF_LSB _u(3) +#define SPI_SSPSR_RFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RNE +// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive +// FIFO is not empty. +#define SPI_SSPSR_RNE_RESET _u(0x0) +#define SPI_SSPSR_RNE_BITS _u(0x00000004) +#define SPI_SSPSR_RNE_MSB _u(2) +#define SPI_SSPSR_RNE_LSB _u(2) +#define SPI_SSPSR_RNE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TNF +// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit +// FIFO is not full. +#define SPI_SSPSR_TNF_RESET _u(0x1) +#define SPI_SSPSR_TNF_BITS _u(0x00000002) +#define SPI_SSPSR_TNF_MSB _u(1) +#define SPI_SSPSR_TNF_LSB _u(1) +#define SPI_SSPSR_TNF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TFE +// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 +// Transmit FIFO is empty. +#define SPI_SSPSR_TFE_RESET _u(0x1) +#define SPI_SSPSR_TFE_BITS _u(0x00000001) +#define SPI_SSPSR_TFE_MSB _u(0) +#define SPI_SSPSR_TFE_LSB _u(0) +#define SPI_SSPSR_TFE_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPCPSR +// Description : Clock prescale register, SSPCPSR on page 3-8 +#define SPI_SSPCPSR_OFFSET _u(0x00000010) +#define SPI_SSPCPSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCPSR_CPSDVSR +// Description : Clock prescale divisor. Must be an even number from 2-254, +// depending on the frequency of SSPCLK. The least significant bit +// always returns zero on reads. +#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00) +#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_CPSDVSR_MSB _u(7) +#define SPI_SSPCPSR_CPSDVSR_LSB _u(0) +#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPIMSC +// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 +#define SPI_SSPIMSC_OFFSET _u(0x00000014) +#define SPI_SSPIMSC_BITS _u(0x0000000f) +#define SPI_SSPIMSC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_TXIM +// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or +// less condition interrupt is masked. 1 Transmit FIFO half empty +// or less condition interrupt is not masked. +#define SPI_SSPIMSC_TXIM_RESET _u(0x0) +#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008) +#define SPI_SSPIMSC_TXIM_MSB _u(3) +#define SPI_SSPIMSC_TXIM_LSB _u(3) +#define SPI_SSPIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RXIM +// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less +// condition interrupt is masked. 1 Receive FIFO half full or less +// condition interrupt is not masked. +#define SPI_SSPIMSC_RXIM_RESET _u(0x0) +#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004) +#define SPI_SSPIMSC_RXIM_MSB _u(2) +#define SPI_SSPIMSC_RXIM_LSB _u(2) +#define SPI_SSPIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RTIM +// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no +// read prior to timeout period interrupt is masked. 1 Receive +// FIFO not empty and no read prior to timeout period interrupt is +// not masked. +#define SPI_SSPIMSC_RTIM_RESET _u(0x0) +#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002) +#define SPI_SSPIMSC_RTIM_MSB _u(1) +#define SPI_SSPIMSC_RTIM_LSB _u(1) +#define SPI_SSPIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RORIM +// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while +// full condition interrupt is masked. 1 Receive FIFO written to +// while full condition interrupt is not masked. +#define SPI_SSPIMSC_RORIM_RESET _u(0x0) +#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001) +#define SPI_SSPIMSC_RORIM_MSB _u(0) +#define SPI_SSPIMSC_RORIM_LSB _u(0) +#define SPI_SSPIMSC_RORIM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPRIS +// Description : Raw interrupt status register, SSPRIS on page 3-10 +#define SPI_SSPRIS_OFFSET _u(0x00000018) +#define SPI_SSPRIS_BITS _u(0x0000000f) +#define SPI_SSPRIS_RESET _u(0x00000008) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_TXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPTXINTR interrupt +#define SPI_SSPRIS_TXRIS_RESET _u(0x1) +#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008) +#define SPI_SSPRIS_TXRIS_MSB _u(3) +#define SPI_SSPRIS_TXRIS_LSB _u(3) +#define SPI_SSPRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRXINTR interrupt +#define SPI_SSPRIS_RXRIS_RESET _u(0x0) +#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004) +#define SPI_SSPRIS_RXRIS_MSB _u(2) +#define SPI_SSPRIS_RXRIS_LSB _u(2) +#define SPI_SSPRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RTRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRTINTR interrupt +#define SPI_SSPRIS_RTRIS_RESET _u(0x0) +#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002) +#define SPI_SSPRIS_RTRIS_MSB _u(1) +#define SPI_SSPRIS_RTRIS_LSB _u(1) +#define SPI_SSPRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RORRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRORINTR interrupt +#define SPI_SSPRIS_RORRIS_RESET _u(0x0) +#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001) +#define SPI_SSPRIS_RORRIS_MSB _u(0) +#define SPI_SSPRIS_RORRIS_LSB _u(0) +#define SPI_SSPRIS_RORRIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPMIS +// Description : Masked interrupt status register, SSPMIS on page 3-11 +#define SPI_SSPMIS_OFFSET _u(0x0000001c) +#define SPI_SSPMIS_BITS _u(0x0000000f) +#define SPI_SSPMIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_TXMIS +// Description : Gives the transmit FIFO masked interrupt state, after masking, +// of the SSPTXINTR interrupt +#define SPI_SSPMIS_TXMIS_RESET _u(0x0) +#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008) +#define SPI_SSPMIS_TXMIS_MSB _u(3) +#define SPI_SSPMIS_TXMIS_LSB _u(3) +#define SPI_SSPMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RXMIS +// Description : Gives the receive FIFO masked interrupt state, after masking, +// of the SSPRXINTR interrupt +#define SPI_SSPMIS_RXMIS_RESET _u(0x0) +#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004) +#define SPI_SSPMIS_RXMIS_MSB _u(2) +#define SPI_SSPMIS_RXMIS_LSB _u(2) +#define SPI_SSPMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RTMIS +// Description : Gives the receive timeout masked interrupt state, after +// masking, of the SSPRTINTR interrupt +#define SPI_SSPMIS_RTMIS_RESET _u(0x0) +#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002) +#define SPI_SSPMIS_RTMIS_MSB _u(1) +#define SPI_SSPMIS_RTMIS_LSB _u(1) +#define SPI_SSPMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RORMIS +// Description : Gives the receive over run masked interrupt status, after +// masking, of the SSPRORINTR interrupt +#define SPI_SSPMIS_RORMIS_RESET _u(0x0) +#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001) +#define SPI_SSPMIS_RORMIS_MSB _u(0) +#define SPI_SSPMIS_RORMIS_LSB _u(0) +#define SPI_SSPMIS_RORMIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPICR +// Description : Interrupt clear register, SSPICR on page 3-11 +#define SPI_SSPICR_OFFSET _u(0x00000020) +#define SPI_SSPICR_BITS _u(0x00000003) +#define SPI_SSPICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RTIC +// Description : Clears the SSPRTINTR interrupt +#define SPI_SSPICR_RTIC_RESET _u(0x0) +#define SPI_SSPICR_RTIC_BITS _u(0x00000002) +#define SPI_SSPICR_RTIC_MSB _u(1) +#define SPI_SSPICR_RTIC_LSB _u(1) +#define SPI_SSPICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RORIC +// Description : Clears the SSPRORINTR interrupt +#define SPI_SSPICR_RORIC_RESET _u(0x0) +#define SPI_SSPICR_RORIC_BITS _u(0x00000001) +#define SPI_SSPICR_RORIC_MSB _u(0) +#define SPI_SSPICR_RORIC_LSB _u(0) +#define SPI_SSPICR_RORIC_ACCESS "WC" +// ============================================================================= +// Register : SPI_SSPDMACR +// Description : DMA control register, SSPDMACR on page 3-12 +#define SPI_SSPDMACR_OFFSET _u(0x00000024) +#define SPI_SSPDMACR_BITS _u(0x00000003) +#define SPI_SSPDMACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_TXDMAE +// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002) +#define SPI_SSPDMACR_TXDMAE_MSB _u(1) +#define SPI_SSPDMACR_TXDMAE_LSB _u(1) +#define SPI_SSPDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_RXDMAE +// Description : Receive DMA Enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001) +#define SPI_SSPDMACR_RXDMAE_MSB _u(0) +#define SPI_SSPDMACR_RXDMAE_LSB _u(0) +#define SPI_SSPDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPPERIPHID0 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0) +#define SPI_SSPPERIPHID0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_RESET _u(0x00000022) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x22 +#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22) +#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7) +#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0) +#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID1 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4) +#define SPI_SSPPERIPHID1_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID1_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1) +#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7) +#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4) +#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3) +#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0) +#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID2 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8) +#define SPI_SSPPERIPHID2_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID2_RESET _u(0x00000034) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_REVISION +// Description : These bits return the peripheral revision +#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3) +#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID2_REVISION_MSB _u(7) +#define SPI_SSPPERIPHID2_REVISION_LSB _u(4) +#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4) +#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3) +#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0) +#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID3 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec) +#define SPI_SSPPERIPHID3_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7) +#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0) +#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID0 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0) +#define SPI_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID0_SSPPCELLID0 +// Description : These bits read back as 0x0D +#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d) +#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7) +#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0) +#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID1 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4) +#define SPI_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_RESET _u(0x000000f0) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID1_SSPPCELLID1 +// Description : These bits read back as 0xF0 +#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0) +#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7) +#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0) +#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID2 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8) +#define SPI_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID2_SSPPCELLID2 +// Description : These bits read back as 0x05 +#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05) +#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7) +#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0) +#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID3 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc) +#define SPI_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID3_SSPPCELLID3 +// Description : These bits read back as 0xB1 +#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1) +#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7) +#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) +#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_SPI_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/syscfg.h b/src/rp2350/hardware_regs/include/hardware/regs/syscfg.h new file mode 100644 index 000000000..455ebf175 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/syscfg.h @@ -0,0 +1,279 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSCFG +// Version : 1 +// Bus type : apb +// Description : Register block for various chip control signals +// ============================================================================= +#ifndef _HARDWARE_REGS_SYSCFG_H +#define _HARDWARE_REGS_SYSCFG_H +// ============================================================================= +// Register : SYSCFG_PROC_CONFIG +// Description : Configuration for processors +#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000) +#define SYSCFG_PROC_CONFIG_BITS _u(0x00000003) +#define SYSCFG_PROC_CONFIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED +// Description : Indication that proc1 has halted +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED +// Description : Indication that proc0 has halted +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 0...31. +#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004) +#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0xffffffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET _u(0x00000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS _u(0xffffffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB _u(31) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB _u(0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 32...47. USB GPIO 56..57 +// QSPI GPIO 58..63 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0xff00ffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS _u(0xf0000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB _u(31) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB _u(28) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS _u(0x08000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB _u(27) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB _u(27) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS _u(0x04000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB _u(26) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB _u(26) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS _u(0x02000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB _u(25) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB _u(25) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS _u(0x01000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB _u(24) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB _u(24) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET _u(0x0000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS _u(0x0000ffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB _u(15) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB _u(0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_DBGFORCE +// Description : Directly control the chip SWD debug port +#define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c) +#define SYSCFG_DBGFORCE_BITS _u(0x0000000f) +#define SYSCFG_DBGFORCE_RESET _u(0x00000006) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_ATTACH +// Description : Attach chip debug port to syscfg controls, and disconnect it +// from external SWD pads. +#define SYSCFG_DBGFORCE_ATTACH_RESET _u(0x0) +#define SYSCFG_DBGFORCE_ATTACH_BITS _u(0x00000008) +#define SYSCFG_DBGFORCE_ATTACH_MSB _u(3) +#define SYSCFG_DBGFORCE_ATTACH_LSB _u(3) +#define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_SWCLK +// Description : Directly drive SWCLK, if ATTACH is set +#define SYSCFG_DBGFORCE_SWCLK_RESET _u(0x1) +#define SYSCFG_DBGFORCE_SWCLK_BITS _u(0x00000004) +#define SYSCFG_DBGFORCE_SWCLK_MSB _u(2) +#define SYSCFG_DBGFORCE_SWCLK_LSB _u(2) +#define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_SWDI +// Description : Directly drive SWDIO input, if ATTACH is set +#define SYSCFG_DBGFORCE_SWDI_RESET _u(0x1) +#define SYSCFG_DBGFORCE_SWDI_BITS _u(0x00000002) +#define SYSCFG_DBGFORCE_SWDI_MSB _u(1) +#define SYSCFG_DBGFORCE_SWDI_LSB _u(1) +#define SYSCFG_DBGFORCE_SWDI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_SWDO +// Description : Observe the value of SWDIO output. +#define SYSCFG_DBGFORCE_SWDO_RESET "-" +#define SYSCFG_DBGFORCE_SWDO_BITS _u(0x00000001) +#define SYSCFG_DBGFORCE_SWDO_MSB _u(0) +#define SYSCFG_DBGFORCE_SWDO_LSB _u(0) +#define SYSCFG_DBGFORCE_SWDO_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_MEMPOWERDOWN +// Description : Control PD pins to memories. +// Set high to put memories to a low power state. In this state +// the memories will retain contents but not be accessible +// Use with caution +#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010) +#define SYSCFG_MEMPOWERDOWN_BITS _u(0x00001fff) +#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_BOOTRAM +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS _u(0x00001000) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB _u(12) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB _u(12) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_ROM +#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000800) +#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(11) +#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(11) +#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_USB +#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000400) +#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(10) +#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(10) +#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM9 +#define SYSCFG_MEMPOWERDOWN_SRAM9_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM9_BITS _u(0x00000200) +#define SYSCFG_MEMPOWERDOWN_SRAM9_MSB _u(9) +#define SYSCFG_MEMPOWERDOWN_SRAM9_LSB _u(9) +#define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM8 +#define SYSCFG_MEMPOWERDOWN_SRAM8_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM8_BITS _u(0x00000100) +#define SYSCFG_MEMPOWERDOWN_SRAM8_MSB _u(8) +#define SYSCFG_MEMPOWERDOWN_SRAM8_LSB _u(8) +#define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM7 +#define SYSCFG_MEMPOWERDOWN_SRAM7_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM7_BITS _u(0x00000080) +#define SYSCFG_MEMPOWERDOWN_SRAM7_MSB _u(7) +#define SYSCFG_MEMPOWERDOWN_SRAM7_LSB _u(7) +#define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM6 +#define SYSCFG_MEMPOWERDOWN_SRAM6_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM6_BITS _u(0x00000040) +#define SYSCFG_MEMPOWERDOWN_SRAM6_MSB _u(6) +#define SYSCFG_MEMPOWERDOWN_SRAM6_LSB _u(6) +#define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) +#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) +#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5) +#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) +#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) +#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4) +#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) +#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) +#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3) +#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) +#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) +#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2) +#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) +#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) +#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1) +#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) +#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_AUXCTRL +// Description : Auxiliary system control register +// * Bits 7:2: Reserved +// +// * Bit 1: When clear, the LPOSC output is XORed into the TRNG +// ROSC output as an additional, uncorrelated entropy source. When +// set, this behaviour is disabled. +// +// * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting +// its WDRESET input. This must be set before initiating a +// watchdog reset of the RSM from a stage that includes CLOCKS, if +// POWMAN is running from clk_ref at the point that the watchdog +// reset takes place. Otherwise, the short pulse generated on +// clk_ref by the reset of the CLOCKS block may affect POWMAN +// register state. +#define SYSCFG_AUXCTRL_OFFSET _u(0x00000014) +#define SYSCFG_AUXCTRL_BITS _u(0x000000ff) +#define SYSCFG_AUXCTRL_RESET _u(0x00000000) +#define SYSCFG_AUXCTRL_MSB _u(7) +#define SYSCFG_AUXCTRL_LSB _u(0) +#define SYSCFG_AUXCTRL_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_SYSCFG_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/sysinfo.h b/src/rp2350/hardware_regs/include/hardware/regs/sysinfo.h new file mode 100644 index 000000000..a6409bc2d --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/sysinfo.h @@ -0,0 +1,111 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSINFO +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_SYSINFO_H +#define _HARDWARE_REGS_SYSINFO_H +// ============================================================================= +// Register : SYSINFO_CHIP_ID +// Description : JEDEC JEP-106 compliant chip identifier. +#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) +#define SYSINFO_CHIP_ID_BITS _u(0xffffffff) +#define SYSINFO_CHIP_ID_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_REVISION +#define SYSINFO_CHIP_ID_REVISION_RESET "-" +#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) +#define SYSINFO_CHIP_ID_REVISION_MSB _u(31) +#define SYSINFO_CHIP_ID_REVISION_LSB _u(28) +#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_PART +#define SYSINFO_CHIP_ID_PART_RESET "-" +#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) +#define SYSINFO_CHIP_ID_PART_MSB _u(27) +#define SYSINFO_CHIP_ID_PART_LSB _u(12) +#define SYSINFO_CHIP_ID_PART_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_MANUFACTURER +#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" +#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000ffe) +#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) +#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(1) +#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_STOP_BIT +#define SYSINFO_CHIP_ID_STOP_BIT_RESET _u(0x1) +#define SYSINFO_CHIP_ID_STOP_BIT_BITS _u(0x00000001) +#define SYSINFO_CHIP_ID_STOP_BIT_MSB _u(0) +#define SYSINFO_CHIP_ID_STOP_BIT_LSB _u(0) +#define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_PACKAGE_SEL +#define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004) +#define SYSINFO_PACKAGE_SEL_BITS _u(0x00000001) +#define SYSINFO_PACKAGE_SEL_RESET _u(0x00000000) +#define SYSINFO_PACKAGE_SEL_MSB _u(0) +#define SYSINFO_PACKAGE_SEL_LSB _u(0) +#define SYSINFO_PACKAGE_SEL_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_PLATFORM +// Description : Platform register. Allows software to know what environment it +// is running in during pre-production development. Post- +// production, the PLATFORM is always ASIC, non-SIM. +#define SYSINFO_PLATFORM_OFFSET _u(0x00000008) +#define SYSINFO_PLATFORM_BITS _u(0x0000001f) +#define SYSINFO_PLATFORM_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_GATESIM +#define SYSINFO_PLATFORM_GATESIM_RESET "-" +#define SYSINFO_PLATFORM_GATESIM_BITS _u(0x00000010) +#define SYSINFO_PLATFORM_GATESIM_MSB _u(4) +#define SYSINFO_PLATFORM_GATESIM_LSB _u(4) +#define SYSINFO_PLATFORM_GATESIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_BATCHSIM +#define SYSINFO_PLATFORM_BATCHSIM_RESET "-" +#define SYSINFO_PLATFORM_BATCHSIM_BITS _u(0x00000008) +#define SYSINFO_PLATFORM_BATCHSIM_MSB _u(3) +#define SYSINFO_PLATFORM_BATCHSIM_LSB _u(3) +#define SYSINFO_PLATFORM_BATCHSIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_HDLSIM +#define SYSINFO_PLATFORM_HDLSIM_RESET "-" +#define SYSINFO_PLATFORM_HDLSIM_BITS _u(0x00000004) +#define SYSINFO_PLATFORM_HDLSIM_MSB _u(2) +#define SYSINFO_PLATFORM_HDLSIM_LSB _u(2) +#define SYSINFO_PLATFORM_HDLSIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_ASIC +#define SYSINFO_PLATFORM_ASIC_RESET "-" +#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) +#define SYSINFO_PLATFORM_ASIC_MSB _u(1) +#define SYSINFO_PLATFORM_ASIC_LSB _u(1) +#define SYSINFO_PLATFORM_ASIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_FPGA +#define SYSINFO_PLATFORM_FPGA_RESET "-" +#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) +#define SYSINFO_PLATFORM_FPGA_MSB _u(0) +#define SYSINFO_PLATFORM_FPGA_LSB _u(0) +#define SYSINFO_PLATFORM_FPGA_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_GITREF_RP2350 +// Description : Git hash of the chip source. Used to identify chip version. +#define SYSINFO_GITREF_RP2350_OFFSET _u(0x00000014) +#define SYSINFO_GITREF_RP2350_BITS _u(0xffffffff) +#define SYSINFO_GITREF_RP2350_RESET "-" +#define SYSINFO_GITREF_RP2350_MSB _u(31) +#define SYSINFO_GITREF_RP2350_LSB _u(0) +#define SYSINFO_GITREF_RP2350_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_SYSINFO_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/tbman.h b/src/rp2350/hardware_regs/include/hardware/regs/tbman.h new file mode 100644 index 000000000..59cf2d1bf --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/tbman.h @@ -0,0 +1,48 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TBMAN +// Version : 1 +// Bus type : apb +// Description : For managing simulation testbenches +// ============================================================================= +#ifndef _HARDWARE_REGS_TBMAN_H +#define _HARDWARE_REGS_TBMAN_H +// ============================================================================= +// Register : TBMAN_PLATFORM +// Description : Indicates the type of platform in use +#define TBMAN_PLATFORM_OFFSET _u(0x00000000) +#define TBMAN_PLATFORM_BITS _u(0x00000007) +#define TBMAN_PLATFORM_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_HDLSIM +// Description : Indicates the platform is a simulation +#define TBMAN_PLATFORM_HDLSIM_RESET _u(0x0) +#define TBMAN_PLATFORM_HDLSIM_BITS _u(0x00000004) +#define TBMAN_PLATFORM_HDLSIM_MSB _u(2) +#define TBMAN_PLATFORM_HDLSIM_LSB _u(2) +#define TBMAN_PLATFORM_HDLSIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_FPGA +// Description : Indicates the platform is an FPGA +#define TBMAN_PLATFORM_FPGA_RESET _u(0x0) +#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002) +#define TBMAN_PLATFORM_FPGA_MSB _u(1) +#define TBMAN_PLATFORM_FPGA_LSB _u(1) +#define TBMAN_PLATFORM_FPGA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_ASIC +// Description : Indicates the platform is an ASIC +#define TBMAN_PLATFORM_ASIC_RESET _u(0x1) +#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001) +#define TBMAN_PLATFORM_ASIC_MSB _u(0) +#define TBMAN_PLATFORM_ASIC_LSB _u(0) +#define TBMAN_PLATFORM_ASIC_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TBMAN_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/ticks.h b/src/rp2350/hardware_regs/include/hardware/regs/ticks.h new file mode 100644 index 000000000..79e13523d --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/ticks.h @@ -0,0 +1,275 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TICKS +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_TICKS_H +#define _HARDWARE_REGS_TICKS_H +// ============================================================================= +// Register : TICKS_PROC0_CTRL +// Description : Controls the tick generator +#define TICKS_PROC0_CTRL_OFFSET _u(0x00000000) +#define TICKS_PROC0_CTRL_BITS _u(0x00000003) +#define TICKS_PROC0_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC0_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_PROC0_CTRL_RUNNING_RESET "-" +#define TICKS_PROC0_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_PROC0_CTRL_RUNNING_MSB _u(1) +#define TICKS_PROC0_CTRL_RUNNING_LSB _u(1) +#define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC0_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_PROC0_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_PROC0_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_PROC0_CTRL_ENABLE_MSB _u(0) +#define TICKS_PROC0_CTRL_ENABLE_LSB _u(0) +#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC0_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004) +#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff) +#define TICKS_PROC0_CYCLES_RESET _u(0x00000000) +#define TICKS_PROC0_CYCLES_MSB _u(8) +#define TICKS_PROC0_CYCLES_LSB _u(0) +#define TICKS_PROC0_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC0_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008) +#define TICKS_PROC0_COUNT_BITS _u(0x000001ff) +#define TICKS_PROC0_COUNT_RESET "-" +#define TICKS_PROC0_COUNT_MSB _u(8) +#define TICKS_PROC0_COUNT_LSB _u(0) +#define TICKS_PROC0_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_PROC1_CTRL +// Description : Controls the tick generator +#define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c) +#define TICKS_PROC1_CTRL_BITS _u(0x00000003) +#define TICKS_PROC1_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC1_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_PROC1_CTRL_RUNNING_RESET "-" +#define TICKS_PROC1_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_PROC1_CTRL_RUNNING_MSB _u(1) +#define TICKS_PROC1_CTRL_RUNNING_LSB _u(1) +#define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC1_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_PROC1_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_PROC1_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_PROC1_CTRL_ENABLE_MSB _u(0) +#define TICKS_PROC1_CTRL_ENABLE_LSB _u(0) +#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC1_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010) +#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff) +#define TICKS_PROC1_CYCLES_RESET _u(0x00000000) +#define TICKS_PROC1_CYCLES_MSB _u(8) +#define TICKS_PROC1_CYCLES_LSB _u(0) +#define TICKS_PROC1_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC1_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014) +#define TICKS_PROC1_COUNT_BITS _u(0x000001ff) +#define TICKS_PROC1_COUNT_RESET "-" +#define TICKS_PROC1_COUNT_MSB _u(8) +#define TICKS_PROC1_COUNT_LSB _u(0) +#define TICKS_PROC1_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_TIMER0_CTRL +// Description : Controls the tick generator +#define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018) +#define TICKS_TIMER0_CTRL_BITS _u(0x00000003) +#define TICKS_TIMER0_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER0_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_TIMER0_CTRL_RUNNING_RESET "-" +#define TICKS_TIMER0_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_TIMER0_CTRL_RUNNING_MSB _u(1) +#define TICKS_TIMER0_CTRL_RUNNING_LSB _u(1) +#define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER0_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_TIMER0_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_TIMER0_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_TIMER0_CTRL_ENABLE_MSB _u(0) +#define TICKS_TIMER0_CTRL_ENABLE_LSB _u(0) +#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER0_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c) +#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff) +#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000) +#define TICKS_TIMER0_CYCLES_MSB _u(8) +#define TICKS_TIMER0_CYCLES_LSB _u(0) +#define TICKS_TIMER0_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER0_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020) +#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff) +#define TICKS_TIMER0_COUNT_RESET "-" +#define TICKS_TIMER0_COUNT_MSB _u(8) +#define TICKS_TIMER0_COUNT_LSB _u(0) +#define TICKS_TIMER0_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_TIMER1_CTRL +// Description : Controls the tick generator +#define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024) +#define TICKS_TIMER1_CTRL_BITS _u(0x00000003) +#define TICKS_TIMER1_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER1_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_TIMER1_CTRL_RUNNING_RESET "-" +#define TICKS_TIMER1_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_TIMER1_CTRL_RUNNING_MSB _u(1) +#define TICKS_TIMER1_CTRL_RUNNING_LSB _u(1) +#define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER1_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_TIMER1_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_TIMER1_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_TIMER1_CTRL_ENABLE_MSB _u(0) +#define TICKS_TIMER1_CTRL_ENABLE_LSB _u(0) +#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER1_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028) +#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff) +#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000) +#define TICKS_TIMER1_CYCLES_MSB _u(8) +#define TICKS_TIMER1_CYCLES_LSB _u(0) +#define TICKS_TIMER1_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER1_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c) +#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff) +#define TICKS_TIMER1_COUNT_RESET "-" +#define TICKS_TIMER1_COUNT_MSB _u(8) +#define TICKS_TIMER1_COUNT_LSB _u(0) +#define TICKS_TIMER1_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_WATCHDOG_CTRL +// Description : Controls the tick generator +#define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030) +#define TICKS_WATCHDOG_CTRL_BITS _u(0x00000003) +#define TICKS_WATCHDOG_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_WATCHDOG_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_WATCHDOG_CTRL_RUNNING_RESET "-" +#define TICKS_WATCHDOG_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_WATCHDOG_CTRL_RUNNING_MSB _u(1) +#define TICKS_WATCHDOG_CTRL_RUNNING_LSB _u(1) +#define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_WATCHDOG_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_WATCHDOG_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_WATCHDOG_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_WATCHDOG_CTRL_ENABLE_MSB _u(0) +#define TICKS_WATCHDOG_CTRL_ENABLE_LSB _u(0) +#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_WATCHDOG_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034) +#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff) +#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000) +#define TICKS_WATCHDOG_CYCLES_MSB _u(8) +#define TICKS_WATCHDOG_CYCLES_LSB _u(0) +#define TICKS_WATCHDOG_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_WATCHDOG_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038) +#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff) +#define TICKS_WATCHDOG_COUNT_RESET "-" +#define TICKS_WATCHDOG_COUNT_MSB _u(8) +#define TICKS_WATCHDOG_COUNT_LSB _u(0) +#define TICKS_WATCHDOG_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_RISCV_CTRL +// Description : Controls the tick generator +#define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c) +#define TICKS_RISCV_CTRL_BITS _u(0x00000003) +#define TICKS_RISCV_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_RISCV_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_RISCV_CTRL_RUNNING_RESET "-" +#define TICKS_RISCV_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_RISCV_CTRL_RUNNING_MSB _u(1) +#define TICKS_RISCV_CTRL_RUNNING_LSB _u(1) +#define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_RISCV_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_RISCV_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_RISCV_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_RISCV_CTRL_ENABLE_MSB _u(0) +#define TICKS_RISCV_CTRL_ENABLE_LSB _u(0) +#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_RISCV_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040) +#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff) +#define TICKS_RISCV_CYCLES_RESET _u(0x00000000) +#define TICKS_RISCV_CYCLES_MSB _u(8) +#define TICKS_RISCV_CYCLES_LSB _u(0) +#define TICKS_RISCV_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_RISCV_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044) +#define TICKS_RISCV_COUNT_BITS _u(0x000001ff) +#define TICKS_RISCV_COUNT_RESET "-" +#define TICKS_RISCV_COUNT_MSB _u(8) +#define TICKS_RISCV_COUNT_LSB _u(0) +#define TICKS_RISCV_COUNT_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TICKS_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/timer.h b/src/rp2350/hardware_regs/include/hardware/regs/timer.h new file mode 100644 index 000000000..c5f4d05b2 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/timer.h @@ -0,0 +1,346 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TIMER +// Version : 1 +// Bus type : apb +// Description : Controls time and alarms +// +// time is a 64 bit value indicating the time since power-on +// +// timeh is the top 32 bits of time & timel is the bottom 32 +// bits to change time write to timelw before timehw to read +// time read from timelr before timehr +// +// An alarm is set by setting alarm_enable and writing to the +// corresponding alarm register When an alarm is pending, the +// corresponding alarm_running signal will be high An alarm can +// be cancelled before it has finished by clearing the +// alarm_enable When an alarm fires, the corresponding +// alarm_irq is set and alarm_running is cleared To clear the +// interrupt write a 1 to the corresponding alarm_irq The timer +// can be locked to prevent writing +// ============================================================================= +#ifndef _HARDWARE_REGS_TIMER_H +#define _HARDWARE_REGS_TIMER_H +// ============================================================================= +// Register : TIMER_TIMEHW +// Description : Write to bits 63:32 of time always write timelw before timehw +#define TIMER_TIMEHW_OFFSET _u(0x00000000) +#define TIMER_TIMEHW_BITS _u(0xffffffff) +#define TIMER_TIMEHW_RESET _u(0x00000000) +#define TIMER_TIMEHW_MSB _u(31) +#define TIMER_TIMEHW_LSB _u(0) +#define TIMER_TIMEHW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMELW +// Description : Write to bits 31:0 of time writes do not get copied to time +// until timehw is written +#define TIMER_TIMELW_OFFSET _u(0x00000004) +#define TIMER_TIMELW_BITS _u(0xffffffff) +#define TIMER_TIMELW_RESET _u(0x00000000) +#define TIMER_TIMELW_MSB _u(31) +#define TIMER_TIMELW_LSB _u(0) +#define TIMER_TIMELW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMEHR +// Description : Read from bits 63:32 of time always read timelr before timehr +#define TIMER_TIMEHR_OFFSET _u(0x00000008) +#define TIMER_TIMEHR_BITS _u(0xffffffff) +#define TIMER_TIMEHR_RESET _u(0x00000000) +#define TIMER_TIMEHR_MSB _u(31) +#define TIMER_TIMEHR_LSB _u(0) +#define TIMER_TIMEHR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMELR +// Description : Read from bits 31:0 of time +#define TIMER_TIMELR_OFFSET _u(0x0000000c) +#define TIMER_TIMELR_BITS _u(0xffffffff) +#define TIMER_TIMELR_RESET _u(0x00000000) +#define TIMER_TIMELR_MSB _u(31) +#define TIMER_TIMELR_LSB _u(0) +#define TIMER_TIMELR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_ALARM0 +// Description : Arm alarm 0, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM0_OFFSET _u(0x00000010) +#define TIMER_ALARM0_BITS _u(0xffffffff) +#define TIMER_ALARM0_RESET _u(0x00000000) +#define TIMER_ALARM0_MSB _u(31) +#define TIMER_ALARM0_LSB _u(0) +#define TIMER_ALARM0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM1 +// Description : Arm alarm 1, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM1_OFFSET _u(0x00000014) +#define TIMER_ALARM1_BITS _u(0xffffffff) +#define TIMER_ALARM1_RESET _u(0x00000000) +#define TIMER_ALARM1_MSB _u(31) +#define TIMER_ALARM1_LSB _u(0) +#define TIMER_ALARM1_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM2 +// Description : Arm alarm 2, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM2_OFFSET _u(0x00000018) +#define TIMER_ALARM2_BITS _u(0xffffffff) +#define TIMER_ALARM2_RESET _u(0x00000000) +#define TIMER_ALARM2_MSB _u(31) +#define TIMER_ALARM2_LSB _u(0) +#define TIMER_ALARM2_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM3 +// Description : Arm alarm 3, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM3_OFFSET _u(0x0000001c) +#define TIMER_ALARM3_BITS _u(0xffffffff) +#define TIMER_ALARM3_RESET _u(0x00000000) +#define TIMER_ALARM3_MSB _u(31) +#define TIMER_ALARM3_LSB _u(0) +#define TIMER_ALARM3_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ARMED +// Description : Indicates the armed/disarmed status of each alarm. A write to +// the corresponding ALARMx register arms the alarm. Alarms +// automatically disarm upon firing, but writing ones here will +// disarm immediately without waiting to fire. +#define TIMER_ARMED_OFFSET _u(0x00000020) +#define TIMER_ARMED_BITS _u(0x0000000f) +#define TIMER_ARMED_RESET _u(0x00000000) +#define TIMER_ARMED_MSB _u(3) +#define TIMER_ARMED_LSB _u(0) +#define TIMER_ARMED_ACCESS "WC" +// ============================================================================= +// Register : TIMER_TIMERAWH +// Description : Raw read from bits 63:32 of time (no side effects) +#define TIMER_TIMERAWH_OFFSET _u(0x00000024) +#define TIMER_TIMERAWH_BITS _u(0xffffffff) +#define TIMER_TIMERAWH_RESET _u(0x00000000) +#define TIMER_TIMERAWH_MSB _u(31) +#define TIMER_TIMERAWH_LSB _u(0) +#define TIMER_TIMERAWH_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMERAWL +// Description : Raw read from bits 31:0 of time (no side effects) +#define TIMER_TIMERAWL_OFFSET _u(0x00000028) +#define TIMER_TIMERAWL_BITS _u(0xffffffff) +#define TIMER_TIMERAWL_RESET _u(0x00000000) +#define TIMER_TIMERAWL_MSB _u(31) +#define TIMER_TIMERAWL_LSB _u(0) +#define TIMER_TIMERAWL_ACCESS "RO" +// ============================================================================= +// Register : TIMER_DBGPAUSE +// Description : Set bits high to enable pause when the corresponding debug +// ports are active +#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c) +#define TIMER_DBGPAUSE_BITS _u(0x00000006) +#define TIMER_DBGPAUSE_RESET _u(0x00000007) +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG1 +// Description : Pause when processor 1 is in debug mode +#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004) +#define TIMER_DBGPAUSE_DBG1_MSB _u(2) +#define TIMER_DBGPAUSE_DBG1_LSB _u(2) +#define TIMER_DBGPAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG0 +// Description : Pause when processor 0 is in debug mode +#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002) +#define TIMER_DBGPAUSE_DBG0_MSB _u(1) +#define TIMER_DBGPAUSE_DBG0_LSB _u(1) +#define TIMER_DBGPAUSE_DBG0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_PAUSE +// Description : Set high to pause the timer +#define TIMER_PAUSE_OFFSET _u(0x00000030) +#define TIMER_PAUSE_BITS _u(0x00000001) +#define TIMER_PAUSE_RESET _u(0x00000000) +#define TIMER_PAUSE_MSB _u(0) +#define TIMER_PAUSE_LSB _u(0) +#define TIMER_PAUSE_ACCESS "RW" +// ============================================================================= +// Register : TIMER_LOCKED +// Description : Set locked bit to disable write access to timer Once set, +// cannot be cleared (without a reset) +#define TIMER_LOCKED_OFFSET _u(0x00000034) +#define TIMER_LOCKED_BITS _u(0x00000001) +#define TIMER_LOCKED_RESET _u(0x00000000) +#define TIMER_LOCKED_MSB _u(0) +#define TIMER_LOCKED_LSB _u(0) +#define TIMER_LOCKED_ACCESS "RW" +// ============================================================================= +// Register : TIMER_SOURCE +// Description : Selects the source for the timer. Defaults to the normal tick +// configured in the ticks block (typically configured to 1 +// microsecond). Writing to 1 will ignore the tick and count +// clk_sys cycles instead. +#define TIMER_SOURCE_OFFSET _u(0x00000038) +#define TIMER_SOURCE_BITS _u(0x00000001) +#define TIMER_SOURCE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_SOURCE_CLK_SYS +// 0x0 -> TICK +// 0x1 -> CLK_SYS +#define TIMER_SOURCE_CLK_SYS_RESET _u(0x0) +#define TIMER_SOURCE_CLK_SYS_BITS _u(0x00000001) +#define TIMER_SOURCE_CLK_SYS_MSB _u(0) +#define TIMER_SOURCE_CLK_SYS_LSB _u(0) +#define TIMER_SOURCE_CLK_SYS_ACCESS "RW" +#define TIMER_SOURCE_CLK_SYS_VALUE_TICK _u(0x0) +#define TIMER_SOURCE_CLK_SYS_VALUE_CLK_SYS _u(0x1) +// ============================================================================= +// Register : TIMER_INTR +// Description : Raw Interrupts +#define TIMER_INTR_OFFSET _u(0x0000003c) +#define TIMER_INTR_BITS _u(0x0000000f) +#define TIMER_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_3 +#define TIMER_INTR_ALARM_3_RESET _u(0x0) +#define TIMER_INTR_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTR_ALARM_3_MSB _u(3) +#define TIMER_INTR_ALARM_3_LSB _u(3) +#define TIMER_INTR_ALARM_3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_2 +#define TIMER_INTR_ALARM_2_RESET _u(0x0) +#define TIMER_INTR_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTR_ALARM_2_MSB _u(2) +#define TIMER_INTR_ALARM_2_LSB _u(2) +#define TIMER_INTR_ALARM_2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_1 +#define TIMER_INTR_ALARM_1_RESET _u(0x0) +#define TIMER_INTR_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTR_ALARM_1_MSB _u(1) +#define TIMER_INTR_ALARM_1_LSB _u(1) +#define TIMER_INTR_ALARM_1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_0 +#define TIMER_INTR_ALARM_0_RESET _u(0x0) +#define TIMER_INTR_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTR_ALARM_0_MSB _u(0) +#define TIMER_INTR_ALARM_0_LSB _u(0) +#define TIMER_INTR_ALARM_0_ACCESS "WC" +// ============================================================================= +// Register : TIMER_INTE +// Description : Interrupt Enable +#define TIMER_INTE_OFFSET _u(0x00000040) +#define TIMER_INTE_BITS _u(0x0000000f) +#define TIMER_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_3 +#define TIMER_INTE_ALARM_3_RESET _u(0x0) +#define TIMER_INTE_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTE_ALARM_3_MSB _u(3) +#define TIMER_INTE_ALARM_3_LSB _u(3) +#define TIMER_INTE_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_2 +#define TIMER_INTE_ALARM_2_RESET _u(0x0) +#define TIMER_INTE_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTE_ALARM_2_MSB _u(2) +#define TIMER_INTE_ALARM_2_LSB _u(2) +#define TIMER_INTE_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_1 +#define TIMER_INTE_ALARM_1_RESET _u(0x0) +#define TIMER_INTE_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTE_ALARM_1_MSB _u(1) +#define TIMER_INTE_ALARM_1_LSB _u(1) +#define TIMER_INTE_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_0 +#define TIMER_INTE_ALARM_0_RESET _u(0x0) +#define TIMER_INTE_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTE_ALARM_0_MSB _u(0) +#define TIMER_INTE_ALARM_0_LSB _u(0) +#define TIMER_INTE_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTF +// Description : Interrupt Force +#define TIMER_INTF_OFFSET _u(0x00000044) +#define TIMER_INTF_BITS _u(0x0000000f) +#define TIMER_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_3 +#define TIMER_INTF_ALARM_3_RESET _u(0x0) +#define TIMER_INTF_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTF_ALARM_3_MSB _u(3) +#define TIMER_INTF_ALARM_3_LSB _u(3) +#define TIMER_INTF_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_2 +#define TIMER_INTF_ALARM_2_RESET _u(0x0) +#define TIMER_INTF_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTF_ALARM_2_MSB _u(2) +#define TIMER_INTF_ALARM_2_LSB _u(2) +#define TIMER_INTF_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_1 +#define TIMER_INTF_ALARM_1_RESET _u(0x0) +#define TIMER_INTF_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTF_ALARM_1_MSB _u(1) +#define TIMER_INTF_ALARM_1_LSB _u(1) +#define TIMER_INTF_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_0 +#define TIMER_INTF_ALARM_0_RESET _u(0x0) +#define TIMER_INTF_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTF_ALARM_0_MSB _u(0) +#define TIMER_INTF_ALARM_0_LSB _u(0) +#define TIMER_INTF_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTS +// Description : Interrupt status after masking & forcing +#define TIMER_INTS_OFFSET _u(0x00000048) +#define TIMER_INTS_BITS _u(0x0000000f) +#define TIMER_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_3 +#define TIMER_INTS_ALARM_3_RESET _u(0x0) +#define TIMER_INTS_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTS_ALARM_3_MSB _u(3) +#define TIMER_INTS_ALARM_3_LSB _u(3) +#define TIMER_INTS_ALARM_3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_2 +#define TIMER_INTS_ALARM_2_RESET _u(0x0) +#define TIMER_INTS_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTS_ALARM_2_MSB _u(2) +#define TIMER_INTS_ALARM_2_LSB _u(2) +#define TIMER_INTS_ALARM_2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_1 +#define TIMER_INTS_ALARM_1_RESET _u(0x0) +#define TIMER_INTS_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTS_ALARM_1_MSB _u(1) +#define TIMER_INTS_ALARM_1_LSB _u(1) +#define TIMER_INTS_ALARM_1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_0 +#define TIMER_INTS_ALARM_0_RESET _u(0x0) +#define TIMER_INTS_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTS_ALARM_0_MSB _u(0) +#define TIMER_INTS_ALARM_0_LSB _u(0) +#define TIMER_INTS_ALARM_0_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TIMER_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/trng.h b/src/rp2350/hardware_regs/include/hardware/regs/trng.h new file mode 100644 index 000000000..c84c715b3 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/trng.h @@ -0,0 +1,625 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TRNG +// Version : 1 +// Bus type : apb +// Description : ARM TrustZone RNG register block +// ============================================================================= +#ifndef _HARDWARE_REGS_TRNG_H +#define _HARDWARE_REGS_TRNG_H +// ============================================================================= +// Register : TRNG_RNG_IMR +// Description : Interrupt masking. +#define TRNG_RNG_IMR_OFFSET _u(0x00000100) +#define TRNG_RNG_IMR_BITS _u(0xffffffff) +#define TRNG_RNG_IMR_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_RESERVED +// Description : RESERVED +#define TRNG_RNG_IMR_RESERVED_RESET _u(0x0000000) +#define TRNG_RNG_IMR_RESERVED_BITS _u(0xfffffff0) +#define TRNG_RNG_IMR_RESERVED_MSB _u(31) +#define TRNG_RNG_IMR_RESERVED_LSB _u(4) +#define TRNG_RNG_IMR_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_VN_ERR_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS _u(0x00000008) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB _u(3) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB _u(3) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS _u(0x00000004) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB _u(2) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB _u(2) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS _u(0x00000002) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB _u(1) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB _u(1) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_EHR_VALID_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS _u(0x00000001) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB _u(0) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB _u(0) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW" +// ============================================================================= +// Register : TRNG_RNG_ISR +// Description : RNG status register. If corresponding RNG_IMR bit is unmasked, +// an interrupt will be generated. +#define TRNG_RNG_ISR_OFFSET _u(0x00000104) +#define TRNG_RNG_ISR_BITS _u(0xffffffff) +#define TRNG_RNG_ISR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_RESERVED +// Description : RESERVED +#define TRNG_RNG_ISR_RESERVED_RESET _u(0x0000000) +#define TRNG_RNG_ISR_RESERVED_BITS _u(0xfffffff0) +#define TRNG_RNG_ISR_RESERVED_MSB _u(31) +#define TRNG_RNG_ISR_RESERVED_LSB _u(4) +#define TRNG_RNG_ISR_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_VN_ERR +// Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if +// 32 consecutive collected bits are identical, ZERO or ONE. +#define TRNG_RNG_ISR_VN_ERR_RESET _u(0x0) +#define TRNG_RNG_ISR_VN_ERR_BITS _u(0x00000008) +#define TRNG_RNG_ISR_VN_ERR_MSB _u(3) +#define TRNG_RNG_ISR_VN_ERR_LSB _u(3) +#define TRNG_RNG_ISR_VN_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_CRNGT_ERR +// Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs +// when two consecutive blocks of 16 collected bits are equal. +#define TRNG_RNG_ISR_CRNGT_ERR_RESET _u(0x0) +#define TRNG_RNG_ISR_CRNGT_ERR_BITS _u(0x00000004) +#define TRNG_RNG_ISR_CRNGT_ERR_MSB _u(2) +#define TRNG_RNG_ISR_CRNGT_ERR_LSB _u(2) +#define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_AUTOCORR_ERR +// Description : 1'b1 indicates Autocorrelation test failed four times in a row. +// When set, RNG cease from functioning until next reset. +#define TRNG_RNG_ISR_AUTOCORR_ERR_RESET _u(0x0) +#define TRNG_RNG_ISR_AUTOCORR_ERR_BITS _u(0x00000002) +#define TRNG_RNG_ISR_AUTOCORR_ERR_MSB _u(1) +#define TRNG_RNG_ISR_AUTOCORR_ERR_LSB _u(1) +#define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_EHR_VALID +// Description : 1'b1 indicates that 192 bits have been collected in the RNG, +// and are ready to be read. +#define TRNG_RNG_ISR_EHR_VALID_RESET _u(0x0) +#define TRNG_RNG_ISR_EHR_VALID_BITS _u(0x00000001) +#define TRNG_RNG_ISR_EHR_VALID_MSB _u(0) +#define TRNG_RNG_ISR_EHR_VALID_LSB _u(0) +#define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_ICR +// Description : Interrupt/status bit clear Register. +#define TRNG_RNG_ICR_OFFSET _u(0x00000108) +#define TRNG_RNG_ICR_BITS _u(0xffffffff) +#define TRNG_RNG_ICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_RESERVED +// Description : RESERVED +#define TRNG_RNG_ICR_RESERVED_RESET _u(0x0000000) +#define TRNG_RNG_ICR_RESERVED_BITS _u(0xfffffff0) +#define TRNG_RNG_ICR_RESERVED_MSB _u(31) +#define TRNG_RNG_ICR_RESERVED_LSB _u(4) +#define TRNG_RNG_ICR_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_VN_ERR +// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. +#define TRNG_RNG_ICR_VN_ERR_RESET _u(0x0) +#define TRNG_RNG_ICR_VN_ERR_BITS _u(0x00000008) +#define TRNG_RNG_ICR_VN_ERR_MSB _u(3) +#define TRNG_RNG_ICR_VN_ERR_LSB _u(3) +#define TRNG_RNG_ICR_VN_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_CRNGT_ERR +// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. +#define TRNG_RNG_ICR_CRNGT_ERR_RESET _u(0x0) +#define TRNG_RNG_ICR_CRNGT_ERR_BITS _u(0x00000004) +#define TRNG_RNG_ICR_CRNGT_ERR_MSB _u(2) +#define TRNG_RNG_ICR_CRNGT_ERR_LSB _u(2) +#define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_AUTOCORR_ERR +// Description : Cannot be cleared by SW! Only RNG reset clears this bit. +#define TRNG_RNG_ICR_AUTOCORR_ERR_RESET _u(0x0) +#define TRNG_RNG_ICR_AUTOCORR_ERR_BITS _u(0x00000002) +#define TRNG_RNG_ICR_AUTOCORR_ERR_MSB _u(1) +#define TRNG_RNG_ICR_AUTOCORR_ERR_LSB _u(1) +#define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_EHR_VALID +// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. +#define TRNG_RNG_ICR_EHR_VALID_RESET _u(0x0) +#define TRNG_RNG_ICR_EHR_VALID_BITS _u(0x00000001) +#define TRNG_RNG_ICR_EHR_VALID_MSB _u(0) +#define TRNG_RNG_ICR_EHR_VALID_LSB _u(0) +#define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_CONFIG +// Description : Selecting the inverter-chain length. +#define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c) +#define TRNG_TRNG_CONFIG_BITS _u(0xffffffff) +#define TRNG_TRNG_CONFIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_CONFIG_RESERVED +// Description : RESERVED +#define TRNG_TRNG_CONFIG_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_CONFIG_RESERVED_BITS _u(0xfffffffc) +#define TRNG_TRNG_CONFIG_RESERVED_MSB _u(31) +#define TRNG_TRNG_CONFIG_RESERVED_LSB _u(2) +#define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_CONFIG_RND_SRC_SEL +// Description : Selects the number of inverters (out of four possible +// selections) in the ring oscillator (the entropy source). +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET _u(0x0) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS _u(0x00000003) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB _u(1) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB _u(0) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_VALID +// Description : 192 bit collection indication. +#define TRNG_TRNG_VALID_OFFSET _u(0x00000110) +#define TRNG_TRNG_VALID_BITS _u(0xffffffff) +#define TRNG_TRNG_VALID_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_VALID_RESERVED +// Description : RESERVED +#define TRNG_TRNG_VALID_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_VALID_RESERVED_BITS _u(0xfffffffe) +#define TRNG_TRNG_VALID_RESERVED_MSB _u(31) +#define TRNG_TRNG_VALID_RESERVED_LSB _u(1) +#define TRNG_TRNG_VALID_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_VALID_EHR_VALID +// Description : 1'b1 indicates that collection of bits in the RNG is completed, +// and data can be read from EHR_DATA register. +#define TRNG_TRNG_VALID_EHR_VALID_RESET _u(0x0) +#define TRNG_TRNG_VALID_EHR_VALID_BITS _u(0x00000001) +#define TRNG_TRNG_VALID_EHR_VALID_MSB _u(0) +#define TRNG_TRNG_VALID_EHR_VALID_LSB _u(0) +#define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA0 +// Description : RNG collected bits. +// Bits [31:0] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA0_OFFSET _u(0x00000114) +#define TRNG_EHR_DATA0_BITS _u(0xffffffff) +#define TRNG_EHR_DATA0_RESET _u(0x00000000) +#define TRNG_EHR_DATA0_MSB _u(31) +#define TRNG_EHR_DATA0_LSB _u(0) +#define TRNG_EHR_DATA0_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA1 +// Description : RNG collected bits. +// Bits [63:32] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA1_OFFSET _u(0x00000118) +#define TRNG_EHR_DATA1_BITS _u(0xffffffff) +#define TRNG_EHR_DATA1_RESET _u(0x00000000) +#define TRNG_EHR_DATA1_MSB _u(31) +#define TRNG_EHR_DATA1_LSB _u(0) +#define TRNG_EHR_DATA1_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA2 +// Description : RNG collected bits. +// Bits [95:64] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA2_OFFSET _u(0x0000011c) +#define TRNG_EHR_DATA2_BITS _u(0xffffffff) +#define TRNG_EHR_DATA2_RESET _u(0x00000000) +#define TRNG_EHR_DATA2_MSB _u(31) +#define TRNG_EHR_DATA2_LSB _u(0) +#define TRNG_EHR_DATA2_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA3 +// Description : RNG collected bits. +// Bits [127:96] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA3_OFFSET _u(0x00000120) +#define TRNG_EHR_DATA3_BITS _u(0xffffffff) +#define TRNG_EHR_DATA3_RESET _u(0x00000000) +#define TRNG_EHR_DATA3_MSB _u(31) +#define TRNG_EHR_DATA3_LSB _u(0) +#define TRNG_EHR_DATA3_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA4 +// Description : RNG collected bits. +// Bits [159:128] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA4_OFFSET _u(0x00000124) +#define TRNG_EHR_DATA4_BITS _u(0xffffffff) +#define TRNG_EHR_DATA4_RESET _u(0x00000000) +#define TRNG_EHR_DATA4_MSB _u(31) +#define TRNG_EHR_DATA4_LSB _u(0) +#define TRNG_EHR_DATA4_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA5 +// Description : RNG collected bits. +// Bits [191:160] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA5_OFFSET _u(0x00000128) +#define TRNG_EHR_DATA5_BITS _u(0xffffffff) +#define TRNG_EHR_DATA5_RESET _u(0x00000000) +#define TRNG_EHR_DATA5_MSB _u(31) +#define TRNG_EHR_DATA5_LSB _u(0) +#define TRNG_EHR_DATA5_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RND_SOURCE_ENABLE +// Description : Enable signal for the random source. +#define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c) +#define TRNG_RND_SOURCE_ENABLE_BITS _u(0xffffffff) +#define TRNG_RND_SOURCE_ENABLE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RND_SOURCE_ENABLE_RESERVED +// Description : RESERVED +#define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET _u(0x00000000) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS _u(0xfffffffe) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB _u(31) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB _u(1) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN +// Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is +// disabled +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET _u(0x0) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS _u(0x00000001) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB _u(0) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB _u(0) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW" +// ============================================================================= +// Register : TRNG_SAMPLE_CNT1 +// Description : Counts clocks between sampling of random bit. +#define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130) +#define TRNG_SAMPLE_CNT1_BITS _u(0xffffffff) +#define TRNG_SAMPLE_CNT1_RESET _u(0x0000ffff) +// ----------------------------------------------------------------------------- +// Field : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1 +// Description : Sets the number of rng_clk cycles between two consecutive ring +// oscillator samples. Note! If the Von-Neuman is bypassed, the +// minimum value for sample counter must not be less then decimal +// seventeen +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET _u(0x0000ffff) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS _u(0xffffffff) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB _u(31) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB _u(0) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW" +// ============================================================================= +// Register : TRNG_AUTOCORR_STATISTIC +// Description : Statistic about Autocorrelation test activations. +#define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134) +#define TRNG_AUTOCORR_STATISTIC_BITS _u(0xffffffff) +#define TRNG_AUTOCORR_STATISTIC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_AUTOCORR_STATISTIC_RESERVED +// Description : RESERVED +#define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET _u(0x000) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS _u(0xffc00000) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB _u(31) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB _u(22) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS +// Description : Count each time an autocorrelation test fails. Any write to the +// register reset the counter. Stop collecting statistic if one of +// the counters reached the limit. +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET _u(0x00) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS _u(0x003fc000) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB _u(21) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB _u(14) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS +// Description : Count each time an autocorrelation test starts. Any write to +// the register reset the counter. Stop collecting statistic if +// one of the counters reached the limit. +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET _u(0x0000) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS _u(0x00003fff) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB _u(13) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB _u(0) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_DEBUG_CONTROL +// Description : Debug register. +#define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138) +#define TRNG_TRNG_DEBUG_CONTROL_BITS _u(0x0000000f) +#define TRNG_TRNG_DEBUG_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS +// Description : When set, the autocorrelation test in the TRNG module is +// bypassed. +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS _u(0x00000008) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB _u(3) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB _u(3) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS +// Description : When set, the CRNGT test in the RNG is bypassed. +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS _u(0x00000004) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB _u(2) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB _u(2) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS +// Description : When set, the Von-Neuman balancer is bypassed (including the 32 +// consecutive bits test). +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS _u(0x00000002) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB _u(1) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB _u(1) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_RESERVED +// Description : N/A +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS _u(0x00000001) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB _u(0) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB _u(0) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO" +// ============================================================================= +// Register : TRNG_TRNG_SW_RESET +// Description : Generate internal SW reset within the RNG block. +#define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140) +#define TRNG_TRNG_SW_RESET_BITS _u(0xffffffff) +#define TRNG_TRNG_SW_RESET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_SW_RESET_RESERVED +// Description : RESERVED +#define TRNG_TRNG_SW_RESET_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_SW_RESET_RESERVED_BITS _u(0xfffffffe) +#define TRNG_TRNG_SW_RESET_RESERVED_MSB _u(31) +#define TRNG_TRNG_SW_RESET_RESERVED_LSB _u(1) +#define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_SW_RESET_TRNG_SW_RESET +// Description : Writing 1'b1 to this register causes an internal RNG reset. +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET _u(0x0) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS _u(0x00000001) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB _u(0) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB _u(0) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW" +// ============================================================================= +// Register : TRNG_RNG_DEBUG_EN_INPUT +// Description : Enable the RNG debug mode +#define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4) +#define TRNG_RNG_DEBUG_EN_INPUT_BITS _u(0xffffffff) +#define TRNG_RNG_DEBUG_EN_INPUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_DEBUG_EN_INPUT_RESERVED +// Description : RESERVED +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET _u(0x00000000) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS _u(0xfffffffe) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB _u(31) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB _u(1) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN +// Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET _u(0x0) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS _u(0x00000001) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB _u(0) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB _u(0) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_BUSY +// Description : RNG Busy indication. +#define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8) +#define TRNG_TRNG_BUSY_BITS _u(0xffffffff) +#define TRNG_TRNG_BUSY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_BUSY_RESERVED +// Description : RESERVED +#define TRNG_TRNG_BUSY_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_BUSY_RESERVED_BITS _u(0xfffffffe) +#define TRNG_TRNG_BUSY_RESERVED_MSB _u(31) +#define TRNG_TRNG_BUSY_RESERVED_LSB _u(1) +#define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_BUSY_TRNG_BUSY +// Description : Reflects rng_busy status. +#define TRNG_TRNG_BUSY_TRNG_BUSY_RESET _u(0x0) +#define TRNG_TRNG_BUSY_TRNG_BUSY_BITS _u(0x00000001) +#define TRNG_TRNG_BUSY_TRNG_BUSY_MSB _u(0) +#define TRNG_TRNG_BUSY_TRNG_BUSY_LSB _u(0) +#define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RST_BITS_COUNTER +// Description : Reset the counter of collected bits in the RNG. +#define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc) +#define TRNG_RST_BITS_COUNTER_BITS _u(0xffffffff) +#define TRNG_RST_BITS_COUNTER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RST_BITS_COUNTER_RESERVED +// Description : RESERVED +#define TRNG_RST_BITS_COUNTER_RESERVED_RESET _u(0x00000000) +#define TRNG_RST_BITS_COUNTER_RESERVED_BITS _u(0xfffffffe) +#define TRNG_RST_BITS_COUNTER_RESERVED_MSB _u(31) +#define TRNG_RST_BITS_COUNTER_RESERVED_LSB _u(1) +#define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER +// Description : Writing any value to this address will reset the bits counter +// and RNG valid registers. RND_SORCE_ENABLE register must be +// unset in order for the reset to take place. +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET _u(0x0) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS _u(0x00000001) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB _u(0) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB _u(0) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW" +// ============================================================================= +// Register : TRNG_RNG_VERSION +// Description : Displays the version settings of the TRNG. +#define TRNG_RNG_VERSION_OFFSET _u(0x000001c0) +#define TRNG_RNG_VERSION_BITS _u(0xffffffff) +#define TRNG_RNG_VERSION_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_RESERVED +// Description : RESERVED +#define TRNG_RNG_VERSION_RESERVED_RESET _u(0x000000) +#define TRNG_RNG_VERSION_RESERVED_BITS _u(0xffffff00) +#define TRNG_RNG_VERSION_RESERVED_MSB _u(31) +#define TRNG_RNG_VERSION_RESERVED_LSB _u(8) +#define TRNG_RNG_VERSION_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_RNG_USE_5_SBOXES +// Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET _u(0x0) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS _u(0x00000080) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB _u(7) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB _u(7) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_RESEEDING_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS _u(0x00000040) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB _u(6) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB _u(6) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_KAT_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_KAT_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_KAT_EXISTS_BITS _u(0x00000020) +#define TRNG_RNG_VERSION_KAT_EXISTS_MSB _u(5) +#define TRNG_RNG_VERSION_KAT_EXISTS_LSB _u(5) +#define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_PRNG_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_PRNG_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_PRNG_EXISTS_BITS _u(0x00000010) +#define TRNG_RNG_VERSION_PRNG_EXISTS_MSB _u(4) +#define TRNG_RNG_VERSION_PRNG_EXISTS_LSB _u(4) +#define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET _u(0x0) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS _u(0x00000008) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB _u(3) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB _u(3) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_AUTOCORR_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS _u(0x00000004) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB _u(2) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB _u(2) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_CRNGT_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS _u(0x00000002) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB _u(1) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB _u(1) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_EHR_WIDTH_192 +// Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR +#define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET _u(0x0) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS _u(0x00000001) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB _u(0) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB _u(0) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_BIST_CNTR_0 +// Description : Collected BIST results. +#define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0) +#define TRNG_RNG_BIST_CNTR_0_BITS _u(0xffffffff) +#define TRNG_RNG_BIST_CNTR_0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_0_RESERVED +// Description : RESERVED +#define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET _u(0x000) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS _u(0xffc00000) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB _u(31) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB _u(22) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL +// Description : Reflects the results of RNG BIST counter. +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET _u(0x000000) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS _u(0x003fffff) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB _u(21) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB _u(0) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_BIST_CNTR_1 +// Description : Collected BIST results. +#define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4) +#define TRNG_RNG_BIST_CNTR_1_BITS _u(0xffffffff) +#define TRNG_RNG_BIST_CNTR_1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_1_RESERVED +// Description : RESERVED +#define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET _u(0x000) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS _u(0xffc00000) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB _u(31) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB _u(22) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL +// Description : Reflects the results of RNG BIST counter. +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET _u(0x000000) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS _u(0x003fffff) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB _u(21) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB _u(0) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_BIST_CNTR_2 +// Description : Collected BIST results. +#define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8) +#define TRNG_RNG_BIST_CNTR_2_BITS _u(0xffffffff) +#define TRNG_RNG_BIST_CNTR_2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_2_RESERVED +// Description : RESERVED +#define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET _u(0x000) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS _u(0xffc00000) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB _u(31) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB _u(22) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL +// Description : Reflects the results of RNG BIST counter. +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET _u(0x000000) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS _u(0x003fffff) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB _u(21) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB _u(0) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TRNG_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/uart.h b/src/rp2350/hardware_regs/include/hardware/regs/uart.h new file mode 100644 index 000000000..0f7f17ec0 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/uart.h @@ -0,0 +1,1150 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : UART +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_UART_H +#define _HARDWARE_REGS_UART_H +// ============================================================================= +// Register : UART_UARTDR +// Description : Data Register, UARTDR +#define UART_UARTDR_OFFSET _u(0x00000000) +#define UART_UARTDR_BITS _u(0x00000fff) +#define UART_UARTDR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// receive FIFO is already full. This is cleared to 0 once there +// is an empty space in the FIFO and a new character can be +// written to it. +#define UART_UARTDR_OE_RESET "-" +#define UART_UARTDR_OE_BITS _u(0x00000800) +#define UART_UARTDR_OE_MSB _u(11) +#define UART_UARTDR_OE_LSB _u(11) +#define UART_UARTDR_OE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity and stop bits). In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state), and the next valid start bit is +// received. +#define UART_UARTDR_BE_RESET "-" +#define UART_UARTDR_BE_BITS _u(0x00000400) +#define UART_UARTDR_BE_MSB _u(10) +#define UART_UARTDR_BE_LSB _u(10) +#define UART_UARTDR_BE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. In +// FIFO mode, this error is associated with the character at the +// top of the FIFO. +#define UART_UARTDR_PE_RESET "-" +#define UART_UARTDR_PE_BITS _u(0x00000200) +#define UART_UARTDR_PE_MSB _u(9) +#define UART_UARTDR_PE_LSB _u(9) +#define UART_UARTDR_PE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). In FIFO mode, this error is associated with the character +// at the top of the FIFO. +#define UART_UARTDR_FE_RESET "-" +#define UART_UARTDR_FE_BITS _u(0x00000100) +#define UART_UARTDR_FE_MSB _u(8) +#define UART_UARTDR_FE_LSB _u(8) +#define UART_UARTDR_FE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_DATA +// Description : Receive (read) data character. Transmit (write) data character. +#define UART_UARTDR_DATA_RESET "-" +#define UART_UARTDR_DATA_BITS _u(0x000000ff) +#define UART_UARTDR_DATA_MSB _u(7) +#define UART_UARTDR_DATA_LSB _u(0) +#define UART_UARTDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : UART_UARTRSR +// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR +#define UART_UARTRSR_OFFSET _u(0x00000004) +#define UART_UARTRSR_BITS _u(0x0000000f) +#define UART_UARTRSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// FIFO is already full. This bit is cleared to 0 by a write to +// UARTECR. The FIFO contents remain valid because no more data is +// written when the FIFO is full, only the contents of the shift +// register are overwritten. The CPU must now read the data, to +// empty the FIFO. +#define UART_UARTRSR_OE_RESET _u(0x0) +#define UART_UARTRSR_OE_BITS _u(0x00000008) +#define UART_UARTRSR_OE_MSB _u(3) +#define UART_UARTRSR_OE_LSB _u(3) +#define UART_UARTRSR_OE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity, and stop bits). This bit is cleared to 0 +// after a write to UARTECR. In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state) and the next valid start bit is +// received. +#define UART_UARTRSR_BE_RESET _u(0x0) +#define UART_UARTRSR_BE_BITS _u(0x00000004) +#define UART_UARTRSR_BE_MSB _u(2) +#define UART_UARTRSR_BE_LSB _u(2) +#define UART_UARTRSR_BE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. This +// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this +// error is associated with the character at the top of the FIFO. +#define UART_UARTRSR_PE_RESET _u(0x0) +#define UART_UARTRSR_PE_BITS _u(0x00000002) +#define UART_UARTRSR_PE_MSB _u(1) +#define UART_UARTRSR_PE_LSB _u(1) +#define UART_UARTRSR_PE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO +// mode, this error is associated with the character at the top of +// the FIFO. +#define UART_UARTRSR_FE_RESET _u(0x0) +#define UART_UARTRSR_FE_BITS _u(0x00000001) +#define UART_UARTRSR_FE_MSB _u(0) +#define UART_UARTRSR_FE_LSB _u(0) +#define UART_UARTRSR_FE_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTFR +// Description : Flag Register, UARTFR +#define UART_UARTFR_OFFSET _u(0x00000018) +#define UART_UARTFR_BITS _u(0x000001ff) +#define UART_UARTFR_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RI +// Description : Ring indicator. This bit is the complement of the UART ring +// indicator, nUARTRI, modem status input. That is, the bit is 1 +// when nUARTRI is LOW. +#define UART_UARTFR_RI_RESET "-" +#define UART_UARTFR_RI_BITS _u(0x00000100) +#define UART_UARTFR_RI_MSB _u(8) +#define UART_UARTFR_RI_LSB _u(8) +#define UART_UARTFR_RI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFE +// Description : Transmit FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the Line Control Register, UARTLCR_H. +// If the FIFO is disabled, this bit is set when the transmit +// holding register is empty. If the FIFO is enabled, the TXFE bit +// is set when the transmit FIFO is empty. This bit does not +// indicate if there is data in the transmit shift register. +#define UART_UARTFR_TXFE_RESET _u(0x1) +#define UART_UARTFR_TXFE_BITS _u(0x00000080) +#define UART_UARTFR_TXFE_MSB _u(7) +#define UART_UARTFR_TXFE_LSB _u(7) +#define UART_UARTFR_TXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFF +// Description : Receive FIFO full. The meaning of this bit depends on the state +// of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// full. If the FIFO is enabled, the RXFF bit is set when the +// receive FIFO is full. +#define UART_UARTFR_RXFF_RESET _u(0x0) +#define UART_UARTFR_RXFF_BITS _u(0x00000040) +#define UART_UARTFR_RXFF_MSB _u(6) +#define UART_UARTFR_RXFF_LSB _u(6) +#define UART_UARTFR_RXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFF +// Description : Transmit FIFO full. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the transmit holding register is +// full. If the FIFO is enabled, the TXFF bit is set when the +// transmit FIFO is full. +#define UART_UARTFR_TXFF_RESET _u(0x0) +#define UART_UARTFR_TXFF_BITS _u(0x00000020) +#define UART_UARTFR_TXFF_MSB _u(5) +#define UART_UARTFR_TXFF_LSB _u(5) +#define UART_UARTFR_TXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFE +// Description : Receive FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// empty. If the FIFO is enabled, the RXFE bit is set when the +// receive FIFO is empty. +#define UART_UARTFR_RXFE_RESET _u(0x1) +#define UART_UARTFR_RXFE_BITS _u(0x00000010) +#define UART_UARTFR_RXFE_MSB _u(4) +#define UART_UARTFR_RXFE_LSB _u(4) +#define UART_UARTFR_RXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_BUSY +// Description : UART busy. If this bit is set to 1, the UART is busy +// transmitting data. This bit remains set until the complete +// byte, including all the stop bits, has been sent from the shift +// register. This bit is set as soon as the transmit FIFO becomes +// non-empty, regardless of whether the UART is enabled or not. +#define UART_UARTFR_BUSY_RESET _u(0x0) +#define UART_UARTFR_BUSY_BITS _u(0x00000008) +#define UART_UARTFR_BUSY_MSB _u(3) +#define UART_UARTFR_BUSY_LSB _u(3) +#define UART_UARTFR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DCD +// Description : Data carrier detect. This bit is the complement of the UART +// data carrier detect, nUARTDCD, modem status input. That is, the +// bit is 1 when nUARTDCD is LOW. +#define UART_UARTFR_DCD_RESET "-" +#define UART_UARTFR_DCD_BITS _u(0x00000004) +#define UART_UARTFR_DCD_MSB _u(2) +#define UART_UARTFR_DCD_LSB _u(2) +#define UART_UARTFR_DCD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DSR +// Description : Data set ready. This bit is the complement of the UART data set +// ready, nUARTDSR, modem status input. That is, the bit is 1 when +// nUARTDSR is LOW. +#define UART_UARTFR_DSR_RESET "-" +#define UART_UARTFR_DSR_BITS _u(0x00000002) +#define UART_UARTFR_DSR_MSB _u(1) +#define UART_UARTFR_DSR_LSB _u(1) +#define UART_UARTFR_DSR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_CTS +// Description : Clear to send. This bit is the complement of the UART clear to +// send, nUARTCTS, modem status input. That is, the bit is 1 when +// nUARTCTS is LOW. +#define UART_UARTFR_CTS_RESET "-" +#define UART_UARTFR_CTS_BITS _u(0x00000001) +#define UART_UARTFR_CTS_MSB _u(0) +#define UART_UARTFR_CTS_LSB _u(0) +#define UART_UARTFR_CTS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTILPR +// Description : IrDA Low-Power Counter Register, UARTILPR +#define UART_UARTILPR_OFFSET _u(0x00000020) +#define UART_UARTILPR_BITS _u(0x000000ff) +#define UART_UARTILPR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTILPR_ILPDVSR +// Description : 8-bit low-power divisor value. These bits are cleared to 0 at +// reset. +#define UART_UARTILPR_ILPDVSR_RESET _u(0x00) +#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff) +#define UART_UARTILPR_ILPDVSR_MSB _u(7) +#define UART_UARTILPR_ILPDVSR_LSB _u(0) +#define UART_UARTILPR_ILPDVSR_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIBRD +// Description : Integer Baud Rate Register, UARTIBRD +#define UART_UARTIBRD_OFFSET _u(0x00000024) +#define UART_UARTIBRD_BITS _u(0x0000ffff) +#define UART_UARTIBRD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTIBRD_BAUD_DIVINT +// Description : The integer baud rate divisor. These bits are cleared to 0 on +// reset. +#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000) +#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff) +#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15) +#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0) +#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTFBRD +// Description : Fractional Baud Rate Register, UARTFBRD +#define UART_UARTFBRD_OFFSET _u(0x00000028) +#define UART_UARTFBRD_BITS _u(0x0000003f) +#define UART_UARTFBRD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTFBRD_BAUD_DIVFRAC +// Description : The fractional baud rate divisor. These bits are cleared to 0 +// on reset. +#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00) +#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f) +#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5) +#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0) +#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTLCR_H +// Description : Line Control Register, UARTLCR_H +#define UART_UARTLCR_H_OFFSET _u(0x0000002c) +#define UART_UARTLCR_H_BITS _u(0x000000ff) +#define UART_UARTLCR_H_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_SPS +// Description : Stick parity select. 0 = stick parity is disabled 1 = either: * +// if the EPS bit is 0 then the parity bit is transmitted and +// checked as a 1 * if the EPS bit is 1 then the parity bit is +// transmitted and checked as a 0. This bit has no effect when the +// PEN bit disables parity checking and generation. +#define UART_UARTLCR_H_SPS_RESET _u(0x0) +#define UART_UARTLCR_H_SPS_BITS _u(0x00000080) +#define UART_UARTLCR_H_SPS_MSB _u(7) +#define UART_UARTLCR_H_SPS_LSB _u(7) +#define UART_UARTLCR_H_SPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_WLEN +// Description : Word length. These bits indicate the number of data bits +// transmitted or received in a frame as follows: b11 = 8 bits b10 +// = 7 bits b01 = 6 bits b00 = 5 bits. +#define UART_UARTLCR_H_WLEN_RESET _u(0x0) +#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060) +#define UART_UARTLCR_H_WLEN_MSB _u(6) +#define UART_UARTLCR_H_WLEN_LSB _u(5) +#define UART_UARTLCR_H_WLEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_FEN +// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, +// the FIFOs become 1-byte-deep holding registers 1 = transmit and +// receive FIFO buffers are enabled (FIFO mode). +#define UART_UARTLCR_H_FEN_RESET _u(0x0) +#define UART_UARTLCR_H_FEN_BITS _u(0x00000010) +#define UART_UARTLCR_H_FEN_MSB _u(4) +#define UART_UARTLCR_H_FEN_LSB _u(4) +#define UART_UARTLCR_H_FEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_STP2 +// Description : Two stop bits select. If this bit is set to 1, two stop bits +// are transmitted at the end of the frame. The receive logic does +// not check for two stop bits being received. +#define UART_UARTLCR_H_STP2_RESET _u(0x0) +#define UART_UARTLCR_H_STP2_BITS _u(0x00000008) +#define UART_UARTLCR_H_STP2_MSB _u(3) +#define UART_UARTLCR_H_STP2_LSB _u(3) +#define UART_UARTLCR_H_STP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_EPS +// Description : Even parity select. Controls the type of parity the UART uses +// during transmission and reception: 0 = odd parity. The UART +// generates or checks for an odd number of 1s in the data and +// parity bits. 1 = even parity. The UART generates or checks for +// an even number of 1s in the data and parity bits. This bit has +// no effect when the PEN bit disables parity checking and +// generation. +#define UART_UARTLCR_H_EPS_RESET _u(0x0) +#define UART_UARTLCR_H_EPS_BITS _u(0x00000004) +#define UART_UARTLCR_H_EPS_MSB _u(2) +#define UART_UARTLCR_H_EPS_LSB _u(2) +#define UART_UARTLCR_H_EPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_PEN +// Description : Parity enable: 0 = parity is disabled and no parity bit added +// to the data frame 1 = parity checking and generation is +// enabled. +#define UART_UARTLCR_H_PEN_RESET _u(0x0) +#define UART_UARTLCR_H_PEN_BITS _u(0x00000002) +#define UART_UARTLCR_H_PEN_MSB _u(1) +#define UART_UARTLCR_H_PEN_LSB _u(1) +#define UART_UARTLCR_H_PEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_BRK +// Description : Send break. If this bit is set to 1, a low-level is continually +// output on the UARTTXD output, after completing transmission of +// the current character. For the proper execution of the break +// command, the software must set this bit for at least two +// complete frames. For normal use, this bit must be cleared to 0. +#define UART_UARTLCR_H_BRK_RESET _u(0x0) +#define UART_UARTLCR_H_BRK_BITS _u(0x00000001) +#define UART_UARTLCR_H_BRK_MSB _u(0) +#define UART_UARTLCR_H_BRK_LSB _u(0) +#define UART_UARTLCR_H_BRK_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTCR +// Description : Control Register, UARTCR +#define UART_UARTCR_OFFSET _u(0x00000030) +#define UART_UARTCR_BITS _u(0x0000ff87) +#define UART_UARTCR_RESET _u(0x00000300) +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_CTSEN +// Description : CTS hardware flow control enable. If this bit is set to 1, CTS +// hardware flow control is enabled. Data is only transmitted when +// the nUARTCTS signal is asserted. +#define UART_UARTCR_CTSEN_RESET _u(0x0) +#define UART_UARTCR_CTSEN_BITS _u(0x00008000) +#define UART_UARTCR_CTSEN_MSB _u(15) +#define UART_UARTCR_CTSEN_LSB _u(15) +#define UART_UARTCR_CTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTSEN +// Description : RTS hardware flow control enable. If this bit is set to 1, RTS +// hardware flow control is enabled. Data is only requested when +// there is space in the receive FIFO for it to be received. +#define UART_UARTCR_RTSEN_RESET _u(0x0) +#define UART_UARTCR_RTSEN_BITS _u(0x00004000) +#define UART_UARTCR_RTSEN_MSB _u(14) +#define UART_UARTCR_RTSEN_LSB _u(14) +#define UART_UARTCR_RTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT2 +// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem +// status output. That is, when the bit is programmed to a 1, the +// output is 0. For DTE this can be used as Ring Indicator (RI). +#define UART_UARTCR_OUT2_RESET _u(0x0) +#define UART_UARTCR_OUT2_BITS _u(0x00002000) +#define UART_UARTCR_OUT2_MSB _u(13) +#define UART_UARTCR_OUT2_LSB _u(13) +#define UART_UARTCR_OUT2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT1 +// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem +// status output. That is, when the bit is programmed to a 1 the +// output is 0. For DTE this can be used as Data Carrier Detect +// (DCD). +#define UART_UARTCR_OUT1_RESET _u(0x0) +#define UART_UARTCR_OUT1_BITS _u(0x00001000) +#define UART_UARTCR_OUT1_MSB _u(12) +#define UART_UARTCR_OUT1_LSB _u(12) +#define UART_UARTCR_OUT1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTS +// Description : Request to send. This bit is the complement of the UART request +// to send, nUARTRTS, modem status output. That is, when the bit +// is programmed to a 1 then nUARTRTS is LOW. +#define UART_UARTCR_RTS_RESET _u(0x0) +#define UART_UARTCR_RTS_BITS _u(0x00000800) +#define UART_UARTCR_RTS_MSB _u(11) +#define UART_UARTCR_RTS_LSB _u(11) +#define UART_UARTCR_RTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_DTR +// Description : Data transmit ready. This bit is the complement of the UART +// data transmit ready, nUARTDTR, modem status output. That is, +// when the bit is programmed to a 1 then nUARTDTR is LOW. +#define UART_UARTCR_DTR_RESET _u(0x0) +#define UART_UARTCR_DTR_BITS _u(0x00000400) +#define UART_UARTCR_DTR_MSB _u(10) +#define UART_UARTCR_DTR_LSB _u(10) +#define UART_UARTCR_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RXE +// Description : Receive enable. If this bit is set to 1, the receive section of +// the UART is enabled. Data reception occurs for either UART +// signals or SIR signals depending on the setting of the SIREN +// bit. When the UART is disabled in the middle of reception, it +// completes the current character before stopping. +#define UART_UARTCR_RXE_RESET _u(0x1) +#define UART_UARTCR_RXE_BITS _u(0x00000200) +#define UART_UARTCR_RXE_MSB _u(9) +#define UART_UARTCR_RXE_LSB _u(9) +#define UART_UARTCR_RXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_TXE +// Description : Transmit enable. If this bit is set to 1, the transmit section +// of the UART is enabled. Data transmission occurs for either +// UART signals, or SIR signals depending on the setting of the +// SIREN bit. When the UART is disabled in the middle of +// transmission, it completes the current character before +// stopping. +#define UART_UARTCR_TXE_RESET _u(0x1) +#define UART_UARTCR_TXE_BITS _u(0x00000100) +#define UART_UARTCR_TXE_MSB _u(8) +#define UART_UARTCR_TXE_LSB _u(8) +#define UART_UARTCR_TXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_LBE +// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is +// set to 1 and the SIRTEST bit in the Test Control Register, +// UARTTCR is set to 1, then the nSIROUT path is inverted, and fed +// through to the SIRIN path. The SIRTEST bit in the test register +// must be set to 1 to override the normal half-duplex SIR +// operation. This must be the requirement for accessing the test +// registers during normal operation, and SIRTEST must be cleared +// to 0 when loopback testing is finished. This feature reduces +// the amount of external coupling required during system test. If +// this bit is set to 1, and the SIRTEST bit is set to 0, the +// UARTTXD path is fed through to the UARTRXD path. In either SIR +// mode or UART mode, when this bit is set, the modem outputs are +// also fed through to the modem inputs. This bit is cleared to 0 +// on reset, to disable loopback. +#define UART_UARTCR_LBE_RESET _u(0x0) +#define UART_UARTCR_LBE_BITS _u(0x00000080) +#define UART_UARTCR_LBE_MSB _u(7) +#define UART_UARTCR_LBE_LSB _u(7) +#define UART_UARTCR_LBE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIRLP +// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding +// mode. If this bit is cleared to 0, low-level bits are +// transmitted as an active high pulse with a width of 3 / 16th of +// the bit period. If this bit is set to 1, low-level bits are +// transmitted with a pulse width that is 3 times the period of +// the IrLPBaud16 input signal, regardless of the selected bit +// rate. Setting this bit uses less power, but might reduce +// transmission distances. +#define UART_UARTCR_SIRLP_RESET _u(0x0) +#define UART_UARTCR_SIRLP_BITS _u(0x00000004) +#define UART_UARTCR_SIRLP_MSB _u(2) +#define UART_UARTCR_SIRLP_LSB _u(2) +#define UART_UARTCR_SIRLP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIREN +// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW +// (no light pulse generated), and signal transitions on SIRIN +// have no effect. 1 = IrDA SIR ENDEC is enabled. Data is +// transmitted and received on nSIROUT and SIRIN. UARTTXD remains +// HIGH, in the marking state. Signal transitions on UARTRXD or +// modem status inputs have no effect. This bit has no effect if +// the UARTEN bit disables the UART. +#define UART_UARTCR_SIREN_RESET _u(0x0) +#define UART_UARTCR_SIREN_BITS _u(0x00000002) +#define UART_UARTCR_SIREN_MSB _u(1) +#define UART_UARTCR_SIREN_LSB _u(1) +#define UART_UARTCR_SIREN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_UARTEN +// Description : UART enable: 0 = UART is disabled. If the UART is disabled in +// the middle of transmission or reception, it completes the +// current character before stopping. 1 = the UART is enabled. +// Data transmission and reception occurs for either UART signals +// or SIR signals depending on the setting of the SIREN bit. +#define UART_UARTCR_UARTEN_RESET _u(0x0) +#define UART_UARTCR_UARTEN_BITS _u(0x00000001) +#define UART_UARTCR_UARTEN_MSB _u(0) +#define UART_UARTCR_UARTEN_LSB _u(0) +#define UART_UARTCR_UARTEN_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIFLS +// Description : Interrupt FIFO Level Select Register, UARTIFLS +#define UART_UARTIFLS_OFFSET _u(0x00000034) +#define UART_UARTIFLS_BITS _u(0x0000003f) +#define UART_UARTIFLS_RESET _u(0x00000012) +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_RXIFLSEL +// Description : Receive interrupt FIFO level select. The trigger points for the +// receive interrupt are as follows: b000 = Receive FIFO becomes +// >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = +// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes +// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full +// b101-b111 = reserved. +#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038) +#define UART_UARTIFLS_RXIFLSEL_MSB _u(5) +#define UART_UARTIFLS_RXIFLSEL_LSB _u(3) +#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_TXIFLSEL +// Description : Transmit interrupt FIFO level select. The trigger points for +// the transmit interrupt are as follows: b000 = Transmit FIFO +// becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 +// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit +// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / +// 8 full b101-b111 = reserved. +#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007) +#define UART_UARTIFLS_TXIFLSEL_MSB _u(2) +#define UART_UARTIFLS_TXIFLSEL_LSB _u(0) +#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIMSC +// Description : Interrupt Mask Set/Clear Register, UARTIMSC +#define UART_UARTIMSC_OFFSET _u(0x00000038) +#define UART_UARTIMSC_BITS _u(0x000007ff) +#define UART_UARTIMSC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_OEIM +// Description : Overrun error interrupt mask. A read returns the current mask +// for the UARTOEINTR interrupt. On a write of 1, the mask of the +// UARTOEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_OEIM_RESET _u(0x0) +#define UART_UARTIMSC_OEIM_BITS _u(0x00000400) +#define UART_UARTIMSC_OEIM_MSB _u(10) +#define UART_UARTIMSC_OEIM_LSB _u(10) +#define UART_UARTIMSC_OEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_BEIM +// Description : Break error interrupt mask. A read returns the current mask for +// the UARTBEINTR interrupt. On a write of 1, the mask of the +// UARTBEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_BEIM_RESET _u(0x0) +#define UART_UARTIMSC_BEIM_BITS _u(0x00000200) +#define UART_UARTIMSC_BEIM_MSB _u(9) +#define UART_UARTIMSC_BEIM_LSB _u(9) +#define UART_UARTIMSC_BEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_PEIM +// Description : Parity error interrupt mask. A read returns the current mask +// for the UARTPEINTR interrupt. On a write of 1, the mask of the +// UARTPEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_PEIM_RESET _u(0x0) +#define UART_UARTIMSC_PEIM_BITS _u(0x00000100) +#define UART_UARTIMSC_PEIM_MSB _u(8) +#define UART_UARTIMSC_PEIM_LSB _u(8) +#define UART_UARTIMSC_PEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_FEIM +// Description : Framing error interrupt mask. A read returns the current mask +// for the UARTFEINTR interrupt. On a write of 1, the mask of the +// UARTFEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_FEIM_RESET _u(0x0) +#define UART_UARTIMSC_FEIM_BITS _u(0x00000080) +#define UART_UARTIMSC_FEIM_MSB _u(7) +#define UART_UARTIMSC_FEIM_LSB _u(7) +#define UART_UARTIMSC_FEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RTIM +// Description : Receive timeout interrupt mask. A read returns the current mask +// for the UARTRTINTR interrupt. On a write of 1, the mask of the +// UARTRTINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RTIM_RESET _u(0x0) +#define UART_UARTIMSC_RTIM_BITS _u(0x00000040) +#define UART_UARTIMSC_RTIM_MSB _u(6) +#define UART_UARTIMSC_RTIM_LSB _u(6) +#define UART_UARTIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_TXIM +// Description : Transmit interrupt mask. A read returns the current mask for +// the UARTTXINTR interrupt. On a write of 1, the mask of the +// UARTTXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_TXIM_RESET _u(0x0) +#define UART_UARTIMSC_TXIM_BITS _u(0x00000020) +#define UART_UARTIMSC_TXIM_MSB _u(5) +#define UART_UARTIMSC_TXIM_LSB _u(5) +#define UART_UARTIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RXIM +// Description : Receive interrupt mask. A read returns the current mask for the +// UARTRXINTR interrupt. On a write of 1, the mask of the +// UARTRXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RXIM_RESET _u(0x0) +#define UART_UARTIMSC_RXIM_BITS _u(0x00000010) +#define UART_UARTIMSC_RXIM_MSB _u(4) +#define UART_UARTIMSC_RXIM_LSB _u(4) +#define UART_UARTIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DSRMIM +// Description : nUARTDSR modem interrupt mask. A read returns the current mask +// for the UARTDSRINTR interrupt. On a write of 1, the mask of the +// UARTDSRINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DSRMIM_RESET _u(0x0) +#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008) +#define UART_UARTIMSC_DSRMIM_MSB _u(3) +#define UART_UARTIMSC_DSRMIM_LSB _u(3) +#define UART_UARTIMSC_DSRMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DCDMIM +// Description : nUARTDCD modem interrupt mask. A read returns the current mask +// for the UARTDCDINTR interrupt. On a write of 1, the mask of the +// UARTDCDINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DCDMIM_RESET _u(0x0) +#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004) +#define UART_UARTIMSC_DCDMIM_MSB _u(2) +#define UART_UARTIMSC_DCDMIM_LSB _u(2) +#define UART_UARTIMSC_DCDMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_CTSMIM +// Description : nUARTCTS modem interrupt mask. A read returns the current mask +// for the UARTCTSINTR interrupt. On a write of 1, the mask of the +// UARTCTSINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_CTSMIM_RESET _u(0x0) +#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002) +#define UART_UARTIMSC_CTSMIM_MSB _u(1) +#define UART_UARTIMSC_CTSMIM_LSB _u(1) +#define UART_UARTIMSC_CTSMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RIMIM +// Description : nUARTRI modem interrupt mask. A read returns the current mask +// for the UARTRIINTR interrupt. On a write of 1, the mask of the +// UARTRIINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RIMIM_RESET _u(0x0) +#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001) +#define UART_UARTIMSC_RIMIM_MSB _u(0) +#define UART_UARTIMSC_RIMIM_LSB _u(0) +#define UART_UARTIMSC_RIMIM_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTRIS +// Description : Raw Interrupt Status Register, UARTRIS +#define UART_UARTRIS_OFFSET _u(0x0000003c) +#define UART_UARTRIS_BITS _u(0x000007ff) +#define UART_UARTRIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_OERIS +// Description : Overrun error interrupt status. Returns the raw interrupt state +// of the UARTOEINTR interrupt. +#define UART_UARTRIS_OERIS_RESET _u(0x0) +#define UART_UARTRIS_OERIS_BITS _u(0x00000400) +#define UART_UARTRIS_OERIS_MSB _u(10) +#define UART_UARTRIS_OERIS_LSB _u(10) +#define UART_UARTRIS_OERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_BERIS +// Description : Break error interrupt status. Returns the raw interrupt state +// of the UARTBEINTR interrupt. +#define UART_UARTRIS_BERIS_RESET _u(0x0) +#define UART_UARTRIS_BERIS_BITS _u(0x00000200) +#define UART_UARTRIS_BERIS_MSB _u(9) +#define UART_UARTRIS_BERIS_LSB _u(9) +#define UART_UARTRIS_BERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_PERIS +// Description : Parity error interrupt status. Returns the raw interrupt state +// of the UARTPEINTR interrupt. +#define UART_UARTRIS_PERIS_RESET _u(0x0) +#define UART_UARTRIS_PERIS_BITS _u(0x00000100) +#define UART_UARTRIS_PERIS_MSB _u(8) +#define UART_UARTRIS_PERIS_LSB _u(8) +#define UART_UARTRIS_PERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_FERIS +// Description : Framing error interrupt status. Returns the raw interrupt state +// of the UARTFEINTR interrupt. +#define UART_UARTRIS_FERIS_RESET _u(0x0) +#define UART_UARTRIS_FERIS_BITS _u(0x00000080) +#define UART_UARTRIS_FERIS_MSB _u(7) +#define UART_UARTRIS_FERIS_LSB _u(7) +#define UART_UARTRIS_FERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RTRIS +// Description : Receive timeout interrupt status. Returns the raw interrupt +// state of the UARTRTINTR interrupt. a +#define UART_UARTRIS_RTRIS_RESET _u(0x0) +#define UART_UARTRIS_RTRIS_BITS _u(0x00000040) +#define UART_UARTRIS_RTRIS_MSB _u(6) +#define UART_UARTRIS_RTRIS_LSB _u(6) +#define UART_UARTRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_TXRIS +// Description : Transmit interrupt status. Returns the raw interrupt state of +// the UARTTXINTR interrupt. +#define UART_UARTRIS_TXRIS_RESET _u(0x0) +#define UART_UARTRIS_TXRIS_BITS _u(0x00000020) +#define UART_UARTRIS_TXRIS_MSB _u(5) +#define UART_UARTRIS_TXRIS_LSB _u(5) +#define UART_UARTRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RXRIS +// Description : Receive interrupt status. Returns the raw interrupt state of +// the UARTRXINTR interrupt. +#define UART_UARTRIS_RXRIS_RESET _u(0x0) +#define UART_UARTRIS_RXRIS_BITS _u(0x00000010) +#define UART_UARTRIS_RXRIS_MSB _u(4) +#define UART_UARTRIS_RXRIS_LSB _u(4) +#define UART_UARTRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DSRRMIS +// Description : nUARTDSR modem interrupt status. Returns the raw interrupt +// state of the UARTDSRINTR interrupt. +#define UART_UARTRIS_DSRRMIS_RESET "-" +#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008) +#define UART_UARTRIS_DSRRMIS_MSB _u(3) +#define UART_UARTRIS_DSRRMIS_LSB _u(3) +#define UART_UARTRIS_DSRRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DCDRMIS +// Description : nUARTDCD modem interrupt status. Returns the raw interrupt +// state of the UARTDCDINTR interrupt. +#define UART_UARTRIS_DCDRMIS_RESET "-" +#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004) +#define UART_UARTRIS_DCDRMIS_MSB _u(2) +#define UART_UARTRIS_DCDRMIS_LSB _u(2) +#define UART_UARTRIS_DCDRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_CTSRMIS +// Description : nUARTCTS modem interrupt status. Returns the raw interrupt +// state of the UARTCTSINTR interrupt. +#define UART_UARTRIS_CTSRMIS_RESET "-" +#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002) +#define UART_UARTRIS_CTSRMIS_MSB _u(1) +#define UART_UARTRIS_CTSRMIS_LSB _u(1) +#define UART_UARTRIS_CTSRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RIRMIS +// Description : nUARTRI modem interrupt status. Returns the raw interrupt state +// of the UARTRIINTR interrupt. +#define UART_UARTRIS_RIRMIS_RESET "-" +#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001) +#define UART_UARTRIS_RIRMIS_MSB _u(0) +#define UART_UARTRIS_RIRMIS_LSB _u(0) +#define UART_UARTRIS_RIRMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTMIS +// Description : Masked Interrupt Status Register, UARTMIS +#define UART_UARTMIS_OFFSET _u(0x00000040) +#define UART_UARTMIS_BITS _u(0x000007ff) +#define UART_UARTMIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_OEMIS +// Description : Overrun error masked interrupt status. Returns the masked +// interrupt state of the UARTOEINTR interrupt. +#define UART_UARTMIS_OEMIS_RESET _u(0x0) +#define UART_UARTMIS_OEMIS_BITS _u(0x00000400) +#define UART_UARTMIS_OEMIS_MSB _u(10) +#define UART_UARTMIS_OEMIS_LSB _u(10) +#define UART_UARTMIS_OEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_BEMIS +// Description : Break error masked interrupt status. Returns the masked +// interrupt state of the UARTBEINTR interrupt. +#define UART_UARTMIS_BEMIS_RESET _u(0x0) +#define UART_UARTMIS_BEMIS_BITS _u(0x00000200) +#define UART_UARTMIS_BEMIS_MSB _u(9) +#define UART_UARTMIS_BEMIS_LSB _u(9) +#define UART_UARTMIS_BEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_PEMIS +// Description : Parity error masked interrupt status. Returns the masked +// interrupt state of the UARTPEINTR interrupt. +#define UART_UARTMIS_PEMIS_RESET _u(0x0) +#define UART_UARTMIS_PEMIS_BITS _u(0x00000100) +#define UART_UARTMIS_PEMIS_MSB _u(8) +#define UART_UARTMIS_PEMIS_LSB _u(8) +#define UART_UARTMIS_PEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_FEMIS +// Description : Framing error masked interrupt status. Returns the masked +// interrupt state of the UARTFEINTR interrupt. +#define UART_UARTMIS_FEMIS_RESET _u(0x0) +#define UART_UARTMIS_FEMIS_BITS _u(0x00000080) +#define UART_UARTMIS_FEMIS_MSB _u(7) +#define UART_UARTMIS_FEMIS_LSB _u(7) +#define UART_UARTMIS_FEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RTMIS +// Description : Receive timeout masked interrupt status. Returns the masked +// interrupt state of the UARTRTINTR interrupt. +#define UART_UARTMIS_RTMIS_RESET _u(0x0) +#define UART_UARTMIS_RTMIS_BITS _u(0x00000040) +#define UART_UARTMIS_RTMIS_MSB _u(6) +#define UART_UARTMIS_RTMIS_LSB _u(6) +#define UART_UARTMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_TXMIS +// Description : Transmit masked interrupt status. Returns the masked interrupt +// state of the UARTTXINTR interrupt. +#define UART_UARTMIS_TXMIS_RESET _u(0x0) +#define UART_UARTMIS_TXMIS_BITS _u(0x00000020) +#define UART_UARTMIS_TXMIS_MSB _u(5) +#define UART_UARTMIS_TXMIS_LSB _u(5) +#define UART_UARTMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RXMIS +// Description : Receive masked interrupt status. Returns the masked interrupt +// state of the UARTRXINTR interrupt. +#define UART_UARTMIS_RXMIS_RESET _u(0x0) +#define UART_UARTMIS_RXMIS_BITS _u(0x00000010) +#define UART_UARTMIS_RXMIS_MSB _u(4) +#define UART_UARTMIS_RXMIS_LSB _u(4) +#define UART_UARTMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DSRMMIS +// Description : nUARTDSR modem masked interrupt status. Returns the masked +// interrupt state of the UARTDSRINTR interrupt. +#define UART_UARTMIS_DSRMMIS_RESET "-" +#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008) +#define UART_UARTMIS_DSRMMIS_MSB _u(3) +#define UART_UARTMIS_DSRMMIS_LSB _u(3) +#define UART_UARTMIS_DSRMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DCDMMIS +// Description : nUARTDCD modem masked interrupt status. Returns the masked +// interrupt state of the UARTDCDINTR interrupt. +#define UART_UARTMIS_DCDMMIS_RESET "-" +#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004) +#define UART_UARTMIS_DCDMMIS_MSB _u(2) +#define UART_UARTMIS_DCDMMIS_LSB _u(2) +#define UART_UARTMIS_DCDMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_CTSMMIS +// Description : nUARTCTS modem masked interrupt status. Returns the masked +// interrupt state of the UARTCTSINTR interrupt. +#define UART_UARTMIS_CTSMMIS_RESET "-" +#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002) +#define UART_UARTMIS_CTSMMIS_MSB _u(1) +#define UART_UARTMIS_CTSMMIS_LSB _u(1) +#define UART_UARTMIS_CTSMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RIMMIS +// Description : nUARTRI modem masked interrupt status. Returns the masked +// interrupt state of the UARTRIINTR interrupt. +#define UART_UARTMIS_RIMMIS_RESET "-" +#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001) +#define UART_UARTMIS_RIMMIS_MSB _u(0) +#define UART_UARTMIS_RIMMIS_LSB _u(0) +#define UART_UARTMIS_RIMMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTICR +// Description : Interrupt Clear Register, UARTICR +#define UART_UARTICR_OFFSET _u(0x00000044) +#define UART_UARTICR_BITS _u(0x000007ff) +#define UART_UARTICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_OEIC +// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. +#define UART_UARTICR_OEIC_RESET "-" +#define UART_UARTICR_OEIC_BITS _u(0x00000400) +#define UART_UARTICR_OEIC_MSB _u(10) +#define UART_UARTICR_OEIC_LSB _u(10) +#define UART_UARTICR_OEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_BEIC +// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. +#define UART_UARTICR_BEIC_RESET "-" +#define UART_UARTICR_BEIC_BITS _u(0x00000200) +#define UART_UARTICR_BEIC_MSB _u(9) +#define UART_UARTICR_BEIC_LSB _u(9) +#define UART_UARTICR_BEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_PEIC +// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. +#define UART_UARTICR_PEIC_RESET "-" +#define UART_UARTICR_PEIC_BITS _u(0x00000100) +#define UART_UARTICR_PEIC_MSB _u(8) +#define UART_UARTICR_PEIC_LSB _u(8) +#define UART_UARTICR_PEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_FEIC +// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. +#define UART_UARTICR_FEIC_RESET "-" +#define UART_UARTICR_FEIC_BITS _u(0x00000080) +#define UART_UARTICR_FEIC_MSB _u(7) +#define UART_UARTICR_FEIC_LSB _u(7) +#define UART_UARTICR_FEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RTIC +// Description : Receive timeout interrupt clear. Clears the UARTRTINTR +// interrupt. +#define UART_UARTICR_RTIC_RESET "-" +#define UART_UARTICR_RTIC_BITS _u(0x00000040) +#define UART_UARTICR_RTIC_MSB _u(6) +#define UART_UARTICR_RTIC_LSB _u(6) +#define UART_UARTICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_TXIC +// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. +#define UART_UARTICR_TXIC_RESET "-" +#define UART_UARTICR_TXIC_BITS _u(0x00000020) +#define UART_UARTICR_TXIC_MSB _u(5) +#define UART_UARTICR_TXIC_LSB _u(5) +#define UART_UARTICR_TXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RXIC +// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. +#define UART_UARTICR_RXIC_RESET "-" +#define UART_UARTICR_RXIC_BITS _u(0x00000010) +#define UART_UARTICR_RXIC_MSB _u(4) +#define UART_UARTICR_RXIC_LSB _u(4) +#define UART_UARTICR_RXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DSRMIC +// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR +// interrupt. +#define UART_UARTICR_DSRMIC_RESET "-" +#define UART_UARTICR_DSRMIC_BITS _u(0x00000008) +#define UART_UARTICR_DSRMIC_MSB _u(3) +#define UART_UARTICR_DSRMIC_LSB _u(3) +#define UART_UARTICR_DSRMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DCDMIC +// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR +// interrupt. +#define UART_UARTICR_DCDMIC_RESET "-" +#define UART_UARTICR_DCDMIC_BITS _u(0x00000004) +#define UART_UARTICR_DCDMIC_MSB _u(2) +#define UART_UARTICR_DCDMIC_LSB _u(2) +#define UART_UARTICR_DCDMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_CTSMIC +// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR +// interrupt. +#define UART_UARTICR_CTSMIC_RESET "-" +#define UART_UARTICR_CTSMIC_BITS _u(0x00000002) +#define UART_UARTICR_CTSMIC_MSB _u(1) +#define UART_UARTICR_CTSMIC_LSB _u(1) +#define UART_UARTICR_CTSMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RIMIC +// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. +#define UART_UARTICR_RIMIC_RESET "-" +#define UART_UARTICR_RIMIC_BITS _u(0x00000001) +#define UART_UARTICR_RIMIC_MSB _u(0) +#define UART_UARTICR_RIMIC_LSB _u(0) +#define UART_UARTICR_RIMIC_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTDMACR +// Description : DMA Control Register, UARTDMACR +#define UART_UARTDMACR_OFFSET _u(0x00000048) +#define UART_UARTDMACR_BITS _u(0x00000007) +#define UART_UARTDMACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_DMAONERR +// Description : DMA on error. If this bit is set to 1, the DMA receive request +// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the +// UART error interrupt is asserted. +#define UART_UARTDMACR_DMAONERR_RESET _u(0x0) +#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004) +#define UART_UARTDMACR_DMAONERR_MSB _u(2) +#define UART_UARTDMACR_DMAONERR_LSB _u(2) +#define UART_UARTDMACR_DMAONERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_TXDMAE +// Description : Transmit DMA enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define UART_UARTDMACR_TXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002) +#define UART_UARTDMACR_TXDMAE_MSB _u(1) +#define UART_UARTDMACR_TXDMAE_LSB _u(1) +#define UART_UARTDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_RXDMAE +// Description : Receive DMA enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define UART_UARTDMACR_RXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001) +#define UART_UARTDMACR_RXDMAE_MSB _u(0) +#define UART_UARTDMACR_RXDMAE_LSB _u(0) +#define UART_UARTDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTPERIPHID0 +// Description : UARTPeriphID0 Register +#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0) +#define UART_UARTPERIPHID0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_RESET _u(0x00000011) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x11 +#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11) +#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7) +#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0) +#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID1 +// Description : UARTPeriphID1 Register +#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4) +#define UART_UARTPERIPHID1_BITS _u(0x000000ff) +#define UART_UARTPERIPHID1_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1) +#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7) +#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4) +#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3) +#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0) +#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID2 +// Description : UARTPeriphID2 Register +#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8) +#define UART_UARTPERIPHID2_BITS _u(0x000000ff) +#define UART_UARTPERIPHID2_RESET _u(0x00000034) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_REVISION +// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 +// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 +#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3) +#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0) +#define UART_UARTPERIPHID2_REVISION_MSB _u(7) +#define UART_UARTPERIPHID2_REVISION_LSB _u(4) +#define UART_UARTPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4) +#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3) +#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0) +#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID3 +// Description : UARTPeriphID3 Register +#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec) +#define UART_UARTPERIPHID3_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7) +#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0) +#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID0 +// Description : UARTPCellID0 Register +#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0) +#define UART_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID0_UARTPCELLID0 +// Description : These bits read back as 0x0D +#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d) +#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7) +#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0) +#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID1 +// Description : UARTPCellID1 Register +#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4) +#define UART_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_RESET _u(0x000000f0) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID1_UARTPCELLID1 +// Description : These bits read back as 0xF0 +#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0) +#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7) +#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0) +#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID2 +// Description : UARTPCellID2 Register +#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8) +#define UART_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID2_UARTPCELLID2 +// Description : These bits read back as 0x05 +#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05) +#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7) +#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0) +#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID3 +// Description : UARTPCellID3 Register +#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc) +#define UART_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID3_UARTPCELLID3 +// Description : These bits read back as 0xB1 +#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1) +#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7) +#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) +#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_UART_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/usb.h b/src/rp2350/hardware_regs/include/hardware/regs/usb.h new file mode 100644 index 000000000..fbf1b7b36 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/usb.h @@ -0,0 +1,4209 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB +// Version : 1 +// Bus type : ahbl +// Description : USB FS/LS controller device registers +// ============================================================================= +#ifndef _HARDWARE_REGS_USB_H +#define _HARDWARE_REGS_USB_H +// ============================================================================= +// Register : USB_ADDR_ENDP +// Description : Device address and endpoint control +#define USB_ADDR_ENDP_OFFSET _u(0x00000000) +#define USB_ADDR_ENDP_BITS _u(0x000f007f) +#define USB_ADDR_ENDP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ENDPOINT +// Description : Device endpoint to send data to. Only valid for HOST mode. +#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ADDRESS +// Description : In device mode, the address that the device should respond to. +// Set in response to a SET_ADDR setup packet from the host. In +// host mode set to the address of the device to communicate with. +#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP1 +// Description : Interrupt endpoint 1. Only valid for HOST mode. +#define USB_ADDR_ENDP1_OFFSET _u(0x00000004) +#define USB_ADDR_ENDP1_BITS _u(0x060f007f) +#define USB_ADDR_ENDP1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP2 +// Description : Interrupt endpoint 2. Only valid for HOST mode. +#define USB_ADDR_ENDP2_OFFSET _u(0x00000008) +#define USB_ADDR_ENDP2_BITS _u(0x060f007f) +#define USB_ADDR_ENDP2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP3 +// Description : Interrupt endpoint 3. Only valid for HOST mode. +#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c) +#define USB_ADDR_ENDP3_BITS _u(0x060f007f) +#define USB_ADDR_ENDP3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP4 +// Description : Interrupt endpoint 4. Only valid for HOST mode. +#define USB_ADDR_ENDP4_OFFSET _u(0x00000010) +#define USB_ADDR_ENDP4_BITS _u(0x060f007f) +#define USB_ADDR_ENDP4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP5 +// Description : Interrupt endpoint 5. Only valid for HOST mode. +#define USB_ADDR_ENDP5_OFFSET _u(0x00000014) +#define USB_ADDR_ENDP5_BITS _u(0x060f007f) +#define USB_ADDR_ENDP5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP6 +// Description : Interrupt endpoint 6. Only valid for HOST mode. +#define USB_ADDR_ENDP6_OFFSET _u(0x00000018) +#define USB_ADDR_ENDP6_BITS _u(0x060f007f) +#define USB_ADDR_ENDP6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP7 +// Description : Interrupt endpoint 7. Only valid for HOST mode. +#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c) +#define USB_ADDR_ENDP7_BITS _u(0x060f007f) +#define USB_ADDR_ENDP7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP8 +// Description : Interrupt endpoint 8. Only valid for HOST mode. +#define USB_ADDR_ENDP8_OFFSET _u(0x00000020) +#define USB_ADDR_ENDP8_BITS _u(0x060f007f) +#define USB_ADDR_ENDP8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP9 +// Description : Interrupt endpoint 9. Only valid for HOST mode. +#define USB_ADDR_ENDP9_OFFSET _u(0x00000024) +#define USB_ADDR_ENDP9_BITS _u(0x060f007f) +#define USB_ADDR_ENDP9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP10 +// Description : Interrupt endpoint 10. Only valid for HOST mode. +#define USB_ADDR_ENDP10_OFFSET _u(0x00000028) +#define USB_ADDR_ENDP10_BITS _u(0x060f007f) +#define USB_ADDR_ENDP10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP11 +// Description : Interrupt endpoint 11. Only valid for HOST mode. +#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c) +#define USB_ADDR_ENDP11_BITS _u(0x060f007f) +#define USB_ADDR_ENDP11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP12 +// Description : Interrupt endpoint 12. Only valid for HOST mode. +#define USB_ADDR_ENDP12_OFFSET _u(0x00000030) +#define USB_ADDR_ENDP12_BITS _u(0x060f007f) +#define USB_ADDR_ENDP12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP13 +// Description : Interrupt endpoint 13. Only valid for HOST mode. +#define USB_ADDR_ENDP13_OFFSET _u(0x00000034) +#define USB_ADDR_ENDP13_BITS _u(0x060f007f) +#define USB_ADDR_ENDP13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP14 +// Description : Interrupt endpoint 14. Only valid for HOST mode. +#define USB_ADDR_ENDP14_OFFSET _u(0x00000038) +#define USB_ADDR_ENDP14_BITS _u(0x060f007f) +#define USB_ADDR_ENDP14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP15 +// Description : Interrupt endpoint 15. Only valid for HOST mode. +#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c) +#define USB_ADDR_ENDP15_BITS _u(0x060f007f) +#define USB_ADDR_ENDP15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_MAIN_CTRL +// Description : Main control register +#define USB_MAIN_CTRL_OFFSET _u(0x00000040) +#define USB_MAIN_CTRL_BITS _u(0x80000007) +#define USB_MAIN_CTRL_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_SIM_TIMING +// Description : Reduced timings for simulation +#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0) +#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000) +#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31) +#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31) +#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_PHY_ISO +// Description : Isolates USB phy after controller power-up +// Remove isolation once software has configured the controller +// Not isolated = 0, Isolated = 1 +#define USB_MAIN_CTRL_PHY_ISO_RESET _u(0x1) +#define USB_MAIN_CTRL_PHY_ISO_BITS _u(0x00000004) +#define USB_MAIN_CTRL_PHY_ISO_MSB _u(2) +#define USB_MAIN_CTRL_PHY_ISO_LSB _u(2) +#define USB_MAIN_CTRL_PHY_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_HOST_NDEVICE +// Description : Device mode = 0, Host mode = 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0) +#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002) +#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1) +#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1) +#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_CONTROLLER_EN +// Description : Enable controller +#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0) +#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001) +#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0) +#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0) +#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_SOF_WR +// Description : Set the SOF (Start of Frame) frame number in the host +// controller. The SOF packet is sent every 1ms and the host will +// increment the frame number by 1 each time. +#define USB_SOF_WR_OFFSET _u(0x00000044) +#define USB_SOF_WR_BITS _u(0x000007ff) +#define USB_SOF_WR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SOF_WR_COUNT +#define USB_SOF_WR_COUNT_RESET _u(0x000) +#define USB_SOF_WR_COUNT_BITS _u(0x000007ff) +#define USB_SOF_WR_COUNT_MSB _u(10) +#define USB_SOF_WR_COUNT_LSB _u(0) +#define USB_SOF_WR_COUNT_ACCESS "WF" +// ============================================================================= +// Register : USB_SOF_RD +// Description : Read the last SOF (Start of Frame) frame number seen. In device +// mode the last SOF received from the host. In host mode the last +// SOF sent by the host. +#define USB_SOF_RD_OFFSET _u(0x00000048) +#define USB_SOF_RD_BITS _u(0x000007ff) +#define USB_SOF_RD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SOF_RD_COUNT +#define USB_SOF_RD_COUNT_RESET _u(0x000) +#define USB_SOF_RD_COUNT_BITS _u(0x000007ff) +#define USB_SOF_RD_COUNT_MSB _u(10) +#define USB_SOF_RD_COUNT_LSB _u(0) +#define USB_SOF_RD_COUNT_ACCESS "RO" +// ============================================================================= +// Register : USB_SIE_CTRL +// Description : SIE control register +#define USB_SIE_CTRL_OFFSET _u(0x0000004c) +#define USB_SIE_CTRL_BITS _u(0xff0fbf5f) +#define USB_SIE_CTRL_RESET _u(0x00008000) +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_STALL +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL +#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000) +#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31) +#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31) +#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF +// Description : Device: EP0 single buffered = 0, double buffered = 1 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_1BUF +// Description : Device: Set bit in BUFF_STATUS for every buffer completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000) +#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29) +#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29) +#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_2BUF +// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000) +#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28) +#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28) +#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_NAK +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK +#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000) +#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27) +#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27) +#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_EN +// Description : Direct bus drive enable +#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000) +#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26) +#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26) +#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DP +// Description : Direct control of DP +#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000) +#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25) +#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25) +#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DM +// Description : Direct control of DM +#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000) +#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24) +#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24) +#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET +// Description : Device: Stop EP0 on a short packet. +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_BITS _u(0x00080000) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_MSB _u(19) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_LSB _u(19) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_TRANSCEIVER_PD +// Description : Power down bus transceiver +#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0) +#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000) +#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18) +#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18) +#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RPU_OPT +// Description : Device: Pull-up strength (0=1K2, 1=2k3) +#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0) +#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000) +#define USB_SIE_CTRL_RPU_OPT_MSB _u(17) +#define USB_SIE_CTRL_RPU_OPT_LSB _u(17) +#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLUP_EN +// Description : Device: Enable pull up resistor +#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000) +#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16) +#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16) +#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLDOWN_EN +// Description : Host: Enable pull down resistors +#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x1) +#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000) +#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15) +#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15) +#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESET_BUS +// Description : Host: Reset bus +#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0) +#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000) +#define USB_SIE_CTRL_RESET_BUS_MSB _u(13) +#define USB_SIE_CTRL_RESET_BUS_LSB _u(13) +#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESUME +// Description : Device: Remote wakeup. Device can initiate its own resume after +// suspend. +#define USB_SIE_CTRL_RESUME_RESET _u(0x0) +#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000) +#define USB_SIE_CTRL_RESUME_MSB _u(12) +#define USB_SIE_CTRL_RESUME_LSB _u(12) +#define USB_SIE_CTRL_RESUME_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_VBUS_EN +// Description : Host: Enable VBUS +#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0) +#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800) +#define USB_SIE_CTRL_VBUS_EN_MSB _u(11) +#define USB_SIE_CTRL_VBUS_EN_LSB _u(11) +#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_KEEP_ALIVE_EN +// Description : Host: Enable keep alive packet (for low speed bus) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_EN +// Description : Host: Enable SOF generation (for full speed bus) +#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200) +#define USB_SIE_CTRL_SOF_EN_MSB _u(9) +#define USB_SIE_CTRL_SOF_EN_LSB _u(9) +#define USB_SIE_CTRL_SOF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_SYNC +// Description : Host: Delay packet(s) until after SOF +#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100) +#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8) +#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8) +#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PREAMBLE_EN +// Description : Host: Preable enable for LS device on FS hub +#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040) +#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6) +#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6) +#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_STOP_TRANS +// Description : Host: Stop transaction +#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010) +#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4) +#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4) +#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RECEIVE_DATA +// Description : Host: Receive transaction (IN to host) +#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008) +#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3) +#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3) +#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_DATA +// Description : Host: Send transaction (OUT from host) +#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004) +#define USB_SIE_CTRL_SEND_DATA_MSB _u(2) +#define USB_SIE_CTRL_SEND_DATA_LSB _u(2) +#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_SETUP +// Description : Host: Send Setup packet +#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002) +#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1) +#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1) +#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_START_TRANS +// Description : Host: Start transaction +#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001) +#define USB_SIE_CTRL_START_TRANS_MSB _u(0) +#define USB_SIE_CTRL_START_TRANS_LSB _u(0) +#define USB_SIE_CTRL_START_TRANS_ACCESS "SC" +// ============================================================================= +// Register : USB_SIE_STATUS +// Description : SIE status register +#define USB_SIE_STATUS_OFFSET _u(0x00000050) +#define USB_SIE_STATUS_BITS _u(0xff8f1f1d) +#define USB_SIE_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_DATA_SEQ_ERROR +// Description : Data Sequence Error. +// +// The device can raise a sequence error in the following +// conditions: +// +// * A SETUP packet is received followed by a DATA1 packet (data +// phase should always be DATA0) * An OUT packet is received from +// the host but doesn't match the data pid in the buffer control +// register read from DPSRAM +// +// The host can raise a data sequence error in the following +// conditions: +// +// * An IN packet from the device has the wrong data PID +#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_ACK_REC +// Description : ACK received. Raised by both host and device. +#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000) +#define USB_SIE_STATUS_ACK_REC_MSB _u(30) +#define USB_SIE_STATUS_ACK_REC_LSB _u(30) +#define USB_SIE_STATUS_ACK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_STALL_REC +// Description : Host: STALL received +#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0) +#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000) +#define USB_SIE_STATUS_STALL_REC_MSB _u(29) +#define USB_SIE_STATUS_STALL_REC_LSB _u(29) +#define USB_SIE_STATUS_STALL_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_NAK_REC +// Description : Host: NAK received +#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000) +#define USB_SIE_STATUS_NAK_REC_MSB _u(28) +#define USB_SIE_STATUS_NAK_REC_LSB _u(28) +#define USB_SIE_STATUS_NAK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_TIMEOUT +// Description : RX timeout is raised by both the host and device if an ACK is +// not received in the maximum time specified by the USB spec. +#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0) +#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000) +#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27) +#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27) +#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_OVERFLOW +// Description : RX overflow is raised by the Serial RX engine if the incoming +// data is too fast. +#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0) +#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000) +#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26) +#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26) +#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BIT_STUFF_ERROR +// Description : Bit Stuff Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CRC_ERROR +// Description : CRC Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000) +#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24) +#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24) +#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_ENDPOINT_ERROR +// Description : An endpoint has encountered an error. Read the ep_rx_error and +// ep_tx_error registers to find out which endpoint had an error. +#define USB_SIE_STATUS_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_ENDPOINT_ERROR_BITS _u(0x00800000) +#define USB_SIE_STATUS_ENDPOINT_ERROR_MSB _u(23) +#define USB_SIE_STATUS_ENDPOINT_ERROR_LSB _u(23) +#define USB_SIE_STATUS_ENDPOINT_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BUS_RESET +// Description : Device: bus reset received +#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0) +#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000) +#define USB_SIE_STATUS_BUS_RESET_MSB _u(19) +#define USB_SIE_STATUS_BUS_RESET_LSB _u(19) +#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_TRANS_COMPLETE +// Description : Transaction complete. +// +// Raised by device if: +// +// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in +// the buffer control register +// +// Raised by host if: +// +// * A setup packet is sent when no data in or data out +// transaction follows * An IN packet is received and the +// `LAST_BUFF` bit is set in the buffer control register * An IN +// packet is received with zero length * An OUT packet is sent and +// the `LAST_BUFF` bit is set +#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000) +#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18) +#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18) +#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SETUP_REC +// Description : Device: Setup packet received +#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0) +#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000) +#define USB_SIE_STATUS_SETUP_REC_MSB _u(17) +#define USB_SIE_STATUS_SETUP_REC_LSB _u(17) +#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CONNECTED +// Description : Device: connected +#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0) +#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) +#define USB_SIE_STATUS_CONNECTED_MSB _u(16) +#define USB_SIE_STATUS_CONNECTED_LSB _u(16) +#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_SHORT_PACKET +// Description : Device or Host has received a short packet. This is when the +// data received is less than configured in the buffer control +// register. Device: If using double buffered mode on device the +// buffer select will not be toggled after writing status back to +// the buffer control register. This is to prevent any further +// transactions on that endpoint until the user has reset the +// buffer control registers. Host: the current transfer will be +// stopped early. +#define USB_SIE_STATUS_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_SIE_STATUS_RX_SHORT_PACKET_BITS _u(0x00001000) +#define USB_SIE_STATUS_RX_SHORT_PACKET_MSB _u(12) +#define USB_SIE_STATUS_RX_SHORT_PACKET_LSB _u(12) +#define USB_SIE_STATUS_RX_SHORT_PACKET_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RESUME +// Description : Host: Device has initiated a remote resume. Device: host has +// initiated a resume. +#define USB_SIE_STATUS_RESUME_RESET _u(0x0) +#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800) +#define USB_SIE_STATUS_RESUME_MSB _u(11) +#define USB_SIE_STATUS_RESUME_LSB _u(11) +#define USB_SIE_STATUS_RESUME_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_OVER_CURR +// Description : VBUS over current detected +#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400) +#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10) +#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10) +#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SPEED +// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 +#define USB_SIE_STATUS_SPEED_RESET _u(0x0) +#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) +#define USB_SIE_STATUS_SPEED_MSB _u(9) +#define USB_SIE_STATUS_SPEED_LSB _u(8) +#define USB_SIE_STATUS_SPEED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SUSPENDED +// Description : Bus in suspended state. Valid for device. Device will go into +// suspend if neither Keep Alive / SOF frames are enabled. +#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0) +#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) +#define USB_SIE_STATUS_SUSPENDED_MSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_LSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_LINE_STATE +// Description : USB bus line state +#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0) +#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c) +#define USB_SIE_STATUS_LINE_STATE_MSB _u(3) +#define USB_SIE_STATUS_LINE_STATE_LSB _u(2) +#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_DETECTED +// Description : Device: VBUS Detected +#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001) +#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0) +#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0) +#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" +// ============================================================================= +// Register : USB_INT_EP_CTRL +// Description : interrupt endpoint control register +#define USB_INT_EP_CTRL_OFFSET _u(0x00000054) +#define USB_INT_EP_CTRL_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE +// Description : Host: Enable interrupt endpoint 1 -> 15 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : USB_BUFF_STATUS +// Description : Buffer status register. A bit set here indicates that a buffer +// has completed on the endpoint (if the buffer interrupt is +// enabled). It is possible for 2 buffers to be completed, so +// clearing the buffer status bit may instantly re set it on the +// next clock cycle. +#define USB_BUFF_STATUS_OFFSET _u(0x00000058) +#define USB_BUFF_STATUS_BITS _u(0xffffffff) +#define USB_BUFF_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_OUT +#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_IN +#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_STATUS_EP15_IN_MSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_LSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_OUT +#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_IN +#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_STATUS_EP14_IN_MSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_LSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_OUT +#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_IN +#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_STATUS_EP13_IN_MSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_LSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_OUT +#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_IN +#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_STATUS_EP12_IN_MSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_LSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_OUT +#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_IN +#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_STATUS_EP11_IN_MSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_LSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_OUT +#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_IN +#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_STATUS_EP10_IN_MSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_LSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_OUT +#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_IN +#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_STATUS_EP9_IN_MSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_LSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_OUT +#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_IN +#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_STATUS_EP8_IN_MSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_LSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_OUT +#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_IN +#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_STATUS_EP7_IN_MSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_LSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_OUT +#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_IN +#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_STATUS_EP6_IN_MSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_LSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_OUT +#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_IN +#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_STATUS_EP5_IN_MSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_LSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_OUT +#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_IN +#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_STATUS_EP4_IN_MSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_LSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_OUT +#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_IN +#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_STATUS_EP3_IN_MSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_LSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_OUT +#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_IN +#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_STATUS_EP2_IN_MSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_LSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_OUT +#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_IN +#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_STATUS_EP1_IN_MSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_LSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_OUT +#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_IN +#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_STATUS_EP0_IN_MSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_LSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_BUFF_CPU_SHOULD_HANDLE +// Description : Which of the double buffers should be handled. Only valid if +// using an interrupt per buffer (i.e. not per 2 buffers). Not +// valid for host interrupt endpoint polling because they are only +// single buffered. +#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c) +#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff) +#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" +// ============================================================================= +// Register : USB_EP_ABORT +// Description : Device only: Can be set to ignore the buffer control register +// for this endpoint in case you would like to revoke a buffer. A +// NAK will be sent for every access to the endpoint until this +// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set +// when it is safe to modify the buffer control register. +#define USB_EP_ABORT_OFFSET _u(0x00000060) +#define USB_EP_ABORT_BITS _u(0xffffffff) +#define USB_EP_ABORT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_OUT +#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_EP15_OUT_LSB _u(31) +#define USB_EP_ABORT_EP15_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_IN +#define USB_EP_ABORT_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_EP15_IN_LSB _u(30) +#define USB_EP_ABORT_EP15_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_OUT +#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_EP14_OUT_LSB _u(29) +#define USB_EP_ABORT_EP14_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_IN +#define USB_EP_ABORT_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_EP14_IN_LSB _u(28) +#define USB_EP_ABORT_EP14_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_OUT +#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_EP13_OUT_LSB _u(27) +#define USB_EP_ABORT_EP13_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_IN +#define USB_EP_ABORT_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_EP13_IN_LSB _u(26) +#define USB_EP_ABORT_EP13_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_OUT +#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_EP12_OUT_LSB _u(25) +#define USB_EP_ABORT_EP12_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_IN +#define USB_EP_ABORT_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_EP12_IN_LSB _u(24) +#define USB_EP_ABORT_EP12_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_OUT +#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_EP11_OUT_LSB _u(23) +#define USB_EP_ABORT_EP11_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_IN +#define USB_EP_ABORT_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_EP11_IN_LSB _u(22) +#define USB_EP_ABORT_EP11_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_OUT +#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_EP10_OUT_LSB _u(21) +#define USB_EP_ABORT_EP10_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_IN +#define USB_EP_ABORT_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_EP10_IN_LSB _u(20) +#define USB_EP_ABORT_EP10_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_OUT +#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_EP9_OUT_LSB _u(19) +#define USB_EP_ABORT_EP9_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_IN +#define USB_EP_ABORT_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_EP9_IN_LSB _u(18) +#define USB_EP_ABORT_EP9_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_OUT +#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_EP8_OUT_LSB _u(17) +#define USB_EP_ABORT_EP8_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_IN +#define USB_EP_ABORT_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_EP8_IN_LSB _u(16) +#define USB_EP_ABORT_EP8_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_OUT +#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_EP7_OUT_LSB _u(15) +#define USB_EP_ABORT_EP7_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_IN +#define USB_EP_ABORT_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_EP7_IN_LSB _u(14) +#define USB_EP_ABORT_EP7_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_OUT +#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_EP6_OUT_LSB _u(13) +#define USB_EP_ABORT_EP6_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_IN +#define USB_EP_ABORT_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_EP6_IN_LSB _u(12) +#define USB_EP_ABORT_EP6_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_OUT +#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_EP5_OUT_LSB _u(11) +#define USB_EP_ABORT_EP5_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_IN +#define USB_EP_ABORT_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_EP5_IN_LSB _u(10) +#define USB_EP_ABORT_EP5_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_OUT +#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_EP4_OUT_LSB _u(9) +#define USB_EP_ABORT_EP4_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_IN +#define USB_EP_ABORT_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_EP4_IN_LSB _u(8) +#define USB_EP_ABORT_EP4_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_OUT +#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_EP3_OUT_LSB _u(7) +#define USB_EP_ABORT_EP3_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_IN +#define USB_EP_ABORT_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_EP3_IN_LSB _u(6) +#define USB_EP_ABORT_EP3_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_OUT +#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_EP2_OUT_LSB _u(5) +#define USB_EP_ABORT_EP2_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_IN +#define USB_EP_ABORT_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_EP2_IN_LSB _u(4) +#define USB_EP_ABORT_EP2_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_OUT +#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_EP1_OUT_LSB _u(3) +#define USB_EP_ABORT_EP1_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_IN +#define USB_EP_ABORT_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_EP1_IN_LSB _u(2) +#define USB_EP_ABORT_EP1_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_OUT +#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_EP0_OUT_LSB _u(1) +#define USB_EP_ABORT_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_IN +#define USB_EP_ABORT_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_EP0_IN_LSB _u(0) +#define USB_EP_ABORT_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_ABORT_DONE +// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an +// endpoint is idle so the programmer knows it is safe to modify +// the buffer control register. +#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064) +#define USB_EP_ABORT_DONE_BITS _u(0xffffffff) +#define USB_EP_ABORT_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_OUT +#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31) +#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_IN +#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30) +#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_OUT +#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29) +#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_IN +#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28) +#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_OUT +#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27) +#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_IN +#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26) +#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_OUT +#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25) +#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_IN +#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24) +#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_OUT +#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23) +#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_IN +#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22) +#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_OUT +#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21) +#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_IN +#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20) +#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_OUT +#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19) +#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_IN +#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18) +#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_OUT +#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17) +#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_IN +#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16) +#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_OUT +#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15) +#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_IN +#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14) +#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_OUT +#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13) +#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_IN +#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12) +#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_OUT +#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11) +#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_IN +#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10) +#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_OUT +#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9) +#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_IN +#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8) +#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_OUT +#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7) +#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_IN +#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6) +#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_OUT +#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5) +#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_IN +#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4) +#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_OUT +#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3) +#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_IN +#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2) +#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_OUT +#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1) +#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_IN +#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0) +#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_EP_STALL_ARM +// Description : Device: this bit must be set in conjunction with the `STALL` +// bit in the buffer control register to send a STALL on EP0. The +// device controller clears these bits when a SETUP packet is +// received because the USB spec requires that a STALL condition +// is cleared when a SETUP packet is received. +#define USB_EP_STALL_ARM_OFFSET _u(0x00000068) +#define USB_EP_STALL_ARM_BITS _u(0x00000003) +#define USB_EP_STALL_ARM_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_OUT +#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) +#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1) +#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_IN +#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) +#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0) +#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_NAK_POLL +// Description : Used by the host controller. Sets the wait time in microseconds +// before trying again if the device replies with a NAK. +#define USB_NAK_POLL_OFFSET _u(0x0000006c) +#define USB_NAK_POLL_BITS _u(0xffffffff) +#define USB_NAK_POLL_RESET _u(0x00100010) +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_RETRY_COUNT_HI +// Description : Bits 9:6 of nak_retry count +#define USB_NAK_POLL_RETRY_COUNT_HI_RESET _u(0x0) +#define USB_NAK_POLL_RETRY_COUNT_HI_BITS _u(0xf0000000) +#define USB_NAK_POLL_RETRY_COUNT_HI_MSB _u(31) +#define USB_NAK_POLL_RETRY_COUNT_HI_LSB _u(28) +#define USB_NAK_POLL_RETRY_COUNT_HI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_EPX_STOPPED_ON_NAK +// Description : EPX polling has stopped because a nak was received +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_BITS _u(0x08000000) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_MSB _u(27) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_LSB _u(27) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_STOP_EPX_ON_NAK +// Description : Stop polling epx when a nak is received +#define USB_NAK_POLL_STOP_EPX_ON_NAK_RESET _u(0x0) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_BITS _u(0x04000000) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_MSB _u(26) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_LSB _u(26) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_FS +// Description : NAK polling interval for a full speed device +#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000) +#define USB_NAK_POLL_DELAY_FS_MSB _u(25) +#define USB_NAK_POLL_DELAY_FS_LSB _u(16) +#define USB_NAK_POLL_DELAY_FS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_RETRY_COUNT_LO +// Description : Bits 5:0 of nak_retry_count +#define USB_NAK_POLL_RETRY_COUNT_LO_RESET _u(0x00) +#define USB_NAK_POLL_RETRY_COUNT_LO_BITS _u(0x0000fc00) +#define USB_NAK_POLL_RETRY_COUNT_LO_MSB _u(15) +#define USB_NAK_POLL_RETRY_COUNT_LO_LSB _u(10) +#define USB_NAK_POLL_RETRY_COUNT_LO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_LS +// Description : NAK polling interval for a low speed device +#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff) +#define USB_NAK_POLL_DELAY_LS_MSB _u(9) +#define USB_NAK_POLL_DELAY_LS_LSB _u(0) +#define USB_NAK_POLL_DELAY_LS_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_STATUS_STALL_NAK +// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` +// bits are set. For EP0 this comes from `SIE_CTRL`. For all other +// endpoints it comes from the endpoint control register. +#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070) +#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff) +#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_IN +#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_IN +#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_IN +#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_IN +#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_IN +#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_IN +#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_IN +#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_IN +#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_IN +#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_IN +#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_IN +#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_IN +#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_IN +#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_IN +#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_IN +#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_IN +#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_USB_MUXING +// Description : Where to connect the USB controller. Should be to_phy by +// default. +#define USB_USB_MUXING_OFFSET _u(0x00000074) +#define USB_USB_MUXING_BITS _u(0x8000001f) +#define USB_USB_MUXING_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_SWAP_DPDM +// Description : Swap the USB PHY DP and DM pins and all related controls and +// flip receive differential data. Can be used to switch USB DP/DP +// on the PCB. +// This is done at a low level so overrides all other controls. +#define USB_USB_MUXING_SWAP_DPDM_RESET _u(0x0) +#define USB_USB_MUXING_SWAP_DPDM_BITS _u(0x80000000) +#define USB_USB_MUXING_SWAP_DPDM_MSB _u(31) +#define USB_USB_MUXING_SWAP_DPDM_LSB _u(31) +#define USB_USB_MUXING_SWAP_DPDM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_USBPHY_AS_GPIO +// Description : Use the usb DP and DM pins as GPIO pins instead of connecting +// them to the USB controller. +#define USB_USB_MUXING_USBPHY_AS_GPIO_RESET _u(0x0) +#define USB_USB_MUXING_USBPHY_AS_GPIO_BITS _u(0x00000010) +#define USB_USB_MUXING_USBPHY_AS_GPIO_MSB _u(4) +#define USB_USB_MUXING_USBPHY_AS_GPIO_LSB _u(4) +#define USB_USB_MUXING_USBPHY_AS_GPIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_SOFTCON +#define USB_USB_MUXING_SOFTCON_RESET _u(0x0) +#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) +#define USB_USB_MUXING_SOFTCON_MSB _u(3) +#define USB_USB_MUXING_SOFTCON_LSB _u(3) +#define USB_USB_MUXING_SOFTCON_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_DIGITAL_PAD +#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) +#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) +#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) +#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2) +#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_EXTPHY +#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) +#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) +#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) +#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1) +#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_PHY +#define USB_USB_MUXING_TO_PHY_RESET _u(0x1) +#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) +#define USB_USB_MUXING_TO_PHY_MSB _u(0) +#define USB_USB_MUXING_TO_PHY_LSB _u(0) +#define USB_USB_MUXING_TO_PHY_ACCESS "RW" +// ============================================================================= +// Register : USB_USB_PWR +// Description : Overrides for the power signals in the event that the VBUS +// signals are not hooked up to GPIO. Set the value of the +// override and then the override enable to switch over to the +// override value. +#define USB_USB_PWR_OFFSET _u(0x00000078) +#define USB_USB_PWR_BITS _u(0x0000003f) +#define USB_USB_PWR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT_EN +#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) +#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) +#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5) +#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT +#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) +#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) +#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4) +#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT +#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) +#define USB_USB_PWR_VBUS_DETECT_MSB _u(2) +#define USB_USB_PWR_VBUS_DETECT_LSB _u(2) +#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN +#define USB_USB_PWR_VBUS_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) +#define USB_USB_PWR_VBUS_EN_MSB _u(0) +#define USB_USB_PWR_VBUS_EN_LSB _u(0) +#define USB_USB_PWR_VBUS_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT +// Description : This register allows for direct control of the USB phy. Use in +// conjunction with usbphy_direct_override register to enable each +// override bit. +#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) +#define USB_USBPHY_DIRECT_BITS _u(0x03ffff77) +#define USB_USBPHY_DIRECT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DM_OVERRIDE +// Description : Override rx_dm value into controller +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_BITS _u(0x02000000) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_MSB _u(25) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_LSB _u(25) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DP_OVERRIDE +// Description : Override rx_dp value into controller +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_BITS _u(0x01000000) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_MSB _u(24) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_LSB _u(24) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DD_OVERRIDE +// Description : Override rx_dd value into controller +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_BITS _u(0x00800000) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_MSB _u(23) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_LSB _u(23) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVV +// Description : DM over voltage +#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) +#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) +#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22) +#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVV +// Description : DP over voltage +#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) +#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) +#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21) +#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVCN +// Description : DM overcurrent +#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) +#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) +#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20) +#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVCN +// Description : DP overcurrent +#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) +#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) +#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19) +#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DM +// Description : DPM pin state +#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) +#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) +#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18) +#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DP +// Description : DPP pin state +#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) +#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) +#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17) +#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DD +// Description : Differential RX +#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) +#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) +#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16) +#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DIFFMODE +// Description : TX_DIFFMODE=0: Single ended mode +// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE +// ignored) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_FSSLEW +// Description : TX_FSSLEW=0: Low speed slew rate +// TX_FSSLEW=1: Full speed slew rate +#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) +#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) +#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14) +#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_PD +// Description : TX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) +#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) +#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13) +#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_PD +// Description : RX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) +#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12) +#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM +// Description : Output data. TX_DIFFMODE=1, Ignored +// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. +// DPM=TX_DM +#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11) +#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11) +#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP +// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. +// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP +// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. +// DPP=TX_DP +#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10) +#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10) +#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM_OE +// Description : Output enable. If TX_DIFFMODE=1, Ignored. +// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - +// DPM driving +#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) +#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9) +#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP_OE +// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - +// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving +// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - +// DPP driving +#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) +#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8) +#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN +// Description : DM pull down enable +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN +// Description : DM pull up enable +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL +// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN +// Description : DP pull down enable +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN +// Description : DP pull up enable +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL +// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT_OVERRIDE +// Description : Override enable for each control in usbphy_direct +#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00079fff) +#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_BITS _u(0x00040000) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_MSB _u(18) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_LSB _u(18) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_BITS _u(0x00020000) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_MSB _u(17) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_LSB _u(17) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_BITS _u(0x00010000) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_MSB _u(16) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_LSB _u(16) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_TRIM +// Description : Used to adjust trim values of USB phy pull down resistors. +#define USB_USBPHY_TRIM_OFFSET _u(0x00000084) +#define USB_USBPHY_TRIM_BITS _u(0x00001f1f) +#define USB_USBPHY_TRIM_RESET _u(0x00001f1f) +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DM pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DP pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" +// ============================================================================= +// Register : USB_LINESTATE_TUNING +// Description : Used for debug only. +#define USB_LINESTATE_TUNING_OFFSET _u(0x00000088) +#define USB_LINESTATE_TUNING_BITS _u(0x00000fff) +#define USB_LINESTATE_TUNING_RESET _u(0x000000f8) +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_SPARE_FIX +#define USB_LINESTATE_TUNING_SPARE_FIX_RESET _u(0x0) +#define USB_LINESTATE_TUNING_SPARE_FIX_BITS _u(0x00000f00) +#define USB_LINESTATE_TUNING_SPARE_FIX_MSB _u(11) +#define USB_LINESTATE_TUNING_SPARE_FIX_LSB _u(8) +#define USB_LINESTATE_TUNING_SPARE_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX +// Description : Device - exit suspend on any non-idle signalling, not qualified +// with a 1ms timer +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_BITS _u(0x00000080) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_MSB _u(7) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_LSB _u(7) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE +// Description : Device - suppress repeated errors until the device FSM is next +// in the process of decoding an inbound packet. +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_RESET _u(0x1) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_BITS _u(0x00000040) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_MSB _u(6) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_LSB _u(6) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX +// Description : RX - when recovering from line chatter or bitstuff errors, +// treat SE0 as the end of chatter as well as +// 8 consecutive idle bits. +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_BITS _u(0x00000020) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_MSB _u(5) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_LSB _u(5) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX +// Description : RX - when a bitstuff error is signalled by rx_dasm, +// unconditionally terminate RX decode to +// avoid a hang during certain packet phases. +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_BITS _u(0x00000010) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_MSB _u(4) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_LSB _u(4) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX +// Description : Device - the controller FSM performs two reads of the buffer +// status memory address to +// avoid sampling metastable data. An enabled buffer is only used +// if both reads match. +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_BITS _u(0x00000008) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_MSB _u(3) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_LSB _u(3) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_MULTI_HUB_FIX +// Description : Host - increase inter-packet and turnaround timeouts to +// accommodate worst-case hub delays. +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_RESET _u(0x0) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_BITS _u(0x00000004) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_MSB _u(2) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_LSB _u(2) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_LINESTATE_DELAY +// Description : Device/Host - add an extra 1-bit debounce of linestate +// sampling. +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_RESET _u(0x0) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_BITS _u(0x00000002) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_MSB _u(1) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_LSB _u(1) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_RCV_DELAY +// Description : Device - register the received data to account for hub bit +// dribble before EOP. Only affects certain hubs. +#define USB_LINESTATE_TUNING_RCV_DELAY_RESET _u(0x0) +#define USB_LINESTATE_TUNING_RCV_DELAY_BITS _u(0x00000001) +#define USB_LINESTATE_TUNING_RCV_DELAY_MSB _u(0) +#define USB_LINESTATE_TUNING_RCV_DELAY_LSB _u(0) +#define USB_LINESTATE_TUNING_RCV_DELAY_ACCESS "RW" +// ============================================================================= +// Register : USB_INTR +// Description : Raw Interrupts +#define USB_INTR_OFFSET _u(0x0000008c) +#define USB_INTR_BITS _u(0x00ffffff) +#define USB_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTR_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTR_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTR_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTR_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTR_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTR_EPX_STOPPED_ON_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTR_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTR_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTR_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTR_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTR_ENDPOINT_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTR_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTR_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTR_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTR_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTR_RX_SHORT_PACKET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTR_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTR_EP_STALL_NAK_MSB _u(19) +#define USB_INTR_EP_STALL_NAK_LSB _u(19) +#define USB_INTR_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTR_ABORT_DONE_RESET _u(0x0) +#define USB_INTR_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTR_ABORT_DONE_MSB _u(18) +#define USB_INTR_ABORT_DONE_LSB _u(18) +#define USB_INTR_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTR_DEV_SOF_RESET _u(0x0) +#define USB_INTR_DEV_SOF_BITS _u(0x00020000) +#define USB_INTR_DEV_SOF_MSB _u(17) +#define USB_INTR_DEV_SOF_LSB _u(17) +#define USB_INTR_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTR_SETUP_REQ_RESET _u(0x0) +#define USB_INTR_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTR_SETUP_REQ_MSB _u(16) +#define USB_INTR_SETUP_REQ_LSB _u(16) +#define USB_INTR_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTR_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTR_DEV_SUSPEND_MSB _u(14) +#define USB_INTR_DEV_SUSPEND_LSB _u(14) +#define USB_INTR_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTR_DEV_CONN_DIS_MSB _u(13) +#define USB_INTR_DEV_CONN_DIS_LSB _u(13) +#define USB_INTR_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTR_BUS_RESET_RESET _u(0x0) +#define USB_INTR_BUS_RESET_BITS _u(0x00001000) +#define USB_INTR_BUS_RESET_MSB _u(12) +#define USB_INTR_BUS_RESET_LSB _u(12) +#define USB_INTR_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTR_VBUS_DETECT_RESET _u(0x0) +#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTR_VBUS_DETECT_MSB _u(11) +#define USB_INTR_VBUS_DETECT_LSB _u(11) +#define USB_INTR_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTR_STALL_RESET _u(0x0) +#define USB_INTR_STALL_BITS _u(0x00000400) +#define USB_INTR_STALL_MSB _u(10) +#define USB_INTR_STALL_LSB _u(10) +#define USB_INTR_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTR_ERROR_CRC_RESET _u(0x0) +#define USB_INTR_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTR_ERROR_CRC_MSB _u(9) +#define USB_INTR_ERROR_CRC_LSB _u(9) +#define USB_INTR_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTR_BUFF_STATUS_RESET _u(0x0) +#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTR_BUFF_STATUS_MSB _u(4) +#define USB_INTR_BUFF_STATUS_LSB _u(4) +#define USB_INTR_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTR_TRANS_COMPLETE_MSB _u(3) +#define USB_INTR_TRANS_COMPLETE_LSB _u(3) +#define USB_INTR_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTR_HOST_SOF_RESET _u(0x0) +#define USB_INTR_HOST_SOF_BITS _u(0x00000004) +#define USB_INTR_HOST_SOF_MSB _u(2) +#define USB_INTR_HOST_SOF_LSB _u(2) +#define USB_INTR_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_HOST_RESUME_RESET _u(0x0) +#define USB_INTR_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTR_HOST_RESUME_MSB _u(1) +#define USB_INTR_HOST_RESUME_LSB _u(1) +#define USB_INTR_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTR_HOST_CONN_DIS_MSB _u(0) +#define USB_INTR_HOST_CONN_DIS_LSB _u(0) +#define USB_INTR_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +// Register : USB_INTE +// Description : Interrupt Enable +#define USB_INTE_OFFSET _u(0x00000090) +#define USB_INTE_BITS _u(0x00ffffff) +#define USB_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTE_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTE_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTE_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTE_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTE_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTE_EPX_STOPPED_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTE_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTE_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTE_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTE_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTE_ENDPOINT_ERROR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTE_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTE_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTE_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTE_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTE_RX_SHORT_PACKET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTE_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTE_EP_STALL_NAK_MSB _u(19) +#define USB_INTE_EP_STALL_NAK_LSB _u(19) +#define USB_INTE_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTE_ABORT_DONE_RESET _u(0x0) +#define USB_INTE_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTE_ABORT_DONE_MSB _u(18) +#define USB_INTE_ABORT_DONE_LSB _u(18) +#define USB_INTE_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTE_DEV_SOF_RESET _u(0x0) +#define USB_INTE_DEV_SOF_BITS _u(0x00020000) +#define USB_INTE_DEV_SOF_MSB _u(17) +#define USB_INTE_DEV_SOF_LSB _u(17) +#define USB_INTE_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTE_SETUP_REQ_RESET _u(0x0) +#define USB_INTE_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTE_SETUP_REQ_MSB _u(16) +#define USB_INTE_SETUP_REQ_LSB _u(16) +#define USB_INTE_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTE_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTE_DEV_SUSPEND_MSB _u(14) +#define USB_INTE_DEV_SUSPEND_LSB _u(14) +#define USB_INTE_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTE_DEV_CONN_DIS_MSB _u(13) +#define USB_INTE_DEV_CONN_DIS_LSB _u(13) +#define USB_INTE_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTE_BUS_RESET_RESET _u(0x0) +#define USB_INTE_BUS_RESET_BITS _u(0x00001000) +#define USB_INTE_BUS_RESET_MSB _u(12) +#define USB_INTE_BUS_RESET_LSB _u(12) +#define USB_INTE_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTE_VBUS_DETECT_RESET _u(0x0) +#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTE_VBUS_DETECT_MSB _u(11) +#define USB_INTE_VBUS_DETECT_LSB _u(11) +#define USB_INTE_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTE_STALL_RESET _u(0x0) +#define USB_INTE_STALL_BITS _u(0x00000400) +#define USB_INTE_STALL_MSB _u(10) +#define USB_INTE_STALL_LSB _u(10) +#define USB_INTE_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTE_ERROR_CRC_RESET _u(0x0) +#define USB_INTE_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTE_ERROR_CRC_MSB _u(9) +#define USB_INTE_ERROR_CRC_LSB _u(9) +#define USB_INTE_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTE_BUFF_STATUS_RESET _u(0x0) +#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTE_BUFF_STATUS_MSB _u(4) +#define USB_INTE_BUFF_STATUS_LSB _u(4) +#define USB_INTE_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTE_TRANS_COMPLETE_MSB _u(3) +#define USB_INTE_TRANS_COMPLETE_LSB _u(3) +#define USB_INTE_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTE_HOST_SOF_RESET _u(0x0) +#define USB_INTE_HOST_SOF_BITS _u(0x00000004) +#define USB_INTE_HOST_SOF_MSB _u(2) +#define USB_INTE_HOST_SOF_LSB _u(2) +#define USB_INTE_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_HOST_RESUME_RESET _u(0x0) +#define USB_INTE_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTE_HOST_RESUME_MSB _u(1) +#define USB_INTE_HOST_RESUME_LSB _u(1) +#define USB_INTE_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTE_HOST_CONN_DIS_MSB _u(0) +#define USB_INTE_HOST_CONN_DIS_LSB _u(0) +#define USB_INTE_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTF +// Description : Interrupt Force +#define USB_INTF_OFFSET _u(0x00000094) +#define USB_INTF_BITS _u(0x00ffffff) +#define USB_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTF_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTF_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTF_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTF_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTF_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTF_EPX_STOPPED_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTF_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTF_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTF_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTF_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTF_ENDPOINT_ERROR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTF_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTF_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTF_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTF_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTF_RX_SHORT_PACKET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTF_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTF_EP_STALL_NAK_MSB _u(19) +#define USB_INTF_EP_STALL_NAK_LSB _u(19) +#define USB_INTF_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTF_ABORT_DONE_RESET _u(0x0) +#define USB_INTF_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTF_ABORT_DONE_MSB _u(18) +#define USB_INTF_ABORT_DONE_LSB _u(18) +#define USB_INTF_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTF_DEV_SOF_RESET _u(0x0) +#define USB_INTF_DEV_SOF_BITS _u(0x00020000) +#define USB_INTF_DEV_SOF_MSB _u(17) +#define USB_INTF_DEV_SOF_LSB _u(17) +#define USB_INTF_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTF_SETUP_REQ_RESET _u(0x0) +#define USB_INTF_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTF_SETUP_REQ_MSB _u(16) +#define USB_INTF_SETUP_REQ_LSB _u(16) +#define USB_INTF_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTF_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTF_DEV_SUSPEND_MSB _u(14) +#define USB_INTF_DEV_SUSPEND_LSB _u(14) +#define USB_INTF_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTF_DEV_CONN_DIS_MSB _u(13) +#define USB_INTF_DEV_CONN_DIS_LSB _u(13) +#define USB_INTF_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTF_BUS_RESET_RESET _u(0x0) +#define USB_INTF_BUS_RESET_BITS _u(0x00001000) +#define USB_INTF_BUS_RESET_MSB _u(12) +#define USB_INTF_BUS_RESET_LSB _u(12) +#define USB_INTF_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTF_VBUS_DETECT_RESET _u(0x0) +#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTF_VBUS_DETECT_MSB _u(11) +#define USB_INTF_VBUS_DETECT_LSB _u(11) +#define USB_INTF_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTF_STALL_RESET _u(0x0) +#define USB_INTF_STALL_BITS _u(0x00000400) +#define USB_INTF_STALL_MSB _u(10) +#define USB_INTF_STALL_LSB _u(10) +#define USB_INTF_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTF_ERROR_CRC_RESET _u(0x0) +#define USB_INTF_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTF_ERROR_CRC_MSB _u(9) +#define USB_INTF_ERROR_CRC_LSB _u(9) +#define USB_INTF_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTF_BUFF_STATUS_RESET _u(0x0) +#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTF_BUFF_STATUS_MSB _u(4) +#define USB_INTF_BUFF_STATUS_LSB _u(4) +#define USB_INTF_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTF_TRANS_COMPLETE_MSB _u(3) +#define USB_INTF_TRANS_COMPLETE_LSB _u(3) +#define USB_INTF_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTF_HOST_SOF_RESET _u(0x0) +#define USB_INTF_HOST_SOF_BITS _u(0x00000004) +#define USB_INTF_HOST_SOF_MSB _u(2) +#define USB_INTF_HOST_SOF_LSB _u(2) +#define USB_INTF_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_HOST_RESUME_RESET _u(0x0) +#define USB_INTF_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTF_HOST_RESUME_MSB _u(1) +#define USB_INTF_HOST_RESUME_LSB _u(1) +#define USB_INTF_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTF_HOST_CONN_DIS_MSB _u(0) +#define USB_INTF_HOST_CONN_DIS_LSB _u(0) +#define USB_INTF_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTS +// Description : Interrupt status after masking & forcing +#define USB_INTS_OFFSET _u(0x00000098) +#define USB_INTS_BITS _u(0x00ffffff) +#define USB_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTS_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTS_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTS_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTS_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTS_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTS_EPX_STOPPED_ON_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTS_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTS_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTS_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTS_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTS_ENDPOINT_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTS_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTS_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTS_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTS_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTS_RX_SHORT_PACKET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTS_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTS_EP_STALL_NAK_MSB _u(19) +#define USB_INTS_EP_STALL_NAK_LSB _u(19) +#define USB_INTS_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTS_ABORT_DONE_RESET _u(0x0) +#define USB_INTS_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTS_ABORT_DONE_MSB _u(18) +#define USB_INTS_ABORT_DONE_LSB _u(18) +#define USB_INTS_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTS_DEV_SOF_RESET _u(0x0) +#define USB_INTS_DEV_SOF_BITS _u(0x00020000) +#define USB_INTS_DEV_SOF_MSB _u(17) +#define USB_INTS_DEV_SOF_LSB _u(17) +#define USB_INTS_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTS_SETUP_REQ_RESET _u(0x0) +#define USB_INTS_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTS_SETUP_REQ_MSB _u(16) +#define USB_INTS_SETUP_REQ_LSB _u(16) +#define USB_INTS_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTS_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTS_DEV_SUSPEND_MSB _u(14) +#define USB_INTS_DEV_SUSPEND_LSB _u(14) +#define USB_INTS_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTS_DEV_CONN_DIS_MSB _u(13) +#define USB_INTS_DEV_CONN_DIS_LSB _u(13) +#define USB_INTS_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTS_BUS_RESET_RESET _u(0x0) +#define USB_INTS_BUS_RESET_BITS _u(0x00001000) +#define USB_INTS_BUS_RESET_MSB _u(12) +#define USB_INTS_BUS_RESET_LSB _u(12) +#define USB_INTS_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTS_VBUS_DETECT_RESET _u(0x0) +#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTS_VBUS_DETECT_MSB _u(11) +#define USB_INTS_VBUS_DETECT_LSB _u(11) +#define USB_INTS_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTS_STALL_RESET _u(0x0) +#define USB_INTS_STALL_BITS _u(0x00000400) +#define USB_INTS_STALL_MSB _u(10) +#define USB_INTS_STALL_LSB _u(10) +#define USB_INTS_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTS_ERROR_CRC_RESET _u(0x0) +#define USB_INTS_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTS_ERROR_CRC_MSB _u(9) +#define USB_INTS_ERROR_CRC_LSB _u(9) +#define USB_INTS_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTS_BUFF_STATUS_RESET _u(0x0) +#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTS_BUFF_STATUS_MSB _u(4) +#define USB_INTS_BUFF_STATUS_LSB _u(4) +#define USB_INTS_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTS_TRANS_COMPLETE_MSB _u(3) +#define USB_INTS_TRANS_COMPLETE_LSB _u(3) +#define USB_INTS_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTS_HOST_SOF_RESET _u(0x0) +#define USB_INTS_HOST_SOF_BITS _u(0x00000004) +#define USB_INTS_HOST_SOF_MSB _u(2) +#define USB_INTS_HOST_SOF_LSB _u(2) +#define USB_INTS_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_HOST_RESUME_RESET _u(0x0) +#define USB_INTS_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTS_HOST_RESUME_MSB _u(1) +#define USB_INTS_HOST_RESUME_LSB _u(1) +#define USB_INTS_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTS_HOST_CONN_DIS_MSB _u(0) +#define USB_INTS_HOST_CONN_DIS_LSB _u(0) +#define USB_INTS_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +// Register : USB_SOF_TIMESTAMP_RAW +// Description : Device only. Raw value of free-running PHY clock counter +// @48MHz. Used to calculate time between SOF events. +#define USB_SOF_TIMESTAMP_RAW_OFFSET _u(0x00000100) +#define USB_SOF_TIMESTAMP_RAW_BITS _u(0x001fffff) +#define USB_SOF_TIMESTAMP_RAW_RESET _u(0x00000000) +#define USB_SOF_TIMESTAMP_RAW_MSB _u(20) +#define USB_SOF_TIMESTAMP_RAW_LSB _u(0) +#define USB_SOF_TIMESTAMP_RAW_ACCESS "RO" +// ============================================================================= +// Register : USB_SOF_TIMESTAMP_LAST +// Description : Device only. Value of free-running PHY clock counter @48MHz +// when last SOF event occurred. +#define USB_SOF_TIMESTAMP_LAST_OFFSET _u(0x00000104) +#define USB_SOF_TIMESTAMP_LAST_BITS _u(0x001fffff) +#define USB_SOF_TIMESTAMP_LAST_RESET _u(0x00000000) +#define USB_SOF_TIMESTAMP_LAST_MSB _u(20) +#define USB_SOF_TIMESTAMP_LAST_LSB _u(0) +#define USB_SOF_TIMESTAMP_LAST_ACCESS "RO" +// ============================================================================= +// Register : USB_SM_STATE +#define USB_SM_STATE_OFFSET _u(0x00000108) +#define USB_SM_STATE_BITS _u(0x00000fff) +#define USB_SM_STATE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SM_STATE_RX_DASM +#define USB_SM_STATE_RX_DASM_RESET _u(0x0) +#define USB_SM_STATE_RX_DASM_BITS _u(0x00000f00) +#define USB_SM_STATE_RX_DASM_MSB _u(11) +#define USB_SM_STATE_RX_DASM_LSB _u(8) +#define USB_SM_STATE_RX_DASM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SM_STATE_BC_STATE +#define USB_SM_STATE_BC_STATE_RESET _u(0x0) +#define USB_SM_STATE_BC_STATE_BITS _u(0x000000e0) +#define USB_SM_STATE_BC_STATE_MSB _u(7) +#define USB_SM_STATE_BC_STATE_LSB _u(5) +#define USB_SM_STATE_BC_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SM_STATE_STATE +#define USB_SM_STATE_STATE_RESET _u(0x00) +#define USB_SM_STATE_STATE_BITS _u(0x0000001f) +#define USB_SM_STATE_STATE_MSB _u(4) +#define USB_SM_STATE_STATE_LSB _u(0) +#define USB_SM_STATE_STATE_ACCESS "RO" +// ============================================================================= +// Register : USB_EP_TX_ERROR +// Description : TX error count for each endpoint. Write to each field to reset +// the counter to 0. +#define USB_EP_TX_ERROR_OFFSET _u(0x0000010c) +#define USB_EP_TX_ERROR_BITS _u(0xffffffff) +#define USB_EP_TX_ERROR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP15 +#define USB_EP_TX_ERROR_EP15_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP15_BITS _u(0xc0000000) +#define USB_EP_TX_ERROR_EP15_MSB _u(31) +#define USB_EP_TX_ERROR_EP15_LSB _u(30) +#define USB_EP_TX_ERROR_EP15_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP14 +#define USB_EP_TX_ERROR_EP14_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP14_BITS _u(0x30000000) +#define USB_EP_TX_ERROR_EP14_MSB _u(29) +#define USB_EP_TX_ERROR_EP14_LSB _u(28) +#define USB_EP_TX_ERROR_EP14_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP13 +#define USB_EP_TX_ERROR_EP13_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP13_BITS _u(0x0c000000) +#define USB_EP_TX_ERROR_EP13_MSB _u(27) +#define USB_EP_TX_ERROR_EP13_LSB _u(26) +#define USB_EP_TX_ERROR_EP13_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP12 +#define USB_EP_TX_ERROR_EP12_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP12_BITS _u(0x03000000) +#define USB_EP_TX_ERROR_EP12_MSB _u(25) +#define USB_EP_TX_ERROR_EP12_LSB _u(24) +#define USB_EP_TX_ERROR_EP12_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP11 +#define USB_EP_TX_ERROR_EP11_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP11_BITS _u(0x00c00000) +#define USB_EP_TX_ERROR_EP11_MSB _u(23) +#define USB_EP_TX_ERROR_EP11_LSB _u(22) +#define USB_EP_TX_ERROR_EP11_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP10 +#define USB_EP_TX_ERROR_EP10_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP10_BITS _u(0x00300000) +#define USB_EP_TX_ERROR_EP10_MSB _u(21) +#define USB_EP_TX_ERROR_EP10_LSB _u(20) +#define USB_EP_TX_ERROR_EP10_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP9 +#define USB_EP_TX_ERROR_EP9_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP9_BITS _u(0x000c0000) +#define USB_EP_TX_ERROR_EP9_MSB _u(19) +#define USB_EP_TX_ERROR_EP9_LSB _u(18) +#define USB_EP_TX_ERROR_EP9_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP8 +#define USB_EP_TX_ERROR_EP8_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP8_BITS _u(0x00030000) +#define USB_EP_TX_ERROR_EP8_MSB _u(17) +#define USB_EP_TX_ERROR_EP8_LSB _u(16) +#define USB_EP_TX_ERROR_EP8_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP7 +#define USB_EP_TX_ERROR_EP7_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP7_BITS _u(0x0000c000) +#define USB_EP_TX_ERROR_EP7_MSB _u(15) +#define USB_EP_TX_ERROR_EP7_LSB _u(14) +#define USB_EP_TX_ERROR_EP7_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP6 +#define USB_EP_TX_ERROR_EP6_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP6_BITS _u(0x00003000) +#define USB_EP_TX_ERROR_EP6_MSB _u(13) +#define USB_EP_TX_ERROR_EP6_LSB _u(12) +#define USB_EP_TX_ERROR_EP6_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP5 +#define USB_EP_TX_ERROR_EP5_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP5_BITS _u(0x00000c00) +#define USB_EP_TX_ERROR_EP5_MSB _u(11) +#define USB_EP_TX_ERROR_EP5_LSB _u(10) +#define USB_EP_TX_ERROR_EP5_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP4 +#define USB_EP_TX_ERROR_EP4_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP4_BITS _u(0x00000300) +#define USB_EP_TX_ERROR_EP4_MSB _u(9) +#define USB_EP_TX_ERROR_EP4_LSB _u(8) +#define USB_EP_TX_ERROR_EP4_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP3 +#define USB_EP_TX_ERROR_EP3_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP3_BITS _u(0x000000c0) +#define USB_EP_TX_ERROR_EP3_MSB _u(7) +#define USB_EP_TX_ERROR_EP3_LSB _u(6) +#define USB_EP_TX_ERROR_EP3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP2 +#define USB_EP_TX_ERROR_EP2_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP2_BITS _u(0x00000030) +#define USB_EP_TX_ERROR_EP2_MSB _u(5) +#define USB_EP_TX_ERROR_EP2_LSB _u(4) +#define USB_EP_TX_ERROR_EP2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP1 +#define USB_EP_TX_ERROR_EP1_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP1_BITS _u(0x0000000c) +#define USB_EP_TX_ERROR_EP1_MSB _u(3) +#define USB_EP_TX_ERROR_EP1_LSB _u(2) +#define USB_EP_TX_ERROR_EP1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP0 +#define USB_EP_TX_ERROR_EP0_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP0_BITS _u(0x00000003) +#define USB_EP_TX_ERROR_EP0_MSB _u(1) +#define USB_EP_TX_ERROR_EP0_LSB _u(0) +#define USB_EP_TX_ERROR_EP0_ACCESS "WC" +// ============================================================================= +// Register : USB_EP_RX_ERROR +// Description : RX error count for each endpoint. Write to each field to reset +// the counter to 0. +#define USB_EP_RX_ERROR_OFFSET _u(0x00000110) +#define USB_EP_RX_ERROR_BITS _u(0xffffffff) +#define USB_EP_RX_ERROR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP15_SEQ +#define USB_EP_RX_ERROR_EP15_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP15_SEQ_BITS _u(0x80000000) +#define USB_EP_RX_ERROR_EP15_SEQ_MSB _u(31) +#define USB_EP_RX_ERROR_EP15_SEQ_LSB _u(31) +#define USB_EP_RX_ERROR_EP15_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP15_TRANSACTION +#define USB_EP_RX_ERROR_EP15_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_BITS _u(0x40000000) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_MSB _u(30) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_LSB _u(30) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP14_SEQ +#define USB_EP_RX_ERROR_EP14_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP14_SEQ_BITS _u(0x20000000) +#define USB_EP_RX_ERROR_EP14_SEQ_MSB _u(29) +#define USB_EP_RX_ERROR_EP14_SEQ_LSB _u(29) +#define USB_EP_RX_ERROR_EP14_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP14_TRANSACTION +#define USB_EP_RX_ERROR_EP14_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_BITS _u(0x10000000) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_MSB _u(28) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_LSB _u(28) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP13_SEQ +#define USB_EP_RX_ERROR_EP13_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP13_SEQ_BITS _u(0x08000000) +#define USB_EP_RX_ERROR_EP13_SEQ_MSB _u(27) +#define USB_EP_RX_ERROR_EP13_SEQ_LSB _u(27) +#define USB_EP_RX_ERROR_EP13_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP13_TRANSACTION +#define USB_EP_RX_ERROR_EP13_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_BITS _u(0x04000000) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_MSB _u(26) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_LSB _u(26) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP12_SEQ +#define USB_EP_RX_ERROR_EP12_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP12_SEQ_BITS _u(0x02000000) +#define USB_EP_RX_ERROR_EP12_SEQ_MSB _u(25) +#define USB_EP_RX_ERROR_EP12_SEQ_LSB _u(25) +#define USB_EP_RX_ERROR_EP12_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP12_TRANSACTION +#define USB_EP_RX_ERROR_EP12_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_BITS _u(0x01000000) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_MSB _u(24) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_LSB _u(24) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP11_SEQ +#define USB_EP_RX_ERROR_EP11_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP11_SEQ_BITS _u(0x00800000) +#define USB_EP_RX_ERROR_EP11_SEQ_MSB _u(23) +#define USB_EP_RX_ERROR_EP11_SEQ_LSB _u(23) +#define USB_EP_RX_ERROR_EP11_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP11_TRANSACTION +#define USB_EP_RX_ERROR_EP11_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_BITS _u(0x00400000) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_MSB _u(22) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_LSB _u(22) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP10_SEQ +#define USB_EP_RX_ERROR_EP10_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP10_SEQ_BITS _u(0x00200000) +#define USB_EP_RX_ERROR_EP10_SEQ_MSB _u(21) +#define USB_EP_RX_ERROR_EP10_SEQ_LSB _u(21) +#define USB_EP_RX_ERROR_EP10_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP10_TRANSACTION +#define USB_EP_RX_ERROR_EP10_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_BITS _u(0x00100000) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_MSB _u(20) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_LSB _u(20) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP9_SEQ +#define USB_EP_RX_ERROR_EP9_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP9_SEQ_BITS _u(0x00080000) +#define USB_EP_RX_ERROR_EP9_SEQ_MSB _u(19) +#define USB_EP_RX_ERROR_EP9_SEQ_LSB _u(19) +#define USB_EP_RX_ERROR_EP9_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP9_TRANSACTION +#define USB_EP_RX_ERROR_EP9_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_BITS _u(0x00040000) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_MSB _u(18) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_LSB _u(18) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP8_SEQ +#define USB_EP_RX_ERROR_EP8_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP8_SEQ_BITS _u(0x00020000) +#define USB_EP_RX_ERROR_EP8_SEQ_MSB _u(17) +#define USB_EP_RX_ERROR_EP8_SEQ_LSB _u(17) +#define USB_EP_RX_ERROR_EP8_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP8_TRANSACTION +#define USB_EP_RX_ERROR_EP8_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_BITS _u(0x00010000) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_MSB _u(16) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_LSB _u(16) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP7_SEQ +#define USB_EP_RX_ERROR_EP7_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP7_SEQ_BITS _u(0x00008000) +#define USB_EP_RX_ERROR_EP7_SEQ_MSB _u(15) +#define USB_EP_RX_ERROR_EP7_SEQ_LSB _u(15) +#define USB_EP_RX_ERROR_EP7_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP7_TRANSACTION +#define USB_EP_RX_ERROR_EP7_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_BITS _u(0x00004000) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_MSB _u(14) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_LSB _u(14) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP6_SEQ +#define USB_EP_RX_ERROR_EP6_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP6_SEQ_BITS _u(0x00002000) +#define USB_EP_RX_ERROR_EP6_SEQ_MSB _u(13) +#define USB_EP_RX_ERROR_EP6_SEQ_LSB _u(13) +#define USB_EP_RX_ERROR_EP6_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP6_TRANSACTION +#define USB_EP_RX_ERROR_EP6_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_BITS _u(0x00001000) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_MSB _u(12) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_LSB _u(12) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP5_SEQ +#define USB_EP_RX_ERROR_EP5_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP5_SEQ_BITS _u(0x00000800) +#define USB_EP_RX_ERROR_EP5_SEQ_MSB _u(11) +#define USB_EP_RX_ERROR_EP5_SEQ_LSB _u(11) +#define USB_EP_RX_ERROR_EP5_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP5_TRANSACTION +#define USB_EP_RX_ERROR_EP5_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_BITS _u(0x00000400) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_MSB _u(10) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_LSB _u(10) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP4_SEQ +#define USB_EP_RX_ERROR_EP4_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP4_SEQ_BITS _u(0x00000200) +#define USB_EP_RX_ERROR_EP4_SEQ_MSB _u(9) +#define USB_EP_RX_ERROR_EP4_SEQ_LSB _u(9) +#define USB_EP_RX_ERROR_EP4_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP4_TRANSACTION +#define USB_EP_RX_ERROR_EP4_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_BITS _u(0x00000100) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_MSB _u(8) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_LSB _u(8) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP3_SEQ +#define USB_EP_RX_ERROR_EP3_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP3_SEQ_BITS _u(0x00000080) +#define USB_EP_RX_ERROR_EP3_SEQ_MSB _u(7) +#define USB_EP_RX_ERROR_EP3_SEQ_LSB _u(7) +#define USB_EP_RX_ERROR_EP3_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP3_TRANSACTION +#define USB_EP_RX_ERROR_EP3_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_BITS _u(0x00000040) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_MSB _u(6) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_LSB _u(6) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP2_SEQ +#define USB_EP_RX_ERROR_EP2_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP2_SEQ_BITS _u(0x00000020) +#define USB_EP_RX_ERROR_EP2_SEQ_MSB _u(5) +#define USB_EP_RX_ERROR_EP2_SEQ_LSB _u(5) +#define USB_EP_RX_ERROR_EP2_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP2_TRANSACTION +#define USB_EP_RX_ERROR_EP2_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_BITS _u(0x00000010) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_MSB _u(4) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_LSB _u(4) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP1_SEQ +#define USB_EP_RX_ERROR_EP1_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP1_SEQ_BITS _u(0x00000008) +#define USB_EP_RX_ERROR_EP1_SEQ_MSB _u(3) +#define USB_EP_RX_ERROR_EP1_SEQ_LSB _u(3) +#define USB_EP_RX_ERROR_EP1_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP1_TRANSACTION +#define USB_EP_RX_ERROR_EP1_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_BITS _u(0x00000004) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_MSB _u(2) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_LSB _u(2) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP0_SEQ +#define USB_EP_RX_ERROR_EP0_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP0_SEQ_BITS _u(0x00000002) +#define USB_EP_RX_ERROR_EP0_SEQ_MSB _u(1) +#define USB_EP_RX_ERROR_EP0_SEQ_LSB _u(1) +#define USB_EP_RX_ERROR_EP0_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP0_TRANSACTION +#define USB_EP_RX_ERROR_EP0_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_BITS _u(0x00000001) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_MSB _u(0) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_LSB _u(0) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_ACCESS "WC" +// ============================================================================= +// Register : USB_DEV_SM_WATCHDOG +// Description : Watchdog that forces the device state machine to idle and +// raises an interrupt if the device stays in a state that isn't +// idle for the configured limit. The counter is reset on every +// state transition. +// Set limit while enable is low and then set the enable. +#define USB_DEV_SM_WATCHDOG_OFFSET _u(0x00000114) +#define USB_DEV_SM_WATCHDOG_BITS _u(0x001fffff) +#define USB_DEV_SM_WATCHDOG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_FIRED +#define USB_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00100000) +#define USB_DEV_SM_WATCHDOG_FIRED_MSB _u(20) +#define USB_DEV_SM_WATCHDOG_FIRED_LSB _u(20) +#define USB_DEV_SM_WATCHDOG_FIRED_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_RESET +// Description : Set to 1 to forcibly reset the device state machine on watchdog +// expiry +#define USB_DEV_SM_WATCHDOG_RESET_RESET _u(0x0) +#define USB_DEV_SM_WATCHDOG_RESET_BITS _u(0x00080000) +#define USB_DEV_SM_WATCHDOG_RESET_MSB _u(19) +#define USB_DEV_SM_WATCHDOG_RESET_LSB _u(19) +#define USB_DEV_SM_WATCHDOG_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_ENABLE +#define USB_DEV_SM_WATCHDOG_ENABLE_RESET _u(0x0) +#define USB_DEV_SM_WATCHDOG_ENABLE_BITS _u(0x00040000) +#define USB_DEV_SM_WATCHDOG_ENABLE_MSB _u(18) +#define USB_DEV_SM_WATCHDOG_ENABLE_LSB _u(18) +#define USB_DEV_SM_WATCHDOG_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_LIMIT +#define USB_DEV_SM_WATCHDOG_LIMIT_RESET _u(0x00000) +#define USB_DEV_SM_WATCHDOG_LIMIT_BITS _u(0x0003ffff) +#define USB_DEV_SM_WATCHDOG_LIMIT_MSB _u(17) +#define USB_DEV_SM_WATCHDOG_LIMIT_LSB _u(0) +#define USB_DEV_SM_WATCHDOG_LIMIT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_USB_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/usb_device_dpram.h b/src/rp2350/hardware_regs/include/hardware/regs/usb_device_dpram.h new file mode 100644 index 000000000..27203f4e1 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/usb_device_dpram.h @@ -0,0 +1,6753 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB_DEVICE_DPRAM +// Version : 1 +// Bus type : ahbl +// Description : DPRAM layout for USB device. +// ============================================================================= +#ifndef _HARDWARE_REGS_USB_DEVICE_DPRAM_H +#define _HARDWARE_REGS_USB_DEVICE_DPRAM_H +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW +// Description : Bytes 0-3 of the SETUP packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH +// Description : Bytes 4-7 of the setup packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_USB_DEVICE_DPRAM_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/watchdog.h b/src/rp2350/hardware_regs/include/hardware/regs/watchdog.h new file mode 100644 index 000000000..07e5b405e --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/watchdog.h @@ -0,0 +1,192 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : WATCHDOG +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_WATCHDOG_H +#define _HARDWARE_REGS_WATCHDOG_H +// ============================================================================= +// Register : WATCHDOG_CTRL +// Description : Watchdog control +// The rst_wdsel register determines which subsystems are reset +// when the watchdog is triggered. +// The watchdog can be triggered in software. +#define WATCHDOG_CTRL_OFFSET _u(0x00000000) +#define WATCHDOG_CTRL_BITS _u(0xc7ffffff) +#define WATCHDOG_CTRL_RESET _u(0x07000000) +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TRIGGER +// Description : Trigger a watchdog reset +#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0) +#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000) +#define WATCHDOG_CTRL_TRIGGER_MSB _u(31) +#define WATCHDOG_CTRL_TRIGGER_LSB _u(31) +#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_ENABLE +// Description : When not enabled the watchdog timer is paused +#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0) +#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000) +#define WATCHDOG_CTRL_ENABLE_MSB _u(30) +#define WATCHDOG_CTRL_ENABLE_LSB _u(30) +#define WATCHDOG_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG1 +// Description : Pause the watchdog timer when processor 1 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000) +#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26) +#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26) +#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG0 +// Description : Pause the watchdog timer when processor 0 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000) +#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25) +#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25) +#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_JTAG +// Description : Pause the watchdog timer when JTAG is accessing the bus fabric +#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000) +#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24) +#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24) +#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TIME +// Description : Indicates the time in usec before a watchdog reset will be +// triggered +#define WATCHDOG_CTRL_TIME_RESET _u(0x000000) +#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff) +#define WATCHDOG_CTRL_TIME_MSB _u(23) +#define WATCHDOG_CTRL_TIME_LSB _u(0) +#define WATCHDOG_CTRL_TIME_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_LOAD +// Description : Load the watchdog timer. The maximum setting is 0xffffff which +// corresponds to approximately 16 seconds. +#define WATCHDOG_LOAD_OFFSET _u(0x00000004) +#define WATCHDOG_LOAD_BITS _u(0x00ffffff) +#define WATCHDOG_LOAD_RESET _u(0x00000000) +#define WATCHDOG_LOAD_MSB _u(23) +#define WATCHDOG_LOAD_LSB _u(0) +#define WATCHDOG_LOAD_ACCESS "WF" +// ============================================================================= +// Register : WATCHDOG_REASON +// Description : Logs the reason for the last reset. Both bits are zero for the +// case of a hardware reset. +// +// Additionally, as of RP2350, a debugger warm reset of either +// core (SYSRESETREQ or hartreset) will also clear the watchdog +// reason register, so that software loaded under the debugger +// following a watchdog timeout will not continue to see the +// timeout condition. +#define WATCHDOG_REASON_OFFSET _u(0x00000008) +#define WATCHDOG_REASON_BITS _u(0x00000003) +#define WATCHDOG_REASON_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_FORCE +#define WATCHDOG_REASON_FORCE_RESET _u(0x0) +#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) +#define WATCHDOG_REASON_FORCE_MSB _u(1) +#define WATCHDOG_REASON_FORCE_LSB _u(1) +#define WATCHDOG_REASON_FORCE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_TIMER +#define WATCHDOG_REASON_TIMER_RESET _u(0x0) +#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) +#define WATCHDOG_REASON_TIMER_MSB _u(0) +#define WATCHDOG_REASON_TIMER_LSB _u(0) +#define WATCHDOG_REASON_TIMER_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_SCRATCH0 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c) +#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH0_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH0_MSB _u(31) +#define WATCHDOG_SCRATCH0_LSB _u(0) +#define WATCHDOG_SCRATCH0_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH1 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010) +#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH1_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH1_MSB _u(31) +#define WATCHDOG_SCRATCH1_LSB _u(0) +#define WATCHDOG_SCRATCH1_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH2 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014) +#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH2_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH2_MSB _u(31) +#define WATCHDOG_SCRATCH2_LSB _u(0) +#define WATCHDOG_SCRATCH2_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH3 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018) +#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH3_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH3_MSB _u(31) +#define WATCHDOG_SCRATCH3_LSB _u(0) +#define WATCHDOG_SCRATCH3_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH4 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c) +#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH4_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH4_MSB _u(31) +#define WATCHDOG_SCRATCH4_LSB _u(0) +#define WATCHDOG_SCRATCH4_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH5 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020) +#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH5_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH5_MSB _u(31) +#define WATCHDOG_SCRATCH5_LSB _u(0) +#define WATCHDOG_SCRATCH5_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH6 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024) +#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH6_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH6_MSB _u(31) +#define WATCHDOG_SCRATCH6_LSB _u(0) +#define WATCHDOG_SCRATCH6_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH7 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028) +#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH7_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH7_MSB _u(31) +#define WATCHDOG_SCRATCH7_LSB _u(0) +#define WATCHDOG_SCRATCH7_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_WATCHDOG_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/xip.h b/src/rp2350/hardware_regs/include/hardware/regs/xip.h new file mode 100644 index 000000000..7487ec63f --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/xip.h @@ -0,0 +1,313 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XIP +// Version : 1 +// Bus type : ahb +// Description : QSPI flash execute-in-place block +// ============================================================================= +#ifndef _HARDWARE_REGS_XIP_H +#define _HARDWARE_REGS_XIP_H +// ============================================================================= +// Register : XIP_CTRL +// Description : Cache control register. Read-only from a Non-secure context. +#define XIP_CTRL_OFFSET _u(0x00000000) +#define XIP_CTRL_BITS _u(0x00000ffb) +#define XIP_CTRL_RESET _u(0x00000083) +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_WRITABLE_M1 +// Description : If 1, enable writes to XIP memory window 1 (addresses +// 0x11000000 through 0x11ffffff, and their uncached mirrors). If +// 0, this region is read-only. +// +// XIP memory is *read-only by default*. This bit must be set to +// enable writes if a RAM device is attached on QSPI chip select +// 1. +// +// The default read-only behaviour avoids two issues with writing +// to a read-only QSPI device (e.g. flash). First, a write will +// initially appear to succeed due to caching, but the data will +// eventually be lost when the written line is evicted, causing +// unpredictable behaviour. +// +// Second, when a written line is evicted, it will cause a write +// command to be issued to the flash, which can break the flash +// out of its continuous read mode. After this point, flash reads +// will return garbage. This is a security concern, as it allows +// Non-secure software to break Secure flash reads if it has +// permission to write to any flash address. +// +// Note the read-only behaviour is implemented by downgrading +// writes to reads, so writes will still cause allocation of an +// address, but have no other effect. +#define XIP_CTRL_WRITABLE_M1_RESET _u(0x0) +#define XIP_CTRL_WRITABLE_M1_BITS _u(0x00000800) +#define XIP_CTRL_WRITABLE_M1_MSB _u(11) +#define XIP_CTRL_WRITABLE_M1_LSB _u(11) +#define XIP_CTRL_WRITABLE_M1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_WRITABLE_M0 +// Description : If 1, enable writes to XIP memory window 0 (addresses +// 0x10000000 through 0x10ffffff, and their uncached mirrors). If +// 0, this region is read-only. +// +// XIP memory is *read-only by default*. This bit must be set to +// enable writes if a RAM device is attached on QSPI chip select +// 0. +// +// The default read-only behaviour avoids two issues with writing +// to a read-only QSPI device (e.g. flash). First, a write will +// initially appear to succeed due to caching, but the data will +// eventually be lost when the written line is evicted, causing +// unpredictable behaviour. +// +// Second, when a written line is evicted, it will cause a write +// command to be issued to the flash, which can break the flash +// out of its continuous read mode. After this point, flash reads +// will return garbage. This is a security concern, as it allows +// Non-secure software to break Secure flash reads if it has +// permission to write to any flash address. +// +// Note the read-only behaviour is implemented by downgrading +// writes to reads, so writes will still cause allocation of an +// address, but have no other effect. +#define XIP_CTRL_WRITABLE_M0_RESET _u(0x0) +#define XIP_CTRL_WRITABLE_M0_BITS _u(0x00000400) +#define XIP_CTRL_WRITABLE_M0_MSB _u(10) +#define XIP_CTRL_WRITABLE_M0_LSB _u(10) +#define XIP_CTRL_WRITABLE_M0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_SPLIT_WAYS +// Description : When 1, route all cached+Secure accesses to way 0 of the cache, +// and route all cached+Non-secure accesses to way 1 of the cache. +// +// This partitions the cache into two half-sized direct-mapped +// regions, such that Non-secure code can not observe cache line +// state changes caused by Secure execution. +// +// A full cache flush is required when changing the value of +// SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is +// 0, so that both cache ways are accessible for invalidation. +#define XIP_CTRL_SPLIT_WAYS_RESET _u(0x0) +#define XIP_CTRL_SPLIT_WAYS_BITS _u(0x00000200) +#define XIP_CTRL_SPLIT_WAYS_MSB _u(9) +#define XIP_CTRL_SPLIT_WAYS_LSB _u(9) +#define XIP_CTRL_SPLIT_WAYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_MAINT_NONSEC +// Description : When 0, Non-secure accesses to the cache maintenance address +// window (addr[27] == 1, addr[26] == 0) will generate a bus +// error. When 1, Non-secure accesses can perform cache +// maintenance operations by writing to the cache maintenance +// address window. +// +// Cache maintenance operations may be used to corrupt Secure data +// by invalidating cache lines inappropriately, or map Secure +// content into a Non-secure region by pinning cache lines. +// Therefore this bit should generally be set to 0, unless Secure +// code is not using the cache. +// +// Care should also be taken to clear the cache data memory and +// tag memory before granting maintenance operations to Non-secure +// code. +#define XIP_CTRL_MAINT_NONSEC_RESET _u(0x0) +#define XIP_CTRL_MAINT_NONSEC_BITS _u(0x00000100) +#define XIP_CTRL_MAINT_NONSEC_MSB _u(8) +#define XIP_CTRL_MAINT_NONSEC_LSB _u(8) +#define XIP_CTRL_MAINT_NONSEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNTRANSLATED_NONSEC +// Description : When 1, Non-secure accesses to the uncached, untranslated +// window (addr[27:26] == 3) will generate a bus error. +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_RESET _u(0x1) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_BITS _u(0x00000080) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_MSB _u(7) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_LSB _u(7) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNTRANSLATED_SEC +// Description : When 1, Secure accesses to the uncached, untranslated window +// (addr[27:26] == 3) will generate a bus error. +#define XIP_CTRL_NO_UNTRANSLATED_SEC_RESET _u(0x0) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_BITS _u(0x00000040) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_MSB _u(6) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_LSB _u(6) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNCACHED_NONSEC +// Description : When 1, Non-secure accesses to the uncached window (addr[27:26] +// == 1) will generate a bus error. This may reduce the number of +// SAU/MPU/PMP regions required to protect flash contents. +// +// Note this does not disable access to the uncached, untranslated +// window -- see NO_UNTRANSLATED_SEC. +#define XIP_CTRL_NO_UNCACHED_NONSEC_RESET _u(0x0) +#define XIP_CTRL_NO_UNCACHED_NONSEC_BITS _u(0x00000020) +#define XIP_CTRL_NO_UNCACHED_NONSEC_MSB _u(5) +#define XIP_CTRL_NO_UNCACHED_NONSEC_LSB _u(5) +#define XIP_CTRL_NO_UNCACHED_NONSEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNCACHED_SEC +// Description : When 1, Secure accesses to the uncached window (addr[27:26] == +// 1) will generate a bus error. This may reduce the number of +// SAU/MPU/PMP regions required to protect flash contents. +// +// Note this does not disable access to the uncached, untranslated +// window -- see NO_UNTRANSLATED_SEC. +#define XIP_CTRL_NO_UNCACHED_SEC_RESET _u(0x0) +#define XIP_CTRL_NO_UNCACHED_SEC_BITS _u(0x00000010) +#define XIP_CTRL_NO_UNCACHED_SEC_MSB _u(4) +#define XIP_CTRL_NO_UNCACHED_SEC_LSB _u(4) +#define XIP_CTRL_NO_UNCACHED_SEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_POWER_DOWN +// Description : When 1, the cache memories are powered down. They retain state, +// but can not be accessed. This reduces static power dissipation. +// Writing 1 to this bit forces CTRL_EN_SECURE and +// CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when +// powered down. +#define XIP_CTRL_POWER_DOWN_RESET _u(0x0) +#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008) +#define XIP_CTRL_POWER_DOWN_MSB _u(3) +#define XIP_CTRL_POWER_DOWN_LSB _u(3) +#define XIP_CTRL_POWER_DOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_EN_NONSECURE +// Description : When 1, enable the cache for Non-secure accesses. When enabled, +// Non-secure XIP accesses to the cached (addr[26] == 0) window +// will query the cache, and QSPI accesses are performed only if +// the requested data is not present. When disabled, Secure access +// ignore the cache contents, and always access the QSPI +// interface. +// +// Accesses to the uncached (addr[26] == 1) window will never +// query the cache, irrespective of this bit. +#define XIP_CTRL_EN_NONSECURE_RESET _u(0x1) +#define XIP_CTRL_EN_NONSECURE_BITS _u(0x00000002) +#define XIP_CTRL_EN_NONSECURE_MSB _u(1) +#define XIP_CTRL_EN_NONSECURE_LSB _u(1) +#define XIP_CTRL_EN_NONSECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_EN_SECURE +// Description : When 1, enable the cache for Secure accesses. When enabled, +// Secure XIP accesses to the cached (addr[26] == 0) window will +// query the cache, and QSPI accesses are performed only if the +// requested data is not present. When disabled, Secure access +// ignore the cache contents, and always access the QSPI +// interface. +// +// Accesses to the uncached (addr[26] == 1) window will never +// query the cache, irrespective of this bit. +// +// There is no cache-as-SRAM address window. Cache lines are +// allocated for SRAM-like use by individually pinning them, and +// keeping the cache enabled. +#define XIP_CTRL_EN_SECURE_RESET _u(0x1) +#define XIP_CTRL_EN_SECURE_BITS _u(0x00000001) +#define XIP_CTRL_EN_SECURE_MSB _u(0) +#define XIP_CTRL_EN_SECURE_LSB _u(0) +#define XIP_CTRL_EN_SECURE_ACCESS "RW" +// ============================================================================= +// Register : XIP_STAT +#define XIP_STAT_OFFSET _u(0x00000008) +#define XIP_STAT_BITS _u(0x00000006) +#define XIP_STAT_RESET _u(0x00000002) +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_FULL +// Description : When 1, indicates the XIP streaming FIFO is completely full. +// The streaming FIFO is 2 entries deep, so the full and empty +// flag allow its level to be ascertained. +#define XIP_STAT_FIFO_FULL_RESET _u(0x0) +#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004) +#define XIP_STAT_FIFO_FULL_MSB _u(2) +#define XIP_STAT_FIFO_FULL_LSB _u(2) +#define XIP_STAT_FIFO_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_EMPTY +// Description : When 1, indicates the XIP streaming FIFO is completely empty. +#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1) +#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002) +#define XIP_STAT_FIFO_EMPTY_MSB _u(1) +#define XIP_STAT_FIFO_EMPTY_LSB _u(1) +#define XIP_STAT_FIFO_EMPTY_ACCESS "RO" +// ============================================================================= +// Register : XIP_CTR_HIT +// Description : Cache Hit counter +// A 32 bit saturating counter that increments upon each cache +// hit, +// i.e. when an XIP access is serviced directly from cached data. +// Write any value to clear. +#define XIP_CTR_HIT_OFFSET _u(0x0000000c) +#define XIP_CTR_HIT_BITS _u(0xffffffff) +#define XIP_CTR_HIT_RESET _u(0x00000000) +#define XIP_CTR_HIT_MSB _u(31) +#define XIP_CTR_HIT_LSB _u(0) +#define XIP_CTR_HIT_ACCESS "WC" +// ============================================================================= +// Register : XIP_CTR_ACC +// Description : Cache Access counter +// A 32 bit saturating counter that increments upon each XIP +// access, +// whether the cache is hit or not. This includes noncacheable +// accesses. +// Write any value to clear. +#define XIP_CTR_ACC_OFFSET _u(0x00000010) +#define XIP_CTR_ACC_BITS _u(0xffffffff) +#define XIP_CTR_ACC_RESET _u(0x00000000) +#define XIP_CTR_ACC_MSB _u(31) +#define XIP_CTR_ACC_LSB _u(0) +#define XIP_CTR_ACC_ACCESS "WC" +// ============================================================================= +// Register : XIP_STREAM_ADDR +// Description : FIFO stream address +// The address of the next word to be streamed from flash to the +// streaming FIFO. +// Increments automatically after each flash access. +// Write the initial access address here before starting a +// streaming read. +#define XIP_STREAM_ADDR_OFFSET _u(0x00000014) +#define XIP_STREAM_ADDR_BITS _u(0xfffffffc) +#define XIP_STREAM_ADDR_RESET _u(0x00000000) +#define XIP_STREAM_ADDR_MSB _u(31) +#define XIP_STREAM_ADDR_LSB _u(2) +#define XIP_STREAM_ADDR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_CTR +// Description : FIFO stream control +// Write a nonzero value to start a streaming read. This will then +// progress in the background, using flash idle cycles to transfer +// a linear data block from flash to the streaming FIFO. +// Decrements automatically (1 at a time) as the stream +// progresses, and halts on reaching 0. +// Write 0 to halt an in-progress stream, and discard any in- +// flight +// read, so that a new stream can immediately be started (after +// draining the FIFO and reinitialising STREAM_ADDR) +#define XIP_STREAM_CTR_OFFSET _u(0x00000018) +#define XIP_STREAM_CTR_BITS _u(0x003fffff) +#define XIP_STREAM_CTR_RESET _u(0x00000000) +#define XIP_STREAM_CTR_MSB _u(21) +#define XIP_STREAM_CTR_LSB _u(0) +#define XIP_STREAM_CTR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_FIFO +// Description : FIFO stream data +// Streamed data is buffered here, for retrieval by the system +// DMA. +// This FIFO can also be accessed via the XIP_AUX slave, to avoid +// exposing +// the DMA to bus stalls caused by other XIP traffic. +#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c) +#define XIP_STREAM_FIFO_BITS _u(0xffffffff) +#define XIP_STREAM_FIFO_RESET _u(0x00000000) +#define XIP_STREAM_FIFO_MSB _u(31) +#define XIP_STREAM_FIFO_LSB _u(0) +#define XIP_STREAM_FIFO_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_XIP_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/xip_aux.h b/src/rp2350/hardware_regs/include/hardware/regs/xip_aux.h new file mode 100644 index 000000000..07940ca44 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/xip_aux.h @@ -0,0 +1,123 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XIP_AUX +// Version : 1 +// Bus type : ahb +// Description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access +// ============================================================================= +#ifndef _HARDWARE_REGS_XIP_AUX_H +#define _HARDWARE_REGS_XIP_AUX_H +// ============================================================================= +// Register : XIP_AUX_STREAM +// Description : Read the XIP stream FIFO (fast bus access to +// XIP_CTRL_STREAM_FIFO) +#define XIP_AUX_STREAM_OFFSET _u(0x00000000) +#define XIP_AUX_STREAM_BITS _u(0xffffffff) +#define XIP_AUX_STREAM_RESET _u(0x00000000) +#define XIP_AUX_STREAM_MSB _u(31) +#define XIP_AUX_STREAM_LSB _u(0) +#define XIP_AUX_STREAM_ACCESS "RF" +// ============================================================================= +// Register : XIP_AUX_QMI_DIRECT_TX +// Description : Write to the QMI direct-mode TX FIFO (fast bus access to +// QMI_DIRECT_TX) +#define XIP_AUX_QMI_DIRECT_TX_OFFSET _u(0x00000004) +#define XIP_AUX_QMI_DIRECT_TX_BITS _u(0x001fffff) +#define XIP_AUX_QMI_DIRECT_TX_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_NOPUSH +// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO +// entry. +// +// Useful to avoid garbage appearing in the RX FIFO when pushing +// the command at the beginning of a SPI transfer. +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_MSB _u(20) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_LSB _u(20) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_OE +// Description : Output enable (active-high). For single width (SPI), this field +// is ignored, and SD0 is always set to output, with SD1 always +// set to input. +// +// For dual and quad width (DSPI/QSPI), this sets whether the +// relevant SDx pads are set to output whilst transferring this +// FIFO record. In this case the command/address should have OE +// set, and the data transfer should have OE set or clear +// depending on the direction of the transfer. +#define XIP_AUX_QMI_DIRECT_TX_OE_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_OE_BITS _u(0x00080000) +#define XIP_AUX_QMI_DIRECT_TX_OE_MSB _u(19) +#define XIP_AUX_QMI_DIRECT_TX_OE_LSB _u(19) +#define XIP_AUX_QMI_DIRECT_TX_OE_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_DWIDTH +// Description : Data width. If 0, hardware will transmit the 8 LSBs of the +// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs +// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and +// 16-bit transfers can be mixed freely. +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_MSB _u(18) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_LSB _u(18) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_IWIDTH +// Description : Configure whether this FIFO record is transferred with +// single/dual/quad interface width (0/1/2). Different widths can +// be mixed freely. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_MSB _u(17) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_LSB _u(16) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_ACCESS "WF" +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_DATA +// Description : Data pushed here will be clocked out falling edges of SCK (or +// before the very first rising edge of SCK, if this is the first +// pulse). For each byte clocked out, the interface will +// simultaneously sample one byte, on rising edges of SCK, and +// push this to the DIRECT_RX FIFO. +// +// For 16-bit data, the least-significant byte is transmitted +// first. +#define XIP_AUX_QMI_DIRECT_TX_DATA_RESET _u(0x0000) +#define XIP_AUX_QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff) +#define XIP_AUX_QMI_DIRECT_TX_DATA_MSB _u(15) +#define XIP_AUX_QMI_DIRECT_TX_DATA_LSB _u(0) +#define XIP_AUX_QMI_DIRECT_TX_DATA_ACCESS "WF" +// ============================================================================= +// Register : XIP_AUX_QMI_DIRECT_RX +// Description : Read from the QMI direct-mode RX FIFO (fast bus access to +// QMI_DIRECT_RX) +// With each byte clocked out on the serial interface, one byte +// will simultaneously be clocked in, and will appear in this +// FIFO. The serial interface will stall when this FIFO is full, +// to avoid dropping data. +// +// When 16-bit data is pushed into the TX FIFO, the corresponding +// RX FIFO push will also contain 16 bits of data. The least- +// significant byte is the first one received. +#define XIP_AUX_QMI_DIRECT_RX_OFFSET _u(0x00000008) +#define XIP_AUX_QMI_DIRECT_RX_BITS _u(0x0000ffff) +#define XIP_AUX_QMI_DIRECT_RX_RESET _u(0x00000000) +#define XIP_AUX_QMI_DIRECT_RX_MSB _u(15) +#define XIP_AUX_QMI_DIRECT_RX_LSB _u(0) +#define XIP_AUX_QMI_DIRECT_RX_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_XIP_AUX_H + diff --git a/src/rp2350/hardware_regs/include/hardware/regs/xosc.h b/src/rp2350/hardware_regs/include/hardware/regs/xosc.h new file mode 100644 index 000000000..782c30ca1 --- /dev/null +++ b/src/rp2350/hardware_regs/include/hardware/regs/xosc.h @@ -0,0 +1,175 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XOSC +// Version : 1 +// Bus type : apb +// Description : Controls the crystal oscillator +// ============================================================================= +#ifndef _HARDWARE_REGS_XOSC_H +#define _HARDWARE_REGS_XOSC_H +// ============================================================================= +// Register : XOSC_CTRL +// Description : Crystal Oscillator Control +#define XOSC_CTRL_OFFSET _u(0x00000000) +#define XOSC_CTRL_BITS _u(0x00ffffff) +#define XOSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_ENABLE +// Description : On power-up this field is initialised to DISABLE and the chip +// runs from the ROSC. +// If the chip has subsequently been programmed to run from the +// XOSC then setting this field to DISABLE may lock-up the chip. +// If this is a concern then run the clk_ref from the ROSC and +// enable the clk_sys RESUS feature. +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will retain the previous +// value. The actual value being used can be read from +// STATUS_ENABLED +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define XOSC_CTRL_ENABLE_RESET "-" +#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define XOSC_CTRL_ENABLE_MSB _u(23) +#define XOSC_CTRL_ENABLE_LSB _u(12) +#define XOSC_CTRL_ENABLE_ACCESS "RW" +#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_FREQ_RANGE +// Description : The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will retain the previous +// value. The actual value being used can be read from +// STATUS_FREQ_RANGE +// 0xaa0 -> 1_15MHZ +// 0xaa1 -> 10_30MHZ +// 0xaa2 -> 25_60MHZ +// 0xaa3 -> 40_100MHZ +#define XOSC_CTRL_FREQ_RANGE_RESET "-" +#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) +#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) +#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) +#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ _u(0xaa1) +#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ _u(0xaa2) +#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ _u(0xaa3) +// ============================================================================= +// Register : XOSC_STATUS +// Description : Crystal Oscillator Status +#define XOSC_STATUS_OFFSET _u(0x00000004) +#define XOSC_STATUS_BITS _u(0x81001003) +#define XOSC_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define XOSC_STATUS_STABLE_RESET _u(0x0) +#define XOSC_STATUS_STABLE_BITS _u(0x80000000) +#define XOSC_STATUS_STABLE_MSB _u(31) +#define XOSC_STATUS_STABLE_LSB _u(31) +#define XOSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or DORMANT +#define XOSC_STATUS_BADWRITE_RESET _u(0x0) +#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define XOSC_STATUS_BADWRITE_MSB _u(24) +#define XOSC_STATUS_BADWRITE_LSB _u(24) +#define XOSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable, +// resets to 0 +#define XOSC_STATUS_ENABLED_RESET "-" +#define XOSC_STATUS_ENABLED_BITS _u(0x00001000) +#define XOSC_STATUS_ENABLED_MSB _u(12) +#define XOSC_STATUS_ENABLED_LSB _u(12) +#define XOSC_STATUS_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_FREQ_RANGE +// Description : The current frequency range setting +// 0x0 -> 1_15MHZ +// 0x1 -> 10_30MHZ +// 0x2 -> 25_60MHZ +// 0x3 -> 40_100MHZ +#define XOSC_STATUS_FREQ_RANGE_RESET "-" +#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) +#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) +#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) +#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) +#define XOSC_STATUS_FREQ_RANGE_VALUE_10_30MHZ _u(0x1) +#define XOSC_STATUS_FREQ_RANGE_VALUE_25_60MHZ _u(0x2) +#define XOSC_STATUS_FREQ_RANGE_VALUE_40_100MHZ _u(0x3) +// ============================================================================= +// Register : XOSC_DORMANT +// Description : Crystal Oscillator pause control +// This is used to save power by pausing the XOSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// Warning: stop the PLLs before selecting dormant mode +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> dormant +// 0x77616b65 -> WAKE +#define XOSC_DORMANT_OFFSET _u(0x00000008) +#define XOSC_DORMANT_BITS _u(0xffffffff) +#define XOSC_DORMANT_RESET "-" +#define XOSC_DORMANT_MSB _u(31) +#define XOSC_DORMANT_LSB _u(0) +#define XOSC_DORMANT_ACCESS "RW" +#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) +// ============================================================================= +// Register : XOSC_STARTUP +// Description : Controls the startup delay +#define XOSC_STARTUP_OFFSET _u(0x0000000c) +#define XOSC_STARTUP_BITS _u(0x00103fff) +#define XOSC_STARTUP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_X4 +// Description : Multiplies the startup_delay by 4, just in case. The reset +// value is controlled by a mask-programmable tiecell and is +// provided in case we are booting from XOSC and the default +// startup delay is insufficient. The reset value is 0x0. +#define XOSC_STARTUP_X4_RESET "-" +#define XOSC_STARTUP_X4_BITS _u(0x00100000) +#define XOSC_STARTUP_X4_MSB _u(20) +#define XOSC_STARTUP_X4_LSB _u(20) +#define XOSC_STARTUP_X4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_DELAY +// Description : in multiples of 256*xtal_period. The reset value of 0xc4 +// corresponds to approx 50 000 cycles. +#define XOSC_STARTUP_DELAY_RESET "-" +#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) +#define XOSC_STARTUP_DELAY_MSB _u(13) +#define XOSC_STARTUP_DELAY_LSB _u(0) +#define XOSC_STARTUP_DELAY_ACCESS "RW" +// ============================================================================= +// Register : XOSC_COUNT +// Description : A down counter running at the xosc frequency which counts to +// zero and stops. +// Can be used for short software pauses when setting up time +// sensitive hardware. +// To start the counter, write a non-zero value. Reads will return +// 1 while the count is running and 0 when it has finished. +// Minimum count value is 4. Count values <4 will be treated as +// count value =4. +// Note that synchronisation to the register clock domain costs 2 +// register clock cycles and the counter cannot compensate for +// that. +#define XOSC_COUNT_OFFSET _u(0x00000010) +#define XOSC_COUNT_BITS _u(0x0000ffff) +#define XOSC_COUNT_RESET _u(0x00000000) +#define XOSC_COUNT_MSB _u(15) +#define XOSC_COUNT_LSB _u(0) +#define XOSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_XOSC_H + diff --git a/src/rp2350/hardware_structs/BUILD.bazel b/src/rp2350/hardware_structs/BUILD.bazel new file mode 100644 index 000000000..518cab219 --- /dev/null +++ b/src/rp2350/hardware_structs/BUILD.bazel @@ -0,0 +1,72 @@ +# Always include these libraries through //src/rp2_common:*! +# This ensures that you'll get the right headers for the MCU you're targeting. + +package( + default_visibility = [ + "//src/rp2350:__subpackages__", + "//src/rp2_common:__pkg__", + ], +) + +cc_library( + name = "hardware_structs", + hdrs = [ + "include/hardware/structs/accessctrl.h", + "include/hardware/structs/adc.h", + "include/hardware/structs/bootram.h", + "include/hardware/structs/bus_ctrl.h", + "include/hardware/structs/busctrl.h", + "include/hardware/structs/clocks.h", + "include/hardware/structs/coresight_trace.h", + "include/hardware/structs/dma.h", + "include/hardware/structs/dma_debug.h", + "include/hardware/structs/glitch_detector.h", + "include/hardware/structs/hstx_ctrl.h", + "include/hardware/structs/hstx_fifo.h", + "include/hardware/structs/i2c.h", + "include/hardware/structs/interp.h", + "include/hardware/structs/io_bank0.h", + "include/hardware/structs/io_qspi.h", + "include/hardware/structs/iobank0.h", + "include/hardware/structs/ioqspi.h", + "include/hardware/structs/m33.h", + "include/hardware/structs/m33_eppb.h", + "include/hardware/structs/mpu.h", + "include/hardware/structs/nvic.h", + "include/hardware/structs/otp.h", + "include/hardware/structs/pads_bank0.h", + "include/hardware/structs/pads_qspi.h", + "include/hardware/structs/padsbank0.h", + "include/hardware/structs/pio.h", + "include/hardware/structs/pll.h", + "include/hardware/structs/powman.h", + "include/hardware/structs/psm.h", + "include/hardware/structs/pwm.h", + "include/hardware/structs/qmi.h", + "include/hardware/structs/resets.h", + "include/hardware/structs/rosc.h", + "include/hardware/structs/sau.h", + "include/hardware/structs/scb.h", + "include/hardware/structs/sha256.h", + "include/hardware/structs/sio.h", + "include/hardware/structs/spi.h", + "include/hardware/structs/syscfg.h", + "include/hardware/structs/sysinfo.h", + "include/hardware/structs/systick.h", + "include/hardware/structs/tbman.h", + "include/hardware/structs/ticks.h", + "include/hardware/structs/timer.h", + "include/hardware/structs/tmds_encode.h", + "include/hardware/structs/trng.h", + "include/hardware/structs/uart.h", + "include/hardware/structs/usb.h", + "include/hardware/structs/usb_dpram.h", + "include/hardware/structs/watchdog.h", + "include/hardware/structs/xip.h", + "include/hardware/structs/xip_aux.h", + "include/hardware/structs/xip_ctrl.h", + "include/hardware/structs/xosc.h", + ], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:rp2350"], +) diff --git a/src/rp2350/hardware_structs/CMakeLists.txt b/src/rp2350/hardware_structs/CMakeLists.txt new file mode 100644 index 000000000..39432130d --- /dev/null +++ b/src/rp2350/hardware_structs/CMakeLists.txt @@ -0,0 +1,4 @@ +add_library(hardware_structs INTERFACE) +add_library(hardware_structs_headers INTERFACE) +target_include_directories(hardware_structs_headers SYSTEM INTERFACE include) +pico_mirrored_target_link_libraries(hardware_structs INTERFACE hardware_regs) diff --git a/src/rp2350/hardware_structs/include/hardware/structs/accessctrl.h b/src/rp2350/hardware_structs/include/hardware/structs/accessctrl.h new file mode 100644 index 000000000..5fd30cb2d --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/accessctrl.h @@ -0,0 +1,519 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ACCESSCTRL_H +#define _HARDWARE_STRUCTS_ACCESSCTRL_H + +/** + * \file rp2350/accessctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/accessctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_accessctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/accessctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ACCESSCTRL_LOCK_OFFSET) // ACCESSCTRL_LOCK + // Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master + // 0x00000008 [3] DEBUG (0) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] CORE1 (0) + // 0x00000001 [0] CORE0 (0) + io_rw_32 lock; + + _REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) // ACCESSCTRL_FORCE_CORE_NS + // Force core 1's bus accesses to always be Non-secure, no matter the core's internal state + // 0x00000002 [1] CORE1 (0) + io_rw_32 force_core_ns; + + _REG_(ACCESSCTRL_CFGRESET_OFFSET) // ACCESSCTRL_CFGRESET + // Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers + // 0x00000001 [0] CFGRESET (0) + io_wo_32 cfgreset; + + // (Description copied from array index 0 register ACCESSCTRL_GPIO_NSMASK0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) // ACCESSCTRL_GPIO_NSMASK0 + // Control whether GPIO0 + // 0xffffffff [31:0] GPIO_NSMASK0 (0x00000000) + io_rw_32 gpio_nsmask[2]; + + _REG_(ACCESSCTRL_ROM_OFFSET) // ACCESSCTRL_ROM + // Control access to ROM. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, ROM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, ROM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ROM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ROM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ROM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, ROM can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, ROM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, ROM can be accessed from a... + io_rw_32 rom; + + _REG_(ACCESSCTRL_XIP_MAIN_OFFSET) // ACCESSCTRL_XIP_MAIN + // Control access to XIP_MAIN. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, XIP_MAIN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, XIP_MAIN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_MAIN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_MAIN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_MAIN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, XIP_MAIN can be accessed from... + // 0x00000002 [1] NSP (1) If 1, XIP_MAIN can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, XIP_MAIN can be accessed from... + io_rw_32 xip_main; + + // (Description copied from array index 0 register ACCESSCTRL_SRAM0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_SRAM0_OFFSET) // ACCESSCTRL_SRAM0 + // Control access to SRAM0. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, SRAM0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SRAM0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SRAM0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SRAM0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SRAM0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SRAM0 can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, SRAM0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SRAM0 can be accessed from a... + io_rw_32 sram[10]; + + _REG_(ACCESSCTRL_DMA_OFFSET) // ACCESSCTRL_DMA + // Control access to DMA. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, DMA can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, DMA can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, DMA can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, DMA can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, DMA can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, DMA can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, DMA can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, DMA can be accessed from a... + io_rw_32 dma; + + _REG_(ACCESSCTRL_USBCTRL_OFFSET) // ACCESSCTRL_USBCTRL + // Control access to USBCTRL. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, USBCTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, USBCTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, USBCTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, USBCTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, USBCTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, USBCTRL can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, USBCTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, USBCTRL can be accessed from... + io_rw_32 usbctrl; + + // (Description copied from array index 0 register ACCESSCTRL_PIO0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_PIO0_OFFSET) // ACCESSCTRL_PIO0 + // Control access to PIO0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PIO0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PIO0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PIO0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PIO0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PIO0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PIO0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PIO0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PIO0 can be accessed from a... + io_rw_32 pio[3]; + + _REG_(ACCESSCTRL_CORESIGHT_TRACE_OFFSET) // ACCESSCTRL_CORESIGHT_TRACE + // Control access to CORESIGHT_TRACE. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CORESIGHT_TRACE can be accessed by the debugger,... + // 0x00000040 [6] DMA (0) If 1, CORESIGHT_TRACE can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_TRACE can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_TRACE can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CORESIGHT_TRACE can be accessed from a Secure,... + // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_TRACE can be... + // 0x00000002 [1] NSP (0) If 1, CORESIGHT_TRACE can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_TRACE can be... + io_rw_32 coresight_trace; + + _REG_(ACCESSCTRL_CORESIGHT_PERIPH_OFFSET) // ACCESSCTRL_CORESIGHT_PERIPH + // Control access to CORESIGHT_PERIPH. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CORESIGHT_PERIPH can be accessed by the debugger,... + // 0x00000040 [6] DMA (0) If 1, CORESIGHT_PERIPH can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_PERIPH can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_PERIPH can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CORESIGHT_PERIPH can be accessed from a Secure,... + // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_PERIPH can be... + // 0x00000002 [1] NSP (0) If 1, CORESIGHT_PERIPH can be accessed from a... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_PERIPH can be... + io_rw_32 coresight_periph; + + _REG_(ACCESSCTRL_SYSINFO_OFFSET) // ACCESSCTRL_SYSINFO + // Control access to SYSINFO. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, SYSINFO can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SYSINFO can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SYSINFO can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SYSINFO can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SYSINFO can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SYSINFO can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, SYSINFO can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SYSINFO can be accessed from... + io_rw_32 sysinfo; + + _REG_(ACCESSCTRL_RESETS_OFFSET) // ACCESSCTRL_RESETS + // Control access to RESETS. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, RESETS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, RESETS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, RESETS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, RESETS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, RESETS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, RESETS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, RESETS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RESETS can be accessed from a... + io_rw_32 resets; + + // (Description copied from array index 0 register ACCESSCTRL_IO_BANK0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_IO_BANK0_OFFSET) // ACCESSCTRL_IO_BANK0 + // Control access to IO_BANK0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, IO_BANK0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, IO_BANK0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, IO_BANK0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, IO_BANK0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, IO_BANK0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, IO_BANK0 can be accessed from... + // 0x00000002 [1] NSP (0) If 1, IO_BANK0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, IO_BANK0 can be accessed from... + io_rw_32 io_bank[2]; + + _REG_(ACCESSCTRL_PADS_BANK0_OFFSET) // ACCESSCTRL_PADS_BANK0 + // Control access to PADS_BANK0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PADS_BANK0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PADS_BANK0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PADS_BANK0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PADS_BANK0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PADS_BANK0 can be accessed from a Secure,... + // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_BANK0 can be accessed... + // 0x00000002 [1] NSP (0) If 1, PADS_BANK0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_BANK0 can be accessed... + io_rw_32 pads_bank0; + + _REG_(ACCESSCTRL_PADS_QSPI_OFFSET) // ACCESSCTRL_PADS_QSPI + // Control access to PADS_QSPI. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PADS_QSPI can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PADS_QSPI can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PADS_QSPI can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PADS_QSPI can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PADS_QSPI can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_QSPI can be accessed from... + // 0x00000002 [1] NSP (0) If 1, PADS_QSPI can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_QSPI can be accessed... + io_rw_32 pads_qspi; + + _REG_(ACCESSCTRL_BUSCTRL_OFFSET) // ACCESSCTRL_BUSCTRL + // Control access to BUSCTRL. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, BUSCTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, BUSCTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, BUSCTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, BUSCTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, BUSCTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, BUSCTRL can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, BUSCTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, BUSCTRL can be accessed from... + io_rw_32 busctrl; + + _REG_(ACCESSCTRL_ADC0_OFFSET) // ACCESSCTRL_ADC0 + // Control access to ADC0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, ADC0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, ADC0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ADC0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ADC0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ADC0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, ADC0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC0 can be accessed from a... + io_rw_32 adc0; + + _REG_(ACCESSCTRL_HSTX_OFFSET) // ACCESSCTRL_HSTX + // Control access to HSTX. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, HSTX can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, HSTX can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, HSTX can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, HSTX can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, HSTX can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, HSTX can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, HSTX can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, HSTX can be accessed from a... + io_rw_32 hstx; + + // (Description copied from array index 0 register ACCESSCTRL_I2C0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_I2C0_OFFSET) // ACCESSCTRL_I2C0 + // Control access to I2C0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, I2C0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, I2C0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, I2C0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, I2C0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, I2C0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, I2C0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, I2C0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, I2C0 can be accessed from a... + io_rw_32 i2c[2]; + + _REG_(ACCESSCTRL_PWM_OFFSET) // ACCESSCTRL_PWM + // Control access to PWM. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PWM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PWM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PWM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PWM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PWM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PWM can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PWM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PWM can be accessed from a... + io_rw_32 pwm; + + // (Description copied from array index 0 register ACCESSCTRL_SPI0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_SPI0_OFFSET) // ACCESSCTRL_SPI0 + // Control access to SPI0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, SPI0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SPI0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SPI0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SPI0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SPI0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SPI0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SPI0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SPI0 can be accessed from a... + io_rw_32 spi[2]; + + // (Description copied from array index 0 register ACCESSCTRL_TIMER0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_TIMER0_OFFSET) // ACCESSCTRL_TIMER0 + // Control access to TIMER0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, TIMER0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, TIMER0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TIMER0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TIMER0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TIMER0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, TIMER0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TIMER0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TIMER0 can be accessed from a... + io_rw_32 timer[2]; + + // (Description copied from array index 0 register ACCESSCTRL_UART0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_UART0_OFFSET) // ACCESSCTRL_UART0 + // Control access to UART0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, UART0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, UART0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, UART0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, UART0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, UART0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, UART0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, UART0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, UART0 can be accessed from a... + io_rw_32 uart[2]; + + _REG_(ACCESSCTRL_OTP_OFFSET) // ACCESSCTRL_OTP + // Control access to OTP. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, OTP can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, OTP can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, OTP can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, OTP can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, OTP can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, OTP can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, OTP can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, OTP can be accessed from a... + io_rw_32 otp; + + _REG_(ACCESSCTRL_TBMAN_OFFSET) // ACCESSCTRL_TBMAN + // Control access to TBMAN. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, TBMAN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, TBMAN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TBMAN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TBMAN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TBMAN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, TBMAN can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TBMAN can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TBMAN can be accessed from a... + io_rw_32 tbman; + + _REG_(ACCESSCTRL_POWMAN_OFFSET) // ACCESSCTRL_POWMAN + // Control access to POWMAN. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, POWMAN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, POWMAN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, POWMAN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, POWMAN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, POWMAN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, POWMAN can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, POWMAN can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, POWMAN can be accessed from a... + io_rw_32 powman; + + _REG_(ACCESSCTRL_TRNG_OFFSET) // ACCESSCTRL_TRNG + // Control access to TRNG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, TRNG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, TRNG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TRNG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TRNG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TRNG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, TRNG can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TRNG can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TRNG can be accessed from a... + io_rw_32 trng; + + _REG_(ACCESSCTRL_SHA256_OFFSET) // ACCESSCTRL_SHA256 + // Control access to SHA256. Defaults to Secure, Privileged access only. + // 0x00000080 [7] DBG (1) If 1, SHA256 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SHA256 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SHA256 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SHA256 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SHA256 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, SHA256 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SHA256 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SHA256 can be accessed from a... + io_rw_32 sha256; + + _REG_(ACCESSCTRL_SYSCFG_OFFSET) // ACCESSCTRL_SYSCFG + // Control access to SYSCFG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, SYSCFG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, SYSCFG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SYSCFG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SYSCFG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SYSCFG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, SYSCFG can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SYSCFG can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SYSCFG can be accessed from a... + io_rw_32 syscfg; + + _REG_(ACCESSCTRL_CLOCKS_OFFSET) // ACCESSCTRL_CLOCKS + // Control access to CLOCKS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CLOCKS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, CLOCKS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CLOCKS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CLOCKS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CLOCKS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, CLOCKS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, CLOCKS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CLOCKS can be accessed from a... + io_rw_32 clocks; + + _REG_(ACCESSCTRL_XOSC_OFFSET) // ACCESSCTRL_XOSC + // Control access to XOSC. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XOSC can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XOSC can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XOSC can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XOSC can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XOSC can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XOSC can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XOSC can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XOSC can be accessed from a... + io_rw_32 xosc; + + _REG_(ACCESSCTRL_ROSC_OFFSET) // ACCESSCTRL_ROSC + // Control access to ROSC. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, ROSC can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, ROSC can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ROSC can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ROSC can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ROSC can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, ROSC can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, ROSC can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ROSC can be accessed from a... + io_rw_32 rosc; + + _REG_(ACCESSCTRL_PLL_SYS_OFFSET) // ACCESSCTRL_PLL_SYS + // Control access to PLL_SYS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, PLL_SYS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, PLL_SYS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PLL_SYS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PLL_SYS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PLL_SYS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_SYS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PLL_SYS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_SYS can be accessed from... + io_rw_32 pll_sys; + + _REG_(ACCESSCTRL_PLL_USB_OFFSET) // ACCESSCTRL_PLL_USB + // Control access to PLL_USB. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, PLL_USB can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, PLL_USB can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PLL_USB can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PLL_USB can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PLL_USB can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_USB can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PLL_USB can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_USB can be accessed from... + io_rw_32 pll_usb; + + _REG_(ACCESSCTRL_TICKS_OFFSET) // ACCESSCTRL_TICKS + // Control access to TICKS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, TICKS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, TICKS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TICKS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TICKS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TICKS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, TICKS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TICKS can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TICKS can be accessed from a... + io_rw_32 ticks; + + _REG_(ACCESSCTRL_WATCHDOG_OFFSET) // ACCESSCTRL_WATCHDOG + // Control access to WATCHDOG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, WATCHDOG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, WATCHDOG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, WATCHDOG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, WATCHDOG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, WATCHDOG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, WATCHDOG can be accessed from... + // 0x00000002 [1] NSP (0) If 1, WATCHDOG can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, WATCHDOG can be accessed from... + io_rw_32 watchdog; + + _REG_(ACCESSCTRL_RSM_OFFSET) // ACCESSCTRL_RSM + // Control access to RSM. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, RSM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, RSM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, RSM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, RSM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, RSM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, RSM can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, RSM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RSM can be accessed from a... + io_rw_32 rsm; + + _REG_(ACCESSCTRL_XIP_CTRL_OFFSET) // ACCESSCTRL_XIP_CTRL + // Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XIP_CTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XIP_CTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_CTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_CTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_CTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_CTRL can be accessed from... + // 0x00000002 [1] NSP (0) If 1, XIP_CTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_CTRL can be accessed from... + io_rw_32 xip_ctrl; + + _REG_(ACCESSCTRL_XIP_QMI_OFFSET) // ACCESSCTRL_XIP_QMI + // Control access to XIP_QMI. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XIP_QMI can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XIP_QMI can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_QMI can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_QMI can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_QMI can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_QMI can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XIP_QMI can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_QMI can be accessed from... + io_rw_32 xip_qmi; + + _REG_(ACCESSCTRL_XIP_AUX_OFFSET) // ACCESSCTRL_XIP_AUX + // Control access to XIP_AUX. Defaults to Secure, Privileged access only. + // 0x00000080 [7] DBG (1) If 1, XIP_AUX can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, XIP_AUX can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_AUX can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_AUX can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_AUX can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_AUX can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XIP_AUX can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_AUX can be accessed from... + io_rw_32 xip_aux; +} accessctrl_hw_t; + +#define accessctrl_hw ((accessctrl_hw_t *)ACCESSCTRL_BASE) +static_assert(sizeof (accessctrl_hw_t) == 0x00ec, ""); + +#endif // _HARDWARE_STRUCTS_ACCESSCTRL_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/adc.h b/src/rp2350/hardware_structs/include/hardware/structs/adc.h new file mode 100644 index 000000000..687128eba --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/adc.h @@ -0,0 +1,96 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ADC_H +#define _HARDWARE_STRUCTS_ADC_H + +/** + * \file rp2350/adc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/adc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_adc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ADC_CS_OFFSET) // ADC_CS + // ADC Control and Status + // 0x01ff0000 [24:16] RROBIN (0x000) Round-robin sampling + // 0x0000f000 [15:12] AINSEL (0x0) Select analog mux input + // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error + // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;... + // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion + // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1 + // 0x00000004 [2] START_ONCE (0) Start a single conversion + // 0x00000002 [1] TS_EN (0) Power on temperature sensor + // 0x00000001 [0] EN (0) Power on ADC and enable its clock + io_rw_32 cs; + + _REG_(ADC_RESULT_OFFSET) // ADC_RESULT + // Result of most recent ADC conversion + // 0x00000fff [11:0] RESULT (0x000) + io_ro_32 result; + + _REG_(ADC_FCS_OFFSET) // ADC_FCS + // FIFO control and status + // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold + // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO + // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed + // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed + // 0x00000200 [9] FULL (0) + // 0x00000100 [8] EMPTY (0) + // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data + // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside... + // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size + // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion + io_rw_32 fcs; + + _REG_(ADC_FIFO_OFFSET) // ADC_FIFO + // Conversion result FIFO + // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error + // 0x00000fff [11:0] VAL (-) + io_ro_32 fifo; + + _REG_(ADC_DIV_OFFSET) // ADC_DIV + // Clock divider + // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor + // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor + io_rw_32 div; + + _REG_(ADC_INTR_OFFSET) // ADC_INTR + // Raw Interrupts + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 intr; + + _REG_(ADC_INTE_OFFSET) // ADC_INTE + // Interrupt Enable + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 inte; + + _REG_(ADC_INTF_OFFSET) // ADC_INTF + // Interrupt Force + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 intf; + + _REG_(ADC_INTS_OFFSET) // ADC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 ints; +} adc_hw_t; + +#define adc_hw ((adc_hw_t *)ADC_BASE) +static_assert(sizeof (adc_hw_t) == 0x0024, ""); + +#endif // _HARDWARE_STRUCTS_ADC_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/bootram.h b/src/rp2350/hardware_structs/include/hardware/structs/bootram.h new file mode 100644 index 000000000..b40a0393f --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/bootram.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BOOTRAM_H +#define _HARDWARE_STRUCTS_BOOTRAM_H + +/** + * \file rp2350/bootram.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/bootram.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_bootram +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/bootram.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register BOOTRAM_WRITE_ONCE0 applies similarly to other array indexes) + _REG_(BOOTRAM_WRITE_ONCE0_OFFSET) // BOOTRAM_WRITE_ONCE0 + // This registers always ORs writes into its current contents + // 0xffffffff [31:0] WRITE_ONCE0 (0x00000000) + io_rw_32 write_once[2]; + + _REG_(BOOTRAM_BOOTLOCK_STAT_OFFSET) // BOOTRAM_BOOTLOCK_STAT + // Bootlock status register + // 0x000000ff [7:0] BOOTLOCK_STAT (0xff) + io_rw_32 bootlock_stat; + + // (Description copied from array index 0 register BOOTRAM_BOOTLOCK0 applies similarly to other array indexes) + _REG_(BOOTRAM_BOOTLOCK0_OFFSET) // BOOTRAM_BOOTLOCK0 + // Read to claim and check + // 0xffffffff [31:0] BOOTLOCK0 (0x00000000) + io_rw_32 bootlock[8]; +} bootram_hw_t; + +#define bootram_hw ((bootram_hw_t *)(BOOTRAM_BASE + BOOTRAM_WRITE_ONCE0_OFFSET)) +static_assert(sizeof (bootram_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_BOOTRAM_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/bus_ctrl.h b/src/rp2350/hardware_structs/include/hardware/structs/bus_ctrl.h new file mode 100644 index 000000000..b94a40459 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/bus_ctrl.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/busctrl.h" +#define bus_ctrl_hw busctrl_hw \ No newline at end of file diff --git a/src/rp2350/hardware_structs/include/hardware/structs/busctrl.h b/src/rp2350/hardware_structs/include/hardware/structs/busctrl.h new file mode 100644 index 000000000..2eb83a992 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/busctrl.h @@ -0,0 +1,90 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUSCTRL_H +#define _HARDWARE_STRUCTS_BUSCTRL_H + +/** + * \file rp2350/busctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_busctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Bus fabric performance counters on RP2350 (used as typedef \ref bus_ctrl_perf_counter_t) + * \ingroup hardware_busctrl + */ +typedef enum bus_ctrl_perf_counter_rp2350 { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +} bus_ctrl_perf_counter_t; + +typedef struct { + _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 + // Bus fabric performance counter 0 + // 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 + + io_rw_32 value; + + _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 + // Bus fabric performance event select for PERFCTR0 + // 0x0000007f [6:0] PERFSEL0 (0x1f) Select an event for PERFCTR0 + io_rw_32 sel; +} bus_ctrl_perf_hw_t; + +typedef struct { + _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY + // Set the priority of each master for bus arbitration + // 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority + // 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority + // 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority + // 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority + io_rw_32 priority; + + _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK + // Bus priority acknowledge + // 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new... + io_ro_32 priority_ack; + + _REG_(BUSCTRL_PERFCTR_EN_OFFSET) // BUSCTRL_PERFCTR_EN + // Enable the performance counters + // 0x00000001 [0] PERFCTR_EN (0) + io_rw_32 perfctr_en; + + bus_ctrl_perf_hw_t counter[4]; +} busctrl_hw_t; + +#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE) +static_assert(sizeof (busctrl_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_BUSCTRL_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/clocks.h b/src/rp2350/hardware_structs/include/hardware/structs/clocks.h new file mode 100644 index 000000000..2cdc1b824 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/clocks.h @@ -0,0 +1,580 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +/** + * \file rp2350/clocks.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/clocks.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_clocks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Clock numbers on RP2350 (used as typedef \ref clock_num_t) + * \ingroup hardware_clocks + */ +/// \tag::clkenum[] +typedef enum clock_num_rp2350 { + clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source + clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source + clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source + clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source + clk_ref = 4, ///< Select CLK_REF as clock source + clk_sys = 5, ///< Select CLK_SYS as clock source + clk_peri = 6, ///< Select CLK_PERI as clock source + clk_hstx = 7, ///< Select CLK_HSTX as clock source + clk_usb = 8, ///< Select CLK_USB as clock source + clk_adc = 9, ///< Select CLK_ADC as clock source + CLK_COUNT +} clock_num_t; +/// \end::clkenum[] + +/** \brief Clock destination numbers on RP2350 (used as typedef \ref clock_dest_num_t) + * \ingroup hardware_clocks + */ +typedef enum clock_dest_num_rp2350 { + CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination + CLK_DEST_SYS_ACCESSCTRL = 1, ///< Select SYS_ACCESSCTRL as clock destination + CLK_DEST_ADC = 2, ///< Select ADC as clock destination + CLK_DEST_SYS_ADC = 3, ///< Select SYS_ADC as clock destination + CLK_DEST_SYS_BOOTRAM = 4, ///< Select SYS_BOOTRAM as clock destination + CLK_DEST_SYS_BUSCTRL = 5, ///< Select SYS_BUSCTRL as clock destination + CLK_DEST_SYS_BUSFABRIC = 6, ///< Select SYS_BUSFABRIC as clock destination + CLK_DEST_SYS_DMA = 7, ///< Select SYS_DMA as clock destination + CLK_DEST_SYS_GLITCH_DETECTOR = 8, ///< Select SYS_GLITCH_DETECTOR as clock destination + CLK_DEST_HSTX = 9, ///< Select HSTX as clock destination + CLK_DEST_SYS_HSTX = 10, ///< Select SYS_HSTX as clock destination + CLK_DEST_SYS_I2C0 = 11, ///< Select SYS_I2C0 as clock destination + CLK_DEST_SYS_I2C1 = 12, ///< Select SYS_I2C1 as clock destination + CLK_DEST_SYS_IO = 13, ///< Select SYS_IO as clock destination + CLK_DEST_SYS_JTAG = 14, ///< Select SYS_JTAG as clock destination + CLK_DEST_REF_OTP = 15, ///< Select REF_OTP as clock destination + CLK_DEST_SYS_OTP = 16, ///< Select SYS_OTP as clock destination + CLK_DEST_SYS_PADS = 17, ///< Select SYS_PADS as clock destination + CLK_DEST_SYS_PIO0 = 18, ///< Select SYS_PIO0 as clock destination + CLK_DEST_SYS_PIO1 = 19, ///< Select SYS_PIO1 as clock destination + CLK_DEST_SYS_PIO2 = 20, ///< Select SYS_PIO2 as clock destination + CLK_DEST_SYS_PLL_SYS = 21, ///< Select SYS_PLL_SYS as clock destination + CLK_DEST_SYS_PLL_USB = 22, ///< Select SYS_PLL_USB as clock destination + CLK_DEST_REF_POWMAN = 23, ///< Select REF_POWMAN as clock destination + CLK_DEST_SYS_POWMAN = 24, ///< Select SYS_POWMAN as clock destination + CLK_DEST_SYS_PWM = 25, ///< Select SYS_PWM as clock destination + CLK_DEST_SYS_RESETS = 26, ///< Select SYS_RESETS as clock destination + CLK_DEST_SYS_ROM = 27, ///< Select SYS_ROM as clock destination + CLK_DEST_SYS_ROSC = 28, ///< Select SYS_ROSC as clock destination + CLK_DEST_SYS_PSM = 29, ///< Select SYS_PSM as clock destination + CLK_DEST_SYS_SHA256 = 30, ///< Select SYS_SHA256 as clock destination + CLK_DEST_SYS_SIO = 31, ///< Select SYS_SIO as clock destination + CLK_DEST_PERI_SPI0 = 32, ///< Select PERI_SPI0 as clock destination + CLK_DEST_SYS_SPI0 = 33, ///< Select SYS_SPI0 as clock destination + CLK_DEST_PERI_SPI1 = 34, ///< Select PERI_SPI1 as clock destination + CLK_DEST_SYS_SPI1 = 35, ///< Select SYS_SPI1 as clock destination + CLK_DEST_SYS_SRAM0 = 36, ///< Select SYS_SRAM0 as clock destination + CLK_DEST_SYS_SRAM1 = 37, ///< Select SYS_SRAM1 as clock destination + CLK_DEST_SYS_SRAM2 = 38, ///< Select SYS_SRAM2 as clock destination + CLK_DEST_SYS_SRAM3 = 39, ///< Select SYS_SRAM3 as clock destination + CLK_DEST_SYS_SRAM4 = 40, ///< Select SYS_SRAM4 as clock destination + CLK_DEST_SYS_SRAM5 = 41, ///< Select SYS_SRAM5 as clock destination + CLK_DEST_SYS_SRAM6 = 42, ///< Select SYS_SRAM6 as clock destination + CLK_DEST_SYS_SRAM7 = 43, ///< Select SYS_SRAM7 as clock destination + CLK_DEST_SYS_SRAM8 = 44, ///< Select SYS_SRAM8 as clock destination + CLK_DEST_SYS_SRAM9 = 45, ///< Select SYS_SRAM9 as clock destination + CLK_DEST_SYS_SYSCFG = 46, ///< Select SYS_SYSCFG as clock destination + CLK_DEST_SYS_SYSINFO = 47, ///< Select SYS_SYSINFO as clock destination + CLK_DEST_SYS_TBMAN = 48, ///< Select SYS_TBMAN as clock destination + CLK_DEST_REF_TICKS = 49, ///< Select REF_TICKS as clock destination + CLK_DEST_SYS_TICKS = 50, ///< Select SYS_TICKS as clock destination + CLK_DEST_SYS_TIMER0 = 51, ///< Select SYS_TIMER0 as clock destination + CLK_DEST_SYS_TIMER1 = 52, ///< Select SYS_TIMER1 as clock destination + CLK_DEST_SYS_TRNG = 53, ///< Select SYS_TRNG as clock destination + CLK_DEST_PERI_UART0 = 54, ///< Select PERI_UART0 as clock destination + CLK_DEST_SYS_UART0 = 55, ///< Select SYS_UART0 as clock destination + CLK_DEST_PERI_UART1 = 56, ///< Select PERI_UART1 as clock destination + CLK_DEST_SYS_UART1 = 57, ///< Select SYS_UART1 as clock destination + CLK_DEST_SYS_USBCTRL = 58, ///< Select SYS_USBCTRL as clock destination + CLK_DEST_USB = 59, ///< Select USB as clock destination + CLK_DEST_SYS_WATCHDOG = 60, ///< Select SYS_WATCHDOG as clock destination + CLK_DEST_SYS_XIP = 61, ///< Select SYS_XIP as clock destination + CLK_DEST_SYS_XOSC = 62, ///< Select SYS_XOSC as clock destination + NUM_CLOCK_DESTINATIONS +} clock_dest_num_t; + +/// \tag::clock_hw[] +typedef struct { + _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL + // Clock control, can be changed on-the-fly (except for auxsrc) + // 0x10000000 [28] ENABLED (0) clock generator is enabled + // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by... + // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the... + // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors, can be... + // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly + // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator, enable must be... + // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV + // 0xffff0000 [31:16] INT (0x0001) Integer part of clock divisor, 0 -> max+1, can be... + // 0x0000ffff [15:0] FRAC (0x0000) Fractional component of the divisor, can be changed on-the-fly + io_rw_32 div; + + _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED + // Indicates which src is currently selected (one-hot) + // 0x00000001 [0] CLK_GPOUT0_SELECTED (1) This slice does not have a glitchless mux (only the... + io_ro_32 selected; +} clock_hw_t; +/// \end::clock_hw[] + +typedef struct { + _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL + // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it... + // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only + // 0x00000100 [8] ENABLE (0) Enable resus + // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles + + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS + // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send... + io_ro_32 status; +} clock_resus_hw_t; + +typedef struct { + _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ + // Reference clock frequency in kHz + // 0x000fffff [19:0] FC0_REF_KHZ (0x00000) + io_rw_32 ref_khz; + + _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ + // Minimum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000) + io_rw_32 min_khz; + + _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ + // Maximum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff) + io_rw_32 max_khz; + + _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY + // Delays the start of frequency counting to allow the mux to settle + + // 0x00000007 [2:0] FC0_DELAY (0x1) + io_rw_32 delay; + + _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL + // The test interval is 0 + // 0x0000000f [3:0] FC0_INTERVAL (0x8) + io_rw_32 interval; + + _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC + // Clock sent to frequency counter, set to 0 when not required + + // 0x000000ff [7:0] FC0_SRC (0x00) + io_rw_32 src; + + _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS + // Frequency counter status + // 0x10000000 [28] DIED (0) Test clock stopped during test + // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1 + // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1 + // 0x00010000 [16] FAIL (0) Test failed + // 0x00001000 [12] WAITING (0) Waiting for test clock to start + // 0x00000100 [8] RUNNING (0) Test running + // 0x00000010 [4] DONE (0) Test complete + // 0x00000001 [0] PASS (0) Test passed + io_ro_32 status; + + _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT + // Result of frequency measurement, only valid when status_done=1 + // 0x3fffffe0 [29:5] KHZ (0x0000000) + // 0x0000001f [4:0] FRAC (0x00) + io_ro_32 result; +} fc_hw_t; + +typedef struct { + clock_hw_t clk[10]; + + _REG_(CLOCKS_DFTCLK_XOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_XOSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_xosc_ctrl; + + _REG_(CLOCKS_DFTCLK_ROSC_CTRL_OFFSET) // CLOCKS_DFTCLK_ROSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_rosc_ctrl; + + _REG_(CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_LPOSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_lposc_ctrl; + + clock_resus_hw_t resus; + + fc_hw_t fc0; + + union { + struct { + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_RSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en0; + + _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 + // enable clock in wake mode + // 0x40000000 [30] CLK_SYS_XOSC (1) + // 0x20000000 [29] CLK_SYS_XIP (1) + // 0x10000000 [28] CLK_SYS_WATCHDOG (1) + // 0x08000000 [27] CLK_USB (1) + // 0x04000000 [26] CLK_SYS_USBCTRL (1) + // 0x02000000 [25] CLK_SYS_UART1 (1) + // 0x01000000 [24] CLK_PERI_UART1 (1) + // 0x00800000 [23] CLK_SYS_UART0 (1) + // 0x00400000 [22] CLK_PERI_UART0 (1) + // 0x00200000 [21] CLK_SYS_TRNG (1) + // 0x00100000 [20] CLK_SYS_TIMER1 (1) + // 0x00080000 [19] CLK_SYS_TIMER0 (1) + // 0x00040000 [18] CLK_SYS_TICKS (1) + // 0x00020000 [17] CLK_REF_TICKS (1) + // 0x00010000 [16] CLK_SYS_TBMAN (1) + // 0x00008000 [15] CLK_SYS_SYSINFO (1) + // 0x00004000 [14] CLK_SYS_SYSCFG (1) + // 0x00002000 [13] CLK_SYS_SRAM9 (1) + // 0x00001000 [12] CLK_SYS_SRAM8 (1) + // 0x00000800 [11] CLK_SYS_SRAM7 (1) + // 0x00000400 [10] CLK_SYS_SRAM6 (1) + // 0x00000200 [9] CLK_SYS_SRAM5 (1) + // 0x00000100 [8] CLK_SYS_SRAM4 (1) + // 0x00000080 [7] CLK_SYS_SRAM3 (1) + // 0x00000040 [6] CLK_SYS_SRAM2 (1) + // 0x00000020 [5] CLK_SYS_SRAM1 (1) + // 0x00000010 [4] CLK_SYS_SRAM0 (1) + // 0x00000008 [3] CLK_SYS_SPI1 (1) + // 0x00000004 [2] CLK_PERI_SPI1 (1) + // 0x00000002 [1] CLK_SYS_SPI0 (1) + // 0x00000001 [0] CLK_PERI_SPI0 (1) + io_rw_32 wake_en1; + }; + // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SIO (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_PSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_RSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en0; + + _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 + // enable clock in sleep mode + // 0x40000000 [30] CLK_SYS_XOSC (1) + // 0x20000000 [29] CLK_SYS_XIP (1) + // 0x10000000 [28] CLK_SYS_WATCHDOG (1) + // 0x08000000 [27] CLK_USB (1) + // 0x04000000 [26] CLK_SYS_USBCTRL (1) + // 0x02000000 [25] CLK_SYS_UART1 (1) + // 0x01000000 [24] CLK_PERI_UART1 (1) + // 0x00800000 [23] CLK_SYS_UART0 (1) + // 0x00400000 [22] CLK_PERI_UART0 (1) + // 0x00200000 [21] CLK_SYS_TRNG (1) + // 0x00100000 [20] CLK_SYS_TIMER1 (1) + // 0x00080000 [19] CLK_SYS_TIMER0 (1) + // 0x00040000 [18] CLK_SYS_TICKS (1) + // 0x00020000 [17] CLK_REF_TICKS (1) + // 0x00010000 [16] CLK_SYS_TBMAN (1) + // 0x00008000 [15] CLK_SYS_SYSINFO (1) + // 0x00004000 [14] CLK_SYS_SYSCFG (1) + // 0x00002000 [13] CLK_SYS_SRAM9 (1) + // 0x00001000 [12] CLK_SYS_SRAM8 (1) + // 0x00000800 [11] CLK_SYS_SRAM7 (1) + // 0x00000400 [10] CLK_SYS_SRAM6 (1) + // 0x00000200 [9] CLK_SYS_SRAM5 (1) + // 0x00000100 [8] CLK_SYS_SRAM4 (1) + // 0x00000080 [7] CLK_SYS_SRAM3 (1) + // 0x00000040 [6] CLK_SYS_SRAM2 (1) + // 0x00000020 [5] CLK_SYS_SRAM1 (1) + // 0x00000010 [4] CLK_SYS_SRAM0 (1) + // 0x00000008 [3] CLK_SYS_SPI1 (1) + // 0x00000004 [2] CLK_PERI_SPI1 (1) + // 0x00000002 [1] CLK_SYS_SPI0 (1) + // 0x00000001 [0] CLK_PERI_SPI0 (1) + io_rw_32 sleep_en1; + }; + // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SIO (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_PSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SIOB (0) + // 0x40000000 [30] CLK_SYS_SHA256 (0) + // 0x20000000 [29] CLK_SYS_RSM (0) + // 0x10000000 [28] CLK_SYS_ROSC (0) + // 0x08000000 [27] CLK_SYS_ROM (0) + // 0x04000000 [26] CLK_SYS_RESETS (0) + // 0x02000000 [25] CLK_SYS_PWM (0) + // 0x01000000 [24] CLK_SYS_POWMAN (0) + // 0x00800000 [23] CLK_REF_POWMAN (0) + // 0x00400000 [22] CLK_SYS_PLL_USB (0) + // 0x00200000 [21] CLK_SYS_PLL_SYS (0) + // 0x00100000 [20] CLK_SYS_PIO2 (0) + // 0x00080000 [19] CLK_SYS_PIO1 (0) + // 0x00040000 [18] CLK_SYS_PIO0 (0) + // 0x00020000 [17] CLK_SYS_PADS (0) + // 0x00010000 [16] CLK_SYS_OTP (0) + // 0x00008000 [15] CLK_REF_OTP (0) + // 0x00004000 [14] CLK_SYS_JTAG (0) + // 0x00002000 [13] CLK_SYS_IO (0) + // 0x00001000 [12] CLK_SYS_I2C1 (0) + // 0x00000800 [11] CLK_SYS_I2C0 (0) + // 0x00000400 [10] CLK_SYS_HSTX (0) + // 0x00000200 [9] CLK_HSTX (0) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) + // 0x00000080 [7] CLK_SYS_DMA (0) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) + // 0x00000020 [5] CLK_SYS_BUSCTRL (0) + // 0x00000010 [4] CLK_SYS_BOOTRAM (0) + // 0x00000008 [3] CLK_SYS_ADC (0) + // 0x00000004 [2] CLK_ADC (0) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled0; + + _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 + // indicates the state of the clock enable + // 0x40000000 [30] CLK_SYS_XOSC (0) + // 0x20000000 [29] CLK_SYS_XIP (0) + // 0x10000000 [28] CLK_SYS_WATCHDOG (0) + // 0x08000000 [27] CLK_USB (0) + // 0x04000000 [26] CLK_SYS_USBCTRL (0) + // 0x02000000 [25] CLK_SYS_UART1 (0) + // 0x01000000 [24] CLK_PERI_UART1 (0) + // 0x00800000 [23] CLK_SYS_UART0 (0) + // 0x00400000 [22] CLK_PERI_UART0 (0) + // 0x00200000 [21] CLK_SYS_TRNG (0) + // 0x00100000 [20] CLK_SYS_TIMER1 (0) + // 0x00080000 [19] CLK_SYS_TIMER0 (0) + // 0x00040000 [18] CLK_SYS_TICKS (0) + // 0x00020000 [17] CLK_REF_TICKS (0) + // 0x00010000 [16] CLK_SYS_TBMAN (0) + // 0x00008000 [15] CLK_SYS_SYSINFO (0) + // 0x00004000 [14] CLK_SYS_SYSCFG (0) + // 0x00002000 [13] CLK_SYS_SRAM9 (0) + // 0x00001000 [12] CLK_SYS_SRAM8 (0) + // 0x00000800 [11] CLK_SYS_SRAM7 (0) + // 0x00000400 [10] CLK_SYS_SRAM6 (0) + // 0x00000200 [9] CLK_SYS_SRAM5 (0) + // 0x00000100 [8] CLK_SYS_SRAM4 (0) + // 0x00000080 [7] CLK_SYS_SRAM3 (0) + // 0x00000040 [6] CLK_SYS_SRAM2 (0) + // 0x00000020 [5] CLK_SYS_SRAM1 (0) + // 0x00000010 [4] CLK_SYS_SRAM0 (0) + // 0x00000008 [3] CLK_SYS_SPI1 (0) + // 0x00000004 [2] CLK_PERI_SPI1 (0) + // 0x00000002 [1] CLK_SYS_SPI0 (0) + // 0x00000001 [0] CLK_PERI_SPI0 (0) + io_ro_32 enabled1; + }; + // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes) + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SIO (0) + // 0x40000000 [30] CLK_SYS_SHA256 (0) + // 0x20000000 [29] CLK_SYS_PSM (0) + // 0x10000000 [28] CLK_SYS_ROSC (0) + // 0x08000000 [27] CLK_SYS_ROM (0) + // 0x04000000 [26] CLK_SYS_RESETS (0) + // 0x02000000 [25] CLK_SYS_PWM (0) + // 0x01000000 [24] CLK_SYS_POWMAN (0) + // 0x00800000 [23] CLK_REF_POWMAN (0) + // 0x00400000 [22] CLK_SYS_PLL_USB (0) + // 0x00200000 [21] CLK_SYS_PLL_SYS (0) + // 0x00100000 [20] CLK_SYS_PIO2 (0) + // 0x00080000 [19] CLK_SYS_PIO1 (0) + // 0x00040000 [18] CLK_SYS_PIO0 (0) + // 0x00020000 [17] CLK_SYS_PADS (0) + // 0x00010000 [16] CLK_SYS_OTP (0) + // 0x00008000 [15] CLK_REF_OTP (0) + // 0x00004000 [14] CLK_SYS_JTAG (0) + // 0x00002000 [13] CLK_SYS_IO (0) + // 0x00001000 [12] CLK_SYS_I2C1 (0) + // 0x00000800 [11] CLK_SYS_I2C0 (0) + // 0x00000400 [10] CLK_SYS_HSTX (0) + // 0x00000200 [9] CLK_HSTX (0) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) + // 0x00000080 [7] CLK_SYS_DMA (0) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) + // 0x00000020 [5] CLK_SYS_BUSCTRL (0) + // 0x00000010 [4] CLK_SYS_BOOTRAM (0) + // 0x00000008 [3] CLK_SYS_ADC (0) + // 0x00000004 [2] CLK_ADC (0) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled[2]; + }; + + _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR + // Raw Interrupts + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 intr; + + _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE + // Interrupt Enable + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 inte; + + _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF + // Interrupt Force + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 intf; + + _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 ints; +} clocks_hw_t; + +#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE) +static_assert(sizeof (clocks_hw_t) == 0x00d4, ""); + +#endif // _HARDWARE_STRUCTS_CLOCKS_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/coresight_trace.h b/src/rp2350/hardware_structs/include/hardware/structs/coresight_trace.h new file mode 100644 index 000000000..61ffb0623 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/coresight_trace.h @@ -0,0 +1,43 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_CORESIGHT_TRACE_H +#define _HARDWARE_STRUCTS_CORESIGHT_TRACE_H + +/** + * \file rp2350/coresight_trace.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/coresight_trace.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_coresight_trace +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/coresight_trace.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(CORESIGHT_TRACE_CTRL_STATUS_OFFSET) // CORESIGHT_TRACE_CTRL_STATUS + // Control and status register + // 0x00000002 [1] TRACE_CAPTURE_FIFO_OVERFLOW (0) This status flag is set high when trace data has been... + // 0x00000001 [0] TRACE_CAPTURE_FIFO_FLUSH (1) Set to 1 to continuously hold the trace FIFO in a... + io_rw_32 ctrl_status; + + _REG_(CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET) // CORESIGHT_TRACE_TRACE_CAPTURE_FIFO + // FIFO for trace data captured from the TPIU + // 0xffffffff [31:0] RDATA (0x00000000) Read from an 8 x 32-bit FIFO containing trace data... + io_ro_32 trace_capture_fifo; +} coresight_trace_hw_t; + +#define coresight_trace_hw ((coresight_trace_hw_t *)CORESIGHT_TRACE_BASE) +static_assert(sizeof (coresight_trace_hw_t) == 0x0008, ""); + +#endif // _HARDWARE_STRUCTS_CORESIGHT_TRACE_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/dma.h b/src/rp2350/hardware_structs/include/hardware/structs/dma.h new file mode 100644 index 000000000..6097a9844 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/dma.h @@ -0,0 +1,336 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +/** + * \file rp2350/dma.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" +#include "hardware/structs/dma_debug.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR + // DMA Channel 0 Read Address pointer + // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes + io_rw_32 read_addr; + + _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR + // DMA Channel 0 Write Address pointer + // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes + io_rw_32 write_addr; + + _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT + // DMA Channel 0 Transfer Count + // 0xf0000000 [31:28] MODE (0x0) When MODE is 0x0, the transfer count decrements with... + // 0x0fffffff [27:0] COUNT (0x0000000) 28-bit transfer count (256 million transfers maximum) + io_rw_32 transfer_count; + + _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG + // DMA Channel 0 Control and Status + // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags + // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error + // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error + // 0x04000000 [26] BUSY (0) This flag goes high when the channel starts a new... + // 0x02000000 [25] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... + // 0x01000000 [24] BSWAP (0) Apply byte-swap transformation to DMA data + // 0x00800000 [23] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... + // 0x007e0000 [22:17] TREQ_SEL (0x00) Select a Transfer Request signal + // 0x0001e000 [16:13] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... + // 0x00001000 [12] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses + // 0x00000f00 [11:8] RING_SIZE (0x0) Size of address wrap region + // 0x00000080 [7] INCR_WRITE_REV (0) If 1, and INCR_WRITE is 1, the write address is... + // 0x00000040 [6] INCR_WRITE (0) If 1, the write address increments with each transfer + // 0x00000020 [5] INCR_READ_REV (0) If 1, and INCR_READ is 1, the read address is... + // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer + // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) + // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... + // 0x00000001 [0] EN (0) DMA Channel Enable + io_rw_32 ctrl_trig; + + _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL1_CTRL (-) + io_rw_32 al1_ctrl; + + _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) + io_rw_32 al1_read_addr; + + _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) + io_rw_32 al1_write_addr; + + _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG + // Alias for channel 0 TRANS_COUNT register + + // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) + io_rw_32 al1_transfer_count_trig; + + _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL2_CTRL (-) + io_rw_32 al2_ctrl; + + _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) + io_rw_32 al2_transfer_count; + + _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) + io_rw_32 al2_read_addr; + + _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG + // Alias for channel 0 WRITE_ADDR register + + // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) + io_rw_32 al2_write_addr_trig; + + _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL3_CTRL (-) + io_rw_32 al3_ctrl; + + _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) + io_rw_32 al3_write_addr; + + _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) + io_rw_32 al3_transfer_count; + + _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG + // Alias for channel 0 READ_ADDR register + + // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + _REG_(DMA_MPU_BAR0_OFFSET) // DMA_MPU_BAR0 + // Base address register for MPU region 0 + // 0xffffffe0 [31:5] ADDR (0x0000000) This MPU region matches addresses where addr[31:5] (the... + io_rw_32 bar; + + _REG_(DMA_MPU_LAR0_OFFSET) // DMA_MPU_LAR0 + // Limit address register for MPU region 0 + // 0xffffffe0 [31:5] ADDR (0x0000000) Limit address bits 31:5 + // 0x00000004 [2] S (0) Determines the Secure/Non-secure (=1/0) status of... + // 0x00000002 [1] P (0) Determines the Privileged/Unprivileged (=1/0) status of... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 lar; +} dma_mpu_region_hw_t; + +typedef struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTS0 + io_rw_32 intf; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints; +} dma_irq_ctrl_hw_t; + +typedef struct { + dma_channel_hw_t ch[16]; + + union { + struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte0; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 + io_rw_32 intf0; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints0; + + uint32_t __pad0; + + _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 + // Interrupt Enables for IRQ 1 + // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 + io_rw_32 inte1; + + _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 + // Force Interrupts for IRQ 1 + // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 + io_rw_32 intf1; + + _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 + // Interrupt Status (masked) for IRQ 1 + // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints1; + + uint32_t __pad1; + + _REG_(DMA_INTE2_OFFSET) // DMA_INTE2 + // Interrupt Enables for IRQ 2 + // 0x0000ffff [15:0] INTE2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 inte2; + + _REG_(DMA_INTF2_OFFSET) // DMA_INTF2 + // Force Interrupts for IRQ 2 + // 0x0000ffff [15:0] INTF2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 intf2; + + _REG_(DMA_INTS2_OFFSET) // DMA_INTS2 + // Interrupt Status (masked) for IRQ 2 + // 0x0000ffff [15:0] INTS2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 ints2; + + uint32_t __pad2; + + _REG_(DMA_INTE3_OFFSET) // DMA_INTE3 + // Interrupt Enables for IRQ 3 + // 0x0000ffff [15:0] INTE3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 inte3; + + _REG_(DMA_INTF3_OFFSET) // DMA_INTF3 + // Force Interrupts for IRQ 3 + // 0x0000ffff [15:0] INTF3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 intf3; + + _REG_(DMA_INTS3_OFFSET) // DMA_INTS3 + // Interrupt Status (masked) for IRQ 3 + // 0x0000ffff [15:0] INTS3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 ints3; + }; + dma_irq_ctrl_hw_t irq_ctrl[4]; + }; + + // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) + _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 + // Pacing timer (generate periodic TREQs) + // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend + // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor + io_rw_32 timer[4]; + + _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER + // Trigger one or more channels simultaneously + // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel + io_wo_32 multi_channel_trigger; + + _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL + // Sniffer Control + // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... + // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read + // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... + // 0x000001e0 [8:5] CALC (0x0) + // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe + // 0x00000001 [0] EN (0) Enable sniffer + io_rw_32 sniff_ctrl; + + _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA + // Data accumulator for sniff hardware + // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... + io_rw_32 sniff_data; + + uint32_t _pad0; + + _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS + // Debug RAF, WAF, TDF levels + // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level + // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level + // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level + io_ro_32 fifo_levels; + + _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT + // Abort an in-progress transfer sequence on one or more channels + // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel + io_wo_32 abort; + + _REG_(DMA_N_CHANNELS_OFFSET) // DMA_N_CHANNELS + // The number of channels this DMA instance is equipped with + // 0x0000001f [4:0] N_CHANNELS (-) + io_ro_32 n_channels; + + uint32_t _pad1[5]; + + // (Description copied from array index 0 register DMA_SECCFG_CH0 applies similarly to other array indexes) + _REG_(DMA_SECCFG_CH0_OFFSET) // DMA_SECCFG_CH0 + // Security level configuration for channel 0. + // 0x00000004 [2] LOCK (0) LOCK is 0 at reset, and is set to 1 automatically upon a... + // 0x00000002 [1] S (1) Secure channel + // 0x00000001 [0] P (1) Privileged channel + io_rw_32 seccfg_ch[16]; + + // (Description copied from array index 0 register DMA_SECCFG_IRQ0 applies similarly to other array indexes) + _REG_(DMA_SECCFG_IRQ0_OFFSET) // DMA_SECCFG_IRQ0 + // Security configuration for IRQ 0 + // 0x00000002 [1] S (1) Secure IRQ + // 0x00000001 [0] P (1) Privileged IRQ + io_rw_32 seccfg_irq[4]; + + _REG_(DMA_SECCFG_MISC_OFFSET) // DMA_SECCFG_MISC + // Miscellaneous security configuration + // 0x00000200 [9] TIMER3_S (1) If 1, the TIMER3 register is only accessible from a... + // 0x00000100 [8] TIMER3_P (1) If 1, the TIMER3 register is only accessible from a... + // 0x00000080 [7] TIMER2_S (1) If 1, the TIMER2 register is only accessible from a... + // 0x00000040 [6] TIMER2_P (1) If 1, the TIMER2 register is only accessible from a... + // 0x00000020 [5] TIMER1_S (1) If 1, the TIMER1 register is only accessible from a... + // 0x00000010 [4] TIMER1_P (1) If 1, the TIMER1 register is only accessible from a... + // 0x00000008 [3] TIMER0_S (1) If 1, the TIMER0 register is only accessible from a... + // 0x00000004 [2] TIMER0_P (1) If 1, the TIMER0 register is only accessible from a... + // 0x00000002 [1] SNIFF_S (1) If 1, the sniffer can see data transfers from Secure... + // 0x00000001 [0] SNIFF_P (1) If 1, the sniffer can see data transfers from Privileged... + io_rw_32 seccfg_misc; + + uint32_t _pad2[11]; + + _REG_(DMA_MPU_CTRL_OFFSET) // DMA_MPU_CTRL + // Control register for DMA MPU + // 0x00000008 [3] NS_HIDE_ADDR (0) By default, when a region's S bit is clear,... + // 0x00000004 [2] S (0) Determine whether an address not covered by an active... + // 0x00000002 [1] P (0) Determine whether an address not covered by an active... + io_rw_32 mpu_ctrl; + + dma_mpu_region_hw_t mpu_region[8]; +} dma_hw_t; + +#define dma_hw ((dma_hw_t *)DMA_BASE) +static_assert(sizeof (dma_hw_t) == 0x0544, ""); + +#endif // _HARDWARE_STRUCTS_DMA_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/dma_debug.h b/src/rp2350/hardware_structs/include/hardware/structs/dma_debug.h new file mode 100644 index 000000000..73c8bf43e --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/dma_debug.h @@ -0,0 +1,47 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H +#define _HARDWARE_STRUCTS_DMA_DEBUG_H + +/** + * \file rp2350/dma_debug.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ + // Read: get channel DREQ counter (i + // 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00) + io_rw_32 dbg_ctdreq; + + _REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR + // Read to get channel TRANS_COUNT reload value, i + // 0xffffffff [31:0] CH0_DBG_TCR (0x00000000) + io_ro_32 dbg_tcr; + + uint32_t _pad0[14]; +} dma_debug_channel_hw_t; + +typedef struct { + dma_debug_channel_hw_t ch[16]; +} dma_debug_hw_t; + +#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/glitch_detector.h b/src/rp2350/hardware_structs/include/hardware/structs/glitch_detector.h new file mode 100644 index 000000000..f25ebb23a --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/glitch_detector.h @@ -0,0 +1,71 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_GLITCH_DETECTOR_H +#define _HARDWARE_STRUCTS_GLITCH_DETECTOR_H + +/** + * \file rp2350/glitch_detector.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/glitch_detector.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_glitch_detector +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/glitch_detector.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(GLITCH_DETECTOR_ARM_OFFSET) // GLITCH_DETECTOR_ARM + // Forcibly arm the glitch detectors, if they are not already armed by OTP + // 0x0000ffff [15:0] ARM (0x5bad) + io_rw_32 arm; + + _REG_(GLITCH_DETECTOR_DISARM_OFFSET) // GLITCH_DETECTOR_DISARM + // 0x0000ffff [15:0] DISARM (0x0000) Forcibly disarm the glitch detectors, if they are armed by OTP + io_rw_32 disarm; + + _REG_(GLITCH_DETECTOR_SENSITIVITY_OFFSET) // GLITCH_DETECTOR_SENSITIVITY + // Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults + // 0xff000000 [31:24] DEFAULT (0x00) + // 0x0000c000 [15:14] DET3_INV (0x0) Must be the inverse of DET3, else the default value is used + // 0x00003000 [13:12] DET2_INV (0x0) Must be the inverse of DET2, else the default value is used + // 0x00000c00 [11:10] DET1_INV (0x0) Must be the inverse of DET1, else the default value is used + // 0x00000300 [9:8] DET0_INV (0x0) Must be the inverse of DET0, else the default value is used + // 0x000000c0 [7:6] DET3 (0x0) Set sensitivity for detector 3 + // 0x00000030 [5:4] DET2 (0x0) Set sensitivity for detector 2 + // 0x0000000c [3:2] DET1 (0x0) Set sensitivity for detector 1 + // 0x00000003 [1:0] DET0 (0x0) Set sensitivity for detector 0 + io_rw_32 sensitivity; + + _REG_(GLITCH_DETECTOR_LOCK_OFFSET) // GLITCH_DETECTOR_LOCK + // 0x000000ff [7:0] LOCK (0x00) Write any nonzero value to disable writes to ARM,... + io_rw_32 lock; + + _REG_(GLITCH_DETECTOR_TRIG_STATUS_OFFSET) // GLITCH_DETECTOR_TRIG_STATUS + // Set when a detector output triggers + // 0x00000008 [3] DET3 (0) + // 0x00000004 [2] DET2 (0) + // 0x00000002 [1] DET1 (0) + // 0x00000001 [0] DET0 (0) + io_rw_32 trig_status; + + _REG_(GLITCH_DETECTOR_TRIG_FORCE_OFFSET) // GLITCH_DETECTOR_TRIG_FORCE + // Simulate the firing of one or more detectors + // 0x0000000f [3:0] TRIG_FORCE (0x0) + io_wo_32 trig_force; +} glitch_detector_hw_t; + +#define glitch_detector_hw ((glitch_detector_hw_t *)GLITCH_DETECTOR_BASE) +static_assert(sizeof (glitch_detector_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_GLITCH_DETECTOR_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/hstx_ctrl.h b/src/rp2350/hardware_structs/include/hardware/structs/hstx_ctrl.h new file mode 100644 index 000000000..735ecee7e --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/hstx_ctrl.h @@ -0,0 +1,70 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_HSTX_CTRL_H +#define _HARDWARE_STRUCTS_HSTX_CTRL_H + +/** + * \file rp2350/hstx_ctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/hstx_ctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_ctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/hstx_ctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(HSTX_CTRL_CSR_OFFSET) // HSTX_CTRL_CSR + // 0xf0000000 [31:28] CLKDIV (0x1) Clock period of the generated clock, measured in HSTX... + // 0x0f000000 [27:24] CLKPHASE (0x0) Set the initial phase of the generated clock + // 0x001f0000 [20:16] N_SHIFTS (0x05) Number of times to shift the shift register before... + // 0x00001f00 [12:8] SHIFT (0x06) How many bits to right-rotate the shift register by each cycle + // 0x00000060 [6:5] COUPLED_SEL (0x0) Select which PIO to use for coupled mode operation + // 0x00000010 [4] COUPLED_MODE (0) Enable the PIO-to-HSTX 1:1 connection + // 0x00000002 [1] EXPAND_EN (0) Enable the command expander + // 0x00000001 [0] EN (0) When EN is 1, the HSTX will shift out data as it appears... + io_rw_32 csr; + + // (Description copied from array index 0 register HSTX_CTRL_BIT0 applies similarly to other array indexes) + _REG_(HSTX_CTRL_BIT0_OFFSET) // HSTX_CTRL_BIT0 + // Data control register for output bit 0 + // 0x00020000 [17] CLK (0) Connect this output to the generated clock, rather than... + // 0x00010000 [16] INV (0) Invert this data output (logical NOT) + // 0x00001f00 [12:8] SEL_N (0x00) Shift register data bit select for the second half of... + // 0x0000001f [4:0] SEL_P (0x00) Shift register data bit select for the first half of the... + io_rw_32 bit[8]; + + _REG_(HSTX_CTRL_EXPAND_SHIFT_OFFSET) // HSTX_CTRL_EXPAND_SHIFT + // Configure the optional shifter inside the command expander + // 0x1f000000 [28:24] ENC_N_SHIFTS (0x01) Number of times to consume from the shift register... + // 0x001f0000 [20:16] ENC_SHIFT (0x00) How many bits to right-rotate the shift register by each... + // 0x00001f00 [12:8] RAW_N_SHIFTS (0x01) Number of times to consume from the shift register... + // 0x0000001f [4:0] RAW_SHIFT (0x00) How many bits to right-rotate the shift register by each... + io_rw_32 expand_shift; + + _REG_(HSTX_CTRL_EXPAND_TMDS_OFFSET) // HSTX_CTRL_EXPAND_TMDS + // Configure the optional TMDS encoder inside the command expander + // 0x00e00000 [23:21] L2_NBITS (0x0) Number of valid data bits for the lane 2 TMDS encoder,... + // 0x001f0000 [20:16] L2_ROT (0x00) Right-rotate applied to the current shifter data before... + // 0x0000e000 [15:13] L1_NBITS (0x0) Number of valid data bits for the lane 1 TMDS encoder,... + // 0x00001f00 [12:8] L1_ROT (0x00) Right-rotate applied to the current shifter data before... + // 0x000000e0 [7:5] L0_NBITS (0x0) Number of valid data bits for the lane 0 TMDS encoder,... + // 0x0000001f [4:0] L0_ROT (0x00) Right-rotate applied to the current shifter data before... + io_rw_32 expand_tmds; +} hstx_ctrl_hw_t; + +#define hstx_ctrl_hw ((hstx_ctrl_hw_t *)HSTX_CTRL_BASE) +static_assert(sizeof (hstx_ctrl_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_HSTX_CTRL_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/hstx_fifo.h b/src/rp2350/hardware_structs/include/hardware/structs/hstx_fifo.h new file mode 100644 index 000000000..a8399fad3 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/hstx_fifo.h @@ -0,0 +1,45 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_HSTX_FIFO_H +#define _HARDWARE_STRUCTS_HSTX_FIFO_H + +/** + * \file rp2350/hstx_fifo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/hstx_fifo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_fifo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/hstx_fifo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(HSTX_FIFO_STAT_OFFSET) // HSTX_FIFO_STAT + // FIFO status + // 0x00000400 [10] WOF (0) FIFO was written when full + // 0x00000200 [9] EMPTY (-) + // 0x00000100 [8] FULL (-) + // 0x000000ff [7:0] LEVEL (0x00) + io_rw_32 stat; + + _REG_(HSTX_FIFO_FIFO_OFFSET) // HSTX_FIFO_FIFO + // Write access to FIFO + // 0xffffffff [31:0] FIFO (0x00000000) + io_wo_32 fifo; +} hstx_fifo_hw_t; + +#define hstx_fifo_hw ((hstx_fifo_hw_t *)HSTX_FIFO_BASE) +static_assert(sizeof (hstx_fifo_hw_t) == 0x0008, ""); + +#endif // _HARDWARE_STRUCTS_HSTX_FIFO_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/i2c.h b/src/rp2350/hardware_structs/include/hardware/structs/i2c.h new file mode 100644 index 000000000..7cd990dbf --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/i2c.h @@ -0,0 +1,338 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_I2C_H +#define _HARDWARE_STRUCTS_I2C_H + +/** + * \file rp2350/i2c.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/i2c.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_i2c +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON + // I2C Control Register + // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... + // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... + // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... + // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... + // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... + // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... + // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... + // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... + // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... + // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled + io_rw_32 con; + + _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR + // I2C Target Address Register + // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... + // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... + // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction + io_rw_32 tar; + + _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR + // I2C Slave Address Register + // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... + io_rw_32 sar; + + uint32_t _pad0; + + _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD + // I2C Rx/Tx Data Buffer and Command Register + // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... + // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... + // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... + // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed + // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... + io_rw_32 data_cmd; + + _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT + // Standard Speed I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_hcnt; + + _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT + // Standard Speed I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_lcnt; + + _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_hcnt; + + _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_lcnt; + + uint32_t _pad1[2]; + + _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT + // I2C Interrupt Status Register + // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit + // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit + // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit + // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit + // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit + // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit + // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit + // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit + // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit + // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit + // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit + io_ro_32 intr_stat; + + _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK + // I2C Interrupt Mask Register + // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... + // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register + // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register + // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register + // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register + // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register + // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register + // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register + // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register + // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register + // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register + // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register + // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register + io_rw_32 intr_mask; + + _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT + // I2C Raw Interrupt Status Register + // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... + // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... + // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... + // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... + // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... + // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... + // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... + // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... + // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... + // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... + // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... + // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... + // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... + io_ro_32 raw_intr_stat; + + _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL + // I2C Receive FIFO Threshold Register + // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level + io_rw_32 rx_tl; + + _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL + // I2C Transmit FIFO Threshold Register + // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level + io_rw_32 tx_tl; + + _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR + // Clear Combined and Individual Interrupt Register + // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... + io_ro_32 clr_intr; + + _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER + // Clear RX_UNDER Interrupt Register + // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... + io_ro_32 clr_rx_under; + + _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER + // Clear RX_OVER Interrupt Register + // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... + io_ro_32 clr_rx_over; + + _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER + // Clear TX_OVER Interrupt Register + // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... + io_ro_32 clr_tx_over; + + _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ + // Clear RD_REQ Interrupt Register + // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... + io_ro_32 clr_rd_req; + + _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT + // Clear TX_ABRT Interrupt Register + // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... + io_ro_32 clr_tx_abrt; + + _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE + // Clear RX_DONE Interrupt Register + // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... + io_ro_32 clr_rx_done; + + _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY + // Clear ACTIVITY Interrupt Register + // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... + io_ro_32 clr_activity; + + _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET + // Clear STOP_DET Interrupt Register + // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... + io_ro_32 clr_stop_det; + + _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET + // Clear START_DET Interrupt Register + // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... + io_ro_32 clr_start_det; + + _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL + // Clear GEN_CALL Interrupt Register + // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... + io_ro_32 clr_gen_call; + + _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE + // I2C ENABLE Register + // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... + // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort + // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled + io_rw_32 enable; + + _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS + // I2C STATUS Register + // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status + // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status + // 0x00000010 [4] RFF (0) Receive FIFO Completely Full + // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty + // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty + // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full + // 0x00000001 [0] ACTIVITY (0) I2C Activity Status + io_ro_32 status; + + _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR + // I2C Transmit FIFO Level Register + // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level + io_ro_32 txflr; + + _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR + // I2C Receive FIFO Level Register + // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level + io_ro_32 rxflr; + + _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD + // I2C SDA Hold Time Length Register + // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... + // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... + io_rw_32 sda_hold; + + _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE + // I2C Transmit Abort Source Register + // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... + // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit + // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... + // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... + // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... + // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... + // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... + // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... + // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... + // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... + // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... + // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... + // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit + // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... + io_ro_32 tx_abrt_source; + + _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY + // Generate Slave Data NACK Register + // 0x00000001 [0] NACK (0) Generate NACK + io_rw_32 slv_data_nack_only; + + _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR + // DMA Control Register + // 0x00000002 [1] TDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RDMAE (0) Receive DMA Enable + io_rw_32 dma_cr; + + _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level + io_rw_32 dma_tdlr; + + _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level + io_rw_32 dma_rdlr; + + _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP + // I2C SDA Setup Register + // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup + io_rw_32 sda_setup; + + _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL + // I2C ACK General Call Register + // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call + io_rw_32 ack_general_call; + + _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS + // I2C Enable Status Register + // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost + // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) + // 0x00000001 [0] IC_EN (0) ic_en Status + io_ro_32 enable_status; + + _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN + // I2C SS, FS or FM+ spike suppression limit + // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... + io_rw_32 fs_spklen; + + uint32_t _pad2; + + _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET + // Clear RESTART_DET Interrupt Register + // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... + io_ro_32 clr_restart_det; + + uint32_t _pad3[18]; + + _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 + // Component Parameter Register 1 + // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 + // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 + // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible + // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled + // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs + // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode + // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE + // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits + io_ro_32 comp_param_1; + + _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION + // I2C Component Version Register + // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) + io_ro_32 comp_version; + + _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE + // I2C Component Type Register + // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 + io_ro_32 comp_type; +} i2c_hw_t; + +#define i2c0_hw ((i2c_hw_t *)I2C0_BASE) +#define i2c1_hw ((i2c_hw_t *)I2C1_BASE) +static_assert(sizeof (i2c_hw_t) == 0x0100, ""); + +#endif // _HARDWARE_STRUCTS_I2C_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/interp.h b/src/rp2350/hardware_structs/include/hardware/structs/interp.h new file mode 100644 index 000000000..eec0e3da6 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/interp.h @@ -0,0 +1,87 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +/** + * \file rp2350/interp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 + // Read/write access to accumulator 0 + // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) + io_rw_32 accum[2]; + + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // Read/write access to BASE0 register + // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) + io_rw_32 base[3]; + + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) + // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) + io_ro_32 pop[3]; + + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // Read LANE0 result, without altering any internal state (PEEK) + // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) + io_ro_32 peek[3]; + + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // Control register for lane 0 + // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core + // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... + // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... + // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... + // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... + // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... + // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] SHIFT (0x00) Right-rotate applied to accumulator before masking + io_rw_32 ctrl[2]; + + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // Values written here are atomically added to ACCUM0 + // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) + io_rw_32 add_raw[2]; + + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +#define interp_hw_array_ns ((interp_hw_t *)(SIO_NONSEC_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +static_assert(sizeof (interp_hw_t) == 0x0040, ""); +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif // _HARDWARE_STRUCTS_INTERP_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/io_bank0.h b/src/rp2350/hardware_structs/include/hardware/structs/io_bank0.h new file mode 100644 index 000000000..c5020e232 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/io_bank0.h @@ -0,0 +1,452 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_BANK0_H +#define _HARDWARE_STRUCTS_IO_BANK0_H + +/** + * \file rp2350/io_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief GPIO pin function selectors on RP2350 (used as typedef \ref gpio_function_t) + * \ingroup hardware_gpio + */ +typedef enum gpio_function_rp2350 { + GPIO_FUNC_HSTX = 0, ///< Select HSTX as GPIO pin function + GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function + GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function + GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function + GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function + GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function + GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function + GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function + GPIO_FUNC_PIO2 = 8, ///< Select PIO2 as GPIO pin function + GPIO_FUNC_GPCK = 9, ///< Select GPCK as GPIO pin function + GPIO_FUNC_XIP_CS1 = 9, ///< Select XIP CS1 as GPIO pin function + GPIO_FUNC_CORESIGHT_TRACE = 9, ///< Select CORESIGHT TRACE as GPIO pin function + GPIO_FUNC_USB = 10, ///< Select USB as GPIO pin function + GPIO_FUNC_UART_AUX = 11, ///< Select UART_AUX as GPIO pin function + GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function +} gpio_function_t; + +typedef struct { + _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 status; + + _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_bank0_status_ctrl_hw_t; + +typedef struct { + // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 inte[6]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intf[6]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_ro_32 ints[6]; +} io_bank0_irq_ctrl_hw_t; + +/// \tag::io_bank0_hw[] +typedef struct { + io_bank0_status_ctrl_hw_t io[48]; + + uint32_t _pad0[32]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc0_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc0_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc1_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc1_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_dormant_wake_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_dormant_wake_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) + _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 + // Raw Interrupts + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intr[6]; + + union { + struct { + io_bank0_irq_ctrl_hw_t proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t proc1_irq_ctrl; + io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_bank0_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_bank0_hw_t; +/// \end::io_bank0_hw[] + +#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE) +static_assert(sizeof (io_bank0_hw_t) == 0x0320, ""); + +#endif // _HARDWARE_STRUCTS_IO_BANK0_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/io_qspi.h b/src/rp2350/hardware_structs/include/hardware/structs/io_qspi.h new file mode 100644 index 000000000..cec2bba65 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/io_qspi.h @@ -0,0 +1,316 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_QSPI_H +#define _HARDWARE_STRUCTS_IO_QSPI_H + +/** + * \file rp2350/io_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief QSPI pin function selectors on RP2350 (used as typedef \ref gpio_function1_t) + */ +typedef enum gpio_function1_rp2350 { + GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function + GPIO_FUNC1_UART = 2, ///< Select UART as QSPI pin function + GPIO_FUNC1_I2C = 3, ///< Select I2C as QSPI pin function + GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function + GPIO_FUNC1_UART_AUX = 11, ///< Select UART_AUX as QSPI pin function + GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function +} gpio_function1_t; + +typedef struct { + _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 status; + + _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_qspi_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 inte; + + _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 intf; + + _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_ro_32 ints; +} io_qspi_irq_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 usbphy_dp_status; + + _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 usbphy_dp_ctrl; + + _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 usbphy_dm_status; + + _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 usbphy_dm_ctrl; + + io_qspi_status_ctrl_hw_t io[6]; + + uint32_t _pad0[112]; + + _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc0_secure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc0_nonsecure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc1_secure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc1_nonsecure; + + _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_dormant_wake_secure; + + _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_dormant_wake_nonsecure; + + _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR + // Raw Interrupts + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 intr; + + union { + struct { + io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; + io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; + io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_qspi_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_qspi_hw_t; + +#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) +static_assert(sizeof (io_qspi_hw_t) == 0x0240, ""); + +#endif // _HARDWARE_STRUCTS_IO_QSPI_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/iobank0.h b/src/rp2350/hardware_structs/include/hardware/structs/iobank0.h new file mode 100644 index 000000000..2dc31e38d --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/iobank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_bank0.h" +#define iobank0_hw io_bank0_hw \ No newline at end of file diff --git a/src/rp2350/hardware_structs/include/hardware/structs/ioqspi.h b/src/rp2350/hardware_structs/include/hardware/structs/ioqspi.h new file mode 100644 index 000000000..20cc74c79 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/ioqspi.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_qspi.h" +#define ioqspi_hw io_qspi_hw \ No newline at end of file diff --git a/src/rp2350/hardware_structs/include/hardware/structs/m33.h b/src/rp2350/hardware_structs/include/hardware/structs/m33.h new file mode 100644 index 000000000..d527c917f --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/m33.h @@ -0,0 +1,1651 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M33_H +#define _HARDWARE_STRUCTS_M33_H + +/** + * \file rp2350/m33.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + // (Description copied from array index 0 register M33_ITM_STIM0 applies similarly to other array indexes) + _REG_(M33_ITM_STIM0_OFFSET) // M33_ITM_STIM0 + // ITM Stimulus Port Register 0 + // 0xffffffff [31:0] STIMULUS (0x00000000) Data to write to the Stimulus Port FIFO, for forwarding... + io_rw_32 itm_stim[32]; + + uint32_t _pad0[864]; + + _REG_(M33_ITM_TER0_OFFSET) // M33_ITM_TER0 + // Provide an individual enable bit for each ITM_STIM register + // 0xffffffff [31:0] STIMENA (0x00000000) For STIMENA[m] in ITM_TER*n, controls whether... + io_rw_32 itm_ter0; + + uint32_t _pad1[15]; + + _REG_(M33_ITM_TPR_OFFSET) // M33_ITM_TPR + // Controls which stimulus ports can be accessed by unprivileged code + // 0x0000000f [3:0] PRIVMASK (0x0) Bit mask to enable tracing on ITM stimulus ports + io_rw_32 itm_tpr; + + uint32_t _pad2[15]; + + _REG_(M33_ITM_TCR_OFFSET) // M33_ITM_TCR + // Configures and controls transfers through the ITM interface + // 0x00800000 [23] BUSY (0) Indicates whether the ITM is currently processing events + // 0x007f0000 [22:16] TRACEBUSID (0x00) Identifier for multi-source trace stream formatting + // 0x00000c00 [11:10] GTSFREQ (0x0) Defines how often the ITM generates a global timestamp,... + // 0x00000300 [9:8] TSPRESCALE (0x0) Local timestamp prescaler, used with the trace packet... + // 0x00000020 [5] STALLENA (0) Stall the PE to guarantee delivery of Data Trace packets + // 0x00000010 [4] SWOENA (0) Enables asynchronous clocking of the timestamp counter + // 0x00000008 [3] TXENA (0) Enables forwarding of hardware event packet from the DWT... + // 0x00000004 [2] SYNCENA (0) Enables Synchronization packet transmission for a... + // 0x00000002 [1] TSENA (0) Enables Local timestamp generation + // 0x00000001 [0] ITMENA (0) Enables the ITM + io_rw_32 itm_tcr; + + uint32_t _pad3[27]; + + _REG_(M33_INT_ATREADY_OFFSET) // M33_INT_ATREADY + // Integration Mode: Read ATB Ready + // 0x00000002 [1] AFVALID (0) A read of this bit returns the value of AFVALID + // 0x00000001 [0] ATREADY (0) A read of this bit returns the value of ATREADY + io_ro_32 int_atready; + + uint32_t _pad4; + + _REG_(M33_INT_ATVALID_OFFSET) // M33_INT_ATVALID + // Integration Mode: Write ATB Valid + // 0x00000002 [1] AFREADY (0) A write to this bit gives the value of AFREADY + // 0x00000001 [0] ATREADY (0) A write to this bit gives the value of ATVALID + io_rw_32 int_atvalid; + + uint32_t _pad5; + + _REG_(M33_ITM_ITCTRL_OFFSET) // M33_ITM_ITCTRL + // Integration Mode Control Register + // 0x00000001 [0] IME (0) Integration mode enable bit - The possible values are: ... + io_rw_32 itm_itctrl; + + uint32_t _pad6[46]; + + _REG_(M33_ITM_DEVARCH_OFFSET) // M33_ITM_DEVARCH + // Provides CoreSight discovery information for the ITM + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa01) Defines the architecture of the component + io_ro_32 itm_devarch; + + uint32_t _pad7[3]; + + _REG_(M33_ITM_DEVTYPE_OFFSET) // M33_ITM_DEVTYPE + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] SUB (0x4) Component sub-type + // 0x0000000f [3:0] MAJOR (0x3) Component major type + io_ro_32 itm_devtype; + + _REG_(M33_ITM_PIDR4_OFFSET) // M33_ITM_PIDR4 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 itm_pidr4; + + _REG_(M33_ITM_PIDR5_OFFSET) // M33_ITM_PIDR5 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR5 (0x00000000) + io_rw_32 itm_pidr5; + + _REG_(M33_ITM_PIDR6_OFFSET) // M33_ITM_PIDR6 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR6 (0x00000000) + io_rw_32 itm_pidr6; + + _REG_(M33_ITM_PIDR7_OFFSET) // M33_ITM_PIDR7 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR7 (0x00000000) + io_rw_32 itm_pidr7; + + _REG_(M33_ITM_PIDR0_OFFSET) // M33_ITM_PIDR0 + // Provides CoreSight discovery information for the ITM + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 itm_pidr0; + + _REG_(M33_ITM_PIDR1_OFFSET) // M33_ITM_PIDR1 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 itm_pidr1; + + _REG_(M33_ITM_PIDR2_OFFSET) // M33_ITM_PIDR2 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 itm_pidr2; + + _REG_(M33_ITM_PIDR3_OFFSET) // M33_ITM_PIDR3 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 itm_pidr3; + + // (Description copied from array index 0 register M33_ITM_CIDR0 applies similarly to other array indexes) + _REG_(M33_ITM_CIDR0_OFFSET) // M33_ITM_CIDR0 + // Provides CoreSight discovery information for the ITM + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 itm_cidr[4]; + + _REG_(M33_DWT_CTRL_OFFSET) // M33_DWT_CTRL + // Provides configuration and status information for the DWT unit, and used to control features of the unit + // 0xf0000000 [31:28] NUMCOMP (0x7) Number of DWT comparators implemented + // 0x08000000 [27] NOTRCPKT (0) Indicates whether the implementation does not support trace + // 0x04000000 [26] NOEXTTRIG (0) Reserved, RAZ + // 0x02000000 [25] NOCYCCNT (1) Indicates whether the implementation does not include a... + // 0x01000000 [24] NOPRFCNT (1) Indicates whether the implementation does not include... + // 0x00800000 [23] CYCDISS (0) Controls whether the cycle counter is disabled in Secure state + // 0x00400000 [22] CYCEVTENA (1) Enables Event Counter packet generation on POSTCNT underflow + // 0x00200000 [21] FOLDEVTENA (1) Enables DWT_FOLDCNT counter + // 0x00100000 [20] LSUEVTENA (1) Enables DWT_LSUCNT counter + // 0x00080000 [19] SLEEPEVTENA (0) Enable DWT_SLEEPCNT counter + // 0x00040000 [18] EXCEVTENA (1) Enables DWT_EXCCNT counter + // 0x00020000 [17] CPIEVTENA (0) Enables DWT_CPICNT counter + // 0x00010000 [16] EXTTRCENA (0) Enables generation of Exception Trace packets + // 0x00001000 [12] PCSAMPLENA (1) Enables use of POSTCNT counter as a timer for Periodic... + // 0x00000c00 [11:10] SYNCTAP (0x2) Selects the position of the synchronization packet... + // 0x00000200 [9] CYCTAP (0) Selects the position of the POSTCNT tap on the CYCCNT counter + // 0x000001e0 [8:5] POSTINIT (0x1) Initial value for the POSTCNT counter + // 0x0000001e [4:1] POSTPRESET (0x2) Reload value for the POSTCNT counter + // 0x00000001 [0] CYCCNTENA (0) Enables CYCCNT + io_rw_32 dwt_ctrl; + + _REG_(M33_DWT_CYCCNT_OFFSET) // M33_DWT_CYCCNT + // Shows or sets the value of the processor cycle counter, CYCCNT + // 0xffffffff [31:0] CYCCNT (0x00000000) Increments one on each processor clock cycle when DWT_CTRL + io_rw_32 dwt_cyccnt; + + uint32_t _pad8; + + _REG_(M33_DWT_EXCCNT_OFFSET) // M33_DWT_EXCCNT + // Counts the total cycles spent in exception processing + // 0x000000ff [7:0] EXCCNT (0x00) Counts one on each cycle when all of the following are... + io_rw_32 dwt_exccnt; + + uint32_t _pad9; + + _REG_(M33_DWT_LSUCNT_OFFSET) // M33_DWT_LSUCNT + // Increments on the additional cycles required to execute all load or store instructions + // 0x000000ff [7:0] LSUCNT (0x00) Counts one on each cycle when all of the following are... + io_rw_32 dwt_lsucnt; + + _REG_(M33_DWT_FOLDCNT_OFFSET) // M33_DWT_FOLDCNT + // Increments on the additional cycles required to execute all load or store instructions + // 0x000000ff [7:0] FOLDCNT (0x00) Counts on each cycle when all of the following are true:... + io_rw_32 dwt_foldcnt; + + uint32_t _pad10; + + _REG_(M33_DWT_COMP0_OFFSET) // M33_DWT_COMP0 + // Provides a reference value for use by watchpoint comparator 0 + // 0xffffffff [31:0] DWT_COMP0 (0x00000000) + io_rw_32 dwt_comp0; + + uint32_t _pad11; + + _REG_(M33_DWT_FUNCTION0_OFFSET) // M33_DWT_FUNCTION0 + // Controls the operation of watchpoint comparator 0 + // 0xf8000000 [31:27] ID (0x0b) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function0; + + uint32_t _pad12; + + _REG_(M33_DWT_COMP1_OFFSET) // M33_DWT_COMP1 + // Provides a reference value for use by watchpoint comparator 1 + // 0xffffffff [31:0] DWT_COMP1 (0x00000000) + io_rw_32 dwt_comp1; + + uint32_t _pad13; + + _REG_(M33_DWT_FUNCTION1_OFFSET) // M33_DWT_FUNCTION1 + // Controls the operation of watchpoint comparator 1 + // 0xf8000000 [31:27] ID (0x11) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (1) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x2) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x8) Controls the type of match generated by this comparator + io_rw_32 dwt_function1; + + uint32_t _pad14; + + _REG_(M33_DWT_COMP2_OFFSET) // M33_DWT_COMP2 + // Provides a reference value for use by watchpoint comparator 2 + // 0xffffffff [31:0] DWT_COMP2 (0x00000000) + io_rw_32 dwt_comp2; + + uint32_t _pad15; + + _REG_(M33_DWT_FUNCTION2_OFFSET) // M33_DWT_FUNCTION2 + // Controls the operation of watchpoint comparator 2 + // 0xf8000000 [31:27] ID (0x0a) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function2; + + uint32_t _pad16; + + _REG_(M33_DWT_COMP3_OFFSET) // M33_DWT_COMP3 + // Provides a reference value for use by watchpoint comparator 3 + // 0xffffffff [31:0] DWT_COMP3 (0x00000000) + io_rw_32 dwt_comp3; + + uint32_t _pad17; + + _REG_(M33_DWT_FUNCTION3_OFFSET) // M33_DWT_FUNCTION3 + // Controls the operation of watchpoint comparator 3 + // 0xf8000000 [31:27] ID (0x04) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function3; + + uint32_t _pad18[984]; + + _REG_(M33_DWT_DEVARCH_OFFSET) // M33_DWT_DEVARCH + // Provides CoreSight discovery information for the DWT + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa02) Defines the architecture of the component + io_ro_32 dwt_devarch; + + uint32_t _pad19[3]; + + _REG_(M33_DWT_DEVTYPE_OFFSET) // M33_DWT_DEVTYPE + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) Component major type + io_ro_32 dwt_devtype; + + _REG_(M33_DWT_PIDR4_OFFSET) // M33_DWT_PIDR4 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 dwt_pidr4; + + _REG_(M33_DWT_PIDR5_OFFSET) // M33_DWT_PIDR5 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR5 (0x00000000) + io_rw_32 dwt_pidr5; + + _REG_(M33_DWT_PIDR6_OFFSET) // M33_DWT_PIDR6 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR6 (0x00000000) + io_rw_32 dwt_pidr6; + + _REG_(M33_DWT_PIDR7_OFFSET) // M33_DWT_PIDR7 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR7 (0x00000000) + io_rw_32 dwt_pidr7; + + _REG_(M33_DWT_PIDR0_OFFSET) // M33_DWT_PIDR0 + // Provides CoreSight discovery information for the DWT + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 dwt_pidr0; + + _REG_(M33_DWT_PIDR1_OFFSET) // M33_DWT_PIDR1 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 dwt_pidr1; + + _REG_(M33_DWT_PIDR2_OFFSET) // M33_DWT_PIDR2 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 dwt_pidr2; + + _REG_(M33_DWT_PIDR3_OFFSET) // M33_DWT_PIDR3 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 dwt_pidr3; + + // (Description copied from array index 0 register M33_DWT_CIDR0 applies similarly to other array indexes) + _REG_(M33_DWT_CIDR0_OFFSET) // M33_DWT_CIDR0 + // Provides CoreSight discovery information for the DWT + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 dwt_cidr[4]; + + _REG_(M33_FP_CTRL_OFFSET) // M33_FP_CTRL + // Provides FPB implementation information, and the global enable for the FPB unit + // 0xf0000000 [31:28] REV (0x6) Flash Patch and Breakpoint Unit architecture revision + // 0x00007000 [14:12] NUM_CODE_14_12_ (0x5) Indicates the number of implemented instruction address... + // 0x00000f00 [11:8] NUM_LIT (0x5) Indicates the number of implemented literal address comparators + // 0x000000f0 [7:4] NUM_CODE_7_4_ (0x8) Indicates the number of implemented instruction address... + // 0x00000002 [1] KEY (0) Writes to the FP_CTRL are ignored unless KEY is... + // 0x00000001 [0] ENABLE (0) Enables the FPB + io_rw_32 fp_ctrl; + + _REG_(M33_FP_REMAP_OFFSET) // M33_FP_REMAP + // Indicates whether the implementation supports Flash Patch remap and, if it does, holds the... + // 0x20000000 [29] RMPSPT (0) Indicates whether the FPB unit supports the Flash Patch... + // 0x1fffffe0 [28:5] REMAP (0x000000) Holds the bits[28:5] of the Flash Patch remap address + io_ro_32 fp_remap; + + // (Description copied from array index 0 register M33_FP_COMP0 applies similarly to other array indexes) + _REG_(M33_FP_COMP0_OFFSET) // M33_FP_COMP0 + // Holds an address for comparison + // 0x00000001 [0] BE (0) Selects between flashpatch and breakpoint functionality + io_rw_32 fp_comp[8]; + + uint32_t _pad20[997]; + + _REG_(M33_FP_DEVARCH_OFFSET) // M33_FP_DEVARCH + // Provides CoreSight discovery information for the FPB + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa03) Defines the architecture of the component + io_ro_32 fp_devarch; + + uint32_t _pad21[3]; + + _REG_(M33_FP_DEVTYPE_OFFSET) // M33_FP_DEVTYPE + // Provides CoreSight discovery information for the FPB + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) Component major type + io_ro_32 fp_devtype; + + _REG_(M33_FP_PIDR4_OFFSET) // M33_FP_PIDR4 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 fp_pidr4; + + _REG_(M33_FP_PIDR5_OFFSET) // M33_FP_PIDR5 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR5 (0x00000000) + io_rw_32 fp_pidr5; + + _REG_(M33_FP_PIDR6_OFFSET) // M33_FP_PIDR6 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR6 (0x00000000) + io_rw_32 fp_pidr6; + + _REG_(M33_FP_PIDR7_OFFSET) // M33_FP_PIDR7 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR7 (0x00000000) + io_rw_32 fp_pidr7; + + _REG_(M33_FP_PIDR0_OFFSET) // M33_FP_PIDR0 + // Provides CoreSight discovery information for the FP + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 fp_pidr0; + + _REG_(M33_FP_PIDR1_OFFSET) // M33_FP_PIDR1 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 fp_pidr1; + + _REG_(M33_FP_PIDR2_OFFSET) // M33_FP_PIDR2 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 fp_pidr2; + + _REG_(M33_FP_PIDR3_OFFSET) // M33_FP_PIDR3 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 fp_pidr3; + + // (Description copied from array index 0 register M33_FP_CIDR0 applies similarly to other array indexes) + _REG_(M33_FP_CIDR0_OFFSET) // M33_FP_CIDR0 + // Provides CoreSight discovery information for the FP + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 fp_cidr[4]; + + uint32_t _pad22[11265]; + + _REG_(M33_ICTR_OFFSET) // M33_ICTR + // Provides information about the interrupt controller + // 0x0000000f [3:0] INTLINESNUM (0x1) Indicates the number of the highest implemented register... + io_ro_32 ictr; + + _REG_(M33_ACTLR_OFFSET) // M33_ACTLR + // Provides IMPLEMENTATION DEFINED configuration and control options + // 0x20000000 [29] EXTEXCLALL (0) External Exclusives Allowed with no MPU + // 0x00001000 [12] DISITMATBFLUSH (0) Disable ATB Flush + // 0x00000400 [10] FPEXCODIS (0) Disable FPU exception outputs + // 0x00000200 [9] DISOOFP (0) Disable out-of-order FP instruction completion + // 0x00000004 [2] DISFOLD (0) Disable dual-issue + // 0x00000001 [0] DISMCYCINT (0) Disable dual-issue + io_rw_32 actlr; + + uint32_t _pad23; + + _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 syst_csr; + + _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 syst_rvr; + + _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 syst_cvr; + + _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 syst_calib; + + uint32_t _pad24[56]; + + // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 + // Enables or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... + io_rw_32 nvic_iser[2]; + + uint32_t _pad25[30]; + + // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 + // Clears or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... + io_rw_32 nvic_icer[2]; + + uint32_t _pad26[30]; + + // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 + // Enables or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... + io_rw_32 nvic_ispr[2]; + + uint32_t _pad27[30]; + + // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 + // Clears or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... + io_rw_32 nvic_icpr[2]; + + uint32_t _pad28[30]; + + // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 + // For each group of 32 interrupts, shows the active state of each interrupt + // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... + io_rw_32 nvic_iabr[2]; + + uint32_t _pad29[30]; + + // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) + _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 + // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... + io_rw_32 nvic_itns[2]; + + uint32_t _pad30[30]; + + // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 + // Sets or reads interrupt priorities + // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... + io_rw_32 nvic_ipr[16]; + + uint32_t _pad31[560]; + + _REG_(M33_CPUID_OFFSET) // M33_CPUID + // Provides identification information for the PE, including an implementer code for the device and... + // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... + // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number + // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE + // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device + // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device + io_ro_32 cpuid; + + _REG_(M33_ICSR_OFFSET) // M33_ICSR + // Controls and provides status information for NMI, PendSV, SysTick and interrupts + // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending + // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared + // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending + // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS + // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending + // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS + // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... + // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... + // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... + // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... + // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... + // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception + io_rw_32 icsr; + + _REG_(M33_VTOR_OFFSET) // M33_VTOR + // Vector Table Offset Register + // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field + io_rw_32 vtor; + + _REG_(M33_AIRCR_OFFSET) // M33_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions + // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable + // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field + // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M33_SCR_OFFSET) // M33_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M33_CCR_OFFSET) // M33_CCR + // Sets or returns configuration and control data + // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS + // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... + // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS + // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... + // 0x00000200 [9] RES1 (1) Reserved, RES1 + // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... + // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... + // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses + // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... + // 0x00000001 [0] RES1_1 (1) Reserved, RES1 + io_rw_32 ccr; + + // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) + _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 + // Sets or returns priority for system handlers 4 - 7 + // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault + // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault + // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault + // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault + io_rw_32 shpr[3]; + + _REG_(M33_SHCSR_OFFSET) // M33_SHCSR + // Provides access to the active and pending status of system exceptions + // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS + // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception + // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled + // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS + // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled + // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS + // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS + // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception + // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS + // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... + // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS + // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS + // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception + // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS + // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception + // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception + // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS + // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... + // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception + // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS + io_rw_32 shcsr; + + _REG_(M33_CFSR_OFFSET) // M33_CFSR + // Contains the three Configurable Fault Status Registers + // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... + // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... + // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... + // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... + // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... + // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR + // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... + // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register + // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... + // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... + // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... + // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred + // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred + // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... + // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions + io_rw_32 cfsr; + + _REG_(M33_HFSR_OFFSET) // M33_HFSR + // Shows the cause of any HardFaults + // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred + // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... + // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... + io_rw_32 hfsr; + + _REG_(M33_DFSR_OFFSET) // M33_DFSR + // Shows which debug event occurred + // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... + // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... + // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... + // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... + // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... + io_rw_32 dfsr; + + _REG_(M33_MMFAR_OFFSET) // M33_MMFAR + // Shows the address of the memory location that caused an MPU fault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 mmfar; + + _REG_(M33_BFAR_OFFSET) // M33_BFAR + // Shows the address associated with a precise data access BusFault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 bfar; + + uint32_t _pad32; + + // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) + _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 + // Gives top-level information about the instruction set supported by the PE + // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support + // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support + io_ro_32 id_pfr[2]; + + _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 + // Provides top level information about the debug system + // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture + io_ro_32 id_dfr0; + + _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 + // Provides information about the IMPLEMENTATION DEFINED features of the PE + // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning + // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning + // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning + // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning + io_ro_32 id_afr0; + + // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) + _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 + // Provides information about the implemented memory model and memory management support + // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers + // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) + // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented + // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented + // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... + io_ro_32 id_mmfr[4]; + + // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) + _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 + // Provides information about the instruction set implemented by the PE + // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions + // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions + // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions + // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions + // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions + // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions + io_ro_32 id_isar[6]; + + uint32_t _pad33; + + _REG_(M33_CTR_OFFSET) // M33_CTR + // Provides information about the architecture of the caches + // 0x80000000 [31] RES1 (1) Reserved, RES1 + // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... + // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... + // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... + // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 + // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... + io_ro_32 ctr; + + uint32_t _pad34[2]; + + _REG_(M33_CPACR_OFFSET) // M33_CPACR + // Specifies the access privileges for coprocessors and the FP Extension + // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored + // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality + // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 + // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 + // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 + // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 + // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 + // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 + // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 + // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 + io_rw_32 cpacr; + + _REG_(M33_NSACR_OFFSET) // M33_NSACR + // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 + // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 + // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 + // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 + // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 + // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 + // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 + // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 + io_rw_32 nsacr; + + _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE + // The MPU Type Register indicates how many regions the MPU `FTSSS supports + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... + io_ro_32 mpu_type; + + _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL + // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... + // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 mpu_ctrl; + + _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR + // Selects the region currently accessed by MPU_RBAR and MPU_RLAR + // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + io_rw_32 mpu_rnr; + + _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR + // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar; + + _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR + // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar; + + _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a1; + + _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a1; + + _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a2; + + _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a2; + + _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a3; + + _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a3; + + uint32_t _pad35; + + // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) + _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 + // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 + // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 + // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 + // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 + io_rw_32 mpu_mair[2]; + + uint32_t _pad36[2]; + + _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL + // Allows enabling of the Security Attribution Unit + // 0x00000002 [1] ALLNS (0) When SAU_CTRL + // 0x00000001 [0] ENABLE (0) Enables the SAU + io_rw_32 sau_ctrl; + + _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE + // Indicates the number of regions implemented by the Security Attribution Unit + // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions + io_ro_32 sau_type; + + _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR + // Selects the region currently accessed by SAU_RBAR and SAU_RLAR + // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + io_rw_32 sau_rnr; + + _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR + // Provides indirect read and write access to the base address of the currently selected SAU region + // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region + io_rw_32 sau_rbar; + + _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR + // Provides indirect read and write access to the limit address of the currently selected SAU region + // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... + // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... + // 0x00000001 [0] ENABLE (0) SAU region enable + io_rw_32 sau_rlar; + + _REG_(M33_SFSR_OFFSET) // M33_SFSR + // Provides information about any security related faults + // 0x00000080 [7] LSERR (0) Sticky flag indicating that an error occurred during... + // 0x00000040 [6] SFARVALID (0) This bit is set when the SFAR register contains a valid value + // 0x00000020 [5] LSPERR (0) Stick flag indicating that an SAU or IDAU violation... + // 0x00000010 [4] INVTRAN (0) Sticky flag indicating that an exception was raised due... + // 0x00000008 [3] AUVIOL (0) Sticky flag indicating that an attempt was made to... + // 0x00000004 [2] INVER (0) This can be caused by EXC_RETURN + // 0x00000002 [1] INVIS (0) This bit is set if the integrity signature in an... + // 0x00000001 [0] INVEP (0) This bit is set if a function call from the Non-secure... + io_rw_32 sfsr; + + _REG_(M33_SFAR_OFFSET) // M33_SFAR + // Shows the address of the memory location that caused a Security violation + // 0xffffffff [31:0] ADDRESS (0x00000000) The address of an access that caused a attribution unit violation + io_rw_32 sfar; + + uint32_t _pad37; + + _REG_(M33_DHCSR_OFFSET) // M33_DHCSR + // Controls halting debug + // 0x04000000 [26] S_RESTART_ST (0) Indicates the PE has processed a request to clear DHCSR + // 0x02000000 [25] S_RESET_ST (0) Indicates whether the PE has been reset since the last... + // 0x01000000 [24] S_RETIRE_ST (0) Set to 1 every time the PE retires one of more instructions + // 0x00100000 [20] S_SDE (0) Indicates whether Secure invasive debug is allowed + // 0x00080000 [19] S_LOCKUP (0) Indicates whether the PE is in Lockup state + // 0x00040000 [18] S_SLEEP (0) Indicates whether the PE is sleeping + // 0x00020000 [17] S_HALT (0) Indicates whether the PE is in Debug state + // 0x00010000 [16] S_REGRDY (0) Handshake flag to transfers through the DCRDR + // 0x00000020 [5] C_SNAPSTALL (0) Allow imprecise entry to Debug state + // 0x00000008 [3] C_MASKINTS (0) When debug is enabled, the debugger can write to this... + // 0x00000004 [2] C_STEP (0) Enable single instruction step + // 0x00000002 [1] C_HALT (0) PE enter Debug state halt request + // 0x00000001 [0] C_DEBUGEN (0) Enable Halting debug + io_rw_32 dhcsr; + + _REG_(M33_DCRSR_OFFSET) // M33_DCRSR + // With the DCRDR, provides debug access to the general-purpose registers, special-purpose... + // 0x00010000 [16] REGWNR (0) Specifies the access type for the transfer + // 0x0000007f [6:0] REGSEL (0x00) Specifies the general-purpose register, special-purpose... + io_rw_32 dcrsr; + + _REG_(M33_DCRDR_OFFSET) // M33_DCRDR + // With the DCRSR, provides debug access to the general-purpose registers, special-purpose... + // 0xffffffff [31:0] DBGTMP (0x00000000) Provides debug access for reading and writing the... + io_rw_32 dcrdr; + + _REG_(M33_DEMCR_OFFSET) // M33_DEMCR + // Manages vector catch behavior and DebugMonitor handling when debugging + // 0x01000000 [24] TRCENA (0) Global enable for all DWT and ITM features + // 0x00100000 [20] SDME (0) Indicates whether the DebugMonitor targets the Secure or... + // 0x00080000 [19] MON_REQ (0) DebugMonitor semaphore bit + // 0x00040000 [18] MON_STEP (0) Enable DebugMonitor stepping + // 0x00020000 [17] MON_PEND (0) Sets or clears the pending state of the DebugMonitor exception + // 0x00010000 [16] MON_EN (0) Enable the DebugMonitor exception + // 0x00000800 [11] VC_SFERR (0) SecureFault exception halting debug vector catch enable + // 0x00000400 [10] VC_HARDERR (0) HardFault exception halting debug vector catch enable + // 0x00000200 [9] VC_INTERR (0) Enable halting debug vector catch for faults during... + // 0x00000100 [8] VC_BUSERR (0) BusFault exception halting debug vector catch enable + // 0x00000080 [7] VC_STATERR (0) Enable halting debug trap on a UsageFault exception... + // 0x00000040 [6] VC_CHKERR (0) Enable halting debug trap on a UsageFault exception... + // 0x00000020 [5] VC_NOCPERR (0) Enable halting debug trap on a UsageFault caused by an... + // 0x00000010 [4] VC_MMERR (0) Enable halting debug trap on a MemManage exception + // 0x00000001 [0] VC_CORERESET (0) Enable Reset Vector Catch + io_rw_32 demcr; + + uint32_t _pad38[2]; + + _REG_(M33_DSCSR_OFFSET) // M33_DSCSR + // Provides control and status information for Secure debug + // 0x00020000 [17] CDSKEY (0) Writes to the CDS bit are ignored unless CDSKEY is... + // 0x00010000 [16] CDS (0) This field indicates the current Security state of the processor + // 0x00000002 [1] SBRSEL (0) If SBRSELEN is 1 this bit selects whether the Non-secure... + // 0x00000001 [0] SBRSELEN (0) Controls whether the SBRSEL field or the current... + io_rw_32 dscsr; + + uint32_t _pad39[61]; + + _REG_(M33_STIR_OFFSET) // M33_STIR + // Provides a mechanism for software to generate an interrupt + // 0x000001ff [8:0] INTID (0x000) Indicates the interrupt to be pended + io_rw_32 stir; + + uint32_t _pad40[12]; + + _REG_(M33_FPCCR_OFFSET) // M33_FPCCR + // Holds control data for the Floating-point extension + // 0x80000000 [31] ASPEN (0) When this bit is set to 1, execution of a floating-point... + // 0x40000000 [30] LSPEN (0) Enables lazy context save of floating-point state + // 0x20000000 [29] LSPENS (1) This bit controls whether the LSPEN bit is writeable... + // 0x10000000 [28] CLRONRET (0) Clear floating-point caller saved registers on exception return + // 0x08000000 [27] CLRONRETS (0) This bit controls whether the CLRONRET bit is writeable... + // 0x04000000 [26] TS (0) Treat floating-point registers as Secure enable + // 0x00000400 [10] UFRDY (1) Indicates whether the software executing when the PE... + // 0x00000200 [9] SPLIMVIOL (0) This bit is banked between the Security states and... + // 0x00000100 [8] MONRDY (0) Indicates whether the software executing when the PE... + // 0x00000080 [7] SFRDY (0) Indicates whether the software executing when the PE... + // 0x00000040 [6] BFRDY (1) Indicates whether the software executing when the PE... + // 0x00000020 [5] MMRDY (1) Indicates whether the software executing when the PE... + // 0x00000010 [4] HFRDY (1) Indicates whether the software executing when the PE... + // 0x00000008 [3] THREAD (0) Indicates the PE mode when it allocated the... + // 0x00000004 [2] S (0) Security status of the floating-point context + // 0x00000002 [1] USER (1) Indicates the privilege level of the software executing... + // 0x00000001 [0] LSPACT (0) Indicates whether lazy preservation of the... + io_rw_32 fpccr; + + _REG_(M33_FPCAR_OFFSET) // M33_FPCAR + // Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + // 0xfffffff8 [31:3] ADDRESS (0x00000000) The location of the unpopulated floating-point register... + io_rw_32 fpcar; + + _REG_(M33_FPDSCR_OFFSET) // M33_FPDSCR + // Holds the default values for the floating-point status control data that the PE assigns to the... + // 0x04000000 [26] AHP (0) Default value for FPSCR + // 0x02000000 [25] DN (0) Default value for FPSCR + // 0x01000000 [24] FZ (0) Default value for FPSCR + // 0x00c00000 [23:22] RMODE (0x0) Default value for FPSCR + io_rw_32 fpdscr; + + // (Description copied from array index 0 register M33_MVFR0 applies similarly to other array indexes) + _REG_(M33_MVFR0_OFFSET) // M33_MVFR0 + // Describes the features provided by the Floating-point Extension + // 0xf0000000 [31:28] FPROUND (0x6) Indicates the rounding modes supported by the FP Extension + // 0x00f00000 [23:20] FPSQRT (0x5) Indicates the support for FP square root operations + // 0x000f0000 [19:16] FPDIVIDE (0x4) Indicates the support for FP divide operations + // 0x00000f00 [11:8] FPDP (0x6) Indicates support for FP double-precision operations + // 0x000000f0 [7:4] FPSP (0x0) Indicates support for FP single-precision operations + // 0x0000000f [3:0] SIMDREG (0x1) Indicates size of FP register file + io_ro_32 mvfr[3]; + + uint32_t _pad41[28]; + + _REG_(M33_DDEVARCH_OFFSET) // M33_DDEVARCH + // Provides CoreSight discovery information for the SCS + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x2) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa04) Defines the architecture of the component + io_ro_32 ddevarch; + + uint32_t _pad42[3]; + + _REG_(M33_DDEVTYPE_OFFSET) // M33_DDEVTYPE + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) CoreSight major type + io_ro_32 ddevtype; + + _REG_(M33_DPIDR4_OFFSET) // M33_DPIDR4 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 dpidr4; + + _REG_(M33_DPIDR5_OFFSET) // M33_DPIDR5 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR5 (0x00000000) + io_rw_32 dpidr5; + + _REG_(M33_DPIDR6_OFFSET) // M33_DPIDR6 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR6 (0x00000000) + io_rw_32 dpidr6; + + _REG_(M33_DPIDR7_OFFSET) // M33_DPIDR7 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR7 (0x00000000) + io_rw_32 dpidr7; + + _REG_(M33_DPIDR0_OFFSET) // M33_DPIDR0 + // Provides CoreSight discovery information for the SCS + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 dpidr0; + + _REG_(M33_DPIDR1_OFFSET) // M33_DPIDR1 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 dpidr1; + + _REG_(M33_DPIDR2_OFFSET) // M33_DPIDR2 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 dpidr2; + + _REG_(M33_DPIDR3_OFFSET) // M33_DPIDR3 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 dpidr3; + + // (Description copied from array index 0 register M33_DCIDR0 applies similarly to other array indexes) + _REG_(M33_DCIDR0_OFFSET) // M33_DCIDR0 + // Provides CoreSight discovery information for the SCS + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 dcidr[4]; + + uint32_t _pad43[51201]; + + _REG_(M33_TRCPRGCTLR_OFFSET) // M33_TRCPRGCTLR + // Programming Control Register + // 0x00000001 [0] EN (0) Trace Unit Enable + io_rw_32 trcprgctlr; + + uint32_t _pad44; + + _REG_(M33_TRCSTATR_OFFSET) // M33_TRCSTATR + // The TRCSTATR indicates the ETM-Teal status + // 0x00000002 [1] PMSTABLE (0) Indicates whether the ETM-Teal registers are stable and... + // 0x00000001 [0] IDLE (0) Indicates that the trace unit is inactive + io_ro_32 trcstatr; + + _REG_(M33_TRCCONFIGR_OFFSET) // M33_TRCCONFIGR + // The TRCCONFIGR sets the basic tracing options for the trace unit + // 0x00001000 [12] RS (0) Return stack enable + // 0x00000800 [11] TS (0) Global timestamp tracing + // 0x000007e0 [10:5] COND (0x00) Conditional instruction tracing + // 0x00000010 [4] CCI (0) Cycle counting in instruction trace + // 0x00000008 [3] BB (0) Branch broadcast mode + io_rw_32 trcconfigr; + + uint32_t _pad45[3]; + + _REG_(M33_TRCEVENTCTL0R_OFFSET) // M33_TRCEVENTCTL0R + // The TRCEVENTCTL0R controls the tracing of events in the trace stream + // 0x00008000 [15] TYPE1 (0) Selects the resource type for event 1 + // 0x00000700 [10:8] SEL1 (0x0) Selects the resource number, based on the value of... + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000007 [2:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trceventctl0r; + + _REG_(M33_TRCEVENTCTL1R_OFFSET) // M33_TRCEVENTCTL1R + // The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + // 0x00001000 [12] LPOVERRIDE (0) Low power state behavior override + // 0x00000800 [11] ATB (0) ATB enabled + // 0x00000002 [1] INSTEN1 (0) One bit per event, to enable generation of an event... + // 0x00000001 [0] INSTEN0 (0) One bit per event, to enable generation of an event... + io_rw_32 trceventctl1r; + + uint32_t _pad46; + + _REG_(M33_TRCSTALLCTLR_OFFSET) // M33_TRCSTALLCTLR + // The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the... + // 0x00000400 [10] INSTPRIORITY (0) Reserved, RES0 + // 0x00000100 [8] ISTALL (0) Stall processor based on instruction trace buffer space + // 0x0000000c [3:2] LEVEL (0x0) Threshold at which stalling becomes active + io_rw_32 trcstallctlr; + + _REG_(M33_TRCTSCTLR_OFFSET) // M33_TRCTSCTLR + // The TRCTSCTLR controls the insertion of global timestamps into the trace stream + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trctsctlr; + + _REG_(M33_TRCSYNCPR_OFFSET) // M33_TRCSYNCPR + // The TRCSYNCPR specifies the period of trace synchronization of the trace streams + // 0x0000001f [4:0] PERIOD (0x0a) Defines the number of bytes of trace between trace... + io_ro_32 trcsyncpr; + + _REG_(M33_TRCCCCTLR_OFFSET) // M33_TRCCCCTLR + // The TRCCCCTLR sets the threshold value for instruction trace cycle counting + // 0x00000fff [11:0] THRESHOLD (0x000) Instruction trace cycle count threshold + io_rw_32 trcccctlr; + + uint32_t _pad47[17]; + + _REG_(M33_TRCVICTLR_OFFSET) // M33_TRCVICTLR + // The TRCVICTLR controls instruction trace filtering + // 0x00080000 [19] EXLEVEL_S3 (0) In Secure state, each bit controls whether instruction... + // 0x00010000 [16] EXLEVEL_S0 (0) In Secure state, each bit controls whether instruction... + // 0x00000800 [11] TRCERR (0) Selects whether a system error exception must always be traced + // 0x00000400 [10] TRCRESET (0) Selects whether a reset exception must always be traced + // 0x00000200 [9] SSSTATUS (0) Indicates the current status of the start/stop logic + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trcvictlr; + + uint32_t _pad48[47]; + + _REG_(M33_TRCCNTRLDVR0_OFFSET) // M33_TRCCNTRLDVR0 + // The TRCCNTRLDVR defines the reload value for the reduced function counter + // 0x0000ffff [15:0] VALUE (0x0000) Defines the reload value for the counter + io_rw_32 trccntrldvr0; + + uint32_t _pad49[15]; + + _REG_(M33_TRCIDR8_OFFSET) // M33_TRCIDR8 + // TRCIDR8 + // 0xffffffff [31:0] MAXSPEC (0x00000000) reads as `ImpDef + io_ro_32 trcidr8; + + _REG_(M33_TRCIDR9_OFFSET) // M33_TRCIDR9 + // TRCIDR9 + // 0xffffffff [31:0] NUMP0KEY (0x00000000) reads as `ImpDef + io_ro_32 trcidr9; + + _REG_(M33_TRCIDR10_OFFSET) // M33_TRCIDR10 + // TRCIDR10 + // 0xffffffff [31:0] NUMP1KEY (0x00000000) reads as `ImpDef + io_ro_32 trcidr10; + + _REG_(M33_TRCIDR11_OFFSET) // M33_TRCIDR11 + // TRCIDR11 + // 0xffffffff [31:0] NUMP1SPC (0x00000000) reads as `ImpDef + io_ro_32 trcidr11; + + _REG_(M33_TRCIDR12_OFFSET) // M33_TRCIDR12 + // TRCIDR12 + // 0xffffffff [31:0] NUMCONDKEY (0x00000001) reads as `ImpDef + io_ro_32 trcidr12; + + _REG_(M33_TRCIDR13_OFFSET) // M33_TRCIDR13 + // TRCIDR13 + // 0xffffffff [31:0] NUMCONDSPC (0x00000000) reads as `ImpDef + io_ro_32 trcidr13; + + uint32_t _pad50[10]; + + _REG_(M33_TRCIMSPEC_OFFSET) // M33_TRCIMSPEC + // The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any... + // 0x0000000f [3:0] SUPPORT (0x0) Reserved, RES0 + io_ro_32 trcimspec; + + uint32_t _pad51[7]; + + _REG_(M33_TRCIDR0_OFFSET) // M33_TRCIDR0 + // TRCIDR0 + // 0x20000000 [29] COMMOPT (1) reads as `ImpDef + // 0x1f000000 [28:24] TSSIZE (0x08) reads as `ImpDef + // 0x00020000 [17] TRCEXDATA (0) reads as `ImpDef + // 0x00018000 [16:15] QSUPP (0x0) reads as `ImpDef + // 0x00004000 [14] QFILT (0) reads as `ImpDef + // 0x00003000 [13:12] CONDTYPE (0x0) reads as `ImpDef + // 0x00000c00 [11:10] NUMEVENT (0x1) reads as `ImpDef + // 0x00000200 [9] RETSTACK (1) reads as `ImpDef + // 0x00000080 [7] TRCCCI (1) reads as `ImpDef + // 0x00000040 [6] TRCCOND (1) reads as `ImpDef + // 0x00000020 [5] TRCBB (1) reads as `ImpDef + // 0x00000018 [4:3] TRCDATA (0x0) reads as `ImpDef + // 0x00000006 [2:1] INSTP0 (0x0) reads as `ImpDef + // 0x00000001 [0] RES1 (1) Reserved, RES1 + io_ro_32 trcidr0; + + _REG_(M33_TRCIDR1_OFFSET) // M33_TRCIDR1 + // TRCIDR1 + // 0xff000000 [31:24] DESIGNER (0x41) reads as `ImpDef + // 0x0000f000 [15:12] RES1 (0xf) Reserved, RES1 + // 0x00000f00 [11:8] TRCARCHMAJ (0x4) reads as 0b0100 + // 0x000000f0 [7:4] TRCARCHMIN (0x2) reads as 0b0000 + // 0x0000000f [3:0] REVISION (0x1) reads as `ImpDef + io_ro_32 trcidr1; + + _REG_(M33_TRCIDR2_OFFSET) // M33_TRCIDR2 + // TRCIDR2 + // 0x1e000000 [28:25] CCSIZE (0x0) reads as `ImpDef + // 0x01f00000 [24:20] DVSIZE (0x00) reads as `ImpDef + // 0x000f8000 [19:15] DASIZE (0x00) reads as `ImpDef + // 0x00007c00 [14:10] VMIDSIZE (0x00) reads as `ImpDef + // 0x000003e0 [9:5] CIDSIZE (0x00) reads as `ImpDef + // 0x0000001f [4:0] IASIZE (0x04) reads as `ImpDef + io_ro_32 trcidr2; + + _REG_(M33_TRCIDR3_OFFSET) // M33_TRCIDR3 + // TRCIDR3 + // 0x80000000 [31] NOOVERFLOW (0) reads as `ImpDef + // 0x70000000 [30:28] NUMPROC (0x0) reads as `ImpDef + // 0x08000000 [27] SYSSTALL (1) reads as `ImpDef + // 0x04000000 [26] STALLCTL (1) reads as `ImpDef + // 0x02000000 [25] SYNCPR (1) reads as `ImpDef + // 0x01000000 [24] TRCERR (1) reads as `ImpDef + // 0x00f00000 [23:20] EXLEVEL_NS (0x0) reads as `ImpDef + // 0x000f0000 [19:16] EXLEVEL_S (0x9) reads as `ImpDef + // 0x00000fff [11:0] CCITMIN (0x004) reads as `ImpDef + io_ro_32 trcidr3; + + _REG_(M33_TRCIDR4_OFFSET) // M33_TRCIDR4 + // TRCIDR4 + // 0xf0000000 [31:28] NUMVMIDC (0x0) reads as `ImpDef + // 0x0f000000 [27:24] NUMCIDC (0x0) reads as `ImpDef + // 0x00f00000 [23:20] NUMSSCC (0x1) reads as `ImpDef + // 0x000f0000 [19:16] NUMRSPAIR (0x1) reads as `ImpDef + // 0x0000f000 [15:12] NUMPC (0x4) reads as `ImpDef + // 0x00000100 [8] SUPPDAC (0) reads as `ImpDef + // 0x000000f0 [7:4] NUMDVC (0x0) reads as `ImpDef + // 0x0000000f [3:0] NUMACPAIRS (0x0) reads as `ImpDef + io_ro_32 trcidr4; + + _REG_(M33_TRCIDR5_OFFSET) // M33_TRCIDR5 + // TRCIDR5 + // 0x80000000 [31] REDFUNCNTR (1) reads as `ImpDef + // 0x70000000 [30:28] NUMCNTR (0x1) reads as `ImpDef + // 0x0e000000 [27:25] NUMSEQSTATE (0x0) reads as `ImpDef + // 0x00800000 [23] LPOVERRIDE (1) reads as `ImpDef + // 0x00400000 [22] ATBTRIG (1) reads as `ImpDef + // 0x003f0000 [21:16] TRACEIDSIZE (0x07) reads as 0x07 + // 0x00000e00 [11:9] NUMEXTINSEL (0x0) reads as `ImpDef + // 0x000001ff [8:0] NUMEXTIN (0x004) reads as `ImpDef + io_ro_32 trcidr5; + + _REG_(M33_TRCIDR6_OFFSET) // M33_TRCIDR6 + // TRCIDR6 + // 0x00000000 [31:0] TRCIDR6 (0x00000000) + io_rw_32 trcidr6; + + _REG_(M33_TRCIDR7_OFFSET) // M33_TRCIDR7 + // TRCIDR7 + // 0x00000000 [31:0] TRCIDR7 (0x00000000) + io_rw_32 trcidr7; + + uint32_t _pad52[2]; + + // (Description copied from array index 0 register M33_TRCRSCTLR2 applies similarly to other array indexes) + _REG_(M33_TRCRSCTLR2_OFFSET) // M33_TRCRSCTLR2 + // The TRCRSCTLR controls the trace resources + // 0x00200000 [21] PAIRINV (0) Inverts the result of a combined pair of resources + // 0x00100000 [20] INV (0) Inverts the selected resources + // 0x00070000 [18:16] GROUP (0x0) Selects a group of resource + // 0x000000ff [7:0] SELECT (0x00) Selects one or more resources from the wanted group + io_rw_32 trcrsctlr[2]; + + uint32_t _pad53[36]; + + _REG_(M33_TRCSSCSR_OFFSET) // M33_TRCSSCSR + // Controls the corresponding single-shot comparator resource + // 0x80000000 [31] STATUS (0) Single-shot status bit + // 0x00000008 [3] PC (0) Reserved, RES1 + // 0x00000004 [2] DV (0) Reserved, RES0 + // 0x00000002 [1] DA (0) Reserved, RES0 + // 0x00000001 [0] INST (0) Reserved, RES0 + io_rw_32 trcsscsr; + + uint32_t _pad54[7]; + + _REG_(M33_TRCSSPCICR_OFFSET) // M33_TRCSSPCICR + // Selects the PE comparator inputs for Single-shot control + // 0x0000000f [3:0] PC (0x0) Selects one or more PE comparator inputs for Single-shot control + io_rw_32 trcsspcicr; + + uint32_t _pad55[19]; + + _REG_(M33_TRCPDCR_OFFSET) // M33_TRCPDCR + // Requests the system to provide power to the trace unit + // 0x00000008 [3] PU (0) Powerup request bit: + io_rw_32 trcpdcr; + + _REG_(M33_TRCPDSR_OFFSET) // M33_TRCPDSR + // Returns the following information about the trace unit: - OS Lock status + // 0x00000020 [5] OSLK (0) OS Lock status bit: + // 0x00000002 [1] STICKYPD (1) Sticky powerdown status bit + // 0x00000001 [0] POWER (1) Power status bit: + io_ro_32 trcpdsr; + + uint32_t _pad56[755]; + + _REG_(M33_TRCITATBIDR_OFFSET) // M33_TRCITATBIDR + // Trace Integration ATB Identification Register + // 0x0000007f [6:0] ID (0x00) Trace ID + io_rw_32 trcitatbidr; + + uint32_t _pad57[3]; + + _REG_(M33_TRCITIATBINR_OFFSET) // M33_TRCITIATBINR + // Trace Integration Instruction ATB In Register + // 0x00000002 [1] AFVALIDM (0) Integration Mode instruction AFVALIDM in + // 0x00000001 [0] ATREADYM (0) Integration Mode instruction ATREADYM in + io_rw_32 trcitiatbinr; + + uint32_t _pad58; + + _REG_(M33_TRCITIATBOUTR_OFFSET) // M33_TRCITIATBOUTR + // Trace Integration Instruction ATB Out Register + // 0x00000002 [1] AFREADY (0) Integration Mode instruction AFREADY out + // 0x00000001 [0] ATVALID (0) Integration Mode instruction ATVALID out + io_rw_32 trcitiatboutr; + + uint32_t _pad59[40]; + + _REG_(M33_TRCCLAIMSET_OFFSET) // M33_TRCCLAIMSET + // Claim Tag Set Register + // 0x00000008 [3] SET3 (1) When a write to one of these bits occurs, with the value: + // 0x00000004 [2] SET2 (1) When a write to one of these bits occurs, with the value: + // 0x00000002 [1] SET1 (1) When a write to one of these bits occurs, with the value: + // 0x00000001 [0] SET0 (1) When a write to one of these bits occurs, with the value: + io_rw_32 trcclaimset; + + _REG_(M33_TRCCLAIMCLR_OFFSET) // M33_TRCCLAIMCLR + // Claim Tag Clear Register + // 0x00000008 [3] CLR3 (0) When a write to one of these bits occurs, with the value: + // 0x00000004 [2] CLR2 (0) When a write to one of these bits occurs, with the value: + // 0x00000002 [1] CLR1 (0) When a write to one of these bits occurs, with the value: + // 0x00000001 [0] CLR0 (0) When a write to one of these bits occurs, with the value: + io_rw_32 trcclaimclr; + + uint32_t _pad60[4]; + + _REG_(M33_TRCAUTHSTATUS_OFFSET) // M33_TRCAUTHSTATUS + // Returns the level of tracing that the trace unit can support + // 0x000000c0 [7:6] SNID (0x0) Indicates whether the system enables the trace unit to... + // 0x00000030 [5:4] SID (0x0) Indicates whether the trace unit supports Secure invasive debug: + // 0x0000000c [3:2] NSNID (0x0) Indicates whether the system enables the trace unit to... + // 0x00000003 [1:0] NSID (0x0) Indicates whether the trace unit supports Non-secure... + io_ro_32 trcauthstatus; + + _REG_(M33_TRCDEVARCH_OFFSET) // M33_TRCDEVARCH + // TRCDEVARCH + // 0xffe00000 [31:21] ARCHITECT (0x23b) reads as 0b01000111011 + // 0x00100000 [20] PRESENT (1) reads as 0b1 + // 0x000f0000 [19:16] REVISION (0x2) reads as 0b0000 + // 0x0000ffff [15:0] ARCHID (0x4a13) reads as 0b0100101000010011 + io_ro_32 trcdevarch; + + uint32_t _pad61[2]; + + _REG_(M33_TRCDEVID_OFFSET) // M33_TRCDEVID + // TRCDEVID + // 0x00000000 [31:0] TRCDEVID (0x00000000) + io_rw_32 trcdevid; + + _REG_(M33_TRCDEVTYPE_OFFSET) // M33_TRCDEVTYPE + // TRCDEVTYPE + // 0x000000f0 [7:4] SUB (0x1) reads as 0b0001 + // 0x0000000f [3:0] MAJOR (0x3) reads as 0b0011 + io_ro_32 trcdevtype; + + _REG_(M33_TRCPIDR4_OFFSET) // M33_TRCPIDR4 + // TRCPIDR4 + // 0x000000f0 [7:4] SIZE (0x0) reads as `ImpDef + // 0x0000000f [3:0] DES_2 (0x4) reads as `ImpDef + io_ro_32 trcpidr4; + + _REG_(M33_TRCPIDR5_OFFSET) // M33_TRCPIDR5 + // TRCPIDR5 + // 0x00000000 [31:0] TRCPIDR5 (0x00000000) + io_rw_32 trcpidr5; + + _REG_(M33_TRCPIDR6_OFFSET) // M33_TRCPIDR6 + // TRCPIDR6 + // 0x00000000 [31:0] TRCPIDR6 (0x00000000) + io_rw_32 trcpidr6; + + _REG_(M33_TRCPIDR7_OFFSET) // M33_TRCPIDR7 + // TRCPIDR7 + // 0x00000000 [31:0] TRCPIDR7 (0x00000000) + io_rw_32 trcpidr7; + + _REG_(M33_TRCPIDR0_OFFSET) // M33_TRCPIDR0 + // TRCPIDR0 + // 0x000000ff [7:0] PART_0 (0x21) reads as `ImpDef + io_ro_32 trcpidr0; + + _REG_(M33_TRCPIDR1_OFFSET) // M33_TRCPIDR1 + // TRCPIDR1 + // 0x000000f0 [7:4] DES_0 (0xb) reads as `ImpDef + // 0x0000000f [3:0] PART_0 (0xd) reads as `ImpDef + io_ro_32 trcpidr1; + + _REG_(M33_TRCPIDR2_OFFSET) // M33_TRCPIDR2 + // TRCPIDR2 + // 0x000000f0 [7:4] REVISION (0x2) reads as `ImpDef + // 0x00000008 [3] JEDEC (1) reads as 0b1 + // 0x00000007 [2:0] DES_0 (0x3) reads as `ImpDef + io_ro_32 trcpidr2; + + _REG_(M33_TRCPIDR3_OFFSET) // M33_TRCPIDR3 + // TRCPIDR3 + // 0x000000f0 [7:4] REVAND (0x0) reads as `ImpDef + // 0x0000000f [3:0] CMOD (0x0) reads as `ImpDef + io_ro_32 trcpidr3; + + // (Description copied from array index 0 register M33_TRCCIDR0 applies similarly to other array indexes) + _REG_(M33_TRCCIDR0_OFFSET) // M33_TRCCIDR0 + // TRCCIDR0 + // 0x000000ff [7:0] PRMBL_0 (0x0d) reads as 0b00001101 + io_ro_32 trccidr[4]; + + _REG_(M33_CTICONTROL_OFFSET) // M33_CTICONTROL + // CTI Control Register + // 0x00000001 [0] GLBEN (0) Enables or disables the CTI + io_rw_32 cticontrol; + + uint32_t _pad62[3]; + + _REG_(M33_CTIINTACK_OFFSET) // M33_CTIINTACK + // CTI Interrupt Acknowledge Register + // 0x000000ff [7:0] INTACK (0x00) Acknowledges the corresponding ctitrigout output + io_rw_32 ctiintack; + + _REG_(M33_CTIAPPSET_OFFSET) // M33_CTIAPPSET + // CTI Application Trigger Set Register + // 0x0000000f [3:0] APPSET (0x0) Setting a bit HIGH generates a channel event for the... + io_rw_32 ctiappset; + + _REG_(M33_CTIAPPCLEAR_OFFSET) // M33_CTIAPPCLEAR + // CTI Application Trigger Clear Register + // 0x0000000f [3:0] APPCLEAR (0x0) Sets the corresponding bits in the CTIAPPSET to 0 + io_rw_32 ctiappclear; + + _REG_(M33_CTIAPPPULSE_OFFSET) // M33_CTIAPPPULSE + // CTI Application Pulse Register + // 0x0000000f [3:0] APPULSE (0x0) Setting a bit HIGH generates a channel event pulse for... + io_rw_32 ctiapppulse; + + // (Description copied from array index 0 register M33_CTIINEN0 applies similarly to other array indexes) + _REG_(M33_CTIINEN0_OFFSET) // M33_CTIINEN0 + // CTI Trigger to Channel Enable Registers + // 0x0000000f [3:0] TRIGINEN (0x0) Enables a cross trigger event to the corresponding... + io_rw_32 ctiinen[8]; + + uint32_t _pad63[24]; + + // (Description copied from array index 0 register M33_CTIOUTEN0 applies similarly to other array indexes) + _REG_(M33_CTIOUTEN0_OFFSET) // M33_CTIOUTEN0 + // CTI Trigger to Channel Enable Registers + // 0x0000000f [3:0] TRIGOUTEN (0x0) Enables a cross trigger event to ctitrigout when the... + io_rw_32 ctiouten[8]; + + uint32_t _pad64[28]; + + _REG_(M33_CTITRIGINSTATUS_OFFSET) // M33_CTITRIGINSTATUS + // CTI Trigger to Channel Enable Registers + // 0x000000ff [7:0] TRIGINSTATUS (0x00) Shows the status of the ctitrigin inputs + io_ro_32 ctitriginstatus; + + _REG_(M33_CTITRIGOUTSTATUS_OFFSET) // M33_CTITRIGOUTSTATUS + // CTI Trigger In Status Register + // 0x000000ff [7:0] TRIGOUTSTATUS (0x00) Shows the status of the ctitrigout outputs + io_ro_32 ctitrigoutstatus; + + _REG_(M33_CTICHINSTATUS_OFFSET) // M33_CTICHINSTATUS + // CTI Channel In Status Register + // 0x0000000f [3:0] CTICHOUTSTATUS (0x0) Shows the status of the ctichout outputs + io_ro_32 ctichinstatus; + + uint32_t _pad65; + + _REG_(M33_CTIGATE_OFFSET) // M33_CTIGATE + // Enable CTI Channel Gate register + // 0x00000008 [3] CTIGATEEN3 (1) Enable ctichout3 + // 0x00000004 [2] CTIGATEEN2 (1) Enable ctichout2 + // 0x00000002 [1] CTIGATEEN1 (1) Enable ctichout1 + // 0x00000001 [0] CTIGATEEN0 (1) Enable ctichout0 + io_rw_32 ctigate; + + _REG_(M33_ASICCTL_OFFSET) // M33_ASICCTL + // External Multiplexer Control register + // 0x00000000 [31:0] ASICCTL (0x00000000) + io_rw_32 asicctl; + + uint32_t _pad66[871]; + + _REG_(M33_ITCHOUT_OFFSET) // M33_ITCHOUT + // Integration Test Channel Output register + // 0x0000000f [3:0] CTCHOUT (0x0) Sets the value of the ctichout outputs + io_rw_32 itchout; + + _REG_(M33_ITTRIGOUT_OFFSET) // M33_ITTRIGOUT + // Integration Test Trigger Output register + // 0x000000ff [7:0] CTTRIGOUT (0x00) Sets the value of the ctitrigout outputs + io_rw_32 ittrigout; + + uint32_t _pad67[2]; + + _REG_(M33_ITCHIN_OFFSET) // M33_ITCHIN + // Integration Test Channel Input register + // 0x0000000f [3:0] CTCHIN (0x0) Reads the value of the ctichin inputs + io_ro_32 itchin; + + uint32_t _pad68[2]; + + _REG_(M33_ITCTRL_OFFSET) // M33_ITCTRL + // Integration Mode Control register + // 0x00000001 [0] IME (0) Integration Mode Enable + io_rw_32 itctrl; + + uint32_t _pad69[46]; + + _REG_(M33_DEVARCH_OFFSET) // M33_DEVARCH + // Device Architecture register + // 0xffe00000 [31:21] ARCHITECT (0x23b) Indicates the component architect + // 0x00100000 [20] PRESENT (1) Indicates whether the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Indicates the architecture revision + // 0x0000ffff [15:0] ARCHID (0x1a14) Indicates the component + io_ro_32 devarch; + + uint32_t _pad70[2]; + + _REG_(M33_DEVID_OFFSET) // M33_DEVID + // Device Configuration register + // 0x000f0000 [19:16] NUMCH (0x4) Number of ECT channels available + // 0x0000ff00 [15:8] NUMTRIG (0x08) Number of ECT triggers available + // 0x0000001f [4:0] EXTMUXNUM (0x00) Indicates the number of multiplexers available on... + io_ro_32 devid; + + _REG_(M33_DEVTYPE_OFFSET) // M33_DEVTYPE + // Device Type Identifier register + // 0x000000f0 [7:4] SUB (0x1) Sub-classification of the type of the debug component as... + // 0x0000000f [3:0] MAJOR (0x4) Major classification of the type of the debug component... + io_ro_32 devtype; + + _REG_(M33_PIDR4_OFFSET) // M33_PIDR4 + // CoreSight Peripheral ID4 + // 0x000000f0 [7:4] SIZE (0x0) Always 0b0000 + // 0x0000000f [3:0] DES_2 (0x4) Together, PIDR1 + io_ro_32 pidr4; + + _REG_(M33_PIDR5_OFFSET) // M33_PIDR5 + // CoreSight Peripheral ID5 + // 0x00000000 [31:0] PIDR5 (0x00000000) + io_rw_32 pidr5; + + _REG_(M33_PIDR6_OFFSET) // M33_PIDR6 + // CoreSight Peripheral ID6 + // 0x00000000 [31:0] PIDR6 (0x00000000) + io_rw_32 pidr6; + + _REG_(M33_PIDR7_OFFSET) // M33_PIDR7 + // CoreSight Peripheral ID7 + // 0x00000000 [31:0] PIDR7 (0x00000000) + io_rw_32 pidr7; + + _REG_(M33_PIDR0_OFFSET) // M33_PIDR0 + // CoreSight Peripheral ID0 + // 0x000000ff [7:0] PART_0 (0x21) Bits[7:0] of the 12-bit part number of the component + io_ro_32 pidr0; + + _REG_(M33_PIDR1_OFFSET) // M33_PIDR1 + // CoreSight Peripheral ID1 + // 0x000000f0 [7:4] DES_0 (0xb) Together, PIDR1 + // 0x0000000f [3:0] PART_1 (0xd) Bits[11:8] of the 12-bit part number of the component + io_ro_32 pidr1; + + _REG_(M33_PIDR2_OFFSET) // M33_PIDR2 + // CoreSight Peripheral ID2 + // 0x000000f0 [7:4] REVISION (0x0) This device is at r1p0 + // 0x00000008 [3] JEDEC (1) Always 1 + // 0x00000007 [2:0] DES_1 (0x3) Together, PIDR1 + io_ro_32 pidr2; + + _REG_(M33_PIDR3_OFFSET) // M33_PIDR3 + // CoreSight Peripheral ID3 + // 0x000000f0 [7:4] REVAND (0x0) Indicates minor errata fixes specific to the revision of... + // 0x0000000f [3:0] CMOD (0x0) Customer Modified + io_ro_32 pidr3; + + // (Description copied from array index 0 register M33_CIDR0 applies similarly to other array indexes) + _REG_(M33_CIDR0_OFFSET) // M33_CIDR0 + // CoreSight Component ID0 + // 0x000000ff [7:0] PRMBL_0 (0x0d) Preamble[0] + io_ro_32 cidr[4]; +} m33_hw_t; + +#define m33_hw ((m33_hw_t *)PPB_BASE) +#define m33_ns_hw ((m33_hw_t *)PPB_NONSEC_BASE) +static_assert(sizeof (m33_hw_t) == 0x43000, ""); + +#endif // _HARDWARE_STRUCTS_M33_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h b/src/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h new file mode 100644 index 000000000..3b271e6f0 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/m33_eppb.h @@ -0,0 +1,50 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M33_EPPB_H +#define _HARDWARE_STRUCTS_M33_EPPB_H + +/** + * \file rp2350/m33_eppb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33_eppb.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33_eppb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33_eppb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + + +typedef struct { + // (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes) + _REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0 + // NMI mask for IRQs 0 through 31 + // 0xffffffff [31:0] NMI_MASK0 (0x00000000) + io_rw_32 nmi_mask[2]; + + _REG_(M33_EPPB_SLEEPCTRL_OFFSET) // M33_EPPB_SLEEPCTRL + // Nonstandard sleep control register + // 0x00000004 [2] WICENACK (0) Status signal from the processor's interrupt controller + // 0x00000002 [1] WICENREQ (1) Request that the next processor deep sleep is a WIC sleep + // 0x00000001 [0] LIGHT_SLEEP (0) By default, any processor sleep will deassert the... + io_rw_32 sleepctrl; +} m33_eppb_hw_t; + +#define eppb_hw ((m33_eppb_hw_t *)EPPB_BASE) +static_assert(sizeof (m33_eppb_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_M33_EPPB_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/mpu.h b/src/rp2350/hardware_structs/include/hardware/structs/mpu.h new file mode 100644 index 000000000..e3bf920d1 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/mpu.h @@ -0,0 +1,126 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_MPU_H +#define _HARDWARE_STRUCTS_MPU_H + +/** + * \file rp2350/mpu.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE + // The MPU Type Register indicates how many regions the MPU `FTSSS supports + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... + io_ro_32 type; + + _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL + // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... + // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 ctrl; + + _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR + // Selects the region currently accessed by MPU_RBAR and MPU_RLAR + // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + io_rw_32 rnr; + + _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR + // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar; + + _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR + // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar; + + _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a1; + + _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a1; + + _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a2; + + _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a2; + + _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a3; + + _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a3; + + uint32_t _pad0; + + // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) + _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 + // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 + // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 + // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 + // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 + io_rw_32 mair[2]; +} mpu_hw_t; + +#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET)) +#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET)) +static_assert(sizeof (mpu_hw_t) == 0x0038, ""); + +#endif // _HARDWARE_STRUCTS_MPU_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/nvic.h b/src/rp2350/hardware_structs/include/hardware/structs/nvic.h new file mode 100644 index 000000000..c0c7b76bd --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/nvic.h @@ -0,0 +1,94 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_NVIC_H +#define _HARDWARE_STRUCTS_NVIC_H + +/** + * \file rp2350/nvic.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 + // Enables or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... + io_rw_32 iser[2]; + + uint32_t _pad0[30]; + + // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 + // Clears or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... + io_rw_32 icer[2]; + + uint32_t _pad1[30]; + + // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 + // Enables or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... + io_rw_32 ispr[2]; + + uint32_t _pad2[30]; + + // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 + // Clears or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... + io_rw_32 icpr[2]; + + uint32_t _pad3[30]; + + // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 + // For each group of 32 interrupts, shows the active state of each interrupt + // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... + io_rw_32 iabr[2]; + + uint32_t _pad4[30]; + + // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) + _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 + // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... + io_rw_32 itns[2]; + + uint32_t _pad5[30]; + + // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 + // Sets or reads interrupt priorities + // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... + io_rw_32 ipr[16]; +} nvic_hw_t; + +#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET)) +#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET)) +static_assert(sizeof (nvic_hw_t) == 0x0340, ""); + +#endif // _HARDWARE_STRUCTS_NVIC_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/otp.h b/src/rp2350/hardware_structs/include/hardware/structs/otp.h new file mode 100644 index 000000000..803643b86 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/otp.h @@ -0,0 +1,192 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_OTP_H +#define _HARDWARE_STRUCTS_OTP_H + +/** + * \file rp2350/otp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/otp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_otp +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/otp.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register OTP_SW_LOCK0 applies similarly to other array indexes) + _REG_(OTP_SW_LOCK0_OFFSET) // OTP_SW_LOCK0 + // Software lock register for page 0. + // 0x0000000c [3:2] NSEC (-) Non-secure lock status + // 0x00000003 [1:0] SEC (-) Secure lock status + io_rw_32 sw_lock[64]; + + _REG_(OTP_SBPI_INSTR_OFFSET) // OTP_SBPI_INSTR + // Dispatch instructions to the SBPI interface, used for programming the OTP fuses + // 0x40000000 [30] EXEC (0) Execute instruction + // 0x20000000 [29] IS_WR (0) Payload type is write + // 0x10000000 [28] HAS_PAYLOAD (0) Instruction has payload (data to be written or to be read) + // 0x0f000000 [27:24] PAYLOAD_SIZE_M1 (0x0) Instruction payload size in bytes minus 1 + // 0x00ff0000 [23:16] TARGET (0x00) Instruction target, it can be PMC (0x3a) or DAP (0x02) + // 0x0000ff00 [15:8] CMD (0x00) + // 0x000000ff [7:0] SHORT_WDATA (0x00) wdata to be used only when payload_size_m1=0 + io_rw_32 sbpi_instr; + + // (Description copied from array index 0 register OTP_SBPI_WDATA_0 applies similarly to other array indexes) + _REG_(OTP_SBPI_WDATA_0_OFFSET) // OTP_SBPI_WDATA_0 + // SBPI write payload bytes 3 + // 0xffffffff [31:0] SBPI_WDATA_0 (0x00000000) + io_rw_32 sbpi_wdata[4]; + + // (Description copied from array index 0 register OTP_SBPI_RDATA_0 applies similarly to other array indexes) + _REG_(OTP_SBPI_RDATA_0_OFFSET) // OTP_SBPI_RDATA_0 + // Read payload bytes 3 + // 0xffffffff [31:0] SBPI_RDATA_0 (0x00000000) + io_ro_32 sbpi_rdata[4]; + + _REG_(OTP_SBPI_STATUS_OFFSET) // OTP_SBPI_STATUS + // 0x00ff0000 [23:16] MISO (-) SBPI MISO (master in - slave out): response from SBPI + // 0x00001000 [12] FLAG (-) SBPI flag + // 0x00000100 [8] INSTR_MISS (0) Last instruction missed (dropped), as the previous has... + // 0x00000010 [4] INSTR_DONE (0) Last instruction done + // 0x00000001 [0] RDATA_VLD (0) Read command has returned data + io_rw_32 sbpi_status; + + _REG_(OTP_USR_OFFSET) // OTP_USR + // Controls for APB data read interface (USER interface) + // 0x00000010 [4] PD (0) Power-down; 1 disables current reference + // 0x00000001 [0] DCTRL (1) 1 enables USER interface; 0 disables USER interface... + io_rw_32 usr; + + _REG_(OTP_DBG_OFFSET) // OTP_DBG + // Debug for OTP power-on state machine + // 0x00001000 [12] CUSTOMER_RMA_FLAG (-) The chip is in RMA mode + // 0x000000f0 [7:4] PSM_STATE (-) Monitor the PSM FSM's state + // 0x00000008 [3] ROSC_UP (-) Ring oscillator is up and running + // 0x00000004 [2] ROSC_UP_SEEN (0) Ring oscillator was seen up and running + // 0x00000002 [1] BOOT_DONE (-) PSM boot done status flag + // 0x00000001 [0] PSM_DONE (-) PSM done status flag + io_rw_32 dbg; + + uint32_t _pad0; + + _REG_(OTP_BIST_OFFSET) // OTP_BIST + // During BIST, count address locations that have at least one leaky bit + // 0x40000000 [30] CNT_FAIL (-) Flag if the count of address locations with at least one... + // 0x20000000 [29] CNT_CLR (0) Clear counter before use + // 0x10000000 [28] CNT_ENA (0) Enable the counter before the BIST function is initiated + // 0x0fff0000 [27:16] CNT_MAX (0xfff) The cnt_fail flag will be set if the number of leaky... + // 0x00001fff [12:0] CNT (-) Number of locations that have at least one leaky bit + io_rw_32 bist; + + // (Description copied from array index 0 register OTP_CRT_KEY_W0 applies similarly to other array indexes) + _REG_(OTP_CRT_KEY_W0_OFFSET) // OTP_CRT_KEY_W0 + // Word 0 (bits 31 + // 0xffffffff [31:0] CRT_KEY_W0 (0x00000000) + io_wo_32 crt_key_w[4]; + + _REG_(OTP_CRITICAL_OFFSET) // OTP_CRITICAL + // Quickly check values of critical flags read during boot up + // 0x00020000 [17] RISCV_DISABLE (0) + // 0x00010000 [16] ARM_DISABLE (0) + // 0x00000060 [6:5] GLITCH_DETECTOR_SENS (0x0) + // 0x00000010 [4] GLITCH_DETECTOR_ENABLE (0) + // 0x00000008 [3] DEFAULT_ARCHSEL (0) + // 0x00000004 [2] DEBUG_DISABLE (0) + // 0x00000002 [1] SECURE_DEBUG_DISABLE (0) + // 0x00000001 [0] SECURE_BOOT_ENABLE (0) + io_ro_32 critical; + + _REG_(OTP_KEY_VALID_OFFSET) // OTP_KEY_VALID + // Which keys were valid (enrolled) at boot time + // 0x000000ff [7:0] KEY_VALID (0x00) + io_ro_32 key_valid; + + _REG_(OTP_DEBUGEN_OFFSET) // OTP_DEBUGEN + // Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + // 0x00000100 [8] MISC (0) Enable other debug components + // 0x00000008 [3] PROC1_SECURE (0) Permit core 1's Mem-AP to generate Secure accesses,... + // 0x00000004 [2] PROC1 (0) Enable core 1's Mem-AP if it is currently disabled + // 0x00000002 [1] PROC0_SECURE (0) Permit core 0's Mem-AP to generate Secure accesses,... + // 0x00000001 [0] PROC0 (0) Enable core 0's Mem-AP if it is currently disabled + io_rw_32 debugen; + + _REG_(OTP_DEBUGEN_LOCK_OFFSET) // OTP_DEBUGEN_LOCK + // Write 1s to lock corresponding bits in DEBUGEN + // 0x00000100 [8] MISC (0) Write 1 to lock the MISC bit of DEBUGEN + // 0x00000008 [3] PROC1_SECURE (0) Write 1 to lock the PROC1_SECURE bit of DEBUGEN + // 0x00000004 [2] PROC1 (0) Write 1 to lock the PROC1 bit of DEBUGEN + // 0x00000002 [1] PROC0_SECURE (0) Write 1 to lock the PROC0_SECURE bit of DEBUGEN + // 0x00000001 [0] PROC0 (0) Write 1 to lock the PROC0 bit of DEBUGEN + io_rw_32 debugen_lock; + + _REG_(OTP_ARCHSEL_OFFSET) // OTP_ARCHSEL + // Architecture select (Arm/RISC-V), applied on next processor reset. The default and allowable values of this register are constrained by the critical boot flags. + // 0x00000002 [1] CORE1 (0) Select architecture for core 1 + // 0x00000001 [0] CORE0 (0) Select architecture for core 0 + io_rw_32 archsel; + + _REG_(OTP_ARCHSEL_STATUS_OFFSET) // OTP_ARCHSEL_STATUS + // Get the current architecture select state of each core + // 0x00000002 [1] CORE1 (0) Current architecture for core 0 + // 0x00000001 [0] CORE0 (0) Current architecture for core 0 + io_ro_32 archsel_status; + + _REG_(OTP_BOOTDIS_OFFSET) // OTP_BOOTDIS + // Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents + // 0x00000001 [0] NOW (0) When the core is powered down, the current value of... + io_rw_32 bootdis; + + _REG_(OTP_INTR_OFFSET) // OTP_INTR + // Raw Interrupts + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 intr; + + _REG_(OTP_INTE_OFFSET) // OTP_INTE + // Interrupt Enable + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 inte; + + _REG_(OTP_INTF_OFFSET) // OTP_INTF + // Interrupt Force + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 intf; + + _REG_(OTP_INTS_OFFSET) // OTP_INTS + // Interrupt status after masking & forcing + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_ro_32 ints; +} otp_hw_t; + +#define otp_hw ((otp_hw_t *)OTP_BASE) +static_assert(sizeof (otp_hw_t) == 0x0174, ""); + +#endif // _HARDWARE_STRUCTS_OTP_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/pads_bank0.h b/src/rp2350/hardware_structs/include/hardware/structs/pads_bank0.h new file mode 100644 index 000000000..bf0f4a53f --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/pads_bank0.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H +#define _HARDWARE_STRUCTS_PADS_BANK0_H + +/** + * \file rp2350/pads_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) + _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 + // 0x00000100 [8] ISO (1) Pad isolation control + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (0) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[48]; +} pads_bank0_hw_t; + +#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) +static_assert(sizeof (pads_bank0_hw_t) == 0x00c4, ""); + +#endif // _HARDWARE_STRUCTS_PADS_BANK0_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/pads_qspi.h b/src/rp2350/hardware_structs/include/hardware/structs/pads_qspi.h new file mode 100644 index 000000000..e6b0f6810 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/pads_qspi.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H +#define _HARDWARE_STRUCTS_PADS_QSPI_H + +/** + * \file rp2350/pads_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) + _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK + // 0x00000100 [8] ISO (1) Pad isolation control + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (1) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[6]; +} pads_qspi_hw_t; + +#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE) +static_assert(sizeof (pads_qspi_hw_t) == 0x001c, ""); + +#endif // _HARDWARE_STRUCTS_PADS_QSPI_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/padsbank0.h b/src/rp2350/hardware_structs/include/hardware/structs/padsbank0.h new file mode 100644 index 000000000..cb14e792b --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/padsbank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/pads_bank0.h" +#define padsbank0_hw pads_bank0_hw \ No newline at end of file diff --git a/src/rp2350/hardware_structs/include/hardware/structs/pio.h b/src/rp2350/hardware_structs/include/hardware/structs/pio.h new file mode 100644 index 000000000..68e5bac08 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/pio.h @@ -0,0 +1,380 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PIO_H +#define _HARDWARE_STRUCTS_PIO_H + +/** + * \file rp2350/pio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV + // Clock divisor register for state machine 0 + + // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) + // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor + io_rw_32 clkdiv; + + _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL + // Execution/behavioural settings for state machine 0 + // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... + // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... + // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... + // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN + // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable + // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + + // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins + // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom + // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address + // 0x00000060 [6:5] STATUS_SEL (0x0) Comparison used for the MOV x, STATUS instruction + // 0x0000001f [4:0] STATUS_N (0x00) Comparison level or IRQ index for the MOV x, STATUS instruction + io_rw_32 execctrl; + + _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL + // Control behaviour of the input/output shift registers for state machine 0 + // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... + // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... + // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... + // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... + // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right + // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) + // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i + // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i + // 0x00008000 [15] FJOIN_RX_PUT (0) If 1, disable this state machine's RX FIFO, make its... + // 0x00004000 [14] FJOIN_RX_GET (0) If 1, disable this state machine's RX FIFO, make its... + // 0x0000001f [4:0] IN_COUNT (0x00) Set the number of pins which are not masked to 0 when... + io_rw_32 shiftctrl; + + _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR + // Current instruction address of state machine 0 + // 0x0000001f [4:0] SM0_ADDR (0x00) + io_ro_32 addr; + + _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR + // Read to see the instruction currently addressed by state machine 0's program counter + + // 0x0000ffff [15:0] SM0_INSTR (-) + io_rw_32 instr; + + _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL + // State machine pin control + // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... + // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET + // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... + // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... + // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... + // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... + // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... + io_rw_32 pinctrl; +} pio_sm_hw_t; + +typedef struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints; +} pio_irq_ctrl_hw_t; + +typedef struct { + _REG_(PIO_CTRL_OFFSET) // PIO_CTRL + // PIO control register + // 0x04000000 [26] NEXTPREV_CLKDIV_RESTART (0) Write 1 to restart the clock dividers of state machines... + // 0x02000000 [25] NEXTPREV_SM_DISABLE (0) Write 1 to disable state machines in neighbouring PIO... + // 0x01000000 [24] NEXTPREV_SM_ENABLE (0) Write 1 to enable state machines in neighbouring PIO... + // 0x00f00000 [23:20] NEXT_PIO_MASK (0x0) A mask of state machines in the neighbouring... + // 0x000f0000 [19:16] PREV_PIO_MASK (0x0) A mask of state machines in the neighbouring... + // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... + // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... + // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... + io_rw_32 ctrl; + + _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT + // FIFO status register + // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty + // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full + // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty + // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full + io_ro_32 fstat; + + _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG + // FIFO debug register + // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... + // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i + // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i + // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... + io_rw_32 fdebug; + + _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL + // FIFO levels + // 0xf0000000 [31:28] RX3 (0x0) + // 0x0f000000 [27:24] TX3 (0x0) + // 0x00f00000 [23:20] RX2 (0x0) + // 0x000f0000 [19:16] TX2 (0x0) + // 0x0000f000 [15:12] RX1 (0x0) + // 0x00000f00 [11:8] TX1 (0x0) + // 0x000000f0 [7:4] RX0 (0x0) + // 0x0000000f [3:0] TX0 (0x0) + io_ro_32 flevel; + + // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) + _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 + // Direct write access to the TX FIFO for this state machine + // 0xffffffff [31:0] TXF0 (0x00000000) + io_wo_32 txf[4]; + + // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) + _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 + // Direct read access to the RX FIFO for this state machine + // 0xffffffff [31:0] RXF0 (-) + io_ro_32 rxf[4]; + + _REG_(PIO_IRQ_OFFSET) // PIO_IRQ + // State machine IRQ flags register + // 0x000000ff [7:0] IRQ (0x00) + io_rw_32 irq; + + _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE + // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ + // 0x000000ff [7:0] IRQ_FORCE (0x00) + io_wo_32 irq_force; + + _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS + // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities + // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) + io_rw_32 input_sync_bypass; + + _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT + // Read to sample the pad output values PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOUT (0x00000000) + io_ro_32 dbg_padout; + + _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE + // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOE (0x00000000) + io_ro_32 dbg_padoe; + + _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO + // The PIO hardware has some free parameters that may vary between chip products + // 0xf0000000 [31:28] VERSION (0x1) Version of the core PIO hardware + // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... + // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with + // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words + io_ro_32 dbg_cfginfo; + + // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) + _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 + // Write-only access to instruction memory location 0 + // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) + io_wo_32 instr_mem[32]; + + pio_sm_hw_t sm[4]; + + // (Description copied from array index 0 register PIO_RXF0_PUTGET0 applies similarly to other array indexes) + _REG_(PIO_RXF0_PUTGET0_OFFSET) // PIO_RXF0_PUTGET0 + // Direct read/write access to the RX FIFO on all SMs, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set + // 0xffffffff [31:0] RXF0_PUTGET0 (0x00000000) + io_rw_32 rxf_putget[4][4]; + + _REG_(PIO_GPIOBASE_OFFSET) // PIO_GPIOBASE + // Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32... + // 0x00000010 [4] GPIOBASE (0) + io_rw_32 gpiobase; + + _REG_(PIO_INTR_OFFSET) // PIO_INTR + // Raw Interrupts + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 intr; + + union { + struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte0; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf0; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints0; + + _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte1; + + _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf1; + + _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints1; + }; + pio_irq_ctrl_hw_t irq_ctrl[2]; + }; +} pio_hw_t; + +#define pio0_hw ((pio_hw_t *)PIO0_BASE) +#define pio1_hw ((pio_hw_t *)PIO1_BASE) +#define pio2_hw ((pio_hw_t *)PIO2_BASE) +static_assert(sizeof (pio_hw_t) == 0x0188, ""); + +#endif // _HARDWARE_STRUCTS_PIO_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/pll.h b/src/rp2350/hardware_structs/include/hardware/structs/pll.h new file mode 100644 index 000000000..8a7276048 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/pll.h @@ -0,0 +1,82 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PLL_H +#define _HARDWARE_STRUCTS_PLL_H + +/** + * \file rp2350/pll.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pll.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pll +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::pll_hw[] +typedef struct { + _REG_(PLL_CS_OFFSET) // PLL_CS + // Control and Status + // 0x80000000 [31] LOCK (0) PLL is locked + // 0x40000000 [30] LOCK_N (0) PLL is not locked + + // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the... + // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock + io_rw_32 cs; + + _REG_(PLL_PWR_OFFSET) // PLL_PWR + // Controls the PLL power modes + // 0x00000020 [5] VCOPD (1) PLL VCO powerdown + + // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown + + // 0x00000004 [2] DSMPD (1) PLL DSM powerdown + + // 0x00000001 [0] PD (1) PLL powerdown + + io_rw_32 pwr; + + _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT + // Feedback divisor + // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints + io_rw_32 fbdiv_int; + + _REG_(PLL_PRIM_OFFSET) // PLL_PRIM + // Controls the PLL post dividers for the primary output + // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7 + // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7 + io_rw_32 prim; + + _REG_(PLL_INTR_OFFSET) // PLL_INTR + // Raw Interrupts + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 intr; + + _REG_(PLL_INTE_OFFSET) // PLL_INTE + // Interrupt Enable + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 inte; + + _REG_(PLL_INTF_OFFSET) // PLL_INTF + // Interrupt Force + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 intf; + + _REG_(PLL_INTS_OFFSET) // PLL_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] LOCK_N_STICKY (0) + io_ro_32 ints; +} pll_hw_t; +/// \end::pll_hw[] + +#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) +#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) +static_assert(sizeof (pll_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_PLL_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/powman.h b/src/rp2350/hardware_structs/include/hardware/structs/powman.h new file mode 100644 index 000000000..a81890e3c --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/powman.h @@ -0,0 +1,338 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_POWMAN_H +#define _HARDWARE_STRUCTS_POWMAN_H + +/** + * \file rp2350/powman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/powman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_powman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/powman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(POWMAN_BADPASSWD_OFFSET) // POWMAN_BADPASSWD + // Indicates a bad password has been used + // 0x00000001 [0] BADPASSWD (0) + io_rw_32 badpasswd; + + _REG_(POWMAN_VREG_CTRL_OFFSET) // POWMAN_VREG_CTRL + // Voltage Regulator Control + // 0x00008000 [15] RST_N (1) returns the regulator to its startup settings + + // 0x00002000 [13] UNLOCK (0) unlocks the VREG control interface after power up + + // 0x00001000 [12] ISOLATE (0) isolates the VREG control interface + + // 0x00000100 [8] DISABLE_VOLTAGE_LIMIT (0) 0=not disabled, 1=enabled + // 0x00000070 [6:4] HT_TH (0x5) high temperature protection threshold + + io_rw_32 vreg_ctrl; + + _REG_(POWMAN_VREG_STS_OFFSET) // POWMAN_VREG_STS + // Voltage Regulator Status + // 0x00000010 [4] VOUT_OK (0) output regulation status + + // 0x00000001 [0] STARTUP (0) startup status + + io_ro_32 vreg_sts; + + _REG_(POWMAN_VREG_OFFSET) // POWMAN_VREG + // Voltage Regulator Settings + // 0x00008000 [15] UPDATE_IN_PROGRESS (0) regulator state is being updated + + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg; + + _REG_(POWMAN_VREG_LP_ENTRY_OFFSET) // POWMAN_VREG_LP_ENTRY + // Voltage Regulator Low Power Entry Settings + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000004 [2] MODE (1) selects either normal (switching) mode or low power... + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg_lp_entry; + + _REG_(POWMAN_VREG_LP_EXIT_OFFSET) // POWMAN_VREG_LP_EXIT + // Voltage Regulator Low Power Exit Settings + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000004 [2] MODE (0) selects either normal (switching) mode or low power... + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg_lp_exit; + + _REG_(POWMAN_BOD_CTRL_OFFSET) // POWMAN_BOD_CTRL + // Brown-out Detection Control + // 0x00001000 [12] ISOLATE (0) isolates the brown-out detection control interface + + io_rw_32 bod_ctrl; + + _REG_(POWMAN_BOD_OFFSET) // POWMAN_BOD + // Brown-out Detection Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (1) enable brown-out detection + + io_rw_32 bod; + + _REG_(POWMAN_BOD_LP_ENTRY_OFFSET) // POWMAN_BOD_LP_ENTRY + // Brown-out Detection Low Power Entry Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (0) enable brown-out detection + + io_rw_32 bod_lp_entry; + + _REG_(POWMAN_BOD_LP_EXIT_OFFSET) // POWMAN_BOD_LP_EXIT + // Brown-out Detection Low Power Exit Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (1) enable brown-out detection + + io_rw_32 bod_lp_exit; + + _REG_(POWMAN_LPOSC_OFFSET) // POWMAN_LPOSC + // Low power oscillator control register + // 0x000003f0 [9:4] TRIM (0x20) Frequency trim - the trim step is typically 1% of the... + // 0x00000003 [1:0] MODE (0x3) This feature has been removed + io_rw_32 lposc; + + _REG_(POWMAN_CHIP_RESET_OFFSET) // POWMAN_CHIP_RESET + // Chip reset control and status + // 0x10000000 [28] HAD_WATCHDOG_RESET_RSM (0) Last reset was a watchdog timeout which was configured... + // 0x08000000 [27] HAD_HZD_SYS_RESET_REQ (0) Last reset was a system reset from the hazard debugger + + // 0x04000000 [26] HAD_GLITCH_DETECT (0) Last reset was due to a power supply glitch + + // 0x02000000 [25] HAD_SWCORE_PD (0) Last reset was a switched core powerdown + + // 0x01000000 [24] HAD_WATCHDOG_RESET_SWCORE (0) Last reset was a watchdog timeout which was configured... + // 0x00800000 [23] HAD_WATCHDOG_RESET_POWMAN (0) Last reset was a watchdog timeout which was configured... + // 0x00400000 [22] HAD_WATCHDOG_RESET_POWMAN_ASYNC (0) Last reset was a watchdog timeout which was configured... + // 0x00200000 [21] HAD_RESCUE (0) Last reset was a rescue reset from the debugger + + // 0x00080000 [19] HAD_DP_RESET_REQ (0) Last reset was an reset request from the arm debugger + + // 0x00040000 [18] HAD_RUN_LOW (0) Last reset was from the RUN pin + + // 0x00020000 [17] HAD_BOR (0) Last reset was from the brown-out detection block + + // 0x00010000 [16] HAD_POR (0) Last reset was from the power-on reset + + // 0x00000010 [4] RESCUE_FLAG (0) This is set by a rescue reset from the RP-AP + // 0x00000001 [0] DOUBLE_TAP (0) This flag is set by double-tapping RUN + io_rw_32 chip_reset; + + _REG_(POWMAN_WDSEL_OFFSET) // POWMAN_WDSEL + // Allows a watchdog reset to reset the internal state of powman in addition to the power-on state... + // 0x00001000 [12] RESET_RSM (0) If set to 1, a watchdog reset will run the full power-on... + // 0x00000100 [8] RESET_SWCORE (0) If set to 1, a watchdog reset will reset the switched... + // 0x00000010 [4] RESET_POWMAN (0) If set to 1, a watchdog reset will restore powman... + // 0x00000001 [0] RESET_POWMAN_ASYNC (0) If set to 1, a watchdog reset will restore powman... + io_rw_32 wdsel; + + _REG_(POWMAN_SEQ_CFG_OFFSET) // POWMAN_SEQ_CFG + // For configuration of the power sequencer + + // 0x00100000 [20] USING_FAST_POWCK (1) 0 indicates the POWMAN clock is running from the low... + // 0x00020000 [17] USING_BOD_LP (0) Indicates the brown-out detector (BOD) mode + + // 0x00010000 [16] USING_VREG_LP (0) Indicates the voltage regulator (VREG) mode + + // 0x00001000 [12] USE_FAST_POWCK (1) selects the reference clock (clk_ref) as the source of... + // 0x00000100 [8] RUN_LPOSC_IN_LP (1) Set to 0 to stop the low power osc when the... + // 0x00000080 [7] USE_BOD_HP (1) Set to 0 to prevent automatic switching to bod high... + // 0x00000040 [6] USE_BOD_LP (1) Set to 0 to prevent automatic switching to bod low power... + // 0x00000020 [5] USE_VREG_HP (1) Set to 0 to prevent automatic switching to vreg high... + // 0x00000010 [4] USE_VREG_LP (1) Set to 0 to prevent automatic switching to vreg low... + // 0x00000002 [1] HW_PWRUP_SRAM0 (0) Specifies the power state of SRAM0 when powering up... + // 0x00000001 [0] HW_PWRUP_SRAM1 (0) Specifies the power state of SRAM1 when powering up... + io_rw_32 seq_cfg; + + _REG_(POWMAN_STATE_OFFSET) // POWMAN_STATE + // This register controls the power state of the 4 power domains + // 0x00002000 [13] CHANGING (0) + // 0x00001000 [12] WAITING (0) + // 0x00000800 [11] BAD_HW_REQ (0) Bad hardware initiated state request + // 0x00000400 [10] BAD_SW_REQ (0) Bad software initiated state request + // 0x00000200 [9] PWRUP_WHILE_WAITING (0) Request ignored because of a pending pwrup request + // 0x00000100 [8] REQ_IGNORED (0) + // 0x000000f0 [7:4] REQ (0x0) + // 0x0000000f [3:0] CURRENT (0xf) + io_rw_32 state; + + _REG_(POWMAN_POW_FASTDIV_OFFSET) // POWMAN_POW_FASTDIV + // 0x000007ff [10:0] POW_FASTDIV (0x040) divides the POWMAN clock to provide a tick for the delay... + io_rw_32 pow_fastdiv; + + _REG_(POWMAN_POW_DELAY_OFFSET) // POWMAN_POW_DELAY + // power state machine delays + // 0x0000ff00 [15:8] SRAM_STEP (0x20) timing between the sram0 and sram1 power state machine steps + + // 0x000000f0 [7:4] XIP_STEP (0x1) timing between the xip power state machine steps + + // 0x0000000f [3:0] SWCORE_STEP (0x1) timing between the swcore power state machine steps + + io_rw_32 pow_delay; + + // (Description copied from array index 0 register POWMAN_EXT_CTRL0 applies similarly to other array indexes) + _REG_(POWMAN_EXT_CTRL0_OFFSET) // POWMAN_EXT_CTRL0 + // Configures a gpio as a power mode aware control output + // 0x00004000 [14] LP_EXIT_STATE (0) output level when exiting the low power state + // 0x00002000 [13] LP_ENTRY_STATE (0) output level when entering the low power state + // 0x00001000 [12] INIT_STATE (0) + // 0x00000100 [8] INIT (0) + // 0x0000003f [5:0] GPIO_SELECT (0x3f) selects from gpio 0->30 + + io_rw_32 ext_ctrl[2]; + + _REG_(POWMAN_EXT_TIME_REF_OFFSET) // POWMAN_EXT_TIME_REF + // Select a GPIO to use as a time reference, the source can be used to drive the low power clock at... + // 0x00000010 [4] DRIVE_LPCK (0) Use the selected GPIO to drive the 32kHz low power... + // 0x00000003 [1:0] SOURCE_SEL (0x0) 0 -> gpio12 + + io_rw_32 ext_time_ref; + + _REG_(POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_INT + // Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC + // 0x0000003f [5:0] LPOSC_FREQ_KHZ_INT (0x20) Integer component of the LPOSC or GPIO clock source... + io_rw_32 lposc_freq_khz_int; + + _REG_(POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_FRAC + // Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC + // 0x0000ffff [15:0] LPOSC_FREQ_KHZ_FRAC (0xc49c) Fractional component of the LPOSC or GPIO clock source... + io_rw_32 lposc_freq_khz_frac; + + _REG_(POWMAN_XOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_XOSC_FREQ_KHZ_INT + // Informs the AON Timer of the integer component of the clock frequency when running off the XOSC + // 0x0000ffff [15:0] XOSC_FREQ_KHZ_INT (0x2ee0) Integer component of the XOSC frequency in kHz + io_rw_32 xosc_freq_khz_int; + + _REG_(POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_XOSC_FREQ_KHZ_FRAC + // Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC + // 0x0000ffff [15:0] XOSC_FREQ_KHZ_FRAC (0x0000) Fractional component of the XOSC frequency in kHz + io_rw_32 xosc_freq_khz_frac; + + _REG_(POWMAN_SET_TIME_63TO48_OFFSET) // POWMAN_SET_TIME_63TO48 + // 0x0000ffff [15:0] SET_TIME_63TO48 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_63to48; + + _REG_(POWMAN_SET_TIME_47TO32_OFFSET) // POWMAN_SET_TIME_47TO32 + // 0x0000ffff [15:0] SET_TIME_47TO32 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_47to32; + + _REG_(POWMAN_SET_TIME_31TO16_OFFSET) // POWMAN_SET_TIME_31TO16 + // 0x0000ffff [15:0] SET_TIME_31TO16 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_31to16; + + _REG_(POWMAN_SET_TIME_15TO0_OFFSET) // POWMAN_SET_TIME_15TO0 + // 0x0000ffff [15:0] SET_TIME_15TO0 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_15to0; + + _REG_(POWMAN_READ_TIME_UPPER_OFFSET) // POWMAN_READ_TIME_UPPER + // 0xffffffff [31:0] READ_TIME_UPPER (0x00000000) For reading bits 63:32 of the timer + io_ro_32 read_time_upper; + + _REG_(POWMAN_READ_TIME_LOWER_OFFSET) // POWMAN_READ_TIME_LOWER + // 0xffffffff [31:0] READ_TIME_LOWER (0x00000000) For reading bits 31:0 of the timer + io_ro_32 read_time_lower; + + _REG_(POWMAN_ALARM_TIME_63TO48_OFFSET) // POWMAN_ALARM_TIME_63TO48 + // 0x0000ffff [15:0] ALARM_TIME_63TO48 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_63to48; + + _REG_(POWMAN_ALARM_TIME_47TO32_OFFSET) // POWMAN_ALARM_TIME_47TO32 + // 0x0000ffff [15:0] ALARM_TIME_47TO32 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_47to32; + + _REG_(POWMAN_ALARM_TIME_31TO16_OFFSET) // POWMAN_ALARM_TIME_31TO16 + // 0x0000ffff [15:0] ALARM_TIME_31TO16 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_31to16; + + _REG_(POWMAN_ALARM_TIME_15TO0_OFFSET) // POWMAN_ALARM_TIME_15TO0 + // 0x0000ffff [15:0] ALARM_TIME_15TO0 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_15to0; + + _REG_(POWMAN_TIMER_OFFSET) // POWMAN_TIMER + // 0x00080000 [19] USING_GPIO_1HZ (0) Timer is synchronised to a 1hz gpio source + // 0x00040000 [18] USING_GPIO_1KHZ (0) Timer is running from a 1khz gpio source + // 0x00020000 [17] USING_LPOSC (0) Timer is running from lposc + // 0x00010000 [16] USING_XOSC (0) Timer is running from xosc + // 0x00002000 [13] USE_GPIO_1HZ (0) Selects the gpio source as the reference for the sec counter + // 0x00000400 [10] USE_GPIO_1KHZ (0) switch to gpio as the source of the 1kHz timer tick + // 0x00000200 [9] USE_XOSC (0) switch to xosc as the source of the 1kHz timer tick + // 0x00000100 [8] USE_LPOSC (0) Switch to lposc as the source of the 1kHz timer tick + // 0x00000040 [6] ALARM (0) Alarm has fired + // 0x00000020 [5] PWRUP_ON_ALARM (0) Alarm wakes the chip from low power mode + // 0x00000010 [4] ALARM_ENAB (0) Enables the alarm + // 0x00000004 [2] CLEAR (0) Clears the timer, does not disable the timer and does... + // 0x00000002 [1] RUN (0) Timer enable + // 0x00000001 [0] NONSEC_WRITE (0) Control whether Non-secure software can write to the... + io_rw_32 timer; + + // (Description copied from array index 0 register POWMAN_PWRUP0 applies similarly to other array indexes) + _REG_(POWMAN_PWRUP0_OFFSET) // POWMAN_PWRUP0 + // 4 GPIO powerup events can be configured to wake the chip up from a low power state + // 0x00000400 [10] RAW_STATUS (0) Value of selected gpio pin (only if enable == 1) + // 0x00000200 [9] STATUS (0) Status of gpio wakeup + // 0x00000100 [8] MODE (0) Edge or level detect + // 0x00000080 [7] DIRECTION (0) + // 0x00000040 [6] ENABLE (0) Set to 1 to enable the wakeup source + // 0x0000003f [5:0] SOURCE (0x3f) + io_rw_32 pwrup[4]; + + _REG_(POWMAN_CURRENT_PWRUP_REQ_OFFSET) // POWMAN_CURRENT_PWRUP_REQ + // Indicates current powerup request state + + // 0x0000007f [6:0] CURRENT_PWRUP_REQ (0x00) + io_ro_32 current_pwrup_req; + + _REG_(POWMAN_LAST_SWCORE_PWRUP_OFFSET) // POWMAN_LAST_SWCORE_PWRUP + // Indicates which pwrup source triggered the last switched-core power up + + // 0x0000007f [6:0] LAST_SWCORE_PWRUP (0x00) + io_ro_32 last_swcore_pwrup; + + _REG_(POWMAN_DBG_PWRCFG_OFFSET) // POWMAN_DBG_PWRCFG + // 0x00000001 [0] IGNORE (0) Ignore pwrup req from debugger + io_rw_32 dbg_pwrcfg; + + _REG_(POWMAN_BOOTDIS_OFFSET) // POWMAN_BOOTDIS + // Tell the bootrom to ignore the BOOT0 + // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents + // 0x00000001 [0] NOW (0) When powman resets the RSM, the current value of... + io_rw_32 bootdis; + + _REG_(POWMAN_DBGCONFIG_OFFSET) // POWMAN_DBGCONFIG + // 0x0000000f [3:0] DP_INSTID (0x0) Configure DP instance ID for SWD multidrop selection + io_rw_32 dbgconfig; + + // (Description copied from array index 0 register POWMAN_SCRATCH0 applies similarly to other array indexes) + _REG_(POWMAN_SCRATCH0_OFFSET) // POWMAN_SCRATCH0 + // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) + io_rw_32 scratch[8]; + + // (Description copied from array index 0 register POWMAN_BOOT0 applies similarly to other array indexes) + _REG_(POWMAN_BOOT0_OFFSET) // POWMAN_BOOT0 + // Scratch register + // 0xffffffff [31:0] BOOT0 (0x00000000) + io_rw_32 boot[4]; + + _REG_(POWMAN_INTR_OFFSET) // POWMAN_INTR + // Raw Interrupts + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 intr; + + _REG_(POWMAN_INTE_OFFSET) // POWMAN_INTE + // Interrupt Enable + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 inte; + + _REG_(POWMAN_INTF_OFFSET) // POWMAN_INTF + // Interrupt Force + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 intf; + + _REG_(POWMAN_INTS_OFFSET) // POWMAN_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_ro_32 ints; +} powman_hw_t; + +#define powman_hw ((powman_hw_t *)POWMAN_BASE) +static_assert(sizeof (powman_hw_t) == 0x00f0, ""); + +#endif // _HARDWARE_STRUCTS_POWMAN_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/psm.h b/src/rp2350/hardware_structs/include/hardware/structs/psm.h new file mode 100644 index 000000000..92144ac63 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/psm.h @@ -0,0 +1,148 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PSM_H +#define _HARDWARE_STRUCTS_PSM_H + +/** + * \file rp2350/psm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/psm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_psm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON + // Force block out of reset (i + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 frce_on; + + _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF + // Force into reset (i + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 frce_off; + + _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL + // Set to 1 if the watchdog should reset this + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 wdsel; + + _REG_(PSM_DONE_OFFSET) // PSM_DONE + // Is the subsystem ready? + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_ro_32 done; +} psm_hw_t; + +#define psm_hw ((psm_hw_t *)PSM_BASE) +static_assert(sizeof (psm_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_PSM_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/pwm.h b/src/rp2350/hardware_structs/include/hardware/structs/pwm.h new file mode 100644 index 000000000..be0e24e5d --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/pwm.h @@ -0,0 +1,252 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PWM_H +#define _HARDWARE_STRUCTS_PWM_H + +/** + * \file rp2350/pwm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pwm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pwm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR + // Control and status register + // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running + // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running + // 0x00000030 [5:4] DIVMODE (0x0) + // 0x00000008 [3] B_INV (0) Invert output B + // 0x00000004 [2] A_INV (0) Invert output A + // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation + // 0x00000001 [0] EN (0) Enable the PWM channel + io_rw_32 csr; + + _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV + // INT and FRAC form a fixed-point fractional number + // 0x00000ff0 [11:4] INT (0x01) + // 0x0000000f [3:0] FRAC (0x0) + io_rw_32 div; + + _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR + // Direct access to the PWM counter + // 0x0000ffff [15:0] CH0_CTR (0x0000) + io_rw_32 ctr; + + _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC + // Counter compare values + // 0xffff0000 [31:16] B (0x0000) + // 0x0000ffff [15:0] A (0x0000) + io_rw_32 cc; + + _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP + // Counter wrap value + // 0x0000ffff [15:0] CH0_TOP (0xffff) + io_rw_32 top; +} pwm_slice_hw_t; + +typedef struct { + _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_ro_32 ints; +} pwm_irq_ctrl_hw_t; + +typedef struct { + pwm_slice_hw_t slice[12]; + + _REG_(PWM_EN_OFFSET) // PWM_EN + // This register aliases the CSR_EN bits for all channels + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 en; + + _REG_(PWM_INTR_OFFSET) // PWM_INTR + // Raw Interrupts + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intr; + + union { + struct { + _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints; + + _REG_(PWM_IRQ1_INTE_OFFSET) // PWM_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte1; + + _REG_(PWM_IRQ1_INTF_OFFSET) // PWM_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf1; + + _REG_(PWM_IRQ1_INTS_OFFSET) // PWM_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints1; + }; + pwm_irq_ctrl_hw_t irq_ctrl[2]; + }; +} pwm_hw_t; + +#define pwm_hw ((pwm_hw_t *)PWM_BASE) +static_assert(sizeof (pwm_hw_t) == 0x0110, ""); + +#endif // _HARDWARE_STRUCTS_PWM_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/qmi.h b/src/rp2350/hardware_structs/include/hardware/structs/qmi.h new file mode 100644 index 000000000..bbcbd7698 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/qmi.h @@ -0,0 +1,125 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_QMI_H +#define _HARDWARE_STRUCTS_QMI_H + +/** + * \file rp2350/qmi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/qmi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/qmi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(QMI_M0_TIMING_OFFSET) // QMI_M0_TIMING + // Timing configuration register for memory address window 0 + // 0xc0000000 [31:30] COOLDOWN (0x1) Chip select cooldown period + // 0x30000000 [29:28] PAGEBREAK (0x0) When page break is enabled, chip select will... + // 0x02000000 [25] SELECT_SETUP (0) Add up to one additional system clock cycle of setup... + // 0x01800000 [24:23] SELECT_HOLD (0x0) Add up to three additional system clock cycles of active... + // 0x007e0000 [22:17] MAX_SELECT (0x00) Enforce a maximum assertion duration for this window's... + // 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window's chip select is deasserted, it... + // 0x00000700 [10:8] RXDELAY (0x0) Delay the read data sample timing, in units of one half... + // 0x000000ff [7:0] CLKDIV (0x04) Clock divisor + io_rw_32 timing; + + _REG_(QMI_M0_RFMT_OFFSET) // QMI_M0_RFMT + // Read transfer format configuration for memory address window 0. + // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for read commands:... + // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... + // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits + // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits + // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer + // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any + // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any + // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address + // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any + io_rw_32 rfmt; + + _REG_(QMI_M0_RCMD_OFFSET) // QMI_M0_RCMD + // Command constants used for reads from memory address window 0. + // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... + // 0x000000ff [7:0] PREFIX (0x03) The command prefix bits to prepend on each new transfer,... + io_rw_32 rcmd; + + _REG_(QMI_M0_WFMT_OFFSET) // QMI_M0_WFMT + // Write transfer format configuration for memory address window 0. + // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for write commands:... + // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... + // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits + // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits + // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer + // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any + // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any + // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address + // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any + io_rw_32 wfmt; + + _REG_(QMI_M0_WCMD_OFFSET) // QMI_M0_WCMD + // Command constants used for writes to memory address window 0. + // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... + // 0x000000ff [7:0] PREFIX (0x02) The command prefix bits to prepend on each new transfer,... + io_rw_32 wcmd; +} qmi_mem_hw_t; + +typedef struct { + _REG_(QMI_DIRECT_CSR_OFFSET) // QMI_DIRECT_CSR + // Control and status for direct serial mode + // 0xc0000000 [31:30] RXDELAY (0x0) Delay the read data sample timing, in units of one half... + // 0x3fc00000 [29:22] CLKDIV (0x06) Clock divisor for direct serial mode + // 0x001c0000 [20:18] RXLEVEL (0x0) Current level of DIRECT_RX FIFO + // 0x00020000 [17] RXFULL (0) When 1, the DIRECT_RX FIFO is currently full + // 0x00010000 [16] RXEMPTY (0) When 1, the DIRECT_RX FIFO is currently empty + // 0x00007000 [14:12] TXLEVEL (0x0) Current level of DIRECT_TX FIFO + // 0x00000800 [11] TXEMPTY (0) When 1, the DIRECT_TX FIFO is currently empty + // 0x00000400 [10] TXFULL (0) When 1, the DIRECT_TX FIFO is currently full + // 0x00000080 [7] AUTO_CS1N (0) When 1, automatically assert the CS1n chip select line... + // 0x00000040 [6] AUTO_CS0N (0) When 1, automatically assert the CS0n chip select line... + // 0x00000008 [3] ASSERT_CS1N (0) When 1, assert (i + // 0x00000004 [2] ASSERT_CS0N (0) When 1, assert (i + // 0x00000002 [1] BUSY (0) Direct mode busy flag + // 0x00000001 [0] EN (0) Enable direct mode + io_rw_32 direct_csr; + + _REG_(QMI_DIRECT_TX_OFFSET) // QMI_DIRECT_TX + // Transmit FIFO for direct mode + // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... + // 0x00080000 [19] OE (0) Output enable (active-high) + // 0x00040000 [18] DWIDTH (0) Data width + // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... + // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... + io_wo_32 direct_tx; + + _REG_(QMI_DIRECT_RX_OFFSET) // QMI_DIRECT_RX + // Receive FIFO for direct mode + // 0x0000ffff [15:0] DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... + io_ro_32 direct_rx; + + qmi_mem_hw_t m[2]; + + // (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes) + _REG_(QMI_ATRANS0_OFFSET) // QMI_ATRANS0 + // Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + // 0x07ff0000 [26:16] SIZE (0x400) Translation aperture size for this virtual address... + // 0x00000fff [11:0] BASE (0x000) Physical address base for this virtual address range, in... + io_rw_32 atrans[8]; +} qmi_hw_t; + +#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE) +static_assert(sizeof (qmi_hw_t) == 0x0054, ""); + +#endif // _HARDWARE_STRUCTS_QMI_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/resets.h b/src/rp2350/hardware_structs/include/hardware/structs/resets.h new file mode 100644 index 000000000..5d5d0e698 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/resets.h @@ -0,0 +1,166 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RESETS_H +#define _HARDWARE_STRUCTS_RESETS_H + +/** + * \file rp2350/resets.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/resets.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_resets +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Resettable component numbers on RP2350 (used as typedef \ref reset_num_t) + * \ingroup hardware_resets + */ +typedef enum reset_num_rp2350 { + RESET_ADC = 0, ///< Select ADC to be reset + RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset + RESET_DMA = 2, ///< Select DMA to be reset + RESET_HSTX = 3, ///< Select HSTX to be reset + RESET_I2C0 = 4, ///< Select I2C0 to be reset + RESET_I2C1 = 5, ///< Select I2C1 to be reset + RESET_IO_BANK0 = 6, ///< Select IO_BANK0 to be reset + RESET_IO_QSPI = 7, ///< Select IO_QSPI to be reset + RESET_JTAG = 8, ///< Select JTAG to be reset + RESET_PADS_BANK0 = 9, ///< Select PADS_BANK0 to be reset + RESET_PADS_QSPI = 10, ///< Select PADS_QSPI to be reset + RESET_PIO0 = 11, ///< Select PIO0 to be reset + RESET_PIO1 = 12, ///< Select PIO1 to be reset + RESET_PIO2 = 13, ///< Select PIO2 to be reset + RESET_PLL_SYS = 14, ///< Select PLL_SYS to be reset + RESET_PLL_USB = 15, ///< Select PLL_USB to be reset + RESET_PWM = 16, ///< Select PWM to be reset + RESET_SHA256 = 17, ///< Select SHA256 to be reset + RESET_SPI0 = 18, ///< Select SPI0 to be reset + RESET_SPI1 = 19, ///< Select SPI1 to be reset + RESET_SYSCFG = 20, ///< Select SYSCFG to be reset + RESET_SYSINFO = 21, ///< Select SYSINFO to be reset + RESET_TBMAN = 22, ///< Select TBMAN to be reset + RESET_TIMER0 = 23, ///< Select TIMER0 to be reset + RESET_TIMER1 = 24, ///< Select TIMER1 to be reset + RESET_TRNG = 25, ///< Select TRNG to be reset + RESET_UART0 = 26, ///< Select UART0 to be reset + RESET_UART1 = 27, ///< Select UART1 to be reset + RESET_USBCTRL = 28, ///< Select USBCTRL to be reset + RESET_COUNT +} reset_num_t; + +/// \tag::resets_hw[] +typedef struct { + _REG_(RESETS_RESET_OFFSET) // RESETS_RESET + // 0x10000000 [28] USBCTRL (1) + // 0x08000000 [27] UART1 (1) + // 0x04000000 [26] UART0 (1) + // 0x02000000 [25] TRNG (1) + // 0x01000000 [24] TIMER1 (1) + // 0x00800000 [23] TIMER0 (1) + // 0x00400000 [22] TBMAN (1) + // 0x00200000 [21] SYSINFO (1) + // 0x00100000 [20] SYSCFG (1) + // 0x00080000 [19] SPI1 (1) + // 0x00040000 [18] SPI0 (1) + // 0x00020000 [17] SHA256 (1) + // 0x00010000 [16] PWM (1) + // 0x00008000 [15] PLL_USB (1) + // 0x00004000 [14] PLL_SYS (1) + // 0x00002000 [13] PIO2 (1) + // 0x00001000 [12] PIO1 (1) + // 0x00000800 [11] PIO0 (1) + // 0x00000400 [10] PADS_QSPI (1) + // 0x00000200 [9] PADS_BANK0 (1) + // 0x00000100 [8] JTAG (1) + // 0x00000080 [7] IO_QSPI (1) + // 0x00000040 [6] IO_BANK0 (1) + // 0x00000020 [5] I2C1 (1) + // 0x00000010 [4] I2C0 (1) + // 0x00000008 [3] HSTX (1) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] BUSCTRL (1) + // 0x00000001 [0] ADC (1) + io_rw_32 reset; + + _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL + // 0x10000000 [28] USBCTRL (0) + // 0x08000000 [27] UART1 (0) + // 0x04000000 [26] UART0 (0) + // 0x02000000 [25] TRNG (0) + // 0x01000000 [24] TIMER1 (0) + // 0x00800000 [23] TIMER0 (0) + // 0x00400000 [22] TBMAN (0) + // 0x00200000 [21] SYSINFO (0) + // 0x00100000 [20] SYSCFG (0) + // 0x00080000 [19] SPI1 (0) + // 0x00040000 [18] SPI0 (0) + // 0x00020000 [17] SHA256 (0) + // 0x00010000 [16] PWM (0) + // 0x00008000 [15] PLL_USB (0) + // 0x00004000 [14] PLL_SYS (0) + // 0x00002000 [13] PIO2 (0) + // 0x00001000 [12] PIO1 (0) + // 0x00000800 [11] PIO0 (0) + // 0x00000400 [10] PADS_QSPI (0) + // 0x00000200 [9] PADS_BANK0 (0) + // 0x00000100 [8] JTAG (0) + // 0x00000080 [7] IO_QSPI (0) + // 0x00000040 [6] IO_BANK0 (0) + // 0x00000020 [5] I2C1 (0) + // 0x00000010 [4] I2C0 (0) + // 0x00000008 [3] HSTX (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_rw_32 wdsel; + + _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE + // 0x10000000 [28] USBCTRL (0) + // 0x08000000 [27] UART1 (0) + // 0x04000000 [26] UART0 (0) + // 0x02000000 [25] TRNG (0) + // 0x01000000 [24] TIMER1 (0) + // 0x00800000 [23] TIMER0 (0) + // 0x00400000 [22] TBMAN (0) + // 0x00200000 [21] SYSINFO (0) + // 0x00100000 [20] SYSCFG (0) + // 0x00080000 [19] SPI1 (0) + // 0x00040000 [18] SPI0 (0) + // 0x00020000 [17] SHA256 (0) + // 0x00010000 [16] PWM (0) + // 0x00008000 [15] PLL_USB (0) + // 0x00004000 [14] PLL_SYS (0) + // 0x00002000 [13] PIO2 (0) + // 0x00001000 [12] PIO1 (0) + // 0x00000800 [11] PIO0 (0) + // 0x00000400 [10] PADS_QSPI (0) + // 0x00000200 [9] PADS_BANK0 (0) + // 0x00000100 [8] JTAG (0) + // 0x00000080 [7] IO_QSPI (0) + // 0x00000040 [6] IO_BANK0 (0) + // 0x00000020 [5] I2C1 (0) + // 0x00000010 [4] I2C0 (0) + // 0x00000008 [3] HSTX (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_ro_32 reset_done; +} resets_hw_t; +/// \end::resets_hw[] + +#define resets_hw ((resets_hw_t *)RESETS_BASE) +static_assert(sizeof (resets_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_RESETS_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/rosc.h b/src/rp2350/hardware_structs/include/hardware/structs/rosc.h new file mode 100644 index 000000000..73503cc15 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/rosc.h @@ -0,0 +1,99 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ROSC_H +#define _HARDWARE_STRUCTS_ROSC_H + +/** + * \file rp2350/rosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/rosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_rosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL + // Ring Oscillator control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE + + // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring + + io_rw_32 ctrl; + + _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA + // Ring Oscillator frequency control A + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength + // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength + // 0x00000080 [7] DS1_RANDOM (0) Randomises the stage 1 drive strength + // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength + // 0x00000008 [3] DS0_RANDOM (0) Randomises the stage 0 drive strength + // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength + io_rw_32 freqa; + + _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB + // Ring Oscillator frequency control B + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength + // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength + // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength + // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength + io_rw_32 freqb; + + _REG_(ROSC_RANDOM_OFFSET) // ROSC_RANDOM + // Loads a value to the LFSR randomiser + // 0xffffffff [31:0] SEED (0x3f04b16d) + io_rw_32 random; + + _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT + // Ring Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC + + io_rw_32 dormant; + + _REG_(ROSC_DIV_OFFSET) // ROSC_DIV + // Controls the output divider + // 0x0000ffff [15:0] DIV (-) set to 0xaa00 + div where + + io_rw_32 div; + + _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE + // Controls the phase shifted output + // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa + + // 0x00000008 [3] ENABLE (1) enable the phase-shifted output + + // 0x00000004 [2] FLIP (0) invert the phase-shifted output + + // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks + + io_rw_32 phase; + + _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS + // Ring Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00010000 [16] DIV_RUNNING (-) post-divider is running + + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable + + io_rw_32 status; + + _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT + // Returns a 1 bit random value + // 0x00000001 [0] RANDOMBIT (1) + io_ro_32 randombit; + + _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT + // A down counter running at the ROSC frequency which counts to zero and stops. + // 0x0000ffff [15:0] COUNT (0x0000) + io_rw_32 count; +} rosc_hw_t; + +#define rosc_hw ((rosc_hw_t *)ROSC_BASE) +static_assert(sizeof (rosc_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_ROSC_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/sau.h b/src/rp2350/hardware_structs/include/hardware/structs/sau.h new file mode 100644 index 000000000..803f35637 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/sau.h @@ -0,0 +1,65 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SAU_H +#define _HARDWARE_STRUCTS_SAU_H + +/** + * \file rp2350/sau.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL + // Allows enabling of the Security Attribution Unit + // 0x00000002 [1] ALLNS (0) When SAU_CTRL + // 0x00000001 [0] ENABLE (0) Enables the SAU + io_rw_32 ctrl; + + _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE + // Indicates the number of regions implemented by the Security Attribution Unit + // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions + io_ro_32 type; + + _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR + // Selects the region currently accessed by SAU_RBAR and SAU_RLAR + // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + io_rw_32 rnr; + + _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR + // Provides indirect read and write access to the base address of the currently selected SAU region + // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region + io_rw_32 rbar; + + _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR + // Provides indirect read and write access to the limit address of the currently selected SAU region + // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... + // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... + // 0x00000001 [0] ENABLE (0) SAU region enable + io_rw_32 rlar; +} armv8m_sau_hw_t; + +#define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET)) +#define sau_ns_hw ((armv8m_sau_hw_t *)(PPB_NONSEC_BASE + M33_SAU_CTRL_OFFSET)) +static_assert(sizeof (armv8m_sau_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_SAU_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/scb.h b/src/rp2350/hardware_structs/include/hardware/structs/scb.h new file mode 100644 index 000000000..9777023dc --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/scb.h @@ -0,0 +1,264 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SCB_H +#define _HARDWARE_STRUCTS_SCB_H + +/** + * \file rp2350/scb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_CPUID_OFFSET) // M33_CPUID + // Provides identification information for the PE, including an implementer code for the device and... + // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... + // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number + // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE + // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device + // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device + io_ro_32 cpuid; + + _REG_(M33_ICSR_OFFSET) // M33_ICSR + // Controls and provides status information for NMI, PendSV, SysTick and interrupts + // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending + // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared + // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending + // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS + // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending + // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS + // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... + // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... + // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... + // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... + // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... + // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception + io_rw_32 icsr; + + _REG_(M33_VTOR_OFFSET) // M33_VTOR + // Vector Table Offset Register + // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field + io_rw_32 vtor; + + _REG_(M33_AIRCR_OFFSET) // M33_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions + // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable + // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field + // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M33_SCR_OFFSET) // M33_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M33_CCR_OFFSET) // M33_CCR + // Sets or returns configuration and control data + // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS + // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... + // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS + // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... + // 0x00000200 [9] RES1 (1) Reserved, RES1 + // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... + // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... + // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses + // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... + // 0x00000001 [0] RES1_1 (1) Reserved, RES1 + io_rw_32 ccr; + + // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) + _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 + // Sets or returns priority for system handlers 4 - 7 + // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault + // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault + // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault + // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault + io_rw_32 shpr[3]; + + _REG_(M33_SHCSR_OFFSET) // M33_SHCSR + // Provides access to the active and pending status of system exceptions + // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS + // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception + // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled + // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS + // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled + // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS + // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS + // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception + // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS + // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... + // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS + // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS + // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception + // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS + // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception + // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception + // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS + // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... + // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception + // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS + io_rw_32 shcsr; + + _REG_(M33_CFSR_OFFSET) // M33_CFSR + // Contains the three Configurable Fault Status Registers + // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... + // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... + // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... + // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... + // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... + // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR + // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... + // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register + // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... + // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... + // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... + // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred + // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred + // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... + // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions + io_rw_32 cfsr; + + _REG_(M33_HFSR_OFFSET) // M33_HFSR + // Shows the cause of any HardFaults + // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred + // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... + // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... + io_rw_32 hfsr; + + _REG_(M33_DFSR_OFFSET) // M33_DFSR + // Shows which debug event occurred + // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... + // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... + // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... + // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... + // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... + io_rw_32 dfsr; + + _REG_(M33_MMFAR_OFFSET) // M33_MMFAR + // Shows the address of the memory location that caused an MPU fault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 mmfar; + + _REG_(M33_BFAR_OFFSET) // M33_BFAR + // Shows the address associated with a precise data access BusFault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 bfar; + + uint32_t _pad0; + + // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) + _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 + // Gives top-level information about the instruction set supported by the PE + // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support + // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support + io_ro_32 id_pfr[2]; + + _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 + // Provides top level information about the debug system + // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture + io_ro_32 id_dfr0; + + _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 + // Provides information about the IMPLEMENTATION DEFINED features of the PE + // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning + // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning + // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning + // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning + io_ro_32 id_afr0; + + // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) + _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 + // Provides information about the implemented memory model and memory management support + // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers + // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) + // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented + // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented + // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... + io_ro_32 id_mmfr[4]; + + // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) + _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 + // Provides information about the instruction set implemented by the PE + // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions + // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions + // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions + // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions + // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions + // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions + io_ro_32 id_isar[6]; + + uint32_t _pad1; + + _REG_(M33_CTR_OFFSET) // M33_CTR + // Provides information about the architecture of the caches + // 0x80000000 [31] RES1 (1) Reserved, RES1 + // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... + // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... + // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... + // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 + // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... + io_ro_32 ctr; + + uint32_t _pad2[2]; + + _REG_(M33_CPACR_OFFSET) // M33_CPACR + // Specifies the access privileges for coprocessors and the FP Extension + // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored + // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality + // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 + // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 + // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 + // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 + // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 + // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 + // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 + // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 + io_rw_32 cpacr; + + _REG_(M33_NSACR_OFFSET) // M33_NSACR + // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 + // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 + // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 + // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 + // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 + // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 + // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 + // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 + io_rw_32 nsacr; +} armv8m_scb_hw_t; + +#define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET)) +#define scb_ns_hw ((armv8m_scb_hw_t *)(PPB_NONSEC_BASE + M33_CPUID_OFFSET)) +static_assert(sizeof (armv8m_scb_hw_t) == 0x0090, ""); + +#endif // _HARDWARE_STRUCTS_SCB_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/sha256.h b/src/rp2350/hardware_structs/include/hardware/structs/sha256.h new file mode 100644 index 000000000..248a00ab4 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/sha256.h @@ -0,0 +1,53 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SHA256_H +#define _HARDWARE_STRUCTS_SHA256_H + +/** + * \file rp2350/sha256.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sha256.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sha256 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sha256.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SHA256_CSR_OFFSET) // SHA256_CSR + // Control and status register + // 0x00001000 [12] BSWAP (1) Enable byte swapping of 32-bit values at the point they... + // 0x00000300 [9:8] DMA_SIZE (0x2) Configure DREQ logic for the correct DMA data size + // 0x00000010 [4] ERR_WDATA_NOT_RDY (0) Set when a write occurs whilst the SHA-256 core is not... + // 0x00000004 [2] SUM_VLD (1) If 1, the SHA-256 checksum presented in registers SUM0... + // 0x00000002 [1] WDATA_RDY (1) If 1, the SHA-256 core is ready to accept more data... + // 0x00000001 [0] START (0) Write 1 to prepare the SHA-256 core for a new checksum + io_rw_32 csr; + + _REG_(SHA256_WDATA_OFFSET) // SHA256_WDATA + // Write data register + // 0xffffffff [31:0] WDATA (0x00000000) After pulsing START and writing 16 words of data to this... + io_wo_32 wdata; + + // (Description copied from array index 0 register SHA256_SUM0 applies similarly to other array indexes) + _REG_(SHA256_SUM0_OFFSET) // SHA256_SUM0 + // 256-bit checksum result + // 0xffffffff [31:0] SUM0 (0x00000000) + io_ro_32 sum[8]; +} sha256_hw_t; + +#define sha256_hw ((sha256_hw_t *)SHA256_BASE) +static_assert(sizeof (sha256_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SHA256_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/sio.h b/src/rp2350/hardware_structs/include/hardware/structs/sio.h new file mode 100644 index 000000000..49a452c8a --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/sio.h @@ -0,0 +1,336 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +/** + * \file rp2350/sio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +typedef struct { + _REG_(SIO_CPUID_OFFSET) // SIO_CPUID + // Processor core identifier + // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... + io_ro_32 cpuid; + + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN + // Input value for GPIO0 + // 0xffffffff [31:0] GPIO_IN (0x00000000) + io_ro_32 gpio_in; + + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN + // Input value on GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + // 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Input value on USB D- pin + // 0x01000000 [24] USB_DP (0) Input value on USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32 + io_ro_32 gpio_hi_in; + + uint32_t _pad0; + + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 + io_rw_32 gpio_out; + + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT + // Output value for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + // 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Output value for USB D- pin + // 0x01000000 [24] USB_DP (0) Output value for USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32 + io_rw_32 gpio_hi_out; + + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i + io_wo_32 gpio_set; + + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET + // Output value set for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_set; + + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i + io_wo_32 gpio_clr; + + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR + // Output value clear for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_clr; + + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i + io_wo_32 gpio_togl; + + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR + // Output value XOR for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_togl; + + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE + // GPIO0 + // 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 + io_rw_32 gpio_oe; + + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE + // Output enable value for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2... + // 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin + // 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32 + io_rw_32 gpio_hi_oe; + + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i + io_wo_32 gpio_oe_set; + + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET + // Output enable set for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_set; + + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i + io_wo_32 gpio_oe_clr; + + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR + // Output enable clear for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_clr; + + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i + io_wo_32 gpio_oe_togl; + + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR + // Output enable XOR for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_togl; + + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST + // Status register for inter-core FIFOs (mailboxes). + // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i + io_rw_32 fifo_st; + + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR + // Write access to this core's TX FIFO + // 0xffffffff [31:0] FIFO_WR (0x00000000) + io_wo_32 fifo_wr; + + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD + // Read access to this core's RX FIFO + // 0xffffffff [31:0] FIFO_RD (-) + io_ro_32 fifo_rd; + + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST + // Spinlock state + // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) + io_ro_32 spinlock_st; + + uint32_t _pad1[8]; + + interp_hw_t interp[2]; + + // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) + _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 + // Spinlock register 0 + // 0xffffffff [31:0] SPINLOCK0 (0x00000000) + io_rw_32 spinlock[32]; + + _REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET + // Trigger a doorbell interrupt on the opposite core + // 0x000000ff [7:0] DOORBELL_OUT_SET (0x00) + io_rw_32 doorbell_out_set; + + _REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR + // Clear doorbells which have been posted to the opposite core + // 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00) + io_rw_32 doorbell_out_clr; + + _REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET + // Write 1s to trigger doorbell interrupts on this core + // 0x000000ff [7:0] DOORBELL_IN_SET (0x00) + io_rw_32 doorbell_in_set; + + _REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR + // Check and acknowledge doorbells posted to this core + // 0x000000ff [7:0] DOORBELL_IN_CLR (0x00) + io_rw_32 doorbell_in_clr; + + _REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC + // Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so... + // 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure... + // 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the... + // 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the... + io_rw_32 peri_nonsec; + + uint32_t _pad2[3]; + + _REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ + // Control the assertion of the standard software interrupt (MIP + // 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag + // 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag + // 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag + // 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag + io_rw_32 riscv_softirq; + + _REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL + // Control register for the RISC-V 64-bit Machine-mode timer + // 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state + // 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state + // 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i + // 0x00000001 [0] EN (1) Timer enable bit + io_rw_32 mtime_ctrl; + + uint32_t _pad3[2]; + + _REG_(SIO_MTIME_OFFSET) // SIO_MTIME + // Read/write access to the high half of RISC-V Machine-mode timer + // 0xffffffff [31:0] MTIME (0x00000000) + io_rw_32 mtime; + + _REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH + // Read/write access to the high half of RISC-V Machine-mode timer + // 0xffffffff [31:0] MTIMEH (0x00000000) + io_rw_32 mtimeh; + + _REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP + // Low half of RISC-V Machine-mode timer comparator + // 0xffffffff [31:0] MTIMECMP (0xffffffff) + io_rw_32 mtimecmp; + + _REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH + // High half of RISC-V Machine-mode timer comparator + // 0xffffffff [31:0] MTIMECMPH (0xffffffff) + io_rw_32 mtimecmph; + + _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL + // Control register for TMDS encoder + // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders + // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... + // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... + // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE + // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... + // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... + // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... + // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + io_rw_32 tmds_ctrl; + + _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA + // Write-only access to the TMDS colour data register + // 0xffffffff [31:0] TMDS_WDATA (0x00000000) + io_wo_32 tmds_wdata; + + _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) + // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) + io_ro_32 tmds_peek_single; + + _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value + // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) + io_ro_32 tmds_pop_single; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_peek_double_l0; + + _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_pop_double_l0; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_peek_double_l1; + + _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_pop_double_l1; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_peek_double_l2; + + _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_pop_double_l2; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) +#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE) +static_assert(sizeof (sio_hw_t) == 0x01e8, ""); + +#endif // _HARDWARE_STRUCTS_SIO_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/spi.h b/src/rp2350/hardware_structs/include/hardware/structs/spi.h new file mode 100644 index 000000000..454128ea2 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/spi.h @@ -0,0 +1,105 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SPI_H +#define _HARDWARE_STRUCTS_SPI_H + +/** + * \file rp2350/spi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/spi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_spi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 + // Control register 0, SSPCR0 on page 3-4 + // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate + // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only + // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format + // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation + io_rw_32 cr0; + + _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 + // Control register 1, SSPCR1 on page 3-5 + // 0x00000008 [3] SOD (0) Slave-mode output disable + // 0x00000004 [2] MS (0) Master or slave mode select + // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled + // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled + io_rw_32 cr1; + + _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR + // Data register, SSPDR on page 3-6 + // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO + io_rw_32 dr; + + _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR + // Status register, SSPSR on page 3-7 + // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle + // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full + // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty + // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full + // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty + io_ro_32 sr; + + _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR + // Clock prescale register, SSPCPSR on page 3-8 + // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor + io_rw_32 cpsr; + + _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC + // Interrupt mask set or clear register, SSPIMSC on page 3-9 + // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty... + // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or... + // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty... + // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written... + io_rw_32 imsc; + + _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS + // Raw interrupt status register, SSPRIS on page 3-10 + // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the... + // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the... + io_ro_32 ris; + + _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS + // Masked interrupt status register, SSPMIS on page 3-11 + // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after... + // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after... + // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after... + // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,... + io_ro_32 mis; + + _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR + // Interrupt clear register, SSPICR on page 3-11 + // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt + // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt + io_rw_32 icr; + + _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR + // DMA control register, SSPDMACR on page 3-12 + // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RXDMAE (0) Receive DMA Enable + io_rw_32 dmacr; +} spi_hw_t; + +#define spi0_hw ((spi_hw_t *)SPI0_BASE) +#define spi1_hw ((spi_hw_t *)SPI1_BASE) +static_assert(sizeof (spi_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SPI_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/syscfg.h b/src/rp2350/hardware_structs/include/hardware/structs/syscfg.h new file mode 100644 index 000000000..8909c0dbf --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/syscfg.h @@ -0,0 +1,83 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSCFG_H +#define _HARDWARE_STRUCTS_SYSCFG_H + +/** + * \file rp2350/syscfg.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/syscfg.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_syscfg +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG + // Configuration for processors + // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted + // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted + io_ro_32 proc_config; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0xffffffff [31:0] GPIO (0x00000000) + io_rw_32 proc_in_sync_bypass; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_rw_32 proc_in_sync_bypass_hi; + + _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE + // Directly control the chip SWD debug port + // 0x00000008 [3] ATTACH (0) Attach chip debug port to syscfg controls, and... + // 0x00000004 [2] SWCLK (1) Directly drive SWCLK, if ATTACH is set + // 0x00000002 [1] SWDI (1) Directly drive SWDIO input, if ATTACH is set + // 0x00000001 [0] SWDO (-) Observe the value of SWDIO output + io_rw_32 dbgforce; + + _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN + // Control PD pins to memories + // 0x00001000 [12] BOOTRAM (0) + // 0x00000800 [11] ROM (0) + // 0x00000400 [10] USB (0) + // 0x00000200 [9] SRAM9 (0) + // 0x00000100 [8] SRAM8 (0) + // 0x00000080 [7] SRAM7 (0) + // 0x00000040 [6] SRAM6 (0) + // 0x00000020 [5] SRAM5 (0) + // 0x00000010 [4] SRAM4 (0) + // 0x00000008 [3] SRAM3 (0) + // 0x00000004 [2] SRAM2 (0) + // 0x00000002 [1] SRAM1 (0) + // 0x00000001 [0] SRAM0 (0) + io_rw_32 mempowerdown; + + _REG_(SYSCFG_AUXCTRL_OFFSET) // SYSCFG_AUXCTRL + // Auxiliary system control register + // 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:2: Reserved + io_rw_32 auxctrl; +} syscfg_hw_t; + +#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) +static_assert(sizeof (syscfg_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_SYSCFG_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/sysinfo.h b/src/rp2350/hardware_structs/include/hardware/structs/sysinfo.h new file mode 100644 index 000000000..688b577e4 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/sysinfo.h @@ -0,0 +1,60 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSINFO_H +#define _HARDWARE_STRUCTS_SYSINFO_H + +/** + * \file rp2350/sysinfo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sysinfo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sysinfo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID + // JEDEC JEP-106 compliant chip identifier + // 0xf0000000 [31:28] REVISION (-) + // 0x0ffff000 [27:12] PART (-) + // 0x00000ffe [11:1] MANUFACTURER (-) + // 0x00000001 [0] STOP_BIT (1) + io_ro_32 chip_id; + + _REG_(SYSINFO_PACKAGE_SEL_OFFSET) // SYSINFO_PACKAGE_SEL + // 0x00000001 [0] PACKAGE_SEL (0) + io_ro_32 package_sel; + + _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM + // Platform register + // 0x00000010 [4] GATESIM (-) + // 0x00000008 [3] BATCHSIM (-) + // 0x00000004 [2] HDLSIM (-) + // 0x00000002 [1] ASIC (-) + // 0x00000001 [0] FPGA (-) + io_ro_32 platform; + + uint32_t _pad0[2]; + + _REG_(SYSINFO_GITREF_RP2350_OFFSET) // SYSINFO_GITREF_RP2350 + // Git hash of the chip source + // 0xffffffff [31:0] GITREF_RP2350 (-) + io_ro_32 gitref_rp2350; +} sysinfo_hw_t; + +#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) +static_assert(sizeof (sysinfo_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_SYSINFO_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/systick.h b/src/rp2350/hardware_structs/include/hardware/structs/systick.h new file mode 100644 index 000000000..f6024b1e9 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/systick.h @@ -0,0 +1,62 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSTICK_H +#define _HARDWARE_STRUCTS_SYSTICK_H + +/** + * \file rp2350/systick.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 csr; + + _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 rvr; + + _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 cvr; + + _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 calib; +} systick_hw_t; + +#define systick_hw ((systick_hw_t *)(PPB_BASE + M33_SYST_CSR_OFFSET)) +#define systick_ns_hw ((systick_hw_t *)(PPB_NONSEC_BASE + M33_SYST_CSR_OFFSET)) +static_assert(sizeof (systick_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_SYSTICK_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/tbman.h b/src/rp2350/hardware_structs/include/hardware/structs/tbman.h new file mode 100644 index 000000000..58d80dd86 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/tbman.h @@ -0,0 +1,39 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TBMAN_H +#define _HARDWARE_STRUCTS_TBMAN_H + +/** + * \file rp2350/tbman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/tbman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_tbman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM + // Indicates the type of platform in use + // 0x00000004 [2] HDLSIM (0) Indicates the platform is a simulation + // 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA + // 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC + io_ro_32 platform; +} tbman_hw_t; + +#define tbman_hw ((tbman_hw_t *)TBMAN_BASE) +static_assert(sizeof (tbman_hw_t) == 0x0004, ""); + +#endif // _HARDWARE_STRUCTS_TBMAN_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/ticks.h b/src/rp2350/hardware_structs/include/hardware/structs/ticks.h new file mode 100644 index 000000000..b436484a3 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/ticks.h @@ -0,0 +1,63 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TICKS_H +#define _HARDWARE_STRUCTS_TICKS_H + +/** + * \file rp2350/ticks.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/ticks.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_ticks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/ticks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/*! \brief Tick generator numbers on RP2350 (used as typedef \ref tick_gen_num_t) + * \ingroup hardware_ticks + */ +typedef enum tick_gen_num_rp2350 { + TICK_PROC0 = 0, + TICK_PROC1 = 1, + TICK_TIMER0 = 2, + TICK_TIMER1 = 3, + TICK_WATCHDOG = 4, + TICK_RISCV = 5, + TICK_COUNT +} tick_gen_num_t; + +typedef struct { + _REG_(TICKS_PROC0_CTRL_OFFSET) // TICKS_PROC0_CTRL + // Controls the tick generator + // 0x00000002 [1] RUNNING (-) Is the tick generator running? + // 0x00000001 [0] ENABLE (0) start / stop tick generation + io_rw_32 ctrl; + + _REG_(TICKS_PROC0_CYCLES_OFFSET) // TICKS_PROC0_CYCLES + // 0x000001ff [8:0] PROC0_CYCLES (0x000) Total number of clk_tick cycles before the next tick + io_rw_32 cycles; + + _REG_(TICKS_PROC0_COUNT_OFFSET) // TICKS_PROC0_COUNT + // 0x000001ff [8:0] PROC0_COUNT (-) Count down timer: the remaining number clk_tick cycles... + io_ro_32 count; +} ticks_slice_hw_t; + +typedef struct { + ticks_slice_hw_t ticks[6]; +} ticks_hw_t; + +#define ticks_hw ((ticks_hw_t *)TICKS_BASE) +static_assert(sizeof (ticks_hw_t) == 0x0048, ""); + +#endif // _HARDWARE_STRUCTS_TICKS_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/timer.h b/src/rp2350/hardware_structs/include/hardware/structs/timer.h new file mode 100644 index 000000000..978dd5688 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/timer.h @@ -0,0 +1,127 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TIMER_H +#define _HARDWARE_STRUCTS_TIMER_H + +/** + * \file rp2350/timer.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/timer.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_timer +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW + // Write to bits 63:32 of time always write timelw before timehw + // 0xffffffff [31:0] TIMEHW (0x00000000) + io_wo_32 timehw; + + _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW + // Write to bits 31:0 of time writes do not get copied to time until timehw is written + // 0xffffffff [31:0] TIMELW (0x00000000) + io_wo_32 timelw; + + _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR + // Read from bits 63:32 of time always read timelr before timehr + // 0xffffffff [31:0] TIMEHR (0x00000000) + io_ro_32 timehr; + + _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR + // Read from bits 31:0 of time + // 0xffffffff [31:0] TIMELR (0x00000000) + io_ro_32 timelr; + + // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) + _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 + // Arm alarm 0, and configure the time it will fire + // 0xffffffff [31:0] ALARM0 (0x00000000) + io_rw_32 alarm[4]; + + _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED + // Indicates the armed/disarmed status of each alarm + // 0x0000000f [3:0] ARMED (0x0) + io_rw_32 armed; + + _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH + // Raw read from bits 63:32 of time (no side effects) + // 0xffffffff [31:0] TIMERAWH (0x00000000) + io_ro_32 timerawh; + + _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL + // Raw read from bits 31:0 of time (no side effects) + // 0xffffffff [31:0] TIMERAWL (0x00000000) + io_ro_32 timerawl; + + _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE + // Set bits high to enable pause when the corresponding debug ports are active + // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode + // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode + io_rw_32 dbgpause; + + _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE + // Set high to pause the timer + // 0x00000001 [0] PAUSE (0) + io_rw_32 pause; + + _REG_(TIMER_LOCKED_OFFSET) // TIMER_LOCKED + // Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + // 0x00000001 [0] LOCKED (0) + io_rw_32 locked; + + _REG_(TIMER_SOURCE_OFFSET) // TIMER_SOURCE + // Selects the source for the timer + // 0x00000001 [0] CLK_SYS (0) + io_rw_32 source; + + _REG_(TIMER_INTR_OFFSET) // TIMER_INTR + // Raw Interrupts + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intr; + + _REG_(TIMER_INTE_OFFSET) // TIMER_INTE + // Interrupt Enable + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 inte; + + _REG_(TIMER_INTF_OFFSET) // TIMER_INTF + // Interrupt Force + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intf; + + _REG_(TIMER_INTS_OFFSET) // TIMER_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_ro_32 ints; +} timer_hw_t; + +#define timer0_hw ((timer_hw_t *)TIMER0_BASE) +#define timer1_hw ((timer_hw_t *)TIMER1_BASE) +static_assert(sizeof (timer_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_TIMER_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/tmds_encode.h b/src/rp2350/hardware_structs/include/hardware/structs/tmds_encode.h new file mode 100644 index 000000000..c1213af19 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/tmds_encode.h @@ -0,0 +1,92 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TMDS_ENCODE_H +#define _HARDWARE_STRUCTS_TMDS_ENCODE_H + +/** + * \file rp2350/tmds_encode.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL + // Control register for TMDS encoder + // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders + // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... + // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... + // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE + // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... + // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... + // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... + // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + io_rw_32 tmds_ctrl; + + _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA + // Write-only access to the TMDS colour data register + // 0xffffffff [31:0] TMDS_WDATA (0x00000000) + io_wo_32 tmds_wdata; + + _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) + // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) + io_ro_32 tmds_peek_single; + + _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value + // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) + io_ro_32 tmds_pop_single; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_peek_double_l0; + + _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_pop_double_l0; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_peek_double_l1; + + _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_pop_double_l1; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_peek_double_l2; + + _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_pop_double_l2; +} tmds_encode_hw_t; + +#define tmds_encode_hw ((tmds_encode_hw_t *)(SIO_BASE + SIO_TMDS_CTRL_OFFSET)) +#define tmds_encode_ns_hw ((tmds_encode_hw_t *)(SIO_NONSEC_BASE + SIO_TMDS_CTRL_OFFSET)) +static_assert(sizeof (tmds_encode_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_TMDS_ENCODE_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/trng.h b/src/rp2350/hardware_structs/include/hardware/structs/trng.h new file mode 100644 index 000000000..5ae592961 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/trng.h @@ -0,0 +1,153 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TRNG_H +#define _HARDWARE_STRUCTS_TRNG_H + +/** + * \file rp2350/trng.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/trng.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_trng +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/trng.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR + // Interrupt masking + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000004 [2] CRNGT_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000002 [1] AUTOCORR_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000001 [0] EHR_VALID_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + io_rw_32 rng_imr; + + _REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR + // RNG status register + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR (0) 1'b1 indicates Von Neuman error + // 0x00000004 [2] CRNGT_ERR (0) 1'b1 indicates CRNGT in the RNG test failed + // 0x00000002 [1] AUTOCORR_ERR (0) 1'b1 indicates Autocorrelation test failed four times in a row + // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that 192 bits have been collected in the... + io_ro_32 rng_isr; + + _REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR + // Interrupt/status bit clear Register + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR + // 0x00000004 [2] CRNGT_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR + // 0x00000002 [1] AUTOCORR_ERR (0) Cannot be cleared by SW! Only RNG reset clears this bit + // 0x00000001 [0] EHR_VALID (0) Write 1'b1 - clear corresponding bit in RNG_ISR + io_rw_32 rng_icr; + + _REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG + // Selecting the inverter-chain length + // 0xfffffffc [31:2] RESERVED (0x00000000) RESERVED + // 0x00000003 [1:0] RND_SRC_SEL (0x0) Selects the number of inverters (out of four possible... + io_rw_32 trng_config; + + _REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID + // 192 bit collection indication + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that collection of bits in the RNG is... + io_ro_32 trng_valid; + + // (Description copied from array index 0 register TRNG_EHR_DATA0 applies similarly to other array indexes) + _REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA0 + // RNG collected bits + // 0xffffffff [31:0] EHR_DATA0 (0x00000000) Bits [31:0] of Entropy Holding Register (EHR) - RNG... + io_ro_32 ehr_data[6]; + + _REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE + // Enable signal for the random source + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RND_SRC_EN (0) * 1'b1 - entropy source is enabled + io_rw_32 rnd_source_enable; + + _REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT1 + // Counts clocks between sampling of random bit + // 0xffffffff [31:0] SAMPLE_CNTR1 (0x0000ffff) Sets the number of rng_clk cycles between two... + io_rw_32 sample_cnt1; + + _REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC + // Statistic about Autocorrelation test activations + // 0xffc00000 [31:22] RESERVED (0x000) RESERVED + // 0x003fc000 [21:14] AUTOCORR_FAILS (0x00) Count each time an autocorrelation test fails + // 0x00003fff [13:0] AUTOCORR_TRYS (0x0000) Count each time an autocorrelation test starts + io_rw_32 autocorr_statistic; + + _REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL + // Debug register + // 0x00000008 [3] AUTO_CORRELATE_BYPASS (0) When set, the autocorrelation test in the TRNG module is bypassed + // 0x00000004 [2] TRNG_CRNGT_BYPASS (0) When set, the CRNGT test in the RNG is bypassed + // 0x00000002 [1] VNC_BYPASS (0) When set, the Von-Neuman balancer is bypassed (including... + // 0x00000001 [0] RESERVED (0) N/A + io_rw_32 trng_debug_control; + + uint32_t _pad0; + + _REG_(TRNG_TRNG_SW_RESET_OFFSET) // TRNG_TRNG_SW_RESET + // Generate internal SW reset within the RNG block + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] TRNG_SW_RESET (0) Writing 1'b1 to this register causes an internal RNG reset + io_rw_32 trng_sw_reset; + + uint32_t _pad1[28]; + + _REG_(TRNG_RNG_DEBUG_EN_INPUT_OFFSET) // TRNG_RNG_DEBUG_EN_INPUT + // Enable the RNG debug mode + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RNG_DEBUG_EN (0) * 1'b1 - debug mode is enabled + io_rw_32 rng_debug_en_input; + + _REG_(TRNG_TRNG_BUSY_OFFSET) // TRNG_TRNG_BUSY + // RNG Busy indication + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] TRNG_BUSY (0) Reflects rng_busy status + io_ro_32 trng_busy; + + _REG_(TRNG_RST_BITS_COUNTER_OFFSET) // TRNG_RST_BITS_COUNTER + // Reset the counter of collected bits in the RNG + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RST_BITS_COUNTER (0) Writing any value to this address will reset the bits... + io_rw_32 rst_bits_counter; + + _REG_(TRNG_RNG_VERSION_OFFSET) // TRNG_RNG_VERSION + // Displays the version settings of the TRNG + // 0xffffff00 [31:8] RESERVED (0x000000) RESERVED + // 0x00000080 [7] RNG_USE_5_SBOXES (0) * 1'b1 - 5 SBOX AES + // 0x00000040 [6] RESEEDING_EXISTS (0) * 1'b1 - Exists + // 0x00000020 [5] KAT_EXISTS (0) * 1'b1 - Exists + // 0x00000010 [4] PRNG_EXISTS (0) * 1'b1 - Exists + // 0x00000008 [3] TRNG_TESTS_BYPASS_EN (0) * 1'b1 - Exists + // 0x00000004 [2] AUTOCORR_EXISTS (0) * 1'b1 - Exists + // 0x00000002 [1] CRNGT_EXISTS (0) * 1'b1 - Exists + // 0x00000001 [0] EHR_WIDTH_192 (0) * 1'b1 - 192-bit EHR + io_ro_32 rng_version; + + uint32_t _pad2[7]; + + // (Description copied from array index 0 register TRNG_RNG_BIST_CNTR_0 applies similarly to other array indexes) + _REG_(TRNG_RNG_BIST_CNTR_0_OFFSET) // TRNG_RNG_BIST_CNTR_0 + // Collected BIST results + // 0xffc00000 [31:22] RESERVED (0x000) RESERVED + // 0x003fffff [21:0] ROSC_CNTR_VAL (0x000000) Reflects the results of RNG BIST counter + io_ro_32 rng_bist_cntr[3]; +} trng_hw_t; + +#define trng_hw ((trng_hw_t *)(TRNG_BASE + TRNG_RNG_IMR_OFFSET)) +static_assert(sizeof (trng_hw_t) == 0x00ec, ""); + +#endif // _HARDWARE_STRUCTS_TRNG_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/uart.h b/src/rp2350/hardware_structs/include/hardware/structs/uart.h new file mode 100644 index 000000000..47ff324e3 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/uart.h @@ -0,0 +1,182 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_UART_H +#define _HARDWARE_STRUCTS_UART_H + +/** + * \file rp2350/uart.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/uart.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_uart +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(UART_UARTDR_OFFSET) // UART_UARTDR + // Data Register, UARTDR + // 0x00000800 [11] OE (-) Overrun error + // 0x00000400 [10] BE (-) Break error + // 0x00000200 [9] PE (-) Parity error + // 0x00000100 [8] FE (-) Framing error + // 0x000000ff [7:0] DATA (-) Receive (read) data character + io_rw_32 dr; + + _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR + // Receive Status Register/Error Clear Register, UARTRSR/UARTECR + // 0x00000008 [3] OE (0) Overrun error + // 0x00000004 [2] BE (0) Break error + // 0x00000002 [1] PE (0) Parity error + // 0x00000001 [0] FE (0) Framing error + io_rw_32 rsr; + + uint32_t _pad0[4]; + + _REG_(UART_UARTFR_OFFSET) // UART_UARTFR + // Flag Register, UARTFR + // 0x00000100 [8] RI (-) Ring indicator + // 0x00000080 [7] TXFE (1) Transmit FIFO empty + // 0x00000040 [6] RXFF (0) Receive FIFO full + // 0x00000020 [5] TXFF (0) Transmit FIFO full + // 0x00000010 [4] RXFE (1) Receive FIFO empty + // 0x00000008 [3] BUSY (0) UART busy + // 0x00000004 [2] DCD (-) Data carrier detect + // 0x00000002 [1] DSR (-) Data set ready + // 0x00000001 [0] CTS (-) Clear to send + io_ro_32 fr; + + uint32_t _pad1; + + _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR + // IrDA Low-Power Counter Register, UARTILPR + // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value + io_rw_32 ilpr; + + _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD + // Integer Baud Rate Register, UARTIBRD + // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor + io_rw_32 ibrd; + + _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD + // Fractional Baud Rate Register, UARTFBRD + // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor + io_rw_32 fbrd; + + _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H + // Line Control Register, UARTLCR_H + // 0x00000080 [7] SPS (0) Stick parity select + // 0x00000060 [6:5] WLEN (0x0) Word length + // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)... + // 0x00000008 [3] STP2 (0) Two stop bits select + // 0x00000004 [2] EPS (0) Even parity select + // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit... + // 0x00000001 [0] BRK (0) Send break + io_rw_32 lcr_h; + + _REG_(UART_UARTCR_OFFSET) // UART_UARTCR + // Control Register, UARTCR + // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable + // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable + // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)... + // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)... + // 0x00000800 [11] RTS (0) Request to send + // 0x00000400 [10] DTR (0) Data transmit ready + // 0x00000200 [9] RXE (1) Receive enable + // 0x00000100 [8] TXE (1) Transmit enable + // 0x00000080 [7] LBE (0) Loopback enable + // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode + // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled + // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled + io_rw_32 cr; + + _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS + // Interrupt FIFO Level Select Register, UARTIFLS + // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select + // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select + io_rw_32 ifls; + + _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC + // Interrupt Mask Set/Clear Register, UARTIMSC + // 0x00000400 [10] OEIM (0) Overrun error interrupt mask + // 0x00000200 [9] BEIM (0) Break error interrupt mask + // 0x00000100 [8] PEIM (0) Parity error interrupt mask + // 0x00000080 [7] FEIM (0) Framing error interrupt mask + // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask + // 0x00000020 [5] TXIM (0) Transmit interrupt mask + // 0x00000010 [4] RXIM (0) Receive interrupt mask + // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask + // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask + // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask + // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask + io_rw_32 imsc; + + _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS + // Raw Interrupt Status Register, UARTRIS + // 0x00000400 [10] OERIS (0) Overrun error interrupt status + // 0x00000200 [9] BERIS (0) Break error interrupt status + // 0x00000100 [8] PERIS (0) Parity error interrupt status + // 0x00000080 [7] FERIS (0) Framing error interrupt status + // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status + // 0x00000020 [5] TXRIS (0) Transmit interrupt status + // 0x00000010 [4] RXRIS (0) Receive interrupt status + // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status + // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status + // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status + // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status + io_ro_32 ris; + + _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS + // Masked Interrupt Status Register, UARTMIS + // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status + // 0x00000200 [9] BEMIS (0) Break error masked interrupt status + // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status + // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status + // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status + // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status + // 0x00000010 [4] RXMIS (0) Receive masked interrupt status + // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status + // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status + // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status + // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status + io_ro_32 mis; + + _REG_(UART_UARTICR_OFFSET) // UART_UARTICR + // Interrupt Clear Register, UARTICR + // 0x00000400 [10] OEIC (-) Overrun error interrupt clear + // 0x00000200 [9] BEIC (-) Break error interrupt clear + // 0x00000100 [8] PEIC (-) Parity error interrupt clear + // 0x00000080 [7] FEIC (-) Framing error interrupt clear + // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear + // 0x00000020 [5] TXIC (-) Transmit interrupt clear + // 0x00000010 [4] RXIC (-) Receive interrupt clear + // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear + // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear + // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear + // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear + io_rw_32 icr; + + _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR + // DMA Control Register, UARTDMACR + // 0x00000004 [2] DMAONERR (0) DMA on error + // 0x00000002 [1] TXDMAE (0) Transmit DMA enable + // 0x00000001 [0] RXDMAE (0) Receive DMA enable + io_rw_32 dmacr; +} uart_hw_t; + +#define uart0_hw ((uart_hw_t *)UART0_BASE) +#define uart1_hw ((uart_hw_t *)UART1_BASE) +static_assert(sizeof (uart_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_UART_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/usb.h b/src/rp2350/hardware_structs/include/hardware/structs/usb.h new file mode 100644 index 000000000..1c6229bd3 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/usb.h @@ -0,0 +1,602 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_USB_H +#define _HARDWARE_STRUCTS_USB_H + +/** + * \file rp2350/usb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" +#include "hardware/structs/usb_dpram.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP + // Device address and endpoint control + // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to + // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to + io_rw_32 dev_addr_ctrl; + + // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) + _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 + // Interrupt endpoint 1 + // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on... + // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint + // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint + // 0x0000007f [6:0] ADDRESS (0x00) Device address + io_rw_32 int_ep_addr_ctrl[15]; + + _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL + // Main control register + // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation + // 0x00000004 [2] PHY_ISO (1) Isolates USB phy after controller power-up + + // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1 + // 0x00000001 [0] CONTROLLER_EN (0) Enable controller + io_rw_32 main_ctrl; + + _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR + // Set the SOF (Start of Frame) frame number in the host controller + // 0x000007ff [10:0] COUNT (0x000) + io_wo_32 sof_wr; + + _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD + // Read the last SOF (Start of Frame) frame number seen + // 0x000007ff [10:0] COUNT (0x000) + io_ro_32 sof_rd; + + _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL + // SIE control register + // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1 + // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers... + // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable + // 0x02000000 [25] DIRECT_DP (0) Direct control of DP + // 0x01000000 [24] DIRECT_DM (0) Direct control of DM + // 0x00080000 [19] EP0_STOP_ON_SHORT_PACKET (0) Device: Stop EP0 on a short packet + // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver + // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3) + // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor + // 0x00008000 [15] PULLDOWN_EN (1) Host: Enable pull down resistors + // 0x00002000 [13] RESET_BUS (0) Host: Reset bus + // 0x00001000 [12] RESUME (0) Device: Remote wakeup + // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS + // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus) + // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus) + // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF + // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub + // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction + // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host) + // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host) + // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet + // 0x00000001 [0] START_TRANS (0) Host: Start transaction + io_rw_32 sie_ctrl; + + _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS + // SIE status register + // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error + // 0x40000000 [30] ACK_REC (0) ACK received + // 0x20000000 [29] STALL_REC (0) Host: STALL received + // 0x10000000 [28] NAK_REC (0) Host: NAK received + // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an... + // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the... + // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error + // 0x01000000 [24] CRC_ERROR (0) CRC Error + // 0x00800000 [23] ENDPOINT_ERROR (0) An endpoint has encountered an error + // 0x00080000 [19] BUS_RESET (0) Device: bus reset received + // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete + // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received + // 0x00010000 [16] CONNECTED (0) Device: connected + // 0x00001000 [12] RX_SHORT_PACKET (0) Device or Host has received a short packet + // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume + // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected + // 0x00000300 [9:8] SPEED (0x0) Host: device speed + // 0x00000010 [4] SUSPENDED (0) Bus in suspended state + // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state + // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected + io_rw_32 sie_status; + + _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL + // interrupt endpoint control register + // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 -> 15 + io_rw_32 int_ep_ctrl; + + _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS + // Buffer status register + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 buf_status; + + _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE + // Which of the double buffers should be handled + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_ro_32 buf_cpu_should_handle; + + _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT + // Device only: Can be set to ignore the buffer control register for this endpoint in case you... + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort; + + _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE + // Device only: Used in conjunction with `EP_ABORT` + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort_done; + + _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM + // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register... + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_stall_arm; + + _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL + // Used by the host controller + // 0xf0000000 [31:28] RETRY_COUNT_HI (0x0) Bits 9:6 of nak_retry count + // 0x08000000 [27] EPX_STOPPED_ON_NAK (0) EPX polling has stopped because a nak was received + // 0x04000000 [26] STOP_EPX_ON_NAK (0) Stop polling epx when a nak is received + // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device + // 0x0000fc00 [15:10] RETRY_COUNT_LO (0x00) Bits 5:0 of nak_retry_count + // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device + io_rw_32 nak_poll; + + _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK + // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_nak_stall_status; + + _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING + // Where to connect the USB controller + // 0x80000000 [31] SWAP_DPDM (0) Swap the USB PHY DP and DM pins and all related controls... + // 0x00000010 [4] USBPHY_AS_GPIO (0) Use the usb DP and DM pins as GPIO pins instead of... + // 0x00000008 [3] SOFTCON (0) + // 0x00000004 [2] TO_DIGITAL_PAD (0) + // 0x00000002 [1] TO_EXTPHY (0) + // 0x00000001 [0] TO_PHY (1) + io_rw_32 muxing; + + _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR + // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO + // 0x00000020 [5] OVERCURR_DETECT_EN (0) + // 0x00000010 [4] OVERCURR_DETECT (0) + // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0) + // 0x00000004 [2] VBUS_DETECT (0) + // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0) + // 0x00000001 [0] VBUS_EN (0) + io_rw_32 pwr; + + _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT + // This register allows for direct control of the USB phy + // 0x02000000 [25] RX_DM_OVERRIDE (0) Override rx_dm value into controller + // 0x01000000 [24] RX_DP_OVERRIDE (0) Override rx_dp value into controller + // 0x00800000 [23] RX_DD_OVERRIDE (0) Override rx_dd value into controller + // 0x00400000 [22] DM_OVV (0) DM over voltage + // 0x00200000 [21] DP_OVV (0) DP over voltage + // 0x00100000 [20] DM_OVCN (0) DM overcurrent + // 0x00080000 [19] DP_OVCN (0) DP overcurrent + // 0x00040000 [18] RX_DM (0) DPM pin state + // 0x00020000 [17] RX_DP (0) DPP pin state + // 0x00010000 [16] RX_DD (0) Differential RX + // 0x00008000 [15] TX_DIFFMODE (0) TX_DIFFMODE=0: Single ended mode + + // 0x00004000 [14] TX_FSSLEW (0) TX_FSSLEW=0: Low speed slew rate + + // 0x00002000 [13] TX_PD (0) TX power down override (if override enable is set) + // 0x00001000 [12] RX_PD (0) RX power down override (if override enable is set) + // 0x00000800 [11] TX_DM (0) Output data + // 0x00000400 [10] TX_DP (0) Output data + // 0x00000200 [9] TX_DM_OE (0) Output enable + // 0x00000100 [8] TX_DP_OE (0) Output enable + // 0x00000040 [6] DM_PULLDN_EN (0) DM pull down enable + // 0x00000020 [5] DM_PULLUP_EN (0) DM pull up enable + // 0x00000010 [4] DM_PULLUP_HISEL (0) Enable the second DM pull up resistor + // 0x00000004 [2] DP_PULLDN_EN (0) DP pull down enable + // 0x00000002 [1] DP_PULLUP_EN (0) DP pull up enable + // 0x00000001 [0] DP_PULLUP_HISEL (0) Enable the second DP pull up resistor + io_rw_32 phy_direct; + + _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE + // Override enable for each control in usbphy_direct + // 0x00040000 [18] RX_DM_OVERRIDE_EN (0) + // 0x00020000 [17] RX_DP_OVERRIDE_EN (0) + // 0x00010000 [16] RX_DD_OVERRIDE_EN (0) + // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) + // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) + // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) + // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) + // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) + // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) + // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) + // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) + // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) + // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) + // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) + io_rw_32 phy_direct_override; + + _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM + // Used to adjust trim values of USB phy pull down resistors + // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + io_rw_32 phy_trim; + + _REG_(USB_LINESTATE_TUNING_OFFSET) // USB_LINESTATE_TUNING + // Used for debug only + // 0x00000f00 [11:8] SPARE_FIX (0x0) + // 0x00000080 [7] DEV_LS_WAKE_FIX (1) Device - exit suspend on any non-idle signalling, not... + // 0x00000040 [6] DEV_RX_ERR_QUIESCE (1) Device - suppress repeated errors until the device FSM... + // 0x00000020 [5] SIE_RX_CHATTER_SE0_FIX (1) RX - when recovering from line chatter or bitstuff... + // 0x00000010 [4] SIE_RX_BITSTUFF_FIX (1) RX - when a bitstuff error is signalled by rx_dasm,... + // 0x00000008 [3] DEV_BUFF_CONTROL_DOUBLE_READ_FIX (1) Device - the controller FSM performs two reads of the... + // 0x00000004 [2] MULTI_HUB_FIX (0) Host - increase inter-packet and turnaround timeouts to... + // 0x00000002 [1] LINESTATE_DELAY (0) Device/Host - add an extra 1-bit debounce of linestate sampling + // 0x00000001 [0] RCV_DELAY (0) Device - register the received data to account for hub... + io_rw_32 linestate_tuning; + + _REG_(USB_INTR_OFFSET) // USB_INTR + // Raw Interrupts + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 intr; + + _REG_(USB_INTE_OFFSET) // USB_INTE + // Interrupt Enable + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 inte; + + _REG_(USB_INTF_OFFSET) // USB_INTF + // Interrupt Force + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 intf; + + _REG_(USB_INTS_OFFSET) // USB_INTS + // Interrupt status after masking & forcing + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 ints; + + uint32_t _pad0[25]; + + _REG_(USB_SOF_TIMESTAMP_RAW_OFFSET) // USB_SOF_TIMESTAMP_RAW + // Device only + // 0x001fffff [20:0] SOF_TIMESTAMP_RAW (0x000000) + io_ro_32 sof_timestamp_raw; + + _REG_(USB_SOF_TIMESTAMP_LAST_OFFSET) // USB_SOF_TIMESTAMP_LAST + // Device only + // 0x001fffff [20:0] SOF_TIMESTAMP_LAST (0x000000) + io_ro_32 sof_timestamp_last; + + _REG_(USB_SM_STATE_OFFSET) // USB_SM_STATE + // 0x00000f00 [11:8] RX_DASM (0x0) + // 0x000000e0 [7:5] BC_STATE (0x0) + // 0x0000001f [4:0] STATE (0x00) + io_ro_32 sm_state; + + _REG_(USB_EP_TX_ERROR_OFFSET) // USB_EP_TX_ERROR + // TX error count for each endpoint + // 0xc0000000 [31:30] EP15 (0x0) + // 0x30000000 [29:28] EP14 (0x0) + // 0x0c000000 [27:26] EP13 (0x0) + // 0x03000000 [25:24] EP12 (0x0) + // 0x00c00000 [23:22] EP11 (0x0) + // 0x00300000 [21:20] EP10 (0x0) + // 0x000c0000 [19:18] EP9 (0x0) + // 0x00030000 [17:16] EP8 (0x0) + // 0x0000c000 [15:14] EP7 (0x0) + // 0x00003000 [13:12] EP6 (0x0) + // 0x00000c00 [11:10] EP5 (0x0) + // 0x00000300 [9:8] EP4 (0x0) + // 0x000000c0 [7:6] EP3 (0x0) + // 0x00000030 [5:4] EP2 (0x0) + // 0x0000000c [3:2] EP1 (0x0) + // 0x00000003 [1:0] EP0 (0x0) + io_rw_32 ep_tx_error; + + _REG_(USB_EP_RX_ERROR_OFFSET) // USB_EP_RX_ERROR + // RX error count for each endpoint + // 0x80000000 [31] EP15_SEQ (0) + // 0x40000000 [30] EP15_TRANSACTION (0) + // 0x20000000 [29] EP14_SEQ (0) + // 0x10000000 [28] EP14_TRANSACTION (0) + // 0x08000000 [27] EP13_SEQ (0) + // 0x04000000 [26] EP13_TRANSACTION (0) + // 0x02000000 [25] EP12_SEQ (0) + // 0x01000000 [24] EP12_TRANSACTION (0) + // 0x00800000 [23] EP11_SEQ (0) + // 0x00400000 [22] EP11_TRANSACTION (0) + // 0x00200000 [21] EP10_SEQ (0) + // 0x00100000 [20] EP10_TRANSACTION (0) + // 0x00080000 [19] EP9_SEQ (0) + // 0x00040000 [18] EP9_TRANSACTION (0) + // 0x00020000 [17] EP8_SEQ (0) + // 0x00010000 [16] EP8_TRANSACTION (0) + // 0x00008000 [15] EP7_SEQ (0) + // 0x00004000 [14] EP7_TRANSACTION (0) + // 0x00002000 [13] EP6_SEQ (0) + // 0x00001000 [12] EP6_TRANSACTION (0) + // 0x00000800 [11] EP5_SEQ (0) + // 0x00000400 [10] EP5_TRANSACTION (0) + // 0x00000200 [9] EP4_SEQ (0) + // 0x00000100 [8] EP4_TRANSACTION (0) + // 0x00000080 [7] EP3_SEQ (0) + // 0x00000040 [6] EP3_TRANSACTION (0) + // 0x00000020 [5] EP2_SEQ (0) + // 0x00000010 [4] EP2_TRANSACTION (0) + // 0x00000008 [3] EP1_SEQ (0) + // 0x00000004 [2] EP1_TRANSACTION (0) + // 0x00000002 [1] EP0_SEQ (0) + // 0x00000001 [0] EP0_TRANSACTION (0) + io_rw_32 ep_rx_error; + + _REG_(USB_DEV_SM_WATCHDOG_OFFSET) // USB_DEV_SM_WATCHDOG + // Watchdog that forces the device state machine to idle and raises an interrupt if the device... + // 0x00100000 [20] FIRED (0) + // 0x00080000 [19] RESET (0) Set to 1 to forcibly reset the device state machine on... + // 0x00040000 [18] ENABLE (0) + // 0x0003ffff [17:0] LIMIT (0x00000) + io_rw_32 dev_sm_watchdog; +} usb_hw_t; + +#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) +static_assert(sizeof (usb_hw_t) == 0x0118, ""); + +#endif // _HARDWARE_STRUCTS_USB_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/usb_dpram.h b/src/rp2350/hardware_structs/include/hardware/structs/usb_dpram.h new file mode 100644 index 000000000..aaa4ec58b --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/usb_dpram.h @@ -0,0 +1,128 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H +#define _HARDWARE_STRUCTS_USB_DPRAM_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +// 0-15 +#define USB_NUM_ENDPOINTS 16 + +// allow user to restrict number of endpoints available to save RAN +#ifndef USB_MAX_ENDPOINTS +#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS +#endif + +// 1-15 +#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) + +// Endpoint buffer control bits +#define USB_BUF_CTRL_FULL 0x00008000u +#define USB_BUF_CTRL_LAST 0x00004000u +#define USB_BUF_CTRL_DATA0_PID 0x00000000u +#define USB_BUF_CTRL_DATA1_PID 0x00002000u +#define USB_BUF_CTRL_SEL 0x00001000u +#define USB_BUF_CTRL_STALL 0x00000800u +#define USB_BUF_CTRL_AVAIL 0x00000400u +#define USB_BUF_CTRL_LEN_MASK 0x000003FFu +#define USB_BUF_CTRL_LEN_LSB 0 + +// ep_inout_ctrl bits +#define EP_CTRL_ENABLE_BITS (1u << 31u) +#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) +#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) +#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) +#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) +#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) +#define EP_CTRL_BUFFER_TYPE_LSB 26u +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u + +#define USB_DPRAM_SIZE 4096u + +// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb +// Allow user to claim some of the USB RAM for themselves +#ifndef USB_DPRAM_MAX +#define USB_DPRAM_MAX USB_DPRAM_SIZE +#endif + +// Define maximum packet sizes +#define USB_MAX_ISO_PACKET_SIZE 1023 +#define USB_MAX_PACKET_SIZE 64 + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Starts at ep1 + struct usb_device_dpram_ep_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_ctrl[USB_NUM_ENDPOINTS - 1]; + + // Starts at ep0 + struct usb_device_dpram_ep_buf_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_buf_ctrl[USB_NUM_ENDPOINTS]; + + // EP0 buffers are fixed. Assumes single buffered mode for EP0 + uint8_t ep0_buf_a[0x40]; + uint8_t ep0_buf_b[0x40]; + + // Rest of DPRAM can be carved up as needed + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_device_dpram_t; + +static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Interrupt endpoint control 1 -> 15 + struct usb_host_dpram_ep_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_buf_ctrl; + io_rw_32 _spare0; + + // Interrupt endpoint buffer control + struct usb_host_dpram_ep_buf_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_ctrl; + + uint8_t _spare1[124]; + + // Should start at 0x180 + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_host_dpram_t; + +static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); + +#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) +#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) + +static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); + +#endif // _HARDWARE_STRUCTS_USB_DPRAM_H \ No newline at end of file diff --git a/src/rp2350/hardware_structs/include/hardware/structs/watchdog.h b/src/rp2350/hardware_structs/include/hardware/structs/watchdog.h new file mode 100644 index 000000000..19c7bfaee --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/watchdog.h @@ -0,0 +1,59 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_WATCHDOG_H +#define _HARDWARE_STRUCTS_WATCHDOG_H + +/** + * \file rp2350/watchdog.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/watchdog.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_watchdog +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL + // Watchdog control + + // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset + // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused + // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode + // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode + // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric + // 0x00ffffff [23:0] TIME (0x000000) Indicates the time in usec before a watchdog reset will... + io_rw_32 ctrl; + + _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD + // Load the watchdog timer + // 0x00ffffff [23:0] LOAD (0x000000) + io_wo_32 load; + + _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON + // Logs the reason for the last reset + // 0x00000002 [1] FORCE (0) + // 0x00000001 [0] TIMER (0) + io_ro_32 reason; + + // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) + _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 + // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) + io_rw_32 scratch[8]; +} watchdog_hw_t; + +#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) +static_assert(sizeof (watchdog_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_WATCHDOG_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/xip.h b/src/rp2350/hardware_structs/include/hardware/structs/xip.h new file mode 100644 index 000000000..ee5cb2366 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/xip.h @@ -0,0 +1,79 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_H +#define _HARDWARE_STRUCTS_XIP_H + +/** + * \file rp2350/xip.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_CTRL_OFFSET) // XIP_CTRL + // Cache control register + // 0x00000800 [11] WRITABLE_M1 (0) If 1, enable writes to XIP memory window 1 (addresses... + // 0x00000400 [10] WRITABLE_M0 (0) If 1, enable writes to XIP memory window 0 (addresses... + // 0x00000200 [9] SPLIT_WAYS (0) When 1, route all cached+Secure accesses to way 0 of the... + // 0x00000100 [8] MAINT_NONSEC (0) When 0, Non-secure accesses to the cache maintenance... + // 0x00000080 [7] NO_UNTRANSLATED_NONSEC (1) When 1, Non-secure accesses to the uncached,... + // 0x00000040 [6] NO_UNTRANSLATED_SEC (0) When 1, Secure accesses to the uncached, untranslated... + // 0x00000020 [5] NO_UNCACHED_NONSEC (0) When 1, Non-secure accesses to the uncached window... + // 0x00000010 [4] NO_UNCACHED_SEC (0) When 1, Secure accesses to the uncached window... + // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down + // 0x00000002 [1] EN_NONSECURE (1) When 1, enable the cache for Non-secure accesses + // 0x00000001 [0] EN_SECURE (1) When 1, enable the cache for Secure accesses + io_rw_32 ctrl; + + uint32_t _pad0; + + _REG_(XIP_STAT_OFFSET) // XIP_STAT + // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full + // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty + io_ro_32 stat; + + _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT + // Cache Hit counter + // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_hit; + + _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC + // Cache Access counter + // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_acc; + + _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR + // FIFO stream address + // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... + io_rw_32 stream_addr; + + _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR + // FIFO stream control + // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read + io_rw_32 stream_ctr; + + _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO + // FIFO stream data + // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA + io_ro_32 stream_fifo; +} xip_ctrl_hw_t; + +#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) +static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_XIP_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/xip_aux.h b/src/rp2350/hardware_structs/include/hardware/structs/xip_aux.h new file mode 100644 index 000000000..1e1caf8c7 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/xip_aux.h @@ -0,0 +1,51 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_AUX_H +#define _HARDWARE_STRUCTS_XIP_AUX_H + +/** + * \file rp2350/xip_aux.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip_aux.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip_aux +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip_aux.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_AUX_STREAM_OFFSET) // XIP_AUX_STREAM + // Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + // 0xffffffff [31:0] STREAM (0x00000000) + io_ro_32 stream; + + _REG_(XIP_AUX_QMI_DIRECT_TX_OFFSET) // XIP_AUX_QMI_DIRECT_TX + // Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... + // 0x00080000 [19] OE (0) Output enable (active-high) + // 0x00040000 [18] DWIDTH (0) Data width + // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... + // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... + io_wo_32 qmi_direct_tx; + + _REG_(XIP_AUX_QMI_DIRECT_RX_OFFSET) // XIP_AUX_QMI_DIRECT_RX + // Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + // 0x0000ffff [15:0] QMI_DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... + io_ro_32 qmi_direct_rx; +} xip_aux_hw_t; + +#define xip_aux_hw ((xip_aux_hw_t *)XIP_AUX_BASE) +static_assert(sizeof (xip_aux_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_XIP_AUX_H + diff --git a/src/rp2350/hardware_structs/include/hardware/structs/xip_ctrl.h b/src/rp2350/hardware_structs/include/hardware/structs/xip_ctrl.h new file mode 100644 index 000000000..c31569b60 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/xip_ctrl.h @@ -0,0 +1,11 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/xip.h" +#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS +#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS +#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS diff --git a/src/rp2350/hardware_structs/include/hardware/structs/xosc.h b/src/rp2350/hardware_structs/include/hardware/structs/xosc.h new file mode 100644 index 000000000..dca0c05e8 --- /dev/null +++ b/src/rp2350/hardware_structs/include/hardware/structs/xosc.h @@ -0,0 +1,64 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XOSC_H +#define _HARDWARE_STRUCTS_XOSC_H + +/** + * \file rp2350/xosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::xosc_hw[] +typedef struct { + _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL + // Crystal Oscillator Control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the... + // 0x00000fff [11:0] FREQ_RANGE (-) The 12-bit code is intended to give some protection... + io_rw_32 ctrl; + + _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS + // Crystal Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and... + // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting + io_rw_32 status; + + _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT + // Crystal Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC + + io_rw_32 dormant; + + _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP + // Controls the startup delay + // 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4, just in case + // 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period + io_rw_32 startup; + + _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT + // A down counter running at the XOSC frequency which counts to zero and stops. + // 0x0000ffff [15:0] COUNT (0x0000) + io_rw_32 count; +} xosc_hw_t; +/// \end::xosc_hw[] + +#define xosc_hw ((xosc_hw_t *)XOSC_BASE) +static_assert(sizeof (xosc_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_XOSC_H + diff --git a/src/rp2350/pico_platform/BUILD.bazel b/src/rp2350/pico_platform/BUILD.bazel new file mode 100644 index 000000000..8b51a2dd6 --- /dev/null +++ b/src/rp2350/pico_platform/BUILD.bazel @@ -0,0 +1,52 @@ +package( + default_visibility = [ + "//src/rp2350:__subpackages__", + "//src/rp2_common:__pkg__", + ], +) + +cc_library( + name = "pico_platform_internal", + hdrs = [ + "include/pico/asm_helper.S", + "include/pico/platform.h", + "include/pico/platform/cpu_regs.h", + ], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:rp2350"], + + # Be extra careful about who references this for now; if users depend on + # this but not `pico_platform` they'll end up with undefined symbols. + # It's generally safe for anything that circularly depends on + # //src/rp2_common:pico_platform to be added to this allowlist because + # that implicitly means the transitive dependencies of pico_platform will + # get linked in. + visibility = [ + "//src/rp2_common:__pkg__", + ], + deps = [ + "//src/rp2350/hardware_regs", + "//src/rp2350/hardware_regs:platform_defs", + "//src/rp2_common/pico_platform_compiler", + "//src/rp2_common/pico_platform_panic:pico_platform_panic_headers", + "//src/rp2_common/pico_platform_sections", + ], +) + +cc_library( + name = "pico_platform", + srcs = ["platform.c"], + includes = ["include"], + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + ":pico_platform_internal", + "//src/common/pico_base_headers", + "//src/rp2350/hardware_regs", + "//src/rp2350/hardware_regs:platform_defs", + "//src/rp2_common/hardware_base", + "//src/rp2_common/pico_platform_compiler", + "//src/rp2_common/pico_platform_panic", + "//src/rp2_common/pico_platform_sections", + "//src/rp2_common/pico_standard_link", + ], +) diff --git a/src/rp2350/pico_platform/CMakeLists.txt b/src/rp2350/pico_platform/CMakeLists.txt new file mode 100644 index 000000000..7f13f5733 --- /dev/null +++ b/src/rp2350/pico_platform/CMakeLists.txt @@ -0,0 +1,36 @@ +if (NOT TARGET pico_platform) + pico_add_library(pico_platform) + + target_sources(pico_platform INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/platform.c + ) + + target_compile_definitions(pico_platform_headers INTERFACE + PICO_NO_HARDWARE=0 + PICO_ON_DEVICE=1 + PICO_BUILD=1 + PICO_RP2350=1 + PICO_32BIT=1 + ) + + if (PICO_RISCV) + target_compile_definitions(pico_platform_headers INTERFACE PICO_RISCV=1) + endif() + + target_include_directories(pico_platform_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_link_libraries(pico_platform_headers INTERFACE + hardware_regs + ) + pico_mirrored_target_link_libraries(pico_platform INTERFACE + pico_platform_compiler + pico_platform_panic + pico_platform_sections + hardware_dcp + hardware_rcp + ) +endif() + +function(pico_add_platform_library TARGET) + target_link_libraries(pico_platform INTERFACE ${TARGET}) +endfunction() \ No newline at end of file diff --git a/src/rp2350/pico_platform/include/pico/asm_helper.S b/src/rp2350/pico_platform/include/pico/asm_helper.S new file mode 100644 index 000000000..7ff55c44c --- /dev/null +++ b/src/rp2350/pico_platform/include/pico/asm_helper.S @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" + +#if !PICO_ASSEMBLER_IS_CLANG +#define apsr_nzcv r15 +#endif +# note we don't do this by default in this file for backwards comaptibility with user code +# that may include this file, but not use unified syntax. Note that this macro does equivalent +# setup to the pico_default_asm macro for inline assembly in C code. +.macro pico_default_asm_setup +#ifndef __riscv +.syntax unified +.cpu cortex-m33 +.fpu fpv5-sp-d16 +.thumb +#endif +.endm + +// do not put align in here as it is used mid function sometimes +.macro regular_func x +.global \x +.type \x,%function +#ifndef __riscv +.thumb_func +#endif +\x: +.endm + +.macro weak_func x +.weak \x +.type \x,%function +#ifndef __riscv +.thumb_func +#endif +\x: +.endm + +.macro regular_func_with_section x +.section .text.\x +regular_func \x +.endm + +// do not put align in here as it is used mid function sometimes +.macro wrapper_func x +regular_func WRAPPER_FUNC_NAME(\x) +.endm + +.macro weak_wrapper_func x +weak_func WRAPPER_FUNC_NAME(\x) +.endm + +.macro __pre_init_with_offset func, offset, priority_string1 +.section .preinit_array.\priority_string1 +.p2align 2 +.word \func + \offset +.endm + +# backwards compatibility +.macro __pre_init func, priority_string1 +__pre_init_with_offset func, 0, priority_string1 +.endm + +#ifdef __riscv +// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits) +.macro h3.bextm rd rs1 rs2 nbits +.if (\nbits < 1) || (\nbits > 8) +.err +.endif + .insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2 +.endm + +// rd = (rs1 >> shamt) & ~(-1 << nbits) +.macro h3.bextmi rd rs1 shamt nbits +.if (\nbits < 1) || (\nbits > 8) +.err +.endif +.if (\shamt < 0) || (\shamt > 31) +.err +.endif + .insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6) +.endm +#endif \ No newline at end of file diff --git a/src/rp2350/pico_platform/include/pico/platform.h b/src/rp2350/pico_platform/include/pico/platform.h new file mode 100644 index 000000000..9fab28cdf --- /dev/null +++ b/src/rp2350/pico_platform/include/pico/platform.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** \file platform.h + * \defgroup pico_platform pico_platform + * + * \brief Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture + * to provide a common abstraction over low level compiler / platform specifics + * + * This header may be included by assembly code + */ + +#ifndef _PICO_PLATFORM_H +#define _PICO_PLATFORM_H + +#ifndef _PICO_H +#error pico/platform.h should not be included directly; include pico.h instead +#endif + +#include "pico/platform/compiler.h" +#include "pico/platform/sections.h" +#include "pico/platform/panic.h" +#include "hardware/regs/addressmap.h" +#include "hardware/regs/sio.h" +#ifdef __riscv +#include "hardware/regs/rvcsr.h" +#endif + +// PICO_CONFIG: PICO_RP2350A, Whether the current board has an RP2350 in an A (30 GPIO) package, type=bool, default=Usually provided via board header, group=pico_platform + +// PICO_CONFIG: PICO_STACK_SIZE, Minimum amount of stack space reserved in the linker script for each core. See also PICO_CORE1_STACK_SIZE, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_STACK_SIZE +#define PICO_STACK_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_HEAP_SIZE, Minimum amount of heap space reserved by the linker script, min=0x100, default=0x800, advanced=true, group=pico_platform +#ifndef PICO_HEAP_SIZE +#define PICO_HEAP_SIZE _u(0x800) +#endif + +// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform +#ifndef PICO_NO_RAM_VECTOR_TABLE +#define PICO_NO_RAM_VECTOR_TABLE 0 +#endif + +#ifndef PICO_RAM_VECTOR_TABLE_SIZE +#define PICO_RAM_VECTOR_TABLE_SIZE (VTABLE_FIRST_IRQ + NUM_IRQS) +#endif + +// PICO_CONFIG: PICO_USE_STACK_GUARDS, Enable/disable stack guards, type=bool, default=0, advanced=true, group=pico_platform +#ifndef PICO_USE_STACK_GUARDS +#define PICO_USE_STACK_GUARDS 0 +#endif + +#ifndef __ASSEMBLER__ + +/*! \brief No-op function for the body of tight loops + * \ingroup pico_platform + * + * No-op function intended to be called by any tight hardware polling loop. Using this ubiquitously + * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup + * debugging might be added + */ +static __force_inline void tight_loop_contents(void) {} + +/*! \brief Helper method to busy-wait for at least the given number of cycles + * \ingroup pico_platform + * + * This method is useful for introducing very short delays. + * + * This method busy-waits in a tight loop for the given number of system clock cycles. The total wait time is only accurate to within 2 cycles, + * and this method uses a loop counter rather than a hardware timer, so the method will always take longer than expected if an + * interrupt is handled on the calling core during the busy-wait; you can of course disable interrupts to prevent this. + * + * You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert an actual + * time duration to a number of cycles. + * + * \param minimum_cycles the minimum number of system clock cycles to delay for + */ +static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) { + pico_default_asm_volatile ( +#ifdef __riscv + // Note the range is halved on RISC-V due to signed comparison (no carry flag) + ".option push\n" + ".option norvc\n" // force 32 bit addi, so branch prediction guaranteed + ".p2align 2\n" + "1: \n" + "addi %0, %0, -2 \n" + "bgez %0, 1b\n" + ".option pop" +#else + "1: subs %0, #3\n" + "bcs 1b\n" +#endif + : "+r" (minimum_cycles) : : "cc", "memory" + ); +} + +// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=platform dependent, advanced=true, group=pico_runtime +#ifndef PICO_NO_FPGA_CHECK +#if !PICO_RP2040 +#define PICO_NO_FPGA_CHECK 1 +#endif +#endif + +// PICO_CONFIG: PICO_NO_SIM_CHECK, Remove the SIM platform check for small code size reduction, type=bool, default=1, advanced=true, group=pico_runtime +#ifndef PICO_NO_SIM_CHECK +#define PICO_NO_SIM_CHECK 1 +#endif + +#if PICO_NO_FPGA_CHECK +static inline bool running_on_fpga(void) {return false;} +#else +bool running_on_fpga(void); +#endif +#if PICO_NO_SIM_CHECK +static inline bool running_in_sim(void) {return false;} +#else +bool running_in_sim(void); +#endif + +/*! \brief Execute a breakpoint instruction + * \ingroup pico_platform + */ +static __force_inline void __breakpoint(void) { +#ifdef __riscv + __asm ("ebreak"); +#else + pico_default_asm_volatile ("bkpt #0" : : : "memory"); +#endif +} + +/*! \brief Get the current core number + * \ingroup pico_platform + * + * \return The core number the call was made from + */ +__force_inline static uint get_core_num(void) { + return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); +} + +/*! \brief Get the current exception level on this core + * \ingroup pico_platform + * + * On Cortex-M this is the exception number defined in the architecture + * reference, which is equal to VTABLE_FIRST_IRQ + irq num if inside an + * interrupt handler. (VTABLE_FIRST_IRQ is defined in platform_defs.h). + * + * On Hazard3, this function returns VTABLE_FIRST_IRQ + irq num if inside of + * an external IRQ handler (or a fault from such a handler), and 0 otherwise, + * generally aligning with the Cortex-M values. + * + * \return the exception number if the CPU is handling an exception, or 0 otherwise + */ +static __force_inline uint __get_current_exception(void) { +#ifdef __riscv + uint32_t meicontext; + pico_default_asm_volatile ( + "csrr %0, %1\n" + : "=r" (meicontext) : "i" (RVCSR_MEICONTEXT_OFFSET) + ); + if (meicontext & RVCSR_MEICONTEXT_NOIRQ_BITS) { + return 0; + } else { + return VTABLE_FIRST_IRQ + ( + (meicontext & RVCSR_MEICONTEXT_IRQ_BITS) >> RVCSR_MEICONTEXT_IRQ_LSB + ); + } +#else + uint exception; + pico_default_asm_volatile ( + "mrs %0, ipsr\n" + "uxtb %0, %0\n" + : "=l" (exception) + ); + return exception; +#endif +} + +/*! \brief Return true if executing in the NonSecure state (Arm-only) + * \ingroup pico_platform + * + * \return True if currently executing in the NonSecure state on an Arm processor + */ +__force_inline static bool pico_processor_state_is_nonsecure(void) { +#ifndef __riscv + // todo add a define to disable NS checking at all? + // IDAU-Exempt addresses return S=1 when tested in the Secure state, + // whereas executing a tt in the NonSecure state will always return S=0. + uint32_t tt; + pico_default_asm_volatile ( + "movs %0, #0\n" + "tt %0, %0\n" + : "=r" (tt) : : "cc" + ); + return !(tt & (1u << 22)); +#else + // NonSecure is an Arm concept, there is nothing meaningful to return + // here. Note it's not possible in general to detect whether you are + // executing in U-mode as, for example, M-mode is classically + // virtualisable in U-mode. + return false; +#endif +} + +#define host_safe_hw_ptr(x) ((uintptr_t)(x)) +#define native_safe_hw_ptr(x) host_safe_hw_ptr(x) + +/*! \brief Returns the RP2350 chip revision number + * \ingroup pico_platform + * @return the RP2350 chip revision number (1 for B0/B1, 2 for B2) + */ +uint8_t rp2350_chip_version(void); + +/*! \brief Returns the RP2040 chip revision number for compatibility + * \ingroup pico_platform + * @return 2 RP2040 errata fixed in B2 are fixed in RP2350 + */ +static inline uint8_t rp2040_chip_version(void) { + return 2; +} + +/*! \brief Returns the RP2040 rom version number + * \ingroup pico_platform + * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2) + */ +static inline uint8_t rp2040_rom_version(void) { + GCC_Pragma("GCC diagnostic push") + GCC_Pragma("GCC diagnostic ignored \"-Warray-bounds\"") + return *(uint8_t*)0x13; + GCC_Pragma("GCC diagnostic pop") +} + +/*! \brief Multiply two integers using an assembly `MUL` instruction + * \ingroup pico_platform + * + * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler + * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation. + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ +__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) { +#ifdef __riscv + __asm ("mul %0, %0, %1" : "+l" (a) : "l" (b) : ); +#else + pico_default_asm ("muls %0, %1" : "+l" (a) : "l" (b) : "cc"); +#endif + return a; +} + +/*! \brief multiply two integer values using the fastest method possible + * \ingroup pico_platform + * + * Efficiently multiplies value a by possibly constant value b. + * + * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default + * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable + * and will be used + * + * \param a the first operand + * \param b the second operand + * \return a * b + */ +#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ + (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ + (a)*(b)) + +#endif // __ASSEMBLER__ + +#endif + diff --git a/src/rp2350/pico_platform/include/pico/platform/cpu_regs.h b/src/rp2350/pico_platform/include/pico/platform/cpu_regs.h new file mode 100644 index 000000000..b79127c79 --- /dev/null +++ b/src/rp2350/pico_platform/include/pico/platform/cpu_regs.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** \file platform.h + * \defgroup pico_platform pico_platform + * + * \brief Macros and definitions for accessing the CPU registers + * + * This header may be included by assembly code + */ + +#ifndef _PICO_PLATFORM_CPU_REGS_H +#define _PICO_PLATFORM_CPU_REGS_H + +#if defined(__riscv) +#include "hardware/hazard3.h" +#else +#include "hardware/regs/m33.h" +#define ARM_CPU_PREFIXED(x) M33_ ## x +#ifndef __ASSEMBLER__ +#include "hardware/structs/m33.h" +#define arm_cpu_hw m33_hw +#include "hardware/structs/nvic.h" +#include "hardware/structs/scb.h" +#endif +#endif +#endif \ No newline at end of file diff --git a/src/rp2350/pico_platform/platform.c b/src/rp2350/pico_platform/platform.c new file mode 100644 index 000000000..912cc53ff --- /dev/null +++ b/src/rp2350/pico_platform/platform.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" +#include "hardware/address_mapped.h" +#include "hardware/regs/tbman.h" +#include "hardware/regs/sysinfo.h" + +// Note we leave the FPGA check in by default so that we can run bug repro +// binaries coming in from the wild on the FPGA platform. It takes up around +// 48 bytes if you include all the calls, so you can pass PICO_NO_FPGA_CHECK=1 +// to remove it. The FPGA check is used to skip initialisation of hardware +// (mainly clock generators and oscillators) that aren't present on FPGA. + +#if !PICO_NO_FPGA_CHECK +// Inline stub provided in header if this code is unused (so folding can be +// done in each TU instead of relying on LTO) +bool __attribute__((weak)) running_on_fpga(void) { + return (*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS; +} +#endif +#if !PICO_NO_SIM_CHECK +bool __attribute__((weak)) running_in_sim(void) { + return (*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_HDLSIM_BITS; +} +#endif + +#define MANUFACTURER_RPI 0x927 +#define PART_RP4 0x4 + +uint8_t rp2350_chip_version(void) { + // First register of sysinfo is chip id + uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET)); + uint32_t __unused manufacturer = chip_id & SYSINFO_CHIP_ID_MANUFACTURER_BITS; + uint32_t __unused part = (chip_id & SYSINFO_CHIP_ID_PART_BITS) >> SYSINFO_CHIP_ID_PART_LSB; + assert(manufacturer == MANUFACTURER_RPI); + assert(part == PART_RP4); + // 0 == A0, 1 == A1, 2 == A2 + uint version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB; + return (uint8_t)version; +} \ No newline at end of file diff --git a/src/rp2_common.cmake b/src/rp2_common.cmake deleted file mode 100644 index 7ad6e64b4..000000000 --- a/src/rp2_common.cmake +++ /dev/null @@ -1,61 +0,0 @@ -# include targets for all for PICO on device - -enable_language(ASM) - -function(pico_add_hex_output TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Oihex $ $>,$,$>.hex - VERBATIM) -endfunction() - -function(pico_add_bin_output TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_OBJCOPY} -Obinary $ $>,$,$>.bin - VERBATIM) -endfunction() - -function(pico_add_dis_output TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ${CMAKE_OBJDUMP} -h $ > $>,$,$>.dis - COMMAND ${CMAKE_OBJDUMP} -d $ >> $>,$,$>.dis - VERBATIM) -endfunction() - -function(pico_add_extra_outputs TARGET) - pico_add_hex_output(${TARGET}) - pico_add_bin_output(${TARGET}) - pico_add_dis_output(${TARGET}) - - # PICO_CMAKE_CONFIG: PICO_NO_TARGET_NAME, Don't define PICO_TARGET_NAME, type=bool, default=0, group=build - # PICO_BUILD_DEFINE: PICO_TARGET_NAME, The name of the build target being compiled (unless PICO_NO_TARGET_NAME set in build), type=string, default=target name, group=build - if (NOT PICO_NO_TARGET_NAME) - target_compile_definitions(${TARGET} PRIVATE - PICO_TARGET_NAME="${TARGET}" - ) - endif() - - if (PICO_SYMLINK_ELF_AS_FILENAME) - add_custom_target(${TARGET}_symlinked) - add_dependencies(${TARGET}_symlinked ${TARGET}) - - add_custom_command(TARGET ${TARGET}_symlinked POST_BUILD - COMMAND rm -f "${PICO_SYMLINK_ELF_AS_FILENAME}" - COMMAND ln -s -r $ "${PICO_SYMLINK_ELF_AS_FILENAME}" - COMMENT "Symlinking from ${PICO_SYMLINK_ELF_AS_FILENAME} to ${TARGET}" - ) - endif () - # PICO_CMAKE_CONFIG: PICO_NO_UF2, Disable UF2 output, type=bool, default=0, group=build - if (NOT PICO_NO_UF2) - pico_add_uf2_output(${TARGET}) - endif() -endfunction() - -add_subdirectory(common) -add_subdirectory(rp2_common) - -# PICO_CMAKE_CONFIG: PICO_NO_HARDWARE, OPTION: Whether the build is not targeting an RP2040 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build -# PICO_BUILD_DEFINE: PICO_NO_HARDWARE, Whether the build is not targeting an RP2040 device, type=bool, default=1 when PICO_PLATFORM is host, 0 otherwise, group=build -set(PICO_NO_HARDWARE "0" CACHE INTERNAL "") -# PICO_CMAKE_CONFIG: PICO_ON_DEVICE, OPTION: Whether the build is targeting an RP2040 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build -# PICO_BUILD_DEFINE: PICO_ON_DEVICE, Whether the build is targeting an RP2040 device, type=bool, default=0 when PICO_PLATFORM is host, 1 otherwise, group=build -set(PICO_ON_DEVICE "1" CACHE INTERNAL "") - -set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE) diff --git a/src/rp2_common/BUILD.bazel b/src/rp2_common/BUILD.bazel new file mode 100644 index 000000000..6ad8f2241 --- /dev/null +++ b/src/rp2_common/BUILD.bazel @@ -0,0 +1,92 @@ +package(default_visibility = ["//visibility:public"]) + +# This alias is exposed here to simplify configuration. +alias( + name = "build_selected_boot2", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/boot_stage2:build_selected_boot2", + "//bazel/constraint:rp2350": "//src/rp2350/boot_stage2:build_selected_boot2", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "boot_stage2_config", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/boot_stage2:config", + "//bazel/constraint:rp2350": "//src/rp2350/boot_stage2:config", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "boot_stage2", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/boot_stage2:boot_stage2", + "//bazel/constraint:rp2350": "//src/rp2350/boot_stage2:boot_stage2", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "hardware_regs", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/hardware_regs:hardware_regs", + "//bazel/constraint:rp2350": "//src/rp2350/hardware_regs:hardware_regs", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "hardware_structs", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/hardware_structs:hardware_structs", + "//bazel/constraint:rp2350": "//src/rp2350/hardware_structs:hardware_structs", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "platform_defs", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/hardware_regs:platform_defs", + "//bazel/constraint:rp2350": "//src/rp2350/hardware_regs:platform_defs", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +# This shim exists as a way to break internal header dependency cycles +# that occur within the dependency chain of the pico_platform target below. +alias( + name = "pico_platform_internal", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/pico_platform:pico_platform_internal", + "//bazel/constraint:rp2350": "//src/rp2350/pico_platform:pico_platform_internal", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), + visibility = [ + "//src:__pkg__", + "//src/rp2040/boot_stage2:__pkg__", + "//src/rp2350/boot_stage2:__pkg__", + "//src/rp2_common/hardware_base:__pkg__", + "//src/rp2_common/hardware_irq:__pkg__", + "//src/rp2_common/hardware_pll:__pkg__", + "//src/rp2_common/hardware_watchdog:__pkg__", + "//src/rp2_common/hardware_xosc:__pkg__", + "//src/rp2_common/pico_bit_ops:__pkg__", + "//src/rp2_common/pico_bootrom:__pkg__", + "//src/rp2_common/pico_crt0:__pkg__", + "//src/rp2_common/pico_mem_ops:__pkg__", + "//src/rp2_common/pico_printf:__pkg__", + "//src/rp2_common/pico_runtime_init:__pkg__", + ], +) + +alias( + name = "pico_platform", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2040/pico_platform:pico_platform", + "//bazel/constraint:rp2350": "//src/rp2350/pico_platform:pico_platform", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) diff --git a/src/rp2_common/CMakeLists.txt b/src/rp2_common/CMakeLists.txt deleted file mode 100644 index fa121cfb7..000000000 --- a/src/rp2_common/CMakeLists.txt +++ /dev/null @@ -1,89 +0,0 @@ -option(PICO_NO_FLASH "Default binaries to not not use flash") -option(PICO_COPY_TO_RAM "Default binaries to Copy code to RAM when booting from flash") - -set(CMAKE_EXECUTABLE_SUFFIX .elf) - -pico_add_subdirectory(hardware_base) -pico_add_subdirectory(hardware_claim) -# HAL items which expose a public (inline) functions/macro API above the raw hardware -pico_add_subdirectory(hardware_adc) -pico_add_subdirectory(hardware_clocks) -pico_add_subdirectory(hardware_dma) -pico_add_subdirectory(hardware_divider) -pico_add_subdirectory(hardware_exception) -pico_add_subdirectory(hardware_flash) -pico_add_subdirectory(hardware_gpio) -pico_add_subdirectory(hardware_i2c) -pico_add_subdirectory(hardware_interp) -pico_add_subdirectory(hardware_irq) -pico_add_subdirectory(hardware_pio) -pico_add_subdirectory(hardware_pll) -pico_add_subdirectory(hardware_pwm) -pico_add_subdirectory(hardware_resets) -pico_add_subdirectory(hardware_rtc) -pico_add_subdirectory(hardware_spi) -pico_add_subdirectory(hardware_sync) -pico_add_subdirectory(hardware_timer) -pico_add_subdirectory(hardware_uart) -pico_add_subdirectory(hardware_vreg) -pico_add_subdirectory(hardware_watchdog) -pico_add_subdirectory(hardware_xosc) - -# Helper functions to connect to data/functions in the bootrom -pico_add_subdirectory(pico_bootrom) -pico_add_subdirectory(pico_platform) - -if (NOT PICO_BARE_METAL) - # NOTE THE ORDERING HERE IS IMPORTANT AS SOME TARGETS CHECK ON EXISTENCE OF OTHER TARGETS - pico_add_subdirectory(boot_stage2) - - pico_add_subdirectory(pico_bootsel_via_double_reset) - pico_add_subdirectory(pico_multicore) - pico_add_subdirectory(pico_unique_id) - - pico_add_subdirectory(pico_bit_ops) - pico_add_subdirectory(pico_divider) - pico_add_subdirectory(pico_double) - pico_add_subdirectory(pico_int64_ops) - pico_add_subdirectory(pico_flash) - pico_add_subdirectory(pico_float) - pico_add_subdirectory(pico_mem_ops) - pico_add_subdirectory(pico_malloc) - pico_add_subdirectory(pico_printf) - pico_add_subdirectory(pico_rand) - - pico_add_subdirectory(pico_stdio) - pico_add_subdirectory(pico_stdio_semihosting) - pico_add_subdirectory(pico_stdio_uart) - pico_add_subdirectory(pico_stdio_rtt) - - pico_add_subdirectory(cmsis) - pico_add_subdirectory(tinyusb) - pico_add_subdirectory(pico_stdio_usb) - pico_add_subdirectory(pico_i2c_slave) - - # networking libraries - note dependency order is important - pico_add_subdirectory(pico_async_context) - pico_add_subdirectory(pico_btstack) - pico_add_subdirectory(pico_cyw43_driver) - pico_add_subdirectory(pico_lwip) - pico_add_subdirectory(pico_cyw43_arch) - pico_add_subdirectory(pico_mbedtls) - - pico_add_subdirectory(pico_stdlib) - - pico_add_subdirectory(pico_cxx_options) - pico_add_subdirectory(pico_standard_link) - - pico_add_subdirectory(pico_fix) - - pico_add_subdirectory(pico_runtime) - -endif() - -set(CMAKE_EXECUTABLE_SUFFIX "${CMAKE_EXECUTABLE_SUFFIX}" PARENT_SCOPE) - -pico_add_doxygen(${CMAKE_CURRENT_LIST_DIR}) -pico_add_doxygen_exclude(${CMAKE_CURRENT_LIST_DIR}/cmsis) - -pico_promote_common_scope_vars() diff --git a/src/rp2_common/README.md b/src/rp2_common/README.md index b89380100..a598ebc5a 100644 --- a/src/rp2_common/README.md +++ b/src/rp2_common/README.md @@ -1,5 +1,4 @@ -This directory contains libraries specifically targeting the RP2040 or possible future related devices. It is selected when -`PICO_PLATFORM=rp2040` (the default) is specified for the build +This directory contains libraries specifically targeting the RP2040, RP2350 and possible future related devices. `hardware_` libraries exist for individual hardware components to provide a simple API providing a thin abstraction hiding the details of accessing the hardware registers directly. diff --git a/src/rp2_common/cmsis/BUILD.bazel b/src/rp2_common/cmsis/BUILD.bazel index c3787295f..4af320e1e 100644 --- a/src/rp2_common/cmsis/BUILD.bazel +++ b/src/rp2_common/cmsis/BUILD.bazel @@ -2,7 +2,7 @@ load("//bazel:defs.bzl", "compatible_with_rp2") package(default_visibility = ["//visibility:public"]) -# This is added to @pico-sdk//src/common/pico_base:default_platform_headers +# This is added to @pico-sdk//src/common/pico_base_headers:default_platform_headers # by default. cc_library( name = "rename_exceptions", @@ -18,27 +18,61 @@ cc_library( cc_library( name = "cmsis_core", - srcs = [ - "stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c", - ], + srcs = select({ + "//bazel/constraint:rp2040": [ + "stub/CMSIS/Device/RP2040/Source/system_RP2040.c", + ], + "//bazel/constraint:rp2350": [ + "stub/CMSIS/Device/RP2350/Source/system_RP2350.c", + ], + "//conditions:default": [], + }), hdrs = [ "stub/CMSIS/Core/Include/cmsis_armcc.h", "stub/CMSIS/Core/Include/cmsis_armclang.h", "stub/CMSIS/Core/Include/cmsis_armclang_ltm.h", + "stub/CMSIS/Core/Include/cmsis_clang.h", "stub/CMSIS/Core/Include/cmsis_compiler.h", "stub/CMSIS/Core/Include/cmsis_gcc.h", "stub/CMSIS/Core/Include/cmsis_iccarm.h", "stub/CMSIS/Core/Include/cmsis_version.h", "stub/CMSIS/Core/Include/core_cm0plus.h", + "stub/CMSIS/Core/Include/core_cm33.h", + "stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h", + "stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h", + "stub/CMSIS/Core/Include/m-profile/armv81m_pac.h", + "stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h", + "stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h", + "stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h", + "stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h", + "stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h", + "stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h", + "stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h", "stub/CMSIS/Core/Include/mpu_armv7.h", - "stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h", - "stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h", - ], + "stub/CMSIS/Core/Include/mpu_armv8.h", + "stub/CMSIS/Core/Include/tz_context.h", + ] + select({ + "//bazel/constraint:rp2040": [ + "stub/CMSIS/Device/RP2040/Include/RP2040.h", + "stub/CMSIS/Device/RP2040/Include/system_RP2040.h", + ], + "//bazel/constraint:rp2350": [ + "stub/CMSIS/Device/RP2350/Include/RP2350.h", + "stub/CMSIS/Device/RP2350/Include/system_RP2350.h", + ], + "//conditions:default": [], + }), defines = ["LIB_CMSIS_CORE=1"], includes = [ "stub/CMSIS/Core/Include", - "stub/CMSIS/Device/RaspberryPi/RP2040/Include", - ], + ] + select({ + "//bazel/constraint:rp2040": [ + "stub/CMSIS/Device/RP2040/Include", + ], + "//bazel/constraint:rp2350": [ + "stub/CMSIS/Device/RP2350/Include", + ], + }), target_compatible_with = compatible_with_rp2(), deps = [ "//src/rp2_common/hardware_clocks", diff --git a/src/rp2_common/cmsis/CMakeLists.txt b/src/rp2_common/cmsis/CMakeLists.txt index fdc0da071..fa70ce430 100644 --- a/src/rp2_common/cmsis/CMakeLists.txt +++ b/src/rp2_common/cmsis/CMakeLists.txt @@ -46,21 +46,19 @@ # ... using these 3 lines instead set(PICO_CMSIS_CORE_PATH ${CMAKE_CURRENT_LIST_DIR}/stub) -set(PICO_CMSIS_VENDOR RaspberryPi) -set(PICO_CMSIS_DEVICE RP2040) -if (PICO_CMSIS_CORE_PATH) +if (PICO_CMSIS_CORE_PATH AND PICO_CMSIS_DEVICE) pico_add_library(cmsis_core) target_sources(cmsis_core INTERFACE - ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Source/system_${PICO_CMSIS_DEVICE}.c + ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_DEVICE}/Source/system_${PICO_CMSIS_DEVICE}.c ) - target_include_directories(cmsis_core_headers INTERFACE + target_include_directories(cmsis_core_headers SYSTEM INTERFACE ${PICO_CMSIS_CORE_PATH}/CMSIS/Core/Include - ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_VENDOR}/${PICO_CMSIS_DEVICE}/Include + ${PICO_CMSIS_CORE_PATH}/CMSIS/Device/${PICO_CMSIS_DEVICE}/Include ) pico_mirrored_target_link_libraries(cmsis_core INTERFACE hardware_clocks pico_platform) - list(APPEND PICO_RP2040_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/cmsis/rename_exceptions.h) + list(APPEND PICO_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/cmsis/rename_exceptions.h) pico_promote_common_scope_vars() endif() diff --git a/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h b/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h index a523d27f1..e825473da 100644 --- a/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h +++ b/src/rp2_common/cmsis/include/cmsis/rename_exceptions.h @@ -16,6 +16,7 @@ #endif #if PICO_CMSIS_RENAME_EXCEPTIONS +#if PICO_RP2040 #define isr_nmi NMI_Handler #define isr_hardfault HardFault_Handler #define isr_svcall SVC_Handler @@ -48,6 +49,58 @@ #define isr_irq24 I2C1_IRQ_Handler #define isr_irq25 RTC_IRQ_Handler #endif +#if PICO_RP2350 +#define isr_nmi NMI_Handler +#define isr_hardfault HardFault_Handler +#define isr_svcall SVC_Handler +#define isr_pendsv PendSV_Handler +#define isr_systick SysTick_Handler +#define isr_irq0 TIMER0_IRQ_0_IRQn +#define isr_irq1 TIMER0_IRQ_1_IRQn +#define isr_irq2 TIMER0_IRQ_2_IRQn +#define isr_irq3 TIMER0_IRQ_3_IRQn +#define isr_irq4 TIMER1_IRQ_0_IRQn +#define isr_irq5 TIMER1_IRQ_1_IRQn +#define isr_irq6 TIMER1_IRQ_2_IRQn +#define isr_irq7 TIMER1_IRQ_3_IRQn +#define isr_irq8 PWM_IRQ_WRAP_0_IRQn +#define isr_irq9 PWM_IRQ_WRAP_1_IRQn +#define isr_irq10 DMA_IRQ_0_IRQn +#define isr_irq11 DMA_IRQ_1_IRQn +#define isr_irq12 DMA_IRQ_2_IRQn +#define isr_irq13 DMA_IRQ_3_IRQn +#define isr_irq14 USBCTRL_IRQ_IRQn +#define isr_irq15 PIO0_IRQ_0_IRQn +#define isr_irq16 PIO0_IRQ_1_IRQn +#define isr_irq17 PIO1_IRQ_0_IRQn +#define isr_irq18 PIO1_IRQ_1_IRQn +#define isr_irq19 PIO2_IRQ_0_IRQn +#define isr_irq20 PIO2_IRQ_1_IRQn +#define isr_irq21 IO_IRQ_BANK0_IRQn +#define isr_irq22 IO_IRQ_BANK0_NS_IRQn +#define isr_irq23 IO_IRQ_QSPI_IRQn +#define isr_irq24 IO_IRQ_QSPI_NS_IRQn +#define isr_irq25 SIO_IRQ_FIFO_IRQn +#define isr_irq26 SIO_IRQ_BELL_IRQn +#define isr_irq27 SIO_IRQ_FIFO_NS_IRQn +#define isr_irq28 SIO_IRQ_BELL_NS_IRQn +#define isr_irq29 SIO_IRQ_MTIMECMP_IRQn +#define isr_irq30 CLOCKS_IRQ_IRQn +#define isr_irq31 SPI0_IRQ_IRQn +#define isr_irq32 SPI1_IRQ_IRQn +#define isr_irq33 UART0_IRQ_IRQn +#define isr_irq34 UART1_IRQ_IRQn +#define isr_irq35 ADC_IRQ_FIFO_IRQn +#define isr_irq36 I2C0_IRQ_IRQn +#define isr_irq37 I2C1_IRQ_IRQn +#define isr_irq38 OTP_IRQ_IRQn +#define isr_irq39 TRNG_IRQ_IRQn +#define isr_irq42 PLL_SYS_IRQ_IRQn +#define isr_irq43 PLL_USB_IRQ_IRQn +#define isr_irq44 POWMAN_IRQ_POW_IRQn +#define isr_irq45 POWMAN_IRQ_TIMER_IRQn +#endif +#endif #endif #endif /* _CMSIS_RENAME_EXCEPTIONS_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h index 90de9dbf8..446d21a91 100644 --- a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.3.1 - * @date 26. March 2020 + * @version V6.0.0 + * @date 27. July 2024 ******************************************************************************/ /* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,33 +22,36 @@ * limitations under the License. */ -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE - #define __INLINE __inline + #define __INLINE inline #endif #ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline + #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif #ifndef __USED #define __USED __attribute__((used)) #endif @@ -64,18 +67,9 @@ #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) @@ -83,7 +77,6 @@ #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) @@ -91,7 +84,6 @@ #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) @@ -99,7 +91,6 @@ #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) @@ -113,699 +104,13 @@ #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) #endif - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @@ -829,13 +134,14 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ -#define __NOP __builtin_arm_nop +#define __NOP() __nop() + /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -#define __WFI __builtin_arm_wfi +#define __WFI() __wfi() /** @@ -843,14 +149,14 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -#define __WFE __builtin_arm_wfe +#define __WFE() __wfe() /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -#define __SEV __builtin_arm_sev +#define __SEV() __sev() /** @@ -859,14 +165,15 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __builtin_arm_isb(0xF) +#define __ISB() __isb(0xF) + /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __builtin_arm_dsb(0xF) +#define __DSB() __dsb(0xF) /** @@ -874,7 +181,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __builtin_arm_dmb(0xF) +#define __DMB() __dmb(0xF) /** @@ -883,7 +190,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \param [in] value Value to reverse \return Reversed value */ -#define __REV(value) __builtin_bswap32(value) +#define __REV(value) __rev(value) /** @@ -892,7 +199,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \param [in] value Value to reverse \return Reversed value */ -#define __REV16(value) __ROR(__REV(value), 16) +#define __REV16(value) __rev16(value) /** @@ -901,7 +208,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \param [in] value Value to reverse \return Reversed value */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) +#define __REVSH(value) __revsh(value) /** @@ -911,15 +218,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \param [in] op2 Number of Bits to rotate \return Rotated value */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} +#define __ROR(op1, op2) __ror(op1, op2) /** @@ -929,7 +228,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) +#define __BKPT(value) __ASM volatile ("bkpt "#value) /** @@ -938,7 +237,8 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) \param [in] value Value to reverse \return Reversed value */ -#define __RBIT __builtin_arm_rbit +#define __RBIT(value) __rbit(value) + /** \brief Count leading zeros @@ -946,56 +246,99 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) + if ((sat >= 1U) && (sat <= 32U)) { - return 32U; + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } } - return __builtin_clz(value); + return (val); } -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - /** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ +#if (__ARM_FEATURE_LDREX >= 1) /** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex +#define __CLREX __builtin_arm_clrex /** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) + \return value of type uint8_t at (*ptr) */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex +#define __LDREXB (uint8_t)__builtin_arm_ldrex /** @@ -1007,6 +350,17 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex /** @@ -1018,6 +372,17 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex /** @@ -1029,46 +394,10 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - +#if (__ARM_ARCH_ISA_THUMB >= 2) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. @@ -1080,8 +409,8 @@ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); } @@ -1096,7 +425,7 @@ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ + return ((uint8_t)result); /* Add explicit type cast here */ } @@ -1111,7 +440,7 @@ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ + return ((uint16_t)result); /* Add explicit type cast here */ } @@ -1126,109 +455,12 @@ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; + return (result); } +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - +#if (__ARM_ARCH >= 8) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. @@ -1240,7 +472,7 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); + return ((uint8_t)result); /* Add explicit type cast here */ } @@ -1255,7 +487,7 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); + return ((uint16_t)result); /* Add explicit type cast here */ } @@ -1270,7 +502,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); + return (result); } @@ -1316,7 +548,7 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex +#define __LDAEXB (uint8_t)__builtin_arm_ldaex /** @@ -1325,7 +557,7 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex +#define __LDAEXH (uint16_t)__builtin_arm_ldaex /** @@ -1334,7 +566,7 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex +#define __LDAEX (uint32_t)__builtin_arm_ldaex /** @@ -1345,7 +577,7 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) \return 0 Function succeeded \return 1 Function failed */ -#define __STLEXB (uint32_t)__builtin_arm_stlex +#define __STLEXB (uint32_t)__builtin_arm_stlex /** @@ -1356,7 +588,7 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) \return 0 Function succeeded \return 1 Function failed */ -#define __STLEXH (uint32_t)__builtin_arm_stlex +#define __STLEXH (uint32_t)__builtin_arm_stlex /** @@ -1367,101 +599,109 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) \return 0 Function succeeded \return 1 Function failed */ -#define __STLEX (uint32_t)__builtin_arm_stlex +#define __STLEX (uint32_t)__builtin_arm_stlex -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ +#endif /* (__ARM_ARCH >= 8) */ -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ -*/ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -#define __SADD8 __builtin_arm_sadd8 -#define __QADD8 __builtin_arm_qadd8 -#define __SHADD8 __builtin_arm_shadd8 -#define __UADD8 __builtin_arm_uadd8 -#define __UQADD8 __builtin_arm_uqadd8 -#define __UHADD8 __builtin_arm_uhadd8 -#define __SSUB8 __builtin_arm_ssub8 -#define __QSUB8 __builtin_arm_qsub8 -#define __SHSUB8 __builtin_arm_shsub8 -#define __USUB8 __builtin_arm_usub8 -#define __UQSUB8 __builtin_arm_uqsub8 -#define __UHSUB8 __builtin_arm_uhsub8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __UADD16 __builtin_arm_uadd16 -#define __UQADD16 __builtin_arm_uqadd16 -#define __UHADD16 __builtin_arm_uhadd16 -#define __SSUB16 __builtin_arm_ssub16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __USUB16 __builtin_arm_usub16 -#define __UQSUB16 __builtin_arm_uqsub16 -#define __UHSUB16 __builtin_arm_uhsub16 -#define __SASX __builtin_arm_sasx -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __UASX __builtin_arm_uasx -#define __UQASX __builtin_arm_uqasx -#define __UHASX __builtin_arm_uhasx -#define __SSAX __builtin_arm_ssax -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __USAX __builtin_arm_usax -#define __UQSAX __builtin_arm_uqsax -#define __UHSAX __builtin_arm_uhsax -#define __USAD8 __builtin_arm_usad8 -#define __USADA8 __builtin_arm_usada8 -#define __SSAT16 __builtin_arm_ssat16 -#define __USAT16 __builtin_arm_usat16 -#define __UXTB16 __builtin_arm_uxtb16 -#define __UXTAB16 __builtin_arm_uxtab16 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSD __builtin_arm_smlsd -#define __SMLSDX __builtin_arm_smlsdx -#define __SMLSLD __builtin_arm_smlsld -#define __SMLSLDX __builtin_arm_smlsldx -#define __SEL __builtin_arm_sel -#define __QADD __builtin_arm_qadd -#define __QSUB __builtin_arm_qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { - int32_t result; +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif } -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ +/** @} end of CMSIS_Core_RegAccFunctions */ +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_armclang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_armclang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_armclang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif #endif /* __CMSIS_ARMCLANG_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h index 0e5c7349d..1e255d590 100644 --- a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang_ltm.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.3.0 - * @date 26. March 2020 + * @version V1.5.3 + * @date 27. May 2021 ******************************************************************************/ /* - * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -29,10 +29,6 @@ #pragma clang system_header /* treat file as system include file */ -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm @@ -136,1070 +132,1047 @@ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) #endif +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. */ +#define __NOP __builtin_arm_nop /** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -/* intrinsic void __enable_irq(); see arm_compat.h */ +#define __WFI __builtin_arm_wfi /** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. */ -/* intrinsic void __disable_irq(); see arm_compat.h */ +#define __WFE __builtin_arm_wfe /** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} +#define __SEV __builtin_arm_sev -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; +#define __ISB() __builtin_arm_isb(0xF) - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) /** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} +#define __DMB() __builtin_arm_dmb(0xF) -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif +#define __REV(value) __builtin_bswap32(value) /** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} +#define __REV16(value) __ROR(__REV(value), 16) /** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} +#define __REVSH(value) (int16_t)__builtin_bswap16(value) /** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); } /** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; +#define __BKPT(value) __ASM volatile ("bkpt "#value) - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); } -#endif +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} +#define __LDREXB (uint8_t)__builtin_arm_ldrex -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif +#define __LDREXH (uint16_t)__builtin_arm_ldrex /** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} +#define __LDREXW (uint32_t)__builtin_arm_ldrex -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif +#define __STREXB (uint32_t)__builtin_arm_strex /** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} +#define __STREXH (uint32_t)__builtin_arm_strex -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif +#define __STREXW (uint32_t)__builtin_arm_strex -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif +#define __SSAT __builtin_arm_ssat /** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} +#define __USAT __builtin_arm_usat -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } -#endif /** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - + uint32_t result; -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ } -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } -#endif /** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } -#endif /** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; } - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; } -#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + uint32_t result; + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); } -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } -#endif /** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } -#endif /** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} +#define __LDAEXB (uint8_t)__builtin_arm_ldaex -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif +#define __LDAEXH (uint16_t)__builtin_arm_ldaex /** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} +#define __STLEXB (uint32_t)__builtin_arm_stlex -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif +#define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + /** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} #endif + /** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} #endif -/*@} end of CMSIS_Core_RegAccFunctions */ - +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value */ -#define __NOP __builtin_arm_nop +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif /** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set */ -#define __WFE __builtin_arm_wfe +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set */ -#define __SEV __builtin_arm_sev +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif /** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value */ -#define __ISB() __builtin_arm_isb(0xF) +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + /** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value */ -#define __DSB() __builtin_arm_dsb(0xF) +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} /** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value */ -#define __DMB() __builtin_arm_dmb(0xF) +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} /** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value */ -#define __REV(value) __builtin_bswap32(value) +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value */ -#define __REV16(value) __ROR(__REV(value), 16) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif /** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } +#endif /** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value */ -#define __RBIT __builtin_arm_rbit +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + /** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} /** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif /** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value */ -#define __STREXB (uint32_t)__builtin_arm_strex +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value */ -#define __STREXH (uint32_t)__builtin_arm_strex +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif /** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask */ -#define __STREXW (uint32_t)__builtin_arm_strex +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - /** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. */ -#define __SSAT __builtin_arm_ssat +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} /** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. */ -#define __USAT __builtin_arm_usat +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} /** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); } +#endif /** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } +#endif /** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); } +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); } +#endif -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } +#endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ @@ -1208,150 +1181,210 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + /** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif } - +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif } +#endif /** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif } +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif } +#endif /** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif } +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif } +#endif /** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set */ -#define __STLEXB (uint32_t)__builtin_arm_stlex +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif /** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set */ -#define __STLEX (uint32_t)__builtin_arm_stlex +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +/*@} end of CMSIS_Core_RegAccFunctions */ /* ################### Compiler specific Intrinsics ########################### */ @@ -1878,6 +1911,8 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h new file mode 100644 index 000000000..364d18e14 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_clang.h @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file cmsis_clang.h + * @brief CMSIS compiler LLVM/Clang header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_H +#define __CMSIS_CLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) +#include +#else +#error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin +#define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED +#define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT +#define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER +#define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT +#define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS +#define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' +#include "./a-profile/cmsis_clang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' +#include "./r-profile/cmsis_clang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' +#include "./m-profile/cmsis_clang_m.h" +#else +#error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_CLANG_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h index adbf296f1..cf3f5b027 100644 --- a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_compiler.h @@ -1,11 +1,5 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,29 +16,33 @@ * limitations under the License. */ +/* + * CMSIS Compiler Generic Header File + */ + #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* - * Arm Compiler 4/5 + * Arm Compiler above 6.10.1 (armclang) */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" /* - * Arm Compiler 6.6 LTM (armclang) + * TI Arm Clang Compiler (tiarmclang) */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" +#elif defined (__ti__) + #include "cmsis_tiarmclang.h" - /* - * Arm Compiler above 6.10.1 (armclang) + +/* + * LLVM/Clang Compiler */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" +#elif defined ( __clang__ ) + #include "cmsis_clang.h" /* @@ -58,11 +56,19 @@ * IAR Compiler */ #elif defined ( __ICCARM__ ) - #include + #if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_iccarm_a.h" + #elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_iccarm_r.h" + #elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_iccarm_m.h" + #else + #error "Unknown Arm architecture profile" + #endif /* - * TI Arm Compiler + * TI Arm Compiler (armcl) */ #elif defined ( __TI_ARM__ ) #include @@ -97,10 +103,6 @@ #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) @@ -127,7 +129,12 @@ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif - + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif /* * TASKING Compiler @@ -169,10 +176,6 @@ #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) @@ -190,7 +193,7 @@ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) + #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. @@ -200,7 +203,12 @@ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif - + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif /* * COSMIC Compiler @@ -240,10 +248,6 @@ #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) @@ -272,7 +276,12 @@ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif - + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif #else #error Unknown compiler. diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h index a2778f58e..4771466f0 100644 --- a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.3.0 - * @date 26. March 2020 + * @version V6.0.0 + * @date 27. July 2024 ******************************************************************************/ /* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -25,11 +25,9 @@ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC system_header /* treat file as system include file */ + +#include /* Fallback for __has_builtin */ #ifndef __has_builtin @@ -46,12 +44,15 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif #ifndef __USED #define __USED __attribute__((used)) #endif @@ -67,14 +68,6 @@ #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" @@ -116,713 +109,730 @@ #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) #endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) #endif -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) #endif -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ +#define __WFI() __ASM volatile ("wfi":::"memory") + /** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} +#define __WFE() __ASM volatile ("wfe":::"memory") /** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} +#define __SEV() __ASM volatile ("sev") /** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +__STATIC_FORCEINLINE void __ISB(void) { - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); + __ASM volatile ("isb 0xF":::"memory"); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +__STATIC_FORCEINLINE void __DSB(void) { - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); + __ASM volatile ("dsb 0xF":::"memory"); } -#endif /** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +__STATIC_FORCEINLINE void __DMB(void) { - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ASM volatile ("dmb 0xF":::"memory"); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + return __builtin_bswap32(value); } -#endif /** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return (result); } /** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); + return (int16_t)__builtin_bswap16(value); } /** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); } /** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} +#define __BKPT(value) __ASM volatile ("bkpt "#value) -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} +#if (__ARM_ARCH_ISA_THUMB >= 2) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ #endif + return (result); +} /** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +#if (__ARM_FEATURE_SAT >= 1) /** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif +#define __SSAT(value, sat) __ssat(value, sat) /** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - +#define __USAT(value, sat) __usat(value, sat) -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +#else /* (__ARM_FEATURE_SAT >= 1) */ /** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); } -#endif /** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); } +#endif /* (__ARM_FEATURE_SAT >= 1) */ -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +#if (__ARM_FEATURE_LDREX >= 1) /** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +__STATIC_FORCEINLINE void __CLREX(void) { - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + __ASM volatile ("clrex" ::: "memory"); } -#endif -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint8_t) result); /* Add explicit type cast here */ } /** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); } -#endif +#endif /* (__ARM_FEATURE_LDREX >= 1) */ +#if (__ARM_FEATURE_LDREX >= 2) /** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint16_t)result); /* Add explicit type cast here */ } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); } -#endif +#endif /* (__ARM_FEATURE_LDREX >= 2) */ +#if (__ARM_FEATURE_LDREX >= 4) /** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return (result); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return (result); } -#endif +#endif /* (__ARM_FEATURE_LDREX >= 4) */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if (__ARM_ARCH_ISA_THUMB >= 2) /** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { - __ASM volatile ("cpsie f" : : : "memory"); + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); } /** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { - __ASM volatile ("cpsid f" : : : "memory"); + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ } /** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); } -#endif /** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } -#endif /** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ +#if (__ARM_ARCH >= 8) /** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ } -#endif /** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } -#endif -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ } -#endif /** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); } -#endif /** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); } -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); } -#endif /** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); } +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +__STATIC_FORCEINLINE void __disable_irq(void) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif + __ASM volatile ("cpsid i" : : : "memory"); } -#endif -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ +#if (__ARM_ARCH_ISA_THUMB >= 2) + /** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __enable_fault_irq(void) + { + __ASM volatile ("cpsie f" : : : "memory"); + } + + + /** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __disable_fault_irq(void) + { + __ASM volatile ("cpsid f" : : : "memory"); + } +#endif /** @@ -832,21 +842,10 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); #else - return(0U); + return (0U); #endif } @@ -858,1320 +857,150 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif #else (void)fpscr; #endif } -/*@} end of CMSIS_Core_RegAccFunctions */ +/** @} end of CMSIS_Core_RegAccFunctions */ -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions @{ */ -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __sadd8 + #define __QADD8 __qadd8 + #define __SHADD8 __shadd8 + #define __UADD8 __uadd8 + #define __UQADD8 __uqadd8 + #define __UHADD8 __uhadd8 + #define __SSUB8 __ssub8 + #define __QSUB8 __qsub8 + #define __SHSUB8 __shsub8 + #define __USUB8 __usub8 + #define __UQSUB8 __uqsub8 + #define __UHSUB8 __uhsub8 + #define __SADD16 __sadd16 + #define __QADD16 __qadd16 + #define __SHADD16 __shadd16 + #define __UADD16 __uadd16 + #define __UQADD16 __uqadd16 + #define __UHADD16 __uhadd16 + #define __SSUB16 __ssub16 + #define __QSUB16 __qsub16 + #define __SHSUB16 __shsub16 + #define __USUB16 __usub16 + #define __UQSUB16 __uqsub16 + #define __UHSUB16 __uhsub16 + #define __SASX __sasx + #define __QASX __qasx + #define __SHASX __shasx + #define __UASX __uasx + #define __UQASX __uqasx + #define __UHASX __uhasx + #define __SSAX __ssax + #define __QSAX __qsax + #define __SHSAX __shsax + #define __USAX __usax + #define __UQSAX __uqsax + #define __UHSAX __uhsax + #define __USAD8 __usad8 + #define __USADA8 __usada8 + #define __SSAT16 __ssat16 + #define __USAT16 __usat16 + #define __UXTB16 __uxtb16 + #define __UXTAB16 __uxtab16 + #define __SXTB16 __sxtb16 + #define __SXTAB16 __sxtab16 + #define __SMUAD __smuad + #define __SMUADX __smuadx + #define __SMLAD __smlad + #define __SMLADX __smladx + #define __SMLALD __smlald + #define __SMLALDX __smlaldx + #define __SMUSD __smusd + #define __SMUSDX __smusdx + #define __SMLSD __smlsd + #define __SMLSDX __smlsdx + #define __SMLSLD __smlsld + #define __SMLSLDX __smlsldx + #define __SEL __sel + #define __QADD __qadd + #define __QSUB __qsub + + #define __PKHBT(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + #define __PKHTB(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) + { + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); + } +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_gcc_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_gcc_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_gcc_m.h" #else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) + #error "Unknown Arm architecture profile" #endif -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - #endif /* __CMSIS_GCC_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h index 7eeffca5c..65b824b00 100644 --- a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_iccarm.h @@ -1,14 +1,14 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.2.0 - * @date 28. January 2020 + * @version V5.3.0 + * @date 14. April 2021 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017-2019 IAR Systems -// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. // // SPDX-License-Identifier: Apache-2.0 // @@ -238,6 +238,7 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #endif +#undef __WEAK /* undo the definition from DLib_Defaults.h */ #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) @@ -266,6 +267,24 @@ __packed struct __iar_u32 { uint32_t v; }; #define __VECTOR_TABLE_ATTRIBUTE @".intvec" #endif +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif @@ -336,7 +355,13 @@ __packed struct __iar_u32 { uint32_t v; }; #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) @@ -358,7 +383,13 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) @@ -680,6 +711,7 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) @@ -965,4 +997,6 @@ __packed struct __iar_u32 { uint32_t v; }; #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + #endif /* __CMSIS_ICCARM_H__ */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h index 2f048e455..849a8a4a1 100644 --- a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/cmsis_version.h @@ -1,11 +1,5 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.4 - * @date 23. July 2019 - ******************************************************************************/ /* - * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS Core Version Definitions + */ + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) @@ -31,9 +29,16 @@ #ifndef __CMSIS_VERSION_H #define __CMSIS_VERSION_H -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +/* CMSIS-Core(M) Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ + __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ + +/* CMSIS-Core(A) Version definitions */ +#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + #endif diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h index 4e7179a61..1ee945756 100644 --- a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm0plus.h @@ -1,11 +1,5 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.9 - * @date 21. August 2019 - ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,10 +16,16 @@ * limitations under the License. */ +/* + * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + */ + #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC @@ -61,14 +61,10 @@ */ #include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#define __CORTEX_M (0U) /*!< Cortex-M Core */ +/* CMSIS CM0+ definitions */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all @@ -76,12 +72,17 @@ #define __FPU_USED 0U #if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP + #if defined (__TARGET_FPU_VFP) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -91,17 +92,17 @@ #endif #elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ + #if defined (__ARMVFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ + #if defined (__TI_VFP_SUPPORT__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ + #if defined (__FPU_VFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -220,7 +221,7 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; -/* APSR Register Definitions */ +/** \brief APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ @@ -247,7 +248,7 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; -/* IPSR Register Definitions */ +/** \brief IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ @@ -271,7 +272,7 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; -/* xPSR Register Definitions */ +/** \brief xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ @@ -305,7 +306,7 @@ typedef union uint32_t w; /*!< Type used for word access */ } CONTROL_Type; -/* CONTROL Register Definitions */ +/** \brief CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ @@ -336,7 +337,7 @@ typedef struct __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ @@ -365,11 +366,11 @@ typedef struct __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; -/* SCB CPUID Register Definitions */ +/** \brief SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ @@ -385,7 +386,7 @@ typedef struct #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ -/* SCB Interrupt Control State Register Definitions */ +/** \brief SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ @@ -414,20 +415,20 @@ typedef struct #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ +/** \brief SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif -/* SCB Application Interrupt and Reset Control Register Definitions */ +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ @@ -435,7 +436,7 @@ typedef struct #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -/* SCB System Control Register Definitions */ +/** \brief SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ @@ -445,14 +446,14 @@ typedef struct #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ -/* SCB Configuration Control Register Definitions */ +/** \brief SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -/* SCB System Handler Control and State Register Definitions */ +/** \brief SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ @@ -477,7 +478,7 @@ typedef struct __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; -/* SysTick Control / Status Register Definitions */ +/** \brief SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ @@ -490,15 +491,15 @@ typedef struct #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ -/* SysTick Reload Register Definitions */ +/** \brief SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ -/* SysTick Current Register Definitions */ +/** \brief SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ -/* SysTick Calibration Register Definitions */ +/** \brief SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ @@ -525,14 +526,14 @@ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 1U -/* MPU Type Register Definitions */ +/** \brief MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -542,7 +543,7 @@ typedef struct #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ -/* MPU Control Register Definitions */ +/** \brief MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ @@ -552,11 +553,11 @@ typedef struct #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ -/* MPU Region Number Register Definitions */ +/** \brief MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ -/* MPU Region Base Address Register Definitions */ +/** \brief MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ @@ -566,7 +567,7 @@ typedef struct #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ -/* MPU Region Attribute and Size Register Definitions */ +/** \brief MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ @@ -662,6 +663,21 @@ typedef struct /*@} */ +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + /******************************************************************************* * Hardware Abstraction Layer @@ -698,7 +714,7 @@ typedef struct #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ +/* NVIC_GetActive not available for Cortex-M0+ */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset @@ -851,12 +867,12 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } @@ -876,11 +892,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } @@ -950,7 +966,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; #else uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ @@ -971,7 +987,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; #else uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ @@ -1004,7 +1020,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#include "mpu_armv7.h" +#include "m-profile/armv7m_mpu.h" #endif diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm33.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 000000000..464bfdd26 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3245 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M33 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/** \brief NVIC Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/** \brief SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/** \brief SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/** \brief SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/** \brief SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/** \brief SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/** \brief SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/** \brief SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/** \brief SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/** \brief SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/** \brief SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/** \brief SCnSCB Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} ITM_Type; + +/** \brief ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/** \brief ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/** \brief ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/** \brief ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/** \brief ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/** \brief ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED14[984U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/** \brief DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/** \brief DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/** \brief DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/** \brief DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/** \brief DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/** \brief SAU Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/** \brief FPU Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/** \brief FPU Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/** \brief FPU Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/** \brief FPU Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */ + +#define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */ +#define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */ + +/** \brief FPU Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/** \brief FPU Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos +#define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk + +#define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos +#define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk + +#define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos +#define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk + +#define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos +#define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos +#define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk + +#define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos +#define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk + +#define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos +#define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk + +#define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos +#define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos +#define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk + +#define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos +#define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be written. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be written + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h new file mode 100644 index 000000000..d7338a72e --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_cachel1.h @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later + */ + +#ifndef ARM_ARMV7M_CACHEL1_H +#define ARM_ARMV7M_CACHEL1_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_ARMV7M_CACHEL1_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h new file mode 100644 index 000000000..5a4eba231 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv7m_mpu.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv7-M MPU + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv81m_pac.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv81m_pac.h new file mode 100644 index 000000000..648cf8864 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv81m_pac.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension + */ + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h new file mode 100644 index 000000000..d743af12c --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_mpu.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h new file mode 100644 index 000000000..fb1653317 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/armv8m_pmu.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PMU API for Armv8.1-M PMU + */ + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h new file mode 100644 index 000000000..82fb6d46f --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h @@ -0,0 +1,818 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_M_H +#define __CMSIS_ARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_M_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h new file mode 100644 index 000000000..a59444266 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_clang_m.h @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_M_H +#define __CMSIS_CLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __stack +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __stack_limit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __stack_seal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CMSIS_CLANG_M_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h new file mode 100644 index 000000000..54d1f5495 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h @@ -0,0 +1,717 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler GCC Header File + */ + +#ifndef __CMSIS_GCC_M_H +#define __CMSIS_GCC_M_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +#include + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct __copy_table { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct __zero_table { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CMSIS_GCC_M_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h new file mode 100644 index 000000000..cfc6f8083 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h @@ -0,0 +1,1043 @@ +/* + * Copyright (c) 2017-2021 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_M_H__ +#define __CMSIS_ICCARM_M_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #elif __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if defined(__cplusplus) && __cplusplus >= 201103L + #define __NO_RETURN [[noreturn]] + #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define __NO_RETURN _Noreturn + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + #endif + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if (defined (__ARM_FP) && (__ARM_FP >= 1)) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + + /* + * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. + * As a workaround we use inline assembly and a memory barrier. + * (IAR issue EWARM-11901) + */ + #define __CLREX() (__ASM volatile ("CLREX" ::: "memory")) + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!(defined (__ARM_FP) && (__ARM_FP >= 1))) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extension and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_M_H__ */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h new file mode 100644 index 000000000..5b193a17a --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h @@ -0,0 +1,1451 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler TIARMClang Header File + */ + +#ifndef __CMSIS_TIARMCLANG_M_H +#define __CMSIS_TIARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _c_int00 +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __STACK_END +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __STACK_SIZE +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_TIARMCLANG_M_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv8.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 000000000..3de16efc8 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/src/rp2_common/cmsis/stub/CMSIS/Core/Include/tz_context.h b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/tz_context.h new file mode 100644 index 000000000..e095956a8 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core(M) Context Management for Armv8-M TrustZone + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h new file mode 100644 index 000000000..8da431fae --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h @@ -0,0 +1,2673 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + * + * @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h + * @brief CMSIS HeaderFile + * @version 0.1 + * @date Tue Aug 6 18:22:05 2024 + * @note Generated by SVDConv V3.3.47 + * from File 'src/rp2_common/cmsis/../../rp2040/hardware_regs/RP2040.svd', + * last modified on Tue Aug 6 17:58:50 2024 + */ + + +/** @addtogroup Raspberry Pi + * @{ + */ + + +/** @addtogroup RP2040 + * @{ + */ + + +#ifndef RP2040_H +#define RP2040_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== RP2040 Specific Interrupt Numbers =========================================== */ + TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */ + TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */ + TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */ + TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */ + PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */ + USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */ + XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */ + PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */ + PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */ + PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */ + PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */ + DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */ + DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */ + IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */ + IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */ + SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */ + SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */ + CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */ + SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */ + SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */ + UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */ + UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */ + ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */ + I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */ + I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */ + RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_RP2040.h" /*!< RP2040 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ RESETS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief RESETS (RESETS) + */ + +typedef struct { /*!< RESETS Structure */ + __IOM uint32_t RESET; /*!< Reset control. If a bit is set it means the peripheral is in + reset. 0 means the peripheral's reset is deasserted. */ + __IOM uint32_t WDSEL; /*!< Watchdog select. If a bit is set then the watchdog will reset + this peripheral when the watchdog fires. */ + __IOM uint32_t RESET_DONE; /*!< Reset done. If a bit is set then a reset done signal has been + returned by the peripheral. This indicates that the peripheral's + registers are ready to be accessed. */ +} RESETS_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ PSM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PSM (PSM) + */ + +typedef struct { /*!< PSM Structure */ + __IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */ + __IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */ + __IOM uint32_t WDSEL; /*!< Set to 1 if this peripheral should be reset when the watchdog + fires. */ + __IOM uint32_t DONE; /*!< Indicates the peripheral's registers are ready to access. */ +} PSM_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCKS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CLOCKS (CLOCKS) + */ + +typedef struct { /*!< CLOCKS Structure */ + __IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT0_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT1_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT2_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT3_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_REF_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_SYS_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_PERI_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_USB_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_ADC_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_RTC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_RTC_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_RTC_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */ + __IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */ + __IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if + you are not using the pass/fail flags */ + __IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff + if you are not using the pass/fail flags */ + __IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period */ + __IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it + 1us * 2**interval The default gives a test interval of + 250us */ + __IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count */ + __IOM uint32_t FC0_STATUS; /*!< Frequency counter status */ + __IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */ + __IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */ + __IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */ + __IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */ + __IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */ + __IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */ + __IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} CLOCKS_Type; /*!< Size = 200 (0xc8) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_BANK0 (PADS_BANK0) + */ + +typedef struct { /*!< PADS_BANK0 Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO0; /*!< Pad control register */ + __IOM uint32_t GPIO1; /*!< Pad control register */ + __IOM uint32_t GPIO2; /*!< Pad control register */ + __IOM uint32_t GPIO3; /*!< Pad control register */ + __IOM uint32_t GPIO4; /*!< Pad control register */ + __IOM uint32_t GPIO5; /*!< Pad control register */ + __IOM uint32_t GPIO6; /*!< Pad control register */ + __IOM uint32_t GPIO7; /*!< Pad control register */ + __IOM uint32_t GPIO8; /*!< Pad control register */ + __IOM uint32_t GPIO9; /*!< Pad control register */ + __IOM uint32_t GPIO10; /*!< Pad control register */ + __IOM uint32_t GPIO11; /*!< Pad control register */ + __IOM uint32_t GPIO12; /*!< Pad control register */ + __IOM uint32_t GPIO13; /*!< Pad control register */ + __IOM uint32_t GPIO14; /*!< Pad control register */ + __IOM uint32_t GPIO15; /*!< Pad control register */ + __IOM uint32_t GPIO16; /*!< Pad control register */ + __IOM uint32_t GPIO17; /*!< Pad control register */ + __IOM uint32_t GPIO18; /*!< Pad control register */ + __IOM uint32_t GPIO19; /*!< Pad control register */ + __IOM uint32_t GPIO20; /*!< Pad control register */ + __IOM uint32_t GPIO21; /*!< Pad control register */ + __IOM uint32_t GPIO22; /*!< Pad control register */ + __IOM uint32_t GPIO23; /*!< Pad control register */ + __IOM uint32_t GPIO24; /*!< Pad control register */ + __IOM uint32_t GPIO25; /*!< Pad control register */ + __IOM uint32_t GPIO26; /*!< Pad control register */ + __IOM uint32_t GPIO27; /*!< Pad control register */ + __IOM uint32_t GPIO28; /*!< Pad control register */ + __IOM uint32_t GPIO29; /*!< Pad control register */ + __IOM uint32_t SWCLK; /*!< Pad control register */ + __IOM uint32_t SWD; /*!< Pad control register */ +} PADS_BANK0_Type; /*!< Size = 132 (0x84) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_QSPI (PADS_QSPI) + */ + +typedef struct { /*!< PADS_QSPI Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO_QSPI_SCLK; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD0; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD1; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD2; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD3; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SS; /*!< Pad control register */ +} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_QSPI (IO_QSPI) + */ + +typedef struct { /*!< IO_QSPI Structure */ + __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_QSPI_Type; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_BANK0 (IO_BANK0) + */ + +typedef struct { /*!< IO_BANK0 Structure */ + __IOM uint32_t GPIO0_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO0_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO1_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO1_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO2_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO2_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO3_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO3_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO4_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO4_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO5_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO5_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO6_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO6_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO7_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO7_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO8_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO8_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO9_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO9_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO10_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO10_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO11_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO11_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO12_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO12_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO13_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO13_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO14_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO14_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO15_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO15_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO16_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO16_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO17_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO17_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO18_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO18_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO19_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO19_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO20_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO20_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO21_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO21_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO22_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO22_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO23_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO23_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO24_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO24_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO25_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO25_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO26_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO26_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO27_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO27_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO28_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO28_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO29_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO29_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t INTR0; /*!< Raw Interrupts */ + __IOM uint32_t INTR1; /*!< Raw Interrupts */ + __IOM uint32_t INTR2; /*!< Raw Interrupts */ + __IOM uint32_t INTR3; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_BANK0_Type; /*!< Size = 400 (0x190) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSINFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SYSINFO (SYSINFO) + */ + +typedef struct { /*!< SYSINFO Structure */ + __IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */ + __IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment + it is running in. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t GITREF_RP2040; /*!< Git hash of the chip source. Used to identify chip version. */ +} SYSINFO_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ PPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PPB (PPB) + */ + +typedef struct { /*!< PPB Structure */ + __IM uint32_t RESERVED[14340]; + __IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick + features. */ + __IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value + to load into the current value register when the counter + reaches 0. It can be any value between 0 and 0x00FFFFFF. + A start value of 0 is possible, but has no effect because + the SysTick interrupt and COUNTFLAG are activated when + counting from 1 to 0. The reset value of this register + is UNKNOWN. To generate a multi-shot timer with a period + of N processor clock cycles, use a RELOAD value of N-1. + For example, if the SysTick interrupt is required every + 100 clock pulses, set RELOAD to 99. */ + __IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value + in the register. The reset value of this register is UNKNOWN. */ + __IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software + to scale to any required speed using divide and multiply. */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t NVIC_ISER; /*!< Use the Interrupt Set-Enable Register to enable interrupts and + determine which interrupts are currently enabled. If a + pending interrupt is enabled, the NVIC activates the interrupt + based on its priority. If an interrupt is not enabled, + asserting its interrupt signal changes the interrupt state + to pending, but the NVIC never activates the interrupt, + regardless of its priority. */ + __IM uint32_t RESERVED2[31]; + __IOM uint32_t NVIC_ICER; /*!< Use the Interrupt Clear-Enable Registers to disable interrupts + and determine which interrupts are currently enabled. */ + __IM uint32_t RESERVED3[31]; + __IOM uint32_t NVIC_ISPR; /*!< The NVIC_ISPR forces interrupts into the pending state, and + shows which interrupts are pending. */ + __IM uint32_t RESERVED4[31]; + __IOM uint32_t NVIC_ICPR; /*!< Use the Interrupt Clear-Pending Register to clear pending interrupts + and determine which interrupts are currently pending. */ + __IM uint32_t RESERVED5[95]; + __IOM uint32_t NVIC_IPR0; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR + bit does not affect the active state of the corresponding + interrupt. These registers are only word-accessible */ + __IOM uint32_t NVIC_IPR1; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR2; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR3; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR4; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR5; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR6; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR7; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IM uint32_t RESERVED6[568]; + __IOM uint32_t CPUID; /*!< Read the CPU ID Base Register to determine: the ID number of + the processor core, the version number of the processor + core, the implementation details of the processor core. */ + __IOM uint32_t ICSR; /*!< Use the Interrupt Control State Register to set a pending Non-Maskable + Interrupt (NMI), set or clear a pending PendSV, set or + clear a pending SysTick, check for pending exceptions, + check the vector number of the highest priority pended + exception, check the vector number of the active exception. */ + __IOM uint32_t VTOR; /*!< The VTOR holds the vector table offset address. */ + __IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to: + determine data endianness, clear all active state information + from debug halt mode, request a system reset. */ + __IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for + power-management functions: signal to the system when the + processor can enter a low power state, control how the + processor enters and exits low power states. */ + __IOM uint32_t CCR; /*!< The Configuration and Control Register permanently enables stack + alignment and causes unaligned accesses to result in a + Hard Fault. */ + __IM uint32_t RESERVED7; + __IOM uint32_t SHPR2; /*!< System handlers are a special class of exception handler that + can have their priority set to any of the priority levels. + Use the System Handler Priority Register 2 to set the priority + of SVCall. */ + __IOM uint32_t SHPR3; /*!< System handlers are a special class of exception handler that + can have their priority set to any of the priority levels. + Use the System Handler Priority Register 3 to set the priority + of PendSV and SysTick. */ + __IOM uint32_t SHCSR; /*!< Use the System Handler Control and State Register to determine + or clear the pending status of SVCall. */ + __IM uint32_t RESERVED8[26]; + __IOM uint32_t MPU_TYPE; /*!< Read the MPU Type Register to determine if the processor implements + an MPU, and how many regions the MPU supports. */ + __IOM uint32_t MPU_CTRL; /*!< Use the MPU Control Register to enable and disable the MPU, + and to control whether the default memory map is enabled + as a background region for privileged accesses, and whether + the MPU is enabled for HardFaults and NMIs. */ + __IOM uint32_t MPU_RNR; /*!< Use the MPU Region Number Register to select the region currently + accessed by MPU_RBAR and MPU_RASR. */ + __IOM uint32_t MPU_RBAR; /*!< Read the MPU Region Base Address Register to determine the base + address of the region identified by MPU_RNR. Write to update + the base address of said region or that of a specified + region, with whose number MPU_RNR will also be updated. */ + __IOM uint32_t MPU_RASR; /*!< Use the MPU Region Attribute and Size Register to define the + size, access behaviour and memory type of the region identified + by MPU_RNR, and enable that region. */ +} PPB_Type; /*!< Size = 60836 (0xeda4) */ + + + +/* =========================================================================================================================== */ +/* ================ SSI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW_apb_ssi has the following features: + * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. + * APB3 and APB4 protocol support. + * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. + * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. + * Programmable Dual/Quad/Octal SPI support in Master Mode. + * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. + * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. + * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. + * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. + * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. + * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. + * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. + * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. + * Programmable features: + - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. + - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. + - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. + * Configured features: + - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. + - 1 slave select output. + - Hardware slave-select – Dedicated hardware slave-select line. + - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. + - Interrupt polarity – active high interrupt lines. + - Serial clock polarity – low serial-clock polarity directly after reset. + - Serial clock phase – capture on first edge of serial-clock directly after reset. (SSI) + */ + +typedef struct { /*!< SSI Structure */ + __IOM uint32_t CTRLR0; /*!< Control register 0 */ + __IOM uint32_t CTRLR1; /*!< Master Control register 1 */ + __IOM uint32_t SSIENR; /*!< SSI Enable */ + __IOM uint32_t MWCR; /*!< Microwire Control */ + __IOM uint32_t SER; /*!< Slave enable */ + __IOM uint32_t BAUDR; /*!< Baud rate */ + __IOM uint32_t TXFTLR; /*!< TX FIFO threshold level */ + __IOM uint32_t RXFTLR; /*!< RX FIFO threshold level */ + __IOM uint32_t TXFLR; /*!< TX FIFO level */ + __IOM uint32_t RXFLR; /*!< RX FIFO level */ + __IOM uint32_t SR; /*!< Status register */ + __IOM uint32_t IMR; /*!< Interrupt mask */ + __IOM uint32_t ISR; /*!< Interrupt status */ + __IOM uint32_t RISR; /*!< Raw interrupt status */ + __IOM uint32_t TXOICR; /*!< TX FIFO overflow interrupt clear */ + __IOM uint32_t RXOICR; /*!< RX FIFO overflow interrupt clear */ + __IOM uint32_t RXUICR; /*!< RX FIFO underflow interrupt clear */ + __IOM uint32_t MSTICR; /*!< Multi-master interrupt clear */ + __IOM uint32_t ICR; /*!< Interrupt clear */ + __IOM uint32_t DMACR; /*!< DMA control */ + __IOM uint32_t DMATDLR; /*!< DMA TX data level */ + __IOM uint32_t DMARDLR; /*!< DMA RX data level */ + __IOM uint32_t IDR; /*!< Identification register */ + __IOM uint32_t SSI_VERSION_ID; /*!< Version ID */ + __IOM uint32_t DR0; /*!< Data Register 0 (of 36) */ + __IM uint32_t RESERVED[35]; + __IOM uint32_t RX_SAMPLE_DLY; /*!< RX sample delay */ + __IOM uint32_t SPI_CTRLR0; /*!< SPI control */ + __IOM uint32_t TXD_DRIVE_EDGE; /*!< TX drive edge */ +} SSI_Type; /*!< Size = 252 (0xfc) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI flash execute-in-place block (XIP_CTRL) + */ + +typedef struct { /*!< XIP_CTRL Structure */ + __IOM uint32_t CTRL; /*!< Cache control */ + __IOM uint32_t FLUSH; /*!< Cache Flush control */ + __IOM uint32_t STAT; /*!< Cache Status */ + __IOM uint32_t CTR_HIT; /*!< Cache Hit counter */ + __IOM uint32_t CTR_ACC; /*!< Cache Access counter */ + __IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */ + __IOM uint32_t STREAM_CTR; /*!< FIFO stream control */ + __IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */ +} XIP_CTRL_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for various chip control signals (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + __IOM uint32_t PROC0_NMI_MASK; /*!< Processor core 0 NMI source mask */ + __IOM uint32_t PROC1_NMI_MASK; /*!< Processor core 1 NMI source mask */ + __IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */ + __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 0...29. */ + __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 30...35 (the QSPI IOs). */ + __IOM uint32_t DBGFORCE; /*!< Directly control the SWD debug port of either processor */ + __IOM uint32_t MEMPOWERDOWN; /*!< Control power downs to memories. Set high to power down memories. + Use with extreme caution */ +} SYSCFG_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ XOSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls the crystal oscillator (XOSC) + */ + +typedef struct { /*!< XOSC Structure */ + __IOM uint32_t CTRL; /*!< Crystal Oscillator Control */ + __IOM uint32_t STATUS; /*!< Crystal Oscillator Status */ + __IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */ + __IOM uint32_t STARTUP; /*!< Controls the startup delay */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to + zero and stops. To start the counter write a non-zero value. + Can be used for short software pauses when setting up time + sensitive hardware. */ +} XOSC_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ PLL_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PLL_SYS (PLL_SYS) + */ + +typedef struct { /*!< PLL_SYS Structure */ + __IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency + min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO + frequency min=750MHz, max=1600MHz */ + __IOM uint32_t PWR; /*!< Controls the PLL power modes. */ + __IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional + division) */ + __IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note: + this PLL does not have a secondary output) the primary + output is driven from VCO divided by postdiv1*postdiv2 */ +} PLL_SYS_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + __IOM uint32_t UARTDR; /*!< Data Register, UARTDR */ + __IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */ + __IM uint32_t RESERVED1; + __IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */ + __IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */ + __IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */ + __IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */ + __IOM uint32_t UARTCR; /*!< Control Register, UARTCR */ + __IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ + __IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ + __IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */ + __IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */ + __IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */ + __IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */ + __IM uint32_t RESERVED2[997]; + __IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */ + __IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */ + __IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */ + __IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */ + __IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */ + __IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */ + __IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */ + __IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */ +} UART0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ ROSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ROSC (ROSC) + */ + +typedef struct { /*!< ROSC Structure */ + __IOM uint32_t CTRL; /*!< Ring Oscillator control */ + __IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling + the drive strength of each stage The drive strength has + 4 levels determined by the number of bits set Increasing + the number of bits set increases the drive strength and + increases the oscillation frequency 0 bits set is the default + drive strength 1 bit set doubles the drive strength 2 bits + set triples drive strength 3 bits set quadruples drive + strength */ + __IOM uint32_t FREQB; /*!< For a detailed description see freqa register */ + __IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */ + __IOM uint32_t DIV; /*!< Controls the output divider */ + __IOM uint32_t PHASE; /*!< Controls the phase shifted output */ + __IOM uint32_t STATUS; /*!< Ring Oscillator Status */ + __IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness + is compromised if the ring oscillator is stopped or run + at a harmonic of the bus frequency */ + __IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to + zero and stops. To start the counter write a non-zero value. + Can be used for short software pauses when setting up time + sensitive hardware. */ +} ROSC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ WATCHDOG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief WATCHDOG (WATCHDOG) + */ + +typedef struct { /*!< WATCHDOG Structure */ + __IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems + are reset when the watchdog is triggered. The watchdog + can be triggered in software. */ + __IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which + corresponds to 0xffffff / 2 ticks before triggering a watchdog + reset (see errata RP2040-E1). */ + __IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the + case of a hardware reset. */ + __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t TICK; /*!< Controls the tick generator */ +} WATCHDOG_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA with separate read and write masters (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */ + __IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */ + __IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */ + __IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */ + __IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */ + __IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */ + __IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */ + __IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */ + __IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */ + __IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */ + __IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */ + __IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */ + __IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */ + __IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */ + __IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */ + __IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */ + __IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */ + __IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */ + __IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */ + __IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */ + __IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */ + __IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */ + __IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */ + __IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */ + __IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */ + __IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */ + __IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */ + __IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */ + __IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */ + __IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */ + __IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */ + __IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */ + __IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */ + __IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */ + __IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */ + __IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */ + __IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */ + __IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */ + __IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */ + __IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */ + __IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */ + __IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */ + __IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */ + __IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */ + __IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */ + __IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */ + __IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */ + __IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */ + __IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t INTR; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */ + __IOM uint32_t INTF0; /*!< Force Interrupts */ + __IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */ + __IOM uint32_t INTR1; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */ + __IOM uint32_t INTF1; /*!< Force Interrupts for IRQ 1 */ + __IOM uint32_t INTS1; /*!< Interrupt Status (masked) for IRQ 1 */ + __IOM uint32_t TIMER0; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER1; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER2; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER3; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */ + __IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */ + __IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */ + __IM uint32_t RESERVED1; + __IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */ + __IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */ + __IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This + DMA supports up to 16 hardware channels, but can be configured + with as few as one, to minimise silicon area. */ + __IM uint32_t RESERVED2[237]; + __IOM uint32_t CH0_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH0_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED3[14]; + __IOM uint32_t CH1_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH1_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED4[14]; + __IOM uint32_t CH2_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH2_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED5[14]; + __IOM uint32_t CH3_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH3_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED6[14]; + __IOM uint32_t CH4_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH4_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED7[14]; + __IOM uint32_t CH5_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH5_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED8[14]; + __IOM uint32_t CH6_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH6_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED9[14]; + __IOM uint32_t CH7_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH7_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t CH8_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH8_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t CH9_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH9_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED12[14]; + __IOM uint32_t CH10_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH10_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED13[14]; + __IOM uint32_t CH11_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH11_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ +} DMA_Type; /*!< Size = 2760 (0xac8) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls time and alarms + time is a 64 bit value indicating the time in usec since power-on + timeh is the top 32 bits of time & timel is the bottom 32 bits + to change time write to timelw before timehw + to read time read from timelr before timehr + An alarm is set by setting alarm_enable and writing to the corresponding alarm register + When an alarm is pending, the corresponding alarm_running signal will be high + An alarm can be cancelled before it has finished by clearing the alarm_enable + When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared + To clear the interrupt write a 1 to the corresponding alarm_irq (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __IOM uint32_t TIMEHW; /*!< Write to bits 63:32 of time always write timelw before timehw */ + __IOM uint32_t TIMELW; /*!< Write to bits 31:0 of time writes do not get copied to time + until timehw is written */ + __IOM uint32_t TIMEHR; /*!< Read from bits 63:32 of time always read timelr before timehr */ + __IOM uint32_t TIMELR; /*!< Read from bits 31:0 of time */ + __IOM uint32_t ALARM0; /*!< Arm alarm 0, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM0 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM1; /*!< Arm alarm 1, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM1 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM2; /*!< Arm alarm 2, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM2 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM3; /*!< Arm alarm 3, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM3 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ARMED; /*!< Indicates the armed/disarmed status of each alarm. A write to + the corresponding ALARMx register arms the alarm. Alarms + automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. */ + __IOM uint32_t TIMERAWH; /*!< Raw read from bits 63:32 of time (no side effects) */ + __IOM uint32_t TIMERAWL; /*!< Raw read from bits 31:0 of time (no side effects) */ + __IOM uint32_t DBGPAUSE; /*!< Set bits high to enable pause when the corresponding debug ports + are active */ + __IOM uint32_t PAUSE; /*!< Set high to pause the timer */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} TIMER_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Simple PWM (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __IOM uint32_t CH0_CSR; /*!< Control and status register */ + __IOM uint32_t CH0_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH0_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH0_CC; /*!< Counter compare values */ + __IOM uint32_t CH0_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH1_CSR; /*!< Control and status register */ + __IOM uint32_t CH1_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH1_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH1_CC; /*!< Counter compare values */ + __IOM uint32_t CH1_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH2_CSR; /*!< Control and status register */ + __IOM uint32_t CH2_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH2_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH2_CC; /*!< Counter compare values */ + __IOM uint32_t CH2_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH3_CSR; /*!< Control and status register */ + __IOM uint32_t CH3_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH3_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH3_CC; /*!< Counter compare values */ + __IOM uint32_t CH3_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH4_CSR; /*!< Control and status register */ + __IOM uint32_t CH4_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH4_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH4_CC; /*!< Counter compare values */ + __IOM uint32_t CH4_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH5_CSR; /*!< Control and status register */ + __IOM uint32_t CH5_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH5_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH5_CC; /*!< Counter compare values */ + __IOM uint32_t CH5_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH6_CSR; /*!< Control and status register */ + __IOM uint32_t CH6_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH6_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH6_CC; /*!< Counter compare values */ + __IOM uint32_t CH6_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH7_CSR; /*!< Control and status register */ + __IOM uint32_t CH7_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH7_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH7_CC; /*!< Counter compare values */ + __IOM uint32_t CH7_TOP; /*!< Counter wrap value */ + __IOM uint32_t EN; /*!< This register aliases the CSR_EN bits for all channels. Writing + to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect + sync. For each channel, there is only one physical EN register + bit, which can be accessed through here or CHx_CSR. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} PWM_Type; /*!< Size = 180 (0xb4) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control and data interface to SAR ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __IOM uint32_t CS; /*!< ADC Control and Status */ + __IOM uint32_t RESULT; /*!< Result of most recent ADC conversion */ + __IOM uint32_t FCS; /*!< FIFO control and status */ + __IOM uint32_t FIFO; /*!< Conversion result FIFO */ + __IOM uint32_t DIV; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. The divider + is reset when either of these fields are written. Total + period is 1 + INT + FRAC / 256 */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} ADC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + __IOM uint32_t IC_CON; /*!< I2C Control Register. This register can be written only when + the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] + register being set to 0. Writes at other times have no + effect. Read/Write Access: - bit 10 is read only. - bit + 11 is read only - bit 16 is read only - bit 17 is read + only - bits 18 and 19 are read only. */ + __IOM uint32_t IC_TAR; /*!< I2C Target Address Register This register is 12 bits wide, and + bits 31:12 are reserved. This register can be written to + only when IC_ENABLE[0] is set to 0. Note: If the software + or application is aware that the DW_apb_i2c is not using + the TAR address for the pending commands in the Tx FIFO, + then it is possible to update the TAR address even while + the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not + necessary to perform any write to this register if DW_apb_i2c + is enabled as an I2C slave only. */ + __IOM uint32_t IC_SAR; /*!< I2C Slave Address Register */ + __IM uint32_t RESERVED; + __IOM uint32_t IC_DATA_CMD; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register + the CPU writes to when filling the TX FIFO and the CPU + reads from when retrieving bytes from RX FIFO. The size + of the register changes as follows: Write: - 11 bits when + IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 + Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 + bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order + for the DW_apb_i2c to continue acknowledging reads, a read + command should be written for every byte that is to be + received; otherwise the DW_apb_i2c will stop acknowledging. */ + __IOM uint32_t IC_SS_SCL_HCNT; /*!< Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t IC_SS_SCL_LCNT; /*!< Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t IC_FS_SCL_HCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ + __IOM uint32_t IC_FS_SCL_LCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t IC_INTR_STAT; /*!< I2C Interrupt Status Register Each bit in this register has + a corresponding mask bit in the IC_INTR_MASK register. + These bits are cleared by reading the matching interrupt + clear register. The unmasked raw versions of these bits + are available in the IC_RAW_INTR_STAT register. */ + __IOM uint32_t IC_INTR_MASK; /*!< I2C Interrupt Mask Register. These bits mask their corresponding + interrupt status bits. This register is active low; a value + of 0 masks the interrupt, whereas a value of 1 unmasks + the interrupt. */ + __IOM uint32_t IC_RAW_INTR_STAT; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, + these bits are not masked so they always show the true + status of the DW_apb_i2c. */ + __IOM uint32_t IC_RX_TL; /*!< I2C Receive FIFO Threshold Register */ + __IOM uint32_t IC_TX_TL; /*!< I2C Transmit FIFO Threshold Register */ + __IOM uint32_t IC_CLR_INTR; /*!< Clear Combined and Individual Interrupt Register */ + __IOM uint32_t IC_CLR_RX_UNDER; /*!< Clear RX_UNDER Interrupt Register */ + __IOM uint32_t IC_CLR_RX_OVER; /*!< Clear RX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_TX_OVER; /*!< Clear TX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_RD_REQ; /*!< Clear RD_REQ Interrupt Register */ + __IOM uint32_t IC_CLR_TX_ABRT; /*!< Clear TX_ABRT Interrupt Register */ + __IOM uint32_t IC_CLR_RX_DONE; /*!< Clear RX_DONE Interrupt Register */ + __IOM uint32_t IC_CLR_ACTIVITY; /*!< Clear ACTIVITY Interrupt Register */ + __IOM uint32_t IC_CLR_STOP_DET; /*!< Clear STOP_DET Interrupt Register */ + __IOM uint32_t IC_CLR_START_DET; /*!< Clear START_DET Interrupt Register */ + __IOM uint32_t IC_CLR_GEN_CALL; /*!< Clear GEN_CALL Interrupt Register */ + __IOM uint32_t IC_ENABLE; /*!< I2C Enable Register */ + __IOM uint32_t IC_STATUS; /*!< I2C Status Register This is a read-only register used to indicate + the current transfer status and FIFO status. The status + register may be read at any time. None of the bits in this + register request an interrupt. When the I2C is disabled + by writing 0 in bit 0 of the IC_ENABLE register: - Bits + 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When + the master or slave state machines goes to idle and ic_en=0: + - Bits 5 and 6 are set to 0 */ + __IOM uint32_t IC_TXFLR; /*!< I2C Transmit FIFO Level Register This register contains the + number of valid data entries in the transmit FIFO buffer. + It is cleared whenever: - The I2C is disabled - There is + a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT + register - The slave bulk transmit mode is aborted The + register increments whenever data is placed into the transmit + FIFO and decrements when data is taken from the transmit + FIFO. */ + __IOM uint32_t IC_RXFLR; /*!< I2C Receive FIFO Level Register This register contains the number + of valid data entries in the receive FIFO buffer. It is + cleared whenever: - The I2C is disabled - Whenever there + is a transmit abort caused by any of the events tracked + in IC_TX_ABRT_SOURCE The register increments whenever data + is placed into the receive FIFO and decrements when data + is taken from the receive FIFO. */ + __IOM uint32_t IC_SDA_HOLD; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register + are used to control the hold time of SDA during transmit + in both slave and master mode (after SCL goes from HIGH + to LOW). The bits [23:16] of this register are used to + extend the SDA transition (if any) whenever SCL is HIGH + in the receiver in either master or slave mode. Writes + to this register succeed only when IC_ENABLE[0]=0. The + values in this register are in units of ic_clk period. + The value programmed in IC_SDA_TX_HOLD must be greater + than the minimum hold time in each mode (one cycle in master + mode, seven cycles in slave mode) for the value to be implemented. + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) + cannot exceed at any time the duration of the low part + of scl. Therefore the programmed value cannot be larger + than N_SCL_LOW-2, where N_SCL_LOW is the duration of the + low part of the scl period measured in ic_clk cycles. */ + __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< I2C Transmit Abort Source Register This register has 32 bits + that indicate the source of the TX_ABRT bit. Except for + Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT + register or the IC_CLR_INTR register is read. To clear + Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed + first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL + bit must be cleared (IC_TAR[11]), or the GC_OR_START bit + must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT + is fixed, then this bit can be cleared in the same manner + as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT + is not fixed before attempting to clear this bit, Bit 9 + clears for one cycle and is then re-asserted. */ + __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< Generate Slave Data NACK Register The register is used to generate + a NACK for the data part of a transfer when DW_apb_i2c + is acting as a slave-receiver. This register only exists + when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When + this parameter disabled, this register does not exist and + writing to the register's address has no effect. A write + can occur on this register if both of the following conditions + are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - + Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] + is a register read-back location for the internal slv_activity + signal; the user should poll this before writing the ic_slv_data_nack_onl + bit. */ + __IOM uint32_t IC_DMA_CR; /*!< DMA Control Register The register is used to enable the DMA + Controller interface operation. There is a separate bit + for transmit and receive. This can be programmed regardless + of the state of IC_ENABLE. */ + __IOM uint32_t IC_DMA_TDLR; /*!< DMA Transmit Data Level Register */ + __IOM uint32_t IC_DMA_RDLR; /*!< I2C Receive Data Level Register */ + __IOM uint32_t IC_SDA_SETUP; /*!< I2C SDA Setup Register This register controls the amount of + time delay (in terms of number of ic_clk clock periods) + introduced in the rising edge of SCL - relative to SDA + changing - when DW_apb_i2c services a read request in a + slave-transmitter operation. The relevant I2C requirement + is tSU:DAT (note 4) as detailed in the I2C Bus Specification. + This register must be programmed with a value equal to + or greater than 2. Writes to this register succeed only + when IC_ENABLE[0] = 0. Note: The length of setup time is + calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], + so if the user requires 10 ic_clk periods of setup time, + they should program a value of 11. The IC_SDA_SETUP register + is only used by the DW_apb_i2c when operating as a slave + transmitter. */ + __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK General Call Register The register controls whether + DW_apb_i2c responds with a ACK or NACK when it receives + an I2C General Call address. This register is applicable + only when the DW_apb_i2c is in slave mode. */ + __IOM uint32_t IC_ENABLE_STATUS; /*!< I2C Enable Status Register The register is used to report the + DW_apb_i2c hardware status when the IC_ENABLE[0] register + is set from 1 to 0; that is, when DW_apb_i2c is disabled. + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced + to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been + set to 0, bits 2:1 is only be valid as soon as bit 0 is + read as '0'. Note: When IC_ENABLE[0] has been set to 0, + a delay occurs for bit 0 to be read as 0 because disabling + the DW_apb_i2c depends on I2C bus activities. */ + __IOM uint32_t IC_FS_SPKLEN; /*!< I2C SS, FS or FM+ spike suppression limit This register is used + to store the duration, measured in ic_clk cycles, of the + longest spike that is filtered out by the spike suppression + logic when the component is operating in SS, FS or FM+ + modes. The relevant I2C requirement is tSP (table 4) as + detailed in the I2C Bus Specification. This register must + be programmed with a minimum value of 1. */ + __IM uint32_t RESERVED2; + __IOM uint32_t IC_CLR_RESTART_DET; /*!< Clear RESTART_DET Interrupt Register */ + __IM uint32_t RESERVED3[18]; + __IOM uint32_t IC_COMP_PARAM_1; /*!< Component Parameter Register 1 Note This register is not implemented + and therefore reads as 0. If it was implemented it would + be a constant read-only register that contains encoded + information about the component's parameter settings. Fields + shown below are the settings for those parameters */ + __IOM uint32_t IC_COMP_VERSION; /*!< I2C Component Version Register */ + __IOM uint32_t IC_COMP_TYPE; /*!< I2C Component Type Register */ +} I2C0_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + __IOM uint32_t SSPCR0; /*!< Control register 0, SSPCR0 on page 3-4 */ + __IOM uint32_t SSPCR1; /*!< Control register 1, SSPCR1 on page 3-5 */ + __IOM uint32_t SSPDR; /*!< Data register, SSPDR on page 3-6 */ + __IOM uint32_t SSPSR; /*!< Status register, SSPSR on page 3-7 */ + __IOM uint32_t SSPCPSR; /*!< Clock prescale register, SSPCPSR on page 3-8 */ + __IOM uint32_t SSPIMSC; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ + __IOM uint32_t SSPRIS; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ + __IOM uint32_t SSPMIS; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ + __IOM uint32_t SSPICR; /*!< Interrupt clear register, SSPICR on page 3-11 */ + __IOM uint32_t SSPDMACR; /*!< DMA control register, SSPDMACR on page 3-12 */ + __IM uint32_t RESERVED[1006]; + __IOM uint32_t SSPPERIPHID0; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID1; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID2; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID3; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPCELLID0; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID1; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID2; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID3; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ +} SPI0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ PIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable IO block (PIO0) + */ + +typedef struct { /*!< PIO0 Structure */ + __IOM uint32_t CTRL; /*!< PIO control register */ + __IOM uint32_t FSTAT; /*!< FIFO status register */ + __IOM uint32_t FDEBUG; /*!< FIFO debug register */ + __IOM uint32_t FLEVEL; /*!< FIFO levels */ + __IOM uint32_t TXF0; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF1; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF2; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF3; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t RXF0; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF1; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF2; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF3; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t IRQ; /*!< State machine IRQ flags register. Write 1 to clear. There are + 8 state machine IRQ flags, which can be set, cleared, and + waited on by the state machines. There's no fixed association + between flags and state machines -- any state machine can + use any flag. Any of the 8 flags can be used for timing + synchronisation between state machines, using IRQ and WAIT + instructions. The lower four of these flags are also routed + out to system-level interrupt requests, alongside FIFO + status interrupts -- see e.g. IRQ0_INTE. */ + __IOM uint32_t IRQ_FORCE; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding + IRQ. Note this is different to the INTF register: writing + here affects PIO internal state. INTF just asserts the + processor-facing IRQ signal for testing ISRs, and is not + visible to the state machines. */ + __IOM uint32_t INPUT_SYNC_BYPASS; /*!< There is a 2-flipflop synchronizer on each GPIO input, which + protects PIO logic from metastabilities. This increases + input delay, and for fast synchronous IO (e.g. SPI) these + synchronizers may need to be bypassed. Each bit in this + register corresponds to one GPIO. 0 -> input is synchronized + (default) 1 -> synchronizer is bypassed If in doubt, leave + this register as all zeroes. */ + __IOM uint32_t DBG_PADOUT; /*!< Read to sample the pad output values PIO is currently driving + to the GPIOs. On RP2040 there are 30 GPIOs, so the two + most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_PADOE; /*!< Read to sample the pad output enables (direction) PIO is currently + driving to the GPIOs. On RP2040 there are 30 GPIOs, so + the two most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_CFGINFO; /*!< The PIO hardware has some free parameters that may vary between + chip products. These should be provided in the chip datasheet, + but are also exposed here. */ + __IOM uint32_t INSTR_MEM0; /*!< Write-only access to instruction memory location 0 */ + __IOM uint32_t INSTR_MEM1; /*!< Write-only access to instruction memory location 1 */ + __IOM uint32_t INSTR_MEM2; /*!< Write-only access to instruction memory location 2 */ + __IOM uint32_t INSTR_MEM3; /*!< Write-only access to instruction memory location 3 */ + __IOM uint32_t INSTR_MEM4; /*!< Write-only access to instruction memory location 4 */ + __IOM uint32_t INSTR_MEM5; /*!< Write-only access to instruction memory location 5 */ + __IOM uint32_t INSTR_MEM6; /*!< Write-only access to instruction memory location 6 */ + __IOM uint32_t INSTR_MEM7; /*!< Write-only access to instruction memory location 7 */ + __IOM uint32_t INSTR_MEM8; /*!< Write-only access to instruction memory location 8 */ + __IOM uint32_t INSTR_MEM9; /*!< Write-only access to instruction memory location 9 */ + __IOM uint32_t INSTR_MEM10; /*!< Write-only access to instruction memory location 10 */ + __IOM uint32_t INSTR_MEM11; /*!< Write-only access to instruction memory location 11 */ + __IOM uint32_t INSTR_MEM12; /*!< Write-only access to instruction memory location 12 */ + __IOM uint32_t INSTR_MEM13; /*!< Write-only access to instruction memory location 13 */ + __IOM uint32_t INSTR_MEM14; /*!< Write-only access to instruction memory location 14 */ + __IOM uint32_t INSTR_MEM15; /*!< Write-only access to instruction memory location 15 */ + __IOM uint32_t INSTR_MEM16; /*!< Write-only access to instruction memory location 16 */ + __IOM uint32_t INSTR_MEM17; /*!< Write-only access to instruction memory location 17 */ + __IOM uint32_t INSTR_MEM18; /*!< Write-only access to instruction memory location 18 */ + __IOM uint32_t INSTR_MEM19; /*!< Write-only access to instruction memory location 19 */ + __IOM uint32_t INSTR_MEM20; /*!< Write-only access to instruction memory location 20 */ + __IOM uint32_t INSTR_MEM21; /*!< Write-only access to instruction memory location 21 */ + __IOM uint32_t INSTR_MEM22; /*!< Write-only access to instruction memory location 22 */ + __IOM uint32_t INSTR_MEM23; /*!< Write-only access to instruction memory location 23 */ + __IOM uint32_t INSTR_MEM24; /*!< Write-only access to instruction memory location 24 */ + __IOM uint32_t INSTR_MEM25; /*!< Write-only access to instruction memory location 25 */ + __IOM uint32_t INSTR_MEM26; /*!< Write-only access to instruction memory location 26 */ + __IOM uint32_t INSTR_MEM27; /*!< Write-only access to instruction memory location 27 */ + __IOM uint32_t INSTR_MEM28; /*!< Write-only access to instruction memory location 28 */ + __IOM uint32_t INSTR_MEM29; /*!< Write-only access to instruction memory location 29 */ + __IOM uint32_t INSTR_MEM30; /*!< Write-only access to instruction memory location 30 */ + __IOM uint32_t INSTR_MEM31; /*!< Write-only access to instruction memory location 31 */ + __IOM uint32_t SM0_CLKDIV; /*!< Clock divisor register for state machine 0 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM0_EXECCTRL; /*!< Execution/behavioural settings for state machine 0 */ + __IOM uint32_t SM0_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 0 */ + __IOM uint32_t SM0_ADDR; /*!< Current instruction address of state machine 0 */ + __IOM uint32_t SM0_INSTR; /*!< Read to see the instruction currently addressed by state machine + 0's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM0_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM1_CLKDIV; /*!< Clock divisor register for state machine 1 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM1_EXECCTRL; /*!< Execution/behavioural settings for state machine 1 */ + __IOM uint32_t SM1_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 1 */ + __IOM uint32_t SM1_ADDR; /*!< Current instruction address of state machine 1 */ + __IOM uint32_t SM1_INSTR; /*!< Read to see the instruction currently addressed by state machine + 1's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM1_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM2_CLKDIV; /*!< Clock divisor register for state machine 2 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM2_EXECCTRL; /*!< Execution/behavioural settings for state machine 2 */ + __IOM uint32_t SM2_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 2 */ + __IOM uint32_t SM2_ADDR; /*!< Current instruction address of state machine 2 */ + __IOM uint32_t SM2_INSTR; /*!< Read to see the instruction currently addressed by state machine + 2's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM2_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM3_CLKDIV; /*!< Clock divisor register for state machine 3 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM3_EXECCTRL; /*!< Execution/behavioural settings for state machine 3 */ + __IOM uint32_t SM3_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 3 */ + __IOM uint32_t SM3_ADDR; /*!< Current instruction address of state machine 3 */ + __IOM uint32_t SM3_INSTR; /*!< Read to see the instruction currently addressed by state machine + 3's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM3_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ + __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ +} PIO0_Type; /*!< Size = 324 (0x144) */ + + + +/* =========================================================================================================================== */ +/* ================ BUSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for busfabric control signals and performance counters (BUSCTRL) + */ + +typedef struct { /*!< BUSCTRL Structure */ + __IOM uint32_t BUS_PRIORITY; /*!< Set the priority of each master for bus arbitration. */ + __IOM uint32_t BUS_PRIORITY_ACK; /*!< Bus priority acknowledge */ + __IOM uint32_t PERFCTR0; /*!< Bus fabric performance counter 0 */ + __IOM uint32_t PERFSEL0; /*!< Bus fabric performance event select for PERFCTR0 */ + __IOM uint32_t PERFCTR1; /*!< Bus fabric performance counter 1 */ + __IOM uint32_t PERFSEL1; /*!< Bus fabric performance event select for PERFCTR1 */ + __IOM uint32_t PERFCTR2; /*!< Bus fabric performance counter 2 */ + __IOM uint32_t PERFSEL2; /*!< Bus fabric performance event select for PERFCTR2 */ + __IOM uint32_t PERFCTR3; /*!< Bus fabric performance counter 3 */ + __IOM uint32_t PERFSEL3; /*!< Bus fabric performance event select for PERFCTR3 */ +} BUSCTRL_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) + */ + +typedef struct { /*!< SIO Structure */ + __IOM uint32_t CPUID; /*!< Processor core identifier */ + __IOM uint32_t GPIO_IN; /*!< Input value for GPIO pins */ + __IOM uint32_t GPIO_HI_IN; /*!< Input value for QSPI pins */ + __IM uint32_t RESERVED; + __IOM uint32_t GPIO_OUT; /*!< GPIO output value */ + __IOM uint32_t GPIO_OUT_SET; /*!< GPIO output value set */ + __IOM uint32_t GPIO_OUT_CLR; /*!< GPIO output value clear */ + __IOM uint32_t GPIO_OUT_XOR; /*!< GPIO output value XOR */ + __IOM uint32_t GPIO_OE; /*!< GPIO output enable */ + __IOM uint32_t GPIO_OE_SET; /*!< GPIO output enable set */ + __IOM uint32_t GPIO_OE_CLR; /*!< GPIO output enable clear */ + __IOM uint32_t GPIO_OE_XOR; /*!< GPIO output enable XOR */ + __IOM uint32_t GPIO_HI_OUT; /*!< QSPI output value */ + __IOM uint32_t GPIO_HI_OUT_SET; /*!< QSPI output value set */ + __IOM uint32_t GPIO_HI_OUT_CLR; /*!< QSPI output value clear */ + __IOM uint32_t GPIO_HI_OUT_XOR; /*!< QSPI output value XOR */ + __IOM uint32_t GPIO_HI_OE; /*!< QSPI output enable */ + __IOM uint32_t GPIO_HI_OE_SET; /*!< QSPI output enable set */ + __IOM uint32_t GPIO_HI_OE_CLR; /*!< QSPI output enable clear */ + __IOM uint32_t GPIO_HI_OE_XOR; /*!< QSPI output enable XOR */ + __IOM uint32_t FIFO_ST; /*!< Status register for inter-core FIFOs (mailboxes). There is one + FIFO in the core 0 -> core 1 direction, and one core 1 + -> core 0. Both are 32 bits wide and 8 words deep. Core + 0 can see the read side of the 1->0 FIFO (RX), and the + write side of 0->1 FIFO (TX). Core 1 can see the read side + of the 0->1 FIFO (RX), and the write side of 1->0 FIFO + (TX). The SIO IRQ for each core is the logical OR of the + VLD, WOF and ROE fields of its FIFO_ST register. */ + __IOM uint32_t FIFO_WR; /*!< Write access to this core's TX FIFO */ + __IOM uint32_t FIFO_RD; /*!< Read access to this core's RX FIFO */ + __IOM uint32_t SPINLOCK_ST; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks + (1=locked). Mainly intended for debugging. */ + __IOM uint32_t DIV_UDIVIDEND; /*!< Divider unsigned dividend Write to the DIVIDEND operand of the + divider, i.e. the p in `p / q`. Any operand write starts + a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVIDEND/SDIVIDEND are aliases of the same internal register. + The U alias starts an unsigned calculation, and the S alias + starts a signed calculation. */ + __IOM uint32_t DIV_UDIVISOR; /*!< Divider unsigned divisor Write to the DIVISOR operand of the + divider, i.e. the q in `p / q`. Any operand write starts + a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVISOR/SDIVISOR are aliases of the same internal register. + The U alias starts an unsigned calculation, and the S alias + starts a signed calculation. */ + __IOM uint32_t DIV_SDIVIDEND; /*!< Divider signed dividend The same as UDIVIDEND, but starts a + signed calculation, rather than unsigned. */ + __IOM uint32_t DIV_SDIVISOR; /*!< Divider signed divisor The same as UDIVISOR, but starts a signed + calculation, rather than unsigned. */ + __IOM uint32_t DIV_QUOTIENT; /*!< Divider result quotient The result of `DIVIDEND / DIVISOR` (division). + Contents undefined while CSR_READY is low. For signed calculations, + QUOTIENT is negative when the signs of DIVIDEND and DIVISOR + differ. This register can be written to directly, for context + save/restore purposes. This halts any in-progress calculation + and sets the CSR_READY and CSR_DIRTY flags. Reading from + QUOTIENT clears the CSR_DIRTY flag, so should read results + in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. */ + __IOM uint32_t DIV_REMAINDER; /*!< Divider result remainder The result of `DIVIDEND % DIVISOR` + (modulo). Contents undefined while CSR_READY is low. For + signed calculations, REMAINDER is negative only when DIVIDEND + is negative. This register can be written to directly, + for context save/restore purposes. This halts any in-progress + calculation and sets the CSR_READY and CSR_DIRTY flags. */ + __IOM uint32_t DIV_CSR; /*!< Control and status register for divider. */ + __IM uint32_t RESERVED1; + __IOM uint32_t INTERP0_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP0_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP0_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP0_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP0_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP0_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP0_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP0_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP0_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t INTERP1_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP1_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP1_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP1_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP1_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP1_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP1_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP1_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP1_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t SPINLOCK0; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK1; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK2; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK3; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK4; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK5; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK6; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK7; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK8; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK9; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK10; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK11; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK12; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK13; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK14; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK15; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK16; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK17; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK18; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK19; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK20; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK21; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK22; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK23; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK24; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK25; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK26; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK27; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK28; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK29; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK30; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK31; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ +} SIO_Type; /*!< Size = 384 (0x180) */ + + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB FS/LS controller device registers (USB) + */ + +typedef struct { /*!< USB Structure */ + __IOM uint32_t ADDR_ENDP; /*!< Device address and endpoint control */ + __IOM uint32_t ADDR_ENDP1; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP2; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP3; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP4; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP5; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP6; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP7; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP8; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP9; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP10; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP11; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP12; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP13; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP14; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP15; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ + __IOM uint32_t MAIN_CTRL; /*!< Main control register */ + __IOM uint32_t SOF_WR; /*!< Set the SOF (Start of Frame) frame number in the host controller. + The SOF packet is sent every 1ms and the host will increment + the frame number by 1 each time. */ + __IOM uint32_t SOF_RD; /*!< Read the last SOF (Start of Frame) frame number seen. In device + mode the last SOF received from the host. In host mode + the last SOF sent by the host. */ + __IOM uint32_t SIE_CTRL; /*!< SIE control register */ + __IOM uint32_t SIE_STATUS; /*!< SIE status register */ + __IOM uint32_t INT_EP_CTRL; /*!< interrupt endpoint control register */ + __IOM uint32_t BUFF_STATUS; /*!< Buffer status register. A bit set here indicates that a buffer + has completed on the endpoint (if the buffer interrupt + is enabled). It is possible for 2 buffers to be completed, + so clearing the buffer status bit may instantly re set + it on the next clock cycle. */ + __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< Which of the double buffers should be handled. Only valid if + using an interrupt per buffer (i.e. not per 2 buffers). + Not valid for host interrupt endpoint polling because they + are only single buffered. */ + __IOM uint32_t EP_ABORT; /*!< Device only: Can be set to ignore the buffer control register + for this endpoint in case you would like to revoke a buffer. + A NAK will be sent for every access to the endpoint until + this bit is cleared. A corresponding bit in `EP_ABORT_DONE` + is set when it is safe to modify the buffer control register. */ + __IOM uint32_t EP_ABORT_DONE; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an + endpoint is idle so the programmer knows it is safe to + modify the buffer control register. */ + __IOM uint32_t EP_STALL_ARM; /*!< Device: this bit must be set in conjunction with the `STALL` + bit in the buffer control register to send a STALL on EP0. + The device controller clears these bits when a SETUP packet + is received because the USB spec requires that a STALL + condition is cleared when a SETUP packet is received. */ + __IOM uint32_t NAK_POLL; /*!< Used by the host controller. Sets the wait time in microseconds + before trying again if the device replies with a NAK. */ + __IOM uint32_t EP_STATUS_STALL_NAK; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` + bits are set. For EP0 this comes from `SIE_CTRL`. For all + other endpoints it comes from the endpoint control register. */ + __IOM uint32_t USB_MUXING; /*!< Where to connect the USB controller. Should be to_phy by default. */ + __IOM uint32_t USB_PWR; /*!< Overrides for the power signals in the event that the VBUS signals + are not hooked up to GPIO. Set the value of the override + and then the override enable so switch over to the override + value. */ + __IOM uint32_t USBPHY_DIRECT; /*!< Note that most functions are driven directly from usb_fsls controller. + This register allows more detailed control/status from + the USB PHY. Useful for debug but not expected to be used + in normal operation Use in conjunction with usbphy_direct_override + register */ + __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< USBPHY_DIRECT_OVERRIDE */ + __IOM uint32_t USBPHY_TRIM; /*!< Note that most functions are driven directly from usb_fsls controller. + This register allows more detailed control/status from + the USB PHY. Useful for debug but not expected to be used + in normal operation */ + __IM uint32_t RESERVED; + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} USB_Type; /*!< Size = 156 (0x9c) */ + + + +/* =========================================================================================================================== */ +/* ================ USB_DPRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DPRAM layout for USB device. (USB_DPRAM) + */ + +typedef struct { /*!< USB_DPRAM Structure */ + __IOM uint32_t SETUP_PACKET_LOW; /*!< Bytes 0-3 of the SETUP packet from the host. */ + __IOM uint32_t SETUP_PACKET_HIGH; /*!< Bytes 4-7 of the setup packet from the host. */ + __IOM uint32_t EP1_IN_CONTROL; /*!< EP1_IN_CONTROL */ + __IOM uint32_t EP1_OUT_CONTROL; /*!< EP1_OUT_CONTROL */ + __IOM uint32_t EP2_IN_CONTROL; /*!< EP2_IN_CONTROL */ + __IOM uint32_t EP2_OUT_CONTROL; /*!< EP2_OUT_CONTROL */ + __IOM uint32_t EP3_IN_CONTROL; /*!< EP3_IN_CONTROL */ + __IOM uint32_t EP3_OUT_CONTROL; /*!< EP3_OUT_CONTROL */ + __IOM uint32_t EP4_IN_CONTROL; /*!< EP4_IN_CONTROL */ + __IOM uint32_t EP4_OUT_CONTROL; /*!< EP4_OUT_CONTROL */ + __IOM uint32_t EP5_IN_CONTROL; /*!< EP5_IN_CONTROL */ + __IOM uint32_t EP5_OUT_CONTROL; /*!< EP5_OUT_CONTROL */ + __IOM uint32_t EP6_IN_CONTROL; /*!< EP6_IN_CONTROL */ + __IOM uint32_t EP6_OUT_CONTROL; /*!< EP6_OUT_CONTROL */ + __IOM uint32_t EP7_IN_CONTROL; /*!< EP7_IN_CONTROL */ + __IOM uint32_t EP7_OUT_CONTROL; /*!< EP7_OUT_CONTROL */ + __IOM uint32_t EP8_IN_CONTROL; /*!< EP8_IN_CONTROL */ + __IOM uint32_t EP8_OUT_CONTROL; /*!< EP8_OUT_CONTROL */ + __IOM uint32_t EP9_IN_CONTROL; /*!< EP9_IN_CONTROL */ + __IOM uint32_t EP9_OUT_CONTROL; /*!< EP9_OUT_CONTROL */ + __IOM uint32_t EP10_IN_CONTROL; /*!< EP10_IN_CONTROL */ + __IOM uint32_t EP10_OUT_CONTROL; /*!< EP10_OUT_CONTROL */ + __IOM uint32_t EP11_IN_CONTROL; /*!< EP11_IN_CONTROL */ + __IOM uint32_t EP11_OUT_CONTROL; /*!< EP11_OUT_CONTROL */ + __IOM uint32_t EP12_IN_CONTROL; /*!< EP12_IN_CONTROL */ + __IOM uint32_t EP12_OUT_CONTROL; /*!< EP12_OUT_CONTROL */ + __IOM uint32_t EP13_IN_CONTROL; /*!< EP13_IN_CONTROL */ + __IOM uint32_t EP13_OUT_CONTROL; /*!< EP13_OUT_CONTROL */ + __IOM uint32_t EP14_IN_CONTROL; /*!< EP14_IN_CONTROL */ + __IOM uint32_t EP14_OUT_CONTROL; /*!< EP14_OUT_CONTROL */ + __IOM uint32_t EP15_IN_CONTROL; /*!< EP15_IN_CONTROL */ + __IOM uint32_t EP15_OUT_CONTROL; /*!< EP15_OUT_CONTROL */ + __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ +} USB_DPRAM_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ TBMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Testbench manager. Allows the programmer to know what platform their software is running on. (TBMAN) + */ + +typedef struct { /*!< TBMAN Structure */ + __IOM uint32_t PLATFORM; /*!< Indicates the type of platform in use */ +} TBMAN_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ VREG_AND_CHIP_RESET ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief control and status for on-chip voltage regulator and chip level reset subsystem (VREG_AND_CHIP_RESET) + */ + +typedef struct { /*!< VREG_AND_CHIP_RESET Structure */ + __IOM uint32_t VREG; /*!< Voltage regulator control and status */ + __IOM uint32_t BOD; /*!< brown-out detection control */ + __IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */ +} VREG_AND_CHIP_RESET_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block to control RTC (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __IOM uint32_t CLKDIV_M1; /*!< Divider minus 1 for the 1 second counter. Safe to change the + value when RTC is not enabled. */ + __IOM uint32_t SETUP_0; /*!< RTC setup register 0 */ + __IOM uint32_t SETUP_1; /*!< RTC setup register 1 */ + __IOM uint32_t CTRL; /*!< RTC Control and status */ + __IOM uint32_t IRQ_SETUP_0; /*!< Interrupt setup register 0 */ + __IOM uint32_t IRQ_SETUP_1; /*!< Interrupt setup register 1 */ + __IOM uint32_t RTC_1; /*!< RTC register 1. */ + __IOM uint32_t RTC_0; /*!< RTC register 0 Read this before RTC 1! */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} RTC_Type; /*!< Size = 48 (0x30) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define RESETS_BASE 0x4000C000UL +#define PSM_BASE 0x40010000UL +#define CLOCKS_BASE 0x40008000UL +#define PADS_BANK0_BASE 0x4001C000UL +#define PADS_QSPI_BASE 0x40020000UL +#define IO_QSPI_BASE 0x40018000UL +#define IO_BANK0_BASE 0x40014000UL +#define SYSINFO_BASE 0x40000000UL +#define PPB_BASE 0xE0000000UL +#define SSI_BASE 0x18000000UL +#define XIP_CTRL_BASE 0x14000000UL +#define SYSCFG_BASE 0x40004000UL +#define XOSC_BASE 0x40024000UL +#define PLL_SYS_BASE 0x40028000UL +#define PLL_USB_BASE 0x4002C000UL +#define UART0_BASE 0x40034000UL +#define UART1_BASE 0x40038000UL +#define ROSC_BASE 0x40060000UL +#define WATCHDOG_BASE 0x40058000UL +#define DMA_BASE 0x50000000UL +#define TIMER_BASE 0x40054000UL +#define PWM_BASE 0x40050000UL +#define ADC_BASE 0x4004C000UL +#define I2C0_BASE 0x40044000UL +#define I2C1_BASE 0x40048000UL +#define SPI0_BASE 0x4003C000UL +#define SPI1_BASE 0x40040000UL +#define PIO0_BASE 0x50200000UL +#define PIO1_BASE 0x50300000UL +#define BUSCTRL_BASE 0x40030000UL +#define SIO_BASE 0xD0000000UL +#define USB_BASE 0x50110000UL +#define USB_DPRAM_BASE 0x50100000UL +#define TBMAN_BASE 0x4006C000UL +#define VREG_AND_CHIP_RESET_BASE 0x40064000UL +#define RTC_BASE 0x4005C000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define RESETS ((RESETS_Type*) RESETS_BASE) +#define PSM ((PSM_Type*) PSM_BASE) +#define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) +#define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) +#define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) +#define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) +#define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) +#define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) +#define PPB ((PPB_Type*) PPB_BASE) +#define SSI ((SSI_Type*) SSI_BASE) +#define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) +#define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) +#define XOSC ((XOSC_Type*) XOSC_BASE) +#define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) +#define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define ROSC ((ROSC_Type*) ROSC_BASE) +#define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) +#define DMA ((DMA_Type*) DMA_BASE) +#define TIMER ((TIMER_Type*) TIMER_BASE) +#define PWM ((PWM_Type*) PWM_BASE) +#define ADC ((ADC_Type*) ADC_BASE) +#define I2C0 ((I2C0_Type*) I2C0_BASE) +#define I2C1 ((I2C0_Type*) I2C1_BASE) +#define SPI0 ((SPI0_Type*) SPI0_BASE) +#define SPI1 ((SPI0_Type*) SPI1_BASE) +#define PIO0 ((PIO0_Type*) PIO0_BASE) +#define PIO1 ((PIO0_Type*) PIO1_BASE) +#define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) +#define SIO ((SIO_Type*) SIO_BASE) +#define USB ((USB_Type*) USB_BASE) +#define USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) +#define TBMAN ((TBMAN_Type*) TBMAN_BASE) +#define VREG_AND_CHIP_RESET ((VREG_AND_CHIP_RESET_Type*) VREG_AND_CHIP_RESET_BASE) +#define RTC ((RTC_Type*) RTC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +#ifdef __cplusplus +} +#endif + +#endif /* RP2040_H */ + + +/** @} */ /* End of group RP2040 */ + +/** @} */ /* End of group Raspberry Pi */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/system_RP2040.h similarity index 100% rename from src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h rename to src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/system_RP2040.h diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Source/system_RP2040.c similarity index 100% rename from src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c rename to src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Source/system_RP2040.c diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h new file mode 100644 index 000000000..8ae014e04 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h @@ -0,0 +1,6068 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + * + * @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h + * @brief CMSIS HeaderFile + * @version 0.1 + * @date Thu Aug 8 04:04:02 2024 + * @note Generated by SVDConv V3.3.47 + * from File 'src/rp2_common/cmsis/../../rp2350/hardware_regs/RP2350.svd', + * last modified on Thu Aug 8 03:59:33 2024 + */ + + +/** @addtogroup Raspberry Pi + * @{ + */ + + +/** @addtogroup RP2350 + * @{ + */ + + +#ifndef RP2350_H +#define RP2350_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== RP2350 Specific Interrupt Numbers =========================================== */ + TIMER0_IRQ_0_IRQn = 0, /*!< 0 TIMER0_IRQ_0 */ + TIMER0_IRQ_1_IRQn = 1, /*!< 1 TIMER0_IRQ_1 */ + TIMER0_IRQ_2_IRQn = 2, /*!< 2 TIMER0_IRQ_2 */ + TIMER0_IRQ_3_IRQn = 3, /*!< 3 TIMER0_IRQ_3 */ + TIMER1_IRQ_0_IRQn = 4, /*!< 4 TIMER1_IRQ_0 */ + TIMER1_IRQ_1_IRQn = 5, /*!< 5 TIMER1_IRQ_1 */ + TIMER1_IRQ_2_IRQn = 6, /*!< 6 TIMER1_IRQ_2 */ + TIMER1_IRQ_3_IRQn = 7, /*!< 7 TIMER1_IRQ_3 */ + PWM_IRQ_WRAP_0_IRQn = 8, /*!< 8 PWM_IRQ_WRAP_0 */ + PWM_IRQ_WRAP_1_IRQn = 9, /*!< 9 PWM_IRQ_WRAP_1 */ + DMA_IRQ_0_IRQn = 10, /*!< 10 DMA_IRQ_0 */ + DMA_IRQ_1_IRQn = 11, /*!< 11 DMA_IRQ_1 */ + DMA_IRQ_2_IRQn = 12, /*!< 12 DMA_IRQ_2 */ + DMA_IRQ_3_IRQn = 13, /*!< 13 DMA_IRQ_3 */ + USBCTRL_IRQ_IRQn = 14, /*!< 14 USBCTRL_IRQ */ + PIO0_IRQ_0_IRQn = 15, /*!< 15 PIO0_IRQ_0 */ + PIO0_IRQ_1_IRQn = 16, /*!< 16 PIO0_IRQ_1 */ + PIO1_IRQ_0_IRQn = 17, /*!< 17 PIO1_IRQ_0 */ + PIO1_IRQ_1_IRQn = 18, /*!< 18 PIO1_IRQ_1 */ + PIO2_IRQ_0_IRQn = 19, /*!< 19 PIO2_IRQ_0 */ + PIO2_IRQ_1_IRQn = 20, /*!< 20 PIO2_IRQ_1 */ + IO_IRQ_BANK0_IRQn = 21, /*!< 21 IO_IRQ_BANK0 */ + IO_IRQ_BANK0_NS_IRQn = 22, /*!< 22 IO_IRQ_BANK0_NS */ + IO_IRQ_QSPI_IRQn = 23, /*!< 23 IO_IRQ_QSPI */ + IO_IRQ_QSPI_NS_IRQn = 24, /*!< 24 IO_IRQ_QSPI_NS */ + SIO_IRQ_FIFO_IRQn = 25, /*!< 25 SIO_IRQ_FIFO */ + SIO_IRQ_BELL_IRQn = 26, /*!< 26 SIO_IRQ_BELL */ + SIO_IRQ_FIFO_NS_IRQn = 27, /*!< 27 SIO_IRQ_FIFO_NS */ + SIO_IRQ_BELL_NS_IRQn = 28, /*!< 28 SIO_IRQ_BELL_NS */ + SIO_IRQ_MTIMECMP_IRQn = 29, /*!< 29 SIO_IRQ_MTIMECMP */ + CLOCKS_IRQ_IRQn = 30, /*!< 30 CLOCKS_IRQ */ + SPI0_IRQ_IRQn = 31, /*!< 31 SPI0_IRQ */ + SPI1_IRQ_IRQn = 32, /*!< 32 SPI1_IRQ */ + UART0_IRQ_IRQn = 33, /*!< 33 UART0_IRQ */ + UART1_IRQ_IRQn = 34, /*!< 34 UART1_IRQ */ + ADC_IRQ_FIFO_IRQn = 35, /*!< 35 ADC_IRQ_FIFO */ + I2C0_IRQ_IRQn = 36, /*!< 36 I2C0_IRQ */ + I2C1_IRQ_IRQn = 37, /*!< 37 I2C1_IRQ */ + OTP_IRQ_IRQn = 38, /*!< 38 OTP_IRQ */ + TRNG_IRQ_IRQn = 39, /*!< 39 TRNG_IRQ */ + PLL_SYS_IRQ_IRQn = 42, /*!< 42 PLL_SYS_IRQ */ + PLL_USB_IRQ_IRQn = 43, /*!< 43 PLL_USB_IRQ */ + POWMAN_IRQ_POW_IRQn = 44, /*!< 44 POWMAN_IRQ_POW */ + POWMAN_IRQ_TIMER_IRQn = 45 /*!< 45 POWMAN_IRQ_TIMER */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ +#define __CM33_REV 0x0100U /*!< CM33 Core Revision */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __DSP_PRESENT 1 /*!< DSP extension present */ +#define __SAUREGION_PRESENT 1 /*!< SAU region present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_RP2350.h" /*!< RP2350 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ RESETS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief RESETS (RESETS) + */ + +typedef struct { /*!< RESETS Structure */ + __IOM uint32_t RESET; /*!< RESET */ + __IOM uint32_t WDSEL; /*!< WDSEL */ + __IOM uint32_t RESET_DONE; /*!< RESET_DONE */ +} RESETS_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ PSM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PSM (PSM) + */ + +typedef struct { /*!< PSM Structure */ + __IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */ + __IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */ + __IOM uint32_t WDSEL; /*!< Set to 1 if the watchdog should reset this */ + __IOM uint32_t DONE; /*!< Is the subsystem ready? */ +} PSM_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCKS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CLOCKS (CLOCKS) + */ + +typedef struct { /*!< CLOCKS Structure */ + __IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT0_DIV; /*!< CLK_GPOUT0_DIV */ + __IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT1_DIV; /*!< CLK_GPOUT1_DIV */ + __IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT2_DIV; /*!< CLK_GPOUT2_DIV */ + __IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT3_DIV; /*!< CLK_GPOUT3_DIV */ + __IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_REF_DIV; /*!< CLK_REF_DIV */ + __IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_SYS_DIV; /*!< CLK_SYS_DIV */ + __IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_PERI_DIV; /*!< CLK_PERI_DIV */ + __IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_HSTX_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_HSTX_DIV; /*!< CLK_HSTX_DIV */ + __IOM uint32_t CLK_HSTX_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_USB_DIV; /*!< CLK_USB_DIV */ + __IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_ADC_DIV; /*!< CLK_ADC_DIV */ + __IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t DFTCLK_XOSC_CTRL; /*!< DFTCLK_XOSC_CTRL */ + __IOM uint32_t DFTCLK_ROSC_CTRL; /*!< DFTCLK_ROSC_CTRL */ + __IOM uint32_t DFTCLK_LPOSC_CTRL; /*!< DFTCLK_LPOSC_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */ + __IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */ + __IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if + you are not using the pass/fail flags */ + __IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff + if you are not using the pass/fail flags */ + __IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period */ + __IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it + 1us * 2**interval The default gives a test interval of + 250us */ + __IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count */ + __IOM uint32_t FC0_STATUS; /*!< Frequency counter status */ + __IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */ + __IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */ + __IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */ + __IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */ + __IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */ + __IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */ + __IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} CLOCKS_Type; /*!< Size = 212 (0xd4) */ + + + +/* =========================================================================================================================== */ +/* ================ TICKS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TICKS (TICKS) + */ + +typedef struct { /*!< TICKS Structure */ + __IOM uint32_t PROC0_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t PROC0_CYCLES; /*!< PROC0_CYCLES */ + __IOM uint32_t PROC0_COUNT; /*!< PROC0_COUNT */ + __IOM uint32_t PROC1_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t PROC1_CYCLES; /*!< PROC1_CYCLES */ + __IOM uint32_t PROC1_COUNT; /*!< PROC1_COUNT */ + __IOM uint32_t TIMER0_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t TIMER0_CYCLES; /*!< TIMER0_CYCLES */ + __IOM uint32_t TIMER0_COUNT; /*!< TIMER0_COUNT */ + __IOM uint32_t TIMER1_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t TIMER1_CYCLES; /*!< TIMER1_CYCLES */ + __IOM uint32_t TIMER1_COUNT; /*!< TIMER1_COUNT */ + __IOM uint32_t WATCHDOG_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t WATCHDOG_CYCLES; /*!< WATCHDOG_CYCLES */ + __IOM uint32_t WATCHDOG_COUNT; /*!< WATCHDOG_COUNT */ + __IOM uint32_t RISCV_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t RISCV_CYCLES; /*!< RISCV_CYCLES */ + __IOM uint32_t RISCV_COUNT; /*!< RISCV_COUNT */ +} TICKS_Type; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_BANK0 (PADS_BANK0) + */ + +typedef struct { /*!< PADS_BANK0 Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO0; /*!< GPIO0 */ + __IOM uint32_t GPIO1; /*!< GPIO1 */ + __IOM uint32_t GPIO2; /*!< GPIO2 */ + __IOM uint32_t GPIO3; /*!< GPIO3 */ + __IOM uint32_t GPIO4; /*!< GPIO4 */ + __IOM uint32_t GPIO5; /*!< GPIO5 */ + __IOM uint32_t GPIO6; /*!< GPIO6 */ + __IOM uint32_t GPIO7; /*!< GPIO7 */ + __IOM uint32_t GPIO8; /*!< GPIO8 */ + __IOM uint32_t GPIO9; /*!< GPIO9 */ + __IOM uint32_t GPIO10; /*!< GPIO10 */ + __IOM uint32_t GPIO11; /*!< GPIO11 */ + __IOM uint32_t GPIO12; /*!< GPIO12 */ + __IOM uint32_t GPIO13; /*!< GPIO13 */ + __IOM uint32_t GPIO14; /*!< GPIO14 */ + __IOM uint32_t GPIO15; /*!< GPIO15 */ + __IOM uint32_t GPIO16; /*!< GPIO16 */ + __IOM uint32_t GPIO17; /*!< GPIO17 */ + __IOM uint32_t GPIO18; /*!< GPIO18 */ + __IOM uint32_t GPIO19; /*!< GPIO19 */ + __IOM uint32_t GPIO20; /*!< GPIO20 */ + __IOM uint32_t GPIO21; /*!< GPIO21 */ + __IOM uint32_t GPIO22; /*!< GPIO22 */ + __IOM uint32_t GPIO23; /*!< GPIO23 */ + __IOM uint32_t GPIO24; /*!< GPIO24 */ + __IOM uint32_t GPIO25; /*!< GPIO25 */ + __IOM uint32_t GPIO26; /*!< GPIO26 */ + __IOM uint32_t GPIO27; /*!< GPIO27 */ + __IOM uint32_t GPIO28; /*!< GPIO28 */ + __IOM uint32_t GPIO29; /*!< GPIO29 */ + __IOM uint32_t GPIO30; /*!< GPIO30 */ + __IOM uint32_t GPIO31; /*!< GPIO31 */ + __IOM uint32_t GPIO32; /*!< GPIO32 */ + __IOM uint32_t GPIO33; /*!< GPIO33 */ + __IOM uint32_t GPIO34; /*!< GPIO34 */ + __IOM uint32_t GPIO35; /*!< GPIO35 */ + __IOM uint32_t GPIO36; /*!< GPIO36 */ + __IOM uint32_t GPIO37; /*!< GPIO37 */ + __IOM uint32_t GPIO38; /*!< GPIO38 */ + __IOM uint32_t GPIO39; /*!< GPIO39 */ + __IOM uint32_t GPIO40; /*!< GPIO40 */ + __IOM uint32_t GPIO41; /*!< GPIO41 */ + __IOM uint32_t GPIO42; /*!< GPIO42 */ + __IOM uint32_t GPIO43; /*!< GPIO43 */ + __IOM uint32_t GPIO44; /*!< GPIO44 */ + __IOM uint32_t GPIO45; /*!< GPIO45 */ + __IOM uint32_t GPIO46; /*!< GPIO46 */ + __IOM uint32_t GPIO47; /*!< GPIO47 */ + __IOM uint32_t SWCLK; /*!< SWCLK */ + __IOM uint32_t SWD; /*!< SWD */ +} PADS_BANK0_Type; /*!< Size = 204 (0xcc) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_QSPI (PADS_QSPI) + */ + +typedef struct { /*!< PADS_QSPI Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO_QSPI_SCLK; /*!< GPIO_QSPI_SCLK */ + __IOM uint32_t GPIO_QSPI_SD0; /*!< GPIO_QSPI_SD0 */ + __IOM uint32_t GPIO_QSPI_SD1; /*!< GPIO_QSPI_SD1 */ + __IOM uint32_t GPIO_QSPI_SD2; /*!< GPIO_QSPI_SD2 */ + __IOM uint32_t GPIO_QSPI_SD3; /*!< GPIO_QSPI_SD3 */ + __IOM uint32_t GPIO_QSPI_SS; /*!< GPIO_QSPI_SS */ +} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_QSPI (IO_QSPI) + */ + +typedef struct { /*!< IO_QSPI Structure */ + __IOM uint32_t USBPHY_DP_STATUS; /*!< USBPHY_DP_STATUS */ + __IOM uint32_t USBPHY_DP_CTRL; /*!< USBPHY_DP_CTRL */ + __IOM uint32_t USBPHY_DM_STATUS; /*!< USBPHY_DM_STATUS */ + __IOM uint32_t USBPHY_DM_CTRL; /*!< USBPHY_DM_CTRL */ + __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO_QSPI_SCLK_STATUS */ + __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO_QSPI_SCLK_CTRL */ + __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO_QSPI_SS_STATUS */ + __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO_QSPI_SS_CTRL */ + __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO_QSPI_SD0_STATUS */ + __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO_QSPI_SD0_CTRL */ + __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO_QSPI_SD1_STATUS */ + __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO_QSPI_SD1_CTRL */ + __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO_QSPI_SD2_STATUS */ + __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO_QSPI_SD2_CTRL */ + __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO_QSPI_SD3_STATUS */ + __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO_QSPI_SD3_CTRL */ + __IM uint32_t RESERVED[112]; + __IOM uint32_t IRQSUMMARY_PROC0_SECURE; /*!< IRQSUMMARY_PROC0_SECURE */ + __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE; /*!< IRQSUMMARY_PROC0_NONSECURE */ + __IOM uint32_t IRQSUMMARY_PROC1_SECURE; /*!< IRQSUMMARY_PROC1_SECURE */ + __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE; /*!< IRQSUMMARY_PROC1_NONSECURE */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_QSPI_Type; /*!< Size = 576 (0x240) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_BANK0 (IO_BANK0) + */ + +typedef struct { /*!< IO_BANK0 Structure */ + __IOM uint32_t GPIO0_STATUS; /*!< GPIO0_STATUS */ + __IOM uint32_t GPIO0_CTRL; /*!< GPIO0_CTRL */ + __IOM uint32_t GPIO1_STATUS; /*!< GPIO1_STATUS */ + __IOM uint32_t GPIO1_CTRL; /*!< GPIO1_CTRL */ + __IOM uint32_t GPIO2_STATUS; /*!< GPIO2_STATUS */ + __IOM uint32_t GPIO2_CTRL; /*!< GPIO2_CTRL */ + __IOM uint32_t GPIO3_STATUS; /*!< GPIO3_STATUS */ + __IOM uint32_t GPIO3_CTRL; /*!< GPIO3_CTRL */ + __IOM uint32_t GPIO4_STATUS; /*!< GPIO4_STATUS */ + __IOM uint32_t GPIO4_CTRL; /*!< GPIO4_CTRL */ + __IOM uint32_t GPIO5_STATUS; /*!< GPIO5_STATUS */ + __IOM uint32_t GPIO5_CTRL; /*!< GPIO5_CTRL */ + __IOM uint32_t GPIO6_STATUS; /*!< GPIO6_STATUS */ + __IOM uint32_t GPIO6_CTRL; /*!< GPIO6_CTRL */ + __IOM uint32_t GPIO7_STATUS; /*!< GPIO7_STATUS */ + __IOM uint32_t GPIO7_CTRL; /*!< GPIO7_CTRL */ + __IOM uint32_t GPIO8_STATUS; /*!< GPIO8_STATUS */ + __IOM uint32_t GPIO8_CTRL; /*!< GPIO8_CTRL */ + __IOM uint32_t GPIO9_STATUS; /*!< GPIO9_STATUS */ + __IOM uint32_t GPIO9_CTRL; /*!< GPIO9_CTRL */ + __IOM uint32_t GPIO10_STATUS; /*!< GPIO10_STATUS */ + __IOM uint32_t GPIO10_CTRL; /*!< GPIO10_CTRL */ + __IOM uint32_t GPIO11_STATUS; /*!< GPIO11_STATUS */ + __IOM uint32_t GPIO11_CTRL; /*!< GPIO11_CTRL */ + __IOM uint32_t GPIO12_STATUS; /*!< GPIO12_STATUS */ + __IOM uint32_t GPIO12_CTRL; /*!< GPIO12_CTRL */ + __IOM uint32_t GPIO13_STATUS; /*!< GPIO13_STATUS */ + __IOM uint32_t GPIO13_CTRL; /*!< GPIO13_CTRL */ + __IOM uint32_t GPIO14_STATUS; /*!< GPIO14_STATUS */ + __IOM uint32_t GPIO14_CTRL; /*!< GPIO14_CTRL */ + __IOM uint32_t GPIO15_STATUS; /*!< GPIO15_STATUS */ + __IOM uint32_t GPIO15_CTRL; /*!< GPIO15_CTRL */ + __IOM uint32_t GPIO16_STATUS; /*!< GPIO16_STATUS */ + __IOM uint32_t GPIO16_CTRL; /*!< GPIO16_CTRL */ + __IOM uint32_t GPIO17_STATUS; /*!< GPIO17_STATUS */ + __IOM uint32_t GPIO17_CTRL; /*!< GPIO17_CTRL */ + __IOM uint32_t GPIO18_STATUS; /*!< GPIO18_STATUS */ + __IOM uint32_t GPIO18_CTRL; /*!< GPIO18_CTRL */ + __IOM uint32_t GPIO19_STATUS; /*!< GPIO19_STATUS */ + __IOM uint32_t GPIO19_CTRL; /*!< GPIO19_CTRL */ + __IOM uint32_t GPIO20_STATUS; /*!< GPIO20_STATUS */ + __IOM uint32_t GPIO20_CTRL; /*!< GPIO20_CTRL */ + __IOM uint32_t GPIO21_STATUS; /*!< GPIO21_STATUS */ + __IOM uint32_t GPIO21_CTRL; /*!< GPIO21_CTRL */ + __IOM uint32_t GPIO22_STATUS; /*!< GPIO22_STATUS */ + __IOM uint32_t GPIO22_CTRL; /*!< GPIO22_CTRL */ + __IOM uint32_t GPIO23_STATUS; /*!< GPIO23_STATUS */ + __IOM uint32_t GPIO23_CTRL; /*!< GPIO23_CTRL */ + __IOM uint32_t GPIO24_STATUS; /*!< GPIO24_STATUS */ + __IOM uint32_t GPIO24_CTRL; /*!< GPIO24_CTRL */ + __IOM uint32_t GPIO25_STATUS; /*!< GPIO25_STATUS */ + __IOM uint32_t GPIO25_CTRL; /*!< GPIO25_CTRL */ + __IOM uint32_t GPIO26_STATUS; /*!< GPIO26_STATUS */ + __IOM uint32_t GPIO26_CTRL; /*!< GPIO26_CTRL */ + __IOM uint32_t GPIO27_STATUS; /*!< GPIO27_STATUS */ + __IOM uint32_t GPIO27_CTRL; /*!< GPIO27_CTRL */ + __IOM uint32_t GPIO28_STATUS; /*!< GPIO28_STATUS */ + __IOM uint32_t GPIO28_CTRL; /*!< GPIO28_CTRL */ + __IOM uint32_t GPIO29_STATUS; /*!< GPIO29_STATUS */ + __IOM uint32_t GPIO29_CTRL; /*!< GPIO29_CTRL */ + __IOM uint32_t GPIO30_STATUS; /*!< GPIO30_STATUS */ + __IOM uint32_t GPIO30_CTRL; /*!< GPIO30_CTRL */ + __IOM uint32_t GPIO31_STATUS; /*!< GPIO31_STATUS */ + __IOM uint32_t GPIO31_CTRL; /*!< GPIO31_CTRL */ + __IOM uint32_t GPIO32_STATUS; /*!< GPIO32_STATUS */ + __IOM uint32_t GPIO32_CTRL; /*!< GPIO32_CTRL */ + __IOM uint32_t GPIO33_STATUS; /*!< GPIO33_STATUS */ + __IOM uint32_t GPIO33_CTRL; /*!< GPIO33_CTRL */ + __IOM uint32_t GPIO34_STATUS; /*!< GPIO34_STATUS */ + __IOM uint32_t GPIO34_CTRL; /*!< GPIO34_CTRL */ + __IOM uint32_t GPIO35_STATUS; /*!< GPIO35_STATUS */ + __IOM uint32_t GPIO35_CTRL; /*!< GPIO35_CTRL */ + __IOM uint32_t GPIO36_STATUS; /*!< GPIO36_STATUS */ + __IOM uint32_t GPIO36_CTRL; /*!< GPIO36_CTRL */ + __IOM uint32_t GPIO37_STATUS; /*!< GPIO37_STATUS */ + __IOM uint32_t GPIO37_CTRL; /*!< GPIO37_CTRL */ + __IOM uint32_t GPIO38_STATUS; /*!< GPIO38_STATUS */ + __IOM uint32_t GPIO38_CTRL; /*!< GPIO38_CTRL */ + __IOM uint32_t GPIO39_STATUS; /*!< GPIO39_STATUS */ + __IOM uint32_t GPIO39_CTRL; /*!< GPIO39_CTRL */ + __IOM uint32_t GPIO40_STATUS; /*!< GPIO40_STATUS */ + __IOM uint32_t GPIO40_CTRL; /*!< GPIO40_CTRL */ + __IOM uint32_t GPIO41_STATUS; /*!< GPIO41_STATUS */ + __IOM uint32_t GPIO41_CTRL; /*!< GPIO41_CTRL */ + __IOM uint32_t GPIO42_STATUS; /*!< GPIO42_STATUS */ + __IOM uint32_t GPIO42_CTRL; /*!< GPIO42_CTRL */ + __IOM uint32_t GPIO43_STATUS; /*!< GPIO43_STATUS */ + __IOM uint32_t GPIO43_CTRL; /*!< GPIO43_CTRL */ + __IOM uint32_t GPIO44_STATUS; /*!< GPIO44_STATUS */ + __IOM uint32_t GPIO44_CTRL; /*!< GPIO44_CTRL */ + __IOM uint32_t GPIO45_STATUS; /*!< GPIO45_STATUS */ + __IOM uint32_t GPIO45_CTRL; /*!< GPIO45_CTRL */ + __IOM uint32_t GPIO46_STATUS; /*!< GPIO46_STATUS */ + __IOM uint32_t GPIO46_CTRL; /*!< GPIO46_CTRL */ + __IOM uint32_t GPIO47_STATUS; /*!< GPIO47_STATUS */ + __IOM uint32_t GPIO47_CTRL; /*!< GPIO47_CTRL */ + __IM uint32_t RESERVED[32]; + __IOM uint32_t IRQSUMMARY_PROC0_SECURE0; /*!< IRQSUMMARY_PROC0_SECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC0_SECURE1; /*!< IRQSUMMARY_PROC0_SECURE1 */ + __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE0; /*!< IRQSUMMARY_PROC0_NONSECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE1; /*!< IRQSUMMARY_PROC0_NONSECURE1 */ + __IOM uint32_t IRQSUMMARY_PROC1_SECURE0; /*!< IRQSUMMARY_PROC1_SECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC1_SECURE1; /*!< IRQSUMMARY_PROC1_SECURE1 */ + __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE0; /*!< IRQSUMMARY_PROC1_NONSECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE1; /*!< IRQSUMMARY_PROC1_NONSECURE1 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE0 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE1 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE0 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE1 */ + __IOM uint32_t INTR0; /*!< Raw Interrupts */ + __IOM uint32_t INTR1; /*!< Raw Interrupts */ + __IOM uint32_t INTR2; /*!< Raw Interrupts */ + __IOM uint32_t INTR3; /*!< Raw Interrupts */ + __IOM uint32_t INTR4; /*!< Raw Interrupts */ + __IOM uint32_t INTR5; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE4; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE5; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF4; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF5; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS4; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS5; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE4; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE5; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF4; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF5; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS4; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS5; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE4; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE5; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF4; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF5; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS4; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS5; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_BANK0_Type; /*!< Size = 800 (0x320) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSINFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SYSINFO (SYSINFO) + */ + +typedef struct { /*!< SYSINFO Structure */ + __IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */ + __IOM uint32_t PACKAGE_SEL; /*!< PACKAGE_SEL */ + __IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment + it is running in during pre-production development. Post-production, + the PLATFORM is always ASIC, non-SIM. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t GITREF_RP2350; /*!< Git hash of the chip source. Used to identify chip version. */ +} SYSINFO_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SHA256 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SHA-256 hash function implementation (SHA256) + */ + +typedef struct { /*!< SHA256 Structure */ + __IOM uint32_t CSR; /*!< Control and status register */ + __IOM uint32_t WDATA; /*!< Write data register */ + __IOM uint32_t SUM0; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM1; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM2; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM3; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM4; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM5; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM6; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM7; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ +} SHA256_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ HSTX_FIFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FIFO status and write access for HSTX (HSTX_FIFO) + */ + +typedef struct { /*!< HSTX_FIFO Structure */ + __IOM uint32_t STAT; /*!< FIFO status */ + __IOM uint32_t FIFO; /*!< Write access to FIFO */ +} HSTX_FIFO_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ HSTX_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. (HSTX_CTRL) + */ + +typedef struct { /*!< HSTX_CTRL Structure */ + __IOM uint32_t CSR; /*!< CSR */ + __IOM uint32_t BIT0; /*!< Data control register for output bit 0 */ + __IOM uint32_t BIT1; /*!< Data control register for output bit 1 */ + __IOM uint32_t BIT2; /*!< Data control register for output bit 2 */ + __IOM uint32_t BIT3; /*!< Data control register for output bit 3 */ + __IOM uint32_t BIT4; /*!< Data control register for output bit 4 */ + __IOM uint32_t BIT5; /*!< Data control register for output bit 5 */ + __IOM uint32_t BIT6; /*!< Data control register for output bit 6 */ + __IOM uint32_t BIT7; /*!< Data control register for output bit 7 */ + __IOM uint32_t EXPAND_SHIFT; /*!< Configure the optional shifter inside the command expander */ + __IOM uint32_t EXPAND_TMDS; /*!< Configure the optional TMDS encoder inside the command expander */ +} HSTX_CTRL_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ EPPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cortex-M33 EPPB vendor register block for RP2350 (EPPB) + */ + +typedef struct { /*!< EPPB Structure */ + __IOM uint32_t NMI_MASK0; /*!< NMI mask for IRQs 0 through 31. This register is core-local, + and is reset by a processor warm reset. */ + __IOM uint32_t NMI_MASK1; /*!< NMI mask for IRQs 0 though 51. This register is core-local, + and is reset by a processor warm reset. */ + __IOM uint32_t SLEEPCTRL; /*!< Nonstandard sleep control register */ +} EPPB_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ PPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TEAL registers accessible through the debug interface (PPB) + */ + +typedef struct { /*!< PPB Structure */ + __IOM uint32_t ITM_STIM0; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM1; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM2; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM3; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM4; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM5; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM6; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM7; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM8; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM9; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM10; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM11; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM12; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM13; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM14; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM15; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM16; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM17; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM18; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM19; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM20; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM21; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM22; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM23; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM24; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM25; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM26; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM27; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM28; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM29; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM30; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM31; /*!< Provides the interface for generating Instrumentation packets */ + __IM uint32_t RESERVED[864]; + __IOM uint32_t ITM_TER0; /*!< Provide an individual enable bit for each ITM_STIM register */ + __IM uint32_t RESERVED1[15]; + __IOM uint32_t ITM_TPR; /*!< Controls which stimulus ports can be accessed by unprivileged + code */ + __IM uint32_t RESERVED2[15]; + __IOM uint32_t ITM_TCR; /*!< Configures and controls transfers through the ITM interface */ + __IM uint32_t RESERVED3[27]; + __IOM uint32_t INT_ATREADY; /*!< Integration Mode: Read ATB Ready */ + __IM uint32_t RESERVED4; + __IOM uint32_t INT_ATVALID; /*!< Integration Mode: Write ATB Valid */ + __IM uint32_t RESERVED5; + __IOM uint32_t ITM_ITCTRL; /*!< Integration Mode Control Register */ + __IM uint32_t RESERVED6[46]; + __IOM uint32_t ITM_DEVARCH; /*!< Provides CoreSight discovery information for the ITM */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t ITM_DEVTYPE; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR4; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR5; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR6; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR7; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR0; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR1; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR2; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR3; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR0; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR1; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR2; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR3; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t DWT_CTRL; /*!< Provides configuration and status information for the DWT unit, + and used to control features of the unit */ + __IOM uint32_t DWT_CYCCNT; /*!< Shows or sets the value of the processor cycle counter, CYCCNT */ + __IM uint32_t RESERVED8; + __IOM uint32_t DWT_EXCCNT; /*!< Counts the total cycles spent in exception processing */ + __IM uint32_t RESERVED9; + __IOM uint32_t DWT_LSUCNT; /*!< Increments on the additional cycles required to execute all + load or store instructions */ + __IOM uint32_t DWT_FOLDCNT; /*!< Increments on the additional cycles required to execute all + load or store instructions */ + __IM uint32_t RESERVED10; + __IOM uint32_t DWT_COMP0; /*!< Provides a reference value for use by watchpoint comparator + 0 */ + __IM uint32_t RESERVED11; + __IOM uint32_t DWT_FUNCTION0; /*!< Controls the operation of watchpoint comparator 0 */ + __IM uint32_t RESERVED12; + __IOM uint32_t DWT_COMP1; /*!< Provides a reference value for use by watchpoint comparator + 1 */ + __IM uint32_t RESERVED13; + __IOM uint32_t DWT_FUNCTION1; /*!< Controls the operation of watchpoint comparator 1 */ + __IM uint32_t RESERVED14; + __IOM uint32_t DWT_COMP2; /*!< Provides a reference value for use by watchpoint comparator + 2 */ + __IM uint32_t RESERVED15; + __IOM uint32_t DWT_FUNCTION2; /*!< Controls the operation of watchpoint comparator 2 */ + __IM uint32_t RESERVED16; + __IOM uint32_t DWT_COMP3; /*!< Provides a reference value for use by watchpoint comparator + 3 */ + __IM uint32_t RESERVED17; + __IOM uint32_t DWT_FUNCTION3; /*!< Controls the operation of watchpoint comparator 3 */ + __IM uint32_t RESERVED18[984]; + __IOM uint32_t DWT_DEVARCH; /*!< Provides CoreSight discovery information for the DWT */ + __IM uint32_t RESERVED19[3]; + __IOM uint32_t DWT_DEVTYPE; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR4; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR5; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR6; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR7; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR0; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR1; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR2; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR3; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR0; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR1; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR2; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR3; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t FP_CTRL; /*!< Provides FPB implementation information, and the global enable + for the FPB unit */ + __IOM uint32_t FP_REMAP; /*!< Indicates whether the implementation supports Flash Patch remap + and, if it does, holds the target address for remap */ + __IOM uint32_t FP_COMP0; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP1; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP2; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP3; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP4; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP5; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP6; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP7; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IM uint32_t RESERVED20[997]; + __IOM uint32_t FP_DEVARCH; /*!< Provides CoreSight discovery information for the FPB */ + __IM uint32_t RESERVED21[3]; + __IOM uint32_t FP_DEVTYPE; /*!< Provides CoreSight discovery information for the FPB */ + __IOM uint32_t FP_PIDR4; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR5; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR6; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR7; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR0; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR1; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR2; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR3; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR0; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR1; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR2; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR3; /*!< Provides CoreSight discovery information for the FP */ + __IM uint32_t RESERVED22[11265]; + __IOM uint32_t ICTR; /*!< Provides information about the interrupt controller */ + __IOM uint32_t ACTLR; /*!< Provides IMPLEMENTATION DEFINED configuration and control options */ + __IM uint32_t RESERVED23; + __IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick + features. */ + __IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value + to load into the current value register when the counter + reaches 0. It can be any value between 0 and 0x00FFFFFF. + A start value of 0 is possible, but has no effect because + the SysTick interrupt and COUNTFLAG are activated when + counting from 1 to 0. The reset value of this register + is UNKNOWN. To generate a multi-shot timer with a period + of N processor clock cycles, use a RELOAD value of N-1. + For example, if the SysTick interrupt is required every + 100 clock pulses, set RELOAD to 99. */ + __IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value + in the register. The reset value of this register is UNKNOWN. */ + __IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software + to scale to any required speed using divide and multiply. */ + __IM uint32_t RESERVED24[56]; + __IOM uint32_t NVIC_ISER0; /*!< Enables or reads the enabled state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ISER1; /*!< Enables or reads the enabled state of each group of 32 interrupts */ + __IM uint32_t RESERVED25[30]; + __IOM uint32_t NVIC_ICER0; /*!< Clears or reads the enabled state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ICER1; /*!< Clears or reads the enabled state of each group of 32 interrupts */ + __IM uint32_t RESERVED26[30]; + __IOM uint32_t NVIC_ISPR0; /*!< Enables or reads the pending state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ISPR1; /*!< Enables or reads the pending state of each group of 32 interrupts */ + __IM uint32_t RESERVED27[30]; + __IOM uint32_t NVIC_ICPR0; /*!< Clears or reads the pending state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ICPR1; /*!< Clears or reads the pending state of each group of 32 interrupts */ + __IM uint32_t RESERVED28[30]; + __IOM uint32_t NVIC_IABR0; /*!< For each group of 32 interrupts, shows the active state of each + interrupt */ + __IOM uint32_t NVIC_IABR1; /*!< For each group of 32 interrupts, shows the active state of each + interrupt */ + __IM uint32_t RESERVED29[30]; + __IOM uint32_t NVIC_ITNS0; /*!< For each group of 32 interrupts, determines whether each interrupt + targets Non-secure or Secure state */ + __IOM uint32_t NVIC_ITNS1; /*!< For each group of 32 interrupts, determines whether each interrupt + targets Non-secure or Secure state */ + __IM uint32_t RESERVED30[30]; + __IOM uint32_t NVIC_IPR0; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR1; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR2; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR3; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR4; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR5; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR6; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR7; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR8; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR9; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR10; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR11; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR12; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR13; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR14; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR15; /*!< Sets or reads interrupt priorities */ + __IM uint32_t RESERVED31[560]; + __IOM uint32_t CPUID; /*!< Provides identification information for the PE, including an + implementer code for the device and a device ID number */ + __IOM uint32_t ICSR; /*!< Controls and provides status information for NMI, PendSV, SysTick + and interrupts */ + __IOM uint32_t VTOR; /*!< The VTOR indicates the offset of the vector table base address + from memory address 0x00000000. */ + __IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to: + determine data endianness, clear all active state information + from debug halt mode, request a system reset. */ + __IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for + power-management functions: signal to the system when the + processor can enter a low power state, control how the + processor enters and exits low power states. */ + __IOM uint32_t CCR; /*!< Sets or returns configuration and control data */ + __IOM uint32_t SHPR1; /*!< Sets or returns priority for system handlers 4 - 7 */ + __IOM uint32_t SHPR2; /*!< Sets or returns priority for system handlers 8 - 11 */ + __IOM uint32_t SHPR3; /*!< Sets or returns priority for system handlers 12 - 15 */ + __IOM uint32_t SHCSR; /*!< Provides access to the active and pending status of system exceptions */ + __IOM uint32_t CFSR; /*!< Contains the three Configurable Fault Status Registers. 31:16 + UFSR: Provides information on UsageFault exceptions 15:8 + BFSR: Provides information on BusFault exceptions 7:0 MMFSR: + Provides information on MemManage exceptions */ + __IOM uint32_t HFSR; /*!< Shows the cause of any HardFaults */ + __IOM uint32_t DFSR; /*!< Shows which debug event occurred */ + __IOM uint32_t MMFAR; /*!< Shows the address of the memory location that caused an MPU + fault */ + __IOM uint32_t BFAR; /*!< Shows the address associated with a precise data access BusFault */ + __IM uint32_t RESERVED32; + __IOM uint32_t ID_PFR0; /*!< Gives top-level information about the instruction set supported + by the PE */ + __IOM uint32_t ID_PFR1; /*!< Gives information about the programmers' model and Extensions + support */ + __IOM uint32_t ID_DFR0; /*!< Provides top level information about the debug system */ + __IOM uint32_t ID_AFR0; /*!< Provides information about the IMPLEMENTATION DEFINED features + of the PE */ + __IOM uint32_t ID_MMFR0; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_MMFR1; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_MMFR2; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_MMFR3; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_ISAR0; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR1; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR2; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR3; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR4; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR5; /*!< Provides information about the instruction set implemented by + the PE */ + __IM uint32_t RESERVED33; + __IOM uint32_t CTR; /*!< Provides information about the architecture of the caches. CTR + is RES0 if CLIDR is zero. */ + __IM uint32_t RESERVED34[2]; + __IOM uint32_t CPACR; /*!< Specifies the access privileges for coprocessors and the FP + Extension */ + __IOM uint32_t NSACR; /*!< Defines the Non-secure access permissions for both the FP Extension + and coprocessors CP0 to CP7 */ + __IOM uint32_t MPU_TYPE; /*!< The MPU Type Register indicates how many regions the MPU `FTSSS + supports */ + __IOM uint32_t MPU_CTRL; /*!< Enables the MPU and, when the MPU is enabled, controls whether + the default memory map is enabled as a background region + for privileged accesses, and whether the MPU is enabled + for HardFaults, NMIs, and exception handlers when FAULTMASK + is set to 1 */ + __IOM uint32_t MPU_RNR; /*!< Selects the region currently accessed by MPU_RBAR and MPU_RLAR */ + __IOM uint32_t MPU_RBAR; /*!< Provides indirect read and write access to the base address + of the currently selected MPU region `FTSSS */ + __IOM uint32_t MPU_RLAR; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region `FTSSS */ + __IOM uint32_t MPU_RBAR_A1; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS */ + __IOM uint32_t MPU_RLAR_A1; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) + `FTSSS */ + __IOM uint32_t MPU_RBAR_A2; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS */ + __IOM uint32_t MPU_RLAR_A2; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) + `FTSSS */ + __IOM uint32_t MPU_RBAR_A3; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS */ + __IOM uint32_t MPU_RLAR_A3; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) + `FTSSS */ + __IM uint32_t RESERVED35; + __IOM uint32_t MPU_MAIR0; /*!< Along with MPU_MAIR1, provides the memory attribute encodings + corresponding to the AttrIndex values */ + __IOM uint32_t MPU_MAIR1; /*!< Along with MPU_MAIR0, provides the memory attribute encodings + corresponding to the AttrIndex values */ + __IM uint32_t RESERVED36[2]; + __IOM uint32_t SAU_CTRL; /*!< Allows enabling of the Security Attribution Unit */ + __IOM uint32_t SAU_TYPE; /*!< Indicates the number of regions implemented by the Security + Attribution Unit */ + __IOM uint32_t SAU_RNR; /*!< Selects the region currently accessed by SAU_RBAR and SAU_RLAR */ + __IOM uint32_t SAU_RBAR; /*!< Provides indirect read and write access to the base address + of the currently selected SAU region */ + __IOM uint32_t SAU_RLAR; /*!< Provides indirect read and write access to the limit address + of the currently selected SAU region */ + __IOM uint32_t SFSR; /*!< Provides information about any security related faults */ + __IOM uint32_t SFAR; /*!< Shows the address of the memory location that caused a Security + violation */ + __IM uint32_t RESERVED37; + __IOM uint32_t DHCSR; /*!< Controls halting debug */ + __IOM uint32_t DCRSR; /*!< With the DCRDR, provides debug access to the general-purpose + registers, special-purpose registers, and the FP extension + registers. A write to the DCRSR specifies the register + to transfer, whether the transfer is a read or write, and + starts the transfer */ + __IOM uint32_t DCRDR; /*!< With the DCRSR, provides debug access to the general-purpose + registers, special-purpose registers, and the FP Extension + registers. If the Main Extension is implemented, it can + also be used for message passing between an external debugger + and a debug agent running on the PE */ + __IOM uint32_t DEMCR; /*!< Manages vector catch behavior and DebugMonitor handling when + debugging */ + __IM uint32_t RESERVED38[2]; + __IOM uint32_t DSCSR; /*!< Provides control and status information for Secure debug */ + __IM uint32_t RESERVED39[61]; + __IOM uint32_t STIR; /*!< Provides a mechanism for software to generate an interrupt */ + __IM uint32_t RESERVED40[12]; + __IOM uint32_t FPCCR; /*!< Holds control data for the Floating-point extension */ + __IOM uint32_t FPCAR; /*!< Holds the location of the unpopulated floating-point register + space allocated on an exception stack frame */ + __IOM uint32_t FPDSCR; /*!< Holds the default values for the floating-point status control + data that the PE assigns to the FPSCR when it creates a + new floating-point context */ + __IOM uint32_t MVFR0; /*!< Describes the features provided by the Floating-point Extension */ + __IOM uint32_t MVFR1; /*!< Describes the features provided by the Floating-point Extension */ + __IOM uint32_t MVFR2; /*!< Describes the features provided by the Floating-point Extension */ + __IM uint32_t RESERVED41[28]; + __IOM uint32_t DDEVARCH; /*!< Provides CoreSight discovery information for the SCS */ + __IM uint32_t RESERVED42[3]; + __IOM uint32_t DDEVTYPE; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR4; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR5; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR6; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR7; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR0; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR1; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR2; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR3; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR0; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR1; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR2; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR3; /*!< Provides CoreSight discovery information for the SCS */ + __IM uint32_t RESERVED43[51201]; + __IOM uint32_t TRCPRGCTLR; /*!< Programming Control Register */ + __IM uint32_t RESERVED44; + __IOM uint32_t TRCSTATR; /*!< The TRCSTATR indicates the ETM-Teal status */ + __IOM uint32_t TRCCONFIGR; /*!< The TRCCONFIGR sets the basic tracing options for the trace + unit */ + __IM uint32_t RESERVED45[3]; + __IOM uint32_t TRCEVENTCTL0R; /*!< The TRCEVENTCTL0R controls the tracing of events in the trace + stream. The events also drive the ETM-Teal external outputs. */ + __IOM uint32_t TRCEVENTCTL1R; /*!< The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R + behave */ + __IM uint32_t RESERVED46; + __IOM uint32_t TRCSTALLCTLR; /*!< The TRCSTALLCTLR enables ETM-Teal to stall the processor if + the ETM-Teal FIFO goes over the programmed level to minimize + risk of overflow */ + __IOM uint32_t TRCTSCTLR; /*!< The TRCTSCTLR controls the insertion of global timestamps into + the trace stream. A timestamp is always inserted into the + instruction trace stream */ + __IOM uint32_t TRCSYNCPR; /*!< The TRCSYNCPR specifies the period of trace synchronization + of the trace streams. TRCSYNCPR defines a number of bytes + of trace between requests for trace synchronization. This + value is always a power of two */ + __IOM uint32_t TRCCCCTLR; /*!< The TRCCCCTLR sets the threshold value for instruction trace + cycle counting. The threshold represents the minimum interval + between cycle count trace packets */ + __IM uint32_t RESERVED47[17]; + __IOM uint32_t TRCVICTLR; /*!< The TRCVICTLR controls instruction trace filtering */ + __IM uint32_t RESERVED48[47]; + __IOM uint32_t TRCCNTRLDVR0; /*!< The TRCCNTRLDVR defines the reload value for the reduced function + counter */ + __IM uint32_t RESERVED49[15]; + __IOM uint32_t TRCIDR8; /*!< TRCIDR8 */ + __IOM uint32_t TRCIDR9; /*!< TRCIDR9 */ + __IOM uint32_t TRCIDR10; /*!< TRCIDR10 */ + __IOM uint32_t TRCIDR11; /*!< TRCIDR11 */ + __IOM uint32_t TRCIDR12; /*!< TRCIDR12 */ + __IOM uint32_t TRCIDR13; /*!< TRCIDR13 */ + __IM uint32_t RESERVED50[10]; + __IOM uint32_t TRCIMSPEC; /*!< The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC + features, and enables any features that are provided */ + __IM uint32_t RESERVED51[7]; + __IOM uint32_t TRCIDR0; /*!< TRCIDR0 */ + __IOM uint32_t TRCIDR1; /*!< TRCIDR1 */ + __IOM uint32_t TRCIDR2; /*!< TRCIDR2 */ + __IOM uint32_t TRCIDR3; /*!< TRCIDR3 */ + __IOM uint32_t TRCIDR4; /*!< TRCIDR4 */ + __IOM uint32_t TRCIDR5; /*!< TRCIDR5 */ + __IOM uint32_t TRCIDR6; /*!< TRCIDR6 */ + __IOM uint32_t TRCIDR7; /*!< TRCIDR7 */ + __IM uint32_t RESERVED52[2]; + __IOM uint32_t TRCRSCTLR2; /*!< The TRCRSCTLR controls the trace resources */ + __IOM uint32_t TRCRSCTLR3; /*!< The TRCRSCTLR controls the trace resources */ + __IM uint32_t RESERVED53[36]; + __IOM uint32_t TRCSSCSR; /*!< Controls the corresponding single-shot comparator resource */ + __IM uint32_t RESERVED54[7]; + __IOM uint32_t TRCSSPCICR; /*!< Selects the PE comparator inputs for Single-shot control */ + __IM uint32_t RESERVED55[19]; + __IOM uint32_t TRCPDCR; /*!< Requests the system to provide power to the trace unit */ + __IOM uint32_t TRCPDSR; /*!< Returns the following information about the trace unit: - OS + Lock status. - Core power domain status. - Power interruption + status */ + __IM uint32_t RESERVED56[755]; + __IOM uint32_t TRCITATBIDR; /*!< Trace Integration ATB Identification Register */ + __IM uint32_t RESERVED57[3]; + __IOM uint32_t TRCITIATBINR; /*!< Trace Integration Instruction ATB In Register */ + __IM uint32_t RESERVED58; + __IOM uint32_t TRCITIATBOUTR; /*!< Trace Integration Instruction ATB Out Register */ + __IM uint32_t RESERVED59[40]; + __IOM uint32_t TRCCLAIMSET; /*!< Claim Tag Set Register */ + __IOM uint32_t TRCCLAIMCLR; /*!< Claim Tag Clear Register */ + __IM uint32_t RESERVED60[4]; + __IOM uint32_t TRCAUTHSTATUS; /*!< Returns the level of tracing that the trace unit can support */ + __IOM uint32_t TRCDEVARCH; /*!< TRCDEVARCH */ + __IM uint32_t RESERVED61[2]; + __IOM uint32_t TRCDEVID; /*!< TRCDEVID */ + __IOM uint32_t TRCDEVTYPE; /*!< TRCDEVTYPE */ + __IOM uint32_t TRCPIDR4; /*!< TRCPIDR4 */ + __IOM uint32_t TRCPIDR5; /*!< TRCPIDR5 */ + __IOM uint32_t TRCPIDR6; /*!< TRCPIDR6 */ + __IOM uint32_t TRCPIDR7; /*!< TRCPIDR7 */ + __IOM uint32_t TRCPIDR0; /*!< TRCPIDR0 */ + __IOM uint32_t TRCPIDR1; /*!< TRCPIDR1 */ + __IOM uint32_t TRCPIDR2; /*!< TRCPIDR2 */ + __IOM uint32_t TRCPIDR3; /*!< TRCPIDR3 */ + __IOM uint32_t TRCCIDR0; /*!< TRCCIDR0 */ + __IOM uint32_t TRCCIDR1; /*!< TRCCIDR1 */ + __IOM uint32_t TRCCIDR2; /*!< TRCCIDR2 */ + __IOM uint32_t TRCCIDR3; /*!< TRCCIDR3 */ + __IOM uint32_t CTICONTROL; /*!< CTI Control Register */ + __IM uint32_t RESERVED62[3]; + __IOM uint32_t CTIINTACK; /*!< CTI Interrupt Acknowledge Register */ + __IOM uint32_t CTIAPPSET; /*!< CTI Application Trigger Set Register */ + __IOM uint32_t CTIAPPCLEAR; /*!< CTI Application Trigger Clear Register */ + __IOM uint32_t CTIAPPPULSE; /*!< CTI Application Pulse Register */ + __IOM uint32_t CTIINEN0; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN1; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN2; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN3; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN4; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN5; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN6; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN7; /*!< CTI Trigger to Channel Enable Registers */ + __IM uint32_t RESERVED63[24]; + __IOM uint32_t CTIOUTEN0; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN1; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN2; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN3; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN4; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN5; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN6; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN7; /*!< CTI Trigger to Channel Enable Registers */ + __IM uint32_t RESERVED64[28]; + __IOM uint32_t CTITRIGINSTATUS; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTITRIGOUTSTATUS; /*!< CTI Trigger In Status Register */ + __IOM uint32_t CTICHINSTATUS; /*!< CTI Channel In Status Register */ + __IM uint32_t RESERVED65; + __IOM uint32_t CTIGATE; /*!< Enable CTI Channel Gate register */ + __IOM uint32_t ASICCTL; /*!< External Multiplexer Control register */ + __IM uint32_t RESERVED66[871]; + __IOM uint32_t ITCHOUT; /*!< Integration Test Channel Output register */ + __IOM uint32_t ITTRIGOUT; /*!< Integration Test Trigger Output register */ + __IM uint32_t RESERVED67[2]; + __IOM uint32_t ITCHIN; /*!< Integration Test Channel Input register */ + __IM uint32_t RESERVED68[2]; + __IOM uint32_t ITCTRL; /*!< Integration Mode Control register */ + __IM uint32_t RESERVED69[46]; + __IOM uint32_t DEVARCH; /*!< Device Architecture register */ + __IM uint32_t RESERVED70[2]; + __IOM uint32_t DEVID; /*!< Device Configuration register */ + __IOM uint32_t DEVTYPE; /*!< Device Type Identifier register */ + __IOM uint32_t PIDR4; /*!< CoreSight Peripheral ID4 */ + __IOM uint32_t PIDR5; /*!< CoreSight Peripheral ID5 */ + __IOM uint32_t PIDR6; /*!< CoreSight Peripheral ID6 */ + __IOM uint32_t PIDR7; /*!< CoreSight Peripheral ID7 */ + __IOM uint32_t PIDR0; /*!< CoreSight Peripheral ID0 */ + __IOM uint32_t PIDR1; /*!< CoreSight Peripheral ID1 */ + __IOM uint32_t PIDR2; /*!< CoreSight Peripheral ID2 */ + __IOM uint32_t PIDR3; /*!< CoreSight Peripheral ID3 */ + __IOM uint32_t CIDR0; /*!< CoreSight Component ID0 */ + __IOM uint32_t CIDR1; /*!< CoreSight Component ID1 */ + __IOM uint32_t CIDR2; /*!< CoreSight Component ID2 */ + __IOM uint32_t CIDR3; /*!< CoreSight Component ID3 */ +} PPB_Type; /*!< Size = 274432 (0x43000) */ + + + +/* =========================================================================================================================== */ +/* ================ QMI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. (QMI) + */ + +typedef struct { /*!< QMI Structure */ + __IOM uint32_t DIRECT_CSR; /*!< Control and status for direct serial mode Direct serial mode + allows the processor to send and receive raw serial frames, + for programming, configuration and control of the external + memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. */ + __IOM uint32_t DIRECT_TX; /*!< Transmit FIFO for direct mode */ + __IOM uint32_t DIRECT_RX; /*!< Receive FIFO for direct mode */ + __IOM uint32_t M0_TIMING; /*!< Timing configuration register for memory address window 0. */ + __IOM uint32_t M0_RFMT; /*!< Read transfer format configuration for memory address window + 0. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M0_RFMT register is configured to support a basic 03h serial + read transfer with no additional configuration. */ + __IOM uint32_t M0_RCMD; /*!< Command constants used for reads from memory address window + 0. The reset value of the M0_RCMD register is configured + to support a basic 03h serial read transfer with no additional + configuration. */ + __IOM uint32_t M0_WFMT; /*!< Write transfer format configuration for memory address window + 0. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M0_WFMT register is configured to support a basic 02h serial + write transfer. However, writes to this window must first + be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory + is read-only by default. */ + __IOM uint32_t M0_WCMD; /*!< Command constants used for writes to memory address window 0. + The reset value of the M0_WCMD register is configured to + support a basic 02h serial write transfer with no additional + configuration. */ + __IOM uint32_t M1_TIMING; /*!< Timing configuration register for memory address window 1. */ + __IOM uint32_t M1_RFMT; /*!< Read transfer format configuration for memory address window + 1. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M1_RFMT register is configured to support a basic 03h serial + read transfer with no additional configuration. */ + __IOM uint32_t M1_RCMD; /*!< Command constants used for reads from memory address window + 1. The reset value of the M1_RCMD register is configured + to support a basic 03h serial read transfer with no additional + configuration. */ + __IOM uint32_t M1_WFMT; /*!< Write transfer format configuration for memory address window + 1. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M1_WFMT register is configured to support a basic 02h serial + write transfer. However, writes to this window must first + be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory + is read-only by default. */ + __IOM uint32_t M1_WCMD; /*!< Command constants used for writes to memory address window 1. + The reset value of the M1_WCMD register is configured to + support a basic 02h serial write transfer with no additional + configuration. */ + __IOM uint32_t ATRANS0; /*!< Configure address translation for XIP virtual addresses 0x000000 + through 0x3fffff (a 4 MiB window starting at +0 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + __IOM uint32_t ATRANS1; /*!< Configure address translation for XIP virtual addresses 0x400000 + through 0x7fffff (a 4 MiB window starting at +4 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + __IOM uint32_t ATRANS2; /*!< Configure address translation for XIP virtual addresses 0x800000 + through 0xbfffff (a 4 MiB window starting at +8 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + __IOM uint32_t ATRANS3; /*!< Configure address translation for XIP virtual addresses 0xc00000 + through 0xffffff (a 4 MiB window starting at +12 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS4; /*!< Configure address translation for XIP virtual addresses 0x1000000 + through 0x13fffff (a 4 MiB window starting at +16 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS5; /*!< Configure address translation for XIP virtual addresses 0x1400000 + through 0x17fffff (a 4 MiB window starting at +20 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS6; /*!< Configure address translation for XIP virtual addresses 0x1800000 + through 0x1bfffff (a 4 MiB window starting at +24 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS7; /*!< Configure address translation for XIP virtual addresses 0x1c00000 + through 0x1ffffff (a 4 MiB window starting at +28 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ +} QMI_Type; /*!< Size = 84 (0x54) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI flash execute-in-place block (XIP_CTRL) + */ + +typedef struct { /*!< XIP_CTRL Structure */ + __IOM uint32_t CTRL; /*!< Cache control register. Read-only from a Non-secure context. */ + __IM uint32_t RESERVED; + __IOM uint32_t STAT; /*!< STAT */ + __IOM uint32_t CTR_HIT; /*!< Cache Hit counter */ + __IOM uint32_t CTR_ACC; /*!< Cache Access counter */ + __IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */ + __IOM uint32_t STREAM_CTR; /*!< FIFO stream control */ + __IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */ +} XIP_CTRL_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_AUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Auxiliary DMA access to XIP FIFOs, via fast AHB bus access (XIP_AUX) + */ + +typedef struct { /*!< XIP_AUX Structure */ + __IOM uint32_t STREAM; /*!< Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) */ + __IOM uint32_t QMI_DIRECT_TX; /*!< Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) */ + __IOM uint32_t QMI_DIRECT_RX; /*!< Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) */ +} XIP_AUX_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for various chip control signals (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + __IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */ + __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 0...31. */ + __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 32...47. USB GPIO 56..57 + QSPI GPIO 58..63 */ + __IOM uint32_t DBGFORCE; /*!< Directly control the chip SWD debug port */ + __IOM uint32_t MEMPOWERDOWN; /*!< Control PD pins to memories. Set high to put memories to a low + power state. In this state the memories will retain contents + but not be accessible Use with caution */ + __IOM uint32_t AUXCTRL; /*!< Auxiliary system control register */ +} SYSCFG_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ XOSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls the crystal oscillator (XOSC) + */ + +typedef struct { /*!< XOSC Structure */ + __IOM uint32_t CTRL; /*!< Crystal Oscillator Control */ + __IOM uint32_t STATUS; /*!< Crystal Oscillator Status */ + __IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */ + __IOM uint32_t STARTUP; /*!< Controls the startup delay */ + __IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to + zero and stops. Can be used for short software pauses when + setting up time sensitive hardware. To start the counter, + write a non-zero value. Reads will return 1 while the count + is running and 0 when it has finished. Minimum count value + is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain + costs 2 register clock cycles and the counter cannot compensate + for that. */ +} XOSC_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ PLL_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PLL_SYS (PLL_SYS) + */ + +typedef struct { /*!< PLL_SYS Structure */ + __IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency + min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO + frequency min=750MHz, max=1600MHz */ + __IOM uint32_t PWR; /*!< Controls the PLL power modes. */ + __IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional + division) */ + __IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note: + this PLL does not have a secondary output) the primary + output is driven from VCO divided by postdiv1*postdiv2 */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} PLL_SYS_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ ACCESSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Hardware access control registers (ACCESSCTRL) + */ + +typedef struct { /*!< ACCESSCTRL Structure */ + __IOM uint32_t LOCK; /*!< Once a LOCK bit is written to 1, ACCESSCTRL silently ignores + writes from that master. LOCK is writable only by a Secure, + Privileged processor or debugger. LOCK bits are only writable + when their value is zero. Once set, they can never be cleared, + except by a full reset of ACCESSCTRL Setting the LOCK bit + does not affect whether an access raises a bus error. Unprivileged + writes, or writes from the DMA, will continue to raise + bus errors. All other accesses will continue not to. */ + __IOM uint32_t FORCE_CORE_NS; /*!< Force core 1's bus accesses to always be Non-secure, no matter + the core's internal state. Useful for schemes where one + core is designated as the Non-secure core, since some peripherals + may filter individual registers internally based on security + state but not on master ID. */ + __IOM uint32_t CFGRESET; /*!< Write 1 to reset all ACCESSCTRL configuration, except for the + LOCK and FORCE_CORE_NS registers. This bit is used in the + RP2350 bootrom to quickly restore ACCESSCTRL to a known + state during the boot path. Note that, like all registers + in ACCESSCTRL, this register is not writable when the writer's + corresponding LOCK bit is set, therefore a master which + has been locked out of ACCESSCTRL can not use the CFGRESET + register to disturb its contents. */ + __IOM uint32_t GPIO_NSMASK0; /*!< Control whether GPIO0...31 are accessible to Non-secure code. + Writable only by a Secure, Privileged processor or debugger. + 0 -> Secure access only 1 -> Secure + Non-secure access */ + __IOM uint32_t GPIO_NSMASK1; /*!< Control whether GPIO32..47 are accessible to Non-secure code, + and whether QSPI and USB bitbang are accessible through + the Non-secure SIO. Writable only by a Secure, Privileged + processor or debugger. */ + __IOM uint32_t ROM; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ROM, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t XIP_MAIN; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_MAIN, and at what security/privilege levels they can + do so. Defaults to fully open access. This register is + writable only from a Secure, Privileged processor or debugger, + with the exception of the NSU bit, which becomes Non-secure-Privileged-wr + table when the NSP bit is set. */ + __IOM uint32_t SRAM0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM0, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM1, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM2; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM2, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM3; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM3, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM4; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM4, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM5; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM5, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM6; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM6, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM7; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM7, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM8; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM8, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM9; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM9, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t DMA; /*!< Control whether debugger, DMA, core 0 and core 1 can access + DMA, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t USBCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access + USBCTRL, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PIO0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PIO1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PIO2; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO2, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t CORESIGHT_TRACE; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CORESIGHT_TRACE, and at what security/privilege levels + they can do so. Defaults to Secure, Privileged processor + or debug access only. This register is writable only from + a Secure, Privileged processor or debugger, with the exception + of the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t CORESIGHT_PERIPH; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CORESIGHT_PERIPH, and at what security/privilege levels + they can do so. Defaults to Secure, Privileged processor + or debug access only. This register is writable only from + a Secure, Privileged processor or debugger, with the exception + of the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t SYSINFO; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SYSINFO, and at what security/privilege levels they can + do so. Defaults to fully open access. This register is + writable only from a Secure, Privileged processor or debugger, + with the exception of the NSU bit, which becomes Non-secure-Privileged-wr + table when the NSP bit is set. */ + __IOM uint32_t RESETS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + RESETS, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t IO_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + IO_BANK0, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t IO_BANK1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + IO_BANK1, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PADS_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PADS_BANK0, and at what security/privilege levels they + can do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PADS_QSPI; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PADS_QSPI, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t BUSCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access + BUSCTRL, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t ADC0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ADC0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t HSTX; /*!< Control whether debugger, DMA, core 0 and core 1 can access + HSTX, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t I2C0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + I2C0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t I2C1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + I2C1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PWM; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PWM, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t SPI0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SPI0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t SPI1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SPI1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t TIMER0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TIMER0, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t TIMER1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TIMER1, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t UART0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + UART0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t UART1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + UART1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t OTP; /*!< Control whether debugger, DMA, core 0 and core 1 can access + OTP, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t TBMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TBMAN, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t POWMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access + POWMAN, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t TRNG; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TRNG, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t SHA256; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SHA256, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged access only. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t SYSCFG; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SYSCFG, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t CLOCKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CLOCKS, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t XOSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XOSC, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t ROSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ROSC, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t PLL_SYS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PLL_SYS, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t PLL_USB; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PLL_USB, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t TICKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TICKS, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t WATCHDOG; /*!< Control whether debugger, DMA, core 0 and core 1 can access + WATCHDOG, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t RSM; /*!< Control whether debugger, DMA, core 0 and core 1 can access + RSM, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t XIP_CTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_CTRL, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t XIP_QMI; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_QMI, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t XIP_AUX; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_AUX, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged access only. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ +} ACCESSCTRL_Type; /*!< Size = 236 (0xec) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + __IOM uint32_t UARTDR; /*!< Data Register, UARTDR */ + __IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */ + __IM uint32_t RESERVED1; + __IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */ + __IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */ + __IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */ + __IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */ + __IOM uint32_t UARTCR; /*!< Control Register, UARTCR */ + __IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ + __IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ + __IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */ + __IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */ + __IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */ + __IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */ + __IM uint32_t RESERVED2[997]; + __IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */ + __IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */ + __IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */ + __IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */ + __IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */ + __IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */ + __IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */ + __IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */ +} UART0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ ROSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ROSC (ROSC) + */ + +typedef struct { /*!< ROSC Structure */ + __IOM uint32_t CTRL; /*!< Ring Oscillator control */ + __IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling + the drive strength of each stage The drive strength has + 4 levels determined by the number of bits set Increasing + the number of bits set increases the drive strength and + increases the oscillation frequency 0 bits set is the default + drive strength 1 bit set doubles the drive strength 2 bits + set triples drive strength 3 bits set quadruples drive + strength For frequency randomisation set both DS0_RANDOM=1 + & DS1_RANDOM=1 */ + __IOM uint32_t FREQB; /*!< For a detailed description see freqa register */ + __IOM uint32_t RANDOM; /*!< Loads a value to the LFSR randomiser */ + __IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */ + __IOM uint32_t DIV; /*!< Controls the output divider */ + __IOM uint32_t PHASE; /*!< Controls the phase shifted output */ + __IOM uint32_t STATUS; /*!< Ring Oscillator Status */ + __IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness + is compromised if the ring oscillator is stopped or run + at a harmonic of the bus frequency */ + __IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to + zero and stops. To start the counter write a non-zero value. + Can be used for short software pauses when setting up time + sensitive hardware. */ +} ROSC_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ POWMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use (POWMAN) + */ + +typedef struct { /*!< POWMAN Structure */ + __IOM uint32_t BADPASSWD; /*!< Indicates a bad password has been used */ + __IOM uint32_t VREG_CTRL; /*!< Voltage Regulator Control */ + __IOM uint32_t VREG_STS; /*!< Voltage Regulator Status */ + __IOM uint32_t VREG; /*!< Voltage Regulator Settings */ + __IOM uint32_t VREG_LP_ENTRY; /*!< Voltage Regulator Low Power Entry Settings */ + __IOM uint32_t VREG_LP_EXIT; /*!< Voltage Regulator Low Power Exit Settings */ + __IOM uint32_t BOD_CTRL; /*!< Brown-out Detection Control */ + __IOM uint32_t BOD; /*!< Brown-out Detection Settings */ + __IOM uint32_t BOD_LP_ENTRY; /*!< Brown-out Detection Low Power Entry Settings */ + __IOM uint32_t BOD_LP_EXIT; /*!< Brown-out Detection Low Power Exit Settings */ + __IOM uint32_t LPOSC; /*!< Low power oscillator control register. */ + __IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */ + __IOM uint32_t WDSEL; /*!< Allows a watchdog reset to reset the internal state of powman + in addition to the power-on state machine (PSM). Note that + powman ignores watchdog resets that do not select at least + the CLOCKS stage or earlier stages in the PSM. If using + these bits, it's recommended to set PSM_WDSEL to all-ones + in addition to the desired bits in this register. Failing + to select CLOCKS or earlier will result in the POWMAN_WDSEL + register having no effect. */ + __IOM uint32_t SEQ_CFG; /*!< For configuration of the power sequencer Writes are ignored + while POWMAN_STATE_CHANGING=1 */ + __IOM uint32_t STATE; /*!< This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT + which is read-only. To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds + to the power states defined in the datasheet: bit 3 = SWCORE + bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered + up 1 = powered down When POWMAN_STATE_REQ is written, the + POWMAN_STATE_WAITING flag is set while the Power Manager + determines what is required. If an invalid transition is + requested the Power Manager will still register the request + in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ + flag. It will then implement the power-up requests and + ignore the power down requests. To do nothing would risk + entering an unrecoverable lock-up state. Invalid requests + are: any combination of power up and power down requests + any request that results in swcore boing powered and xip + unpowered If the request is to power down the switched-core + domain then POWMAN_STATE_WAITING stays active until the + processors halt. During this time the POWMAN_STATE_REQ + field can be re-written to change or cancel the request. + When the power state transition begins the POWMAN_STATE_WAITING_flag + is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN + register writes are ignored until the transition completes. */ + __IOM uint32_t POW_FASTDIV; /*!< POW_FASTDIV */ + __IOM uint32_t POW_DELAY; /*!< power state machine delays */ + __IOM uint32_t EXT_CTRL0; /*!< Configures a gpio as a power mode aware control output */ + __IOM uint32_t EXT_CTRL1; /*!< Configures a gpio as a power mode aware control output */ + __IOM uint32_t EXT_TIME_REF; /*!< Select a GPIO to use as a time reference, the source can be + used to drive the low power clock at 32kHz, or to provide + a 1ms tick to the timer, or provide a 1Hz tick to the timer. + The tick selection is controlled by the POWMAN_TIMER register. */ + __IOM uint32_t LPOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock + frequency when running off the LPOSC. */ + __IOM uint32_t LPOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock + frequency when running off the LPOSC. */ + __IOM uint32_t XOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock + frequency when running off the XOSC. */ + __IOM uint32_t XOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock + frequency when running off the XOSC. */ + __IOM uint32_t SET_TIME_63TO48; /*!< SET_TIME_63TO48 */ + __IOM uint32_t SET_TIME_47TO32; /*!< SET_TIME_47TO32 */ + __IOM uint32_t SET_TIME_31TO16; /*!< SET_TIME_31TO16 */ + __IOM uint32_t SET_TIME_15TO0; /*!< SET_TIME_15TO0 */ + __IOM uint32_t READ_TIME_UPPER; /*!< READ_TIME_UPPER */ + __IOM uint32_t READ_TIME_LOWER; /*!< READ_TIME_LOWER */ + __IOM uint32_t ALARM_TIME_63TO48; /*!< ALARM_TIME_63TO48 */ + __IOM uint32_t ALARM_TIME_47TO32; /*!< ALARM_TIME_47TO32 */ + __IOM uint32_t ALARM_TIME_31TO16; /*!< ALARM_TIME_31TO16 */ + __IOM uint32_t ALARM_TIME_15TO0; /*!< ALARM_TIME_15TO0 */ + __IOM uint32_t TIMER; /*!< TIMER */ + __IOM uint32_t PWRUP0; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t PWRUP1; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t PWRUP2; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t PWRUP3; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t CURRENT_PWRUP_REQ; /*!< Indicates current powerup request state pwrup events can be + cleared by removing the enable from the pwrup register. + The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup + 6 = alarm_pwrup */ + __IOM uint32_t LAST_SWCORE_PWRUP; /*!< Indicates which pwrup source triggered the last switched-core + power up 0 = chip reset, for the source of the last reset + see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 + 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup */ + __IOM uint32_t DBG_PWRCFG; /*!< DBG_PWRCFG */ + __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore the BOOT0..3 registers following + the next RSM reset (e.g. the next core power down/up). + If an early boot stage has soft-locked some OTP pages in + order to protect their contents from later stages, there + is a risk that Secure code running at a later stage can + unlock the pages by powering the core up and down. This + register can be used to ensure that the bootloader runs + as normal on the next power up, preventing Secure code + at a later stage from accessing OTP in its unlocked state. + Should be used in conjunction with the OTP BOOTDIS register. */ + __IOM uint32_t DBGCONFIG; /*!< DBGCONFIG */ + __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT0; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT1; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT2; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT3; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} POWMAN_Type; /*!< Size = 240 (0xf0) */ + + + +/* =========================================================================================================================== */ +/* ================ WATCHDOG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief WATCHDOG (WATCHDOG) + */ + +typedef struct { /*!< WATCHDOG Structure */ + __IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems + are reset when the watchdog is triggered. The watchdog + can be triggered in software. */ + __IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which + corresponds to approximately 16 seconds. */ + __IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the + case of a hardware reset. Additionally, as of RP2350, a + debugger warm reset of either core (SYSRESETREQ or hartreset) + will also clear the watchdog reason register, so that software + loaded under the debugger following a watchdog timeout + will not continue to see the timeout condition. */ + __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of + the chip. */ +} WATCHDOG_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA with separate read and write masters (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */ + __IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */ + __IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */ + __IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */ + __IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */ + __IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */ + __IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */ + __IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */ + __IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */ + __IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */ + __IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */ + __IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */ + __IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */ + __IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */ + __IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */ + __IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */ + __IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */ + __IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */ + __IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */ + __IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */ + __IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */ + __IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */ + __IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */ + __IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */ + __IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */ + __IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */ + __IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */ + __IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */ + __IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */ + __IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */ + __IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */ + __IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */ + __IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */ + __IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */ + __IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */ + __IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */ + __IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */ + __IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */ + __IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */ + __IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */ + __IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */ + __IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */ + __IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */ + __IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */ + __IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */ + __IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */ + __IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */ + __IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */ + __IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH12_READ_ADDR; /*!< DMA Channel 12 Read Address pointer */ + __IOM uint32_t CH12_WRITE_ADDR; /*!< DMA Channel 12 Write Address pointer */ + __IOM uint32_t CH12_TRANS_COUNT; /*!< DMA Channel 12 Transfer Count */ + __IOM uint32_t CH12_CTRL_TRIG; /*!< DMA Channel 12 Control and Status */ + __IOM uint32_t CH12_AL1_CTRL; /*!< Alias for channel 12 CTRL register */ + __IOM uint32_t CH12_AL1_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ + __IOM uint32_t CH12_AL1_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ + __IOM uint32_t CH12_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 12 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH12_AL2_CTRL; /*!< Alias for channel 12 CTRL register */ + __IOM uint32_t CH12_AL2_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ + __IOM uint32_t CH12_AL2_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ + __IOM uint32_t CH12_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 12 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH12_AL3_CTRL; /*!< Alias for channel 12 CTRL register */ + __IOM uint32_t CH12_AL3_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ + __IOM uint32_t CH12_AL3_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ + __IOM uint32_t CH12_AL3_READ_ADDR_TRIG; /*!< Alias for channel 12 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH13_READ_ADDR; /*!< DMA Channel 13 Read Address pointer */ + __IOM uint32_t CH13_WRITE_ADDR; /*!< DMA Channel 13 Write Address pointer */ + __IOM uint32_t CH13_TRANS_COUNT; /*!< DMA Channel 13 Transfer Count */ + __IOM uint32_t CH13_CTRL_TRIG; /*!< DMA Channel 13 Control and Status */ + __IOM uint32_t CH13_AL1_CTRL; /*!< Alias for channel 13 CTRL register */ + __IOM uint32_t CH13_AL1_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ + __IOM uint32_t CH13_AL1_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ + __IOM uint32_t CH13_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 13 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH13_AL2_CTRL; /*!< Alias for channel 13 CTRL register */ + __IOM uint32_t CH13_AL2_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ + __IOM uint32_t CH13_AL2_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ + __IOM uint32_t CH13_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 13 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH13_AL3_CTRL; /*!< Alias for channel 13 CTRL register */ + __IOM uint32_t CH13_AL3_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ + __IOM uint32_t CH13_AL3_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ + __IOM uint32_t CH13_AL3_READ_ADDR_TRIG; /*!< Alias for channel 13 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH14_READ_ADDR; /*!< DMA Channel 14 Read Address pointer */ + __IOM uint32_t CH14_WRITE_ADDR; /*!< DMA Channel 14 Write Address pointer */ + __IOM uint32_t CH14_TRANS_COUNT; /*!< DMA Channel 14 Transfer Count */ + __IOM uint32_t CH14_CTRL_TRIG; /*!< DMA Channel 14 Control and Status */ + __IOM uint32_t CH14_AL1_CTRL; /*!< Alias for channel 14 CTRL register */ + __IOM uint32_t CH14_AL1_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ + __IOM uint32_t CH14_AL1_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ + __IOM uint32_t CH14_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 14 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH14_AL2_CTRL; /*!< Alias for channel 14 CTRL register */ + __IOM uint32_t CH14_AL2_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ + __IOM uint32_t CH14_AL2_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ + __IOM uint32_t CH14_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 14 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH14_AL3_CTRL; /*!< Alias for channel 14 CTRL register */ + __IOM uint32_t CH14_AL3_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ + __IOM uint32_t CH14_AL3_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ + __IOM uint32_t CH14_AL3_READ_ADDR_TRIG; /*!< Alias for channel 14 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH15_READ_ADDR; /*!< DMA Channel 15 Read Address pointer */ + __IOM uint32_t CH15_WRITE_ADDR; /*!< DMA Channel 15 Write Address pointer */ + __IOM uint32_t CH15_TRANS_COUNT; /*!< DMA Channel 15 Transfer Count */ + __IOM uint32_t CH15_CTRL_TRIG; /*!< DMA Channel 15 Control and Status */ + __IOM uint32_t CH15_AL1_CTRL; /*!< Alias for channel 15 CTRL register */ + __IOM uint32_t CH15_AL1_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ + __IOM uint32_t CH15_AL1_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ + __IOM uint32_t CH15_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 15 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH15_AL2_CTRL; /*!< Alias for channel 15 CTRL register */ + __IOM uint32_t CH15_AL2_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ + __IOM uint32_t CH15_AL2_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ + __IOM uint32_t CH15_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 15 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH15_AL3_CTRL; /*!< Alias for channel 15 CTRL register */ + __IOM uint32_t CH15_AL3_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ + __IOM uint32_t CH15_AL3_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ + __IOM uint32_t CH15_AL3_READ_ADDR_TRIG; /*!< Alias for channel 15 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t INTR; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */ + __IOM uint32_t INTF0; /*!< Force Interrupts */ + __IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */ + __IOM uint32_t INTR1; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */ + __IOM uint32_t INTF1; /*!< Force Interrupts */ + __IOM uint32_t INTS1; /*!< Interrupt Status for IRQ 1 */ + __IOM uint32_t INTR2; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE2; /*!< Interrupt Enables for IRQ 2 */ + __IOM uint32_t INTF2; /*!< Force Interrupts */ + __IOM uint32_t INTS2; /*!< Interrupt Status for IRQ 2 */ + __IOM uint32_t INTR3; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE3; /*!< Interrupt Enables for IRQ 3 */ + __IOM uint32_t INTF3; /*!< Force Interrupts */ + __IOM uint32_t INTS3; /*!< Interrupt Status for IRQ 3 */ + __IOM uint32_t TIMER0; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER1; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER2; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER3; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */ + __IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */ + __IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */ + __IM uint32_t RESERVED; + __IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */ + __IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */ + __IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This + DMA supports up to 16 hardware channels, but can be configured + with as few as one, to minimise silicon area. */ + __IM uint32_t RESERVED1[5]; + __IOM uint32_t SECCFG_CH0; /*!< Security configuration for channel 0. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH1; /*!< Security configuration for channel 1. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH2; /*!< Security configuration for channel 2. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH3; /*!< Security configuration for channel 3. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH4; /*!< Security configuration for channel 4. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH5; /*!< Security configuration for channel 5. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH6; /*!< Security configuration for channel 6. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH7; /*!< Security configuration for channel 7. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH8; /*!< Security configuration for channel 8. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH9; /*!< Security configuration for channel 9. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH10; /*!< Security configuration for channel 10. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH11; /*!< Security configuration for channel 11. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH12; /*!< Security configuration for channel 12. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH13; /*!< Security configuration for channel 13. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH14; /*!< Security configuration for channel 14. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH15; /*!< Security configuration for channel 15. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_IRQ0; /*!< Security configuration for IRQ 0. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_IRQ1; /*!< Security configuration for IRQ 1. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_IRQ2; /*!< Security configuration for IRQ 2. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_IRQ3; /*!< Security configuration for IRQ 3. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_MISC; /*!< Miscellaneous security configuration */ + __IM uint32_t RESERVED2[11]; + __IOM uint32_t MPU_CTRL; /*!< Control register for DMA MPU. Accessible only from a Privileged + context. */ + __IOM uint32_t MPU_BAR0; /*!< Base address register for MPU region 0. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR0; /*!< Limit address register for MPU region 0. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR1; /*!< Base address register for MPU region 1. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR1; /*!< Limit address register for MPU region 1. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR2; /*!< Base address register for MPU region 2. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR2; /*!< Limit address register for MPU region 2. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR3; /*!< Base address register for MPU region 3. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR3; /*!< Limit address register for MPU region 3. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR4; /*!< Base address register for MPU region 4. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR4; /*!< Limit address register for MPU region 4. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR5; /*!< Base address register for MPU region 5. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR5; /*!< Limit address register for MPU region 5. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR6; /*!< Base address register for MPU region 6. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR6; /*!< Limit address register for MPU region 6. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR7; /*!< Base address register for MPU region 7. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR7; /*!< Limit address register for MPU region 7. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IM uint32_t RESERVED3[175]; + __IOM uint32_t CH0_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH0_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED4[14]; + __IOM uint32_t CH1_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH1_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED5[14]; + __IOM uint32_t CH2_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH2_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED6[14]; + __IOM uint32_t CH3_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH3_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED7[14]; + __IOM uint32_t CH4_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH4_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED8[14]; + __IOM uint32_t CH5_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH5_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED9[14]; + __IOM uint32_t CH6_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH6_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t CH7_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH7_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t CH8_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH8_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED12[14]; + __IOM uint32_t CH9_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH9_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED13[14]; + __IOM uint32_t CH10_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH10_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED14[14]; + __IOM uint32_t CH11_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH11_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED15[14]; + __IOM uint32_t CH12_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH12_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED16[14]; + __IOM uint32_t CH13_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH13_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED17[14]; + __IOM uint32_t CH14_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH14_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED18[14]; + __IOM uint32_t CH15_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH15_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ +} DMA_Type; /*!< Size = 3016 (0xbc8) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing (TIMER0) + */ + +typedef struct { /*!< TIMER0 Structure */ + __IOM uint32_t TIMEHW; /*!< Write to bits 63:32 of time always write timelw before timehw */ + __IOM uint32_t TIMELW; /*!< Write to bits 31:0 of time writes do not get copied to time + until timehw is written */ + __IOM uint32_t TIMEHR; /*!< Read from bits 63:32 of time always read timelr before timehr */ + __IOM uint32_t TIMELR; /*!< Read from bits 31:0 of time */ + __IOM uint32_t ALARM0; /*!< Arm alarm 0, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM0 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM1; /*!< Arm alarm 1, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM1 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM2; /*!< Arm alarm 2, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM2 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM3; /*!< Arm alarm 3, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM3 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ARMED; /*!< Indicates the armed/disarmed status of each alarm. A write to + the corresponding ALARMx register arms the alarm. Alarms + automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. */ + __IOM uint32_t TIMERAWH; /*!< Raw read from bits 63:32 of time (no side effects) */ + __IOM uint32_t TIMERAWL; /*!< Raw read from bits 31:0 of time (no side effects) */ + __IOM uint32_t DBGPAUSE; /*!< Set bits high to enable pause when the corresponding debug ports + are active */ + __IOM uint32_t PAUSE; /*!< Set high to pause the timer */ + __IOM uint32_t LOCKED; /*!< Set locked bit to disable write access to timer Once set, cannot + be cleared (without a reset) */ + __IOM uint32_t SOURCE; /*!< Selects the source for the timer. Defaults to the normal tick + configured in the ticks block (typically configured to + 1 microsecond). Writing to 1 will ignore the tick and count + clk_sys cycles instead. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} TIMER0_Type; /*!< Size = 76 (0x4c) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Simple PWM (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __IOM uint32_t CH0_CSR; /*!< Control and status register */ + __IOM uint32_t CH0_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH0_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH0_CC; /*!< Counter compare values */ + __IOM uint32_t CH0_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH1_CSR; /*!< Control and status register */ + __IOM uint32_t CH1_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH1_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH1_CC; /*!< Counter compare values */ + __IOM uint32_t CH1_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH2_CSR; /*!< Control and status register */ + __IOM uint32_t CH2_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH2_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH2_CC; /*!< Counter compare values */ + __IOM uint32_t CH2_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH3_CSR; /*!< Control and status register */ + __IOM uint32_t CH3_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH3_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH3_CC; /*!< Counter compare values */ + __IOM uint32_t CH3_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH4_CSR; /*!< Control and status register */ + __IOM uint32_t CH4_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH4_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH4_CC; /*!< Counter compare values */ + __IOM uint32_t CH4_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH5_CSR; /*!< Control and status register */ + __IOM uint32_t CH5_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH5_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH5_CC; /*!< Counter compare values */ + __IOM uint32_t CH5_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH6_CSR; /*!< Control and status register */ + __IOM uint32_t CH6_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH6_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH6_CC; /*!< Counter compare values */ + __IOM uint32_t CH6_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH7_CSR; /*!< Control and status register */ + __IOM uint32_t CH7_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH7_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH7_CC; /*!< Counter compare values */ + __IOM uint32_t CH7_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH8_CSR; /*!< Control and status register */ + __IOM uint32_t CH8_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH8_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH8_CC; /*!< Counter compare values */ + __IOM uint32_t CH8_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH9_CSR; /*!< Control and status register */ + __IOM uint32_t CH9_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH9_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH9_CC; /*!< Counter compare values */ + __IOM uint32_t CH9_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH10_CSR; /*!< Control and status register */ + __IOM uint32_t CH10_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH10_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH10_CC; /*!< Counter compare values */ + __IOM uint32_t CH10_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH11_CSR; /*!< Control and status register */ + __IOM uint32_t CH11_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH11_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH11_CC; /*!< Counter compare values */ + __IOM uint32_t CH11_TOP; /*!< Counter wrap value */ + __IOM uint32_t EN; /*!< This register aliases the CSR_EN bits for all channels. Writing + to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect + sync. For each channel, there is only one physical EN register + bit, which can be accessed through here or CHx_CSR. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ + __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ +} PWM_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control and data interface to SAR ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __IOM uint32_t CS; /*!< ADC Control and Status */ + __IOM uint32_t RESULT; /*!< Result of most recent ADC conversion */ + __IOM uint32_t FCS; /*!< FIFO control and status */ + __IOM uint32_t FIFO; /*!< Conversion result FIFO */ + __IOM uint32_t DIV; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. The divider + is reset when either of these fields are written. Total + period is 1 + INT + FRAC / 256 */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} ADC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + __IOM uint32_t IC_CON; /*!< I2C Control Register. This register can be written only when + the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] + register being set to 0. Writes at other times have no + effect. Read/Write Access: - bit 10 is read only. - bit + 11 is read only - bit 16 is read only - bit 17 is read + only - bits 18 and 19 are read only. */ + __IOM uint32_t IC_TAR; /*!< I2C Target Address Register This register is 12 bits wide, and + bits 31:12 are reserved. This register can be written to + only when IC_ENABLE[0] is set to 0. Note: If the software + or application is aware that the DW_apb_i2c is not using + the TAR address for the pending commands in the Tx FIFO, + then it is possible to update the TAR address even while + the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not + necessary to perform any write to this register if DW_apb_i2c + is enabled as an I2C slave only. */ + __IOM uint32_t IC_SAR; /*!< I2C Slave Address Register */ + __IM uint32_t RESERVED; + __IOM uint32_t IC_DATA_CMD; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register + the CPU writes to when filling the TX FIFO and the CPU + reads from when retrieving bytes from RX FIFO. The size + of the register changes as follows: Write: - 11 bits when + IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 + Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 + bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order + for the DW_apb_i2c to continue acknowledging reads, a read + command should be written for every byte that is to be + received; otherwise the DW_apb_i2c will stop acknowledging. */ + __IOM uint32_t IC_SS_SCL_HCNT; /*!< Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t IC_SS_SCL_LCNT; /*!< Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t IC_FS_SCL_HCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ + __IOM uint32_t IC_FS_SCL_LCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t IC_INTR_STAT; /*!< I2C Interrupt Status Register Each bit in this register has + a corresponding mask bit in the IC_INTR_MASK register. + These bits are cleared by reading the matching interrupt + clear register. The unmasked raw versions of these bits + are available in the IC_RAW_INTR_STAT register. */ + __IOM uint32_t IC_INTR_MASK; /*!< I2C Interrupt Mask Register. These bits mask their corresponding + interrupt status bits. This register is active low; a value + of 0 masks the interrupt, whereas a value of 1 unmasks + the interrupt. */ + __IOM uint32_t IC_RAW_INTR_STAT; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, + these bits are not masked so they always show the true + status of the DW_apb_i2c. */ + __IOM uint32_t IC_RX_TL; /*!< I2C Receive FIFO Threshold Register */ + __IOM uint32_t IC_TX_TL; /*!< I2C Transmit FIFO Threshold Register */ + __IOM uint32_t IC_CLR_INTR; /*!< Clear Combined and Individual Interrupt Register */ + __IOM uint32_t IC_CLR_RX_UNDER; /*!< Clear RX_UNDER Interrupt Register */ + __IOM uint32_t IC_CLR_RX_OVER; /*!< Clear RX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_TX_OVER; /*!< Clear TX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_RD_REQ; /*!< Clear RD_REQ Interrupt Register */ + __IOM uint32_t IC_CLR_TX_ABRT; /*!< Clear TX_ABRT Interrupt Register */ + __IOM uint32_t IC_CLR_RX_DONE; /*!< Clear RX_DONE Interrupt Register */ + __IOM uint32_t IC_CLR_ACTIVITY; /*!< Clear ACTIVITY Interrupt Register */ + __IOM uint32_t IC_CLR_STOP_DET; /*!< Clear STOP_DET Interrupt Register */ + __IOM uint32_t IC_CLR_START_DET; /*!< Clear START_DET Interrupt Register */ + __IOM uint32_t IC_CLR_GEN_CALL; /*!< Clear GEN_CALL Interrupt Register */ + __IOM uint32_t IC_ENABLE; /*!< I2C Enable Register */ + __IOM uint32_t IC_STATUS; /*!< I2C Status Register This is a read-only register used to indicate + the current transfer status and FIFO status. The status + register may be read at any time. None of the bits in this + register request an interrupt. When the I2C is disabled + by writing 0 in bit 0 of the IC_ENABLE register: - Bits + 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When + the master or slave state machines goes to idle and ic_en=0: + - Bits 5 and 6 are set to 0 */ + __IOM uint32_t IC_TXFLR; /*!< I2C Transmit FIFO Level Register This register contains the + number of valid data entries in the transmit FIFO buffer. + It is cleared whenever: - The I2C is disabled - There is + a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT + register - The slave bulk transmit mode is aborted The + register increments whenever data is placed into the transmit + FIFO and decrements when data is taken from the transmit + FIFO. */ + __IOM uint32_t IC_RXFLR; /*!< I2C Receive FIFO Level Register This register contains the number + of valid data entries in the receive FIFO buffer. It is + cleared whenever: - The I2C is disabled - Whenever there + is a transmit abort caused by any of the events tracked + in IC_TX_ABRT_SOURCE The register increments whenever data + is placed into the receive FIFO and decrements when data + is taken from the receive FIFO. */ + __IOM uint32_t IC_SDA_HOLD; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register + are used to control the hold time of SDA during transmit + in both slave and master mode (after SCL goes from HIGH + to LOW). The bits [23:16] of this register are used to + extend the SDA transition (if any) whenever SCL is HIGH + in the receiver in either master or slave mode. Writes + to this register succeed only when IC_ENABLE[0]=0. The + values in this register are in units of ic_clk period. + The value programmed in IC_SDA_TX_HOLD must be greater + than the minimum hold time in each mode (one cycle in master + mode, seven cycles in slave mode) for the value to be implemented. + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) + cannot exceed at any time the duration of the low part + of scl. Therefore the programmed value cannot be larger + than N_SCL_LOW-2, where N_SCL_LOW is the duration of the + low part of the scl period measured in ic_clk cycles. */ + __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< I2C Transmit Abort Source Register This register has 32 bits + that indicate the source of the TX_ABRT bit. Except for + Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT + register or the IC_CLR_INTR register is read. To clear + Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed + first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL + bit must be cleared (IC_TAR[11]), or the GC_OR_START bit + must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT + is fixed, then this bit can be cleared in the same manner + as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT + is not fixed before attempting to clear this bit, Bit 9 + clears for one cycle and is then re-asserted. */ + __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< Generate Slave Data NACK Register The register is used to generate + a NACK for the data part of a transfer when DW_apb_i2c + is acting as a slave-receiver. This register only exists + when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When + this parameter disabled, this register does not exist and + writing to the register's address has no effect. A write + can occur on this register if both of the following conditions + are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - + Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] + is a register read-back location for the internal slv_activity + signal; the user should poll this before writing the ic_slv_data_nack_onl + bit. */ + __IOM uint32_t IC_DMA_CR; /*!< DMA Control Register The register is used to enable the DMA + Controller interface operation. There is a separate bit + for transmit and receive. This can be programmed regardless + of the state of IC_ENABLE. */ + __IOM uint32_t IC_DMA_TDLR; /*!< DMA Transmit Data Level Register */ + __IOM uint32_t IC_DMA_RDLR; /*!< I2C Receive Data Level Register */ + __IOM uint32_t IC_SDA_SETUP; /*!< I2C SDA Setup Register This register controls the amount of + time delay (in terms of number of ic_clk clock periods) + introduced in the rising edge of SCL - relative to SDA + changing - when DW_apb_i2c services a read request in a + slave-transmitter operation. The relevant I2C requirement + is tSU:DAT (note 4) as detailed in the I2C Bus Specification. + This register must be programmed with a value equal to + or greater than 2. Writes to this register succeed only + when IC_ENABLE[0] = 0. Note: The length of setup time is + calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], + so if the user requires 10 ic_clk periods of setup time, + they should program a value of 11. The IC_SDA_SETUP register + is only used by the DW_apb_i2c when operating as a slave + transmitter. */ + __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK General Call Register The register controls whether + DW_apb_i2c responds with a ACK or NACK when it receives + an I2C General Call address. This register is applicable + only when the DW_apb_i2c is in slave mode. */ + __IOM uint32_t IC_ENABLE_STATUS; /*!< I2C Enable Status Register The register is used to report the + DW_apb_i2c hardware status when the IC_ENABLE[0] register + is set from 1 to 0; that is, when DW_apb_i2c is disabled. + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced + to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been + set to 0, bits 2:1 is only be valid as soon as bit 0 is + read as '0'. Note: When IC_ENABLE[0] has been set to 0, + a delay occurs for bit 0 to be read as 0 because disabling + the DW_apb_i2c depends on I2C bus activities. */ + __IOM uint32_t IC_FS_SPKLEN; /*!< I2C SS, FS or FM+ spike suppression limit This register is used + to store the duration, measured in ic_clk cycles, of the + longest spike that is filtered out by the spike suppression + logic when the component is operating in SS, FS or FM+ + modes. The relevant I2C requirement is tSP (table 4) as + detailed in the I2C Bus Specification. This register must + be programmed with a minimum value of 1. */ + __IM uint32_t RESERVED2; + __IOM uint32_t IC_CLR_RESTART_DET; /*!< Clear RESTART_DET Interrupt Register */ + __IM uint32_t RESERVED3[18]; + __IOM uint32_t IC_COMP_PARAM_1; /*!< Component Parameter Register 1 Note This register is not implemented + and therefore reads as 0. If it was implemented it would + be a constant read-only register that contains encoded + information about the component's parameter settings. Fields + shown below are the settings for those parameters */ + __IOM uint32_t IC_COMP_VERSION; /*!< I2C Component Version Register */ + __IOM uint32_t IC_COMP_TYPE; /*!< I2C Component Type Register */ +} I2C0_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + __IOM uint32_t SSPCR0; /*!< Control register 0, SSPCR0 on page 3-4 */ + __IOM uint32_t SSPCR1; /*!< Control register 1, SSPCR1 on page 3-5 */ + __IOM uint32_t SSPDR; /*!< Data register, SSPDR on page 3-6 */ + __IOM uint32_t SSPSR; /*!< Status register, SSPSR on page 3-7 */ + __IOM uint32_t SSPCPSR; /*!< Clock prescale register, SSPCPSR on page 3-8 */ + __IOM uint32_t SSPIMSC; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ + __IOM uint32_t SSPRIS; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ + __IOM uint32_t SSPMIS; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ + __IOM uint32_t SSPICR; /*!< Interrupt clear register, SSPICR on page 3-11 */ + __IOM uint32_t SSPDMACR; /*!< DMA control register, SSPDMACR on page 3-12 */ + __IM uint32_t RESERVED[1006]; + __IOM uint32_t SSPPERIPHID0; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID1; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID2; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID3; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPCELLID0; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID1; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID2; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID3; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ +} SPI0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ PIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable IO block (PIO0) + */ + +typedef struct { /*!< PIO0 Structure */ + __IOM uint32_t CTRL; /*!< PIO control register */ + __IOM uint32_t FSTAT; /*!< FIFO status register */ + __IOM uint32_t FDEBUG; /*!< FIFO debug register */ + __IOM uint32_t FLEVEL; /*!< FIFO levels */ + __IOM uint32_t TXF0; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF1; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF2; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF3; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t RXF0; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF1; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF2; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF3; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t IRQ; /*!< State machine IRQ flags register. Write 1 to clear. There are + eight state machine IRQ flags, which can be set, cleared, + and waited on by the state machines. There's no fixed association + between flags and state machines -- any state machine can + use any flag. Any of the eight flags can be used for timing + synchronisation between state machines, using IRQ and WAIT + instructions. Any combination of the eight flags can also + routed out to either of the two system-level interrupt + requests, alongside FIFO status interrupts -- see e.g. + IRQ0_INTE. */ + __IOM uint32_t IRQ_FORCE; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding + IRQ. Note this is different to the INTF register: writing + here affects PIO internal state. INTF just asserts the + processor-facing IRQ signal for testing ISRs, and is not + visible to the state machines. */ + __IOM uint32_t INPUT_SYNC_BYPASS; /*!< There is a 2-flipflop synchronizer on each GPIO input, which + protects PIO logic from metastabilities. This increases + input delay, and for fast synchronous IO (e.g. SPI) these + synchronizers may need to be bypassed. Each bit in this + register corresponds to one GPIO. 0 -> input is synchronized + (default) 1 -> synchronizer is bypassed If in doubt, leave + this register as all zeroes. */ + __IOM uint32_t DBG_PADOUT; /*!< Read to sample the pad output values PIO is currently driving + to the GPIOs. On RP2040 there are 30 GPIOs, so the two + most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_PADOE; /*!< Read to sample the pad output enables (direction) PIO is currently + driving to the GPIOs. On RP2040 there are 30 GPIOs, so + the two most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_CFGINFO; /*!< The PIO hardware has some free parameters that may vary between + chip products. These should be provided in the chip datasheet, + but are also exposed here. */ + __IOM uint32_t INSTR_MEM0; /*!< Write-only access to instruction memory location 0 */ + __IOM uint32_t INSTR_MEM1; /*!< Write-only access to instruction memory location 1 */ + __IOM uint32_t INSTR_MEM2; /*!< Write-only access to instruction memory location 2 */ + __IOM uint32_t INSTR_MEM3; /*!< Write-only access to instruction memory location 3 */ + __IOM uint32_t INSTR_MEM4; /*!< Write-only access to instruction memory location 4 */ + __IOM uint32_t INSTR_MEM5; /*!< Write-only access to instruction memory location 5 */ + __IOM uint32_t INSTR_MEM6; /*!< Write-only access to instruction memory location 6 */ + __IOM uint32_t INSTR_MEM7; /*!< Write-only access to instruction memory location 7 */ + __IOM uint32_t INSTR_MEM8; /*!< Write-only access to instruction memory location 8 */ + __IOM uint32_t INSTR_MEM9; /*!< Write-only access to instruction memory location 9 */ + __IOM uint32_t INSTR_MEM10; /*!< Write-only access to instruction memory location 10 */ + __IOM uint32_t INSTR_MEM11; /*!< Write-only access to instruction memory location 11 */ + __IOM uint32_t INSTR_MEM12; /*!< Write-only access to instruction memory location 12 */ + __IOM uint32_t INSTR_MEM13; /*!< Write-only access to instruction memory location 13 */ + __IOM uint32_t INSTR_MEM14; /*!< Write-only access to instruction memory location 14 */ + __IOM uint32_t INSTR_MEM15; /*!< Write-only access to instruction memory location 15 */ + __IOM uint32_t INSTR_MEM16; /*!< Write-only access to instruction memory location 16 */ + __IOM uint32_t INSTR_MEM17; /*!< Write-only access to instruction memory location 17 */ + __IOM uint32_t INSTR_MEM18; /*!< Write-only access to instruction memory location 18 */ + __IOM uint32_t INSTR_MEM19; /*!< Write-only access to instruction memory location 19 */ + __IOM uint32_t INSTR_MEM20; /*!< Write-only access to instruction memory location 20 */ + __IOM uint32_t INSTR_MEM21; /*!< Write-only access to instruction memory location 21 */ + __IOM uint32_t INSTR_MEM22; /*!< Write-only access to instruction memory location 22 */ + __IOM uint32_t INSTR_MEM23; /*!< Write-only access to instruction memory location 23 */ + __IOM uint32_t INSTR_MEM24; /*!< Write-only access to instruction memory location 24 */ + __IOM uint32_t INSTR_MEM25; /*!< Write-only access to instruction memory location 25 */ + __IOM uint32_t INSTR_MEM26; /*!< Write-only access to instruction memory location 26 */ + __IOM uint32_t INSTR_MEM27; /*!< Write-only access to instruction memory location 27 */ + __IOM uint32_t INSTR_MEM28; /*!< Write-only access to instruction memory location 28 */ + __IOM uint32_t INSTR_MEM29; /*!< Write-only access to instruction memory location 29 */ + __IOM uint32_t INSTR_MEM30; /*!< Write-only access to instruction memory location 30 */ + __IOM uint32_t INSTR_MEM31; /*!< Write-only access to instruction memory location 31 */ + __IOM uint32_t SM0_CLKDIV; /*!< Clock divisor register for state machine 0 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM0_EXECCTRL; /*!< Execution/behavioural settings for state machine 0 */ + __IOM uint32_t SM0_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 0 */ + __IOM uint32_t SM0_ADDR; /*!< Current instruction address of state machine 0 */ + __IOM uint32_t SM0_INSTR; /*!< Read to see the instruction currently addressed by state machine + 0's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM0_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM1_CLKDIV; /*!< Clock divisor register for state machine 1 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM1_EXECCTRL; /*!< Execution/behavioural settings for state machine 1 */ + __IOM uint32_t SM1_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 1 */ + __IOM uint32_t SM1_ADDR; /*!< Current instruction address of state machine 1 */ + __IOM uint32_t SM1_INSTR; /*!< Read to see the instruction currently addressed by state machine + 1's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM1_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM2_CLKDIV; /*!< Clock divisor register for state machine 2 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM2_EXECCTRL; /*!< Execution/behavioural settings for state machine 2 */ + __IOM uint32_t SM2_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 2 */ + __IOM uint32_t SM2_ADDR; /*!< Current instruction address of state machine 2 */ + __IOM uint32_t SM2_INSTR; /*!< Read to see the instruction currently addressed by state machine + 2's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM2_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM3_CLKDIV; /*!< Clock divisor register for state machine 3 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM3_EXECCTRL; /*!< Execution/behavioural settings for state machine 3 */ + __IOM uint32_t SM3_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 3 */ + __IOM uint32_t SM3_ADDR; /*!< Current instruction address of state machine 3 */ + __IOM uint32_t SM3_INSTR; /*!< Read to see the instruction currently addressed by state machine + 3's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM3_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t RXF0_PUTGET0; /*!< Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF0_PUTGET1; /*!< Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF0_PUTGET2; /*!< Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF0_PUTGET3; /*!< Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET0; /*!< Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET1; /*!< Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET2; /*!< Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET3; /*!< Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET0; /*!< Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET1; /*!< Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET2; /*!< Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET3; /*!< Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET0; /*!< Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET1; /*!< Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET2; /*!< Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET3; /*!< Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t GPIOBASE; /*!< Relocate GPIO 0 (from PIO's point of view) in the system GPIO + numbering, to access more than 32 GPIOs from PIO. Only + the values 0 and 16 are supported (only bit 4 is writable). */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ + __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ +} PIO0_Type; /*!< Size = 392 (0x188) */ + + + +/* =========================================================================================================================== */ +/* ================ BUSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for busfabric control signals and performance counters (BUSCTRL) + */ + +typedef struct { /*!< BUSCTRL Structure */ + __IOM uint32_t BUS_PRIORITY; /*!< Set the priority of each master for bus arbitration. */ + __IOM uint32_t BUS_PRIORITY_ACK; /*!< Bus priority acknowledge */ + __IOM uint32_t PERFCTR_EN; /*!< Enable the performance counters. If 0, the performance counters + do not increment. This can be used to precisely start/stop + event sampling around the profiled section of code. The + performance counters are initially disabled, to save energy. */ + __IOM uint32_t PERFCTR0; /*!< Bus fabric performance counter 0 */ + __IOM uint32_t PERFSEL0; /*!< Bus fabric performance event select for PERFCTR0 */ + __IOM uint32_t PERFCTR1; /*!< Bus fabric performance counter 1 */ + __IOM uint32_t PERFSEL1; /*!< Bus fabric performance event select for PERFCTR1 */ + __IOM uint32_t PERFCTR2; /*!< Bus fabric performance counter 2 */ + __IOM uint32_t PERFSEL2; /*!< Bus fabric performance event select for PERFCTR2 */ + __IOM uint32_t PERFCTR3; /*!< Bus fabric performance counter 3 */ + __IOM uint32_t PERFSEL3; /*!< Bus fabric performance event select for PERFCTR3 */ +} BUSCTRL_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) + */ + +typedef struct { /*!< SIO Structure */ + __IOM uint32_t CPUID; /*!< Processor core identifier */ + __IOM uint32_t GPIO_IN; /*!< Input value for GPIO0...31. In the Non-secure SIO, Secure-only + GPIOs (as per ACCESSCTRL) appear as zero. */ + __IOM uint32_t GPIO_HI_IN; /*!< Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure + SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. */ + __IM uint32_t RESERVED; + __IOM uint32_t GPIO_OUT; /*!< GPIO0...31 output value */ + __IOM uint32_t GPIO_HI_OUT; /*!< Output value for GPIO32...47, QSPI IOs and USB pins. Write to + set output level (1/0 -> high/low). Reading back gives + the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously + (or to a SET/CLR/XOR alias), the result is as though the + write from core 0 took place first, and the write from + core 1 was then applied to that intermediate result. In + the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) + ignore writes, and their output status reads back as zero. + This is also true for SET/CLR/XOR aliases of this register. */ + __IOM uint32_t GPIO_OUT_SET; /*!< GPIO0...31 output value set */ + __IOM uint32_t GPIO_HI_OUT_SET; /*!< Output value set for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= + wdata` */ + __IOM uint32_t GPIO_OUT_CLR; /*!< GPIO0...31 output value clear */ + __IOM uint32_t GPIO_HI_OUT_CLR; /*!< Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= + ~wdata` */ + __IOM uint32_t GPIO_OUT_XOR; /*!< GPIO0...31 output value XOR */ + __IOM uint32_t GPIO_HI_OUT_XOR; /*!< Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT + ^= wdata` */ + __IOM uint32_t GPIO_OE; /*!< GPIO0...31 output enable */ + __IOM uint32_t GPIO_HI_OE; /*!< Output enable value for GPIO32...47, QSPI IOs and USB pins. + Write output enable (1/0 -> output/input). Reading back + gives the last value written. If core 0 and core 1 both + write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR + alias), the result is as though the write from core 0 took + place first, and the write from core 1 was then applied + to that intermediate result. In the Non-secure SIO, Secure-only + GPIOs (as per ACCESSCTRL) ignore writes, and their output + status reads back as zero. This is also true for SET/CLR/XOR + aliases of this register. */ + __IOM uint32_t GPIO_OE_SET; /*!< GPIO0...31 output enable set */ + __IOM uint32_t GPIO_HI_OE_SET; /*!< Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform + an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` */ + __IOM uint32_t GPIO_OE_CLR; /*!< GPIO0...31 output enable clear */ + __IOM uint32_t GPIO_HI_OE_CLR; /*!< Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE + &= ~wdata` */ + __IOM uint32_t GPIO_OE_XOR; /*!< GPIO0...31 output enable XOR */ + __IOM uint32_t GPIO_HI_OE_XOR; /*!< Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform + an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= + wdata` */ + __IOM uint32_t FIFO_ST; /*!< Status register for inter-core FIFOs (mailboxes). There is one + FIFO in the core 0 -> core 1 direction, and one core 1 + -> core 0. Both are 32 bits wide and 8 words deep. Core + 0 can see the read side of the 1->0 FIFO (RX), and the + write side of 0->1 FIFO (TX). Core 1 can see the read side + of the 0->1 FIFO (RX), and the write side of 1->0 FIFO + (TX). The SIO IRQ for each core is the logical OR of the + VLD, WOF and ROE fields of its FIFO_ST register. */ + __IOM uint32_t FIFO_WR; /*!< Write access to this core's TX FIFO */ + __IOM uint32_t FIFO_RD; /*!< Read access to this core's RX FIFO */ + __IOM uint32_t SPINLOCK_ST; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks + (1=locked). Mainly intended for debugging. */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t INTERP0_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP0_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP0_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP0_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP0_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP0_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP0_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP0_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP0_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t INTERP1_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP1_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP1_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP1_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP1_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP1_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP1_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP1_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP1_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t SPINLOCK0; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK1; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK2; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK3; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK4; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK5; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK6; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK7; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK8; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK9; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK10; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK11; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK12; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK13; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK14; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK15; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK16; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK17; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK18; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK19; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK20; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK21; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK22; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK23; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK24; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK25; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK26; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK27; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK28; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK29; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK30; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK31; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t DOORBELL_OUT_SET; /*!< Trigger a doorbell interrupt on the opposite core. Write 1 to + a bit to set the corresponding bit in DOORBELL_IN on the + opposite core. This raises the opposite core's doorbell + interrupt. Read to get the status of the doorbells currently + asserted on the opposite core. This is equivalent to that + core reading its own DOORBELL_IN status. */ + __IOM uint32_t DOORBELL_OUT_CLR; /*!< Clear doorbells which have been posted to the opposite core. + This register is intended for debugging and initialisation + purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears + the corresponding bit in DOORBELL_IN on the opposite core. + Clearing all bits will cause that core's doorbell interrupt + to deassert. Since the usual order of events is for software + to send events using DOORBELL_OUT_SET, and acknowledge + incoming events by writing to DOORBELL_IN_CLR, this register + should be used with caution to avoid race conditions. Reading + returns the status of the doorbells currently asserted + on the other core, i.e. is equivalent to that core reading + its own DOORBELL_IN status. */ + __IOM uint32_t DOORBELL_IN_SET; /*!< Write 1s to trigger doorbell interrupts on this core. Read to + get status of doorbells currently asserted on this core. */ + __IOM uint32_t DOORBELL_IN_CLR; /*!< Check and acknowledge doorbells posted to this core. This core's + doorbell interrupt is asserted when any bit in this register + is 1. Write 1 to each bit to clear that bit. The doorbell + interrupt deasserts once all bits are cleared. Read to + get status of doorbells currently asserted on this core. */ + __IOM uint32_t PERI_NONSEC; /*!< Detach certain core-local peripherals from Secure SIO, and attach + them to Non-secure SIO, so that Non-secure software can + use them. Attempting to access one of these peripherals + from the Secure SIO when it is attached to the Non-secure + SIO, or vice versa, will generate a bus error. This register + is per-core, and is only present on the Secure SIO. Most + SIO hardware is duplicated across the Secure and Non-secure + SIO, so is not listed in this register. */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t RISCV_SOFTIRQ; /*!< Control the assertion of the standard software interrupt (MIP.MSIP) + on the RISC-V cores. Unlike the RISC-V timer, this interrupt + is not routed to a normal system-level interrupt line, + so can not be used by the Arm cores. It is safe for both + cores to write to this register on the same cycle. The + set/clear effect is accumulated across both cores, and + then applied. If a flag is both set and cleared on the + same cycle, only the set takes effect. */ + __IOM uint32_t MTIME_CTRL; /*!< Control register for the RISC-V 64-bit Machine-mode timer. This + timer is only present in the Secure SIO, so is only accessible + to an Arm core in Secure mode or a RISC-V core in Machine + mode. Note whilst this timer follows the RISC-V privileged + specification, it is equally usable by the Arm cores. The + interrupts are routed to normal system-level interrupt + lines as well as to the MIP.MTIP inputs on the RISC-V cores. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t MTIME; /*!< Read/write access to the high half of RISC-V Machine-mode timer. + This register is shared between both cores. If both cores + write on the same cycle, core 1 takes precedence. */ + __IOM uint32_t MTIMEH; /*!< Read/write access to the high half of RISC-V Machine-mode timer. + This register is shared between both cores. If both cores + write on the same cycle, core 1 takes precedence. */ + __IOM uint32_t MTIMECMP; /*!< Low half of RISC-V Machine-mode timer comparator. This register + is core-local, i.e., each core gets a copy of this register, + with the comparison result routed to its own interrupt + line. The timer interrupt is asserted whenever MTIME is + greater than or equal to MTIMECMP. This comparison is unsigned, + and performed on the full 64-bit values. */ + __IOM uint32_t MTIMECMPH; /*!< High half of RISC-V Machine-mode timer comparator. This register + is core-local. The timer interrupt is asserted whenever + MTIME is greater than or equal to MTIMECMP. This comparison + is unsigned, and performed on the full 64-bit values. */ + __IOM uint32_t TMDS_CTRL; /*!< Control register for TMDS encoder. */ + __IOM uint32_t TMDS_WDATA; /*!< Write-only access to the TMDS colour data register. */ + __IOM uint32_t TMDS_PEEK_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed + into a 32-bit value (3x10-bit symbols). The PEEK alias + does not shift the colour register when read, but still + advances the running DC balance state of each encoder. + This is useful for pixel doubling. */ + __IOM uint32_t TMDS_POP_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed + into a 32-bit value. The packing is 5 chunks of 3 lanes + times 2 bits (30 bits total). Each chunk contains two bits + of a TMDS symbol per lane. This format is intended for + shifting out with the HSTX peripheral on RP2350. The POP + alias shifts the colour register when read, as well as + advancing the running DC balance state of each encoder. */ + __IOM uint32_t TMDS_PEEK_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 0 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + __IOM uint32_t TMDS_POP_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ + __IOM uint32_t TMDS_PEEK_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 1 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + __IOM uint32_t TMDS_POP_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ + __IOM uint32_t TMDS_PEEK_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 2 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + __IOM uint32_t TMDS_POP_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ +} SIO_Type; /*!< Size = 488 (0x1e8) */ + + + +/* =========================================================================================================================== */ +/* ================ BOOTRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Additional registers mapped adjacent to the bootram, for use by the bootrom. (BOOTRAM) + */ + +typedef struct { /*!< BOOTRAM Structure */ + __IM uint32_t RESERVED[512]; + __IOM uint32_t WRITE_ONCE0; /*!< This registers always ORs writes into its current contents. + Once a bit is set, it can only be cleared by a reset. */ + __IOM uint32_t WRITE_ONCE1; /*!< This registers always ORs writes into its current contents. + Once a bit is set, it can only be cleared by a reset. */ + __IOM uint32_t BOOTLOCK_STAT; /*!< Bootlock status register. 1=unclaimed, 0=claimed. These locks + function identically to the SIO spinlocks, but are reserved + for bootrom use. */ + __IOM uint32_t BOOTLOCK0; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK1; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK2; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK3; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK4; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK5; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK6; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK7; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ +} BOOTRAM_Type; /*!< Size = 2092 (0x82c) */ + + + +/* =========================================================================================================================== */ +/* ================ CORESIGHT_TRACE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Coresight block - RP specific registers (CORESIGHT_TRACE) + */ + +typedef struct { /*!< CORESIGHT_TRACE Structure */ + __IOM uint32_t CTRL_STATUS; /*!< Control and status register */ + __IOM uint32_t TRACE_CAPTURE_FIFO; /*!< FIFO for trace data captured from the TPIU */ +} CORESIGHT_TRACE_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB FS/LS controller device registers (USB) + */ + +typedef struct { /*!< USB Structure */ + __IOM uint32_t ADDR_ENDP; /*!< Device address and endpoint control */ + __IOM uint32_t ADDR_ENDP1; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP2; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP3; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP4; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP5; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP6; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP7; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP8; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP9; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP10; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP11; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP12; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP13; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP14; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP15; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ + __IOM uint32_t MAIN_CTRL; /*!< Main control register */ + __IOM uint32_t SOF_WR; /*!< Set the SOF (Start of Frame) frame number in the host controller. + The SOF packet is sent every 1ms and the host will increment + the frame number by 1 each time. */ + __IOM uint32_t SOF_RD; /*!< Read the last SOF (Start of Frame) frame number seen. In device + mode the last SOF received from the host. In host mode + the last SOF sent by the host. */ + __IOM uint32_t SIE_CTRL; /*!< SIE control register */ + __IOM uint32_t SIE_STATUS; /*!< SIE status register */ + __IOM uint32_t INT_EP_CTRL; /*!< interrupt endpoint control register */ + __IOM uint32_t BUFF_STATUS; /*!< Buffer status register. A bit set here indicates that a buffer + has completed on the endpoint (if the buffer interrupt + is enabled). It is possible for 2 buffers to be completed, + so clearing the buffer status bit may instantly re set + it on the next clock cycle. */ + __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< Which of the double buffers should be handled. Only valid if + using an interrupt per buffer (i.e. not per 2 buffers). + Not valid for host interrupt endpoint polling because they + are only single buffered. */ + __IOM uint32_t EP_ABORT; /*!< Device only: Can be set to ignore the buffer control register + for this endpoint in case you would like to revoke a buffer. + A NAK will be sent for every access to the endpoint until + this bit is cleared. A corresponding bit in `EP_ABORT_DONE` + is set when it is safe to modify the buffer control register. */ + __IOM uint32_t EP_ABORT_DONE; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an + endpoint is idle so the programmer knows it is safe to + modify the buffer control register. */ + __IOM uint32_t EP_STALL_ARM; /*!< Device: this bit must be set in conjunction with the `STALL` + bit in the buffer control register to send a STALL on EP0. + The device controller clears these bits when a SETUP packet + is received because the USB spec requires that a STALL + condition is cleared when a SETUP packet is received. */ + __IOM uint32_t NAK_POLL; /*!< Used by the host controller. Sets the wait time in microseconds + before trying again if the device replies with a NAK. */ + __IOM uint32_t EP_STATUS_STALL_NAK; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` + bits are set. For EP0 this comes from `SIE_CTRL`. For all + other endpoints it comes from the endpoint control register. */ + __IOM uint32_t USB_MUXING; /*!< Where to connect the USB controller. Should be to_phy by default. */ + __IOM uint32_t USB_PWR; /*!< Overrides for the power signals in the event that the VBUS signals + are not hooked up to GPIO. Set the value of the override + and then the override enable to switch over to the override + value. */ + __IOM uint32_t USBPHY_DIRECT; /*!< This register allows for direct control of the USB phy. Use + in conjunction with usbphy_direct_override register to + enable each override bit. */ + __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< Override enable for each control in usbphy_direct */ + __IOM uint32_t USBPHY_TRIM; /*!< Used to adjust trim values of USB phy pull down resistors. */ + __IOM uint32_t LINESTATE_TUNING; /*!< Used for debug only. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ + __IM uint32_t RESERVED[25]; + __IOM uint32_t SOF_TIMESTAMP_RAW; /*!< Device only. Raw value of free-running PHY clock counter @48MHz. + Used to calculate time between SOF events. */ + __IOM uint32_t SOF_TIMESTAMP_LAST; /*!< Device only. Value of free-running PHY clock counter @48MHz + when last SOF event occurred. */ + __IOM uint32_t SM_STATE; /*!< SM_STATE */ + __IOM uint32_t EP_TX_ERROR; /*!< TX error count for each endpoint. Write to each field to reset + the counter to 0. */ + __IOM uint32_t EP_RX_ERROR; /*!< RX error count for each endpoint. Write to each field to reset + the counter to 0. */ + __IOM uint32_t DEV_SM_WATCHDOG; /*!< Watchdog that forces the device state machine to idle and raises + an interrupt if the device stays in a state that isn't + idle for the configured limit. The counter is reset on + every state transition. Set limit while enable is low and + then set the enable. */ +} USB_Type; /*!< Size = 280 (0x118) */ + + + +/* =========================================================================================================================== */ +/* ================ TRNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone RNG register block (TRNG) + */ + +typedef struct { /*!< TRNG Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t RNG_IMR; /*!< Interrupt masking. */ + __IOM uint32_t RNG_ISR; /*!< RNG status register. If corresponding RNG_IMR bit is unmasked, + an interrupt will be generated. */ + __IOM uint32_t RNG_ICR; /*!< Interrupt/status bit clear Register. */ + __IOM uint32_t TRNG_CONFIG; /*!< Selecting the inverter-chain length. */ + __IOM uint32_t TRNG_VALID; /*!< 192 bit collection indication. */ + __IOM uint32_t EHR_DATA0; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA1; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA2; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA3; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA4; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA5; /*!< RNG collected bits. */ + __IOM uint32_t RND_SOURCE_ENABLE; /*!< Enable signal for the random source. */ + __IOM uint32_t SAMPLE_CNT1; /*!< Counts clocks between sampling of random bit. */ + __IOM uint32_t AUTOCORR_STATISTIC; /*!< Statistic about Autocorrelation test activations. */ + __IOM uint32_t TRNG_DEBUG_CONTROL; /*!< Debug register. */ + __IM uint32_t RESERVED1; + __IOM uint32_t TRNG_SW_RESET; /*!< Generate internal SW reset within the RNG block. */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t RNG_DEBUG_EN_INPUT; /*!< Enable the RNG debug mode */ + __IOM uint32_t TRNG_BUSY; /*!< RNG Busy indication. */ + __IOM uint32_t RST_BITS_COUNTER; /*!< Reset the counter of collected bits in the RNG. */ + __IOM uint32_t RNG_VERSION; /*!< Displays the version settings of the TRNG. */ + __IM uint32_t RESERVED3[7]; + __IOM uint32_t RNG_BIST_CNTR_0; /*!< Collected BIST results. */ + __IOM uint32_t RNG_BIST_CNTR_1; /*!< Collected BIST results. */ + __IOM uint32_t RNG_BIST_CNTR_2; /*!< Collected BIST results. */ +} TRNG_Type; /*!< Size = 492 (0x1ec) */ + + + +/* =========================================================================================================================== */ +/* ================ GLITCH_DETECTOR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Glitch detector controls (GLITCH_DETECTOR) + */ + +typedef struct { /*!< GLITCH_DETECTOR Structure */ + __IOM uint32_t ARM; /*!< Forcibly arm the glitch detectors, if they are not already armed + by OTP. When armed, any individual detector trigger will + cause a restart of the switched core power domain's power-on + reset state machine. Glitch detector triggers are recorded + accumulatively in TRIG_STATUS. If the system is reset by + a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + This register is Secure read/write only. */ + __IOM uint32_t DISARM; /*!< DISARM */ + __IOM uint32_t SENSITIVITY; /*!< Adjust the sensitivity of glitch detectors to values other than + their OTP-provided defaults. This register is Secure read/write + only. */ + __IOM uint32_t LOCK; /*!< LOCK */ + __IOM uint32_t TRIG_STATUS; /*!< Set when a detector output triggers. Write-1-clear. (May immediately + return high if the detector remains in a failed state. + Detectors can only be cleared by a full reset of the switched + core power domain.) This register is Secure read/write + only. */ + __IOM uint32_t TRIG_FORCE; /*!< Simulate the firing of one or more detectors. Writing ones to + this register will set the matching bits in STATUS_TRIG. + If the glitch detectors are currently armed, writing ones + will also immediately reset the switched core power domain, + and set the reset reason latches in POWMAN_CHIP_RESET to + indicate a glitch detector resets. This register is Secure + read/write only. */ +} GLITCH_DETECTOR_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SNPS OTP control IF (SBPI and RPi wrapper control) (OTP) + */ + +typedef struct { /*!< OTP Structure */ + __IOM uint32_t SW_LOCK0; /*!< Software lock register for page 0. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK1; /*!< Software lock register for page 1. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK2; /*!< Software lock register for page 2. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK3; /*!< Software lock register for page 3. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK4; /*!< Software lock register for page 4. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK5; /*!< Software lock register for page 5. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK6; /*!< Software lock register for page 6. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK7; /*!< Software lock register for page 7. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK8; /*!< Software lock register for page 8. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK9; /*!< Software lock register for page 9. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK10; /*!< Software lock register for page 10. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK11; /*!< Software lock register for page 11. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK12; /*!< Software lock register for page 12. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK13; /*!< Software lock register for page 13. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK14; /*!< Software lock register for page 14. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK15; /*!< Software lock register for page 15. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK16; /*!< Software lock register for page 16. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK17; /*!< Software lock register for page 17. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK18; /*!< Software lock register for page 18. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK19; /*!< Software lock register for page 19. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK20; /*!< Software lock register for page 20. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK21; /*!< Software lock register for page 21. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK22; /*!< Software lock register for page 22. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK23; /*!< Software lock register for page 23. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK24; /*!< Software lock register for page 24. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK25; /*!< Software lock register for page 25. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK26; /*!< Software lock register for page 26. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK27; /*!< Software lock register for page 27. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK28; /*!< Software lock register for page 28. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK29; /*!< Software lock register for page 29. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK30; /*!< Software lock register for page 30. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK31; /*!< Software lock register for page 31. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK32; /*!< Software lock register for page 32. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK33; /*!< Software lock register for page 33. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK34; /*!< Software lock register for page 34. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK35; /*!< Software lock register for page 35. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK36; /*!< Software lock register for page 36. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK37; /*!< Software lock register for page 37. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK38; /*!< Software lock register for page 38. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK39; /*!< Software lock register for page 39. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK40; /*!< Software lock register for page 40. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK41; /*!< Software lock register for page 41. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK42; /*!< Software lock register for page 42. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK43; /*!< Software lock register for page 43. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK44; /*!< Software lock register for page 44. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK45; /*!< Software lock register for page 45. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK46; /*!< Software lock register for page 46. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK47; /*!< Software lock register for page 47. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK48; /*!< Software lock register for page 48. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK49; /*!< Software lock register for page 49. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK50; /*!< Software lock register for page 50. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK51; /*!< Software lock register for page 51. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK52; /*!< Software lock register for page 52. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK53; /*!< Software lock register for page 53. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK54; /*!< Software lock register for page 54. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK55; /*!< Software lock register for page 55. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK56; /*!< Software lock register for page 56. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK57; /*!< Software lock register for page 57. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK58; /*!< Software lock register for page 58. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK59; /*!< Software lock register for page 59. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK60; /*!< Software lock register for page 60. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK61; /*!< Software lock register for page 61. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK62; /*!< Software lock register for page 62. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK63; /*!< Software lock register for page 63. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SBPI_INSTR; /*!< Dispatch instructions to the SBPI interface, used for programming + the OTP fuses. */ + __IOM uint32_t SBPI_WDATA_0; /*!< SBPI write payload bytes 3..0 */ + __IOM uint32_t SBPI_WDATA_1; /*!< SBPI write payload bytes 7..4 */ + __IOM uint32_t SBPI_WDATA_2; /*!< SBPI write payload bytes 11..8 */ + __IOM uint32_t SBPI_WDATA_3; /*!< SBPI write payload bytes 15..12 */ + __IOM uint32_t SBPI_RDATA_0; /*!< Read payload bytes 3..0. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_RDATA_1; /*!< Read payload bytes 7..4. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_RDATA_2; /*!< Read payload bytes 11..8. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_RDATA_3; /*!< Read payload bytes 15..12. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_STATUS; /*!< SBPI_STATUS */ + __IOM uint32_t USR; /*!< Controls for APB data read interface (USER interface) */ + __IOM uint32_t DBG; /*!< Debug for OTP power-on state machine */ + __IM uint32_t RESERVED; + __IOM uint32_t BIST; /*!< During BIST, count address locations that have at least one + leaky bit */ + __IOM uint32_t CRT_KEY_W0; /*!< Word 0 (bits 31..0) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRT_KEY_W1; /*!< Word 1 (bits 63..32) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRT_KEY_W2; /*!< Word 2 (bits 95..64) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRT_KEY_W3; /*!< Word 3 (bits 127..96) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRITICAL; /*!< Quickly check values of critical flags read during boot up */ + __IOM uint32_t KEY_VALID; /*!< Which keys were valid (enrolled) at boot time */ + __IOM uint32_t DEBUGEN; /*!< Enable a debug feature that has been disabled. Debug features + are disabled if one of the relevant critical boot flags + is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), + OR if a debug key is marked valid in OTP, and the matching + key value has not been supplied over SWD. Specifically: + - The DEBUG_DISABLE flag disables all debug features. This + can be fully overridden by setting all bits of this register. + - The SECURE_DEBUG_DISABLE flag disables secure processor + debug. This can be fully overridden by setting the PROC0_SECURE + and PROC1_SECURE bits of this register. - If a single debug + key has been registered, and no matching key value has + been supplied over SWD, then all debug features are disabled. + This can be fully overridden by setting all bits of this + register. - If both debug keys have been registered, and + the Non-secure key's value (key 6) has been supplied over + SWD, secure processor debug is disabled. This can be fully + overridden by setting the PROC0_SECURE and PROC1_SECURE + bits of this register. - If both debug keys have been registered, + and the Secure key's value (key 5) has been supplied over + SWD, then no debug features are disabled by the key mechanism. + However, note that in this case debug features may still + be disabled by the critical boot flags. */ + __IOM uint32_t DEBUGEN_LOCK; /*!< Write 1s to lock corresponding bits in DEBUGEN. This register + is reset by the processor cold reset. */ + __IOM uint32_t ARCHSEL; /*!< Architecture select (Arm/RISC-V). The default and allowable + values of this register are constrained by the critical + boot flags. This register is reset by the earliest reset + in the switched core power domain (before a processor cold + reset). Cores sample their architecture select signal on + a warm reset. The source of the warm reset could be the + system power-up state machine, the watchdog timer, Arm + SYSRESETREQ or from RISC-V hartresetreq. Note that when + an Arm core is deselected, its cold reset domain is also + held in reset, since in particular the SYSRESETREQ bit + becomes inaccessible once the core is deselected. Note + also the RISC-V cores do not have a cold reset domain, + since their corresponding controls are located in the Debug + Module. */ + __IOM uint32_t ARCHSEL_STATUS; /*!< Get the current architecture select state of each core. Cores + sample the current value of the ARCHSEL register when their + warm reset is released, at which point the corresponding + bit in this register will also update. */ + __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore scratch register boot vectors (both + power manager and watchdog) on the next power up. If an + early boot stage has soft-locked some OTP pages in order + to protect their contents from later stages, there is a + risk that Secure code running at a later stage can unlock + the pages by performing a watchdog reset that resets the + OTP. This register can be used to ensure that the bootloader + runs as normal on the next power up, preventing Secure + code at a later stage from accessing OTP in its unlocked + state. Should be used in conjunction with the power manager + BOOTDIS register. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} OTP_Type; /*!< Size = 372 (0x174) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Predefined OTP data layout for RP2350 (OTP_DATA) + */ + +typedef struct { /*!< OTP_DATA Structure */ + __IOM uint16_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain + a 64-bit random identifier for this chip, which can be + read from the USB bootloader PICOBOOT interface or from + the get_sys_info ROM API. The number of random bits makes + the occurrence of twins exceedingly unlikely: for example, + a fleet of a hundred million devices has a 99.97% probability + of no twinned IDs. This is estimated to be lower than the + occurrence of process errors in the assignment of sequential + random IDs, and for practical purposes CHIPID may be treated + as unique. */ + __IOM uint16_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ + __IOM uint16_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ + __IOM uint16_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ + __IOM uint16_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + rows form a 128-bit random number generated during device + test. This ID is not exposed through the USB PICOBOOT GET_INFO + command or the ROM `get_sys_info()` API. However note that + the USB PICOBOOT OTP access point can read the entirety + of page 0, so this value is not meaningfully private unless + the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO + T_IFC flag in BOOT_FLAGS0. */ + __IOM uint16_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ + __IOM uint16_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ + __IOM uint16_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ + __IOM uint16_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ + __IOM uint16_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ + __IOM uint16_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ + __IOM uint16_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ + __IM uint16_t RESERVED[4]; + __IOM uint16_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing + (ECC) This is measured at 1.1 V, at room temperature, with + the ROSC configuration registers in their reset state. */ + __IOM uint16_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing + (ECC) This is measured at 1.1V, at room temperature, with + the LPOSC trim register in its reset state. */ + __IM uint16_t RESERVED1[6]; + __IOM uint16_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the + QFN80 package, and 30 in the QFN60 package. (ECC) */ + __IM uint16_t RESERVED2[29]; + __IOM uint16_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + 0x4c11db7, input reflected, output reflected, seed all-ones, + final XOR all-ones) (ECC) */ + __IOM uint16_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ + __IM uint16_t RESERVED3[28]; + __IOM uint16_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed + to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ + __IOM uint16_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of + flash (the default size is 4096 bytes) (ECC) Enabled by + the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, + the size is 4096 * (value + 1) */ + __IOM uint16_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ + __IOM uint16_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should + be configured to produce an exact 48 MHz based on the crystal + oscillator frequency. User mode software may also use this + value to calculate the expected crystal frequency based + on an assumed 48 MHz PLL output. If no configuration is + given, the crystal is assumed to be 12 MHz. The PLL frequency + can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + frequency can be calculated as: XOSC frequency = 48 MHz + x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the + +1 on REFDIV is because the value stored in this OTP location + is the actual divisor value minus one.) Used if and only + if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + That bit should be set only after this row and BOOTSEL_XOSC_CFG + are both correctly programmed. */ + __IOM uint16_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. + (ECC) These values may also be used by user code configuring + the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL + _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set + only after this row and BOOTSEL_PLL_CFG are both correctly + programmed. */ + __IM uint16_t RESERVED4[3]; + __IOM uint16_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) + The table has 16 rows, each of which are also ECC and marked + valid by the corresponding valid bit in USB_BOOT_FLAGS + (ECC). The entries are either _VALUEs where the 16 bit + value is used as is, or _STRDEFs which acts as a pointers + to a string value. The value stored in a _STRDEF is two + separate bytes: The low seven bits of the first (LSB) byte + indicates the number of characters in the string, and the + top bit of the first (LSB) byte if set to indicate that + each character in the string is two bytes (Unicode) versus + one byte if unset. The second (MSB) byte represents the + location of the string data, and is encoded as the number + of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of + the start of the string is USB_WHITE_LABEL_ADDR value + + msb_byte. In each case, the corresponding valid bit enables + replacing the default value for the corresponding item + provided by the boot rom. Note that Unicode _STRDEFs are + only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST + DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values + will be ignored if specified for other fields, and non-unicode + values for these three items will be converted to Unicode + characters by setting the upper 8 bits to zero. Note that + if the USB_WHITE_LABEL structure or the corresponding strings + are not readable by BOOTSEL mode based on OTP permissions, + or if alignment requirements are not met, then the corresponding + default values are used. The index values indicate where + each field is located (row USB_WHITE_LABEL_ADDR value + + index): */ + __IM uint16_t RESERVED5; + __IOM uint16_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + the bootrom will load from this location into SRAM and + then directly enter the loaded image. Note that the image + must be signed if SECURE_BOOT_ENABLE is set. The image + itself is assumed to be ECC-protected. This must be an + even number. Equivalently, the OTP boot image must start + at a word-aligned location in the ECC read data address + window. */ + __IOM uint16_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must + be even. The total image size must be a multiple of 4 bytes + (32 bits). */ + __IOM uint16_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IOM uint16_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IM uint16_t RESERVED6[30]; + __IOM uint16_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ + __IM uint16_t RESERVED7[3720]; + __IOM uint16_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ +} OTP_DATA_Type; /*!< Size = 7920 (0x1ef0) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA_RAW ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Predefined OTP data layout for RP2350 (OTP_DATA_RAW) + */ + +typedef struct { /*!< OTP_DATA_RAW Structure */ + __IOM uint32_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain + a 64-bit random identifier for this chip, which can be + read from the USB bootloader PICOBOOT interface or from + the get_sys_info ROM API. The number of random bits makes + the occurrence of twins exceedingly unlikely: for example, + a fleet of a hundred million devices has a 99.97% probability + of no twinned IDs. This is estimated to be lower than the + occurrence of process errors in the assignment of sequential + random IDs, and for practical purposes CHIPID may be treated + as unique. */ + __IOM uint32_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ + __IOM uint32_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ + __IOM uint32_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ + __IOM uint32_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + rows form a 128-bit random number generated during device + test. This ID is not exposed through the USB PICOBOOT GET_INFO + command or the ROM `get_sys_info()` API. However note that + the USB PICOBOOT OTP access point can read the entirety + of page 0, so this value is not meaningfully private unless + the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO + T_IFC flag in BOOT_FLAGS0. */ + __IOM uint32_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ + __IOM uint32_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ + __IOM uint32_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ + __IOM uint32_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ + __IOM uint32_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ + __IOM uint32_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ + __IOM uint32_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing + (ECC) This is measured at 1.1 V, at room temperature, with + the ROSC configuration registers in their reset state. */ + __IOM uint32_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing + (ECC) This is measured at 1.1V, at room temperature, with + the LPOSC trim register in its reset state. */ + __IM uint32_t RESERVED1[6]; + __IOM uint32_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the + QFN80 package, and 30 in the QFN60 package. (ECC) */ + __IM uint32_t RESERVED2[29]; + __IOM uint32_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + 0x4c11db7, input reflected, output reflected, seed all-ones, + final XOR all-ones) (ECC) */ + __IOM uint32_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ + __IOM uint32_t CRIT0; /*!< Page 0 critical boot flags (RBIT-8) */ + __IOM uint32_t CRIT0_R1; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R2; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R3; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R4; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R5; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R6; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R7; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT1; /*!< Page 1 critical boot flags (RBIT-8) */ + __IOM uint32_t CRIT1_R1; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R2; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R3; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R4; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R5; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R6; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R7; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t BOOT_FLAGS0; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + always supersede enables. Enables are provided where there + are other configurations in OTP that must be valid. (RBIT-3) */ + __IOM uint32_t BOOT_FLAGS0_R1; /*!< Redundant copy of BOOT_FLAGS0 */ + __IOM uint32_t BOOT_FLAGS0_R2; /*!< Redundant copy of BOOT_FLAGS0 */ + __IOM uint32_t BOOT_FLAGS1; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + always supersede enables. Enables are provided where there + are other configurations in OTP that must be valid. (RBIT-3) */ + __IOM uint32_t BOOT_FLAGS1_R1; /*!< Redundant copy of BOOT_FLAGS1 */ + __IOM uint32_t BOOT_FLAGS1_R2; /*!< Redundant copy of BOOT_FLAGS1 */ + __IOM uint32_t DEFAULT_BOOT_VERSION0; /*!< Default boot version thermometer counter, bits 23:0 (RBIT-3) */ + __IOM uint32_t DEFAULT_BOOT_VERSION0_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ + __IOM uint32_t DEFAULT_BOOT_VERSION0_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ + __IOM uint32_t DEFAULT_BOOT_VERSION1; /*!< Default boot version thermometer counter, bits 47:24 (RBIT-3) */ + __IOM uint32_t DEFAULT_BOOT_VERSION1_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ + __IOM uint32_t DEFAULT_BOOT_VERSION1_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ + __IOM uint32_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed + to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ + __IOM uint32_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of + flash (the default size is 4096 bytes) (ECC) Enabled by + the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, + the size is 4096 * (value + 1) */ + __IOM uint32_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ + __IOM uint32_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should + be configured to produce an exact 48 MHz based on the crystal + oscillator frequency. User mode software may also use this + value to calculate the expected crystal frequency based + on an assumed 48 MHz PLL output. If no configuration is + given, the crystal is assumed to be 12 MHz. The PLL frequency + can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + frequency can be calculated as: XOSC frequency = 48 MHz + x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the + +1 on REFDIV is because the value stored in this OTP location + is the actual divisor value minus one.) Used if and only + if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + That bit should be set only after this row and BOOTSEL_XOSC_CFG + are both correctly programmed. */ + __IOM uint32_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. + (ECC) These values may also be used by user code configuring + the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL + _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set + only after this row and BOOTSEL_PLL_CFG are both correctly + programmed. */ + __IOM uint32_t USB_BOOT_FLAGS; /*!< USB boot specific feature flags (RBIT-3) */ + __IOM uint32_t USB_BOOT_FLAGS_R1; /*!< Redundant copy of USB_BOOT_FLAGS */ + __IOM uint32_t USB_BOOT_FLAGS_R2; /*!< Redundant copy of USB_BOOT_FLAGS */ + __IOM uint32_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) + The table has 16 rows, each of which are also ECC and marked + valid by the corresponding valid bit in USB_BOOT_FLAGS + (ECC). The entries are either _VALUEs where the 16 bit + value is used as is, or _STRDEFs which acts as a pointers + to a string value. The value stored in a _STRDEF is two + separate bytes: The low seven bits of the first (LSB) byte + indicates the number of characters in the string, and the + top bit of the first (LSB) byte if set to indicate that + each character in the string is two bytes (Unicode) versus + one byte if unset. The second (MSB) byte represents the + location of the string data, and is encoded as the number + of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of + the start of the string is USB_WHITE_LABEL_ADDR value + + msb_byte. In each case, the corresponding valid bit enables + replacing the default value for the corresponding item + provided by the boot rom. Note that Unicode _STRDEFs are + only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST + DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values + will be ignored if specified for other fields, and non-unicode + values for these three items will be converted to Unicode + characters by setting the upper 8 bits to zero. Note that + if the USB_WHITE_LABEL structure or the corresponding strings + are not readable by BOOTSEL mode based on OTP permissions, + or if alignment requirements are not met, then the corresponding + default values are used. The index values indicate where + each field is located (row USB_WHITE_LABEL_ADDR value + + index): */ + __IM uint32_t RESERVED3; + __IOM uint32_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + the bootrom will load from this location into SRAM and + then directly enter the loaded image. Note that the image + must be signed if SECURE_BOOT_ENABLE is set. The image + itself is assumed to be ECC-protected. This must be an + even number. Equivalently, the OTP boot image must start + at a word-aligned location in the ECC read data address + window. */ + __IOM uint32_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must + be even. The total image size must be a multiple of 4 bytes + (32 bits). */ + __IOM uint32_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IOM uint32_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IM uint32_t RESERVED4[30]; + __IOM uint32_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ + __IM uint32_t RESERVED5[3720]; + __IOM uint32_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ + __IM uint32_t RESERVED6; + __IOM uint32_t KEY1_VALID; /*!< Valid flag for key 1. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY2_VALID; /*!< Valid flag for key 2. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY3_VALID; /*!< Valid flag for key 3. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY4_VALID; /*!< Valid flag for key 4. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY5_VALID; /*!< Valid flag for key 5. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY6_VALID; /*!< Valid flag for key 6. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IM uint32_t RESERVED7; + __IOM uint32_t PAGE0_LOCK0; /*!< Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE0_LOCK1; /*!< Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE1_LOCK0; /*!< Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE1_LOCK1; /*!< Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE2_LOCK0; /*!< Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE2_LOCK1; /*!< Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE3_LOCK0; /*!< Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE3_LOCK1; /*!< Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE4_LOCK0; /*!< Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE4_LOCK1; /*!< Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE5_LOCK0; /*!< Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE5_LOCK1; /*!< Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE6_LOCK0; /*!< Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE6_LOCK1; /*!< Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE7_LOCK0; /*!< Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE7_LOCK1; /*!< Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE8_LOCK0; /*!< Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE8_LOCK1; /*!< Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE9_LOCK0; /*!< Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE9_LOCK1; /*!< Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE10_LOCK0; /*!< Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE10_LOCK1; /*!< Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE11_LOCK0; /*!< Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE11_LOCK1; /*!< Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE12_LOCK0; /*!< Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE12_LOCK1; /*!< Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE13_LOCK0; /*!< Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE13_LOCK1; /*!< Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE14_LOCK0; /*!< Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE14_LOCK1; /*!< Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE15_LOCK0; /*!< Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE15_LOCK1; /*!< Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE16_LOCK0; /*!< Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE16_LOCK1; /*!< Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE17_LOCK0; /*!< Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE17_LOCK1; /*!< Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE18_LOCK0; /*!< Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE18_LOCK1; /*!< Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE19_LOCK0; /*!< Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE19_LOCK1; /*!< Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE20_LOCK0; /*!< Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE20_LOCK1; /*!< Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE21_LOCK0; /*!< Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE21_LOCK1; /*!< Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE22_LOCK0; /*!< Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE22_LOCK1; /*!< Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE23_LOCK0; /*!< Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE23_LOCK1; /*!< Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE24_LOCK0; /*!< Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE24_LOCK1; /*!< Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE25_LOCK0; /*!< Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE25_LOCK1; /*!< Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE26_LOCK0; /*!< Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE26_LOCK1; /*!< Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE27_LOCK0; /*!< Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE27_LOCK1; /*!< Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE28_LOCK0; /*!< Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE28_LOCK1; /*!< Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE29_LOCK0; /*!< Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE29_LOCK1; /*!< Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE30_LOCK0; /*!< Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE30_LOCK1; /*!< Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE31_LOCK0; /*!< Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE31_LOCK1; /*!< Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE32_LOCK0; /*!< Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE32_LOCK1; /*!< Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE33_LOCK0; /*!< Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE33_LOCK1; /*!< Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE34_LOCK0; /*!< Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE34_LOCK1; /*!< Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE35_LOCK0; /*!< Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE35_LOCK1; /*!< Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE36_LOCK0; /*!< Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE36_LOCK1; /*!< Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE37_LOCK0; /*!< Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE37_LOCK1; /*!< Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE38_LOCK0; /*!< Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE38_LOCK1; /*!< Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE39_LOCK0; /*!< Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE39_LOCK1; /*!< Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE40_LOCK0; /*!< Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE40_LOCK1; /*!< Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE41_LOCK0; /*!< Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE41_LOCK1; /*!< Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE42_LOCK0; /*!< Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE42_LOCK1; /*!< Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE43_LOCK0; /*!< Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE43_LOCK1; /*!< Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE44_LOCK0; /*!< Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE44_LOCK1; /*!< Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE45_LOCK0; /*!< Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE45_LOCK1; /*!< Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE46_LOCK0; /*!< Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE46_LOCK1; /*!< Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE47_LOCK0; /*!< Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE47_LOCK1; /*!< Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE48_LOCK0; /*!< Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE48_LOCK1; /*!< Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE49_LOCK0; /*!< Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE49_LOCK1; /*!< Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE50_LOCK0; /*!< Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE50_LOCK1; /*!< Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE51_LOCK0; /*!< Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE51_LOCK1; /*!< Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE52_LOCK0; /*!< Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE52_LOCK1; /*!< Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE53_LOCK0; /*!< Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE53_LOCK1; /*!< Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE54_LOCK0; /*!< Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE54_LOCK1; /*!< Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE55_LOCK0; /*!< Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE55_LOCK1; /*!< Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE56_LOCK0; /*!< Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE56_LOCK1; /*!< Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE57_LOCK0; /*!< Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE57_LOCK1; /*!< Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE58_LOCK0; /*!< Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE58_LOCK1; /*!< Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE59_LOCK0; /*!< Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE59_LOCK1; /*!< Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE60_LOCK0; /*!< Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE60_LOCK1; /*!< Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE61_LOCK0; /*!< Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE61_LOCK1; /*!< Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE62_LOCK0; /*!< Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE62_LOCK1; /*!< Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE63_LOCK0; /*!< Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE63_LOCK1; /*!< Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ +} OTP_DATA_RAW_Type; /*!< Size = 16384 (0x4000) */ + + + +/* =========================================================================================================================== */ +/* ================ TBMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief For managing simulation testbenches (TBMAN) + */ + +typedef struct { /*!< TBMAN Structure */ + __IOM uint32_t PLATFORM; /*!< Indicates the type of platform in use */ +} TBMAN_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ USB_DPRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DPRAM layout for USB device. (USB_DPRAM) + */ + +typedef struct { /*!< USB_DPRAM Structure */ + __IOM uint32_t SETUP_PACKET_LOW; /*!< Bytes 0-3 of the SETUP packet from the host. */ + __IOM uint32_t SETUP_PACKET_HIGH; /*!< Bytes 4-7 of the setup packet from the host. */ + __IOM uint32_t EP1_IN_CONTROL; /*!< EP1_IN_CONTROL */ + __IOM uint32_t EP1_OUT_CONTROL; /*!< EP1_OUT_CONTROL */ + __IOM uint32_t EP2_IN_CONTROL; /*!< EP2_IN_CONTROL */ + __IOM uint32_t EP2_OUT_CONTROL; /*!< EP2_OUT_CONTROL */ + __IOM uint32_t EP3_IN_CONTROL; /*!< EP3_IN_CONTROL */ + __IOM uint32_t EP3_OUT_CONTROL; /*!< EP3_OUT_CONTROL */ + __IOM uint32_t EP4_IN_CONTROL; /*!< EP4_IN_CONTROL */ + __IOM uint32_t EP4_OUT_CONTROL; /*!< EP4_OUT_CONTROL */ + __IOM uint32_t EP5_IN_CONTROL; /*!< EP5_IN_CONTROL */ + __IOM uint32_t EP5_OUT_CONTROL; /*!< EP5_OUT_CONTROL */ + __IOM uint32_t EP6_IN_CONTROL; /*!< EP6_IN_CONTROL */ + __IOM uint32_t EP6_OUT_CONTROL; /*!< EP6_OUT_CONTROL */ + __IOM uint32_t EP7_IN_CONTROL; /*!< EP7_IN_CONTROL */ + __IOM uint32_t EP7_OUT_CONTROL; /*!< EP7_OUT_CONTROL */ + __IOM uint32_t EP8_IN_CONTROL; /*!< EP8_IN_CONTROL */ + __IOM uint32_t EP8_OUT_CONTROL; /*!< EP8_OUT_CONTROL */ + __IOM uint32_t EP9_IN_CONTROL; /*!< EP9_IN_CONTROL */ + __IOM uint32_t EP9_OUT_CONTROL; /*!< EP9_OUT_CONTROL */ + __IOM uint32_t EP10_IN_CONTROL; /*!< EP10_IN_CONTROL */ + __IOM uint32_t EP10_OUT_CONTROL; /*!< EP10_OUT_CONTROL */ + __IOM uint32_t EP11_IN_CONTROL; /*!< EP11_IN_CONTROL */ + __IOM uint32_t EP11_OUT_CONTROL; /*!< EP11_OUT_CONTROL */ + __IOM uint32_t EP12_IN_CONTROL; /*!< EP12_IN_CONTROL */ + __IOM uint32_t EP12_OUT_CONTROL; /*!< EP12_OUT_CONTROL */ + __IOM uint32_t EP13_IN_CONTROL; /*!< EP13_IN_CONTROL */ + __IOM uint32_t EP13_OUT_CONTROL; /*!< EP13_OUT_CONTROL */ + __IOM uint32_t EP14_IN_CONTROL; /*!< EP14_IN_CONTROL */ + __IOM uint32_t EP14_OUT_CONTROL; /*!< EP14_OUT_CONTROL */ + __IOM uint32_t EP15_IN_CONTROL; /*!< EP15_IN_CONTROL */ + __IOM uint32_t EP15_OUT_CONTROL; /*!< EP15_OUT_CONTROL */ + __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ +} USB_DPRAM_Type; /*!< Size = 256 (0x100) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define RESETS_BASE 0x40020000UL +#define PSM_BASE 0x40018000UL +#define CLOCKS_BASE 0x40010000UL +#define TICKS_BASE 0x40108000UL +#define PADS_BANK0_BASE 0x40038000UL +#define PADS_QSPI_BASE 0x40040000UL +#define IO_QSPI_BASE 0x40030000UL +#define IO_BANK0_BASE 0x40028000UL +#define SYSINFO_BASE 0x40000000UL +#define SHA256_BASE 0x400F8000UL +#define HSTX_FIFO_BASE 0x50600000UL +#define HSTX_CTRL_BASE 0x400C0000UL +#define EPPB_BASE 0xE0080000UL +#define PPB_BASE 0xE0000000UL +#define PPB_NS_BASE 0xE0020000UL +#define QMI_BASE 0x400D0000UL +#define XIP_CTRL_BASE 0x400C8000UL +#define XIP_AUX_BASE 0x50500000UL +#define SYSCFG_BASE 0x40008000UL +#define XOSC_BASE 0x40048000UL +#define PLL_SYS_BASE 0x40050000UL +#define PLL_USB_BASE 0x40058000UL +#define ACCESSCTRL_BASE 0x40060000UL +#define UART0_BASE 0x40070000UL +#define UART1_BASE 0x40078000UL +#define ROSC_BASE 0x400E8000UL +#define POWMAN_BASE 0x40100000UL +#define WATCHDOG_BASE 0x400D8000UL +#define DMA_BASE 0x50000000UL +#define TIMER0_BASE 0x400B0000UL +#define TIMER1_BASE 0x400B8000UL +#define PWM_BASE 0x400A8000UL +#define ADC_BASE 0x400A0000UL +#define I2C0_BASE 0x40090000UL +#define I2C1_BASE 0x40098000UL +#define SPI0_BASE 0x40080000UL +#define SPI1_BASE 0x40088000UL +#define PIO0_BASE 0x50200000UL +#define PIO1_BASE 0x50300000UL +#define PIO2_BASE 0x50400000UL +#define BUSCTRL_BASE 0x40068000UL +#define SIO_BASE 0xD0000000UL +#define SIO_NS_BASE 0xD0020000UL +#define BOOTRAM_BASE 0x400E0000UL +#define CORESIGHT_TRACE_BASE 0x50700000UL +#define USB_BASE 0x50110000UL +#define TRNG_BASE 0x400F0000UL +#define GLITCH_DETECTOR_BASE 0x40158000UL +#define OTP_BASE 0x40120000UL +#define OTP_DATA_BASE 0x40130000UL +#define OTP_DATA_RAW_BASE 0x40134000UL +#define TBMAN_BASE 0x40160000UL +#define USB_DPRAM_BASE 0x50100000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define RESETS ((RESETS_Type*) RESETS_BASE) +#define PSM ((PSM_Type*) PSM_BASE) +#define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) +#define TICKS ((TICKS_Type*) TICKS_BASE) +#define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) +#define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) +#define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) +#define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) +#define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) +#define SHA256 ((SHA256_Type*) SHA256_BASE) +#define HSTX_FIFO ((HSTX_FIFO_Type*) HSTX_FIFO_BASE) +#define HSTX_CTRL ((HSTX_CTRL_Type*) HSTX_CTRL_BASE) +#define EPPB ((EPPB_Type*) EPPB_BASE) +#define PPB ((PPB_Type*) PPB_BASE) +#define PPB_NS ((PPB_Type*) PPB_NS_BASE) +#define QMI ((QMI_Type*) QMI_BASE) +#define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) +#define XIP_AUX ((XIP_AUX_Type*) XIP_AUX_BASE) +#define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) +#define XOSC ((XOSC_Type*) XOSC_BASE) +#define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) +#define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) +#define ACCESSCTRL ((ACCESSCTRL_Type*) ACCESSCTRL_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define ROSC ((ROSC_Type*) ROSC_BASE) +#define POWMAN ((POWMAN_Type*) POWMAN_BASE) +#define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) +#define DMA ((DMA_Type*) DMA_BASE) +#define TIMER0 ((TIMER0_Type*) TIMER0_BASE) +#define TIMER1 ((TIMER0_Type*) TIMER1_BASE) +#define PWM ((PWM_Type*) PWM_BASE) +#define ADC ((ADC_Type*) ADC_BASE) +#define I2C0 ((I2C0_Type*) I2C0_BASE) +#define I2C1 ((I2C0_Type*) I2C1_BASE) +#define SPI0 ((SPI0_Type*) SPI0_BASE) +#define SPI1 ((SPI0_Type*) SPI1_BASE) +#define PIO0 ((PIO0_Type*) PIO0_BASE) +#define PIO1 ((PIO0_Type*) PIO1_BASE) +#define PIO2 ((PIO0_Type*) PIO2_BASE) +#define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) +#define SIO ((SIO_Type*) SIO_BASE) +#define SIO_NS ((SIO_Type*) SIO_NS_BASE) +#define BOOTRAM ((BOOTRAM_Type*) BOOTRAM_BASE) +#define CORESIGHT_TRACE ((CORESIGHT_TRACE_Type*) CORESIGHT_TRACE_BASE) +#define USB ((USB_Type*) USB_BASE) +#define TRNG ((TRNG_Type*) TRNG_BASE) +#define GLITCH_DETECTOR ((GLITCH_DETECTOR_Type*) GLITCH_DETECTOR_BASE) +#define OTP ((OTP_Type*) OTP_BASE) +#define OTP_DATA ((OTP_DATA_Type*) OTP_DATA_BASE) +#define OTP_DATA_RAW ((OTP_DATA_RAW_Type*) OTP_DATA_RAW_BASE) +#define TBMAN ((TBMAN_Type*) TBMAN_BASE) +#define USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +#ifdef __cplusplus +} +#endif + +#endif /* RP2350_H */ + + +/** @} */ /* End of group RP2350 */ + +/** @} */ /* End of group Raspberry Pi */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/system_RP2350.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/system_RP2350.h new file mode 100644 index 000000000..30881ccc6 --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/system_RP2350.h @@ -0,0 +1,65 @@ +/*************************************************************************//** + * @file system_RP2040.h + * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for + * Device RP2040 + * @version V1.0.0 + * @date 5. May 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CMSIS_SYSTEM_RP2040_H +#define _CMSIS_SYSTEM_RP2040_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMSIS_SYSTEM_RP2040_H */ diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Source/system_RP2350.c b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Source/system_RP2350.c new file mode 100644 index 000000000..799d65a2b --- /dev/null +++ b/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Source/system_RP2350.c @@ -0,0 +1,52 @@ +/*************************************************************************//** + * @file system_RP2040.c + * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for + * Device RP2040 + * @version V1.0.0 + * @date 5. May 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "RP2350.h" +#include "hardware/clocks.h" + +/*--------------------------------------------------------------------------- + System Core Clock Variable + *---------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/ + +/*--------------------------------------------------------------------------- + System Core Clock function + *---------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = clock_get_hz(clk_sys); +} + +/*--------------------------------------------------------------------------- + System initialization function + *---------------------------------------------------------------------------*/ +void __attribute__((constructor)) SystemInit (void) +{ + SystemCoreClockUpdate(); +} \ No newline at end of file diff --git a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h b/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h deleted file mode 100644 index a29b9e095..000000000 --- a/src/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h +++ /dev/null @@ -1,109 +0,0 @@ -/*************************************************************************//** - * @file RP2040.h - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device RP2040 - * @version V1.0.0 - * @date 5. May 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CMSIS_RP2040_H_ -#define _CMSIS_RP2040_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum -{ - /* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* =========================================== RP2040 Specific Interrupt Numbers =========================================== */ - TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */ - TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */ - TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */ - TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */ - PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */ - USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */ - XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */ - PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */ - PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */ - PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */ - PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */ - DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */ - DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */ - IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */ - IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */ - SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */ - SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */ - CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */ - SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */ - SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */ - UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */ - UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */ - ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */ - I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */ - I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */ - RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */ -} IRQn_Type; - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ -#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __MPU_PRESENT 1 /*!< MPU present */ -#define __FPU_PRESENT 0 /*!< FPU present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ -#include "system_RP2040.h" /*!< RP2040 System */ - -#ifndef __IM /*!< Fallback for older CMSIS versions */ -#define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ -#define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ -#define __IOM __IO -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _CMSIS_RP2040_H */ diff --git a/src/rp2_common/hardware_adc/BUILD.bazel b/src/rp2_common/hardware_adc/BUILD.bazel index b1532a302..a94c62ca9 100644 --- a/src/rp2_common/hardware_adc/BUILD.bazel +++ b/src/rp2_common/hardware_adc/BUILD.bazel @@ -9,9 +9,9 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_gpio", "//src/rp2_common/hardware_resets", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_adc/adc.c b/src/rp2_common/hardware_adc/adc.c index 9058de0cc..7f7378d95 100644 --- a/src/rp2_common/hardware_adc/adc.c +++ b/src/rp2_common/hardware_adc/adc.c @@ -10,8 +10,7 @@ void adc_init(void) { // ADC is in an unknown state. We should start by resetting it - reset_block(RESETS_RESET_ADC_BITS); - unreset_block_wait(RESETS_RESET_ADC_BITS); + reset_unreset_block_num_wait_blocking(RESET_ADC); // Now turn it back on. Staging of clock etc is handled internally adc_hw->cs = ADC_CS_EN_BITS; diff --git a/src/rp2_common/hardware_adc/include/hardware/adc.h b/src/rp2_common/hardware_adc/include/hardware/adc.h index 1edad1dd4..095a3f5b8 100644 --- a/src/rp2_common/hardware_adc/include/hardware/adc.h +++ b/src/rp2_common/hardware_adc/include/hardware/adc.h @@ -16,37 +16,58 @@ * * \brief Analog to Digital Converter (ADC) API * - * The RP2040 has an internal analogue-digital converter (ADC) with the following features: + * RP-series microcontrollers have + * an internal analogue-digital converter (ADC) with the following features: * - SAR ADC * - 500 kS/s (Using an independent 48MHz clock) - * - 12 bit (8.7 ENOB) - * - 5 input mux: + * - 12 bit (RP2040 8.7 ENOB, RP2350 9.2 ENOB) + * \if rp2040_specific + * - RP2040 5 input mux: * - 4 inputs that are available on package pins shared with GPIO[29:26] * - 1 input is dedicated to the internal temperature sensor - * - 8 element receive sample FIFO + * - 4 element receive sample FIFO + * \endif + * + * \if rp2350_specific + * - RP2350 5 or 9 input mux: + * - 4 inputs available on QFN-60 package pins shared with GPIO[29:26] + * - 8 inputs available on QFN-80 package pins shared with GPIO[47:40] + * - 8 element receive sample FIFO + * \endif + * - One input dedicated to the internal temperature sensor (see Section 12.4.6) * - Interrupt generation * - DMA interface * * Although there is only one ADC you can specify the input to it using the adc_select_input() function. * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read. * - * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4. + * RP2040, RP2350 QFN-60: User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4. + * RP2350 QFN-80 : User ADC inputs are on 0-7 (GPIO 40-47), the temperature sensor is on input 8. * * Temperature sensor values can be approximated in centigrade as: * * T = 27 - (ADC_Voltage - 0.706)/0.001721 * - * The FIFO, if used, can contain up to 8 entries. - * * \subsection adc_example Example * \addtogroup hardware_adc * * \include hello_adc.c */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADC, Enable/disable assertions in the ADC module, type=bool, default=0, group=hardware_adc -#ifndef PARAM_ASSERTIONS_ENABLED_ADC -#define PARAM_ASSERTIONS_ENABLED_ADC 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC, Enable/disable assertions in the hardware_adc module, type=bool, default=0, group=hardware_adc +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC +#ifdef PARAM_ASSERTIONS_ENABLED_ADC // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC PARAM_ASSERTIONS_ENABLED_ADC +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_ADC 0 +#endif +#endif + +/** + * The ADC channel number of the on-board temperature sensor + */ +#ifndef ADC_TEMPERATURE_CHANNEL_NUM +#define ADC_TEMPERATURE_CHANNEL_NUM (NUM_ADC_CHANNELS - 1) #endif #ifdef __cplusplus @@ -64,10 +85,10 @@ void adc_init(void); * * Prepare a GPIO for use with ADC by disabling all digital functions. * - * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive. + * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive on RP2040 or RP2350A, 40-48 inclusive on RP2350B */ static inline void adc_gpio_init(uint gpio) { - invalid_params_if(ADC, gpio < 26 || gpio > 29); + invalid_params_if(HARDWARE_ADC, gpio < ADC_BASE_PIN || gpio >= ADC_BASE_PIN + NUM_ADC_CHANNELS - 1); // Select NULL function to make output driver hi-Z gpio_set_function(gpio, GPIO_FUNC_NULL); // Also disable digital pulls and digital receiver @@ -78,20 +99,35 @@ static inline void adc_gpio_init(uint gpio) { /*! \brief ADC input select * \ingroup hardware_adc * - * Select an ADC input. 0...3 are GPIOs 26...29 respectively. - * Input 4 is the onboard temperature sensor. + * Select an ADC input + * \if rp2040_specific + * On RP02040 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. + * \endif + * \if rp2350_specific + * On RP2350A 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. + * On RP2350B 0...7 are GPIOs 40...47 respectively. Input 8 is the onboard temperature sensor. + * \endif * * \param input Input to select. */ static inline void adc_select_input(uint input) { - valid_params_if(ADC, input < NUM_ADC_CHANNELS); + valid_params_if(HARDWARE_ADC, input < NUM_ADC_CHANNELS); hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS); } /*! \brief Get the currently selected ADC input channel * \ingroup hardware_adc * - * \return The currently selected input channel. 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. + * \return The currently selected input channel. + * + * \if rp2040_specific + * On RP02040 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. + * \endif + * + * \if rp2350_specific + * On RP2350A 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor. + * On RP2350B 0...7 are GPIOs 40...47 respectively. Input 8 is the onboard temperature sensor. + * \endif */ static inline uint adc_get_selected_input(void) { return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB; @@ -101,12 +137,13 @@ static inline uint adc_get_selected_input(void) { * \ingroup hardware_adc * * This function sets which inputs are to be run through in round robin mode. - * Value between 0 and 0x1f (bit 0 to bit 4 for GPIO 26 to 29 and temperature sensor input respectively) + * RP2040, RP2350 QFN-60: Value between 0 and 0x1f (bit 0 to bit 4 for GPIO 26 to 29 and temperature sensor input respectively) + * RP2350 QFN-80: Value between 0 and 0xff (bit 0 to bit 7 for GPIO 40 to 47 and temperature sensor input respectively) * - * \param input_mask A bit pattern indicating which of the 5 inputs are to be sampled. Write a value of 0 to disable round robin sampling. + * \param input_mask A bit pattern indicating which of the 5/8 inputs are to be sampled. Write a value of 0 to disable round robin sampling. */ static inline void adc_set_round_robin(uint input_mask) { - valid_params_if(ADC, input_mask < (1 << NUM_ADC_CHANNELS)); + valid_params_if(HARDWARE_ADC, input_mask < (1 << NUM_ADC_CHANNELS)); hw_write_masked(&adc_hw->cs, input_mask << ADC_CS_RROBIN_LSB, ADC_CS_RROBIN_BITS); } @@ -160,14 +197,22 @@ static inline void adc_run(bool run) { * \param clkdiv If non-zero, conversion will be started at intervals rather than back to back. */ static inline void adc_set_clkdiv(float clkdiv) { - invalid_params_if(ADC, clkdiv >= 1 << (ADC_DIV_INT_MSB - ADC_DIV_INT_LSB + 1)); + invalid_params_if(HARDWARE_ADC, clkdiv >= 1 << (ADC_DIV_INT_MSB - ADC_DIV_INT_LSB + 1)); adc_hw->div = (uint32_t)(clkdiv * (float) (1 << ADC_DIV_INT_LSB)); } /*! \brief Setup the ADC FIFO * \ingroup hardware_adc * - * FIFO is 8 samples long, if a conversion is completed and the FIFO is full, the result is dropped. + * \if rp2040_specific + * On RP2040 the FIFO is 4 samples long. + * \endif + * + * \if rp2350_specific + * On RP2350 the FIFO is 8 samples long. + * \endif + * + * If a conversion is completed and the FIFO is full, the result is dropped. * * \param en Enables write each conversion result to the FIFO * \param dreq_en Enable DMA requests when FIFO contains data @@ -196,13 +241,20 @@ static inline void adc_set_clkdiv(float clkdiv) { * \return Returns true if the FIFO is empty */ static inline bool adc_fifo_is_empty(void) { - return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS); + return adc_hw->fcs & ADC_FCS_EMPTY_BITS; } /*! \brief Get number of entries in the ADC FIFO * \ingroup hardware_adc * - * The ADC FIFO is 8 entries long. This function will return how many samples are currently present. + * \if rp2040_specific + * On RP2040 the FIFO is 4 samples long. + * \endif + * \if rp2350_specific + * On RP2350 the FIFO is 8 samples long. + * \endif + * + * This function will return how many samples are currently present. */ static inline uint8_t adc_fifo_get_level(void) { return (adc_hw->fcs & ADC_FCS_LEVEL_BITS) >> ADC_FCS_LEVEL_LSB; diff --git a/src/rp2_common/hardware_base/BUILD.bazel b/src/rp2_common/hardware_base/BUILD.bazel index 10c514007..0e17e6c89 100644 --- a/src/rp2_common/hardware_base/BUILD.bazel +++ b/src/rp2_common/hardware_base/BUILD.bazel @@ -7,4 +7,10 @@ cc_library( hdrs = ["include/hardware/address_mapped.h"], includes = ["include"], target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform_internal", + ], ) diff --git a/src/rp2_common/hardware_base/CMakeLists.txt b/src/rp2_common/hardware_base/CMakeLists.txt index bc731ca5f..3ccc43b4c 100644 --- a/src/rp2_common/hardware_base/CMakeLists.txt +++ b/src/rp2_common/hardware_base/CMakeLists.txt @@ -1,5 +1,5 @@ add_library(hardware_base INTERFACE) add_library(hardware_base_headers INTERFACE) -target_include_directories(hardware_base_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(hardware_base_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(hardware_base_headers INTERFACE pico_base_headers) target_link_libraries(hardware_base INTERFACE hardware_base_headers) \ No newline at end of file diff --git a/src/rp2_common/hardware_base/include/hardware/address_mapped.h b/src/rp2_common/hardware_base/include/hardware/address_mapped.h index 9ffb74949..b384f5572 100644 --- a/src/rp2_common/hardware_base/include/hardware/address_mapped.h +++ b/src/rp2_common/hardware_base/include/hardware/address_mapped.h @@ -34,7 +34,7 @@ * When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write * 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`. * - * RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within + * RP-series hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within * a hardware register so that concurrent access by two cores is always consistent with one atomic operation * being performed first, followed by the second. * @@ -60,6 +60,9 @@ extern "C" { #define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0 #endif +typedef volatile uint64_t io_rw_64; +typedef const volatile uint64_t io_ro_64; +typedef volatile uint64_t io_wo_64; typedef volatile uint32_t io_rw_32; typedef const volatile uint32_t io_ro_32; typedef volatile uint32_t io_wo_32; @@ -89,20 +92,31 @@ typedef ioptr const const_ioptr; // return rc; //} +#if PICO_RP2040 // Helper method used by xip_alias macros to optionally check input validity __force_inline static uint32_t xip_alias_check_addr(const void *addr) { uint32_t rc = (uintptr_t)addr; valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE); return rc; } +#else +//static __force_inline uint32_t xip_alias_check_addr(const void *addr) { +// uint32_t rc = (uintptr_t)addr; +// valid_params_if(ADDRESS_ALIAS, rc >= XIP_BASE && rc < XIP_END); +// return rc; +//} +#endif // Untyped conversion alias pointer generation macros -#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr))) -#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr))) -#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr))) +#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS + hw_alias_check_addr(addr))) +#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS + hw_alias_check_addr(addr))) +#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS + hw_alias_check_addr(addr))) + +#if PICO_RP2040 #define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr))) #define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr))) #define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr))) +#endif // Typed conversion alias pointer generation macros #define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p)) @@ -158,6 +172,11 @@ __force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint hw_xor_bits(addr, (*addr ^ values) & write_mask); } +#if !PICO_RP2040 +// include this here to avoid the check in every other hardware/structs header that needs it +#include "hardware/structs/accessctrl.h" +#endif + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/hardware_boot_lock/BUILD.bazel b/src/rp2_common/hardware_boot_lock/BUILD.bazel new file mode 100644 index 000000000..4f288dd59 --- /dev/null +++ b/src/rp2_common/hardware_boot_lock/BUILD.bazel @@ -0,0 +1,27 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +# Picotool needs this, so we can't strictly constrain compatibility. +cc_library( + name = "hardware_boot_lock_headers", + hdrs = ["include/hardware/boot_lock.h"], + includes = ["include"], + tags = ["manual"], + visibility = ["//src/rp2_common/pico_bootrom:__pkg__"], +) + +cc_library( + name = "hardware_boot_lock", + srcs = ["boot_lock.c"], + hdrs = ["include/hardware/boot_lock.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/common/pico_sync", + "//src/rp2_common:hardware_structs", + "//src/rp2_common/pico_runtime", + "//src/rp2_common/pico_runtime_init", + ], +) diff --git a/src/rp2_common/hardware_boot_lock/CMakeLists.txt b/src/rp2_common/hardware_boot_lock/CMakeLists.txt new file mode 100644 index 000000000..38158b032 --- /dev/null +++ b/src/rp2_common/hardware_boot_lock/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(boot_lock) diff --git a/src/rp2_common/hardware_boot_lock/boot_lock.c b/src/rp2_common/hardware_boot_lock/boot_lock.c new file mode 100644 index 000000000..a344631b3 --- /dev/null +++ b/src/rp2_common/hardware_boot_lock/boot_lock.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "hardware/boot_lock.h" +#include "pico/runtime_init.h" + +#if NUM_BOOT_LOCKS > 0 +void boot_locks_reset(void) { + GCC_Pragma("GCC unroll 1") // prevent GCC unrolling this loop which is 8 bytes per + for (uint i = 0; i < NUM_BOOT_LOCKS; i++) { + boot_unlock_unsafe(boot_lock_instance(i)); + } +} + +boot_lock_t *boot_lock_init(uint lock_num) { + assert(lock_num < NUM_BOOT_LOCKS); + boot_lock_t *lock = boot_lock_instance(lock_num); + boot_unlock_unsafe(lock); + return lock; +} + +#if !PICO_RUNTIME_NO_INIT_BOOT_LOCKS_RESET +#include "hardware/sync.h" +void __weak runtime_init_boot_locks_reset(void) { + boot_locks_reset(); +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET +PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_boot_locks_reset, PICO_RUNTIME_INIT_BOOT_LOCKS_RESET); +#endif + +#endif diff --git a/src/rp2_common/hardware_boot_lock/include/hardware/boot_lock.h b/src/rp2_common/hardware_boot_lock/include/hardware/boot_lock.h new file mode 100644 index 000000000..dd63ef0e8 --- /dev/null +++ b/src/rp2_common/hardware_boot_lock/include/hardware/boot_lock.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_BOOT_LOCK_H +#define _HARDWARE_BOOT_LOCK_H + +#include "pico.h" + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK, Enable/disable assertions in the hardware_boot_lock module, type=bool, default=0, group=hardware_boot_lock +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_BOOT_LOCK 0 +#endif + +#if NUM_BOOT_LOCKS > 0 +#include "hardware/sync.h" +#include "hardware/structs/bootram.h" + +/** \brief A boot lock identifier + * \ingroup hardware_sync + */ +typedef volatile uint32_t boot_lock_t; + +/*! \brief Get HW Bootlock instance from number + * \ingroup hardware_sync + * + * \param lock_num Bootlock ID + * \return The bootlock instance + */ +__force_inline static boot_lock_t *boot_lock_instance(uint lock_num) { + invalid_params_if(HARDWARE_BOOT_LOCK, lock_num >= NUM_BOOT_LOCKS); + return (boot_lock_t *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET + lock_num * 4); +} + +/*! \brief Get HW Bootlock number from instance + * \ingroup hardware_sync + * + * \param lock The Bootlock instance + * \return The Bootlock ID + */ +__force_inline static uint boot_lock_get_num(boot_lock_t *lock) { + invalid_params_if(HARDWARE_BOOT_LOCK, (uint) lock < BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET || + (uint) lock >= NUM_BOOT_LOCKS * sizeof(boot_lock_t) + BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET || + ((uint) lock - BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET) % sizeof(boot_lock_t) != 0); + return (uint) (lock - (boot_lock_t *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK0_OFFSET)); +} + +/*! \brief Acquire a boot lock without disabling interrupts (hence unsafe) + * \ingroup hardware_sync + * + * \param lock Bootlock instance + */ +__force_inline static void boot_lock_unsafe_blocking(boot_lock_t *lock) { + // Note we don't do a wfe or anything, because by convention these boot_locks are VERY SHORT LIVED and NEVER BLOCK and run + // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core + // anyway which should be finished soon + while (__builtin_expect(!*lock, 0)) { // read from bootlock register (tries to acquire the lock) + tight_loop_contents(); + } + __mem_fence_acquire(); +} + +/*! \brief try to acquire a boot lock without disabling interrupts (hence unsafe) + * \ingroup hardware_sync + * + * \param lock Bootlock instance + */ +__force_inline static bool boot_try_lock_unsafe(boot_lock_t *lock) { + if (*lock) { + __mem_fence_acquire(); + return true; + } + return false; +} + +/*! \brief Release a boot lock without re-enabling interrupts + * \ingroup hardware_sync + * + * \param lock Bootlock instance + */ +__force_inline static void boot_unlock_unsafe(boot_lock_t *lock) { + __mem_fence_release(); + *lock = 0; // write to bootlock register (release lock) +} + +/*! \brief Acquire a boot lock safely + * \ingroup hardware_sync + * + * This function will disable interrupts prior to acquiring the bootlock + * + * \param lock Bootlock instance + * \return interrupt status to be used when unlocking, to restore to original state + */ +__force_inline static uint32_t boot_lock_blocking(boot_lock_t *lock) { + uint32_t save = save_and_disable_interrupts(); + boot_lock_unsafe_blocking(lock); + return save; +} + +/*! \brief Check to see if a bootlock is currently acquired elsewhere. + * \ingroup hardware_sync + * + * \param lock Bootlock instance + */ +inline static bool is_boot_locked(boot_lock_t *lock) { + check_hw_size(boot_lock_t, 4); + uint lock_num = boot_lock_get_num(lock); + return 0 != (*(io_ro_32 *) (BOOTRAM_BASE + BOOTRAM_BOOTLOCK_STAT_OFFSET) & (1u << lock_num)); +} + +/*! \brief Release a boot lock safely + * \ingroup hardware_sync + * + * This function will re-enable interrupts according to the parameters. + * + * \param lock Bootlock instance + * \param saved_irq Return value from the \ref boot_lock_blocking() function. + * + * \sa boot_lock_blocking() + */ +__force_inline static void boot_unlock(boot_lock_t *lock, uint32_t saved_irq) { + boot_unlock_unsafe(lock); + restore_interrupts_from_disabled(saved_irq); +} + +/*! \brief Initialise a boot lock + * \ingroup hardware_sync + * + * The boot lock is initially unlocked + * + * \param lock_num The boot lock number + * \return The boot lock instance + */ +boot_lock_t *boot_lock_init(uint lock_num); + +/*! \brief Release all boot locks + * \ingroup hardware_sync + */ +void boot_locks_reset(void); + +#endif +#endif \ No newline at end of file diff --git a/src/rp2_common/hardware_claim/BUILD.bazel b/src/rp2_common/hardware_claim/BUILD.bazel deleted file mode 100644 index 395e8e0d5..000000000 --- a/src/rp2_common/hardware_claim/BUILD.bazel +++ /dev/null @@ -1,16 +0,0 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") - -package(default_visibility = ["//visibility:public"]) - -cc_library( - name = "hardware_claim", - srcs = ["claim.c"], - hdrs = ["include/hardware/claim.h"], - includes = ["include"], - target_compatible_with = compatible_with_rp2(), - deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/common/pico_base:pico_platform", - "//src/rp2_common/hardware_sync:hardware_sync_headers", - ], -) diff --git a/src/rp2_common/hardware_clocks/BUILD.bazel b/src/rp2_common/hardware_clocks/BUILD.bazel index 8fe301b19..2c2ffe24d 100644 --- a/src/rp2_common/hardware_clocks/BUILD.bazel +++ b/src/rp2_common/hardware_clocks/BUILD.bazel @@ -15,8 +15,9 @@ cc_library( "//src/rp2_common/hardware_xosc:__pkg__", ], deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", + "//src/rp2_common/hardware_base", ], ) @@ -27,14 +28,15 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:platform_defs", + "//src/rp2_common/hardware_base", "//src/rp2_common/hardware_gpio", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_pll", "//src/rp2_common/hardware_watchdog", "//src/rp2_common/hardware_xosc", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", - "//src/rp2_common/pico_platform:platform_defs", ], ) diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c index ad1eaeb77..05a4723d2 100644 --- a/src/rp2_common/hardware_clocks/clocks.c +++ b/src/rp2_common/hardware_clocks/clocks.c @@ -8,18 +8,10 @@ #include "hardware/regs/clocks.h" #include "hardware/platform_defs.h" #include "hardware/clocks.h" -#include "hardware/watchdog.h" #include "hardware/pll.h" -#include "hardware/xosc.h" #include "hardware/irq.h" #include "hardware/gpio.h" -// The RTC clock frequency is 48MHz divided by power of 2 (to ensure an integer -// division ratio will be used in the clocks block). A divisor of 1024 generates -// an RTC clock tick of 46875Hz. This frequency is relatively close to the -// customary 32 or 32.768kHz 'slow clock' crystals and provides good timing resolution. -#define RTC_CLOCK_FREQ_HZ (USB_CLK_KHZ * KHZ / 1024) - check_hw_layout(clocks_hw_t, clk[clk_adc].selected, CLOCKS_CLK_ADC_SELECTED_OFFSET); check_hw_layout(clocks_hw_t, fc0.result, CLOCKS_FC0_RESULT_OFFSET); check_hw_layout(clocks_hw_t, ints, CLOCKS_INTS_OFFSET); @@ -34,42 +26,32 @@ static resus_callback_t _resus_callback; // - An auxiliary (glitchy) mux, whose output glitches when switched, but has // no constraints on its inputs // Not all clocks have both types of mux. -static inline bool has_glitchless_mux(enum clock_index clk_index) { - return clk_index == clk_sys || clk_index == clk_ref; +static inline bool has_glitchless_mux(clock_handle_t clock) { + return clock == clk_sys || clock == clk_ref; } -void clock_stop(enum clock_index clk_index) { - clock_hw_t *clock = &clocks_hw->clk[clk_index]; - hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); - configured_freq[clk_index] = 0; +void clock_stop(clock_handle_t clock) { + clock_hw_t *clock_hw = &clocks_hw->clk[clock]; + hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); + configured_freq[clock] = 0; } /// \tag::clock_configure[] -bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) { - uint32_t div; - - assert(src_freq >= freq); - - if (freq > src_freq) - return false; - - // Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8) - div = (uint32_t) (((uint64_t) src_freq << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / freq); - - clock_hw_t *clock = &clocks_hw->clk[clk_index]; +static void clock_configure_internal(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t actual_freq, uint32_t div) { + clock_hw_t *clock_hw = &clocks_hw->clk[clock]; // If increasing divisor, set divisor before source. Otherwise set source // before divisor. This avoids a momentary overspeed when e.g. switching // to a faster source and increasing divisor to compensate. - if (div > clock->div) - clock->div = div; + if (div > clock_hw->div) + clock_hw->div = div; // If switching a glitchless slice (ref or sys) to an aux source, switch // away from aux *first* to avoid passing glitches when changing aux mux. // Assume (!!!) glitchless source 0 is no faster than the aux source. - if (has_glitchless_mux(clk_index) && src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) { - hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); - while (!(clock->selected & 1u)) + if (has_glitchless_mux(clock) && src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) { + hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); + while (!(clock_hw->selected & 1u)) tight_loop_contents(); } // If no glitchless mux, cleanly stop the clock to avoid glitches @@ -78,133 +60,73 @@ bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, else { // Disable clock. On clk_ref and clk_sys this does nothing, // all other clocks have the ENABLE bit in the same position. - hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); - if (configured_freq[clk_index] > 0) { + hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); + if (configured_freq[clock] > 0) { // Delay for 3 cycles of the target clock, for ENABLE propagation. // Note XOSC_COUNT is not helpful here because XOSC is not - // necessarily running, nor is timer...: - uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1; + // necessarily running, nor is timer... + uint delay_cyc = configured_freq[clk_sys] / configured_freq[clock] + 1; busy_wait_at_least_cycles(delay_cyc * 3); } } // Set aux mux first, and then glitchless mux if this clock has one - hw_write_masked(&clock->ctrl, + hw_write_masked(&clock_hw->ctrl, (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS ); - if (has_glitchless_mux(clk_index)) { - hw_write_masked(&clock->ctrl, + if (has_glitchless_mux(clock)) { + hw_write_masked(&clock_hw->ctrl, src << CLOCKS_CLK_REF_CTRL_SRC_LSB, CLOCKS_CLK_REF_CTRL_SRC_BITS ); - while (!(clock->selected & (1u << src))) + while (!(clock_hw->selected & (1u << src))) tight_loop_contents(); } // Enable clock. On clk_ref and clk_sys this does nothing, // all other clocks have the ENABLE bit in the same position. - hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); + hw_set_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); // Now that the source is configured, we can trust that the user-supplied // divisor is a safe value. - clock->div = div; - - // Store the configured frequency - configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div); - - return true; + clock_hw->div = div; + configured_freq[clock] = actual_freq; } -/// \end::clock_configure[] -void clocks_init(void) { - // Start tick in watchdog, the argument is in 'cycles per microsecond' i.e. MHz - watchdog_start_tick(XOSC_KHZ / KHZ); +bool clock_configure(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) { + assert(src_freq >= freq); - // Everything is 48MHz on FPGA apart from RTC. Otherwise set to 0 and will be set in clock configure - if (running_on_fpga()) { - for (uint i = 0; i < CLK_COUNT; i++) { - configured_freq[i] = 48 * MHZ; - } - configured_freq[clk_rtc] = RTC_CLOCK_FREQ_HZ; - return; - } + if (freq > src_freq) + return false; - // Disable resus that may be enabled from previous software - clocks_hw->resus.ctrl = 0; + uint32_t div = (uint32_t)((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / freq); + uint32_t actual_freq = (uint32_t) ((((uint64_t) src_freq) << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) / div); - // Enable the xosc - xosc_init(); + clock_configure_internal(clock, src, auxsrc, actual_freq, div); + // Store the configured frequency + return true; +} - // Before we touch PLLs, switch sys and ref cleanly away from their aux sources. - hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); - while (clocks_hw->clk[clk_sys].selected != 0x1) - tight_loop_contents(); - hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); - while (clocks_hw->clk[clk_ref].selected != 0x1) - tight_loop_contents(); +void clock_configure_int_divider(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t int_divider) { + clock_configure_internal(clock, src, auxsrc, src_freq / int_divider, int_divider << CLOCKS_CLK_GPOUT0_DIV_INT_LSB); +} - /// \tag::pll_init[] - pll_init(pll_sys, PLL_COMMON_REFDIV, PLL_SYS_VCO_FREQ_KHZ * KHZ, PLL_SYS_POSTDIV1, PLL_SYS_POSTDIV2); - pll_init(pll_usb, PLL_COMMON_REFDIV, PLL_USB_VCO_FREQ_KHZ * KHZ, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2); - /// \end::pll_init[] - - // Configure clocks - // CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz - clock_configure(clk_ref, - CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, - 0, // No aux mux - XOSC_KHZ * KHZ, - XOSC_KHZ * KHZ); - - /// \tag::configure_clk_sys[] - // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz - clock_configure(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, - SYS_CLK_KHZ * KHZ, - SYS_CLK_KHZ * KHZ); - /// \end::configure_clk_sys[] - - // CLK USB = PLL USB 48MHz / 1 = 48MHz - clock_configure(clk_usb, - 0, // No GLMUX - CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_KHZ * KHZ, - USB_CLK_KHZ * KHZ); - - // CLK ADC = PLL USB 48MHZ / 1 = 48MHz - clock_configure(clk_adc, - 0, // No GLMUX - CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_KHZ * KHZ, - USB_CLK_KHZ * KHZ); - - // CLK RTC = PLL USB 48MHz / 1024 = 46875Hz - clock_configure(clk_rtc, - 0, // No GLMUX - CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_KHZ * KHZ, - RTC_CLOCK_FREQ_HZ); - - // CLK PERI = clk_sys. Used as reference clock for Peripherals. No dividers so just select and enable - // Normally choose clk_sys or clk_usb - clock_configure(clk_peri, - 0, - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, - SYS_CLK_KHZ * KHZ, - SYS_CLK_KHZ * KHZ); +void clock_configure_undivided(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq) { + clock_configure_internal(clock, src, auxsrc, src_freq, 1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB); } +/// \end::clock_configure[] + /// \tag::clock_get_hz[] -uint32_t clock_get_hz(enum clock_index clk_index) { - return configured_freq[clk_index]; +uint32_t clock_get_hz(clock_handle_t clock) { + return configured_freq[clock]; } /// \end::clock_get_hz[] -void clock_set_reported_hz(enum clock_index clk_index, uint hz) { - configured_freq[clk_index] = hz; +void clock_set_reported_hz(clock_handle_t clock, uint hz) { + configured_freq[clock] = hz; } /// \tag::frequency_count_khz[] @@ -244,10 +166,9 @@ static void clocks_handle_resus(void) { // CLK SYS = CLK_REF. Must be running for this code to be running uint clk_ref_freq = clock_get_hz(clk_ref); - clock_configure(clk_sys, + clock_configure_undivided(clk_sys, CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF, 0, - clk_ref_freq, clk_ref_freq); // Assert we have been resussed @@ -316,8 +237,12 @@ void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div else if (gpio == 23) gpclk = clk_gpout1; else if (gpio == 24) gpclk = clk_gpout2; else if (gpio == 25) gpclk = clk_gpout3; +#if !PICO_RP2040 + else if (gpio == 13) gpclk = clk_gpout0; + else if (gpio == 15) gpclk = clk_gpout1; +#endif else { - invalid_params_if(CLOCKS, true); + invalid_params_if(HARDWARE_CLOCKS, true); } // Set up the gpclk generator @@ -337,9 +262,14 @@ static const uint8_t gpin0_src[CLK_COUNT] = { CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_REF CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_SYS CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_PERI +#if !PICO_RP2040 + CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_HSTX +#endif CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_USB CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_ADC +#if PICO_RP2040 CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_RTC +#endif }; // Assert GPIN1 is GPIN0 + 1 @@ -350,26 +280,35 @@ static_assert(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GP static_assert(CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); static_assert(CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); static_assert(CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +#if HAS_HSTX +static_assert(CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +#endif static_assert(CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); static_assert(CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +#if HAS_RP2040_RTC static_assert(CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch"); +#endif -bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq) { +bool clock_configure_gpin(clock_handle_t clock, uint gpio, uint32_t src_freq, uint32_t freq) { // Configure a clock to run from a GPIO input uint gpin = 0; if (gpio == 20) gpin = 0; else if (gpio == 22) gpin = 1; +#if PICO_RP2350 + else if (gpio == 12) gpin = 0; + else if (gpio == 14) gpin = 1; +#endif else { - invalid_params_if(CLOCKS, true); + invalid_params_if(HARDWARE_CLOCKS, true); } // Work out sources. GPIN is always an auxsrc uint src = 0; // GPIN1 == GPIN0 + 1 - uint auxsrc = gpin0_src[clk_index] + gpin; + uint auxsrc = gpin0_src[clock] + gpin; - if (has_glitchless_mux(clk_index)) { + if (has_glitchless_mux(clock)) { // AUX src is always 1 src = 1; } @@ -379,5 +318,113 @@ bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_fr // Now we have the src, auxsrc, and configured the gpio input // call clock configure to run the clock from a gpio - return clock_configure(clk_index, src, auxsrc, src_freq, freq); + return clock_configure(clock, src, auxsrc, src_freq, freq); +} + +// everything running off the USB oscillator +void set_sys_clock_48mhz(void) { + if (!running_on_fpga()) { + // Change clk_sys to be 48MHz. The simplest way is to take this from PLL_USB + // which has a source frequency of 48MHz + clock_configure_undivided(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + USB_CLK_HZ); + + // Turn off PLL sys for good measure + pll_deinit(pll_sys); + + // CLK peri is clocked from clk_sys so need to change clk_peri's freq + clock_configure_undivided(clk_peri, + 0, + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, + USB_CLK_HZ); + } +} + +// PICO_CONFIG: PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK, When the SYS clock PLL is changed keep the peripheral clock attached to it, type=bool, default=0, advanced=true, group=hardware_clocks +#ifndef PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK +// By default, when reconfiguring the system clock PLL settings after runtime initialization, +// the peripheral clock is switched to the 48MHz USB clock to ensure continuity of peripheral operation. +// Setting this value to 1 changes the behavior to have the peripheral clock re-configured +// to the system clock at it's new frequency. +#define PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK 0 +#endif + +void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2) { + if (!running_on_fpga()) { + clock_configure_undivided(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + USB_CLK_HZ); + + pll_init(pll_sys, PLL_SYS_REFDIV, vco_freq, post_div1, post_div2); + uint32_t freq = vco_freq / (post_div1 * post_div2); + + // Configure clocks + // CLK_REF is the XOSC source + clock_configure_undivided(clk_ref, + CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, + 0, // No aux mux + XOSC_HZ); + + // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz + clock_configure_undivided(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, + freq); + +#if PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK + clock_configure_undivided(clk_peri, + 0, + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, + freq); +#else + clock_configure_undivided(clk_peri, + 0, // Only AUX mux on ADC + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + USB_CLK_HZ); +#endif + } +} + +bool check_sys_clock_hz(uint32_t freq_hz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) { + uint reference_freq_hz = XOSC_HZ / PLL_SYS_REFDIV; + for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) { + uint vco_hz = fbdiv * reference_freq_hz; + if (vco_hz < PICO_PLL_VCO_MIN_FREQ_HZ || vco_hz > PICO_PLL_VCO_MAX_FREQ_HZ) continue; + for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) { + for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) { + uint out = vco_hz / (postdiv1 * postdiv2); + if (out == freq_hz && !(vco_hz % (postdiv1 * postdiv2))) { + *vco_out = vco_hz; + *postdiv1_out = postdiv1; + *postdiv2_out = postdiv2; + return true; + } + } + } + } + return false; } + +// Note this impl is kept to preserve previous rounding behavior, vs calling check_sys_clock_hz +bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) { + uint reference_freq_khz = (XOSC_HZ / KHZ) / PLL_SYS_REFDIV; + for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) { + uint vco_khz = fbdiv * reference_freq_khz; + if (vco_khz < PICO_PLL_VCO_MIN_FREQ_HZ / KHZ || vco_khz > PICO_PLL_VCO_MAX_FREQ_HZ / KHZ) continue; + for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) { + for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) { + uint out = vco_khz / (postdiv1 * postdiv2); + if (out == freq_khz && !(vco_khz % (postdiv1 * postdiv2))) { + *vco_out = vco_khz * KHZ; + *postdiv1_out = postdiv1; + *postdiv2_out = postdiv2; + return true; + } + } + } + } + return false; +} \ No newline at end of file diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h index 0110d32e7..b626c3825 100644 --- a/src/rp2_common/hardware_clocks/include/hardware/clocks.h +++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h @@ -26,12 +26,15 @@ extern "C" { * it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and * stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies * - * Please refer to the datasheet for more details on the RP2040 clocks. + * Please refer to the appropriate datasheet for more details on the RP-series clocks. * * The clock source depends on which clock you are attempting to configure. The first table below shows main clock sources. If * you are not setting the Reference clock or the System clock, or you are specifying that one of those two will be using an auxiliary * clock source, then you will need to use one of the entries from the subsequent tables. * + * * \if rp2040_specific + * On RP2040 the clock sources are: + * * **Main Clock Sources** * * Source | Reference Clock | System Clock @@ -79,6 +82,53 @@ extern "C" { * USB PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB * ROSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH * XOSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC + * \endif + * + * \if rp2350_specific + * On RP2350 the clock sources are: + * * **Main Clock Sources** + * + * Source | Reference Clock | System Clock + * -------|-----------------|--------- + * ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH | | + * Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX + * XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC | | + * LPOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_LPOSC_CLKSRC | | + * Reference | | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF + * + * **Auxiliary Clock Sources** + * + * The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table + * describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3. + * + * + * Aux Source | clk_gpout[x] | clk_ref | clk_sys + * -----------|------------|---------|-------- + * System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS + * GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + * GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 + * USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB + * ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC + * XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC + * LPOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC | | + * System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS | | | + * USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB | | | + * ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC | | | + * REF clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF | | | + * PERI clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_PERI | | | + * HSTX clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_PERI | | | + + * + * Aux Source | clk_peri | clk_hstx | clk_usb | clk_adc + * -----------|-----------|----------|---------|-------- + * System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS + * GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + * GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 + * USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB + * ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH + * XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC + * System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS | CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS | | | + * \endif * * \section clock_example Example @@ -89,56 +139,99 @@ extern "C" { #define KHZ 1000 #define MHZ 1000000 -/// \tag::pll_settings[] -// -// There are two PLLs in RP2040: -// 1. The 'SYS PLL' generates the 125MHz system clock, the frequency is defined by `SYS_CLK_KHZ`. -// 2. The 'USB PLL' generates the 48MHz USB clock, the frequency is defined by `USB_CLK_KHZ`. +// \tag::pll_settings[] +// There are two PLLs in RP-series microcontrollers: +// 1. The 'SYS PLL' generates the system clock, the frequency is defined by `SYS_CLK_KHZ`. +// 2. The 'USB PLL' generates the USB clock, the frequency is defined by `USB_CLK_KHZ`. // // The two PLLs use the crystal oscillator output directly as their reference frequency input; the PLLs reference -// frequency cannot be reduced by the dividers present in the clocks block. The crystal frequency is defined by `XOSC_KHZ` or -// `XOSC_MHZ`. +// frequency cannot be reduced by the dividers present in the clocks block. The crystal frequency is defined by `XOSC_HZ` (or +// `XOSC_KHZ` or `XOSC_MHZ`). // // The system's default definitions are correct for the above frequencies with a 12MHz // crystal frequency. If different frequencies are required, these must be defined in // the board configuration file together with the revised PLL settings // Use `vcocalc.py` to check and calculate new PLL settings if you change any of these frequencies. // -// Default PLL configuration: +// Default PLL configuration RP2040: // REF FBDIV VCO POSTDIV // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 6 / 2 = 125MHz // PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz -/// \end::pll_settings[] +// +// Default PLL configuration RP2350: +// REF FBDIV VCO POSTDIV +// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHz / 5 / 2 = 150MHz +// PLL USB: 12 / 1 = 12MHz * 100 = 1200MHz / 5 / 5 = 48MHz +// \end::pll_settings[] -// PICO_CONFIG: PLL_COMMON_REFDIV, PLL reference divider setting - used for both PLLs, type=int, default=1, advanced=true, group=hardware_clocks #ifndef PLL_COMMON_REFDIV -#define PLL_COMMON_REFDIV 1 +// backwards compatibility, but now deprecated +#define PLL_COMMON_REFDIV 1 +#endif + +// PICO_CONFIG: PLL_SYS_REFDIV, PLL reference divider setting for PLL_SYS, type=int, default=1, advanced=true, group=hardware_clocks +#ifndef PLL_SYS_REFDIV +// backwards compatibility with deprecated PLL_COMMON_REFDIV +#ifdef PLL_COMMON_REFDIV +#define PLL_SYS_REFDIV PLL_COMMON_REFDIV +#else +#define PLL_SYS_REFDIV 1 +#endif +#endif + +#ifndef PLL_SYS_VCO_FREQ_HZ +// For backwards compatibility define PLL_SYS_VCO_FREQ_HZ if PLL_SYS_VCO_FREQ_KHZ is defined +#ifdef PLL_SYS_VCO_FREQ_KHZ +#define PLL_SYS_VCO_FREQ_HZ (PLL_SYS_VCO_FREQ_KHZ * KHZ) +#endif #endif -#if (SYS_CLK_KHZ == 125000) && (XOSC_KHZ == 12000) && (PLL_COMMON_REFDIV == 1) -// PLL settings for standard 125 MHz system clock. -// PICO_CONFIG: PLL_SYS_VCO_FREQ_KHZ, System clock PLL frequency, type=int, default=1500 * KHZ, advanced=true, group=hardware_clocks -#ifndef PLL_SYS_VCO_FREQ_KHZ -#define PLL_SYS_VCO_FREQ_KHZ (1500 * KHZ) +#if (SYS_CLK_HZ == 125 * MHZ || SYS_CLK_HZ == 150 * MHZ) && (XOSC_HZ == 12 * MHZ) && (PLL_SYS_REFDIV == 1) +// PLL settings for standard 125/150 MHz system clock. +// PICO_CONFIG: PLL_SYS_VCO_FREQ_HZ, System clock PLL frequency, type=int, default=(1500 * MHZ), advanced=true, group=hardware_clocks +#ifndef PLL_SYS_VCO_FREQ_HZ +#define PLL_SYS_VCO_FREQ_HZ (1500 * MHZ) #endif -// PICO_CONFIG: PLL_SYS_POSTDIV1, System clock PLL post divider 1 setting, type=int, default=6, advanced=true, group=hardware_clocks +// PICO_CONFIG: PLL_SYS_POSTDIV1, System clock PLL post divider 1 setting, type=int, default=6 on RP2040 5 or on RP2350, advanced=true, group=hardware_clocks #ifndef PLL_SYS_POSTDIV1 +#if SYS_CLK_HZ == 125 * MHZ #define PLL_SYS_POSTDIV1 6 +#else +#define PLL_SYS_POSTDIV1 5 +#endif #endif // PICO_CONFIG: PLL_SYS_POSTDIV2, System clock PLL post divider 2 setting, type=int, default=2, advanced=true, group=hardware_clocks #ifndef PLL_SYS_POSTDIV2 #define PLL_SYS_POSTDIV2 2 #endif #endif // SYS_CLK_KHZ == 125000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1 -#if !defined(PLL_SYS_VCO_FREQ_KHZ) || !defined(PLL_SYS_POSTDIV1) || !defined(PLL_SYS_POSTDIV2) -#error PLL_SYS_VCO_FREQ_KHZ, PLL_SYS_POSTDIV1 and PLL_SYS_POSTDIV2 must all be specified when using custom clock setup + +#if !defined(PLL_SYS_VCO_FREQ_HZ) || !defined(PLL_SYS_POSTDIV1) || !defined(PLL_SYS_POSTDIV2) +#error PLL_SYS_VCO_FREQ_HZ, PLL_SYS_POSTDIV1 and PLL_SYS_POSTDIV2 must all be specified when using custom clock setup #endif -#if (USB_CLK_KHZ == 48000) && (XOSC_KHZ == 12000) && (PLL_COMMON_REFDIV == 1) +// PICO_CONFIG: PLL_USB_REFDIV, PLL reference divider setting for PLL_USB, type=int, default=1, advanced=true, group=hardware_clocks +#ifndef PLL_USB_REFDIV +// backwards compatibility with deprecated PLL_COMMON_REFDIV +#ifdef PLL_COMMON_REFDIV +#define PLL_USB_REFDIV PLL_COMMON_REFDIV +#else +#define PLL_USB_REFDIV 1 +#endif +#endif + +#ifndef PLL_USB_VCO_FREQ_HZ +// For backwards compatibility define PLL_USB_VCO_FREQ_HZ if PLL_USB_VCO_FREQ_KHZ is defined +#ifdef PLL_USB_VCO_FREQ_KHZ +#define PLL_USB_VCO_FREQ_HZ (PLL_USB_VCO_FREQ_KHZ * KHZ) +#endif +#endif + +#if (USB_CLK_HZ == 48 * MHZ) && (XOSC_HZ == 12 * MHZ) && (PLL_USB_REFDIV == 1) // PLL settings for a USB clock of 48MHz. -// PICO_CONFIG: PLL_USB_VCO_FREQ_KHZ, USB clock PLL frequency, type=int, default=1200 * KHZ, advanced=true, group=hardware_clocks -#ifndef PLL_USB_VCO_FREQ_KHZ -#define PLL_USB_VCO_FREQ_KHZ (1200 * KHZ) +// PICO_CONFIG: PLL_USB_VCO_FREQ_HZ, USB clock PLL frequency, type=int, default=(1200 * MHZ), advanced=true, group=hardware_clocks +#ifndef PLL_USB_VCO_FREQ_HZ +#define PLL_USB_VCO_FREQ_HZ (1200 * MHZ) #endif // PICO_CONFIG: PLL_USB_POSTDIV1, USB clock PLL post divider 1 setting, type=int, default=5, advanced=true, group=hardware_clocks #ifndef PLL_USB_POSTDIV1 @@ -148,50 +241,74 @@ extern "C" { #ifndef PLL_USB_POSTDIV2 #define PLL_USB_POSTDIV2 5 #endif -#endif // USB_CLK_KHZ == 48000 && XOSC_KHZ == 12000 && PLL_COMMON_REFDIV == 1 -#if !defined(PLL_USB_VCO_FREQ_KHZ) || !defined(PLL_USB_POSTDIV1) || !defined(PLL_USB_POSTDIV2) -#error PLL_USB_VCO_FREQ_KHZ, PLL_USB_POSTDIV1 and PLL_USB_POSTDIV2 must all be specified when using custom clock setup. +#endif // USB_CLK_HZ == 48000000 && XOSC_HZ == 12000000 && PLL_COMMON_REFDIV == 1 +#if !defined(PLL_USB_VCO_FREQ_HZ) || !defined(PLL_USB_POSTDIV1) || !defined(PLL_USB_POSTDIV2) +#error PLL_USB_VCO_FREQ_HZ, PLL_USB_POSTDIV1 and PLL_USB_POSTDIV2 must all be specified when using custom clock setup. #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_CLOCKS, Enable/disable assertions in the clocks module, type=bool, default=0, group=hardware_clocks -#ifndef PARAM_ASSERTIONS_ENABLED_CLOCKS -#define PARAM_ASSERTIONS_ENABLED_CLOCKS 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS, Enable/disable assertions in the hardware_clocks module, type=bool, default=0, group=hardware_clocks +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS +#ifdef PARAM_ASSERTIONS_ENABLED_CLOCKS // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS PARAM_ASSERTIONS_ENABLED_CLOCKS +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_CLOCKS 0 +#endif #endif -/*! \brief Initialise the clock hardware +typedef clock_num_t clock_handle_t; + +/*! \brief Configure the specified clock + * \ingroup hardware_clocks + * + * See the tables in the description for details on the possible values for clock sources. + * + * \param clock The clock to configure + * \param src The main clock source, can be 0. + * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0 + * \param src_freq Frequency of the input clock source + * \param freq Requested frequency + */ +bool clock_configure(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq); + +/*! \brief Configure the specified clock to use the undividded input source * \ingroup hardware_clocks * - * Must be called before any other clock function. + * See the tables in the description for details on the possible values for clock sources. + * + * \param clock The clock to configure + * \param src The main clock source, can be 0. + * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0 + * \param src_freq Frequency of the input clock source */ -void clocks_init(void); +void clock_configure_undivided(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq); -/*! \brief Configure the specified clock +/*! \brief Configure the specified clock to use the undividded input source * \ingroup hardware_clocks * * See the tables in the description for details on the possible values for clock sources. * - * \param clk_index The clock to configure + * \param clock The clock to configure * \param src The main clock source, can be 0. * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0 * \param src_freq Frequency of the input clock source - * \param freq Requested frequency + * \param int_divider an integer divider */ -bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq); +void clock_configure_int_divider(clock_handle_t clock, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t int_divider); /*! \brief Stop the specified clock * \ingroup hardware_clocks * - * \param clk_index The clock to stop + * \param clock The clock to stop */ -void clock_stop(enum clock_index clk_index); +void clock_stop(clock_handle_t clock); /*! \brief Get the current frequency of the specified clock * \ingroup hardware_clocks * - * \param clk_index Clock + * \param clock Clock * \return Clock frequency in Hz */ -uint32_t clock_get_hz(enum clock_index clk_index); +uint32_t clock_get_hz(clock_handle_t clock); /*! \brief Measure a clocks frequency using the Frequency counter. * \ingroup hardware_clocks @@ -206,7 +323,7 @@ uint32_t frequency_count_khz(uint src); * * \see clock_get_hz() */ -void clock_set_reported_hz(enum clock_index clk_index, uint hz); +void clock_set_reported_hz(clock_handle_t clock, uint hz); /// \tag::frequency_count_mhz[] static inline float frequency_count_mhz(uint src) { @@ -258,13 +375,96 @@ static inline void clock_gpio_init(uint gpio, uint src, float div) /*! \brief Configure a clock to come from a gpio input * \ingroup hardware_clocks * - * \param clk_index The clock to configure + * \param clock The clock to configure * \param gpio The GPIO pin to run the clock from. Valid GPIOs are: 20 and 22. * \param src_freq Frequency of the input clock source * \param freq Requested frequency */ -bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq); +bool clock_configure_gpin(clock_handle_t clock, uint gpio, uint32_t src_freq, uint32_t freq); +/*! \brief Initialise the system clock to 48MHz + * \ingroup pico_stdlib + * + * Set the system clock to 48MHz, and set the peripheral clock to match. + */ +void set_sys_clock_48mhz(void); + +/*! \brief Initialise the system clock + * \ingroup pico_stdlib + * + * \param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL + * \param post_div1 The first post divider for the SYS PLL + * \param post_div2 The second post divider for the SYS PLL. + * + * See the PLL documentation in the datasheet for details of driving the PLLs. + */ +void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2); + +/*! \brief Check if a given system clock frequency is valid/attainable + * \ingroup pico_stdlib + * + * \param freq_hz Requested frequency + * \param vco_freq_out On success, the voltage controlled oscillator frequency to be used by the SYS PLL + * \param post_div1_out On success, The first post divider for the SYS PLL + * \param post_div2_out On success, The second post divider for the SYS PLL. + * @return true if the frequency is possible and the output parameters have been written. + */ +bool check_sys_clock_hz(uint32_t freq_hz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out); + +/*! \brief Check if a given system clock frequency is valid/attainable + * \ingroup pico_stdlib + * + * \param freq_khz Requested frequency + * \param vco_freq_out On success, the voltage controlled oscillator frequency to be used by the SYS PLL + * \param post_div1_out On success, The first post divider for the SYS PLL + * \param post_div2_out On success, The second post divider for the SYS PLL. + * @return true if the frequency is possible and the output parameters have been written. + */ +bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out); + +/*! \brief Attempt to set a system clock frequency in hz + * \ingroup pico_stdlib + * + * Note that not all clock frequencies are possible; it is preferred that you + * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters + * for use with set_sys_clock_pll + * + * \param freq_hz Requested frequency + * \param required if true then this function will assert if the frequency is not attainable. + * \return true if the clock was configured + */ +static inline bool set_sys_clock_hz(uint32_t freq_hz, bool required) { + uint vco, postdiv1, postdiv2; + if (check_sys_clock_hz(freq_hz, &vco, &postdiv1, &postdiv2)) { + set_sys_clock_pll(vco, postdiv1, postdiv2); + return true; + } else if (required) { + panic("System clock of %u Hz cannot be exactly achieved", freq_hz); + } + return false; +} + +/*! \brief Attempt to set a system clock frequency in khz + * \ingroup pico_stdlib + * + * Note that not all clock frequencies are possible; it is preferred that you + * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters + * for use with set_sys_clock_pll + * + * \param freq_khz Requested frequency + * \param required if true then this function will assert if the frequency is not attainable. + * \return true if the clock was configured + */ +static inline bool set_sys_clock_khz(uint32_t freq_khz, bool required) { + uint vco, postdiv1, postdiv2; + if (check_sys_clock_khz(freq_khz, &vco, &postdiv1, &postdiv2)) { + set_sys_clock_pll(vco, postdiv1, postdiv2); + return true; + } else if (required) { + panic("System clock of %u kHz cannot be exactly achieved", freq_khz); + } + return false; +} #ifdef __cplusplus } diff --git a/src/rp2_common/hardware_clocks/scripts/vcocalc.py b/src/rp2_common/hardware_clocks/scripts/vcocalc.py index 69f4d029c..08cca4126 100755 --- a/src/rp2_common/hardware_clocks/scripts/vcocalc.py +++ b/src/rp2_common/hardware_clocks/scripts/vcocalc.py @@ -1,30 +1,43 @@ #!/usr/bin/env python3 import argparse +import sys + +# Fixed hardware parameters +fbdiv_range = range(16, 320 + 1) +postdiv_range = range(1, 7 + 1) +ref_min = 5 +refdiv_min = 1 +refdiv_max = 63 + +def validRefdiv(string): + if ((int(string) < refdiv_min) or (int(string) > refdiv_max)): + raise ValueError("REFDIV must be in the range {} to {}".format(refdiv_min, refdiv_max)) + return int(string) parser = argparse.ArgumentParser(description="PLL parameter calculator") parser.add_argument("--input", "-i", default=12, help="Input (reference) frequency. Default 12 MHz", type=float) parser.add_argument("--ref-min", default=5, help="Override minimum reference frequency. Default 5 MHz", type=float) parser.add_argument("--vco-max", default=1600, help="Override maximum VCO frequency. Default 1600 MHz", type=float) parser.add_argument("--vco-min", default=750, help="Override minimum VCO frequency. Default 750 MHz", type=float) +parser.add_argument("--cmake", action="store_true", help="Print out a CMake snippet to apply the selected PLL parameters to your program") +parser.add_argument("--cmake-only", action="store_true", help="Same as --cmake, but do not print anything other than the CMake output") +parser.add_argument("--cmake-executable-name", default="", help="Set the executable name to use in the generated CMake output") +parser.add_argument("--lock-refdiv", help="Lock REFDIV to specified number in the range {} to {}".format(refdiv_min, refdiv_max), type=validRefdiv) parser.add_argument("--low-vco", "-l", action="store_true", help="Use a lower VCO frequency when possible. This reduces power consumption, at the cost of increased jitter") parser.add_argument("output", help="Output frequency in MHz.", type=float) args = parser.parse_args() -# Fixed hardware parameters -fbdiv_range = range(16, 320 + 1) -postdiv_range = range(1, 7 + 1) -ref_min = 5 -refdiv_min = 1 -refdiv_max = 63 - refdiv_range = range(refdiv_min, max(refdiv_min, min(refdiv_max, int(args.input / args.ref_min))) + 1) +if args.lock_refdiv: + print("Locking REFDIV to", args.lock_refdiv) + refdiv_range = [args.lock_refdiv] -best = (0, 0, 0, 0, 0) +best = (0, 0, 0, 0, 0, 0) best_margin = args.output for refdiv in refdiv_range: - for fbdiv in (fbdiv_range if args.low_vco else reversed(fbdiv_range)): + for fbdiv in fbdiv_range: vco = args.input / refdiv * fbdiv if vco < args.vco_min or vco > args.vco_max: continue @@ -33,13 +46,39 @@ for pd1 in postdiv_range: out = vco / pd1 / pd2 margin = abs(out - args.output) - if margin < best_margin: - best = (out, fbdiv, pd1, pd2, refdiv) + vco_is_better = vco < best[5] if args.low_vco else vco > best[5] + if ((vco * 1000) % (pd1 * pd2)): + continue + if margin < best_margin or (abs(margin - best_margin) < 1e-9 and vco_is_better): + best = (out, fbdiv, pd1, pd2, refdiv, vco) best_margin = margin -print("Requested: {} MHz".format(args.output)) -print("Achieved: {} MHz".format(best[0])) -print("REFDIV: {}".format(best[4])) -print("FBDIV: {} (VCO = {} MHz)".format(best[1], args.input / best[4] * best[1])) -print("PD1: {}".format(best[2])) -print("PD2: {}".format(best[3])) +best_out, best_fbdiv, best_pd1, best_pd2, best_refdiv, best_vco = best + +if best[0] > 0: + cmake_output = \ +f"""target_compile_definitions({args.cmake_executable_name} PRIVATE + PLL_SYS_REFDIV={best_refdiv} + PLL_SYS_VCO_FREQ_HZ={int((args.input * 1_000_000) / best_refdiv * best_fbdiv)} + PLL_SYS_POSTDIV1={best_pd1} + PLL_SYS_POSTDIV2={best_pd2} +) +""" + if not args.cmake_only: + print("Requested: {} MHz".format(args.output)) + print("Achieved: {} MHz".format(best_out)) + print("REFDIV: {}".format(best_refdiv)) + print("FBDIV: {} (VCO = {} MHz)".format(best_fbdiv, args.input / best_refdiv * best_fbdiv)) + print("PD1: {}".format(best_pd1)) + print("PD2: {}".format(best_pd2)) + if best_refdiv != 1: + print( + "\nThis requires a non-default REFDIV value.\n" + "Add the following to your CMakeLists.txt to apply the REFDIV:\n" + ) + elif args.cmake or args.cmake_only: + print("") + if args.cmake or args.cmake_only or best_refdiv != 1: + print(cmake_output) +else: + sys.exit("No solution found") diff --git a/src/rp2_common/hardware_dcp/BUILD.bazel b/src/rp2_common/hardware_dcp/BUILD.bazel new file mode 100644 index 000000000..2a267c233 --- /dev/null +++ b/src/rp2_common/hardware_dcp/BUILD.bazel @@ -0,0 +1,13 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_dcp", + hdrs = [ + "include/hardware/dcp_canned.inc.S", + "include/hardware/dcp_instr.inc.S", + ], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), +) diff --git a/src/rp2_common/hardware_dcp/CMakeLists.txt b/src/rp2_common/hardware_dcp/CMakeLists.txt new file mode 100644 index 000000000..20449b1a3 --- /dev/null +++ b/src/rp2_common/hardware_dcp/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_headers_only_target(dcp) diff --git a/src/rp2_common/hardware_dcp/doc.h b/src/rp2_common/hardware_dcp/doc.h new file mode 100644 index 000000000..4ccef81ed --- /dev/null +++ b/src/rp2_common/hardware_dcp/doc.h @@ -0,0 +1,4 @@ +/** + * \defgroup hardware_dcp hardware_dcp + * \brief Assembly macros for the Double Coprocessor + */ diff --git a/src/rp2_common/hardware_dcp/include/hardware/dcp_canned.inc.S b/src/rp2_common/hardware_dcp/include/hardware/dcp_canned.inc.S new file mode 100644 index 000000000..e4fe2fe6f --- /dev/null +++ b/src/rp2_common/hardware_dcp/include/hardware/dcp_canned.inc.S @@ -0,0 +1,420 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Canned instruction sequences for use with the DCP + +.macro dcp_fadd_m rz,rx,ry + WXYU \rx,\ry + ADD0 + ADD1 + NRDF + RDFA \rz +.endm + +.macro dcp_fsub_m rz,rx,ry + WXYU \rx,\ry + ADD0 + SUB1 + NRDF + RDFS \rz +.endm + +.macro dcp_fmul_m rz,rx,ry,ra,rb + WXYU \rx,\ry + RXYH \ra,\rb + umull \ra,\rb,\ra,\rb + WXFM \ra,\rb + NRDF + RDFM \rz +.endm + +.macro dcp_fxprod_m rzl,rzh,rx,ry,ra,rb + WXYU \rx,\ry + RXYH \ra,\rb + umull \ra,\rb,\ra,\rb + WXMO \ra,\rb + NRDD + RDDM \rzl,\rzh +.endm + +.macro dcp_fdiv_fast_m rz,rx,ry,ra,rb,rc + WXYU \rx,\ry + RYMR \ra,\rb + umull \rb,\rc,\ra,\rb + mvn \rc,\rc,lsl #2 + smmlar \ra,\rc,\ra,\ra + smmulr \rc,\rc,\rc + smmlar \ra,\rc,\ra,\ra + RXYH \rb,\rc + umull \ra,\rb,\ra,\rb + WXFD \rb,\rb + NRDF + RDFD \rz +.endm + +.macro dcp_fdiv_m rz,rx,ry,ra,rb,rc,rd + WXYU \rx,\ry + RYMR \ra,\rb + umull \rb,\rc,\ra,\rb + mvn \rc,\rc,lsl #2 + smmlar \ra,\rc,\ra,\ra + smmulr \rc,\rc,\rc + smmlar \ra,\rc,\ra,\ra + RXYH \rb,\rc + umull \rd,\ra,\ra,\rb + orr \ra,\ra,\ra,lsr #24 + bic \ra,\ra,\ra,lsr #25 + bic \ra,\ra,#15 + mov \rc,\rc,lsr #7 + mul \rd,\ra,\rc + rsb \rd,\rd,\rb,lsl #22 + sub \ra,\ra,\rd,lsr #31 + WXFD \ra,\ra + NRDF + RDFD \rz +.endm + +.macro dcp_fsqrt_fast_m rz,rx,ra,rb,rc,rd + WXYU \rx,\rx + SQR0 + RXMQ \rc,\rd + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + mov \rb,\rb,lsl #3 + sub \rb,\rb,#2147483648 + smmlsr \rc,\rc,\rb,\rc + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + movs \ra,\ra,lsr #28 + adc \rb,\ra,\rb,lsl #4 + smmulr \ra,\rb,\rc + sub \rc,\rc,\ra,asr #1 + umull \ra,\rb,\rc,\rd + WXFQ \ra,\rb + NRDF + RDFQ \rz +.endm + +.macro dcp_fsqrt_m rz,rx,ra,rb,rc,rd + WXYU \rx,\rx + SQR0 + RXMQ \rc,\rd + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + mov \rb,\rb,lsl #3 + sub \rb,\rb,#2147483648 + smmlsr \rc,\rc,\rb,\rc + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + movs \ra,\ra,lsr #28 + adc \rb,\ra,\rb,lsl #4 + smmulr \ra,\rb,\rc + sub \rc,\rc,\ra,asr #1 + umull \ra,\rb,\rc,\rd + orr \rb,\rb,#63 + mov \ra,\rb,lsr #5 + mul \ra,\ra,\ra + rsb \ra,\ra,\rd,lsl #18 + bic \rb,\rb,\ra,lsr #26 + WXFQ \ra,\rb + NRDF + RDFQ \rz +.endm + +.macro dcp_fclassify_m rz,rx + WXYU \rx,\rx + RXVD \rz +.endm + +.macro dcp_fcmp_m rz,rx,ry + WXYU \rx,\ry + ADD0 + RCMP \rz +.endm + +.macro dcp_dadd_m rzl,rzh,rxl,rxh,ryl,ryh + WXUP \rxl,\rxh + WYUP \ryl,\ryh + ADD0 + ADD1 + NRDD + RDDA \rzl,\rzh +.endm + +.macro dcp_dsub_m rzl,rzh,rxl,rxh,ryl,ryh + WXUP \rxl,\rxh + WYUP \ryl,\ryh + ADD0 + SUB1 + NRDD + RDDS \rzl,\rzh +.endm + +.macro dcp_dmul_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re,rf,rg + WXUP \rxl,\rxh + WYUP \ryl,\ryh + RXMS \ra,\rb,0 + RYMS \rc,\rd,0 + umull \re,\rf,\ra,\rc + movs \rg,#0 + umlal \rf,\rg,\ra,\rd + umlal \rf,\rg,\rb,\rc + WXMS \re,\rf + movs \re,#0 + umlal \rg,\re,\rb,\rd + WXMO \rg,\re + NRDD + RDDM \rzl,\rzh +.endm + +.macro dcp_ddiv_fast_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re + WXUP \rxl,\rxh + WYUP \ryl,\ryh + RYMR \ra,\rb + umull \rb,\rc,\ra,\rb + mvn \rc,\rc,lsl #2 + smmlar \ra,\rc,\ra,\ra + smmulr \rc,\rc,\rc + smmlar \ra,\rc,\ra,\ra + sub \re,\ra,\ra,lsr #31 + RXMS \rc,\rd,0 + smmulr \rb,\re,\rd + RYMS \rc,\rd,1 + umull \rc,\ra,\rb,\rc + mla \ra,\rb,\rd,\ra + RXMS \rc,\rd,4 + sub \ra,\rc,\ra + smmulr \rc,\ra,\re + mov \rd,\rb,lsr #4 + adds \ra,\rc,\rb,lsl #28 + adc \rb,\rd,\rc,asr #31 + WXDD \ra,\rb + NRDD + RDDD \rzl,\rzh +.endm + +.macro dcp_ddiv_m rzl,rzh,rxl,rxh,ryl,ryh,ra,rb,rc,rd,re + WXUP \rxl,\rxh + WYUP \ryl,\ryh + RYMR \ra,\rb + umull \rb,\rc,\ra,\rb + mvn \rc,\rc,lsl #2 + smmlar \ra,\rc,\ra,\ra + smmulr \rc,\rc,\rc + smmlar \ra,\rc,\ra,\ra + sub \re,\ra,\ra,lsr #31 + RXMS \rc,\rd,0 + smmulr \rb,\re,\rd + RYMS \rc,\rd,1 + umull \rc,\ra,\rb,\rc + mla \ra,\rb,\rd,\ra + RXMS \rc,\rd,4 + sub \ra,\rc,\ra + smmulr \rc,\ra,\re + mov \rd,\rb,lsr #4 + adds \ra,\rc,\rb,lsl #28 + adc \rb,\rd,\rc,asr #31 + orr \ra,\ra,\rb,lsr #21 + bic \ra,\ra,\rb,lsr #22 + bic \ra,\ra,#7 + RYMS \rc,\rd,7 + umull \rd,\re,\ra,\rc + RYMS \rc,\rd,7 + mla \re,\ra,\rd,\re + mla \re,\rb,\rc,\re + RXMS \rc,\rd,0 + sub \re,\re,\rc,lsl #18 + orr \ra,\ra,\re,lsr #29 + sub \ra,\ra,#1 + WXDD \ra,\rb + NRDD + RDDD \rzl,\rzh +.endm + +.macro dcp_dsqrt_fast_m rzl,rzh,rxl,rxh,ra,rb,rc,rd,re + WXUP \rxl,\rxh + SQR0 + RXMQ \rc,\rd + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + mov \rb,\rb,lsl #3 + sub \rb,\rb,#2147483648 + smmlsr \rc,\rc,\rb,\rc + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + movs \ra,\ra,lsr #28 + adc \rb,\ra,\rb,lsl #4 + smmulr \ra,\rb,\rc + sub \rc,\rc,\ra,asr #1 + umull \ra,\rb,\rc,\rd + mov \rb,\rb,lsr #1 + umull \rd,\ra,\rb,\rb + RXMS \ra,\re,6 + sub \ra,\ra,\rd + smmulr \ra,\ra,\rc + add \rb,\rb,\ra,asr #28 + mov \ra,\ra,lsl #4 + WXDQ \ra,\rb + NRDD + RDDQ \rzl,\rzh +.endm + +.macro dcp_dsqrt_m rzl,rzh,rxl,rxh,ra,rb,rc,rd,re + WXUP \rxl,\rxh + SQR0 + RXMQ \rc,\rd + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + mov \rb,\rb,lsl #3 + sub \rb,\rb,#2147483648 + smmlsr \rc,\rc,\rb,\rc + umull \ra,\rb,\rc,\rc + umull \ra,\rb,\rb,\rd + movs \ra,\ra,lsr #28 + adc \rb,\ra,\rb,lsl #4 + smmulr \ra,\rb,\rc + sub \rc,\rc,\ra,asr #1 + umull \ra,\rb,\rc,\rd + mov \rb,\rb,lsr #1 + umull \rd,\ra,\rb,\rb + RXMS \ra,\re,6 + sub \rd,\ra,\rd + smmulr \rd,\rd,\rc + add \rb,\rb,\rd,asr #28 + mov \rd,\rd,lsl #4 + bic \rd,\rd,#255 + orr \rd,\rd,#128 + umull \re,\rc,\rd,\rd + mul \re,\rb,\rb + umlal \rc,\re,\rb,\rd + umlal \rc,\re,\rb,\rd + sub \re,\re,\ra + orr \rd,\rd,\re,lsr #24 + sub \rd,\rd,#11 + WXDQ \rd,\rb + NRDD + RDDQ \rzl,\rzh +.endm + +.macro dcp_dclassify_m rz,rxl,rxh + WXUP \rxl,\rxh + RXVD \rz +.endm + +.macro dcp_dcmp_m rz,rxl,rxh,ryl,ryh + WXUP \rxl,\rxh + WYUP \ryl,\ryh + ADD0 + RCMP \rz +.endm + +.macro dcp_float2double_m rzl,rzh,rx + WXYU \rx,\rx + NRDD + RDDG \rzl,\rzh +.endm + +.macro dcp_double2float_m rz,rxl,rxh + WXUP \rxl,\rxh + NRDF + RDFG \rz +.endm + +.macro dcp_int2double_m rzl,rzh,rx + WXIC \rx,\rx + ADD0 + SUB1 + NRDD + RDDS \rzl,\rzh +.endm + +.macro dcp_uint2double_m rzl,rzh,rx + WXUC \rx,\rx + ADD0 + SUB1 + NRDD + RDDS \rzl,\rzh +.endm + +.macro dcp_int2float_m rz,rx + WXIC \rx,\rx + ADD0 + SUB1 + NRDF + RDFS \rz +.endm + +.macro dcp_uint2float_m rz,rx + WXUC \rx,\rx + ADD0 + SUB1 + NRDF + RDFS \rz +.endm + +.macro dcp_double2int_m rz,rxl,rxh + WXDC \rxl,\rxh + ADD0 + ADD1 + NTDC + RDIC \rz +.endm + +.macro dcp_double2uint_m rz,rxl,rxh + WXDC \rxl,\rxh + ADD0 + ADD1 + NTDC + RDUC \rz +.endm + +.macro dcp_float2int_m rz,rx + WXFC \rx,\rx + ADD0 + ADD1 + NTDC + RDIC \rz +.endm + +.macro dcp_float2uint_m rz,rx + WXFC \rx,\rx + ADD0 + ADD1 + NTDC + RDUC \rz +.endm + +.macro dcp_double2int_r_m rz,rxl,rxh + WXDC \rxl,\rxh + ADD0 + ADD1 + NRDC + RDIC \rz +.endm + +.macro dcp_double2uint_r_m rz,rxl,rxh + WXDC \rxl,\rxh + ADD0 + ADD1 + NRDC + RDUC \rz +.endm + +.macro dcp_float2int_r_m rz,rx + WXFC \rx,\rx + ADD0 + ADD1 + NRDC + RDIC \rz +.endm + +.macro dcp_float2uint_r_m rz,rx + WXFC \rx,\rx + ADD0 + ADD1 + NRDC + RDUC \rz +.endm diff --git a/src/rp2_common/hardware_dcp/include/hardware/dcp_instr.inc.S b/src/rp2_common/hardware_dcp/include/hardware/dcp_instr.inc.S new file mode 100644 index 000000000..2dc2f523c --- /dev/null +++ b/src/rp2_common/hardware_dcp/include/hardware/dcp_instr.inc.S @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +.macro INIT + cdp p4,#0,c0,c0,c0,#0 +.endm +.macro ADD0 + cdp p4,#0,c0,c0,c1,#0 +.endm +.macro ADD1 + cdp p4,#1,c0,c0,c1,#0 +.endm +.macro SUB1 + cdp p4,#1,c0,c0,c1,#1 +.endm +.macro SQR0 + cdp p4,#2,c0,c0,c1,#0 +.endm +.macro NORM + cdp p4,#8,c0,c0,c2,#0 +.endm +.macro NRDF + cdp p4,#8,c0,c0,c2,#1 +.endm +.macro NRDD + cdp p4,#8,c0,c0,c0,#1 +.endm +.macro NTDC + cdp p4,#8,c0,c0,c0,#2 +.endm +.macro NRDC + cdp p4,#8,c0,c0,c0,#3 +.endm +.macro WXMD rl,rh + mcrr p4,#0,\rl,\rh,c0 +.endm +.macro WYMD rl,rh + mcrr p4,#0,\rl,\rh,c1 +.endm +.macro WEFD rl,rh + mcrr p4,#0,\rl,\rh,c2 +.endm +.macro WXUP rl,rh + mcrr p4,#1,\rl,\rh,c0 +.endm +.macro WYUP rl,rh + mcrr p4,#1,\rl,\rh,c1 +.endm +.macro WXYU rl,rh + mcrr p4,#1,\rl,\rh,c2 +.endm +.macro WXMS rl,rh + mcrr p4,#2,\rl,\rh,c0 +.endm +.macro WXMO rl,rh + mcrr p4,#3,\rl,\rh,c0 +.endm +.macro WXDD rl,rh + mcrr p4,#4,\rl,\rh,c0 +.endm +.macro WXDQ rl,rh + mcrr p4,#5,\rl,\rh,c0 +.endm +.macro WXUC rl,rh + mcrr p4,#6,\rl,\rh,c0 +.endm +.macro WXIC rl,rh + mcrr p4,#7,\rl,\rh,c0 +.endm +.macro WXDC rl,rh + mcrr p4,#8,\rl,\rh,c0 +.endm +.macro WXFC rl,rh + mcrr p4,#9,\rl,\rh,c2 +.endm +.macro WXFM rl,rh + mcrr p4,#10,\rl,\rh,c0 +.endm +.macro WXFD rl,rh + mcrr p4,#11,\rl,\rh,c0 +.endm +.macro WXFQ rl,rh + mcrr p4,#12,\rl,\rh,c0 +.endm +.macro RXVD rt + mrc p4,#0,\rt,c0,c0,#0 +.endm +.macro RCMP rt + mrc p4,#0,\rt,c0,c0,#1 +.endm +.macro RDFA rt + mrc p4,#0,\rt,c0,c2,#0 +.endm +.macro RDFS rt + mrc p4,#0,\rt,c0,c2,#1 +.endm +.macro RDFM rt + mrc p4,#0,\rt,c0,c2,#2 +.endm +.macro RDFD rt + mrc p4,#0,\rt,c0,c2,#3 +.endm +.macro RDFQ rt + mrc p4,#0,\rt,c0,c2,#4 +.endm +.macro RDFG rt + mrc p4,#0,\rt,c0,c2,#5 +.endm +.macro RDIC rt + mrc p4,#0,\rt,c0,c3,#0 +.endm +.macro RDUC rt + mrc p4,#0,\rt,c0,c3,#1 +.endm +.macro RXMD rl,rh + mrrc p4,#0,\rl,\rh,c8 +.endm +.macro RYMD rl,rh + mrrc p4,#0,\rl,\rh,c9 +.endm +.macro REFD rl,rh + mrrc p4,#0,\rl,\rh,c10 +.endm +.macro RXMS rl,rh,s + mrrc p4,#\s,\rl,\rh,c4 +.endm +.macro RYMS rl,rh,s + mrrc p4,#\s,\rl,\rh,c5 +.endm +.macro RXYH rl,rh + mrrc p4,#1,\rl,\rh,c1 +.endm +.macro RYMR rl,rh + mrrc p4,#2,\rl,\rh,c1 +.endm +.macro RXMQ rl,rh + mrrc p4,#4,\rl,\rh,c1 +.endm +.macro RDDA rl,rh + mrrc p4,#1,\rl,\rh,c0 +.endm +.macro RDDS rl,rh + mrrc p4,#3,\rl,\rh,c0 +.endm +.macro RDDM rl,rh + mrrc p4,#5,\rl,\rh,c0 +.endm +.macro RDDD rl,rh + mrrc p4,#7,\rl,\rh,c0 +.endm +.macro RDDQ rl,rh + mrrc p4,#9,\rl,\rh,c0 +.endm +.macro RDDG rl,rh + mrrc p4,#11,\rl,\rh,c0 +.endm +.macro PXVD rt + mrc2 p4,#0,\rt,c0,c0,#0 +.endm +.macro PCMP rt + mrc2 p4,#0,\rt,c0,c0,#1 +.endm +.macro PDFA rt + mrc2 p4,#0,\rt,c0,c2,#0 +.endm +.macro PDFS rt + mrc2 p4,#0,\rt,c0,c2,#1 +.endm +.macro PDFM rt + mrc2 p4,#0,\rt,c0,c2,#2 +.endm +.macro PDFD rt + mrc2 p4,#0,\rt,c0,c2,#3 +.endm +.macro PDFQ rt + mrc2 p4,#0,\rt,c0,c2,#4 +.endm +.macro PDFG rt + mrc2 p4,#0,\rt,c0,c2,#5 +.endm +.macro PDIC rt + mrc2 p4,#0,\rt,c0,c3,#0 +.endm +.macro PDUC rt + mrc2 p4,#0,\rt,c0,c3,#1 +.endm +.macro PXMD rl,rh + mrrc2 p4,#0,\rl,\rh,c8 +.endm +.macro PYMD rl,rh + mrrc2 p4,#0,\rl,\rh,c9 +.endm +.macro PEFD rl,rh + mrrc2 p4,#0,\rl,\rh,c10 +.endm +.macro PXMS rl,rh,s + mrrc2 p4,#\s,\rl,\rh,c4 +.endm +.macro PYMS rl,rh,s + mrrc2 p4,#\s,\rl,\rh,c5 +.endm +.macro PXYH rl,rh + mrrc2 p4,#1,\rl,\rh,c1 +.endm +.macro PYMR rl,rh + mrrc2 p4,#2,\rl,\rh,c1 +.endm +.macro PXMQ rl,rh + mrrc2 p4,#4,\rl,\rh,c1 +.endm +.macro PDDA rl,rh + mrrc2 p4,#1,\rl,\rh,c0 +.endm +.macro PDDS rl,rh + mrrc2 p4,#3,\rl,\rh,c0 +.endm +.macro PDDM rl,rh + mrrc2 p4,#5,\rl,\rh,c0 +.endm +.macro PDDD rl,rh + mrrc2 p4,#7,\rl,\rh,c0 +.endm +.macro PDDQ rl,rh + mrrc2 p4,#9,\rl,\rh,c0 +.endm +.macro PDDG rl,rh + mrrc2 p4,#11,\rl,\rh,c0 +.endm + diff --git a/src/rp2_common/hardware_divider/BUILD.bazel b/src/rp2_common/hardware_divider/BUILD.bazel index 72cf37666..30b4b8eec 100644 --- a/src/rp2_common/hardware_divider/BUILD.bazel +++ b/src/rp2_common/hardware_divider/BUILD.bazel @@ -4,7 +4,10 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "hardware_divider", - srcs = ["divider.S"], + srcs = select({ + "//bazel/constraint:rp2040": ["divider.S"], + "//conditions:default": ["divider.c"], + }), hdrs = [ "include/hardware/divider.h", "include/hardware/divider_helper.S", @@ -12,9 +15,8 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", - "//src/rp2_common/pico_platform", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", ], ) diff --git a/src/rp2_common/hardware_divider/CMakeLists.txt b/src/rp2_common/hardware_divider/CMakeLists.txt index 2572a9b14..018391d9c 100644 --- a/src/rp2_common/hardware_divider/CMakeLists.txt +++ b/src/rp2_common/hardware_divider/CMakeLists.txt @@ -1,3 +1,7 @@ pico_simple_hardware_headers_only_target(divider) -target_sources(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.S) +if (PICO_RP2040) + target_sources(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.S) +else() + target_sources(hardware_divider INTERFACE ${CMAKE_CURRENT_LIST_DIR}/divider.c) +endif() target_link_libraries(hardware_divider_headers INTERFACE hardware_structs) \ No newline at end of file diff --git a/src/rp2_common/hardware_divider/divider.S b/src/rp2_common/hardware_divider/divider.S index 9d90e24a9..129233192 100644 --- a/src/rp2_common/hardware_divider/divider.S +++ b/src/rp2_common/hardware_divider/divider.S @@ -2,6 +2,10 @@ #include "hardware/regs/addressmap.h" #include "hardware/regs/sio.h" +#if !PICO_RP2040 +#warning "Building hardware/divider.S on a platform with no SIO divider hardware" +#endif + pico_default_asm_setup // tag::hw_div_s32[] @@ -37,7 +41,7 @@ regular_func_with_section hw_divider_save_state ldr r1, [r3, #SIO_DIV_UDIVIDEND_OFFSET] ldr r2, [r3, #SIO_DIV_UDIVISOR_OFFSET] stmia r0!, {r1-r2} - // The 8 cycles needed to guarantee that the result is ready is ensured by the preceeding + // The 8 cycles needed to guarantee that the result is ready is ensured by the preceding // code of 7 cycles together with any branch to it taking at least 2 cycles. ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET] ldr r2, [r3, #SIO_DIV_QUOTIENT_OFFSET] diff --git a/src/rp2_common/hardware_divider/divider.c b/src/rp2_common/hardware_divider/divider.c new file mode 100644 index 000000000..fc444eee8 --- /dev/null +++ b/src/rp2_common/hardware_divider/divider.c @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/divider.h" + +#if PICO_EMULATE_DIVIDER +divmod_result_t hw_divider_results[NUM_CORES]; +#endif \ No newline at end of file diff --git a/src/rp2_common/hardware_divider/include/hardware/divider.h b/src/rp2_common/hardware_divider/include/hardware/divider.h index c321515b3..de8772dfd 100644 --- a/src/rp2_common/hardware_divider/include/hardware/divider.h +++ b/src/rp2_common/hardware_divider/include/hardware/divider.h @@ -8,12 +8,11 @@ #define _HARDWARE_DIVIDER_H #include "pico.h" -#include "hardware/structs/sio.h" /** \file hardware/divider.h * \defgroup hardware_divider hardware_divider * - * \brief Low-level hardware-divider access + * \brief RP2040 Low Low-level hardware-divider API. Non-RP2040 platforms provide software versions of all the functions * * The SIO contains an 8-cycle signed/unsigned divide/modulo circuit, per core. Calculation is started by writing a dividend * and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient / and remainder % of @@ -29,6 +28,10 @@ * 64 bit divides), and of course by default regular C language integer divisions are redirected through that library, meaning * you can just use C level `/` and `%` operators and gain the benefits of the fast hardware divider. * + * \if rp2350_specific + * On RP2350 there is no hardware divider, and the functions are implemented in software + * \endif + * * @see pico_divider * * \subsection divider_example Example @@ -36,12 +39,62 @@ * \include hello_divider.c */ +#if HAS_SIO_DIVIDER +#include "hardware/structs/sio.h" +#else +#define PICO_EMULATE_DIVIDER 1 +#endif + #ifdef __cplusplus extern "C" { #endif typedef uint64_t divmod_result_t; +#if PICO_EMULATE_DIVIDER +extern divmod_result_t hw_divider_results[NUM_CORES]; + +static inline int __sign_of(int32_t v) { + return v > 0 ? 1 : (v < 0 ? -1 : 0); +} +#endif + +/*! \brief Do a signed HW divide and wait for result + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. + * + * \param a The dividend + * \param b The divisor + * \return Results of divide as a pair of 32-bit quotient/remainder values. + */ +#if !PICO_EMULATE_DIVIDER +divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b); +#else +static inline divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b) { + if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a)); + return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b); +} +#endif + +/*! \brief Do an unsigned HW divide and wait for result + * \ingroup hardware_divider + * + * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. + * + * \param a The dividend + * \param b The divisor + * \return Results of divide as a pair of 32-bit quotient/remainder values. + */ +#if !PICO_EMULATE_DIVIDER +divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b); +#else +static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { + if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this + return (((uint64_t)(a%b))<<32u) | (a/b); +} +#endif + /*! \brief Start a signed asynchronous divide * \ingroup hardware_divider * @@ -52,9 +105,13 @@ typedef uint64_t divmod_result_t; * \param b The divisor */ static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) { +#if !PICO_EMULATE_DIVIDER check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET); sio_hw->div_sdividend = (uint32_t)a; sio_hw->div_sdivisor = (uint32_t)b; +#else + hw_divider_divmod_s32(a, b); +#endif } /*! \brief Start an unsigned asynchronous divide @@ -67,10 +124,14 @@ static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) { * \param b The divisor */ static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { +#if !PICO_EMULATE_DIVIDER check_hw_layout( sio_hw_t, div_udividend, SIO_DIV_UDIVIDEND_OFFSET); sio_hw->div_udividend = a; sio_hw->div_udivisor = b; +#else + hw_divider_divmod_u32(a, b); +#endif } /*! \brief Wait for a divide to complete @@ -79,6 +140,7 @@ static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { * Wait for a divide to complete */ static inline void hw_divider_wait_ready(void) { +#if !PICO_EMULATE_DIVIDER // this is #1 in lsr below static_assert(SIO_DIV_CSR_READY_BITS == 1, ""); @@ -92,8 +154,9 @@ static inline void hw_divider_wait_ready(void) { "bcc hw_divider_result_loop_%=\n\t" : "=&l" (tmp) : "l" (sio_hw), "I" (SIO_DIV_CSR_OFFSET) - : + : "cc" ); +#endif } /*! \brief Return result of HW divide, nowait @@ -104,10 +167,14 @@ static inline void hw_divider_wait_ready(void) { * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient. */ static inline divmod_result_t hw_divider_result_nowait(void) { +#if !PICO_EMULATE_DIVIDER // as ugly as this looks it is actually quite efficient divmod_result_t rc = ((divmod_result_t) sio_hw->div_remainder) << 32u; rc |= sio_hw->div_quotient; return rc; +#else + return hw_divider_results[get_core_num()]; +#endif } /*! \brief Return result of last asynchronous HW divide @@ -122,6 +189,51 @@ static inline divmod_result_t hw_divider_result_wait(void) { return hw_divider_result_nowait(); } +/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r A pair of 32-bit quotient/remainder values. + * \return Unsigned quotient + */ +inline static uint32_t to_quotient_u32(divmod_result_t r) { + return (uint32_t) r; +} + +/*! \brief Efficient extraction of signed quotient from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r A pair of 32-bit quotient/remainder values. + * \return Unsigned quotient + */ +inline static int32_t to_quotient_s32(divmod_result_t r) { + return (int32_t)(uint32_t)r; +} + +/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r A pair of 32-bit quotient/remainder values. + * \return Unsigned remainder + * + * \note On Arm this is just a 32 bit register move or a nop + */ +inline static uint32_t to_remainder_u32(divmod_result_t r) { + return (uint32_t)(r >> 32u); +} + +/*! \brief Efficient extraction of signed remainder from 32p32 fixed point + * \ingroup hardware_divider + * + * \param r A pair of 32-bit quotient/remainder values. + * \return Signed remainder + * + * \note On arm this is just a 32 bit register move or a nop + */ +inline static int32_t to_remainder_s32(divmod_result_t r) { + return (int32_t)(r >> 32u); +} + + /*! \brief Return result of last asynchronous HW divide, unsigned quotient only * \ingroup hardware_divider * @@ -130,8 +242,12 @@ static inline divmod_result_t hw_divider_result_wait(void) { * \return Current unsigned quotient result. */ static inline uint32_t hw_divider_u32_quotient_wait(void) { +#if !PICO_EMULATE_DIVIDER hw_divider_wait_ready(); return sio_hw->div_quotient; +#else + return to_quotient_u32(hw_divider_result_wait()); +#endif } /*! \brief Return result of last asynchronous HW divide, signed quotient only @@ -142,8 +258,12 @@ static inline uint32_t hw_divider_u32_quotient_wait(void) { * \return Current signed quotient result. */ static inline int32_t hw_divider_s32_quotient_wait(void) { +#if !PICO_EMULATE_DIVIDER hw_divider_wait_ready(); return (int32_t)sio_hw->div_quotient; +#else + return to_quotient_s32(hw_divider_result_wait()); +#endif } /*! \brief Return result of last asynchronous HW divide, unsigned remainder only @@ -154,10 +274,14 @@ static inline int32_t hw_divider_s32_quotient_wait(void) { * \return Current unsigned remainder result. */ static inline uint32_t hw_divider_u32_remainder_wait(void) { +#if !PICO_EMULATE_DIVIDER hw_divider_wait_ready(); uint32_t rc = sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; +#else + return to_remainder_u32(hw_divider_result_wait()); +#endif } /*! \brief Return result of last asynchronous HW divide, signed remainder only @@ -168,76 +292,14 @@ static inline uint32_t hw_divider_u32_remainder_wait(void) { * \return Current remainder results. */ static inline int32_t hw_divider_s32_remainder_wait(void) { +#if !PICO_EMULATE_DIVIDER hw_divider_wait_ready(); int32_t rc = (int32_t)sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; -} - -/*! \brief Do a signed HW divide and wait for result - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. - * - * \param a The dividend - * \param b The divisor - * \return Results of divide as a pair of 32-bit quotient/remainder values. - */ -divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b); - -/*! \brief Do an unsigned HW divide and wait for result - * \ingroup hardware_divider - * - * Divide \p a by \p b, wait for calculation to complete, return result as a pair of 32-bit quotient/remainder values. - * - * \param a The dividend - * \param b The divisor - * \return Results of divide as a pair of 32-bit quotient/remainder values. - */ -divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b); - -/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Unsigned quotient - */ -inline static uint32_t to_quotient_u32(divmod_result_t r) { - return (uint32_t) r; -} - -/*! \brief Efficient extraction of signed quotient from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Unsigned quotient - */ -inline static int32_t to_quotient_s32(divmod_result_t r) { - return (int32_t)(uint32_t)r; -} - -/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Unsigned remainder - * - * \note On Arm this is just a 32 bit register move or a nop - */ -inline static uint32_t to_remainder_u32(divmod_result_t r) { - return (uint32_t)(r >> 32u); -} - -/*! \brief Efficient extraction of signed remainder from 32p32 fixed point - * \ingroup hardware_divider - * - * \param r A pair of 32-bit quotient/remainder values. - * \return Signed remainder - * - * \note On arm this is just a 32 bit register move or a nop - */ -inline static int32_t to_remainder_s32(divmod_result_t r) { - return (int32_t)(r >> 32u); +#else + return to_remainder_s32(hw_divider_result_wait()); +#endif } /*! \brief Do an unsigned HW divide, wait for result, return quotient @@ -250,7 +312,11 @@ inline static int32_t to_remainder_s32(divmod_result_t r) { * \return Quotient results of the divide */ static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) { +#if !PICO_EMULATE_DIVIDER return to_quotient_u32(hw_divider_divmod_u32(a, b)); +#else + return b ? (a / b) : (uint32_t)(-1); +#endif } /*! \brief Do an unsigned HW divide, wait for result, return remainder @@ -263,7 +329,11 @@ static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) { * \return Remainder results of the divide */ static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) { +#if !PICO_EMULATE_DIVIDER return to_remainder_u32(hw_divider_divmod_u32(a, b)); +#else + return b ? (a % b) : a; +#endif } /*! \brief Do a signed HW divide, wait for result, return quotient @@ -276,7 +346,11 @@ static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) { * \return Quotient results of the divide */ static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) { +#if !PICO_EMULATE_DIVIDER return to_quotient_s32(hw_divider_divmod_s32(a, b)); +#else + return b ? (a / b) : -1; +#endif } /*! \brief Do a signed HW divide, wait for result, return remainder @@ -289,13 +363,18 @@ static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) { * \return Remainder results of the divide */ static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) { +#if !PICO_EMULATE_DIVIDER return to_remainder_s32(hw_divider_divmod_s32(a, b)); +#else + return b ? (a % b) : a; +#endif } /*! \brief Pause for exact amount of time needed for a asynchronous divide to complete * \ingroup hardware_divider */ static inline void hw_divider_pause(void) { +#if !PICO_EMULATE_DIVIDER pico_default_asm_volatile( "b _1_%=\n" "_1_%=:\n" @@ -306,6 +385,7 @@ static inline void hw_divider_pause(void) { "b _4_%=\n" "_4_%=:\n" :::); +#endif } /*! \brief Do a hardware unsigned HW divide, wait for result, return quotient @@ -318,9 +398,13 @@ static inline void hw_divider_pause(void) { * \return Quotient result of the divide */ static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) { +#if !PICO_EMULATE_DIVIDER hw_divider_divmod_u32_start(a, b); hw_divider_pause(); return sio_hw->div_quotient; +#else + return hw_divider_u32_quotient(a,b); +#endif } /*! \brief Do a hardware unsigned HW divide, wait for result, return remainder @@ -333,11 +417,15 @@ static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) { * \return Remainder result of the divide */ static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) { +#if !PICO_EMULATE_DIVIDER hw_divider_divmod_u32_start(a, b); hw_divider_pause(); uint32_t rc = sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; +#else + return hw_divider_u32_remainder(a,b); +#endif } /*! \brief Do a hardware signed HW divide, wait for result, return quotient @@ -350,9 +438,13 @@ static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) * \return Quotient result of the divide */ static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { +#if !PICO_EMULATE_DIVIDER hw_divider_divmod_s32_start(a, b); hw_divider_pause(); return (int32_t)sio_hw->div_quotient; +#else + return hw_divider_quotient_s32(a,b); +#endif } /*! \brief Do a hardware signed HW divide, wait for result, return remainder @@ -365,16 +457,24 @@ static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) { * \return Remainder result of the divide */ static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) { +#if !PICO_EMULATE_DIVIDER hw_divider_divmod_s32_start(a, b); hw_divider_pause(); int32_t rc = (int32_t)sio_hw->div_remainder; sio_hw->div_quotient; // must read quotient to cooperate with other SDK code return rc; +#else + return hw_divider_remainder_s32(a,b); +#endif } +#if !PICO_EMULATE_DIVIDER typedef struct { uint32_t values[4]; } hw_divider_state_t; +#else +typedef uint64_t hw_divider_state_t; +#endif /*! \brief Save the calling cores hardware divider state * \ingroup hardware_divider @@ -385,7 +485,13 @@ typedef struct { * * \param dest the location to store the divider state */ +#if !PICO_EMULATE_DIVIDER void hw_divider_save_state(hw_divider_state_t *dest); +#else +static inline void hw_divider_save_state(hw_divider_state_t *dest) { + *dest = hw_divider_results[get_core_num()]; +} +#endif /*! \brief Load a saved hardware divider state into the current core's hardware divider * \ingroup hardware_divider @@ -394,8 +500,13 @@ void hw_divider_save_state(hw_divider_state_t *dest); * * \param src the location to load the divider state from */ - +#if !PICO_EMULATE_DIVIDER void hw_divider_restore_state(hw_divider_state_t *src); +#else +static inline void hw_divider_restore_state(hw_divider_state_t *src) { + hw_divider_results[get_core_num()] = *src; +} +#endif #ifdef __cplusplus } diff --git a/src/rp2_common/hardware_dma/BUILD.bazel b/src/rp2_common/hardware_dma/BUILD.bazel index 4e0c75369..7adbd39f6 100644 --- a/src/rp2_common/hardware_dma/BUILD.bazel +++ b/src/rp2_common/hardware_dma/BUILD.bazel @@ -9,9 +9,9 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", - "//src/rp2_common/hardware_claim", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/common/hardware_claim", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", ], ) diff --git a/src/rp2_common/hardware_dma/dma.c b/src/rp2_common/hardware_dma/dma.c index f306def8b..5c405959f 100644 --- a/src/rp2_common/hardware_dma/dma.c +++ b/src/rp2_common/hardware_dma/dma.c @@ -105,8 +105,8 @@ void print_dma_ctrl(dma_channel_hw_t *channel) { } #endif -#if PARAM_ASSERTIONS_ENABLED(DMA) +#if PARAM_ASSERTIONS_ENABLED(HARDWARE_DMA) void check_dma_channel_param_impl(uint __unused channel) { - valid_params_if(DMA, channel < NUM_DMA_CHANNELS); + valid_params_if(HARDWARE_DMA, channel < NUM_DMA_CHANNELS); } #endif diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h index f6643a260..dd940ffc7 100644 --- a/src/rp2_common/hardware_dma/include/hardware/dma.h +++ b/src/rp2_common/hardware_dma/include/hardware/dma.h @@ -11,6 +11,7 @@ #include "hardware/structs/dma.h" #include "hardware/regs/dreq.h" #include "pico/assert.h" +#include "hardware/regs/intctrl.h" #ifdef __cplusplus extern "C" { @@ -21,9 +22,9 @@ extern "C" { * * \brief DMA Controller API * - * The RP2040 Direct Memory Access (DMA) master performs bulk data transfers on a processor’s + * The RP-series microcontroller Direct Memory Access (DMA) master performs bulk data transfers on a processor’s * behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states. The - * data throughput of the DMA is also significantly higher than one of RP2040’s processors. + * data throughput of the DMA is also significantly higher than one of RP-series microcontroller’s processors. * * The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle. * There are 12 independent channels, which each supervise a sequence of bus transfers, usually in @@ -34,20 +35,29 @@ extern "C" { * * Memory to memory */ -// these are not defined in generated dreq.h -#define DREQ_DMA_TIMER0 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 -#define DREQ_DMA_TIMER1 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 -#define DREQ_DMA_TIMER2 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 -#define DREQ_DMA_TIMER3 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 -#define DREQ_FORCE DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA, Enable/disable hardware_dma assertions, type=bool, default=0, group=hardware_dma +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA +#ifdef PARAM_ASSERTIONS_ENABLED_DMA // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA PARAM_ASSERTIONS_ENABLED_DMA +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA 0 +#endif +#endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma -#ifndef PARAM_ASSERTIONS_ENABLED_DMA -#define PARAM_ASSERTIONS_ENABLED_DMA 0 +/** + * \def DMA_IRQ_NUM(n) + * \ingroup hardware_dma + * \hideinitializer + * \brief Returns the \ref irq_num_t for the nth DMA interrupt + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef DMA_IRQ_NUM +#define DMA_IRQ_NUM(irq_index) (DMA_IRQ_0 + (irq_index)) #endif static inline void check_dma_channel_param(__unused uint channel) { -#if PARAM_ASSERTIONS_ENABLED(DMA) +#if PARAM_ASSERTIONS_ENABLED(HARDWARE_DMA) // this method is used a lot by inline functions so avoid code bloat by deferring to function extern void check_dma_channel_param_impl(uint channel); check_dma_channel_param_impl(channel); @@ -55,7 +65,7 @@ static inline void check_dma_channel_param(__unused uint channel) { } static inline void check_dma_timer_param(__unused uint timer_num) { - valid_params_if(DMA, timer_num < NUM_DMA_TIMERS); + valid_params_if(HARDWARE_DMA, timer_num < NUM_DMA_TIMERS); } inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) { @@ -478,7 +488,7 @@ inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile voi * \param chan_mask Bitmask of all the channels requiring starting. Channel 0 = bit 0, channel 1 = bit 1 etc. */ static inline void dma_start_channel_mask(uint32_t chan_mask) { - valid_params_if(DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS)); + valid_params_if(HARDWARE_DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS)); dma_hw->multi_channel_trigger = chan_mask; } @@ -496,10 +506,12 @@ static inline void dma_channel_start(uint channel) { * * Function will only return once the DMA has stopped. * - * Note that due to errata RP2040-E13, aborting a channel which has transfers + * \if rp2040_specific + * RP2040 only: Note that due to errata RP2040-E13, aborting a channel which has transfers * in-flight (i.e. an individual read has taken place but the corresponding write has not), the ABORT * status bit will clear prematurely, and subsequently the in-flight * transfers will trigger a completion interrupt once they complete. + *\endif * * The effect of this is that you \em may see a spurious completion interrupt * on the channel as a result of calling this method. @@ -522,6 +534,11 @@ static inline void dma_channel_start(uint channel) { * dma_channel_set_irq0_enabled(channel, true); *\endcode * + * \if rp2350_specific + * RP2350 only: Due to errata RP12350-E5 (see the RP2350 datasheet for further detail), it is necessary to clear the enable bit of + * the aborted channel and any chained channels prior to the abort to prevent re-triggering. + * \endif + * * \param channel DMA channel */ static inline void dma_channel_abort(uint channel) { @@ -598,12 +615,12 @@ static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool * \param enabled true to enable interrupt via irq_index for specified channel, false to disable. */ static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) { - invalid_params_if(DMA, irq_index > 1); - if (irq_index) { - dma_channel_set_irq1_enabled(channel, enabled); - } else { - dma_channel_set_irq0_enabled(channel, enabled); - } + invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); + + if (enabled) + hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel); + else + hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel); } /*! \brief Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1 @@ -614,11 +631,11 @@ static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bo * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask. */ static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) { - invalid_params_if(DMA, irq_index > 1); - if (irq_index) { - dma_set_irq1_channel_mask_enabled(channel_mask, enabled); + invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); + if (enabled) { + hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask); } else { - dma_set_irq0_channel_mask_enabled(channel_mask, enabled); + hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask); } } @@ -652,9 +669,9 @@ static inline bool dma_channel_get_irq1_status(uint channel) { * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise */ static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) { - invalid_params_if(DMA, irq_index > 1); + invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); check_dma_channel_param(channel); - return (irq_index ? dma_hw->ints1 : dma_hw->ints0) & (1u << channel); + return dma_hw->irq_ctrl[irq_index].ints & (1u << channel); } /*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0 @@ -684,12 +701,9 @@ static inline void dma_channel_acknowledge_irq1(uint channel) { * \param channel DMA channel */ static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) { - invalid_params_if(DMA, irq_index > 1); + invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS); check_dma_channel_param(channel); - if (irq_index) - dma_hw->ints1 = 1u << channel; - else - dma_hw->ints0 = 1u << channel; + dma_hw->irq_ctrl[irq_index].ints = 1u << channel; } /*! \brief Check if DMA channel is busy @@ -700,7 +714,7 @@ static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) { */ inline static bool dma_channel_is_busy(uint channel) { check_dma_channel_param(channel); - return !!(dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS); + return dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS; } /*! \brief Wait for a DMA channel transfer to complete @@ -710,7 +724,7 @@ inline static bool dma_channel_is_busy(uint channel) { */ inline static void dma_channel_wait_for_finish_blocking(uint channel) { while (dma_channel_is_busy(channel)) tight_loop_contents(); - // stop the compiler hoisting a non volatile buffer access above the DMA completion. + // stop the compiler hoisting a non-volatile buffer access above the DMA completion. __compiler_memory_barrier(); } @@ -876,7 +890,7 @@ bool dma_timer_is_claimed(uint timer); */ static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) { check_dma_timer_param(timer); - invalid_params_if(DMA, numerator > denominator); + invalid_params_if(HARDWARE_DMA, numerator > denominator); dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB); } @@ -893,6 +907,17 @@ static inline uint dma_get_timer_dreq(uint timer_num) { return DREQ_DMA_TIMER0 + timer_num; } +/*! \brief Return DMA_IRQ_ + * \ingroup hardware_dma + * + * \param irq_index 0 the DMA irq index + * \return The \ref irq_num_to use for DMA + */ +static inline int dma_get_irq_num(uint irq_index) { + valid_params_if(HARDWARE_DMA, irq_index < NUM_DMA_IRQS); + return DMA_IRQ_NUM(irq_index); +} + /*! \brief Performs DMA channel cleanup after use * \ingroup hardware_dma * diff --git a/src/rp2_common/hardware_exception/BUILD.bazel b/src/rp2_common/hardware_exception/BUILD.bazel index b19f9cff6..ddbc0f67a 100644 --- a/src/rp2_common/hardware_exception/BUILD.bazel +++ b/src/rp2_common/hardware_exception/BUILD.bazel @@ -9,10 +9,16 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", + "//src/rp2_common:platform_defs", "//src/rp2_common/hardware_base", "//src/rp2_common/hardware_sync", - "//src/rp2_common/pico_platform:hardware_structs", - "//src/rp2_common/pico_platform:platform_defs", ], ) + +# TODO: RISC-V support. +filegroup( + name = "exception_table_riscv", + srcs = ["exception_table_riscv.S"], +) diff --git a/src/rp2_common/hardware_exception/CMakeLists.txt b/src/rp2_common/hardware_exception/CMakeLists.txt index 481ebf93f..25268ddf1 100644 --- a/src/rp2_common/hardware_exception/CMakeLists.txt +++ b/src/rp2_common/hardware_exception/CMakeLists.txt @@ -1,2 +1,9 @@ pico_simple_hardware_target(exception) -pico_mirrored_target_link_libraries(hardware_exception INTERFACE hardware_sync) \ No newline at end of file +pico_mirrored_target_link_libraries(hardware_exception INTERFACE hardware_sync) + +if (PICO_RISCV) + target_compile_definitions(hardware_exception INTERFACE PICO_CRT0_NO_ISR_RISCV_MACHINE_EXCEPTION=1) + target_sources(hardware_exception INTERFACE + exception_table_riscv.S + ) +endif() \ No newline at end of file diff --git a/src/rp2_common/hardware_exception/exception.c b/src/rp2_common/hardware_exception/exception.c index 8e141a698..2c318e462 100644 --- a/src/rp2_common/hardware_exception/exception.c +++ b/src/rp2_common/hardware_exception/exception.c @@ -5,38 +5,46 @@ */ #include "hardware/exception.h" -#include "hardware/platform_defs.h" -#include "hardware/structs/scb.h" #include "hardware/sync.h" -#include "pico/assert.h" +#include "pico/platform/cpu_regs.h" #ifndef exception_is_compile_time_default static bool exception_is_compile_time_default(exception_handler_t handler) { +#ifdef __riscv + extern char __unhandled_exception; + return (uintptr_t)handler == (uintptr_t)__unhandled_exception; +#else extern char __default_isrs_start; extern char __default_isrs_end; return ((uintptr_t)handler) >= (uintptr_t)&__default_isrs_start && ((uintptr_t)handler) < (uintptr_t)&__default_isrs_end; +#endif } #endif -static inline exception_handler_t *get_vtable(void) { +static inline exception_handler_t *get_exception_table(void) { +#ifdef __riscv + extern uintptr_t __riscv_exception_table; + return (exception_handler_t *) &__riscv_exception_table; +#else return (exception_handler_t *) scb_hw->vtor; +#endif } static void set_raw_exception_handler_and_restore_interrupts(enum exception_number num, exception_handler_t handler, uint32_t save) { // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness) - get_vtable()[16 + num] = handler; + get_exception_table()[num] = handler; __dmb(); - restore_interrupts(save); + restore_interrupts_from_disabled(save); } static inline void check_exception_param(__unused enum exception_number num) { - invalid_params_if(EXCEPTION, num < NMI_EXCEPTION || num >=0); + invalid_params_if(HARDWARE_EXCEPTION, num < MIN_EXCEPTION_NUM || num >= MAX_EXCEPTION_NUM); } exception_handler_t exception_get_vtable_handler(enum exception_number num) { check_exception_param(num); - return get_vtable()[16 + num]; + return get_exception_table()[num]; } exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler) { @@ -60,4 +68,38 @@ void exception_restore_handler(enum exception_number num, exception_handler_t or #else panic_unsupported(); #endif -} \ No newline at end of file +} + +#ifndef __riscv + +static io_rw_32 *get_shpr0(uint num) { + io_rw_32 *shpr0 = NULL; +#if __ARM_ARCH_6M__ + // only has shpr2-3 + if (num >= 8 && num < 16) shpr0 = (io_rw_32 *) (PPB_BASE + ARM_CPU_PREFIXED(SHPR2_OFFSET) - 8); +#elif __ARM_ARCH_8M_MAIN__ + // only has shpr1-3 + if (num >= 4 && num < 16) shpr0 = (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(SHPR1_OFFSET) - 4); +#endif + return shpr0; +} + +bool exception_set_priority(uint num, uint8_t hardware_priority) { + io_rw_32 *shpr0 = get_shpr0(num); + if (shpr0) { + // note that only 32 bit writes are supported + shpr0[num / 4] = (shpr0[num/4] & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u))); + return true; + } + return false; +} + +uint exception_get_priority(uint num) { + io_rw_32 *shpr0 = get_shpr0(num); + if (shpr0) { + // note that only 32 bit writes are supported + return (uint8_t) (shpr0[num/4] >> (8 * (num & 3))); + } + return PICO_LOWEST_EXCEPTION_PRIORITY; +} +#endif \ No newline at end of file diff --git a/src/rp2_common/hardware_exception/exception_table_riscv.S b/src/rp2_common/hardware_exception/exception_table_riscv.S new file mode 100644 index 000000000..1bd24c910 --- /dev/null +++ b/src/rp2_common/hardware_exception/exception_table_riscv.S @@ -0,0 +1,135 @@ +#include "pico/asm_helper.S" + +// Support for breaking out individual RISC-V exception causes to handlers +// implemented as normal C functions. Note the handler is still responsible +// for incrementing `mepc` before return, if it intends to return to the +// instruction after the one that caused the exception. + +.macro decl_isr name +.weak \name +\name: +.endm + +// must be in RAM due to branches from vector table +.section .time_critical.hardware_exception + +.p2align 2 +.global __riscv_exception_table +__riscv_exception_table: +.word isr_riscv_machine_instr_align_exception +.word isr_riscv_machine_instr_fault_exception +.word isr_riscv_machine_instr_illegal_exception +.word isr_riscv_machine_ebreak_exception +.word isr_riscv_machine_load_align_exception +.word isr_riscv_machine_load_fault_exception +.word isr_riscv_machine_store_align_exception +.word isr_riscv_machine_store_fault_exception +.word isr_riscv_machine_ecall_umode_exception +.word isr_riscv_machine_ecall_smode_exception +.word __unhandled_exception // reserved +.word isr_riscv_machine_ecall_mmode_exception + +// mscratch = 0 outside of exception handler. mscratch = user ra during +// exception handler. Assume 0 is not a valid ra. +.global isr_riscv_machine_exception +// still allow override just in case hardware_exception is pulled in by a library +// note: that when LIX_HARDWARE_EXCEPTION=1, crt0_riscv.S does not define its own weak method +.weak isr_riscv_machine_exception +isr_riscv_machine_exception: + csrrw ra, mscratch, ra + bnez ra, __nested_exception + // Exception handler runs on foreground stack: this may fault, but we will + // catch the fault and go to __nested_exception. + addi sp, sp, -64 + // Work downward, to ensure that after tripping a stack guard PMP region + // we re-trip it before trashing memory below the guard. + sw t6, 60(sp) + sw t5, 56(sp) + sw t4, 52(sp) + sw t3, 48(sp) + sw a7, 44(sp) + sw a6, 40(sp) + sw a5, 36(sp) + sw a4, 32(sp) + sw a3, 28(sp) + sw a2, 24(sp) + sw a1, 20(sp) + sw a0, 16(sp) + sw t2, 12(sp) + sw t1, 8(sp) + sw t0, 4(sp) + // ra already saved + + // Using unsigned comparison for double-ended bounds check + csrr ra, mcause + li t6, 11 // XCAUSE_ECALL_M + bltu t6, ra, __unhandled_exception + + // Enter exception through table + la t6, __riscv_exception_table + sh2add ra, ra, t6 + lw ra, (ra) + jalr ra, ra + + // Restore saved registers + lw t6, 60(sp) + lw t5, 56(sp) + lw t4, 52(sp) + lw t3, 48(sp) + lw a7, 44(sp) + lw a6, 40(sp) + lw a5, 36(sp) + lw a4, 32(sp) + lw a3, 28(sp) + lw a2, 24(sp) + lw a1, 20(sp) + lw a0, 16(sp) + lw t2, 12(sp) + lw t1, 8(sp) + lw t0, 4(sp) + // ra restored from mscratch + addi sp, sp, 64 + + // Restore mscratch to 0 to avoid tripping next exception + csrrw ra, mscratch, zero + mret + +decl_isr isr_riscv_machine_instr_align_exception +decl_isr isr_riscv_machine_instr_fault_exception +decl_isr isr_riscv_machine_instr_illegal_exception +decl_isr isr_riscv_machine_ebreak_exception +decl_isr isr_riscv_machine_load_align_exception +decl_isr isr_riscv_machine_load_fault_exception +decl_isr isr_riscv_machine_store_align_exception +decl_isr isr_riscv_machine_store_fault_exception +decl_isr isr_riscv_machine_ecall_umode_exception +decl_isr isr_riscv_machine_ecall_smode_exception +decl_isr isr_riscv_machine_ecall_mmode_exception + // fall through + +// Reach here when executing an exception that did not have a non-default +// handler assigned. Since a breakpoint will cause another exception if the +// debugger is not connected, we can't have an ebreak here. Just spin the +// core forever. You can check `mcause` and `mepc` to see what happened and +// where. +.global __unhandled_exception +__unhandled_exception: + // Restore original registers and stack pointer so debugger can backtrace + csrr ra, mscratch + lw t6, 60(sp) + addi sp, sp, -64 + // Second symbol here just to make it clearer in the debugger why you got + // here; the entry point can appear labelled with the name of any one of the + // unhandled exceptions, which is less clear. +.global __halt_on_unhandled_exception +__halt_on_unhandled_exception: +1: + j 1b + +// Detected an exception occurring whilst running an exception handler. State +// of original exception was trashed by new exception, so this is not +// recoverable. Best we can do is to halt now to avoid further trashing. +__nested_exception: +1: + j 1b + diff --git a/src/rp2_common/hardware_exception/include/hardware/exception.h b/src/rp2_common/hardware_exception/include/hardware/exception.h index 92cd2643d..377ec0156 100644 --- a/src/rp2_common/hardware_exception/include/hardware/exception.h +++ b/src/rp2_common/hardware_exception/include/hardware/exception.h @@ -23,37 +23,83 @@ * \note That all exception APIs affect the executing core only (i.e. the core calling the function). */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_EXCEPTION, Enable/disable assertions in the exception module, type=bool, default=0, group=hardware_exception -#ifndef PARAM_ASSERTIONS_ENABLED_EXCEPTION -#define PARAM_ASSERTIONS_ENABLED_EXCEPTION 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION, Enable/disable assertions in the hardware_exception module, type=bool, default=0, group=hardware_exception +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION +#ifdef PARAM_ASSERTIONS_ENABLED_EXCEPTION // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION PARAM_ASSERTIONS_ENABLED_EXCEPTION +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_EXCEPTION 0 +#endif #endif - #ifdef __cplusplus extern "C" { #endif /*! \brief Exception number definitions * - * Note for consistency with irq numbers, these numbers are defined to be negative. The VTABLE index is - * the number here plus 16. + * On Arm these are vector table indices: * * Name | Value | Exception - * ---------------------|-------|---------- - * NMI_EXCEPTION | -14 | Non Maskable Interrupt - * HARDFAULT_EXCEPTION | -13 | HardFault - * SVCALL_EXCEPTION | -5 | SV Call - * PENDSV_EXCEPTION | -2 | Pend SV - * SYSTICK_EXCEPTION | -1 | System Tick + * ---------------------|-------|----------------------- + * NMI_EXCEPTION | 2 | Non Maskable Interrupt + * HARDFAULT_EXCEPTION | 3 | HardFault + * SVCALL_EXCEPTION | 11 | SV Call + * PENDSV_EXCEPTION | 14 | Pend SV + * SYSTICK_EXCEPTION | 15 | System Tick + * + * \if rp2350_specific + * On RISC-V these are exception cause numbers: + * + * Name | Value | Exception + * ------------------------|-------|----------------------------- + * INSTR_ALIGN_EXCEPTION | 0 | Instruction fetch misaligned + * INSTR_FAULT_EXCEPTION | 1 | Instruction fetch bus fault + * INSTR_ILLEGAL_EXCEPTION | 2 | Invalid or illegal instruction + * EBREAK_EXCEPTION | 3 | ebreak was not caught by an ex + * LOAD_ALIGN_EXCEPTION | 4 | Load address not naturally ali + * LOAD_FAULT_EXCEPTION | 5 | Load bus fault + * STORE_ALIGN_EXCEPTION | 6 | Store or AMO address not natur + * STORE_FAULT_EXCEPTION | 7 | Store or AMO bus fault + * ECALL_UMODE_EXCEPTION | 8 | ecall was executed in U-mode + * ECALL_SMODE_EXCEPTION | 9 | ecall was executed in S-mode + * ECALL_MMODE_EXCEPTION | 11 | ecall was executed in M-mode + * \endif * * \ingroup hardware_exception */ +#ifdef __riscv enum exception_number { - NMI_EXCEPTION = -14, /* Non Maskable Interrupt */ - HARDFAULT_EXCEPTION = -13, /* HardFault Interrupt */ - SVCALL_EXCEPTION = -5, /* SV Call Interrupt */ - PENDSV_EXCEPTION = -2, /* Pend SV Interrupt */ - SYSTICK_EXCEPTION = -1, /* System Tick Interrupt */ + // Assigned to non-IRQ xcause values + MIN_EXCEPTION_NUM = 0, + INSTR_ALIGN_EXCEPTION = 0, ///< Instruction fetch misaligned (never fires if C/Zca is present) + INSTR_FAULT_EXCEPTION = 1, ///< Instruction fetch bus fault + INSTR_ILLEGAL_EXCEPTION = 2, ///< Invalid or illegal instruction + EBREAK_EXCEPTION = 3, ///< ebreak was not caught by an external debugger + LOAD_ALIGN_EXCEPTION = 4, ///< Load address not naturally aligned + LOAD_FAULT_EXCEPTION = 5, ///< Load bus fault + STORE_ALIGN_EXCEPTION = 6, ///< Store or AMO address not naturally aligned + STORE_FAULT_EXCEPTION = 7, ///< Store or AMO bus fault + ECALL_UMODE_EXCEPTION = 8, ///< ecall was executed in U-mode + ECALL_SMODE_EXCEPTION = 9, ///< ecall was executed in S-mode + ECALL_MMODE_EXCEPTION = 11, ///< ecall was executed in M-mode + MAX_EXCEPTION_NUM = 11 }; +#else +enum exception_number { + // Assigned to VTOR indices + MIN_EXCEPTION_NUM = 2, + NMI_EXCEPTION = 2, ///< Non Maskable Interrupt + HARDFAULT_EXCEPTION = 3, ///< HardFault Interrupt + SVCALL_EXCEPTION = 11, ///< SV Call Interrupt + PENDSV_EXCEPTION = 14, ///< Pend SV Interrupt + SYSTICK_EXCEPTION = 15, ///< System Tick Interrupt + MAX_EXCEPTION_NUM = 15 +}; +#endif + +#define PICO_LOWEST_EXCEPTION_PRIORITY 0xff +#define PICO_HIGHEST_EXCEPTION_PRIORITY 0x00 + /*! \brief Exception handler function type * \ingroup hardware_exception @@ -98,6 +144,49 @@ void exception_restore_handler(enum exception_number num, exception_handler_t or * \return the address stored in the VTABLE for the given exception number */ exception_handler_t exception_get_vtable_handler(enum exception_number num); + +#ifndef __riscv +/*! \brief Set specified exception's priority + * \ingroup hardware_exception + * + * \param num Exception number \ref exception_number + * \param hardware_priority Priority to set. + * + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority). + * + * \if rp2040_specific + * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. + * \endif + * + * \if rp2350_specific + * Only the top 4 bits are significant on ARM Cortex-M33 on RP2350, and exception priorities + * are not supported on RISC-V + * \endif + */ +bool exception_set_priority(uint num, uint8_t hardware_priority); + +/*! \brief Get specified exception's priority + * \ingroup hardware_exception + * + * Numerically-lower values indicate a higher priority. Hardware priorities + * range from 0 (highest priority) to 255 (lowest priority). + * + * \if rp2040_specific + * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. + * \endif + * + * \if rp2350_specific + * Only the top 4 bits are significant on ARM Cortex-M33 on RP2350, and exception priorities + * are not supported on RISC-V + * \endif + * + * \param num Exception number \ref exception_number + * \return the exception priority + */ +uint exception_get_priority(uint num); +#endif + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/hardware_flash/BUILD.bazel b/src/rp2_common/hardware_flash/BUILD.bazel index c5b86507c..e443e261c 100644 --- a/src/rp2_common/hardware_flash/BUILD.bazel +++ b/src/rp2_common/hardware_flash/BUILD.bazel @@ -2,6 +2,7 @@ load("//bazel:defs.bzl", "compatible_with_rp2") package(default_visibility = ["//visibility:public"]) +# TODO: Needs LIB_FREERTOS_KERNEL defined. cc_library( name = "hardware_flash", srcs = ["flash.c"], @@ -9,8 +10,9 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/rp2_common/pico_multicore", ], ) diff --git a/src/rp2_common/hardware_flash/flash.c b/src/rp2_common/hardware_flash/flash.c index 1423fdb2b..2116b0972 100644 --- a/src/rp2_common/hardware_flash/flash.c +++ b/src/rp2_common/hardware_flash/flash.c @@ -7,8 +7,12 @@ #include "hardware/flash.h" #include "pico/bootrom.h" +#if PICO_RP2040 +#include "hardware/structs/io_qspi.h" #include "hardware/structs/ssi.h" -#include "hardware/structs/ioqspi.h" +#else +#include "hardware/structs/qmi.h" +#endif #define FLASH_BLOCK_ERASE_CMD 0xd8 @@ -34,12 +38,20 @@ static bool boot2_copyout_valid = false; static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) { if (boot2_copyout_valid) return; + // todo we may want the option of boot2 just being a free function in + // user RAM, e.g. if it is larger than 256 bytes +#if PICO_RP2040 + const volatile uint32_t *copy_from = (uint32_t *)XIP_BASE; +#else + const volatile uint32_t *copy_from = (uint32_t *)BOOTRAM_BASE; +#endif for (int i = 0; i < BOOT2_SIZE_WORDS; ++i) - boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i]; + boot2_copyout[i] = copy_from[i]; __compiler_memory_barrier(); boot2_copyout_valid = true; } + static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) { ((void (*)(void))((intptr_t)boot2_copyout+1))(); } @@ -50,9 +62,9 @@ static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {} static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) { // Set up XIP for 03h read on bus access (slow but generic) - rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP); - assert(flash_enter_cmd_xip); - flash_enter_cmd_xip(); + rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip_func = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP); + assert(flash_enter_cmd_xip_func); + flash_enter_cmd_xip_func(); } #endif @@ -64,8 +76,8 @@ void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_ #ifdef PICO_FLASH_SIZE_BYTES hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES); #endif - invalid_params_if(FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1)); - invalid_params_if(FLASH, count & (FLASH_SECTOR_SIZE - 1)); + invalid_params_if(HARDWARE_FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1)); + invalid_params_if(HARDWARE_FLASH, count & (FLASH_SECTOR_SIZE - 1)); rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); rom_flash_range_erase_fn flash_range_erase_func = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE); @@ -83,17 +95,22 @@ void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_ flash_enable_xip_via_boot2(); } +void __no_inline_not_in_flash_func(flash_flush_cache)(void) { + rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); + flash_flush_cache_func(); +} + void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, const uint8_t *data, size_t count) { #ifdef PICO_FLASH_SIZE_BYTES hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES); #endif - invalid_params_if(FLASH, flash_offs & (FLASH_PAGE_SIZE - 1)); - invalid_params_if(FLASH, count & (FLASH_PAGE_SIZE - 1)); + invalid_params_if(HARDWARE_FLASH, flash_offs & (FLASH_PAGE_SIZE - 1)); + invalid_params_if(HARDWARE_FLASH, count & (FLASH_PAGE_SIZE - 1)); rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); rom_flash_range_program_fn flash_range_program_func = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM); - rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); - assert(connect_internal_flash_func && flash_exit_xip_func && flash_range_program_func && flash_flush_cache); + rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); + assert(connect_internal_flash_func && flash_exit_xip_func && flash_range_program_func && flash_flush_cache_func); flash_init_boot2_copyout(); __compiler_memory_barrier(); @@ -101,7 +118,7 @@ void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, con connect_internal_flash_func(); flash_exit_xip_func(); flash_range_program_func(flash_offs, data, count); - flash_flush_cache(); // Note this is needed to remove CSn IO force as well as cache flushing + flash_flush_cache_func(); // Note this is needed to remove CSn IO force as well as cache flushing flash_enable_xip_via_boot2(); } @@ -112,13 +129,21 @@ void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, con // Bitbanging the chip select using IO overrides, in case RAM-resident IRQs // are still running, and the FIFO bottoms out. (the bootrom does the same) static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) { +#if PICO_RP2040 uint32_t field_val = high ? IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW; - hw_write_masked(&ioqspi_hw->io[1].ctrl, + hw_write_masked(&io_qspi_hw->io[1].ctrl, field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB, IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS ); +#else + if (high) { + hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS); + } else { + hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS); + } +#endif } void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) { @@ -134,12 +159,14 @@ void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t * flash_cs_force(0); size_t tx_remaining = count; size_t rx_remaining = count; +#if PICO_RP2040 + // Synopsys SSI version // We may be interrupted -- don't want FIFO to overflow if we're distracted. const size_t max_in_flight = 16 - 2; while (tx_remaining || rx_remaining) { uint32_t flags = ssi_hw->sr; - bool can_put = !!(flags & SSI_SR_TFNF_BITS); - bool can_get = !!(flags & SSI_SR_RFNE_BITS); + bool can_put = flags & SSI_SR_TFNF_BITS; + bool can_get = flags & SSI_SR_RFNE_BITS; if (can_put && tx_remaining && rx_remaining - tx_remaining < max_in_flight) { ssi_hw->dr0 = *txbuf++; --tx_remaining; @@ -149,6 +176,24 @@ void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t * --rx_remaining; } } +#else + // QMI version -- no need to bound FIFO contents as QMI stalls on full DIRECT_RX. + hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); + while (tx_remaining || rx_remaining) { + uint32_t flags = qmi_hw->direct_csr; + bool can_put = !(flags & QMI_DIRECT_CSR_TXFULL_BITS); + bool can_get = !(flags & QMI_DIRECT_CSR_RXEMPTY_BITS); + if (can_put && tx_remaining) { + qmi_hw->direct_tx = *txbuf++; + --tx_remaining; + } + if (can_get && rx_remaining) { + *rxbuf++ = (uint8_t)qmi_hw->direct_rx; + --rx_remaining; + } + } + hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); +#endif flash_cs_force(1); flash_flush_cache_func(); diff --git a/src/rp2_common/hardware_flash/include/hardware/flash.h b/src/rp2_common/hardware_flash/include/hardware/flash.h index eb132d191..87dafb15c 100644 --- a/src/rp2_common/hardware_flash/include/hardware/flash.h +++ b/src/rp2_common/hardware_flash/include/hardware/flash.h @@ -34,18 +34,21 @@ * \include flash_program.c */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash -#ifndef PARAM_ASSERTIONS_ENABLED_FLASH -#define PARAM_ASSERTIONS_ENABLED_FLASH 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH, Enable/disable assertions in the hardware_flash module, type=bool, default=0, group=hardware_flash +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH +#ifdef PARAM_ASSERTIONS_ENABLED_FLASH // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH PARAM_ASSERTIONS_ENABLED_FLASH +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH 0 +#endif #endif - #define FLASH_PAGE_SIZE (1u << 8) #define FLASH_SECTOR_SIZE (1u << 12) #define FLASH_BLOCK_SIZE (1u << 16) #define FLASH_UNIQUE_ID_SIZE_BYTES 8 -// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, group=hardware_flash +// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, default=Usually provided via board header, group=hardware_flash #ifdef __cplusplus extern "C" { @@ -114,6 +117,7 @@ void flash_get_unique_id(uint8_t *id_out); */ void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count); +void flash_flush_cache(void); #ifdef __cplusplus } diff --git a/src/rp2_common/hardware_gpio/BUILD.bazel b/src/rp2_common/hardware_gpio/BUILD.bazel index 5dacb7de8..c6646b626 100644 --- a/src/rp2_common/hardware_gpio/BUILD.bazel +++ b/src/rp2_common/hardware_gpio/BUILD.bazel @@ -5,14 +5,17 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "hardware_gpio", srcs = ["gpio.c"], - hdrs = ["include/hardware/gpio.h"], + hdrs = [ + "include/hardware/gpio.h", + "include/hardware/gpio_coproc.h", + ], includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", + "//src/common/pico_base_headers", "//src/common/pico_binary_info", + "//src/rp2_common:hardware_structs", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_sync", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_gpio/gpio.c b/src/rp2_common/hardware_gpio/gpio.c index 7cb72f0eb..b26d0cc95 100644 --- a/src/rp2_common/hardware_gpio/gpio.c +++ b/src/rp2_common/hardware_gpio/gpio.c @@ -7,7 +7,7 @@ #include "hardware/gpio.h" #include "hardware/sync.h" -#include "hardware/structs/iobank0.h" +#include "hardware/structs/io_bank0.h" #include "hardware/irq.h" #if LIB_PICO_BINARY_INFO @@ -16,36 +16,46 @@ static gpio_irq_callback_t callbacks[NUM_CORES]; // a 1 bit means the IRQ is handled by a raw IRQ handler -static uint32_t raw_irq_mask[NUM_CORES]; +#if NUM_BANK0_GPIOS > 32 +typedef uint64_t raw_irq_mask_type_t; +#else +typedef uint32_t raw_irq_mask_type_t; +#endif + +static raw_irq_mask_type_t raw_irq_mask[NUM_CORES]; // Get the raw value from the pin, bypassing any muxing or overrides. int gpio_get_pad(uint gpio) { check_gpio_param(gpio); - hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); - return (iobank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS) + hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); + return (io_bank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS) >> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB; } /// \tag::gpio_set_function[] // Select function for this GPIO, and ensure input/output are enabled at the pad. // This also clears the input/output/irq override bits. -void gpio_set_function(uint gpio, enum gpio_function fn) { +void gpio_set_function(uint gpio, gpio_function_t fn) { check_gpio_param(gpio); - invalid_params_if(GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS); + invalid_params_if(HARDWARE_GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS); // Set input enable on, output disable off - hw_write_masked(&padsbank0_hw->io[gpio], + hw_write_masked(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS, PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS ); // Zero all fields apart from fsel; we want this IO to do what the peripheral tells it. // This doesn't affect e.g. pullup/pulldown, as these are in pad controls. - iobank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; + io_bank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; +#if !PICO_RP2040 + // Remove pad isolation now that the correct peripheral is in control of the pad + hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_ISO_BITS); +#endif } /// \end::gpio_set_function[] -enum gpio_function gpio_get_function(uint gpio) { +gpio_function_t gpio_get_function(uint gpio) { check_gpio_param(gpio); - return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB); + return (gpio_function_t) ((io_bank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB); } // Note that, on RP2040, setting both pulls enables a "bus keep" function, @@ -53,7 +63,7 @@ enum gpio_function gpio_get_function(uint gpio) { void gpio_set_pulls(uint gpio, bool up, bool down) { check_gpio_param(gpio); hw_write_masked( - &padsbank0_hw->io[gpio], + &pads_bank0_hw->io[gpio], (bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB), PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS ); @@ -62,7 +72,7 @@ void gpio_set_pulls(uint gpio, bool up, bool down) { // Direct override for per-GPIO IRQ signal void gpio_set_irqover(uint gpio, uint value) { check_gpio_param(gpio); - hw_write_masked(&iobank0_hw->io[gpio].ctrl, + hw_write_masked(&io_bank0_hw->io[gpio].ctrl, value << IO_BANK0_GPIO0_CTRL_IRQOVER_LSB, IO_BANK0_GPIO0_CTRL_IRQOVER_BITS ); @@ -71,7 +81,7 @@ void gpio_set_irqover(uint gpio, uint value) { // Direct overrides for pad controls void gpio_set_inover(uint gpio, uint value) { check_gpio_param(gpio); - hw_write_masked(&iobank0_hw->io[gpio].ctrl, + hw_write_masked(&io_bank0_hw->io[gpio].ctrl, value << IO_BANK0_GPIO0_CTRL_INOVER_LSB, IO_BANK0_GPIO0_CTRL_INOVER_BITS ); @@ -79,7 +89,7 @@ void gpio_set_inover(uint gpio, uint value) { void gpio_set_outover(uint gpio, uint value) { check_gpio_param(gpio); - hw_write_masked(&iobank0_hw->io[gpio].ctrl, + hw_write_masked(&io_bank0_hw->io[gpio].ctrl, value << IO_BANK0_GPIO0_CTRL_OUTOVER_LSB, IO_BANK0_GPIO0_CTRL_OUTOVER_BITS ); @@ -87,7 +97,7 @@ void gpio_set_outover(uint gpio, uint value) { void gpio_set_oeover(uint gpio, uint value) { check_gpio_param(gpio); - hw_write_masked(&iobank0_hw->io[gpio].ctrl, + hw_write_masked(&io_bank0_hw->io[gpio].ctrl, value << IO_BANK0_GPIO0_CTRL_OEOVER_LSB, IO_BANK0_GPIO0_CTRL_OEOVER_BITS ); @@ -96,20 +106,20 @@ void gpio_set_oeover(uint gpio, uint value) { void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) { check_gpio_param(gpio); if (enabled) - hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); + hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); else - hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); + hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); } bool gpio_is_input_hysteresis_enabled(uint gpio) { check_gpio_param(gpio); - return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0; + return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0; } void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) { check_gpio_param(gpio); - hw_write_masked(&padsbank0_hw->io[gpio], + hw_write_masked(&pads_bank0_hw->io[gpio], (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB, PADS_BANK0_GPIO0_SLEWFAST_BITS ); @@ -117,8 +127,8 @@ void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) { enum gpio_slew_rate gpio_get_slew_rate(uint gpio) { check_gpio_param(gpio); - return (enum gpio_slew_rate)((padsbank0_hw->io[gpio] - & PADS_BANK0_GPIO0_SLEWFAST_BITS) + return (enum gpio_slew_rate)((pads_bank0_hw->io[gpio] + & PADS_BANK0_GPIO0_SLEWFAST_BITS) >> PADS_BANK0_GPIO0_SLEWFAST_LSB); } @@ -127,7 +137,7 @@ enum gpio_slew_rate gpio_get_slew_rate(uint gpio) { static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, ""); void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) { check_gpio_param(gpio); - hw_write_masked(&padsbank0_hw->io[gpio], + hw_write_masked(&pads_bank0_hw->io[gpio], (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB, PADS_BANK0_GPIO0_DRIVE_BITS ); @@ -135,21 +145,21 @@ void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) { enum gpio_drive_strength gpio_get_drive_strength(uint gpio) { check_gpio_param(gpio); - return (enum gpio_drive_strength)((padsbank0_hw->io[gpio] - & PADS_BANK0_GPIO0_DRIVE_BITS) + return (enum gpio_drive_strength)((pads_bank0_hw->io[gpio] + & PADS_BANK0_GPIO0_DRIVE_BITS) >> PADS_BANK0_GPIO0_DRIVE_LSB); } static void gpio_default_irq_handler(void) { uint core = get_core_num(); gpio_irq_callback_t callback = callbacks[core]; - io_irq_ctrl_hw_t *irq_ctrl_base = core ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t *irq_ctrl_base = core ? &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl; for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio+=8) { uint32_t events8 = irq_ctrl_base->ints[gpio >> 3u]; // note we assume events8 is 0 for non-existent GPIO for(uint i=gpio;events8 && iproc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? + &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl; _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); } @@ -208,35 +218,51 @@ void gpio_set_irq_callback(gpio_irq_callback_t callback) { } } -void gpio_add_raw_irq_handler_with_order_priority_masked(uint gpio_mask, irq_handler_t handler, uint8_t order_priority) { +void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler, uint8_t order_priority) { hard_assert(!(raw_irq_mask[get_core_num()] & gpio_mask)); // should not add multiple handlers for the same event raw_irq_mask[get_core_num()] |= gpio_mask; irq_add_shared_handler(IO_IRQ_BANK0, handler, order_priority); } -void gpio_add_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler) { +void gpio_add_raw_irq_handler_with_order_priority_masked64(uint64_t gpio_mask, irq_handler_t handler, uint8_t order_priority) { + hard_assert(!(raw_irq_mask[get_core_num()] & gpio_mask)); // should not add multiple handlers for the same event + raw_irq_mask[get_core_num()] |= (raw_irq_mask_type_t) gpio_mask; + irq_add_shared_handler(IO_IRQ_BANK0, handler, order_priority); +} + +void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler) { gpio_add_raw_irq_handler_with_order_priority_masked(gpio_mask, handler, GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY); } -void gpio_remove_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler) { +void gpio_add_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler) { + gpio_add_raw_irq_handler_with_order_priority_masked64(gpio_mask, handler, GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY); +} + +void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler) { assert(raw_irq_mask[get_core_num()] & gpio_mask); // should not remove handlers that are not added irq_remove_handler(IO_IRQ_BANK0, handler); raw_irq_mask[get_core_num()] &= ~gpio_mask; } +void gpio_remove_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler) { + assert(raw_irq_mask[get_core_num()] & gpio_mask); // should not remove handlers that are not added + irq_remove_handler(IO_IRQ_BANK0, handler); + raw_irq_mask[get_core_num()] &= (raw_irq_mask_type_t)~gpio_mask; +} + void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled) { check_gpio_param(gpio); - io_irq_ctrl_hw_t *irq_ctrl_base = &iobank0_hw->dormant_wake_irq_ctrl; + io_bank0_irq_ctrl_hw_t *irq_ctrl_base = &io_bank0_hw->dormant_wake_irq_ctrl; _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); } void gpio_acknowledge_irq(uint gpio, uint32_t events) { check_gpio_param(gpio); - iobank0_hw->intr[gpio / 8] = events << (4 * (gpio % 8)); + io_bank0_hw->intr[gpio / 8] = events << (4 * (gpio % 8)); } #define DEBUG_PIN_MASK (((1u << PICO_DEBUG_PIN_COUNT)-1) << PICO_DEBUG_PIN_BASE) -void gpio_debug_pins_init() { +void gpio_debug_pins_init(void) { gpio_init_mask(DEBUG_PIN_MASK); gpio_set_dir_masked(DEBUG_PIN_MASK, DEBUG_PIN_MASK); #if LIB_PICO_BINARY_INFO @@ -245,10 +271,11 @@ void gpio_debug_pins_init() { } void gpio_set_input_enabled(uint gpio, bool enabled) { + check_gpio_param(gpio); if (enabled) - hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); + hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); else - hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); + hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); } void gpio_init(uint gpio) { @@ -270,9 +297,18 @@ void gpio_init_mask(uint gpio_mask) { } } -void gpio_set_function_masked(uint gpio_mask, enum gpio_function fn) { - for (uint i = 0; i < NUM_BANK0_GPIOS; i++) { - if (gpio_mask & 1) { +void gpio_set_function_masked(uint32_t gpio_mask, gpio_function_t fn) { + for (uint i = 0; i < MIN(NUM_BANK0_GPIOS, 32u); i++) { + if (gpio_mask & 1u) { + gpio_set_function(i, fn); + } + gpio_mask >>= 1; + } +} + +void gpio_set_function_masked64(uint64_t gpio_mask, gpio_function_t fn) { + for (uint i = 0; i < MIN(NUM_BANK0_GPIOS, 64u); i++) { + if (gpio_mask & 1u) { gpio_set_function(i, fn); } gpio_mask >>= 1; diff --git a/src/rp2_common/hardware_gpio/include/hardware/gpio.h b/src/rp2_common/hardware_gpio/include/hardware/gpio.h index a4d301e93..029619cfe 100644 --- a/src/rp2_common/hardware_gpio/include/hardware/gpio.h +++ b/src/rp2_common/hardware_gpio/include/hardware/gpio.h @@ -9,17 +9,30 @@ #include "pico.h" #include "hardware/structs/sio.h" -#include "hardware/structs/padsbank0.h" -#include "hardware/structs/iobank0.h" +#include "hardware/structs/pads_bank0.h" +#include "hardware/structs/io_bank0.h" #include "hardware/irq.h" +// PICO_CONFIG: PICO_USE_GPIO_COPROCESSOR, Enable/disable use of the GPIO coprocessor for GPIO access, type=bool, default=1, group=hardware_gpio +#if !defined(PICO_USE_GPIO_COPROCESSOR) && HAS_GPIO_COPROCESSOR +#define PICO_USE_GPIO_COPROCESSOR 1 +#endif + +#if PICO_USE_GPIO_COPROCESSOR +#include "hardware/gpio_coproc.h" +#endif + #ifdef __cplusplus extern "C" { #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_GPIO, Enable/disable assertions in the GPIO module, type=bool, default=0, group=hardware_gpio -#ifndef PARAM_ASSERTIONS_ENABLED_GPIO -#define PARAM_ASSERTIONS_ENABLED_GPIO 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO, Enable/disable assertions in the hardware_gpio module, type=bool, default=0, group=hardware_gpio +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO +#ifdef PARAM_ASSERTIONS_ENABLED_GPIO // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO PARAM_ASSERTIONS_ENABLED_GPIO +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO 0 +#endif #endif /** \file gpio.h @@ -27,11 +40,25 @@ extern "C" { * * \brief General Purpose Input/Output (GPIO) API * - * RP2040 has 36 multi-functional General Purpose Input / Output (GPIO) pins, divided into two banks. In a typical use case, - * the pins in the QSPI bank (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3) are used to execute code from an external - * flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. All GPIOs support digital input and - * output, but GPIO26 to GPIO29 can also be used as inputs to the chip’s Analogue to Digital Converter (ADC). Each GPIO - * can be controlled directly by software running on the processors, or by a number of other functional blocks. + * RP-series microcontrollers have two banks of General Purpose Input / Output (GPIO) pins, which are assigned as follows: + * + * \if rp2040-specific + * RP2040 has 30 user GPIO pins in bank 0, and 6 QSPI pins in the QSPI bank 1 (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3). The QSPI + * pins are used to execute code from an external flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. + * \endif + * + * \if rp2350-specific + * The number of GPIO pins available depends on the package. There are 30 user GPIOs in bank 0 in the QFN-60 package (RP2350A), or 48 user GPIOs + * in the QFN-80 package. Bank 1 contains the 6 QSPI pins and the USB DP/DM pins. + * \endif + * + * All GPIOs support digital input and output, but a subset can also be used as inputs to the chip’s Analogue to Digital + * Converter (ADC). The allocation of GPIO pins to the ADC depends on the packaging. + * + * RP2040 and RP2350 QFN-60 GPIO, ADC pins are 26-29. + * RP2350 QFN-80, ADC pins are 40-47. + * + * Each GPIO can be controlled directly by software running on the processors, or by a number of other functional blocks. * * The function allocated to each GPIO is selected by calling the \ref gpio_set_function function. \note Not all functions * are available on all pins. @@ -42,67 +69,108 @@ extern "C" { * * ### Function Select Table * - * GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 - * -------|----------|-----------|----------|--------|-----|------|------|---------------|---- - * 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET - * 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN - * 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET - * 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN - * 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET - * 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN - * 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET - * 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN - * 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET - * 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN - * 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET - * 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN - * 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET - * 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN - * 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET - * 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET - * 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN - * 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET - * 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET - * 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN - * 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET - * 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET - * 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN - - */ - -/*! \brief GPIO function definitions for use with function select - * \ingroup hardware_gpio - * \brief GPIO function selectors - * - * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be - * selected on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical - * OR of these GPIO inputs. - * - * Please refer to the datasheet for more information on GPIO function selection. - */ -enum gpio_function { - GPIO_FUNC_XIP = 0, - GPIO_FUNC_SPI = 1, - GPIO_FUNC_UART = 2, - GPIO_FUNC_I2C = 3, - GPIO_FUNC_PWM = 4, - GPIO_FUNC_SIO = 5, - GPIO_FUNC_PIO0 = 6, - GPIO_FUNC_PIO1 = 7, - GPIO_FUNC_GPCK = 8, - GPIO_FUNC_USB = 9, - GPIO_FUNC_NULL = 0x1f, -}; + * \if rp2040_specific + * On RP2040 the function selects are: + * + * | GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | + * |--------|----------|-----------|----------|--------|-----|------|------|---------------|---------------| + * | 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN | + * | 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN | + * | 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN | + * | 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN | + * | 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN | + * | 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN | + * | 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN | + * | 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET | + * | 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET | + * | 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN | + * | 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET | + * | 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET | + * | 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN | + * | 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET | + * | 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET | + * | 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN | + * \endif + * \if rp2350_specific + * On RP2350 the function selects are: + * + * | GPIO | F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | + * |-------|------|----------|-----------|----------|--------|-----|------|------|------|--------------|---------------|----------| + * | 0 | | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB OVCUR DET | | + * | 1 | | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | PIO2 | TRACECLK | USB VBUS DET | | + * | 2 | | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA0 | USB VBUS EN | UART0 TX | + * | 3 | | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA1 | USB OVCUR DET | UART0 RX | + * | 4 | | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA2 | USB VBUS DET | | + * | 5 | | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | PIO2 | TRACEDATA3 | USB VBUS EN | | + * | 6 | | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 TX | + * | 7 | | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART1 RX | + * | 8 | | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB VBUS EN | | + * | 9 | | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | + * | 10 | | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART1 TX | + * | 11 | | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART1 RX | + * | 12 | HSTX | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN0 | USB OVCUR DET | | + * | 13 | HSTX | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT0 | USB VBUS DET | | + * | 14 | HSTX | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN1 | USB VBUS EN | UART0 TX | + * | 15 | HSTX | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT1 | USB OVCUR DET | UART0 RX | + * | 16 | HSTX | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | + * | 17 | HSTX | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | + * | 18 | HSTX | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART0 TX | + * | 19 | HSTX | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB VBUS DET | UART0 RX | + * | 20 | | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN0 | USB VBUS EN | | + * | 21 | | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT0 | USB OVCUR DET | | + * | 22 | | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPIN1 | USB VBUS DET | UART1 TX | + * | 23 | | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT1 | USB VBUS EN | UART1 RX | + * | 24 | | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT2 | USB OVCUR DET | | + * | 25 | | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | PIO2 | CLOCK GPOUT3 | USB VBUS DET | | + * | 26 | | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART1 TX | + * | 27 | | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 RX | + * | 28 | | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | + * | 29 | | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | + * + * GPIOs 30 through 47 are QFN-80 only: + * + * | GPIO | F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | + * |------|----|----------|----------|-----------|---------|-----|------|------|------|----------|---------------|----------| + * | 30 | | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART0 TX | + * | 31 | | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART0 RX | + * | 32 | | SPI0 RX | UART0 TX | I2C0 SDA | PWM8 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | + * | 33 | | SPI0 CSn | UART0 RX | I2C0 SCL | PWM8 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | + * | 34 | | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM9 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART0 TX | + * | 35 | | SPI0 TX | UART0 RTS | I2C1 SCL | PWM9 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART0 RX | + * | 36 | | SPI0 RX | UART1 TX | I2C0 SDA | PWM10 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | + * | 37 | | SPI0 CSn | UART1 RX | I2C0 SCL | PWM10 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | + * | 38 | | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM11 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | UART1 TX | + * | 39 | | SPI0 TX | UART1 RTS | I2C1 SCL | PWM11 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 RX | + * | 40 | | SPI1 RX | UART1 TX | I2C0 SDA | PWM8 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | | + * | 41 | | SPI1 CSn | UART1 RX | I2C0 SCL | PWM8 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | + * | 42 | | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM9 A | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | UART1 TX | + * | 43 | | SPI1 TX | UART1 RTS | I2C1 SCL | PWM9 B | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART1 RX | + * | 44 | | SPI1 RX | UART0 TX | I2C0 SDA | PWM10 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS EN | | + * | 45 | | SPI1 CSn | UART0 RX | I2C0 SCL | PWM10 B | SIO | PIO0 | PIO1 | PIO2 | | USB OVCUR DET | | + * | 46 | | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM11 A | SIO | PIO0 | PIO1 | PIO2 | | USB VBUS DET | UART0 TX | + * | 47 | | SPI1 TX | UART0 RTS | I2C1 SCL | PWM11 B | SIO | PIO0 | PIO1 | PIO2 | XIP_CS1n | USB VBUS EN | UART0 RX | + * + * \endif + */ -#define GPIO_OUT 1 -#define GPIO_IN 0 +enum gpio_dir { + GPIO_OUT = 1u, ///< set GPIO to output + GPIO_IN = 0u, ///< set GPIO to input +}; /*! \brief GPIO Interrupt level definitions (GPIO events) * \ingroup hardware_gpio @@ -120,10 +188,10 @@ enum gpio_function { * cleared by writing to the INTR register. */ enum gpio_irq_level { - GPIO_IRQ_LEVEL_LOW = 0x1u, - GPIO_IRQ_LEVEL_HIGH = 0x2u, - GPIO_IRQ_EDGE_FALL = 0x4u, - GPIO_IRQ_EDGE_RISE = 0x8u, + GPIO_IRQ_LEVEL_LOW = 0x1u, ///< IRQ when the GPIO pin is a logical 1 + GPIO_IRQ_LEVEL_HIGH = 0x2u, ///< IRQ when the GPIO pin is a logical 0 + GPIO_IRQ_EDGE_FALL = 0x4u, ///< IRQ when the GPIO has transitioned from a logical 0 to a logical 1 + GPIO_IRQ_EDGE_RISE = 0x8u, ///< IRQ when the GPIO has transitioned from a logical 1 to a logical 0 }; /*! Callback function type for GPIO events @@ -169,7 +237,7 @@ enum gpio_drive_strength { }; static inline void check_gpio_param(__unused uint gpio) { - invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS); + invalid_params_if(HARDWARE_GPIO, gpio >= NUM_BANK0_GPIOS); } // ---------------------------------------------------------------------------- @@ -183,7 +251,16 @@ static inline void check_gpio_param(__unused uint gpio) { * \param gpio GPIO number * \param fn Which GPIO function select to use from list \ref gpio_function */ -void gpio_set_function(uint gpio, enum gpio_function fn); +void gpio_set_function(uint gpio, gpio_function_t fn); + +/*! \brief Select the function for multiple GPIOs + * \ingroup hardware_gpio + * + * \sa gpio_set_function + * \param gpio_mask Mask with 1 bit per GPIO number to set the function for + * \param fn Which GPIO function select to use from list \ref gpio_function +*/ +void gpio_set_function_masked(uint32_t gpio_mask, gpio_function_t fn); /*! \brief Select the function for multiple GPIOs * \ingroup hardware_gpio @@ -192,7 +269,7 @@ void gpio_set_function(uint gpio, enum gpio_function fn); * \param gpio_mask Mask with 1 bit per GPIO number to set the function for * \param fn Which GPIO function select to use from list \ref gpio_function */ -void gpio_set_function_masked(uint gpio_mask, enum gpio_function fn); +void gpio_set_function_masked64(uint64_t gpio_mask, gpio_function_t fn); /*! \brief Determine current GPIO function * \ingroup hardware_gpio @@ -200,7 +277,7 @@ void gpio_set_function_masked(uint gpio_mask, enum gpio_function fn); * \param gpio GPIO number * \return Which GPIO function is currently selected from list \ref gpio_function */ -enum gpio_function gpio_get_function(uint gpio); +gpio_function_t gpio_get_function(uint gpio); /*! \brief Select up and down pulls on specific GPIO * \ingroup hardware_gpio @@ -230,7 +307,7 @@ static inline void gpio_pull_up(uint gpio) { * \return true if the GPIO is pulled up */ static inline bool gpio_is_pulled_up(uint gpio) { - return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0; + return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0; } /*! \brief Set specified GPIO to be pulled down. @@ -249,7 +326,7 @@ static inline void gpio_pull_down(uint gpio) { * \return true if the GPIO is pulled down */ static inline bool gpio_is_pulled_down(uint gpio) { - return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0; + return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0; } /*! \brief Disable pulls on specified GPIO @@ -325,7 +402,6 @@ void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled); */ bool gpio_is_input_hysteresis_enabled(uint gpio); - /*! \brief Set slew rate for a specified GPIO * \ingroup hardware_gpio * @@ -389,12 +465,12 @@ enum gpio_drive_strength gpio_get_drive_strength(uint gpio); */ void gpio_set_irq_enabled(uint gpio, uint32_t event_mask, bool enabled); -// PICO_CONFIG: GPIO_IRQ_CALLBACK_ORDER_PRIORITY, the irq priority order of the default IRQ callback, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY, group=hardware_gpio +// PICO_CONFIG: GPIO_IRQ_CALLBACK_ORDER_PRIORITY, IRQ priority order of the default IRQ callback, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY, group=hardware_gpio #ifndef GPIO_IRQ_CALLBACK_ORDER_PRIORITY #define GPIO_IRQ_CALLBACK_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY #endif -// PICO_CONFIG: GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, the irq priority order of raw IRQ handlers if the priortiy is not specified, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, group=hardware_gpio +// PICO_CONFIG: GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, IRQ priority order of raw IRQ handlers if the priority is not specified, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, group=hardware_gpio #ifndef GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY #define GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY #endif @@ -469,8 +545,8 @@ void gpio_set_dormant_irq_enabled(uint gpio, uint32_t event_mask, bool enabled); */ static inline uint32_t gpio_get_irq_event_mask(uint gpio) { check_gpio_param(gpio); - io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? - &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? + &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl; io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio >> 3u]; return (*status_reg >> (4 * (gpio & 7u))) & 0xfu; } @@ -524,7 +600,42 @@ void gpio_acknowledge_irq(uint gpio, uint32_t event_mask); * @param handler the handler to add to the list of GPIO IRQ handlers for this core * @param order_priority the priority order to determine the relative position of the handler in the list of GPIO IRQ handlers for this core. */ -void gpio_add_raw_irq_handler_with_order_priority_masked(uint gpio_mask, irq_handler_t handler, uint8_t order_priority); +void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler, uint8_t order_priority); + +/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core + * \ingroup hardware_gpio + * + * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), + * it is possible to add explicit GPIO IRQ handlers which are called independent of the default callback. The order + * relative to the default callback can be controlled via the order_priority parameter (the default callback has the priority + * \ref GPIO_IRQ_CALLBACK_ORDER_PRIORITY which defaults to the lowest priority with the intention of it running last). + * + * This method adds such an explicit GPIO IRQ handler, and disables the "default" callback for the specified GPIOs. + * + * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to. + * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers + * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. + * + * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: + * + * \code{.c} + * void my_irq_handler(void) { + * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { + * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); + * // handle the IRQ + * } + * if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) { + * gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2); + * // handle the IRQ + * } + * } + * \endcode + * + * @param gpio_mask a bit mask of the GPIO numbers that will no longer be passed to the default callback for this core + * @param handler the handler to add to the list of GPIO IRQ handlers for this core + * @param order_priority the priority order to determine the relative position of the handler in the list of GPIO IRQ handlers for this core. + */ +void gpio_add_raw_irq_handler_with_order_priority_masked64(uint64_t gpio_mask, irq_handler_t handler, uint8_t order_priority); /*! \brief Adds a raw GPIO IRQ handler for a specific GPIO on the current core * \ingroup hardware_gpio @@ -557,7 +668,11 @@ void gpio_add_raw_irq_handler_with_order_priority_masked(uint gpio_mask, irq_han */ static inline void gpio_add_raw_irq_handler_with_order_priority(uint gpio, irq_handler_t handler, uint8_t order_priority) { check_gpio_param(gpio); +#if NUM_BANK0_GPIOS > 32 + gpio_add_raw_irq_handler_with_order_priority_masked64(1ull << gpio, handler, order_priority); +#else gpio_add_raw_irq_handler_with_order_priority_masked(1u << gpio, handler, order_priority); +#endif } /*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core @@ -590,7 +705,39 @@ static inline void gpio_add_raw_irq_handler_with_order_priority(uint gpio, irq_h * @param gpio_mask a bit mask of the GPIO numbers that will no longer be passed to the default callback for this core * @param handler the handler to add to the list of GPIO IRQ handlers for this core */ -void gpio_add_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler); +void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler); + +/*! \brief Adds a raw GPIO IRQ handler for the specified GPIOs on the current core + * \ingroup hardware_gpio + * + * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), + * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. + * + * This method adds such a callback, and disables the "default" callback for the specified GPIOs. + * + * \note Multiple raw handlers should not be added for the same GPIOs, and this method will assert if you attempt to. + * Internally, this function calls \ref irq_add_shared_handler, which will assert if the maximum number of shared handlers + * (configurable via PICO_MAX_IRQ_SHARED_HANDLERS) would be exceeded. + * + * A raw handler should check for whichever GPIOs and events it handles, and acknowledge them itself; it might look something like: + * + * \code{.c} + * void my_irq_handler(void) { + * if (gpio_get_irq_event_mask(my_gpio_num) & my_gpio_event_mask) { + * gpio_acknowledge_irq(my_gpio_num, my_gpio_event_mask); + * // handle the IRQ + * } + * if (gpio_get_irq_event_mask(my_gpio_num2) & my_gpio_event_mask2) { + * gpio_acknowledge_irq(my_gpio_num2, my_gpio_event_mask2); + * // handle the IRQ + * } + * } + * \endcode + * + * @param gpio_mask a 64 bit mask of the GPIO numbers that will no longer be passed to the default callback for this core + * @param handler the handler to add to the list of GPIO IRQ handlers for this core + */ +void gpio_add_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler); /*! \brief Adds a raw GPIO IRQ handler for a specific GPIO on the current core * \ingroup hardware_gpio @@ -620,7 +767,11 @@ void gpio_add_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler); */ static inline void gpio_add_raw_irq_handler(uint gpio, irq_handler_t handler) { check_gpio_param(gpio); +#if NUM_BANK0_GPIOS > 32 + gpio_add_raw_irq_handler_masked64(1ull << gpio, handler); +#else gpio_add_raw_irq_handler_masked(1u << gpio, handler); +#endif } /*! \brief Removes a raw GPIO IRQ handler for the specified GPIOs on the current core @@ -634,7 +785,20 @@ static inline void gpio_add_raw_irq_handler(uint gpio, irq_handler_t handler) { * @param gpio_mask a bit mask of the GPIO numbers that will now be passed to the default callback for this core * @param handler the handler to remove from the list of GPIO IRQ handlers for this core */ -void gpio_remove_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler); +void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler); + +/*! \brief Removes a raw GPIO IRQ handler for the specified GPIOs on the current core + * \ingroup hardware_gpio + * + * In addition to the default mechanism of a single GPIO IRQ event callback per core (see \ref gpio_set_irq_callback), + * it is possible to add explicit GPIO IRQ handlers which are called independent of the default event callback. + * + * This method removes such a callback, and enables the "default" callback for the specified GPIOs. + * + * @param gpio_mask a bit mask of the GPIO numbers that will now be passed to the default callback for this core + * @param handler the handler to remove from the list of GPIO IRQ handlers for this core + */ +void gpio_remove_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler); /*! \brief Removes a raw GPIO IRQ handler for the specified GPIO on the current core * \ingroup hardware_gpio @@ -649,7 +813,11 @@ void gpio_remove_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler); */ static inline void gpio_remove_raw_irq_handler(uint gpio, irq_handler_t handler) { check_gpio_param(gpio); +#if NUM_BANK0_GPIOS > 32 + gpio_remove_raw_irq_handler_masked64(1ull << gpio, handler); +#else gpio_remove_raw_irq_handler_masked(1u << gpio, handler); +#endif } /*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO) @@ -689,16 +857,43 @@ void gpio_init_mask(uint gpio_mask); * \return Current state of the GPIO. 0 for low, non-zero for high */ static inline bool gpio_get(uint gpio) { - return !!((1ul << gpio) & sio_hw->gpio_in); +#if NUM_BANK0_GPIOS <= 32 + return sio_hw->gpio_in & (1u << gpio); +#else + if (gpio < 32) { + return sio_hw->gpio_in & (1u << gpio); + } else { + return sio_hw->gpio_hi_in & (1u << (gpio - 32)); + } +#endif } /*! \brief Get raw value of all GPIOs * \ingroup hardware_gpio * - * \return Bitmask of raw GPIO values, as bits 0-29 + * \return Bitmask of raw GPIO values */ static inline uint32_t gpio_get_all(void) { +#if PICO_USE_GPIO_COPROCESSOR + return gpioc_lo_in_get(); +#else return sio_hw->gpio_in; +#endif +} + +/*! \brief Get raw value of all GPIOs + * \ingroup hardware_gpio + * + * \return Bitmask of raw GPIO values + */ +static inline uint64_t gpio_get_all64(void) { +#if PICO_USE_GPIO_COPROCESSOR + return gpioc_hilo_in_get(); +#elif NUM_BANK0_GPIOS <= 32 + return sio_hw->gpio_in; +#else + return sio_hw->gpio_in | (((uint64_t)sio_hw->gpio_hi_in) << 32u); +#endif } // ---------------------------------------------------------------------------- @@ -708,34 +903,149 @@ static inline uint32_t gpio_get_all(void) { /*! \brief Drive high every GPIO appearing in mask * \ingroup hardware_gpio * - * \param mask Bitmask of GPIO values to set, as bits 0-29 + * \param mask Bitmask of GPIO values to set */ static inline void gpio_set_mask(uint32_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_out_set(mask); +#else sio_hw->gpio_set = mask; +#endif +} + +/*! \brief Drive high every GPIO appearing in mask + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to set + */ +static inline void gpio_set_mask64(uint64_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_out_set(mask); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_set = (uint32_t)mask; +#else + sio_hw->gpio_set = (uint32_t)mask; + sio_hw->gpio_hi_set = (uint32_t)(mask >> 32u); +#endif +} + +/*! \brief Drive high every GPIO appearing in mask + * \ingroup hardware_gpio + * + * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. + * \param mask Bitmask of 32 GPIO values to set + */ +static inline void gpio_set_mask_n(uint n, uint32_t mask) { + if (!n) { + gpio_set_mask(mask); + } else if (n == 1) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hi_out_set(mask); +#elif NUM_BANK0_GPIOS >= 32 + sio_hw->gpio_hi_set = mask; +#endif + } } /*! \brief Drive low every GPIO appearing in mask * \ingroup hardware_gpio * - * \param mask Bitmask of GPIO values to clear, as bits 0-29 + * \param mask Bitmask of GPIO values to clear */ static inline void gpio_clr_mask(uint32_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_out_clr(mask); +#else sio_hw->gpio_clr = mask; +#endif +} + +/*! \brief Drive low every GPIO appearing in mask +* \ingroup hardware_gpio +* +* \param mask Bitmask of GPIO values to clear +*/ +static inline void gpio_clr_mask64(uint64_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_out_clr(mask); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_clr = (uint32_t)mask; +#else + sio_hw->gpio_clr = (uint32_t)mask; + sio_hw->gpio_hi_clr = (uint32_t)(mask >> 32u); +#endif +} + + +/*! \brief Drive low every GPIO appearing in mask + * \ingroup hardware_gpio + * + * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. + * \param mask Bitmask of 32 GPIO values to clear + */ +static inline void gpio_clr_mask_n(uint n, uint32_t mask) { + if (!n) { + gpio_clr_mask(mask); + } else if (n == 1) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hi_out_clr(mask); +#elif NUM_BANK0_GPIOS >= 32 + sio_hw->gpio_hi_clr = mask; +#endif + } } /*! \brief Toggle every GPIO appearing in mask * \ingroup hardware_gpio * - * \param mask Bitmask of GPIO values to toggle, as bits 0-29 + * \param mask Bitmask of GPIO values to toggle */ static inline void gpio_xor_mask(uint32_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_out_xor(mask); +#else sio_hw->gpio_togl = mask; +#endif +} + +/*! \brief Toggle every GPIO appearing in mask + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to toggle + */ +static inline void gpio_xor_mask64(uint64_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_out_xor(mask); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_togl = (uint32_t)mask; +#else + sio_hw->gpio_togl = (uint32_t)mask; + sio_hw->gpio_hi_togl = (uint32_t)(mask >> 32u); +#endif } -/*! \brief Drive GPIO high/low depending on parameters +/*! \brief Toggle every GPIO appearing in mask * \ingroup hardware_gpio * - * \param mask Bitmask of GPIO values to change, as bits 0-29 + * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. + * \param mask Bitmask of 32 GPIO values to toggle + */ +static inline void gpio_xor_mask_n(uint n, uint32_t mask) { + if (!n) { + gpio_xor_mask(mask); + } else if (n == 1) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hi_out_xor(mask); +#elif NUM_BANK0_GPIOS >= 32 + sio_hw->gpio_hi_togl = mask; +#endif + } +} + +/*! \brief Drive GPIOs high/low depending on parameters + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to change * \param value Value to set * * For each 1 bit in \p mask, drive that pin to the value given by @@ -744,16 +1054,86 @@ static inline void gpio_xor_mask(uint32_t mask) { * bashing different pins from the same core. */ static inline void gpio_put_masked(uint32_t mask, uint32_t value) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_out_xor((gpioc_lo_out_get() ^ value) & mask); +#else sio_hw->gpio_togl = (sio_hw->gpio_out ^ value) & mask; +#endif +} + +/*! \brief Drive GPIOs high/low depending on parameters + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO values to change + * \param value Value to set + * + * For each 1 bit in \p mask, drive that pin to the value given by + * corresponding bit in \p value, leaving other pins unchanged. + * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ + * bashing different pins from the same core. + */ +static inline void gpio_put_masked64(uint64_t mask, uint64_t value) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_out_xor((gpioc_hilo_out_get() ^ value) & mask); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_togl = (sio_hw->gpio_out ^ (uint32_t)value) & (uint32_t)mask; +#else + sio_hw->gpio_togl = (sio_hw->gpio_out ^ (uint32_t)value) & (uint32_t)mask; + sio_hw->gpio_hi_togl = (sio_hw->gpio_hi_out ^ (uint32_t)(value>>32u)) & (uint32_t)(mask>>32u); +#endif +} + +/*! \brief Drive GPIOs high/low depending on parameters + * \ingroup hardware_gpio + * + * \param n the base GPIO index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. + * \param mask Bitmask of GPIO values to change + * \param value Value to set + * + * For each 1 bit in \p mask, drive that pin to the value given by + * corresponding bit in \p value, leaving other pins unchanged. + * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ + * bashing different pins from the same core. + */ +static inline void gpio_put_masked_n(uint n, uint32_t mask, uint32_t value) { + if (!n) { + gpio_put_masked(mask, value); + } else if (n == 1) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hi_out_xor((gpioc_hi_out_get() ^ value) & mask); +#else + sio_hw->gpio_hi_togl = (sio_hw->gpio_hi_out ^ value) & mask; +#endif + } } /*! \brief Drive all pins simultaneously * \ingroup hardware_gpio * - * \param value Bitmask of GPIO values to change, as bits 0-29 + * \param value Bitmask of GPIO values to change */ static inline void gpio_put_all(uint32_t value) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_out_put(value); +#else sio_hw->gpio_out = value; +#endif +} + +/*! \brief Drive all pins simultaneously + * \ingroup hardware_gpio + * + * \param value Bitmask of GPIO values to change + */ +static inline void gpio_put_all64(uint64_t value) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_out_put(value); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_out = (uint32_t)value; +#else + sio_hw->gpio_out = (uint32_t)value; + sio_hw->gpio_hi_out = (uint32_t)(value >> 32u); +#endif } /*! \brief Drive a single GPIO high/low @@ -763,11 +1143,30 @@ static inline void gpio_put_all(uint32_t value) { * \param value If false clear the GPIO, otherwise set it. */ static inline void gpio_put(uint gpio, bool value) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_bit_out_put(gpio, value); +#elif NUM_BANK0_GPIOS <= 32 uint32_t mask = 1ul << gpio; if (value) gpio_set_mask(mask); else gpio_clr_mask(mask); +#else + uint32_t mask = 1ul << (gpio & 0x1fu); + if (gpio < 32) { + if (value) { + sio_hw->gpio_set = mask; + } else { + sio_hw->gpio_clr = mask; + } + } else { + if (value) { + sio_hw->gpio_hi_set = mask; + } else { + sio_hw->gpio_hi_clr = mask; + } + } +#endif } /*! \brief Determine whether a GPIO is currently driven high or low @@ -787,7 +1186,12 @@ static inline void gpio_put(uint gpio, bool value) { * \return true if the GPIO output level is high, false if low. */ static inline bool gpio_get_out_level(uint gpio) { - return !!(sio_hw->gpio_out & (1u << gpio)); +#if NUM_BANK0_GPIOS <= 32 + return sio_hw->gpio_out & (1u << gpio); +#else + uint32_t bits = gpio < 32 ? sio_hw->gpio_out : sio_hw->gpio_hi_out; + return bits & (1u << (gpio & 0x1fu)); +#endif } // ---------------------------------------------------------------------------- @@ -799,19 +1203,61 @@ static inline bool gpio_get_out_level(uint gpio) { * * Switch all GPIOs in "mask" to output * - * \param mask Bitmask of GPIO to set to output, as bits 0-29 + * \param mask Bitmask of GPIO to set to output */ static inline void gpio_set_dir_out_masked(uint32_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_oe_set(mask); +#else + sio_hw->gpio_oe_set = mask; +#endif +} + +/*! \brief Set a number of GPIOs to output + * \ingroup hardware_gpio + * + * Switch all GPIOs in "mask" to output + * + * \param mask Bitmask of GPIO to set to output + */ +static inline void gpio_set_dir_out_masked64(uint64_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_oe_set(mask); +#elif NUM_BANK0_GPIOS <= 32 sio_hw->gpio_oe_set = mask; +#else + sio_hw->gpio_oe_set = (uint32_t)mask; + sio_hw->gpio_hi_oe_set = (uint32_t)(mask >> 32u); +#endif } /*! \brief Set a number of GPIOs to input * \ingroup hardware_gpio * - * \param mask Bitmask of GPIO to set to input, as bits 0-29 + * \param mask Bitmask of GPIO to set to input */ static inline void gpio_set_dir_in_masked(uint32_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_oe_clr(mask); +#else sio_hw->gpio_oe_clr = mask; +#endif +} + +/*! \brief Set a number of GPIOs to input + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO to set to input + */ +static inline void gpio_set_dir_in_masked64(uint64_t mask) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_oe_clr(mask); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_oe_clr = mask; +#else + sio_hw->gpio_oe_clr = (uint32_t)mask; + sio_hw->gpio_hi_oe_clr = (uint32_t)(mask >> 32u); +#endif } /*! \brief Set multiple GPIO directions @@ -826,16 +1272,63 @@ static inline void gpio_set_dir_in_masked(uint32_t mask) { * simultaneously. */ static inline void gpio_set_dir_masked(uint32_t mask, uint32_t value) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_oe_xor((gpioc_lo_oe_get() ^ value) & mask); +#else sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ value) & mask; +#endif } +/*! \brief Set multiple GPIO directions + * \ingroup hardware_gpio + * + * \param mask Bitmask of GPIO to set to input, as bits 0-29 + * \param value Values to set + * + * For each 1 bit in "mask", switch that pin to the direction given by + * corresponding bit in "value", leaving other pins unchanged. + * E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output, + * simultaneously. + */ +static inline void gpio_set_dir_masked64(uint64_t mask, uint64_t value) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_oe_xor((gpioc_hilo_oe_get() ^ value) & mask); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ (uint32_t)value) & (uint32_t)mask; +#else + sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ (uint32_t)value) & (uint32_t)mask; + sio_hw->gpio_hi_oe_togl = (sio_hw->gpio_hi_oe ^ (uint32_t)(value >> 32u)) & (uint32_t)(mask >> 32u); +#endif +} + + /*! \brief Set direction of all pins simultaneously. * \ingroup hardware_gpio * * \param values individual settings for each gpio; for GPIO N, bit N is 1 for out, 0 for in */ static inline void gpio_set_dir_all_bits(uint32_t values) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_lo_oe_put(values); +#else sio_hw->gpio_oe = values; +#endif +} + +/*! \brief Set direction of all pins simultaneously. + * \ingroup hardware_gpio + * + * \param values individual settings for each gpio; for GPIO N, bit N is 1 for out, 0 for in + */ +static inline void gpio_set_dir_all_bits64(uint64_t values) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_hilo_oe_put(values); +#elif NUM_BANK0_GPIOS <= 32 + sio_hw->gpio_oe = (uint32_t)values; +#else + sio_hw->gpio_oe = (uint32_t)values; + sio_hw->gpio_hi_oe = (uint32_t)(values >> 32u); +#endif } /*! \brief Set a single GPIO direction @@ -845,11 +1338,30 @@ static inline void gpio_set_dir_all_bits(uint32_t values) { * \param out true for out, false for in */ static inline void gpio_set_dir(uint gpio, bool out) { +#if PICO_USE_GPIO_COPROCESSOR + gpioc_bit_oe_put(gpio, out); +#elif PICO_RP2040 || NUM_BANK0_GPIOS <= 32 uint32_t mask = 1ul << gpio; if (out) gpio_set_dir_out_masked(mask); else gpio_set_dir_in_masked(mask); +#else + uint32_t mask = 1u << (gpio & 0x1fu); + if (gpio < 32) { + if (out) { + sio_hw->gpio_oe_set = mask; + } else { + sio_hw->gpio_oe_clr = mask; + } + } else { + if (out) { + sio_hw->gpio_hi_oe_set = mask; + } else { + sio_hw->gpio_hi_oe_clr = mask; + } + } +#endif } /*! \brief Check if a specific GPIO direction is OUT @@ -859,7 +1371,12 @@ static inline void gpio_set_dir(uint gpio, bool out) { * \return true if the direction for the pin is OUT */ static inline bool gpio_is_dir_out(uint gpio) { - return !!(sio_hw->gpio_oe & (1u << (gpio))); +#if NUM_BANK0_GPIOS <= 32 + return sio_hw->gpio_oe & (1u << (gpio)); +#else + uint32_t bits = gpio < 32 ? sio_hw->gpio_oe : sio_hw->gpio_hi_oe; + return bits & (1u << (gpio & 0x1fu)); +#endif } /*! \brief Get a specific GPIO direction @@ -872,6 +1389,13 @@ static inline uint gpio_get_dir(uint gpio) { return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway } +#if PICO_SECURE +static inline void gpio_assign_to_ns(uint gpio, bool ns) { + check_gpio_param(gpio); + if (ns) hw_set_bits(&accessctrl_hw->gpio_nsmask[gpio/32], 1u << (gpio & 0x1fu)); + else hw_clear_bits(&accessctrl_hw->gpio_nsmask[gpio/32], 1u << (gpio & 0x1fu)); +} +#endif extern void gpio_debug_pins_init(void); #ifdef __cplusplus diff --git a/src/rp2_common/hardware_gpio/include/hardware/gpio_coproc.h b/src/rp2_common/hardware_gpio/include/hardware/gpio_coproc.h new file mode 100644 index 000000000..d51c57a4c --- /dev/null +++ b/src/rp2_common/hardware_gpio/include/hardware/gpio_coproc.h @@ -0,0 +1,465 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_GPIO_COPROC_H +#define _HARDWARE_GPIO_COPROC_H + +#ifdef __riscv +#error "GPIO coprocessor port is not available on RISC-V" +#endif + +#if PICO_RP2040 +#error "GPIO coprocessor is not available on RP2040" +#endif + +#if !HAS_GPIO_COPROCESSOR +#error "GPIO coprocessor is not available" +#endif + +#include "pico.h" + +// ---------------------------------------------------------------------------- +// OUT mask write instructions + +// Equivalent to sio_hw->gpio_out = x; +__force_inline static void gpioc_lo_out_put(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #0, %0, c0, c0" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_togl = x; +__force_inline static void gpioc_lo_out_xor(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #1, %0, c0, c0" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_set = x; +__force_inline static void gpioc_lo_out_set(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #2, %0, c0, c0" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_clr = x; +__force_inline static void gpioc_lo_out_clr(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #3, %0, c0, c0" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_out = x; +__force_inline static void gpioc_hi_out_put(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #0, %0, c0, c1" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_togl = x; +__force_inline static void gpioc_hi_out_xor(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #1, %0, c0, c1" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_set = x; +__force_inline static void gpioc_hi_out_set(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #2, %0, c0, c1" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_clr = x; +__force_inline static void gpioc_hi_out_clr(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #3, %0, c0, c1" : : "r" (x)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_out = x & 0xffffffff; +// - sio_hw->gpio_hi_out = x >> 32; +__force_inline static void gpioc_hilo_out_put(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #0, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_togl = x & 0xffffffff; +// - sio_hw->gpio_hi_togl = x >> 32; +__force_inline static void gpioc_hilo_out_xor(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #1, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_set = x & 0xffffffff; +// - sio_hw->gpio_hi_set = x >> 32; +__force_inline static void gpioc_hilo_out_set(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #2, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_clr = x & 0xffffffff; +// - sio_hw->gpio_hi_clr = x >> 32; +__force_inline static void gpioc_hilo_out_clr(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #3, %0, %1, c0" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// ---------------------------------------------------------------------------- +// OE mask write instructions + +// Equivalent to sio_hw->gpio_oe = x; +__force_inline static void gpioc_lo_oe_put(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #0, %0, c0, c4" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_oe_togl = x; +__force_inline static void gpioc_lo_oe_xor(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #1, %0, c0, c4" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_oe_set = x; +__force_inline static void gpioc_lo_oe_set(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #2, %0, c0, c4" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_oe_clr = x; +__force_inline static void gpioc_lo_oe_clr(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #3, %0, c0, c4" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_oe = x; +__force_inline static void gpioc_hi_oe_put(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #0, %0, c0, c5" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_oe_togl = x; +__force_inline static void gpioc_hi_oe_xor(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #1, %0, c0, c5" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_oe_set = x; +__force_inline static void gpioc_hi_oe_set(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #2, %0, c0, c5" : : "r" (x)); +} + +// Equivalent to sio_hw->gpio_hi_oe_clr = x; +__force_inline static void gpioc_hi_oe_clr(uint32_t x) { + pico_default_asm_volatile ("mcr p0, #3, %0, c0, c5" : : "r" (x)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_oe = x & 0xffffffff; +// - sio_hw->gpio_hi_oe = x >> 32; +__force_inline static void gpioc_hilo_oe_put(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #0, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_oe_togl = x & 0xffffffff; +// - sio_hw->gpio_hi_oe_togl = x >> 32; +__force_inline static void gpioc_hilo_oe_xor(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #1, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_oe_set = x & 0xffffffff; +// - sio_hw->gpio_hi_oe_set = x >> 32; +__force_inline static void gpioc_hilo_oe_set(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #2, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// Equivalent to these two operations performed on the same cycle: +// - sio_hw->gpio_oe_clr = x & 0xffffffff; +// - sio_hw->gpio_hi_oe_clr = x >> 32; +__force_inline static void gpioc_hilo_oe_clr(uint64_t x) { + pico_default_asm_volatile ("mcrr p0, #3, %0, %1, c4" : : "r" (x & 0xffffffffu), "r" (x >> 32)); +} + +// ---------------------------------------------------------------------------- +// Single-bit write instructions + +// Write a 1-bit value to any output. Equivalent to: +// +// if (val) +// gpioc_hilo_out_set(1ull << pin); +// else +// gpioc_hilo_out_clr(1ull << pin); +__force_inline static void gpioc_bit_out_put(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c0" : : "r" (pin), "r" (val)); +} + +// Unconditionally toggle any single output. Equivalent to: +// +// gpioc_hilo_out_xor(1ull << pin); +__force_inline static void gpioc_bit_out_xor(uint pin) { + pico_default_asm_volatile ("mcr p0, #5, %0, c0, c0" : : "r" (pin)); +} + +// Unconditionally set any single output. Equivalent to: +// +// gpioc_hilo_out_set(1ull << pin); +__force_inline static void gpioc_bit_out_set(uint pin) { + pico_default_asm_volatile ("mcr p0, #6, %0, c0, c0" : : "r" (pin)); +} + +// Unconditionally clear any single output. Equivalent to: +// +// gpioc_hilo_out_clr(1ull << pin); +__force_inline static void gpioc_bit_out_clr(uint pin) { + pico_default_asm_volatile ("mcr p0, #7, %0, c0, c0" : : "r" (pin)); +} + +// Conditionally toggle any single output. Equivalent to: +// +// gpioc_hilo_out_xor((uint64_t)val << pin); +__force_inline static void gpioc_bit_out_xor2(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #5, %0, %1, c0" : : "r" (pin), "r" (val)); +} + +// Conditionally set any single output. Equivalent to: +// +// gpioc_hilo_out_set((uint64_t)val << pin); +__force_inline static void gpioc_bit_out_set2(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #6, %0, %1, c0" : : "r" (pin), "r" (val)); +} + +// Conditionally clear any single output. Equivalent to: +// +// gpioc_hilo_out_clr((uint64_t)val << pin); +__force_inline static void gpioc_bit_out_clr2(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #7, %0, %1, c0" : : "r" (pin), "r" (val)); +} + +// Write a 1-bit value to any output enable. Equivalent to: +// +// if (val) +// gpioc_hilo_oe_set(1ull << pin); +// else +// gpioc_hilo_oe_clr(1ull << pin); +__force_inline static void gpioc_bit_oe_put(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c4" : : "r" (pin), "r" (val)); +} + +// Unconditionally toggle any output enable. Equivalent to: +// +// gpioc_hilo_oe_xor(1ull << pin); +__force_inline static void gpioc_bit_oe_xor(uint pin) { + pico_default_asm_volatile ("mcr p0, #5, %0, c0, c4" : : "r" (pin)); +} + +// Unconditionally set any output enable (set to output). Equivalent to: +// +// gpioc_hilo_oe_set(1ull << pin); +__force_inline static void gpioc_bit_oe_set(uint pin) { + pico_default_asm_volatile ("mcr p0, #6, %0, c0, c4" : : "r" (pin)); +} + +// Unconditionally clear any output enable (set to input). Equivalent to: +// +// gpioc_hilo_oe_clr(1ull << pin); +__force_inline static void gpioc_bit_oe_clr(uint pin) { + pico_default_asm_volatile ("mcr p0, #7, %0, c0, c4" : : "r" (pin)); +} + +// Conditionally toggle any output enable. Equivalent to: +// +// gpioc_hilo_oe_xor((uint64_t)val << pin); +__force_inline static void gpioc_bit_oe_xor2(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #5, %0, %1, c4" : : "r" (pin), "r" (val)); +} + +// Conditionally set any output enable (set to output). Equivalent to: +// +// gpioc_hilo_oe_set((uint64_t)val << pin); +__force_inline static void gpioc_bit_oe_set2(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #6, %0, %1, c4" : : "r" (pin), "r" (val)); +} + +// Conditionally clear any output enable (set to input). Equivalent to: +// +// gpioc_hilo_oe_clr((uint64_t)val << pin); +__force_inline static void gpioc_bit_oe_clr2(uint pin, bool val) { + pico_default_asm_volatile ("mcrr p0, #7, %0, %1, c4" : : "r" (pin), "r" (val)); +} + +// ---------------------------------------------------------------------------- +// Indexed mask write instructions -- write to a dynamically selected 32-bit +// GPIO register + +// Write to a selected GPIO output register. Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_out_put(val); +// } else if (reg_index == 1) { +// gpioc_hi_out_put(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_out_put(uint reg_index, uint32_t val) { + pico_default_asm_volatile ("mcrr p0, #8, %1, %0, c0" : : "r" (reg_index), "r" (val)); +} + +// Toggle bits in a selected GPIO output register. Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_out_xor(val); +// } else if (reg_index == 1) { +// gpioc_hi_out_xor(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_out_xor(uint reg_index, uint32_t mask) { + pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c0" : : "r" (reg_index), "r" (mask)); +} + +// Set bits in a selected GPIO output register. Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_out_set(val); +// } else if (reg_index == 1) { +// gpioc_hi_out_set(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_out_set(uint reg_index, uint32_t mask) { + pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c0" : : "r" (reg_index), "r" (mask)); +} + +// Clear bits in a selected GPIO output register. Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_out_clr(val); +// } else if (reg_index == 1) { +// gpioc_hi_out_clr(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_out_clr(uint reg_index, uint32_t mask) { + pico_default_asm_volatile ("mcrr p0, #11, %1, %0, c0" : : "r" (reg_index), "r" (mask)); +} + +// Write to a selected GPIO output enable register. Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_oe_put(val); +// } else if (reg_index == 1) { +// gpioc_hi_oe_put(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_oe_put(uint reg_index, uint32_t val) { + pico_default_asm_volatile ("mcrr p0, #8, %1, %0, c4" : : "r" (reg_index), "r" (val)); +} + +// Toggle bits in a selected GPIO output enable register. Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_oe_xor(val); +// } else if (reg_index == 1) { +// gpioc_hi_oe_xor(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_oe_xor(uint reg_index, uint32_t mask) { + pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c4" : : "r" (reg_index), "r" (mask)); +} + +// Set bits in a selected GPIO output enable register (set to output). Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_oe_set(val); +// } else if (reg_index == 1) { +// gpioc_hi_oe_set(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_oe_set(uint reg_index, uint32_t mask) { + pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c4" : : "r" (reg_index), "r" (mask)); +} + +// Clear bits in a selected GPIO output enable register (set to input). Equivalent to: +// +// if (reg_index == 0) { +// gpioc_lo_oe_clr(val); +// } else if (reg_index == 1) { +// gpioc_hi_oe_clr(val); +// } else { +// // undefined +// } +__force_inline static void gpioc_index_oe_clr(uint reg_index, uint32_t mask) { + pico_default_asm_volatile ("mcrr p0, #11, %1, %0, c4" : : "r" (reg_index), "r" (mask)); +} + +// ---------------------------------------------------------------------------- +// Read instructions + +// Read back the lower 32-bit output register. Equivalent to: +// +// return sio_hw->gpio_out; +__force_inline static uint32_t gpioc_lo_out_get(void) { + uint32_t lo; + pico_default_asm_volatile ("mrc p0, #0, %0, c0, c0" : "=r" (lo)); + return lo; +} + +// Read back the upper 32-bit output register. Equivalent to: +// +// return sio_hw->gpio_hi_out; +__force_inline static uint32_t gpioc_hi_out_get(void) { + uint32_t hi; + pico_default_asm_volatile ("mrc p0, #0, %0, c0, c1" : "=r" (hi)); + return hi; +} + +// Read back two 32-bit output registers in a single operation. Equivalent to: +// +// return sio_hw->gpio_out | ((uint64_t)sio_hw->gpio_hi_out << 32); +__force_inline static uint64_t gpioc_hilo_out_get(void) { + uint32_t hi, lo; + pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c0" : "=r" (lo), "=r" (hi)); + return ((uint64_t)hi << 32) | lo; +} + +// Read back the lower 32-bit output enable register. Equivalent to: +// +// return sio_hw->gpio_oe; +__force_inline static uint32_t gpioc_lo_oe_get(void) { + uint32_t lo; + pico_default_asm_volatile ("mrc p0, #0, %0, c0, c4" : "=r" (lo)); + return lo; +} + +// Read back the upper 32-bit output enable register. Equivalent to: +// +// return sio_hw->gpio_hi_oe; +__force_inline static uint32_t gpioc_hi_oe_get(void) { + uint32_t hi; + pico_default_asm_volatile ("mrc p0, #0, %0, c0, c5" : "=r" (hi)); + return hi; +} + +// Read back two 32-bit output enable registers in a single operation. Equivalent to: +// +// return sio_hw->gpio_oe | ((uint64_t)sio_hw->gpio_hi_oe << 32); +__force_inline static uint64_t gpioc_hilo_oe_get(void) { + uint32_t hi, lo; + pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c4" : "=r" (lo), "=r" (hi)); + return ((uint64_t)hi << 32) | lo; +} + +// Sample the lower 32 GPIOs. Equivalent to: +// +// return sio_hw->gpio_in; +__force_inline static uint32_t gpioc_lo_in_get(void) { + uint32_t lo; + pico_default_asm_volatile ("mrc p0, #0, %0, c0, c8" : "=r" (lo)); + return lo; +} + +// Sample the upper 32 GPIOs. Equivalent to: +// +// return sio_hw->gpio_hi_in; +__force_inline static uint32_t gpioc_hi_in_get(void) { + uint32_t hi; + pico_default_asm_volatile ("mrc p0, #0, %0, c0, c9" : "=r" (hi)); + return hi; +} + +// Sample 64 GPIOs on the same cycle. Equivalent to: +// +// return sio_hw->gpio_in | ((uint64_t)sio_hw->gpio_hi_in << 32); +__force_inline static uint64_t gpioc_hilo_in_get(void) { + uint32_t hi, lo; + pico_default_asm_volatile ("mrrc p0, #0, %0, %1, c8" : "=r" (lo), "=r" (hi)); + return ((uint64_t)hi << 32) | lo; +} + +#endif diff --git a/src/rp2_common/hardware_hazard3/BUILD.bazel b/src/rp2_common/hardware_hazard3/BUILD.bazel new file mode 100644 index 000000000..499fed4ca --- /dev/null +++ b/src/rp2_common/hardware_hazard3/BUILD.bazel @@ -0,0 +1,15 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_hazard3", + hdrs = ["include/hardware/hazard3.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2() + ["@platforms//cpu:riscv32"], + deps = [ + "//src/rp2_common:hardware_regs", + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_riscv", + ], +) diff --git a/src/rp2_common/hardware_hazard3/CMakeLists.txt b/src/rp2_common/hardware_hazard3/CMakeLists.txt new file mode 100644 index 000000000..69635e402 --- /dev/null +++ b/src/rp2_common/hardware_hazard3/CMakeLists.txt @@ -0,0 +1,2 @@ +pico_simple_hardware_headers_only_target(hazard3) +target_link_libraries(hardware_hazard3 INTERFACE hardware_riscv) diff --git a/src/rp2_common/hardware_hazard3/include/hardware/hazard3.h b/src/rp2_common/hardware_hazard3/include/hardware/hazard3.h new file mode 100644 index 000000000..77272ff80 --- /dev/null +++ b/src/rp2_common/hardware_hazard3/include/hardware/hazard3.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_HAZARD3_ +#define _HARDWARE_HAZARD3_ + +#include "pico.h" +#include "hardware/riscv.h" +#include "hardware/regs/rvcsr.h" + +/** \file hardware/hazard3.h + * \defgroup hardware_hazard3 hardware_hazard3 + * + * \brief Accessors for Hazard3-specific RISC-V CSRs, and intrinsics for Hazard3 custom instructions + * + */ + +// Feature detection macros for Hazard3 custom extensions +#if PICO_RP2350 +#define __hazard3_extension_xh3power +#define __hazard3_extension_xh3bextm +#define __hazard3_extension_xh3irq +#define __hazard3_extension_xh3pmpm +#endif + +#ifdef __ASSEMBLER__ + +// Assembly language instruction macros for Hazard3 custom instructions + +// h3.bextm: Extract up to 8 consecutive bits from register rs1, with the +// first bit indexed by rs2, and bit count configured by an immediate value. +// R-format instruction. Pseudocode: +// +// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits) + +.macro h3.bextm rd rs1 rs2 nbits +.if (\nbits < 1) || (\nbits > 8) +.err +.endif +#ifdef __hazard3_extension_xh3bextm + .insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2 +#else + srl \rd, \rs1, \rs2 + andi \rd, \rd, ((1 << \nbits) - 1) +#endif +.endm + +// h3.bextmi: Extract up to 8 consecutive bits from register rs1, with the +// first bit index and the number of bits both configured by immediate +// values. I-format instruction. Pseudocode: +// +// rd = (rs1 >> shamt) & ~(-1 << nbits) + +.macro h3.bextmi rd rs1 shamt nbits +.if (\nbits < 1) || (\nbits > 8) +.err +.endif +.if (\shamt < 0) || (\shamt > 31) +.err +.endif +#ifdef __hazard3_extension_xh3bextm + .insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6) +#else + srli \rd, \rs1, \shamt + andi \rd, \rd, ((1 << \nbits) - 1) +#endif +.endm + +// h3.block: enter an idle state until another processor in the same +// multiprocessor complex executes an h3.unblock instruction, or the +// processor is interrupted. Fall through immediately if an h3.unblock has +// been received since the last execution of an h3.block on this processor. +// On RP2350, processors also have their own h3.unblock signals reflected +// back to them. + +.macro h3.block +#ifdef __hazard3_extension_xh3power + slt x0, x0, x0 +#else + nop +#endif +.endm + +// h3.unblock: signal other processors in the same multiprocessor complex to +// exit the idle state entered by an h3.block instruction. On RP2350, this +// signal is also reflected back to the processor that executed the +// h3.unblock, which will cause that processor's next h3.block to fall +// through immediately. + +.macro h3.unblock +#ifdef __hazard3_extension_xh3power + slt x0, x0, x1 +#else + nop +#endif +.endm + +#else // !__ASSEMBLER__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __hazard3_extension_xh3irq +#define hazard3_irqarray_read(csr, index) (riscv_read_set_csr(csr, (index)) >> 16) +#else +#define hazard3_irqarray_read(csr, index) static_assert(false, "Not supported: Xh3irq extension") +#endif + +#ifdef __hazard3_extension_xh3irq +#define hazard3_irqarray_write(csr, index, data) (riscv_write_csr(csr, (index) | ((uint32_t)(data) << 16))) +#else +#define hazard3_irqarray_write(csr, index, data) static_assert(false, "Not supported: Xh3irq extension") +#endif + +#ifdef __hazard3_extension_xh3irq +#define hazard3_irqarray_set(csr, index, data) (riscv_set_csr(csr, (index) | ((uint32_t)(data) << 16))) +#else +#define hazard3_irqarray_set(csr, index, data) static_assert(false, "Not supported: Xh3irq extension") +#endif + +#ifdef __hazard3_extension_xh3irq +#define hazard3_irqarray_clear(csr, index, data) (riscv_clear_csr(csr, (index) | ((uint32_t)(data) << 16))) +#else +#define hazard3_irqarray_clear(csr, index, data) static_assert(false, "Not supported: Xh3irq extension") +#endif + + +// nbits must be a constant expression +#ifdef __hazard3_extension_xh3bextm +#define __hazard3_bextm(nbits, rs1, rs2) ({\ + uint32_t __h3_bextm_rd; \ + asm (".insn r 0x0b, 0, %3, %0, %1, %2"\ + : "=r" (__h3_bextm_rd) \ + : "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\ + ); \ + __h3_bextm_rd; \ +}) +#else +#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((rs2) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) +#endif + +// nbits and shamt must be constant expressions +#ifdef __hazard3_extension_xh3bextm +#define __hazard3_bextmi(nbits, rs1, shamt) ({\ + uint32_t __h3_bextmi_rd; \ + asm (".insn i 0x0b, 0x4, %0, %1, %2"\ + : "=r" (__h3_bextmi_rd) \ + : "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \ + ); \ + __h3_bextmi_rd; \ +}) +#else +#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((shamt) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) +#endif + +#ifdef __hazard3_extension_xh3power +#define __hazard3_block() asm volatile ("slt x0, x0, x0" : : : "memory") +#else +#define __hazard3_block() do {} while (0) +#endif + +#ifdef __hazard3_extension_xh3power +#define __hazard3_unblock() asm volatile ("slt x0, x0, x1" : : : "memory") +#else +#define __hazard3_unblock() do {} while (0) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // !__ASSEMBLER__ + +#endif diff --git a/src/rp2_common/hardware_i2c/BUILD.bazel b/src/rp2_common/hardware_i2c/BUILD.bazel index 9dd54e7d7..877add95c 100644 --- a/src/rp2_common/hardware_i2c/BUILD.bazel +++ b/src/rp2_common/hardware_i2c/BUILD.bazel @@ -9,11 +9,11 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_resets", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_i2c/i2c.c b/src/rp2_common/hardware_i2c/i2c.c index c5cdbec3a..865c16f3b 100644 --- a/src/rp2_common/hardware_i2c/i2c.c +++ b/src/rp2_common/hardware_i2c/i2c.c @@ -16,13 +16,13 @@ i2c_inst_t i2c0_inst = {i2c0_hw, false}; i2c_inst_t i2c1_inst = {i2c1_hw, false}; static inline void i2c_reset(i2c_inst_t *i2c) { - invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1); - reset_block(i2c == i2c0 ? RESETS_RESET_I2C0_BITS : RESETS_RESET_I2C1_BITS); + invalid_params_if(HARDWARE_I2C, i2c != i2c0 && i2c != i2c1); + reset_block_num(i2c == i2c0 ? RESET_I2C0 : RESET_I2C1); } static inline void i2c_unreset(i2c_inst_t *i2c) { - invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1); - unreset_block_wait(i2c == i2c0 ? RESETS_RESET_I2C0_BITS : RESETS_RESET_I2C1_BITS); + invalid_params_if(HARDWARE_I2C, i2c != i2c0 && i2c != i2c1); + unreset_block_num_wait_blocking(i2c == i2c0 ? RESET_I2C0 : RESET_I2C1); } // Addresses of the form 000 0xxx or 111 1xxx are reserved. No slave should @@ -60,7 +60,7 @@ void i2c_deinit(i2c_inst_t *i2c) { } uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) { - invalid_params_if(I2C, baudrate == 0); + invalid_params_if(HARDWARE_I2C, baudrate == 0); // I2C is synchronous design that runs from clk_sys uint freq_in = clock_get_hz(clk_sys); @@ -69,10 +69,10 @@ uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) { uint lcnt = period * 3 / 5; // oof this one hurts uint hcnt = period - lcnt; // Check for out-of-range divisors: - invalid_params_if(I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS); - invalid_params_if(I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS); - invalid_params_if(I2C, hcnt < 8); - invalid_params_if(I2C, lcnt < 8); + invalid_params_if(HARDWARE_I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS); + invalid_params_if(HARDWARE_I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS); + invalid_params_if(HARDWARE_I2C, hcnt < 8); + invalid_params_if(HARDWARE_I2C, lcnt < 8); // Per I2C-bus specification a device in standard or fast mode must // internally provide a hold time of at least 300ns for the SDA signal to @@ -110,8 +110,8 @@ uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) { } void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) { - invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses - invalid_params_if(I2C, i2c_reserved_addr(addr)); + invalid_params_if(HARDWARE_I2C, addr >= 0x80); // 7-bit addresses + invalid_params_if(HARDWARE_I2C, i2c_reserved_addr(addr)); i2c->hw->enable = 0; uint32_t ctrl_set_if_master = I2C_IC_CON_MASTER_MODE_BITS | I2C_IC_CON_IC_SLAVE_DISABLE_BITS; uint32_t ctrl_set_if_slave = I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS; @@ -132,12 +132,12 @@ void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) { static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, check_timeout_fn timeout_check, struct timeout_state *ts) { - invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses - invalid_params_if(I2C, i2c_reserved_addr(addr)); + invalid_params_if(HARDWARE_I2C, addr >= 0x80); // 7-bit addresses + invalid_params_if(HARDWARE_I2C, i2c_reserved_addr(addr)); // Synopsys hw accepts start/stop flags alongside data items in the same // FIFO word, so no 0 byte transfers. - invalid_params_if(I2C, len == 0); - invalid_params_if(I2C, ((int)len) < 0); + invalid_params_if(HARDWARE_I2C, len == 0); + invalid_params_if(HARDWARE_I2C, ((int)len) < 0); i2c->hw->enable = 0; i2c->hw->tar = addr; @@ -154,6 +154,10 @@ static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint bool first = byte_ctr == 0; bool last = byte_ctr == ilen - 1; + if (timeout_check) { + timeout_check(ts, true); // for per iteration checks, this will reset the timeout + } + i2c->hw->data_cmd = bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB | bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB | @@ -165,7 +169,7 @@ static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint // was set in i2c_init. do { if (timeout_check) { - timeout = timeout_check(ts); + timeout = timeout_check(ts, false); abort |= timeout; } tight_loop_contents(); @@ -184,14 +188,14 @@ static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint if (abort || (last && !nostop)) { // If the transaction was aborted or if it completed - // successfully wait until the STOP condition has occured. + // successfully wait until the STOP condition has occurred. // TODO Could there be an abort while waiting for the STOP // condition here? If so, additional code would be needed here // to take care of the abort. do { if (timeout_check) { - timeout = timeout_check(ts); + timeout = timeout_check(ts, false); abort |= timeout; } tight_loop_contents(); @@ -257,10 +261,10 @@ int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t * static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, check_timeout_fn timeout_check, timeout_state_t *ts) { - invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses - invalid_params_if(I2C, i2c_reserved_addr(addr)); - invalid_params_if(I2C, len == 0); - invalid_params_if(I2C, ((int)len) < 0); + invalid_params_if(HARDWARE_I2C, addr >= 0x80); // 7-bit addresses + invalid_params_if(HARDWARE_I2C, i2c_reserved_addr(addr)); + invalid_params_if(HARDWARE_I2C, len == 0); + invalid_params_if(HARDWARE_I2C, ((int)len) < 0); i2c->hw->enable = 0; i2c->hw->tar = addr; @@ -274,6 +278,10 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) { bool first = byte_ctr == 0; bool last = byte_ctr == ilen - 1; + if (timeout_check) { + timeout_check(ts, true); // for per iteration checks, this will reset the timeout + } + while (!i2c_get_write_available(i2c)) tight_loop_contents(); @@ -286,7 +294,7 @@ static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *ds abort_reason = i2c->hw->tx_abrt_source; abort = (bool) i2c->hw->clr_tx_abrt; if (timeout_check) { - timeout = timeout_check(ts); + timeout = timeout_check(ts, false); abort |= timeout; } } while (!abort && !i2c_get_read_available(i2c)); diff --git a/src/rp2_common/hardware_i2c/include/hardware/i2c.h b/src/rp2_common/hardware_i2c/include/hardware/i2c.h index 7327e5f8b..13bafcc2d 100644 --- a/src/rp2_common/hardware_i2c/include/hardware/i2c.h +++ b/src/rp2_common/hardware_i2c/include/hardware/i2c.h @@ -12,11 +12,14 @@ #include "hardware/structs/i2c.h" #include "hardware/regs/dreq.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c -#ifndef PARAM_ASSERTIONS_ENABLED_I2C -#define PARAM_ASSERTIONS_ENABLED_I2C 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C, Enable/disable assertions in the hardware_i2c module, type=bool, default=0, group=hardware_i2c +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C +#ifdef PARAM_ASSERTIONS_ENABLED_I2C // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C PARAM_ASSERTIONS_ENABLED_I2C +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_I2C 0 +#endif #endif - #ifdef __cplusplus extern "C" { #endif @@ -51,9 +54,9 @@ extern "C" { typedef struct i2c_inst i2c_inst_t; -// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, group=hardware_i2c -// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, group=hardware_i2c -// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, group=hardware_i2c +// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, default=Usually provided via board header, group=hardware_i2c +// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, default=Usually provided via board header, group=hardware_i2c +// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, default=Usually provided via board header, group=hardware_i2c /** The I2C identifiers for use in I2C functions. * @@ -69,11 +72,24 @@ extern i2c_inst_t i2c1_inst; #define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1 #if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C) -#define PICO_DEFAULT_I2C_INSTANCE (__CONCAT(i2c,PICO_DEFAULT_I2C)) +#define PICO_DEFAULT_I2C_INSTANCE() (__CONCAT(i2c,PICO_DEFAULT_I2C)) #endif +/** + * \def PICO_DEFAULT_I2C + * \ingroup hardware_i2c + * \hideinitializer + * \brief The default I2C instance number + */ + +/** + * \def PICO_DEFAULT_I2C_INSTANCE() + * \ingroup hardware_i2c + * \hideinitializer + * \brief Returns the default I2C instance based on the value of PICO_DEFAULT_I2C + */ #ifdef PICO_DEFAULT_I2C_INSTANCE -#define i2c_default PICO_DEFAULT_I2C_INSTANCE +#define i2c_default PICO_DEFAULT_I2C_INSTANCE() #endif /** @} */ @@ -137,16 +153,47 @@ struct i2c_inst { bool restart_on_next; }; -/*! \brief Convert I2C instance to hardware instance number - * \ingroup hardware_i2c +/** + * \def I2C_NUM(i2c) + * \ingroup hardware_i2c + * \hideinitializer + * \brief Returns the I2C number for a I2C instance * - * \param i2c I2C instance - * \return Number of I2C, 0 or 1. + * Note this macro is intended to resolve at compile time, and does no parameter checking */ -static inline uint i2c_hw_index(i2c_inst_t *i2c) { - invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1); - return i2c == i2c1 ? 1 : 0; -} +#ifndef I2C_NUM +static_assert(NUM_I2CS == 2, ""); +#define I2C_NUM(i2c) ((i2c) == i2c1) +#endif + +/** + * \def I2C_INSTANCE(i2c_num) + * \ingroup hardware_i2c + * \hideinitializer + * \brief Returns the I2C instance with the given I2C number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef I2C_INSTANCE +static_assert(NUM_I2CS == 2, ""); +#define I2C_INSTANCE(num) ((num) ? i2c1 : i2c0) +#endif + +/** + * \def I2C_DREQ_NUM(i2c, is_tx) + * \ingroup hardware_i2c + * \hideinitializer + * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from this I2C instance. + * If is_tx is true, then it is for transfers to the I2C instance else for transfers from the I2C instance. + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef I2C_DREQ_NUM +static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, ""); +static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, ""); +static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, ""); +#define I2C_DREQ_NUM(i2c,is_tx) (DREQ_I2C0_TX + I2C_NUM(i2c) * 2 + !(is_tx)) +#endif /*! \brief Convert I2C instance to hardware instance number * \ingroup hardware_i2c @@ -155,9 +202,13 @@ static inline uint i2c_hw_index(i2c_inst_t *i2c) { * \return Number of I2C, 0 or 1. */ static inline uint i2c_get_index(i2c_inst_t *i2c) { - return i2c_hw_index(i2c); + invalid_params_if(HARDWARE_I2C, i2c != i2c0 && i2c != i2c1); + return I2C_NUM(i2c); } +// backward compatibility +#define i2c_hw_index(i2c) i2c_get_index(i2c) + /*! \brief Return pointer to structure containing i2c hardware registers * \ingroup hardware_i2c * @@ -172,13 +223,12 @@ static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) { /*! \brief Convert I2C hardware instance number to I2C instance * \ingroup hardware_i2c * - * \param Number of I2C, 0 or 1 + * \param num Number of I2C, 0 or 1 * \return I2C hardware instance */ -static inline i2c_inst_t *i2c_get_instance(uint instance) { - static_assert(NUM_I2CS == 2, ""); - invalid_params_if(I2C, instance >= NUM_I2CS); - return instance ? i2c1 : i2c0; +static inline i2c_inst_t *i2c_get_instance(uint num) { + invalid_params_if(HARDWARE_I2C, num >= NUM_I2CS); + return I2C_INSTANCE(num); } /*! \brief Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached. @@ -370,7 +420,6 @@ static inline void i2c_write_byte_raw(i2c_inst_t *i2c, uint8_t value) { hw->data_cmd = value; } - /*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance * \ingroup hardware_i2c * @@ -378,10 +427,7 @@ static inline void i2c_write_byte_raw(i2c_inst_t *i2c, uint8_t value) { * \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance */ static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) { - static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, ""); - static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, ""); - static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, ""); - return DREQ_I2C0_TX + i2c_hw_index(i2c) * 2 + !is_tx; + return I2C_DREQ_NUM(i2c, is_tx); } #ifdef __cplusplus diff --git a/src/rp2_common/hardware_interp/BUILD.bazel b/src/rp2_common/hardware_interp/BUILD.bazel index 861fae5b8..e26b2a0bc 100644 --- a/src/rp2_common/hardware_interp/BUILD.bazel +++ b/src/rp2_common/hardware_interp/BUILD.bazel @@ -9,9 +9,9 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", - "//src/rp2_common/hardware_claim", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/common/hardware_claim", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", ], ) diff --git a/src/rp2_common/hardware_interp/include/hardware/interp.h b/src/rp2_common/hardware_interp/include/hardware/interp.h index 01b544980..edf541c8a 100644 --- a/src/rp2_common/hardware_interp/include/hardware/interp.h +++ b/src/rp2_common/hardware_interp/include/hardware/interp.h @@ -11,9 +11,13 @@ #include "hardware/structs/interp.h" #include "hardware/regs/sio.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_INTERP, Enable/disable assertions in the interpolation module, type=bool, default=0, group=hardware_interp -#ifndef PARAM_ASSERTIONS_ENABLED_INTERP -#define PARAM_ASSERTIONS_ENABLED_INTERP 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP, Enable/disable assertions in the hardware_interp module, type=bool, default=0, group=hardware_interp +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP +#ifdef PARAM_ASSERTIONS_ENABLED_INTERP // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP PARAM_ASSERTIONS_ENABLED_INTERP +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_INTERP 0 +#endif #endif #ifdef __cplusplus @@ -35,7 +39,8 @@ extern "C" { * flexible configuration make it possible to optimise many other tasks such as quantization and * dithering, table lookup address generation, affine texture mapping, decompression and linear feedback. * - * Please refer to the RP2040 datasheet for more information on the HW interpolators and how they work. + * Please refer to the appropriate RP-series microcontroller datasheet for more information on the HW + * interpolators and how they work. */ #define interp0 interp0_hw @@ -55,7 +60,7 @@ typedef struct { } interp_config; static inline uint interp_index(interp_hw_t *interp) { - valid_params_if(INTERP, interp == interp0 || interp == interp1); + valid_params_if(HARDWARE_INTERP, interp == interp0 || interp == interp1); return interp == interp1 ? 1 : 0; } @@ -119,7 +124,7 @@ void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask); * \param shift Number of bits */ static inline void interp_config_set_shift(interp_config *c, uint shift) { - valid_params_if(INTERP, shift < 32); + valid_params_if(HARDWARE_INTERP, shift < 32); c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) | ((shift << SIO_INTERP0_CTRL_LANE0_SHIFT_LSB) & SIO_INTERP0_CTRL_LANE0_SHIFT_BITS); } @@ -134,8 +139,8 @@ static inline void interp_config_set_shift(interp_config *c, uint shift) { * \param mask_msb The most significant bit allowed to pass */ static inline void interp_config_set_mask(interp_config *c, uint mask_lsb, uint mask_msb) { - valid_params_if(INTERP, mask_msb < 32); - valid_params_if(INTERP, mask_lsb <= mask_msb); + valid_params_if(HARDWARE_INTERP, mask_msb < 32); + valid_params_if(HARDWARE_INTERP, mask_lsb <= mask_msb); c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS)) | ((mask_lsb << SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS) | ((mask_msb << SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS); @@ -243,7 +248,7 @@ static inline void interp_config_set_clamp(interp_config *c, bool clamp) { * \param bits Sets the force bits to that specified. Range 0-3 (two bits) */ static inline void interp_config_set_force_bits(interp_config *c, uint bits) { - invalid_params_if(INTERP, bits > 3); + invalid_params_if(HARDWARE_INTERP, bits > 3); // note cannot use hw_set_bits on SIO c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) | (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB); @@ -273,10 +278,10 @@ static inline interp_config interp_default_config(void) { */ static inline void interp_set_config(interp_hw_t *interp, uint lane, interp_config *config) { - invalid_params_if(INTERP, lane > 1); - invalid_params_if(INTERP, config->ctrl & SIO_INTERP1_CTRL_LANE0_CLAMP_BITS && + invalid_params_if(HARDWARE_INTERP, lane > 1); + invalid_params_if(HARDWARE_INTERP, config->ctrl & SIO_INTERP1_CTRL_LANE0_CLAMP_BITS && (!interp_index(interp) || lane)); // only interp1 lane 0 has clamp bit - invalid_params_if(INTERP, config->ctrl & SIO_INTERP0_CTRL_LANE0_BLEND_BITS && + invalid_params_if(HARDWARE_INTERP, config->ctrl & SIO_INTERP0_CTRL_LANE0_BLEND_BITS && (interp_index(interp) || lane)); // only interp0 lane 0 has blend bit interp->ctrl[lane] = config->ctrl; } diff --git a/src/rp2_common/hardware_interp/interp.c b/src/rp2_common/hardware_interp/interp.c index 37e8a9133..eaa408b31 100644 --- a/src/rp2_common/hardware_interp/interp.c +++ b/src/rp2_common/hardware_interp/interp.c @@ -12,8 +12,6 @@ check_hw_size(interp_hw_t, SIO_INTERP1_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET check_hw_layout(sio_hw_t, interp, SIO_INTERP0_ACCUM0_OFFSET); -static_assert(NUM_DMA_CHANNELS <= 16, ""); - static uint8_t _claimed; static inline uint interp_lane_bit(interp_hw_t * interp, uint lane) { @@ -21,28 +19,28 @@ static inline uint interp_lane_bit(interp_hw_t * interp, uint lane) { } void interp_claim_lane(interp_hw_t *interp, uint lane) { - valid_params_if(INTERP, lane < 2); + valid_params_if(HARDWARE_INTERP, lane < 2); hw_claim_or_assert((uint8_t *) &_claimed, interp_lane_bit(interp, lane), "Lane is already claimed"); } void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) { - valid_params_if(INTERP, lane_mask && lane_mask <= 0x3); + valid_params_if(HARDWARE_INTERP, lane_mask && lane_mask <= 0x3); if (lane_mask & 1u) interp_claim_lane(interp, 0); if (lane_mask & 2u) interp_claim_lane(interp, 1); } void interp_unclaim_lane(interp_hw_t *interp, uint lane) { - valid_params_if(INTERP, lane < 2); + valid_params_if(HARDWARE_INTERP, lane < 2); hw_claim_clear((uint8_t *) &_claimed, interp_lane_bit(interp, lane)); } bool interp_lane_is_claimed(interp_hw_t *interp, uint lane) { - valid_params_if(INTERP, lane < 2); + valid_params_if(HARDWARE_INTERP, lane < 2); return hw_is_claimed((uint8_t *) &_claimed, interp_lane_bit(interp, lane)); } void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask) { - valid_params_if(INTERP, lane_mask <= 0x3); + valid_params_if(HARDWARE_INTERP, lane_mask <= 0x3); if (lane_mask & 1u) interp_unclaim_lane(interp, 0); if (lane_mask & 2u) interp_unclaim_lane(interp, 1); } diff --git a/src/rp2_common/hardware_irq/BUILD.bazel b/src/rp2_common/hardware_irq/BUILD.bazel index ffa7b570c..498fd22a7 100644 --- a/src/rp2_common/hardware_irq/BUILD.bazel +++ b/src/rp2_common/hardware_irq/BUILD.bazel @@ -12,13 +12,13 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", + "//src/common/hardware_claim", "//src/common/pico_sync", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform_internal", + "//src/rp2_common:platform_defs", "//src/rp2_common/hardware_base", - "//src/rp2_common/hardware_claim", - "//src/rp2_common/pico_platform", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", - "//src/rp2_common/pico_platform:platform_defs", ], + alwayslink = True, ) diff --git a/src/rp2_common/hardware_irq/CMakeLists.txt b/src/rp2_common/hardware_irq/CMakeLists.txt index 44ac7c139..4795f85ff 100644 --- a/src/rp2_common/hardware_irq/CMakeLists.txt +++ b/src/rp2_common/hardware_irq/CMakeLists.txt @@ -4,4 +4,7 @@ pico_simple_hardware_target(irq) target_sources(hardware_irq INTERFACE ${CMAKE_CURRENT_LIST_DIR}/irq_handler_chain.S) -pico_mirrored_target_link_libraries(hardware_irq INTERFACE pico_sync) \ No newline at end of file +target_link_libraries(hardware_irq INTERFACE pico_sync) # not mirrored as only implementation requires it +if (PICO_RISCV) + pico_mirrored_target_link_libraries(hardware_irq INTERFACE hardware_hazard3) +endif() diff --git a/src/rp2_common/hardware_irq/include/hardware/irq.h b/src/rp2_common/hardware_irq/include/hardware/irq.h index 44b6f7991..207b9d7db 100644 --- a/src/rp2_common/hardware_irq/include/hardware/irq.h +++ b/src/rp2_common/hardware_irq/include/hardware/irq.h @@ -28,12 +28,13 @@ #include "pico.h" #include "hardware/address_mapped.h" #include "hardware/regs/intctrl.h" -#include "hardware/regs/m0plus.h" + +#include "pico/platform/cpu_regs.h" /** \file irq.h * \defgroup hardware_irq hardware_irq * - * \brief Hardware interrupt handling + * \brief Hardware interrupt handling API * * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC). * @@ -62,7 +63,10 @@ * * \section interrupt_nums Interrupt Numbers * - * Interrupts are numbered as follows, a set of defines is available (intctrl.h) with these names to avoid using the numbers directly. + * A set of defines is available (intctrl.h) with these names to avoid using the numbers directly. + * + * \if rp2040_specific + * On RP2040 the interrupt numbers are as follows: * * IRQ | Interrupt Source * ----|----------------- @@ -92,7 +96,66 @@ * 23 | I2C0_IRQ * 24 | I2C1_IRQ * 25 | RTC_IRQ + * \endif * + * \if rp2350_specific + * On RP2350 the interrupt numbers are as follows: + * + * IRQ | Interrupt Source + * ----|----------------- + * 0 | TIMER0_IRQ_0 + * 1 | TIMER0_IRQ_1 + * 2 | TIMER0_IRQ_2 + * 3 | TIMER0_IRQ_3 + * 4 | TIMER1_IRQ_0 + * 5 | TIMER1_IRQ_1 + * 6 | TIMER1_IRQ_2 + * 7 | TIMER1_IRQ_3 + * 8 | PWM_IRQ_WRAP_0 + * 9 | PWM_IRQ_WRAP_1 + * 10 | DMA_IRQ_0 + * 11 | DMA_IRQ_1 + * 12 | DMA_IRQ_2 + * 13 | DMA_IRQ_3 + * 14 | USBCTRL_IRQ + * 15 | PIO0_IRQ_0 + * 16 | PIO0_IRQ_1 + * 17 | PIO1_IRQ_0 + * 18 | PIO1_IRQ_1 + * 19 | PIO2_IRQ_0 + * 20 | PIO2_IRQ_1 + * 21 | IO_IRQ_BANK0 + * 22 | IO_IRQ_BANK0_NS + * 23 | IO_IRQ_QSPI + * 24 | IO_IRQ_QSPI_NS + * 25 | SIO_IRQ_FIFO + * 26 | SIO_IRQ_BELL + * 27 | SIO_IRQ_FIFO_NS + * 28 | SIO_IRQ_BELL_NS + * 29 | SIO_IRQ_MTIMECMP + * 30 | CLOCKS_IRQ + * 31 | SPI0_IRQ + * 32 | SPI1_IRQ + * 33 | UART0_IRQ + * 34 | UART1_IRQ + * 35 | ADC_IRQ_FIFO + * 36 | I2C0_IRQ + * 37 | I2C1_IRQ + * 38 | OTP_IRQ + * 39 | TRNG_IRQ + * 40 | PROC0_IRQ_CTI + * 41 | PROC1_IRQ_CTI + * 42 | PLL_SYS_IRQ + * 43 | PLL_USB_IRQ + * 44 | POWMAN_IRQ_POW + * 45 | POWMAN_IRQ_TIMER + * 46 | SPAREIRQ_IRQ_0 + * 47 | SPAREIRQ_IRQ_1 + * 48 | SPAREIRQ_IRQ_2 + * 49 | SPAREIRQ_IRQ_3 + * 50 | SPAREIRQ_IRQ_4 + * 51 | SPAREIRQ_IRQ_5 + * \endif */ // PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq @@ -111,9 +174,13 @@ #define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff #define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00 -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_IRQ, Enable/disable assertions in the IRQ module, type=bool, default=0, group=hardware_irq -#ifndef PARAM_ASSERTIONS_ENABLED_IRQ -#define PARAM_ASSERTIONS_ENABLED_IRQ 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ +#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0 +#endif #endif #ifdef __cplusplus @@ -128,7 +195,7 @@ extern "C" { typedef void (*irq_handler_t)(void); static inline void check_irq_param(__unused uint num) { - invalid_params_if(IRQ, num >= NUM_IRQS); + invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS); } /*! \brief Set specified interrupt's priority @@ -137,11 +204,19 @@ static inline void check_irq_param(__unused uint num) { * \param num Interrupt number \ref interrupt_nums * \param hardware_priority Priority to set. * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority) though only the - * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * range from 0 (highest priority) to 255 (lowest priority). To make it easier to specify * higher or lower priorities than the default, all IRQ priorities are * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 + * + * \if rp2040_specific + * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. + * \endif + * + * \if rp2350_specific + * Only the top 4 bits are significant on ARM Cortex-M33 or Hazard3 (RISC-V) on RP2350. + * Note that this API uses the same (inverted) ordering as ARM on RISC-V + * \endif */ void irq_set_priority(uint num, uint8_t hardware_priority); @@ -149,12 +224,20 @@ void irq_set_priority(uint num, uint8_t hardware_priority); * \ingroup hardware_irq * * Numerically-lower values indicate a higher priority. Hardware priorities - * range from 0 (highest priority) to 255 (lowest priority) though only the - * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify + * range from 0 (highest priority) to 255 (lowest priority). To make it easier to specify * higher or lower priorities than the default, all IRQ priorities are * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup. * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80 * + * \if rp2040_specific + * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040. + * \endif + * + * \if rp2350_specific + * Only the top 4 bits are significant on ARM Cortex-M33 or Hazard3 (RISC-V) on RP2350. + * Note that this API uses the same (inverted) ordering as ARM on RISC-V + * \endif + * * \param num Interrupt number \ref interrupt_nums * \return the IRQ priority */ @@ -184,6 +267,15 @@ bool irq_is_enabled(uint num); */ void irq_set_mask_enabled(uint32_t mask, bool enabled); +/*! \brief Enable/disable multiple interrupts on the executing core + * \ingroup hardware_irq + * + * \param n the index of the mask to update. n == 0 means 0->31, n == 1 mean 32->63 etc. + * \param mask 32-bit mask with one bits set for the interrupts to enable/disable \ref interrupt_nums + * \param enabled true to enable the interrupts, false to disable them. + */ +void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled); + /*! \brief Set an exclusive interrupt handler for an interrupt on the executing core. * \ingroup hardware_irq * @@ -277,14 +369,21 @@ irq_handler_t irq_get_vtable_handler(uint num); /*! \brief Clear a specific interrupt on the executing core * \ingroup hardware_irq * - * This method is only useful for "software" IRQs that are not connected to hardware (i.e. IRQs 26-31) + * This method is only useful for "software" IRQs that are not connected to hardware (e.g. IRQs 26-31 on RP2040) * as the the NVIC always reflects the current state of the IRQ state of the hardware for hardware IRQs, and clearing * of the IRQ state of the hardware is performed via the hardware's registers instead. * * \param int_num Interrupt number \ref interrupt_nums */ static inline void irq_clear(uint int_num) { +#if PICO_RP2040 *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F))); +#elif defined(__riscv) + // External IRQs are not latched, but we should clear the IRQ force bit here + hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, int_num / 16, 1u << (int_num % 16)); +#else + nvic_hw->icpr[int_num/32] = 1 << (int_num % 32); +#endif } /*! \brief Force an interrupt to be pending on the executing core @@ -301,14 +400,18 @@ void irq_set_pending(uint num); * * \note This is an internal method and user should generally not call it. */ -void irq_init_priorities(void); +void runtime_init_per_core_irq_priorities(void); + +static __force_inline void irq_init_priorities(void) { + runtime_init_per_core_irq_priorities(); +} /*! \brief Claim ownership of a user IRQ on the calling core * \ingroup hardware_irq * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions * dealing with Uer IRQs affect only the calling core * * This method explicitly claims ownership of a user IRQ, so other code can know it is being used. @@ -320,9 +423,9 @@ void user_irq_claim(uint irq_num); /*! \brief Mark a user IRQ as no longer used on the calling core * \ingroup hardware_irq * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions * dealing with Uer IRQs affect only the calling core * * This method explicitly releases ownership of a user IRQ, so other code can know it is free to use. @@ -336,9 +439,9 @@ void user_irq_unclaim(uint irq_num); /*! \brief Claim ownership of a free user IRQ on the calling core * \ingroup hardware_irq * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions * dealing with Uer IRQs affect only the calling core * * This method explicitly claims ownership of an unused user IRQ if there is one, so other code can know it is being used. @@ -352,9 +455,9 @@ int user_irq_claim_unused(bool required); *! \brief Check if a user IRQ is in use on the calling core * \ingroup hardware_irq * - * User IRQs are numbered 26-31 and are not connected to any hardware, but can be triggered by \ref irq_set_pending. + * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending. * - * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therfore all functions + * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions * dealing with Uer IRQs affect only the calling core * * \param irq_num the irq irq_num @@ -365,6 +468,26 @@ int user_irq_claim_unused(bool required); */ bool user_irq_is_claimed(uint irq_num); +void __unhandled_user_irq(void); + +#ifdef __riscv +enum riscv_vector_num { + RISCV_VEC_MACHINE_EXCEPTION = 0, + RISCV_VEC_MACHINE_SOFTWARE_IRQ = 3, + RISCV_VEC_MACHINE_TIMER_IRQ = 7, + RISCV_VEC_MACHINE_EXTERNAL_IRQ = 11, +}; + +irq_handler_t irq_set_riscv_vector_handler(enum riscv_vector_num index, irq_handler_t handler); +#endif + +#if PICO_SECURE +static inline void irq_assign_to_ns(uint irq_num, bool ns) { + check_irq_param(irq_num); + if (ns) nvic_hw->itns[irq_num >> 5] |= 1u << (irq_num & 0x1fu); + else nvic_hw->itns[irq_num >> 5] &= ~(1u << (irq_num & 0x1fu)); +} +#endif #ifdef __cplusplus } #endif diff --git a/src/rp2_common/hardware_irq/irq.c b/src/rp2_common/hardware_irq/irq.c index 6347fb5e2..916338858 100644 --- a/src/rp2_common/hardware_irq/irq.c +++ b/src/rp2_common/hardware_irq/irq.c @@ -5,15 +5,15 @@ */ #include "hardware/irq.h" -#include "hardware/regs/m0plus.h" -#include "hardware/platform_defs.h" -#include "hardware/structs/scb.h" -#include "hardware/claim.h" +#include "pico/runtime_init.h" +#include "hardware/claim.h" #include "pico/mutex.h" #include "pico/assert.h" -extern void __unhandled_user_irq(void); +#if defined(PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES) && !PICO_RUNTIME_SKIP_INIT_PER_CORE_IRQ_PRIORITIES +PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_irq_priorities, PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES); +#endif #if PICO_VTABLE_PER_CORE static uint8_t user_irq_claimed[NUM_CORES]; @@ -28,15 +28,27 @@ static inline uint8_t *user_irq_claimed_ptr(void) { #endif static inline irq_handler_t *get_vtable(void) { +#ifdef __riscv + return (irq_handler_t *) (riscv_read_csr(RVCSR_MTVEC_OFFSET) & ~0x3u); +#else return (irq_handler_t *) scb_hw->vtor; +#endif } static inline void *add_thumb_bit(void *addr) { +#ifdef __riscv + return addr; +#else return (void *) (((uintptr_t) addr) | 0x1); +#endif } static inline void *remove_thumb_bit(void *addr) { +#ifdef __riscv + return addr; +#else return (void *) (((uintptr_t) addr) & (uint)~0x1); +#endif } static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) { @@ -48,28 +60,73 @@ static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint void irq_set_enabled(uint num, bool enabled) { check_irq_param(num); - irq_set_mask_enabled(1u << num, enabled); + // really should update irq_set_mask_enabled? + irq_set_mask_n_enabled(num / 32, 1u << (num % 32), enabled); } bool irq_is_enabled(uint num) { check_irq_param(num); +#if PICO_RP2040 return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))); +#elif defined(__riscv) + return 0 != (hazard3_irqarray_read(RVCSR_MEIEA_OFFSET, num / 16) & (1u << (num % 16))); +#else + return 0 != (nvic_hw->iser[num/32] & (1 << num % 32)); +#endif } -void irq_set_mask_enabled(uint32_t mask, bool enabled) { +static inline void irq_set_mask_n_enabled_internal(uint n, uint32_t mask, bool enabled) { + invalid_params_if(HARDWARE_IRQ, n * 32u >= ((NUM_IRQS + 31u) & ~31u)); +#if defined(__riscv) if (enabled) { - // Clear pending before enable - // (if IRQ is actually asserted, it will immediately re-pend) - *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = mask; - *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = mask; + hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n, mask & 0xffffu); + hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n + 1, mask >> 16); + hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); + hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); } else { - *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICER_OFFSET)) = mask; + hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); + hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); } +#elif PICO_RP2040 + ((void)n); + if (enabled) { + nvic_hw->icpr = mask; + nvic_hw->iser = mask; + } else { + nvic_hw->icer = mask; + } +#else + // >32 IRQs (well this works for the bottom 32 which is all that is passed in + if (enabled) { + nvic_hw->icpr[n] = mask; + nvic_hw->iser[n] = mask; + } else { + nvic_hw->icer[n] = mask; + } +#endif +} + +void irq_set_mask_enabled(uint32_t mask, bool enabled) { + irq_set_mask_n_enabled_internal(0, mask, enabled); +} + +void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled) { + irq_set_mask_n_enabled_internal(n, mask, enabled); } void irq_set_pending(uint num) { check_irq_param(num); +#ifdef __riscv + // Interrupt force is subsequently cleared by any read of meinext that + // indicates the forced IRQ (can also be cleared manually) + hazard3_irqarray_set(RVCSR_MEIFA_OFFSET, num / 16, 1u << (num % 16)); +#else +#if PICO_RP2040 *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num; +#else + nvic_hw->ispr[num/32] = 1 << (num % 32); +#endif +#endif } #if !PICO_DISABLE_SHARED_IRQ_HANDLERS @@ -80,24 +137,58 @@ static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS extern void irq_handler_chain_first_slot(void); extern void irq_handler_chain_remove_tail(void); +// On Arm: +// +// - The first slot begins with a tail call to irq_handler_chain_first_slot, passing a pointer to +// the slot in r1; this pushes the initial link register to the stack, invokes the slot's handler +// and then returns into the latter half of the slot +// +// - Non-first slots begin with a call of the slot's handler +// +// - Non-last slots end with a tail into the next slot in the chain +// +// - The last slot ends with a pop of the return address pushed by irq_handler_chain_first_slot +// +// On RISC-V: +// +// - The first slot begins with jal t0, irq_handler_first_chain_slot followed by a 32-bit pointer to +// the handler; this pushes the ultimate return address to the stack, invokes the slot's handler +// and then returns into the latter half of the slot +// +// - Non-first slots begin with an lui; jalr sequence to call the handler +// +// - Non-last slots end with a tail into the next slot in the chain +// +// - The last slot ends with a pop of the return address pushed by irq_handler_chain_first_slot +// +// This means the layout is different between Arm and RISC-V (though total size is the same): Arm is +// 6 bytes of code, 2 bytes of link and 4 bytes of pointer. RISC-V is 10 bytes of code and 2 bytes +// of link. + extern struct irq_handler_chain_slot { - // first 3 half words are executable code (raw vtable handler points to one slot, and inst3 will jump to next - // in chain (or end of chain handler) +#ifndef __riscv uint16_t inst1; uint16_t inst2; +#else + uint32_t inst1; + uint32_t inst2; +#endif uint16_t inst3; union { - // when a handler is removed while executing, it needs an extra instruction, which overwrites - // the link and the priority; this is ok because no one else is modifying the chain, as - // the chain is effectively core local, and the user code which might still need this link - // disable the IRQ in question before updating, which means we aren't executing! + // On Arm, when a handler is removed while executing, it needs a 32-bit instruction at + // inst3, which overwrites the link and the priority; this is ok because no one else is + // modifying the chain, as the chain is effectively core-local, and the user code which + // might still need this link disables the IRQ in question before updating, which means we + // aren't executing! struct { int8_t link; uint8_t priority; }; uint16_t inst4; }; +#ifndef __riscv irq_handler_t handler; +#endif } irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS]; static int8_t irq_handler_chain_free_slot_head; @@ -112,7 +203,7 @@ bool irq_has_shared_handler(uint irq_num) { return handler && is_shared_irq_raw_handler(handler); } -#else +#else // PICO_DISABLE_SHARED_IRQ_HANDLERS #define is_shared_irq_raw_handler(h) false bool irq_has_shared_handler(uint irq_num) { return false; @@ -122,7 +213,7 @@ bool irq_has_shared_handler(uint irq_num) { irq_handler_t irq_get_vtable_handler(uint num) { check_irq_param(num); - return get_vtable()[16 + num]; + return get_vtable()[VTABLE_FIRST_IRQ + num]; } void irq_set_exclusive_handler(uint num, irq_handler_t handler) { @@ -156,7 +247,10 @@ irq_handler_t irq_get_exclusive_handler(uint num) { #if !PICO_DISABLE_SHARED_IRQ_HANDLERS -static uint16_t make_branch(uint16_t *from, void *to) { + +#ifndef __riscv + +static uint16_t make_j_16(uint16_t *from, void *to) { uint32_t ui_from = (uint32_t)from; uint32_t ui_to = (uint32_t)to; int32_t delta = (int32_t)(ui_to - ui_from - 4); @@ -164,7 +258,7 @@ static uint16_t make_branch(uint16_t *from, void *to) { return (uint16_t)(0xe000 | ((delta >> 1) & 0x7ff)); } -static void insert_branch_and_link(uint16_t *from, void *to) { +static void insert_bl_32(uint16_t *from, void *to) { uint32_t ui_from = (uint32_t)from; uint32_t ui_to = (uint32_t)to; uint32_t delta = (ui_to - ui_from - 4) / 2; @@ -173,16 +267,65 @@ static void insert_branch_and_link(uint16_t *from, void *to) { from[1] = (uint16_t)(0xf800 | (delta & 0x7ffu)); } -static inline void *resolve_branch(uint16_t *inst) { +static inline void *resolve_j_16(uint16_t *inst) { assert(0x1c == (*inst)>>11u); int32_t i_addr = (*inst) << 21u; i_addr /= (int32_t)(1u<<21u); return inst + 2 + i_addr; } +#else + +static uint16_t make_jal_16(uint16_t *from, void *to) { + uint32_t ui_from = (uint32_t)from; + uint32_t ui_to = (uint32_t)to; + int32_t delta = (int32_t)(ui_to - ui_from); + assert(delta >= -2048 && delta <= 2046 && !(delta & 1)); + return 0x2001u | riscv_encode_imm_cj((uint32_t)delta); +} + +static uint16_t make_j_16(uint16_t *from, void *to) { + return 0x8000u | make_jal_16(from, to); +} + +static inline uint32_t make_call_inst1(void *to) { + // lui ra, %hi(to) + return 0x000000b7u | riscv_encode_imm_u_hi((uintptr_t)to); +} + +static inline uint32_t make_call_inst2(void *to) { + // jalr ra, %lo(to)(ra) + return 0x000080e7u | riscv_encode_imm_i((uintptr_t)to); +} + +static inline uint32_t make_jal_t0_32(uint32_t *from, void *to) { + // jal t0, to + return 0x000002efu | riscv_encode_imm_j((uintptr_t)to - (uintptr_t)from); +} + +static void *resolve_j_16(uint16_t *inst) { + uint32_t inst32 = (uint32_t)*inst; + uint32_t udiff = + ((inst32 & 0x0038) >> 2) + + ((inst32 & 0x0800) >> 7) + + ((inst32 & 0x0004) << 3) + + ((inst32 & 0x0080) >> 1) + + ((inst32 & 0x0040) << 1) + + ((inst32 & 0x0600) >> 1) + + ((inst32 & 0x0100) << 2) - + ((inst32 & 0x2000) >> 2); + return (void *)((uint32_t)inst + udiff); +} + +#endif + // GCC produces horrible code for subtraction of pointers here, and it was bugging me static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) { static_assert(sizeof(struct irq_handler_chain_slot) == 12, ""); +#ifdef __riscv + // todo I think RISC-V also deserves a fancy pointer diff implementation + return (int8_t)(to - from); +#else int32_t result = 0xaaaa; // return (to - from); // note this implementation has limited range, but is fine for plenty more than -128->127 result @@ -193,11 +336,18 @@ static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_han "lsrs %0, %0, #20\n" : "+l" (result), "+l" (to) : "l" (from) - : + : "cc" ); return (int8_t)result; +#endif } +#ifndef __riscv +static const uint16_t inst16_return_from_last_slot = 0xbd01; // pop {r0, pc} +#else +static const uint16_t inst16_return_from_last_slot = 0xbe42; // cm.popret {ra}, 16 +#endif + static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) { return slot_diff(slot, irq_handler_chain_slots); } @@ -216,22 +366,27 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_handler_chain_free_slot_head]; int8_t slot_index = irq_handler_chain_free_slot_head; irq_handler_chain_free_slot_head = slot->link; - irq_handler_t vtable_handler = get_vtable()[16 + num]; + irq_handler_t vtable_handler = get_vtable()[VTABLE_FIRST_IRQ + num]; if (!is_shared_irq_raw_handler(vtable_handler)) { // start new chain hard_assert(vtable_handler == __unhandled_user_irq); struct irq_handler_chain_slot slot_data = { +#ifndef __riscv .inst1 = 0xa100, // add r1, pc, #0 - .inst2 = make_branch(&slot->inst2, (void *) irq_handler_chain_first_slot), // b irq_handler_chain_first_slot - .inst3 = 0xbd01, // pop {r0, pc} + .inst2 = make_j_16(&slot->inst2, (void *) irq_handler_chain_first_slot), // b irq_handler_chain_first_slot + .handler = handler, +#else + .inst1 = make_jal_t0_32(&slot->inst1, irq_handler_chain_first_slot), // jal t0, irq_handler_chain_first_slot + .inst2 = (uint32_t)handler, // (t0 points to handler) +#endif + .inst3 = inst16_return_from_last_slot, .link = -1, - .priority = order_priority, - .handler = handler + .priority = order_priority }; *slot = slot_data; vtable_handler = (irq_handler_t)add_thumb_bit(slot); } else { - assert(!((((uintptr_t)vtable_handler) - ((uintptr_t)irq_handler_chain_slots) - 1)%sizeof(struct irq_handler_chain_slot))); + assert(!((((uintptr_t)remove_thumb_bit(vtable_handler)) - ((uintptr_t)irq_handler_chain_slots)) % sizeof(struct irq_handler_chain_slot))); struct irq_handler_chain_slot *prev_slot = NULL; struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit((void *) vtable_handler); struct irq_handler_chain_slot *cur_slot = existing_vtable_slot; @@ -243,45 +398,80 @@ void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_prior if (prev_slot) { // insert into chain struct irq_handler_chain_slot slot_data = { - .inst1 = 0x4801, // ldr r0, [pc, #4] - .inst2 = 0x4780, // blx r0 +#ifndef __riscv + .inst1 = 0x4801, // ldr r0, [pc, #4] + .inst2 = 0x4780, // blx r0 + .handler = handler, +#else + .inst1 = make_call_inst1(handler), // lui ra, %hi(handler) + .inst2 = make_call_inst2(handler), // jalr ra, %lo(handler)(ra) +#endif .inst3 = prev_slot->link >= 0 ? - make_branch(&slot->inst3, resolve_branch(&prev_slot->inst3)) : // b next_slot - 0xbd01, // pop {r0, pc} + make_j_16(&slot->inst3, resolve_j_16(&prev_slot->inst3)) : // b next_slot + inst16_return_from_last_slot, .link = prev_slot->link, - .priority = order_priority, - .handler = handler + .priority = order_priority }; // update code and data links - prev_slot->inst3 = make_branch(&prev_slot->inst3, slot), + prev_slot->inst3 = make_j_16(&prev_slot->inst3, slot), prev_slot->link = slot_index; *slot = slot_data; } else { // update with new chain head struct irq_handler_chain_slot slot_data = { - .inst1 = 0xa100, // add r1, pc, #0 - .inst2 = make_branch(&slot->inst2, (void *) irq_handler_chain_first_slot), // b irq_handler_chain_first_slot - .inst3 = make_branch(&slot->inst3, existing_vtable_slot), // b existing_slot +#ifndef __riscv + .inst1 = 0xa100, // add r1, pc, #0 + .inst2 = make_j_16(&slot->inst2, (void *) irq_handler_chain_first_slot), // b irq_handler_chain_first_slot + .handler = handler, +#else + .inst1 = make_jal_t0_32(&slot->inst1, irq_handler_chain_first_slot), // jal t0, irq_handler_chain_first_slot + .inst2 = (uint32_t)handler, // (t0 points to handler) +#endif + .inst3 = make_j_16(&slot->inst3, existing_vtable_slot), // b existing_slot .link = get_slot_index(existing_vtable_slot), .priority = order_priority, - .handler = handler }; *slot = slot_data; // fixup previous head slot +#ifndef __riscv existing_vtable_slot->inst1 = 0x4801; // ldr r0, [pc, #4] existing_vtable_slot->inst2 = 0x4780; // blx r0 +#else + // todo lock-freeness? + void *handler_of_existing_head = (void*)existing_vtable_slot->inst2; + existing_vtable_slot->inst1 = make_call_inst1(handler_of_existing_head); + existing_vtable_slot->inst2 = make_call_inst2(handler_of_existing_head); +#endif vtable_handler = (irq_handler_t)add_thumb_bit(slot); } } set_raw_irq_handler_and_unlock(num, vtable_handler, save); +#endif // !PICO_NO_RAM_VECTOR_TABLE && !PICO_DISABLE_SHARED_IRQ_HANDLERS +} + +#if !PICO_DISABLE_SHARED_IRQ_HANDLERS +static inline irq_handler_t handler_from_slot(struct irq_handler_chain_slot *slot) { +#ifndef __riscv + return slot->handler; +#else + if (slot->inst1 & 0x8u) { + // jal t0, irq_handler_chain_first_slot; .word handler + return (irq_handler_t)slot->inst2; + } else { + // lui ra, %hi(handler); jalr ra, %lo(handler)(ra) + return (irq_handler_t)( + ((slot->inst1 >> 12) << 12) + (uint32_t)((int32_t)slot->inst2 >> 20) + ); + } #endif } +#endif void irq_remove_handler(uint num, irq_handler_t handler) { #if !PICO_NO_RAM_VECTOR_TABLE spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ); uint32_t save = spin_lock_blocking(lock); - irq_handler_t vtable_handler = get_vtable()[16 + num]; + irq_handler_t vtable_handler = get_vtable()[VTABLE_FIRST_IRQ + num]; if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) { #if !PICO_DISABLE_SHARED_IRQ_HANDLERS if (is_shared_irq_raw_handler(vtable_handler)) { @@ -311,12 +501,12 @@ void irq_remove_handler(uint num, irq_handler_t handler) { struct irq_handler_chain_slot *prev_slot = NULL; struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit((void *) vtable_handler); struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot; - while (to_free_slot->handler != handler) { + while (handler_from_slot(to_free_slot) != handler) { prev_slot = to_free_slot; if (to_free_slot->link < 0) break; to_free_slot = &irq_handler_chain_slots[to_free_slot->link]; } - if (to_free_slot->handler == handler) { + if (handler_from_slot(to_free_slot) == handler) { int8_t next_slot_index = to_free_slot->link; if (next_slot_index >= 0) { // There is another slot in the chain, so copy that over us, so that our inst3 points at something valid @@ -324,12 +514,22 @@ void irq_remove_handler(uint num, irq_handler_t handler) { // however in that case its IRQ cause should immediately cause re-entry of the IRQ and the only side // effect will be that there was potentially brief out of priority order execution of the handlers struct irq_handler_chain_slot *next_slot = &irq_handler_chain_slots[next_slot_index]; +#ifndef __riscv to_free_slot->handler = next_slot->handler; +#else + irq_handler_t handler_of_next_slot = handler_from_slot(next_slot); + if (to_free_slot == existing_vtable_slot) { + to_free_slot->inst2 = (uint32_t)handler_of_next_slot; + } else { + to_free_slot->inst1 = make_call_inst1(handler_of_next_slot); + to_free_slot->inst2 = make_call_inst2(handler_of_next_slot); + } +#endif to_free_slot->priority = next_slot->priority; to_free_slot->link = next_slot->link; to_free_slot->inst3 = next_slot->link >= 0 ? - make_branch(&to_free_slot->inst3, resolve_branch(&next_slot->inst3)) : // b mext_>slot->next_slot - 0xbd01; // pop {r0, pc} + make_j_16(&to_free_slot->inst3, resolve_j_16(&next_slot->inst3)) : // b next_>slot->next_slot + inst16_return_from_last_slot, // add old next slot back to free list next_slot->link = irq_handler_chain_free_slot_head; @@ -341,7 +541,7 @@ void irq_remove_handler(uint num, irq_handler_t handler) { if (prev_slot) { // chain is not empty prev_slot->link = -1; - prev_slot->inst3 = 0xbd01; // pop {r0, pc} + prev_slot->inst3 = inst16_return_from_last_slot; } else { // chain is not empty vtable_handler = __unhandled_user_irq; @@ -352,9 +552,13 @@ void irq_remove_handler(uint num, irq_handler_t handler) { } else { // since we are the last slot we know that our inst3 hasn't executed yet, so we change // it to bl to irq_handler_chain_remove_tail which will remove the slot. +#ifndef __riscv // NOTE THAT THIS TRASHES PRIORITY AND LINK SINCE THIS IS A 4 BYTE INSTRUCTION // BUT THEY ARE NOT NEEDED NOW - insert_branch_and_link(&to_free_slot->inst3, (void *) irq_handler_chain_remove_tail); + insert_bl_32(&to_free_slot->inst3, (void *) irq_handler_chain_remove_tail); +#else + to_free_slot->inst3 = make_jal_16(&to_free_slot->inst3, (void*) irq_handler_chain_remove_tail); +#endif } } } else { @@ -374,20 +578,40 @@ void irq_remove_handler(uint num, irq_handler_t handler) { #endif } +#ifndef __riscv +static io_rw_32 *nvic_ipr0(void) { + return (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(NVIC_IPR0_OFFSET)); +} +#endif + void irq_set_priority(uint num, uint8_t hardware_priority) { check_irq_param(num); - +#ifdef __riscv + // SDK priorities are upside down due to Cortex-M influence + hardware_priority = (uint8_t)((hardware_priority >> 4) ^ 0xf); + // There is no atomic field write operation, so first drop the IRQ to its + // lowest priority (safe even if it is in a preemption frame below us) and + // then use a set to raise it to the target priority. + hazard3_irqarray_clear(RVCSR_MEIPRA_OFFSET, num / 4, 0xfu << (4 * (num % 4))); + hazard3_irqarray_set(RVCSR_MEIPRA_OFFSET, num / 4, hardware_priority << (4 * (num % 4))); +#else + io_rw_32 *p = nvic_ipr0() + (num >> 2); // note that only 32 bit writes are supported - io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u)); *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u))); +#endif } uint irq_get_priority(uint num) { check_irq_param(num); - +#ifdef __riscv + uint16_t priority_row = (uint16_t) hazard3_irqarray_read(RVCSR_MEIPRA_OFFSET, num / 4u); + uint8_t priority_4bit = (priority_row >> (4 * (num % 4))) & 0xfu; + return ((priority_4bit ^ 0xfu) << 4u); +#else // note that only 32 bit reads are supported - io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u)); + io_rw_32 *p = nvic_ipr0() + (num >> 2); return (uint8_t)(*p >> (8 * (num & 3u))); +#endif } #if !PICO_DISABLE_SHARED_IRQ_HANDLERS @@ -410,7 +634,7 @@ void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) { for(uint i=0;i= NUM_IRQS); + invalid_params_if(HARDWARE_IRQ, irq_num < FIRST_USER_IRQ || irq_num >= NUM_IRQS); // we count backwards from the last, to match the existing hard coded uses of user IRQs in the SDK which were previously using 31 static_assert(NUM_IRQS - FIRST_USER_IRQ <= 8, ""); // we only use a single byte's worth of claim bits today. return NUM_IRQS - irq_num - 1u; @@ -460,3 +690,20 @@ bool user_irq_is_claimed(uint irq_num) { return hw_is_claimed(user_irq_claimed_ptr(), get_user_irq_claim_index(irq_num)); } +#ifdef __riscv +static uint32_t encode_j_instruction(uintptr_t from, uintptr_t to) { + intptr_t delta = (intptr_t) (to - from); + invalid_params_if(HARDWARE_IRQ, delta & 1); + valid_params_if(HARDWARE_IRQ, ((delta >> 21) == 0 || (delta >> 21) == -1)); // range check +- 1 MiB + return 0x6fu | riscv_encode_imm_j((uint32_t)delta); +} + +irq_handler_t irq_set_riscv_vector_handler(enum riscv_vector_num index, irq_handler_t handler) { + invalid_params_if(HARDWARE_IRQ, index > RISCV_VEC_MACHINE_EXTERNAL_IRQ); + irq_handler_t *vtable = get_vtable(); + valid_params_if(HARDWARE_IRQ, ((uintptr_t)vtable & 0x3) == 0x1); // check we are in vector mode + irq_handler_t old = vtable[index]; + vtable[index] = (irq_handler_t)encode_j_instruction((uintptr_t)&vtable[index], (uintptr_t)handler); + return old; +} +#endif diff --git a/src/rp2_common/hardware_irq/irq_handler_chain.S b/src/rp2_common/hardware_irq/irq_handler_chain.S index cd15ce77d..fd4141a5b 100644 --- a/src/rp2_common/hardware_irq/irq_handler_chain.S +++ b/src/rp2_common/hardware_irq/irq_handler_chain.S @@ -23,7 +23,7 @@ pico_default_asm_setup // // These Slots make up the code and structure of the handler chains; the only external information are the VTABLE entries // (obviously one set per core) and a free list head. Each individual handler chain starts with the VTABLE entry I -// pointing at the address of slot S (with thumb bit set). Thus each slot which is part of a chain is executble. +// pointing at the address of slot S (with thumb bit set). Thus each slot which is part of a chain is executable. // // The execution jumps (via branch instruction) from one slot to the other, then jumps to the end of chain handler. // The entirety of the state needed to traverse the chain is contained within the slots of the chain, which is why @@ -34,10 +34,17 @@ irq_handler_chain_slots: .set next_slot_number, 1 .rept PICO_MAX_SHARED_IRQ_HANDLERS // a slot is executable and is always 3 instructions long. - .hword 0 // inst1 (either: ldr r0, [pc, #4] or for the FIRST slot : add r1, pc, #0 ) - .hword 0 // inst2 ( blx r0 b irq_handler_chain_first_slot ) +#ifndef __riscv + .hword 0 // inst1 (either: ldr r0, [pc, #4] or for the FIRST slot: add r1, pc, #0 ) + .hword 0 // inst2 ( blx r0 b irq_handler_chain_first_slot ) - .hword 0 // inst3 (either: b next_slot or for the LAST pop {pc} ) + .hword 0 // inst3 (either: b next_slot or for the LAST pop {pc} ) +#else + .word 0 // inst1 (either: lui ra, %hi(handler) or for the FIRST slot: jal t0, irq_handler_chain_first_slot) + .word 0 // inst2 (either: jalr ra. %lo(handler)(ra) .word handler ) + + .hword 0 // inst3 (either: j next_slot or for the LAST slot: cm.popret {ra}, 16 ) +#endif // next is a single byte index of next slot in chain (or -1 to end) .if next_slot_number == PICO_MAX_SHARED_IRQ_HANDLERS @@ -48,12 +55,15 @@ irq_handler_chain_slots: // next is the 8 bit unsigned priority .byte 0x00 1: - // and finally the handler function pointer - .word 0x00000000 + // and finally the handler function pointer for Arm: +#ifndef __riscv + .word 0x0000000 +#endif .set next_slot_number, next_slot_number + 1 .endr irq_handler_chain_first_slot: +#ifndef __riscv push {r0, lr} // Save EXC_RETURN token, so `pop {r0, pc}` will return from interrupt // Note that r0 does not NEED to be saved, however we must maintain // an 8 byte stack alignment, and this is the cheapest way to do so @@ -61,13 +71,24 @@ irq_handler_chain_first_slot: adds r1, #1 // r1 points to `inst3` field of slot struct. Set Thumb bit on r1, mov lr, r1 // and copy to lr, so `inst3` is executed on return from handler bx r0 // Enter handler +#else + .insn 0xb842 // cm.push {ra}, -16: Save ultimate return address + add ra, t0, 4 // Set up function call to return to offset 8 of the slot + lw t0, (t0) // Load pointer from offset 4 of the slot + jr t0 // Call it, with our calculated return address +#endif irq_handler_chain_remove_tail: +#ifndef __riscv mov r0, lr // Get start of struct. This function was called by a bl at offset +4, subs r0, #9 // so lr points to offset +8. Note also lr has its Thumb bit set! ldr r1, =irq_add_tail_to_free_list blx r1 pop {r0, pc} // Top of stack is EXC_RETURN - +#else + add a0, ra, -10 // Expect to be called with a 16-bit jal, at 8-byte offset in the slot. + call irq_add_tail_to_free_list + .insn 0xbe42 // cm.popret {ra}, 16 +#endif #endif diff --git a/src/rp2_common/hardware_pio/BUILD.bazel b/src/rp2_common/hardware_pio/BUILD.bazel index 518e87505..74fc0668c 100644 --- a/src/rp2_common/hardware_pio/BUILD.bazel +++ b/src/rp2_common/hardware_pio/BUILD.bazel @@ -12,11 +12,11 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", + "//src/common/hardware_claim", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_base", - "//src/rp2_common/hardware_claim", "//src/rp2_common/hardware_gpio", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h index f25d036cc..7eda36da6 100644 --- a/src/rp2_common/hardware_pio/include/hardware/pio.h +++ b/src/rp2_common/hardware_pio/include/hardware/pio.h @@ -14,18 +14,38 @@ #include "hardware/regs/dreq.h" #include "hardware/pio_instructions.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO, Enable/disable assertions in the PIO module, type=bool, default=0, group=hardware_pio -#ifndef PARAM_ASSERTIONS_ENABLED_PIO -#define PARAM_ASSERTIONS_ENABLED_PIO 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO, Enable/disable assertions in the hardware_pio module, type=bool, default=0, group=hardware_pio +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO +#ifdef PARAM_ASSERTIONS_ENABLED_PIO // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO PARAM_ASSERTIONS_ENABLED_PIO +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO 0 +#endif #endif +// PICO_CONFIG: PICO_PIO_VERSION, The PIO hardware version, type=int, default=0 on RP2040 and 1 on RP2350, group=hardware_pio +#ifndef PICO_PIO_VERSION +#if PIO_GPIOBASE_BITS +#define PICO_PIO_VERSION 1 +#else +#define PICO_PIO_VERSION 0 +#endif +#endif /** \file hardware/pio.h * \defgroup hardware_pio hardware_pio * * \brief Programmable I/O (PIO) API * * A programmable input/output block (PIO) is a versatile hardware interface which - * can support a number of different IO standards. There are two PIO blocks in the RP2040. + * can support a number of different IO standards. + * + * \if rp2040_specific + * There are two PIO blocks in the RP2040. + * \endif + * + * \if rp2350_specific + * There are three PIO blocks in the RP2350 + * \endif * * Each PIO is programmable in the same sense as a processor: the four state machines independently * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general @@ -40,7 +60,9 @@ * * DMA interface, sustained throughput up to 1 word per clock from system DMA * * IRQ flag set/clear/status * - * Full details of the PIO can be found in the RP2040 datasheet. + * Full details of the PIO can be found in the appropriate RP-series datasheet. Note that there are + * additional features in the RP2350 PIO implementation that mean care should be taken when writing PIO + * code that needs to run on both the RP2040 and the RP2350. */ #ifdef __cplusplus @@ -53,9 +75,14 @@ static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + * \ingroup hardware_pio */ enum pio_fifo_join { - PIO_FIFO_JOIN_NONE = 0, - PIO_FIFO_JOIN_TX = 1, - PIO_FIFO_JOIN_RX = 2, + PIO_FIFO_JOIN_NONE = 0, ///< TX FIFO length=4 is used for transmit, RX FIFO length=4 is used for receive + PIO_FIFO_JOIN_TX = 1, ///< TX FIFO length=8 is used for transmit, RX FIFO is disabled + PIO_FIFO_JOIN_RX = 2, ///< RX FIFO length=8 is used for receive, TX FIFO is disabled +#if PICO_PIO_VERSION > 0 + PIO_FIFO_JOIN_TXGET = 4, ///< TX FIFO length=4 is used for transmit, RX FIFO is disabled; space is used for "get" instructions or processor writes + PIO_FIFO_JOIN_TXPUT = 8, ///< TX FIFO length=4 is used for transmit, RX FIFO is disabled; space is used for "put" instructions or processor reads + PIO_FIFO_JOIN_PUTGET = 12, ///< TX FIFO length=4 is used for transmit, RX FIFO is disabled; space is used for "put"/"get" instructions with no processor access +#endif }; /** \brief MOV status types @@ -63,7 +90,10 @@ enum pio_fifo_join { */ enum pio_mov_status_type { STATUS_TX_LESSTHAN = 0, - STATUS_RX_LESSTHAN = 1 + STATUS_RX_LESSTHAN = 1, +#if PICO_PIO_VERSION > 0 + STATUS_IRQ_SET = 2 +#endif }; typedef pio_hw_t *PIO; @@ -84,6 +114,91 @@ typedef pio_hw_t *PIO; */ #define pio1 pio1_hw +#if NUM_PIOS > 2 +/** Identifier for the second (PIO 1) hardware PIO instance (for use in PIO functions). + * + * e.g. pio_gpio_init(pio1, 5) + * + * \ingroup hardware_pio + */ +#define pio2 pio2_hw +#endif + +#if PICO_PIO_VERSION > 0 +#ifndef PICO_PIO_USE_GPIO_BASE +// PICO_CONFIG: PICO_PIO_USE_GPIO_BASE, Enable code for handling more than 32 PIO pins, type=bool, default=true when supported and when the device has more than 32 pins, group=hardware_pio +#define PICO_PIO_USE_GPIO_BASE ((NUM_BANK0_GPIOS) > 32) +#endif +#endif + +/** + * \def PIO_NUM(pio) + * \ingroup hardware_pio + * \hideinitializer + * \brief Returns the PIO number for a PIO instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PIO_NUM +static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch"); +#define PIO_NUM(pio) (((uintptr_t)(pio) - PIO0_BASE) >> 20) +#endif + +/** + * \def PIO_INSTANCE(pio_num) + * \ingroup hardware_pio + * \hideinitializer + * \brief Returns the PIO instance with the given PIO number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PIO_INSTANCE +static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch"); +#define PIO_INSTANCE(instance) ((pio_hw_t *)(PIO0_BASE + (instance) * (1u << 20))) +#endif + +/** + * \def PIO_FUNCSEL_NUM(pio, gpio) + * \ingroup hardware_pio + * \hideinitializer + * \brief Returns \ref gpio_function_t needed to select the PIO function for the given PIO instance on the given GPIO + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PIO_FUNCSEL_NUM +#define PIO_FUNCSEL_NUM(pio, gpio) ((gpio_function_t) (GPIO_FUNC_PIO0 + PIO_NUM(pio))) +#endif + +/** + * \def PIO_DREQ_NUM(pio, sm, is_tx) + * \ingroup hardware_pio + * \hideinitializer + * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from a given state machine's FIFOs on this PIO instance. + * If is_tx is true, then it is for transfers to the PIO state machine TX FIFO else for transfers from the PIO state machine RX FIFO. + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PIO_DREQ_NUM +static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, ""); +static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, ""); +static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, ""); +static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, ""); +static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, ""); +#define PIO_DREQ_NUM(pio, sm, is_tx) ((sm) + (((is_tx) ? 0 : NUM_PIO_STATE_MACHINES) + PIO_NUM(pio) * (DREQ_PIO1_TX0 - DREQ_PIO0_TX0))) +#endif + +/** + * \def PIO_IRQ_NUM(pio) + * \ingroup hardware_pio + * \hideinitializer + * \brief Returns the \ref irq_num_t for processor interrupts from the given PIO instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PIO_IRQ_NUM +#define PIO_IRQ_NUM(pio, irqn) (PIO0_IRQ_0 + NUM_PIO_IRQS * PIO_NUM(pio) + (irqn)) +#endif + /** \brief PIO state machine configuration * \defgroup sm_config sm_config * \ingroup hardware_pio @@ -104,81 +219,212 @@ typedef struct { uint32_t execctrl; uint32_t shiftctrl; uint32_t pinctrl; +#if PICO_PIO_USE_GPIO_BASE +#define PINHI_ALL_PINCTRL_LSBS ((1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \ + (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) +static_assert( 0 == (0xff000000u & (PINHI_ALL_PINCTRL_LSBS * 0x1f)), ""); +// note we put the jmp_ctrl pin starting at bit 24 +#define PINHI_ALL_PIN_LSBS ((1u << 24) | (1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \ + (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) + // each 5-bit field which would usually be used for the pin_base in pin_ctrl, is used for: + // 0b11111 - corresponding field not specified + // 0b00000 - pin is in range 0-15 + // 0b00001 - pin is in range 16-31 + // 0b00010 - pin is in range 32-47 + uint32_t pinhi; +#endif } pio_sm_config; static inline void check_sm_param(__unused uint sm) { - valid_params_if(PIO, sm < NUM_PIO_STATE_MACHINES); + valid_params_if(HARDWARE_PIO, sm < NUM_PIO_STATE_MACHINES); } static inline void check_sm_mask(__unused uint mask) { - valid_params_if(PIO, mask < (1u << NUM_PIO_STATE_MACHINES)); + valid_params_if(HARDWARE_PIO, mask < (1u << NUM_PIO_STATE_MACHINES)); } - static inline void check_pio_param(__unused PIO pio) { - valid_params_if(PIO, pio == pio0 || pio == pio1); +#if NUM_PIOS == 2 + valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1); +#elif NUM_PIOS == 3 + valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1 || pio == pio2); +#endif +} + +static inline void check_pio_pin_param(__unused uint pin) { +#if !PICO_PIO_USE_GPIO_BASE + invalid_params_if(HARDWARE_PIO, pin >= 32); +#else + // pin base allows us to move up 16 pins at a time + invalid_params_if(HARDWARE_PIO, pin >= ((NUM_BANK0_GPIOS + 15u)&~15u)); +#endif +} + +/*! \brief Set the base of the 'out' pins in a state machine configuration + * \ingroup sm_config + * + * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param out_base 0-31 First pin to set as output + */ +static inline void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base) { + check_pio_pin_param(out_base); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_BASE_BITS) | + ((out_base & 31) << PIO_SM0_PINCTRL_OUT_BASE_LSB); +#if PICO_PIO_USE_GPIO_BASE + c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_OUT_BASE_LSB)) | + ((out_base >> 4) << PIO_SM0_PINCTRL_OUT_BASE_LSB); +#endif +} + +/*! \brief Set the number of 'out' pins in a state machine configuration + * \ingroup sm_config + * + * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param out_count 0-32 Number of pins to set. + */ +static inline void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count) { + valid_params_if(HARDWARE_PIO, out_count <= 32); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_COUNT_BITS) | + (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); } /*! \brief Set the 'out' pins in a state machine configuration * \ingroup sm_config * - * Can overlap with the 'in', 'set' and 'sideset' pins + * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins * * \param c Pointer to the configuration structure to modify * \param out_base 0-31 First pin to set as output * \param out_count 0-32 Number of pins to set. */ static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) { - valid_params_if(PIO, out_base < 32); - valid_params_if(PIO, out_count <= 32); - c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | - (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | - (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); + sm_config_set_out_pin_base(c, out_base); + sm_config_set_out_pin_count(c, out_count); +} + +/*! \brief Set the base of the 'set' pins in a state machine configuration + * \ingroup sm_config + * + * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param set_base 0-31 First pin to set as + */ +static inline void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base) { + check_pio_pin_param(set_base); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_BASE_BITS) | + ((set_base & 31) << PIO_SM0_PINCTRL_SET_BASE_LSB); +#if PICO_PIO_USE_GPIO_BASE + c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SET_BASE_LSB)) | + ((set_base >> 4) << PIO_SM0_PINCTRL_SET_BASE_LSB); +#endif +} + +/*! \brief Set the count of 'set' pins in a state machine configuration + * \ingroup sm_config + * + * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param set_count 0-5 Number of pins to set. + */ +static inline void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count) { + valid_params_if(HARDWARE_PIO, set_count <= 5); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_COUNT_BITS) | + (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); } /*! \brief Set the 'set' pins in a state machine configuration * \ingroup sm_config * - * Can overlap with the 'in', 'out' and 'sideset' pins + * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins * * \param c Pointer to the configuration structure to modify * \param set_base 0-31 First pin to set as * \param set_count 0-5 Number of pins to set. */ static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) { - valid_params_if(PIO, set_base < 32); - valid_params_if(PIO, set_count <= 5); - c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | - (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | - (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); + sm_config_set_set_pin_base(c, set_base); + sm_config_set_set_pin_count(c, set_count); } -/*! \brief Set the 'in' pins in a state machine configuration +/*! \brief Set the base of the 'in' pins in a state machine configuration * \ingroup sm_config * - * Can overlap with the 'out', 'set' and 'sideset' pins + * 'in' pins can overlap with the 'out', 'set' and 'sideset' pins * * \param c Pointer to the configuration structure to modify * \param in_base 0-31 First pin to use as input */ -static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { - valid_params_if(PIO, in_base < 32); +static inline void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base) { + check_pio_pin_param(in_base); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | - (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); + ((in_base & 31) << PIO_SM0_PINCTRL_IN_BASE_LSB); +#if PICO_PIO_USE_GPIO_BASE + c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_IN_BASE_LSB)) | + ((in_base >> 4) << PIO_SM0_PINCTRL_IN_BASE_LSB); +#endif +} + +/*! \brief Set the base fpr the 'in' pins in a state machine configuration + * \ingroup sm_config + * + * 'in' pins can overlap with the 'out', 'set' and 'sideset' pins + * + * \param c Pointer to the configuration structure to modify + * \param in_base 0-31 First pin to use as input + */ +static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { + sm_config_set_in_pin_base(c, in_base); +} + +static inline void sm_config_set_in_pin_count(pio_sm_config *c, uint in_count) { +#if PICO_PIO_VERSION == 0 + // can't be changed from 32 on PIO v0 + ((void)c); + valid_params_if(HARDWARE_PIO, in_count == 32); +#else + valid_params_if(HARDWARE_PIO, in_count && in_count <= 32); + c->shiftctrl = (c->shiftctrl & ~PIO_SM0_SHIFTCTRL_IN_COUNT_BITS) | + ((in_count - 1) << PIO_SM0_SHIFTCTRL_IN_COUNT_LSB); +#endif +} + +/*! \brief Set the base of the 'sideset' pins in a state machine configuration + * \ingroup sm_config + * + * 'sideset' pins can overlap with the 'in', 'out' and 'set' pins + * + * \param c Pointer to the configuration structure to modify + * \param sideset_base 0-31 base pin for 'side set' + */ +static inline void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base) { + check_pio_pin_param(sideset_base); + c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | + ((sideset_base & 31) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); +#if PICO_PIO_USE_GPIO_BASE + c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) | + ((sideset_base >> 4) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); +#endif } /*! \brief Set the 'sideset' pins in a state machine configuration * \ingroup sm_config * - * Can overlap with the 'in', 'out' and 'set' pins + * This method is identical to \ref sm_config_set_sideset_pin_base, and is provided + * for backwards compatibility + * + * 'sideset' pins can overlap with the 'in', 'out' and 'set' pins * * \param c Pointer to the configuration structure to modify * \param sideset_base 0-31 base pin for 'side set' */ static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) { - valid_params_if(PIO, sideset_base < 32); - c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | - (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); + sm_config_set_sideset_pin_base(c, sideset_base); } /*! \brief Set the 'sideset' options in a state machine configuration @@ -190,11 +436,10 @@ static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_bas * \param pindirs True if the side set affects pin directions rather than values */ static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) { - valid_params_if(PIO, bit_count <= 5); - valid_params_if(PIO, !optional || bit_count >= 1); + valid_params_if(HARDWARE_PIO, bit_count <= 5); + valid_params_if(HARDWARE_PIO, !optional || bit_count >= 1); c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) | (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB); - c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) | (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) | (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); @@ -214,14 +459,14 @@ static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool * \sa sm_config_set_clkdiv() */ static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) { - invalid_params_if(PIO, div_int == 0 && div_frac != 0); + invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0); c->clkdiv = (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); } static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) { - valid_params_if(PIO, div >= 1 && div <= 65536); + valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536); *div_int = (uint16_t)div; if (*div_int == 0) { *div_frac = 0; @@ -261,8 +506,8 @@ static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { * if the instruction does not itself update the program_counter */ static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) { - valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT); - valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT); + valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT); + valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT); c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB); @@ -275,9 +520,13 @@ static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint w * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction */ static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { - valid_params_if(PIO, pin < 32); + check_pio_pin_param(pin); c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) | - (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB); + ((pin & 31) << PIO_SM0_EXECCTRL_JMP_PIN_LSB); +#if PICO_PIO_USE_GPIO_BASE + c->pinhi = (c->pinhi & ~(31u << 24)) | + ((pin >> 4) << 24); +#endif } /*! \brief Setup 'in' shifting parameters in a state machine configuration @@ -289,7 +538,7 @@ static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR */ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) { - valid_params_if(PIO, push_threshold <= 32); + valid_params_if(HARDWARE_PIO, push_threshold <= 32); c->shiftctrl = (c->shiftctrl & ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS | PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS | @@ -308,7 +557,7 @@ static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bo * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR */ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) { - valid_params_if(PIO, pull_threshold <= 32); + valid_params_if(HARDWARE_PIO, pull_threshold <= 32); c->shiftctrl = (c->shiftctrl & ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS | PIO_SM0_SHIFTCTRL_AUTOPULL_BITS | @@ -325,9 +574,20 @@ static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, b * \param join Specifies the join type. \see enum pio_fifo_join */ static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) { - valid_params_if(PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX); + valid_params_if(HARDWARE_PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX +#if PICO_PIO_VERSION > 0 + || join == PIO_FIFO_JOIN_TXPUT || join == PIO_FIFO_JOIN_TXGET || join == PIO_FIFO_JOIN_PUTGET +#endif + ); +#if PICO_PIO_VERSION == 0 c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); +#else + c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS | + PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS)) | + (((uint)(join & 3)) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB) | + (((uint)(join >> 2)) << PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB); +#endif } /*! \brief Set special 'out' operations in a state machine configuration @@ -355,14 +615,18 @@ static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool * \param status_n parameter for the mov status operation (currently a bit count) */ static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) { - valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN); + valid_params_if(HARDWARE_PIO, + status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN +#if PICO_PIO_VERSION > 0 + || status_sel == STATUS_IRQ_SET +#endif + ); c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS)) | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS) | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS); } - /*! \brief Get the default state machine configuration * \ingroup sm_config * @@ -383,7 +647,10 @@ static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_statu * \return the default state machine configuration which can then be modified. */ static inline pio_sm_config pio_get_default_sm_config(void) { - pio_sm_config c = {0, 0, 0, 0}; + pio_sm_config c = {0}; +#if PICO_PIO_USE_GPIO_BASE + c.pinhi = -1; +#endif sm_config_set_clkdiv_int_frac(&c, 1, 0); sm_config_set_wrap(&c, 0, 31); sm_config_set_in_shift(&c, true, false, 32); @@ -391,31 +658,90 @@ static inline pio_sm_config pio_get_default_sm_config(void) { return c; } +/*! \brief Return the base GPIO base for the PIO instance + * \ingroup hardware_pio + * + * \if rp2040_specific + * This method always return 0 in RP2040 + * \endif + * + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \return the current GPIO base for the PIO instance + */ +static inline uint pio_get_gpio_base(PIO pio) { +#if PICO_PIO_VERSION > 0 + return pio->gpiobase; +#else + ((void)pio); + return 0; +#endif +} + /*! \brief Apply a state machine configuration to a state machine * \ingroup hardware_pio * - * \param pio Handle to PIO instance; either \ref pio0 or \ref pio1 + * \param pio Handle to PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param config the configuration to apply + * \return PICO_OK (0) on success, negative error code otherwise */ -static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) { +static inline int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) { check_pio_param(pio); check_sm_param(sm); pio->sm[sm].clkdiv = config->clkdiv; pio->sm[sm].execctrl = config->execctrl; pio->sm[sm].shiftctrl = config->shiftctrl; +#if PICO_PIO_USE_GPIO_BASE + uint used = (~config->pinhi >> 4) & PINHI_ALL_PIN_LSBS; + // configs that use pins 0-15 + uint gpio_under_16 = (~config->pinhi) & (~config->pinhi >> 1) & used; + // configs that use pins 32-47 + uint gpio_over_32 = (config->pinhi >> 1) & used; + uint gpio_base = pio_get_gpio_base(pio); + invalid_params_if_and_return(PIO, gpio_under_16 && gpio_base, PICO_ERROR_BAD_ALIGNMENT); + invalid_params_if_and_return(PIO, gpio_over_32 && !gpio_base, PICO_ERROR_BAD_ALIGNMENT); + // flip the top bit of any used (pinctrl) values to turn: + // bit6(32) + 0-15 -> base(16) + 16-31 + // bit6(0) + 16-31 -> base(16) + 0-15 + pio->sm[sm].pinctrl = config->pinctrl ^ (gpio_base ? ((used << 12) >> 8) : 0); +#else pio->sm[sm].pinctrl = config->pinctrl; +#endif + return PICO_OK; } /*! \brief Return the instance number of a PIO instance * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 - * \return the PIO instance number (either 0 or 1) + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \return the PIO instance number (0, 1, ...) */ static inline uint pio_get_index(PIO pio) { check_pio_param(pio); - return pio == pio1 ? 1 : 0; + return PIO_NUM(pio); +} + +/*! \brief Return the funcsel number of a PIO instance + * \ingroup hardware_pio + * + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \return the PIO instance number (0, 1, ...) + * \see gpio_function + */ +static inline uint pio_get_funcsel(PIO pio) { + check_pio_param(pio); + return PIO_FUNCSEL_NUM(pio, 0); // note GPIO currently unused, so won't bother updating API +} + +/*! \brief Convert PIO instance to hardware instance + * \ingroup hardware_pio + * + * \param instance Instance of PIO, 0 or 1 + * \return the PIO hardware instance + */ +static inline PIO pio_get_instance(uint instance) { + invalid_params_if(HARDWARE_PIO, instance >= NUM_PIOS); + return PIO_INSTANCE(instance); } /*! \brief Setup the function select for a GPIO to use output from the given PIO instance @@ -427,43 +753,55 @@ static inline uint pio_get_index(PIO pio) { * be able to read the *input* value from a GPIO, but only for it to set the * output value or output enable. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param pin the GPIO pin whose function select to set */ static inline void pio_gpio_init(PIO pio, uint pin) { check_pio_param(pio); - valid_params_if(PIO, pin < 32); - gpio_set_function(pin, pio == pio0 ? GPIO_FUNC_PIO0 : GPIO_FUNC_PIO1); + valid_params_if(HARDWARE_PIO, pin < NUM_BANK0_GPIOS); + gpio_set_function(pin, PIO_FUNCSEL_NUM(pio, pin)); } /*! \brief Return the DREQ to use for pacing transfers to/from a particular state machine FIFO * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param is_tx true for sending data to the state machine, false for receiving data from the state machine */ static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) { - static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, ""); - static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, ""); - static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, ""); - static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, ""); - static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, ""); check_pio_param(pio); check_sm_param(sm); - return sm + (is_tx ? 0 : NUM_PIO_STATE_MACHINES) + (pio == pio0 ? DREQ_PIO0_TX0 : DREQ_PIO1_TX0); + return PIO_DREQ_NUM(pio, sm, is_tx); } typedef struct pio_program { const uint16_t *instructions; uint8_t length; int8_t origin; // required instruction memory origin or -1 -} __packed pio_program_t; + uint8_t pio_version; +#if PICO_PIO_VERSION > 0 + uint8_t used_gpio_ranges; // bitmap with one bit per 16 pins +#endif +} pio_program_t; + +/*! \brief Set the base GPIO base for the PIO instance + * \ingroup hardware_pio + * + * Since an individual PIO accesses only 32 pins, to be able to access more pins, the PIO + * instance must specify a base GPIO where the instance's "pin 0" maps. For RP2350 the valid + * values are 0 and 16, indicating the PIO instance has access to pins 0-31, or 16-47 respectively. + * + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \param gpio_base the GPIO base (either 0 or 16) + * \return PICO_OK (0) on success, error code otherwise + */ +int pio_set_gpio_base(PIO pio, uint gpio_base); /*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param program the program definition * \return true if the program can be loaded; false if there is not suitable space in the instruction memory */ @@ -472,39 +810,42 @@ bool pio_can_add_program(PIO pio, const pio_program_t *program); /*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance starting at a particular location * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param program the program definition * \param offset the instruction memory offset wanted for the start of the program * \return true if the program can be loaded at that location; false if there is not space in the instruction memory */ bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset); -/*! \brief Attempt to load the program, panicking if not possible +/*! \brief Attempt to load the program * \ingroup hardware_pio * * \see pio_can_add_program() if you need to check whether the program can be loaded * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param program the program definition - * \return the instruction memory offset the program is loaded at + * \return the instruction memory offset the program is loaded at, or negative for error (for + * backwards compatibility with prior SDK the error value is -1 i.e. PICO_ERROR_GENERIC) */ -uint pio_add_program(PIO pio, const pio_program_t *program); +int pio_add_program(PIO pio, const pio_program_t *program); -/*! \brief Attempt to load the program at the specified instruction memory offset, panicking if not possible +/*! \brief Attempt to load the program at the specified instruction memory offset * \ingroup hardware_pio * * \see pio_can_add_program_at_offset() if you need to check whether the program can be loaded * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param program the program definition * \param offset the instruction memory offset wanted for the start of the program + * \return the instruction memory offset the program is loaded at, or negative for error (for + * backwards compatibility with prior SDK the error value is -1 i.e. PICO_ERROR_GENERIC) */ -void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset); +int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset); /*! \brief Remove a program from a PIO instance's instruction memory * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param program the program definition * \param loaded_offset the loaded offset returned when the program was added */ @@ -513,7 +854,7 @@ void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offse /*! \brief Clears all of a PIO instance's instruction memory * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 */ void pio_clear_instruction_memory(PIO pio); @@ -529,17 +870,18 @@ void pio_clear_instruction_memory(PIO pio); * * The state machine is left disabled on return from this call. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param initial_pc the initial program memory offset to run from * \param config the configuration to apply (or NULL to apply defaults) + * \return PICO_OK, or < 0 for an error (see \enum pico_error_codes) */ -void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config); +int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config); /*! \brief Enable or disable a PIO state machine * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param enabled true to enable the state machine; false to disable */ @@ -558,7 +900,7 @@ static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines * and ensure their clock dividers are in sync. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of * \param enabled true to enable the state machines; false to disable */ @@ -568,13 +910,41 @@ static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); } +#if PICO_PIO_VERSION > 0 +/*! \brief Enable or disable multiple PIO state machines + * \ingroup hardware_pio + * + * Note that this method just sets the enabled state of the state machine; + * if now enabled they continue exactly from where they left off. + * + * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines + * and ensure their clock dividers are in sync. + * + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \param mask_prev bit mask of state machine indexes to modify the enabled state of, in the next-lower numbered PIO instance + * \param mask bit mask of state machine indexes to modify the enabled state of, in this PIO instance + * \param mask bit mask of state machine indexes to modify the enabled state of, in the next-higher numbered PIO instance + * \param enabled true to enable the state machines; false to disable + */ +static inline void pio_set_sm_multi_mask_enabled(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next, bool enabled) { + check_pio_param(pio); + check_sm_mask(mask); + pio->ctrl = (pio->ctrl & ~(mask << PIO_CTRL_SM_ENABLE_LSB)) | + (enabled ? ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) : 0) | + (enabled ? PIO_CTRL_NEXTPREV_SM_ENABLE_BITS : PIO_CTRL_NEXTPREV_SM_DISABLE_BITS) | + ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) | + ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS); + +} +#endif + /*! \brief Restart a state machine with a known state * \ingroup hardware_pio * * This method clears the ISR, shift counters, clock divider counter * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ static inline void pio_sm_restart(PIO pio, uint sm) { @@ -589,7 +959,7 @@ static inline void pio_sm_restart(PIO pio, uint sm) { * This method clears the ISR, shift counters, clock divider counter * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { @@ -616,7 +986,7 @@ static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { * More commonly this hardware mechanism is used to synchronise the execution * clocks of multiple state machines -- see pio_clkdiv_restart_sm_mask(). * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) { @@ -649,9 +1019,9 @@ static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) { * machines and wish to resynchronise them), and that disabling a state * machine does not halt its clock divider: that is, if multiple state * machines have their clocks synchronised, you can safely disable and - * reenable one of the state machines without losing synchronisation. + * re-enable one of the state machines without losing synchronisation. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { @@ -660,6 +1030,48 @@ static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS); } +#if PICO_PIO_VERSION > 0 +/*! \brief Restart multiple state machines' clock dividers on multiple PIOs from a phase of 0. + * \ingroup hardware_pio + * + * Each state machine's clock divider is a free-running piece of hardware, + * that generates a pattern of clock enable pulses for the state machine, + * based *only* on the configured integer/fractional divisor. The pattern of + * running/halted cycles slows the state machine's execution to some + * controlled rate. + * + * This function simultaneously clears the integer and fractional phase + * accumulators of multiple state machines' clock dividers. If these state + * machines all have the same integer and fractional divisors configured, + * their clock dividers will run in precise deterministic lockstep from this + * point. + * + * With their execution clocks synchronised in this way, it is then safe to + * e.g. have multiple state machines performing a 'wait irq' on the same flag, + * and all clear it on the same cycle. + * + * Also note that this function can be called whilst state machines are + * running (e.g. if you have just changed the clock divisors of some state + * machines and wish to resynchronise them), and that disabling a state + * machine does not halt its clock divider: that is, if multiple state + * machines have their clocks synchronised, you can safely disable and + * re-enable one of the state machines without losing synchronisation. + * + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \param mask_prev bit mask of state machine indexes to modify the enabled state of, in the next-lower numbered PIO instance + * \param mask bit mask of state machine indexes to modify the enabled state of, in this PIO instance + * \param mask_next bit mask of state machine indexes to modify the enabled state of, in the next-higher numbered PIO instance + */ +static inline void pio_clkdiv_restart_sm_multi_mask(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) { + check_pio_param(pio); + check_sm_mask(mask); + hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | + PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS | + ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) | + ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS)); +} +#endif + /*! \brief Enable multiple PIO state machines synchronizing their clock dividers * \ingroup hardware_pio * @@ -668,7 +1080,7 @@ static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { * specified by 'mask' are started simultaneously and, assuming they have the * same clock divisors, their divided clocks will stay precisely synchronised. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param mask bit mask of state machine indexes to modify the enabled state of */ static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { @@ -679,34 +1091,67 @@ static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) { ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS)); } +#if PICO_PIO_VERSION > 0 +/*! \brief Enable multiple PIO state machines on multiple PIOs synchronizing their clock dividers + * \ingroup hardware_pio + * + * This is equivalent to calling both pio_set_sm_multi_mask_enabled() and + * pio_clkdiv_restart_sm_multi_mask() on the *same* clock cycle. All state machines + * specified by 'mask' are started simultaneously and, assuming they have the + * same clock divisors, their divided clocks will stay precisely synchronised. + * + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \param mask_prev bit mask of state machine indexes to modify the enabled state of, in the next-lower numbered PIO instance + * \param mask bit mask of state machine indexes to modify the enabled state of, in this PIO instance + * \param mask_next bit mask of state machine indexes to modify the enabled state of, in the next-higher numbered PIO instance + */ +static inline void pio_enable_sm_multi_mask_in_sync(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) { + check_pio_param(pio); + check_sm_mask(mask); + check_pio_param(pio); + check_sm_mask(mask); + hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | + ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) | + PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS | PIO_CTRL_NEXTPREV_SM_ENABLE_BITS | + ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) | + ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS)); +} +#endif + /*! \brief PIO interrupt source numbers for pio related IRQs * \ingroup hardware_pio */ -enum pio_interrupt_source { - pis_interrupt0 = PIO_INTR_SM0_LSB, - pis_interrupt1 = PIO_INTR_SM1_LSB, - pis_interrupt2 = PIO_INTR_SM2_LSB, - pis_interrupt3 = PIO_INTR_SM3_LSB, - pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB, - pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB, - pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB, - pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB, - pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB, - pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB, - pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB, - pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB, -}; +typedef enum pio_interrupt_source { + pis_interrupt0 = PIO_INTR_SM0_LSB, ///< PIO interrupt 0 is raised + pis_interrupt1 = PIO_INTR_SM1_LSB, ///< PIO interrupt 1 is raised + pis_interrupt2 = PIO_INTR_SM2_LSB, ///< PIO interrupt 2 is raised + pis_interrupt3 = PIO_INTR_SM3_LSB, ///< PIO interrupt 3 is raised +#if PICO_PIO_VERSION > 0 + pis_interrupt4 = PIO_INTR_SM4_LSB, ///< PIO interrupt 4 is raised + pis_interrupt5 = PIO_INTR_SM5_LSB, ///< PIO interrupt 5 is raised + pis_interrupt6 = PIO_INTR_SM6_LSB, ///< PIO interrupt 6 is raised + pis_interrupt7 = PIO_INTR_SM7_LSB, ///< PIO interrupt 7 is raised +#endif + pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB, ///< State machine 0 TX FIFO is not full + pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB, ///< State machine 1 TX FIFO is not full + pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB, ///< State machine 2 TX FIFO is not full + pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB, ///< State machine 3 TX FIFO is not full + pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB, ///< State machine 0 RX FIFO is not empty + pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB, ///< State machine 1 RX FIFO is not empty + pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB, ///< State machine 2 RX FIFO is not empty + pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB, ///< State machine 3 RX FIFO is not empty +} pio_interrupt_source_t; /*! \brief Enable/Disable a single source on a PIO's IRQ 0 * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param source the source number (see \ref pio_interrupt_source) * \param enabled true to enable IRQ 0 for the source, false to disable. */ -static inline void pio_set_irq0_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) { +static inline void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) { check_pio_param(pio); - invalid_params_if(PIO, source >= 12); + invalid_params_if(HARDWARE_PIO, source >= 32u || (1u << source) > PIO_INTR_BITS); if (enabled) hw_set_bits(&pio->inte0, 1u << source); else @@ -716,13 +1161,13 @@ static inline void pio_set_irq0_source_enabled(PIO pio, enum pio_interrupt_sourc /*! \brief Enable/Disable a single source on a PIO's IRQ 1 * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param source the source number (see \ref pio_interrupt_source) * \param enabled true to enable IRQ 0 for the source, false to disable. */ -static inline void pio_set_irq1_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) { +static inline void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) { check_pio_param(pio); - invalid_params_if(PIO, source >= 12); + invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS); if (enabled) hw_set_bits(&pio->inte1, 1u << source); else @@ -732,13 +1177,13 @@ static inline void pio_set_irq1_source_enabled(PIO pio, enum pio_interrupt_sourc /*! \brief Enable/Disable multiple sources on a PIO's IRQ 0 * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect * \param enabled true to enable all the sources specified in the mask on IRQ 0, false to disable all the sources specified in the mask on IRQ 0 */ static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { check_pio_param(pio); - invalid_params_if(PIO, source_mask > PIO_INTR_BITS); + invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS); if (enabled) { hw_set_bits(&pio->inte0, source_mask); } else { @@ -749,13 +1194,13 @@ static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mas /*! \brief Enable/Disable multiple sources on a PIO's IRQ 1 * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect * \param enabled true to enable all the sources specified in the mask on IRQ 1, false to disable all the source specified in the mask on IRQ 1 */ static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) { check_pio_param(pio); - invalid_params_if(PIO, source_mask > PIO_INTR_BITS); + invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS); if (enabled) { hw_set_bits(&pio->inte1, source_mask); } else { @@ -766,66 +1211,68 @@ static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mas /*! \brief Enable/Disable a single source on a PIO's specified (0/1) IRQ index * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param irq_index the IRQ index; either 0 or 1 * \param source the source number (see \ref pio_interrupt_source) * \param enabled true to enable the source on the specified IRQ, false to disable. */ -static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, enum pio_interrupt_source source, bool enabled) { - invalid_params_if(PIO, irq_index > 1); - if (irq_index) { - pio_set_irq1_source_enabled(pio, source, enabled); - } else { - pio_set_irq0_source_enabled(pio, source, enabled); - } +static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled) { + invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS); + invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS); + if (enabled) + hw_set_bits(&pio->irq_ctrl[irq_index].inte, 1u << source); + else + hw_clear_bits(&pio->irq_ctrl[irq_index].inte, 1u << source); } /*! \brief Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param irq_index the IRQ index; either 0 or 1 * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect * \param enabled true to enable all the sources specified in the mask on the specified IRQ, false to disable all the sources specified in the mask on the specified IRQ */ static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) { - invalid_params_if(PIO, irq_index > 1); - if (irq_index) { - pio_set_irq1_source_mask_enabled(pio, source_mask, enabled); + invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS); + static_assert(NUM_PIO_IRQS == 2, ""); + invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS); + if (enabled) { + hw_set_bits(&pio->irq_ctrl[irq_index].inte, source_mask); } else { - pio_set_irq0_source_mask_enabled(pio, source_mask, enabled); + hw_clear_bits(&pio->irq_ctrl[irq_index].inte, source_mask); } } /*! \brief Determine if a particular PIO interrupt is set * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param pio_interrupt_num the PIO interrupt number 0-7 * \return true if corresponding PIO interrupt is currently set */ static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) { check_pio_param(pio); - invalid_params_if(PIO, pio_interrupt_num >= 8); + invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8); return pio->irq & (1u << pio_interrupt_num); } /*! \brief Clear a particular PIO interrupt * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param pio_interrupt_num the PIO interrupt number 0-7 */ static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) { check_pio_param(pio); - invalid_params_if(PIO, pio_interrupt_num >= 8); + invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8); pio->irq = (1u << pio_interrupt_num); } /*! \brief Return the current program counter for a state machine * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return the program counter */ @@ -843,7 +1290,7 @@ static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) { * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction * is still running (i.e. it is stalled on some condition) * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param instr the encoded PIO instruction */ @@ -856,14 +1303,14 @@ inline static void pio_sm_exec(PIO pio, uint sm, uint instr) { /*! \brief Determine if an instruction set by pio_sm_exec() is stalled executing * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return true if the executed instruction is still running (stalled) */ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { check_pio_param(pio); check_sm_param(sm); - return !!(pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS); + return pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS; } /*! \brief Immediately execute an instruction on a state machine and wait for it to complete @@ -874,7 +1321,7 @@ static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) { * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction * is still running (i.e. it is stalled on some condition) * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param instr the encoded PIO instruction */ @@ -888,7 +1335,7 @@ static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { /*! \brief Set the current wrap configuration for a state machine * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param wrap_target the instruction memory address to wrap to * \param wrap the instruction memory address after which to set the program counter to wrap_target @@ -897,8 +1344,8 @@ static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) { check_pio_param(pio); check_sm_param(sm); - valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT); - valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT); + valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT); + valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT); pio->sm[sm].execctrl = (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | @@ -908,9 +1355,9 @@ static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap /*! \brief Set the current 'out' pins for a state machine * \ingroup hardware_pio * - * Can overlap with the 'in', 'set' and 'sideset' pins + * 'out' pins can overlap with the 'in', 'set' and 'sideset' pins * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param out_base 0-31 First pin to set as output * \param out_count 0-32 Number of pins to set. @@ -918,8 +1365,11 @@ static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) { check_pio_param(pio); check_sm_param(sm); - valid_params_if(PIO, out_base < 32); - valid_params_if(PIO, out_count <= 32); +#if PICO_PIO_USE_GPIO_BASE + out_base -= pio_get_gpio_base(pio); +#endif + valid_params_if(HARDWARE_PIO, out_base < 32); + valid_params_if(HARDWARE_PIO, out_count <= 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) | (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB); @@ -929,9 +1379,9 @@ static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out /*! \brief Set the current 'set' pins for a state machine * \ingroup hardware_pio * - * Can overlap with the 'in', 'out' and 'sideset' pins + * 'set' pins can overlap with the 'in', 'out' and 'sideset' pins * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param set_base 0-31 First pin to set as * \param set_count 0-5 Number of pins to set. @@ -939,8 +1389,11 @@ static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) { check_pio_param(pio); check_sm_param(sm); - valid_params_if(PIO, set_base < 32); - valid_params_if(PIO, set_count <= 5); +#if PICO_PIO_USE_GPIO_BASE + set_base -= pio_get_gpio_base(pio); +#endif + valid_params_if(HARDWARE_PIO, set_base < 32); + valid_params_if(HARDWARE_PIO, set_count <= 5); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) | (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) | (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB); @@ -949,16 +1402,19 @@ static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set /*! \brief Set the current 'in' pins for a state machine * \ingroup hardware_pio * - * Can overlap with the 'out', 'set' and 'sideset' pins + * 'in' pins can overlap with the 'out', 'set' and 'sideset' pins * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param in_base 0-31 First pin to use as input */ static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { check_pio_param(pio); check_sm_param(sm); - valid_params_if(PIO, in_base < 32); +#if PICO_PIO_USE_GPIO_BASE + in_base -= pio_get_gpio_base(pio); +#endif + valid_params_if(HARDWARE_PIO, in_base < 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) | (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB); } @@ -966,20 +1422,43 @@ static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) { /*! \brief Set the current 'sideset' pins for a state machine * \ingroup hardware_pio * - * Can overlap with the 'in', 'out' and 'set' pins + * 'sideset' pins can overlap with the 'in', 'out' and 'set' pins * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param sideset_base 0-31 base pin for 'side set' */ static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) { check_pio_param(pio); check_sm_param(sm); - valid_params_if(PIO, sideset_base < 32); +#if PICO_PIO_USE_GPIO_BASE + sideset_base -= pio_get_gpio_base(pio); +#endif + valid_params_if(HARDWARE_PIO, sideset_base < 32); pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB); } +/*! \brief Set the 'jmp' pin for a state machine + * \ingroup hardware_pio + * + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 + * \param sm State machine index (0..3) + * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction + */ + +static inline void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin) { + check_pio_param(pio); + check_sm_param(sm); +#if PICO_PIO_USE_GPIO_BASE + pin -= pio_get_gpio_base(pio); +#endif + valid_params_if(HARDWARE_PIO, pin < 32); + pio->sm[sm].execctrl = + (pio->sm[sm].execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) + | (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB); +} + /*! \brief Write a word of data to a state machine's TX FIFO * \ingroup hardware_pio * @@ -988,7 +1467,7 @@ static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) * Hardware sets the TXOVER sticky flag for this FIFO in FDEBUG, to indicate * that the system attempted to write to a full FIFO. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param data the 32 bit data value * @@ -1010,7 +1489,7 @@ static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { * from this FIFO when empty. The data returned by this function is undefined * when the FIFO is empty. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * * \sa pio_sm_get_blocking() @@ -1024,7 +1503,7 @@ static inline uint32_t pio_sm_get(PIO pio, uint sm) { /*! \brief Determine if a state machine's RX FIFO is full * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return true if the RX FIFO is full */ @@ -1037,7 +1516,7 @@ static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { /*! \brief Determine if a state machine's RX FIFO is empty * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return true if the RX FIFO is empty */ @@ -1050,7 +1529,7 @@ static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { /*! \brief Return the number of elements currently in a state machine's RX FIFO * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return the number of elements in the RX FIFO */ @@ -1065,7 +1544,7 @@ static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { /*! \brief Determine if a state machine's TX FIFO is full * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return true if the TX FIFO is full */ @@ -1078,7 +1557,7 @@ static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { /*! \brief Determine if a state machine's TX FIFO is empty * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return true if the TX FIFO is empty */ @@ -1091,7 +1570,7 @@ static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { /*! \brief Return the number of elements currently in a state machine's TX FIFO * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return the number of elements in the TX FIFO */ @@ -1106,7 +1585,7 @@ static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { /*! \brief Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param data the 32 bit data value */ @@ -1120,7 +1599,7 @@ static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { /*! \brief Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { @@ -1138,7 +1617,7 @@ static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { * pio_sm_clear_fifos() which clears both FIFOs but leaves the state machine's * internal state undisturbed. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * * \sa pio_sm_clear_fifos() @@ -1148,7 +1627,7 @@ void pio_sm_drain_tx_fifo(PIO pio, uint sm); /*! \brief set the current clock divider for a state machine using a 16:8 fraction * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param div_int the integer part of the clock divider * \param div_frac the fractional part of the clock divider in 1/256s @@ -1156,7 +1635,7 @@ void pio_sm_drain_tx_fifo(PIO pio, uint sm); static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) { check_pio_param(pio); check_sm_param(sm); - invalid_params_if(PIO, div_int == 0 && div_frac != 0); + invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0); pio->sm[sm].clkdiv = (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) | (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB); @@ -1165,7 +1644,7 @@ static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int /*! \brief set the current clock divider for a state machine * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \param div the floating point clock divider */ @@ -1181,7 +1660,7 @@ static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { /*! \brief Clear a state machine's TX and RX FIFOs * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ static inline void pio_sm_clear_fifos(PIO pio, uint sm) { @@ -1200,7 +1679,7 @@ static inline void pio_sm_clear_fifos(PIO pio, uint sm) { * * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) to use * \param pin_values the pin values to set */ @@ -1214,7 +1693,7 @@ void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values); * * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) to use * \param pin_values the pin values to set (if the corresponding bit in pin_mask is set) * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied. @@ -1229,7 +1708,7 @@ void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t p * * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) to use * \param pin_dirs the pin directions to set - 1 = out, 0 = in (if the corresponding bit in pin_mask is set) * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied. @@ -1244,13 +1723,14 @@ void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t * * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) to use - * \param pin_base the first pin to set a direction for + * \param pins_base the first pin to set a direction for * \param pin_count the count of consecutive pins to set the direction for * \param is_out the direction to set; true = out, false = in + * \return PICO_OK (0) on success, error code otherwise */ -void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, uint pin_count, bool is_out); +int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out); /*! \brief Mark a state machine as used * \ingroup hardware_pio @@ -1259,7 +1739,7 @@ void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, uint pin_co * is already claimed. Use of this method by libraries detects accidental * configurations that would fail in unpredictable ways. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ void pio_sm_claim(PIO pio, uint sm); @@ -1271,7 +1751,7 @@ void pio_sm_claim(PIO pio, uint sm); * are already claimed. Use of this method by libraries detects accidental * configurations that would fail in unpredictable ways. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm_mask Mask of state machine indexes */ void pio_claim_sm_mask(PIO pio, uint sm_mask); @@ -1281,7 +1761,7 @@ void pio_claim_sm_mask(PIO pio, uint sm_mask); * * Method for cooperative claiming of hardware. * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) */ void pio_sm_unclaim(PIO pio, uint sm); @@ -1289,16 +1769,17 @@ void pio_sm_unclaim(PIO pio, uint sm); /*! \brief Claim a free state machine on a PIO instance * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param required if true the function will panic if none are available - * \return the state machine index or -1 if required was false, and none were free + * \return the state machine index or negative if required was false, and none were free (for + * backwards compatibility with prior SDK the error value is -1 i.e. PICO_ERROR_GENERIC) */ int pio_claim_unused_sm(PIO pio, bool required); /*! \brief Determine if a PIO state machine is claimed * \ingroup hardware_pio * - * \param pio The PIO instance; either \ref pio0 or \ref pio1 + * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1 * \param sm State machine index (0..3) * \return true if claimed, false otherwise * \see pio_sm_claim @@ -1306,6 +1787,88 @@ int pio_claim_unused_sm(PIO pio, bool required); */ bool pio_sm_is_claimed(PIO pio, uint sm); +/*! \brief Finds a PIO and statemachine and adds a program into PIO memory + * \ingroup hardware_pio + * + * \param program PIO program to add + * \param pio Returns the PIO hardware instance or NULL if no PIO is available + * \param sm Returns the index of the PIO state machine that was claimed + * \param offset Returns the instruction memory offset of the start of the program + * \return true on success, false otherwise + * \see pio_remove_program_unclaim_sm + */ +bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset); + +/*! \brief Finds a PIO and statemachine and adds a program into PIO memory + * \ingroup hardware_pio + * + * This variation of \ref pio_claim_free_sm_and_add_program is useful on RP2350 QFN80 where the "GPIO Base" + * must be set per PIO instance to either address the 32 GPIOs (0->31) or the 32 GPIOS (16-47). No single + * PIO instance can interact with both pins 0->15 or 32->47 at the same time. + * + * This method takes additional information about the GPIO pins needed (via gpi_base and gpio_count), + * and optionally will set the GPIO base (\see pio_set_gpio_base) of an unused PIO instance if necessary + * + * \param program PIO program to add + * \param pio Returns the PIO hardware instance or NULL if no PIO is available + * \param sm Returns the index of the PIO state machine that was claimed + * \param offset Returns the instruction memory offset of the start of the program + * \param gpio_base the lowest GPIO number required + * \param gpio_count the count of GPIOs required + * \param set_gpio_base if there is no free SM on a PIO instance with the right GPIO base, and there IS an unused PIO + * instance, then that PIO will be reconfigured so that this method can succeed + * + * \return true on success, false otherwise + * \see pio_remove_program_unclaim_sm + */ +bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base); + +/*! \brief Removes a program from PIO memory and unclaims the state machine + * \ingroup hardware_pio + * + * \param program PIO program to remove from memory + * \param pio PIO hardware instance being used + * \param sm PIO state machine that was claimed + * \param offset offset of the program in PIO memory + * \see pio_claim_free_sm_and_add_program + */ +void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset); + +/*! \brief Return an IRQ for a PIO hardware instance + * \ingroup hardware_pio + * + * \param pio PIO hardware instance + * \param irqn 0 for PIOx_IRQ_0 or 1 for PIOx_IRQ_1 etc where x is the PIO number + * \return The IRQ number to use for the PIO + */ +static inline int pio_get_irq_num(PIO pio, uint irqn) { + check_pio_param(pio); + valid_params_if(HARDWARE_PIO, irqn < NUM_PIO_IRQS); + return PIO_IRQ_NUM(pio, irqn); +} + +/*! \brief Return the interrupt source for a state machines TX FIFO not full interrupt + * \ingroup hardware_pio + * + * \param sm State machine index (0..3) + * \return The interrupt source number for use in \ref pio_set_irqn_source_enabled or similar functions + */ +static inline pio_interrupt_source_t pio_get_tx_fifo_not_full_interrupt_source(uint sm) { + check_sm_param(sm); + return ((pio_interrupt_source_t)(pis_sm0_tx_fifo_not_full + sm)); +} + +/*! \brief Return the interrupt source for a state machines RX FIFO not empty interrupt + * \ingroup hardware_pio + * + * \param sm State machine index (0..3) + * \return The interrupt source number for use in \ref pio_set_irqn_source_enabled or similar functions + */ +static inline pio_interrupt_source_t pio_get_rx_fifo_not_empty_interrupt_source(uint sm) { + check_sm_param(sm); + return ((pio_interrupt_source_t)(pis_sm0_rx_fifo_not_empty + sm)); +} + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/hardware_pio/pio.c b/src/rp2_common/hardware_pio/pio.c index 613756621..120dbf3f1 100644 --- a/src/rp2_common/hardware_pio/pio.c +++ b/src/rp2_common/hardware_pio/pio.c @@ -13,21 +13,24 @@ check_hw_layout(pio_hw_t, sm[0].clkdiv, PIO_SM0_CLKDIV_OFFSET); check_hw_layout(pio_hw_t, sm[1].clkdiv, PIO_SM1_CLKDIV_OFFSET); check_hw_layout(pio_hw_t, instr_mem[0], PIO_INSTR_MEM0_OFFSET); check_hw_layout(pio_hw_t, inte0, PIO_IRQ0_INTE_OFFSET); +check_hw_layout(pio_hw_t, irq_ctrl[0].inte, PIO_IRQ0_INTE_OFFSET); check_hw_layout(pio_hw_t, txf[1], PIO_TXF1_OFFSET); check_hw_layout(pio_hw_t, rxf[3], PIO_RXF3_OFFSET); check_hw_layout(pio_hw_t, ints1, PIO_IRQ1_INTS_OFFSET); +check_hw_layout(pio_hw_t, irq_ctrl[1].ints, PIO_IRQ1_INTS_OFFSET); -static_assert(NUM_PIO_STATE_MACHINES * NUM_PIOS <= 8, ""); -static uint8_t claimed; +static uint8_t claimed[(NUM_PIO_STATE_MACHINES * NUM_PIOS + 7) >> 3]; void pio_sm_claim(PIO pio, uint sm) { check_sm_param(sm); uint which = pio_get_index(pio); - if (which) { - hw_claim_or_assert(&claimed, NUM_PIO_STATE_MACHINES + sm, "PIO 1 SM (%d - 4) already claimed"); - } else { - hw_claim_or_assert(&claimed, sm, "PIO 0 SM %d already claimed"); - } + const char *msg = +#if PICO_PIO_VERSION > 0 + which == 2 ? "PIO 2 SM (%d - 8) already claimed" : +#endif + which == 1 ? "PIO 1 SM (%d - 4) already claimed" : + "PIO 0 SM %d already claimed"; + hw_claim_or_assert(&claimed[0], which * NUM_PIO_STATE_MACHINES + sm, msg); } void pio_claim_sm_mask(PIO pio, uint sm_mask) { @@ -39,14 +42,14 @@ void pio_claim_sm_mask(PIO pio, uint sm_mask) { void pio_sm_unclaim(PIO pio, uint sm) { check_sm_param(sm); uint which = pio_get_index(pio); - hw_claim_clear(&claimed, which * NUM_PIO_STATE_MACHINES + sm); + hw_claim_clear(&claimed[0], which * NUM_PIO_STATE_MACHINES + sm); } int pio_claim_unused_sm(PIO pio, bool required) { - // PIO index is 0 or 1. + // PIO index ranges from 0 to NUM_PIOS - 1. uint which = pio_get_index(pio); uint base = which * NUM_PIO_STATE_MACHINES; - int index = hw_claim_unused_from_range((uint8_t*)&claimed, required, base, + int index = hw_claim_unused_from_range((uint8_t*)&claimed[0], required, base, base + NUM_PIO_STATE_MACHINES - 1, "No PIO state machines are available"); return index >= (int)base ? index - (int)base : -1; } @@ -54,18 +57,18 @@ int pio_claim_unused_sm(PIO pio, bool required) { bool pio_sm_is_claimed(PIO pio, uint sm) { check_sm_param(sm); uint which = pio_get_index(pio); - return hw_is_claimed(&claimed, which * NUM_PIO_STATE_MACHINES + sm); + return hw_is_claimed(&claimed[0], which * NUM_PIO_STATE_MACHINES + sm); } static_assert(PIO_INSTRUCTION_COUNT <= 32, ""); -static uint32_t _used_instruction_space[2]; +static uint32_t _used_instruction_space[NUM_PIOS]; -static int _pio_find_offset_for_program(PIO pio, const pio_program_t *program) { +static int find_offset_for_program(PIO pio, const pio_program_t *program) { assert(program->length <= PIO_INSTRUCTION_COUNT); uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; uint32_t program_mask = (1u << program->length) - 1; if (program->origin >= 0) { - if (program->origin > 32 - program->length) return -1; + if (program->origin > 32 - program->length) return PICO_ERROR_GENERIC; return used_mask & (program_mask << program->origin) ? -1 : program->origin; } else { // work down from the top always @@ -74,61 +77,114 @@ static int _pio_find_offset_for_program(PIO pio, const pio_program_t *program) { return i; } } - return -1; + return PICO_ERROR_INSUFFICIENT_RESOURCES; } } -bool pio_can_add_program(PIO pio, const pio_program_t *program) { +static int pio_set_gpio_base_unsafe(PIO pio, uint gpio_base) { + invalid_params_if_and_return(PIO, gpio_base != 0 && (!PICO_PIO_VERSION || gpio_base != 16), PICO_ERROR_BAD_ALIGNMENT); +#if PICO_PIO_VERSION > 0 + uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; + invalid_params_if_and_return(PIO, used_mask, PICO_ERROR_INVALID_STATE); + pio->gpiobase = gpio_base; +#else + ((void)pio); + ((void)gpio_base); +#endif + return PICO_OK; +} + +int pio_set_gpio_base(PIO pio, uint gpio_base) { + int rc = PICO_OK; +#if PICO_PIO_VERSION > 0 uint32_t save = hw_claim_lock(); - bool rc = -1 != _pio_find_offset_for_program(pio, program); + rc = pio_set_gpio_base_unsafe(pio, gpio_base); hw_claim_unlock(save); +#else + ((void)pio); + ((void)gpio_base); +#endif return rc; } -static bool _pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { - valid_params_if(PIO, offset < PIO_INSTRUCTION_COUNT); - valid_params_if(PIO, offset + program->length <= PIO_INSTRUCTION_COUNT); - if (program->origin >= 0 && (uint)program->origin != offset) return false; +static bool is_gpio_compatible(PIO pio, uint32_t used_gpio_ranges) { +#if PICO_PIO_VERSION > 0 + bool gpio_base = pio_get_gpio_base(pio); + return !((gpio_base && (used_gpio_ranges & 1)) || + (!gpio_base && (used_gpio_ranges & 4))); +#else + ((void)pio); + ((void)used_gpio_ranges); + return true; +#endif +} + +static bool is_program_gpio_compatible(PIO pio, const pio_program_t *program) { +#if PICO_PIO_VERSION > 0 + return is_gpio_compatible(pio, program->used_gpio_ranges); +#else + ((void)pio); + ((void)program); + return true; +#endif +} + +static int add_program_at_offset_check(PIO pio, const pio_program_t *program, uint offset) { + valid_params_if(HARDWARE_PIO, offset < PIO_INSTRUCTION_COUNT); + valid_params_if(HARDWARE_PIO, offset + program->length <= PIO_INSTRUCTION_COUNT); +#if PICO_PIO_VERSION == 0 + if (program->pio_version) return PICO_ERROR_VERSION_MISMATCH; +#endif + if (!is_program_gpio_compatible(pio, program)) return PICO_ERROR_BAD_ALIGNMENT; // todo better error? + if (program->origin >= 0 && (uint)program->origin != offset) return PICO_ERROR_BAD_ALIGNMENT; // todo better error? uint32_t used_mask = _used_instruction_space[pio_get_index(pio)]; uint32_t program_mask = (1u << program->length) - 1; - return !(used_mask & (program_mask << offset)); + return (used_mask & (program_mask << offset)) ? PICO_ERROR_INSUFFICIENT_RESOURCES : PICO_OK; +} + +bool pio_can_add_program(PIO pio, const pio_program_t *program) { + uint32_t save = hw_claim_lock(); + int rc = find_offset_for_program(pio, program); + if (rc >= 0) rc = add_program_at_offset_check(pio, program, (uint)rc); + hw_claim_unlock(save); + return rc == 0; } bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { uint32_t save = hw_claim_lock(); - bool rc = _pio_can_add_program_at_offset(pio, program, offset); + bool rc = add_program_at_offset_check(pio, program, offset) == 0; hw_claim_unlock(save); return rc; } -static void _pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { - if (!_pio_can_add_program_at_offset(pio, program, offset)) { - panic("No program space"); - } +static int add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { + int rc = add_program_at_offset_check(pio, program, offset); + if (rc != 0) return rc; for (uint i = 0; i < program->length; ++i) { uint16_t instr = program->instructions[i]; pio->instr_mem[offset + i] = pio_instr_bits_jmp != _pio_major_instr_bits(instr) ? instr : instr + offset; } uint32_t program_mask = (1u << program->length) - 1; _used_instruction_space[pio_get_index(pio)] |= program_mask << offset; + return (int)offset; } // these assert if unable -uint pio_add_program(PIO pio, const pio_program_t *program) { +int pio_add_program(PIO pio, const pio_program_t *program) { uint32_t save = hw_claim_lock(); - int offset = _pio_find_offset_for_program(pio, program); - if (offset < 0) { - panic("No program space"); + int offset = find_offset_for_program(pio, program); + if (offset >= 0) { + offset = add_program_at_offset(pio, program, (uint) offset); } - _pio_add_program_at_offset(pio, program, (uint)offset); hw_claim_unlock(save); - return (uint)offset; + return offset; } -void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { +int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { uint32_t save = hw_claim_lock(); - _pio_add_program_at_offset(pio, program, offset); + int rc = add_program_at_offset(pio, program, offset); hw_claim_unlock(save); + return rc; } void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset) { @@ -211,10 +267,11 @@ void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pindirs, uint32_t p pio->sm[sm].execctrl = execctrl_saved; } -void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) { +int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) { check_pio_param(pio); check_sm_param(sm); - valid_params_if(PIO, pin < 32u); + pin -= pio_get_gpio_base(pio); + invalid_params_if_and_return(PIO, pin >= 32u, PICO_ERROR_INVALID_ARG); uint32_t pinctrl_saved = pio->sm[sm].pinctrl; uint32_t execctrl_saved = pio->sm[sm].execctrl; hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); @@ -229,19 +286,22 @@ void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val)); pio->sm[sm].pinctrl = pinctrl_saved; pio->sm[sm].execctrl = execctrl_saved; + return PICO_OK; } -void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) { - valid_params_if(PIO, initial_pc < PIO_INSTRUCTION_COUNT); +int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) { + valid_params_if(HARDWARE_PIO, initial_pc < PIO_INSTRUCTION_COUNT); // Halt the machine, set some sensible defaults pio_sm_set_enabled(pio, sm, false); + int rc; if (config) { - pio_sm_set_config(pio, sm, config); + rc = pio_sm_set_config(pio, sm, config); } else { pio_sm_config c = pio_get_default_sm_config(); - pio_sm_set_config(pio, sm, &c); + rc = pio_sm_set_config(pio, sm, &c); } + if (rc) return rc; pio_sm_clear_fifos(pio, sm); @@ -257,6 +317,7 @@ void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) pio_sm_restart(pio, sm); pio_sm_clkdiv_restart(pio, sm); pio_sm_exec(pio, sm, pio_encode_jmp(initial_pc)); + return PICO_OK; } void pio_sm_drain_tx_fifo(PIO pio, uint sm) { @@ -266,3 +327,70 @@ void pio_sm_drain_tx_fifo(PIO pio, uint sm) { pio_sm_exec(pio, sm, instr); } } + +bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset) { + return pio_claim_free_sm_and_add_program_for_gpio_range(program, pio, sm, offset, 0, 0, false); +} + +bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base) { + invalid_params_if(HARDWARE_PIO, (gpio_base + gpio_count) > NUM_BANK0_GPIOS); + +#if !PICO_PIO_USE_GPIO_BASE + // short-circuit some logic when not using GIO_BASE + set_gpio_base = 0; + gpio_count = 0; +#endif + + // note if we gpio_count == 0, we don't care about GPIOs so use a zero mask for what we require + // if gpio_count > 0, then we just set used mask for the ends, since that is all that is checked at the moment + uint32_t required_gpio_ranges; + if (gpio_count) required_gpio_ranges = (1u << (gpio_base >> 4)) | (1u << ((gpio_base + gpio_count - 1) >> 4)); + else required_gpio_ranges = 0; + int passes = set_gpio_base ? 2 : 1; + + for(int pass = 0; pass < passes; pass++) { + int pio_num = NUM_PIOS; + while (pio_num--) { + *pio = pio_get_instance((uint)pio_num); + // We need to claim an SM on the PIO + int8_t sm_index[NUM_PIO_STATE_MACHINES]; + // on second pass, if there is one, we try and claim all the state machines so that we can change the GPIO base + uint num_claimed; + for(num_claimed = 0; num_claimed < (pass ? NUM_PIO_STATE_MACHINES : 1u) ; num_claimed++) { + sm_index[num_claimed] = (int8_t)pio_claim_unused_sm(*pio, false); + if (sm_index[num_claimed] < 0) break; + } + if (num_claimed && (!pass || num_claimed == NUM_PIO_STATE_MACHINES)) { + uint32_t save = hw_claim_lock(); + if (pass) { + pio_set_gpio_base_unsafe(*pio, required_gpio_ranges & 4 ? 16 : 0); + } + int rc = is_gpio_compatible(*pio, required_gpio_ranges) ? PICO_OK : PICO_ERROR_BAD_ALIGNMENT; + if (rc == PICO_OK) rc = find_offset_for_program(*pio, program); + if (rc >= 0) rc = add_program_at_offset(*pio, program, (uint)rc); + if (rc >= 0) { + *sm = (uint) sm_index[0]; + *offset = (uint) rc; + } + hw_claim_unlock(save); + // always un-claim all SMs other than the one we need (array index 0), + // or all of them if we had an error + for (uint i = (rc >= 0); i < num_claimed; i++) { + pio_sm_unclaim(*pio, (uint) sm_index[i]); + } + if (rc >= 0) { + return true; + } + } + } + } + *pio = NULL; + return false; +} + +void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset) { + check_pio_param(pio); + check_sm_param(sm); + pio_remove_program(pio, program, offset); + pio_sm_unclaim(pio, sm); +} diff --git a/src/rp2_common/hardware_pll/BUILD.bazel b/src/rp2_common/hardware_pll/BUILD.bazel index 4f1ab2883..3f3a08aed 100644 --- a/src/rp2_common/hardware_pll/BUILD.bazel +++ b/src/rp2_common/hardware_pll/BUILD.bazel @@ -9,10 +9,10 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/common/pico_base:pico_platform", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform_internal", "//src/rp2_common/hardware_clocks:hardware_clocks_headers", "//src/rp2_common/hardware_resets", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_pll/include/hardware/pll.h b/src/rp2_common/hardware_pll/include/hardware/pll.h index 6b8e14be3..357660a73 100644 --- a/src/rp2_common/hardware_pll/include/hardware/pll.h +++ b/src/rp2_common/hardware_pll/include/hardware/pll.h @@ -31,19 +31,23 @@ typedef pll_hw_t *PLL; #define pll_sys pll_sys_hw #define pll_usb pll_usb_hw -#ifndef PICO_PLL_VCO_MIN_FREQ_KHZ -#ifndef PICO_PLL_VCO_MIN_FREQ_MHZ -#define PICO_PLL_VCO_MIN_FREQ_KHZ (750 * KHZ) +#ifndef PICO_PLL_VCO_MIN_FREQ_HZ +#ifdef PICO_PLL_VCO_MIN_FREQ_MHZ +#define PICO_PLL_VCO_MIN_FREQ_HZ (PICO_PLL_VCO_MIN_FREQ_MHZ * MHZ) +#elif defined(PICO_PLL_VCO_MIN_FREQ_KHZ) +#define PICO_PLL_VCO_MIN_FREQ_HZ (PICO_PLL_VCO_MIN_FREQ_KHZ * KHZ) #else -#define PICO_PLL_VCO_MIN_FREQ_KHZ (PICO_PLL_VCO_MIN_FREQ_MHZ * KHZ) +#define PICO_PLL_VCO_MIN_FREQ_HZ (750 * MHZ) #endif #endif -#ifndef PICO_PLL_VCO_MAX_FREQ_KHZ -#ifndef PICO_PLL_VCO_MAX_FREQ_MHZ -#define PICO_PLL_VCO_MAX_FREQ_KHZ (1600 * KHZ) +#ifndef PICO_PLL_VCO_MAX_FREQ_HZ +#ifdef PICO_PLL_VCO_MAX_FREQ_MHZ +#define PICO_PLL_VCO_MAX_FREQ_HZ (PICO_PLL_VCO_MAX_FREQ_MHZ * MHZ) +#elif defined(PICO_PLL_VCO_MAX_FREQ_KHZ) +#define PICO_PLL_VCO_MAX_FREQ_HZ (PICO_PLL_VCO_MAX_FREQ_KHZ * KHZ) #else -#define PICO_PLL_VCO_MAX_FREQ_KHZ (PICO_PLL_VCO_MAX_FREQ_MHZ * KHZ) +#define PICO_PLL_VCO_MAX_FREQ_HZ (1600 * MHZ) #endif #endif @@ -67,6 +71,17 @@ void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_di */ void pll_deinit(PLL pll); +/** + * \def PLL_RESET_NUM(pll) + * \ingroup hardware_pll + * \hideinitializer + * \brief Returns the \ref reset_num_t used to reset a given PLL instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PLL_RESET_NUM +#define PLL_RESET_NUM(pll) ((pll_usb_hw == (pll)) ? RESET_PLL_USB : RESET_PLL_SYS) +#endif #ifdef __cplusplus } diff --git a/src/rp2_common/hardware_pll/pll.c b/src/rp2_common/hardware_pll/pll.c index 48152b819..5df52e236 100644 --- a/src/rp2_common/hardware_pll/pll.c +++ b/src/rp2_common/hardware_pll/pll.c @@ -11,10 +11,10 @@ /// \tag::pll_init_calculations[] void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) { - uint32_t ref_freq = XOSC_KHZ * KHZ / refdiv; + uint32_t ref_freq = XOSC_HZ / refdiv; // Check vco freq is in an acceptable range - assert(vco_freq >= (PICO_PLL_VCO_MIN_FREQ_KHZ * KHZ) && vco_freq <= (PICO_PLL_VCO_MAX_FREQ_KHZ * KHZ)); + assert(vco_freq >= PICO_PLL_VCO_MIN_FREQ_HZ && vco_freq <= PICO_PLL_VCO_MAX_FREQ_HZ); // What are we multiplying the reference clock by to get the vco freq // (The regs are called div, because you divide the vco output and compare it to the refclk) @@ -47,9 +47,7 @@ void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div return; } - uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS; - reset_block(pll_reset); - unreset_block_wait(pll_reset); + reset_unreset_block_num_wait_blocking(PLL_RESET_NUM(pll)); // Load VCO-related dividers before starting VCO pll->cs = refdiv; diff --git a/src/rp2_common/hardware_powman/BUILD.bazel b/src/rp2_common/hardware_powman/BUILD.bazel new file mode 100644 index 000000000..28350d349 --- /dev/null +++ b/src/rp2_common/hardware_powman/BUILD.bazel @@ -0,0 +1,16 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_powman", + srcs = ["powman.c"], + hdrs = ["include/hardware/powman.h"], + implementation_deps = ["//src/rp2_common/hardware_gpio"], + includes = ["include"], + + # TODO: RP2350 only, but doesn't appear gated in CMake. + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", + ], +) diff --git a/src/rp2_common/hardware_powman/CMakeLists.txt b/src/rp2_common/hardware_powman/CMakeLists.txt new file mode 100644 index 000000000..86534332c --- /dev/null +++ b/src/rp2_common/hardware_powman/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(powman) \ No newline at end of file diff --git a/src/rp2_common/hardware_powman/include/hardware/powman.h b/src/rp2_common/hardware_powman/include/hardware/powman.h new file mode 100644 index 000000000..fce8c14cd --- /dev/null +++ b/src/rp2_common/hardware_powman/include/hardware/powman.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_POWMAN_H +#define _HARDWARE_POWMAN_H + +#include "pico.h" +#include "hardware/structs/powman.h" + +/** \file hardware/powman.h + * \defgroup hardware_powman hardware_powman + * + * \brief Power Management API + * + */ + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN, Enable/disable hardware_powman assertions, type=bool, default=0, group=hardware_powman +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_POWMAN 0 +#endif + +/*! \brief Use the ~32KHz low power oscillator as the powman timer source + * \ingroup hardware_powman + */ +void powman_timer_set_1khz_tick_source_lposc(void); + +/*! \brief Use the low power oscillator (specifying frequency) as the powman timer source + * \ingroup hardware_powman + * \param lposc_freq_hz specify an exact lposc freq to trim it + */ +void powman_timer_set_1khz_tick_source_lposc_with_hz(uint32_t lposc_freq_hz); + +/*! \brief Use the crystal oscillator as the powman timer source + * \ingroup hardware_powman + */ +void powman_timer_set_1khz_tick_source_xosc(void); + +/*! \brief Use the crystal oscillator as the powman timer source + * \ingroup hardware_powman + * \param xosc_freq_hz specify a crystal frequency + */ +void powman_timer_set_1khz_tick_source_xosc_with_hz(uint32_t xosc_freq_hz); + +/*! \brief Use a 1KHz external tick as the powman timer source + * \ingroup hardware_powman + * \param gpio the gpio to use. must be 12, 14, 20, 22 + */ +void powman_timer_set_1khz_tick_source_gpio(uint32_t gpio); + +/*! \brief Use a 1Hz external signal as the powman timer source for seconds only + * \ingroup hardware_powman + * + * Use a 1hz sync signal, such as from a gps for the seconds component of the timer. + * The milliseconds will still come from another configured source such as xosc or lposc + * + * \param gpio the gpio to use. must be 12, 14, 20, 22 + */ +void powman_timer_enable_gpio_1hz_sync(uint32_t gpio); + +/*! \brief Stop using 1Hz external signal as the powman timer source for seconds + * \ingroup hardware_powman + */ +void powman_timer_disable_gpio_1hz_sync(void); + +/*! \brief Returns current time in ms + * \ingroup hardware_powman + */ +uint64_t powman_timer_get_ms(void); + +/*! \brief Set current time in ms + * \ingroup hardware_powman + * + * \param time_ms Current time in ms + */ +void powman_timer_set_ms(uint64_t time_ms); + +/*! \brief Set an alarm at an absolute time in ms + * \ingroup hardware_powman + * + * Note, the timer is stopped and then restarted as part of this function. This only controls the alarm + * if you want to use the alarm to wake up powman then you should use \ref powman_enable_alarm_wakeup_at_ms + * + * \param alarm_time_ms time at which the alarm will fire + */ +void powman_timer_enable_alarm_at_ms(uint64_t alarm_time_ms); + +/*! \brief Disable the alarm + * \ingroup hardware_powman + * + * Once an alarm has fired it must be disabled to stop firing as the alarm + * comparison is alarm = alarm_time >= current_time + */ +void powman_timer_disable_alarm(void); + +/*! \brief hw_set_bits helper function + * \ingroup hardware_powman + * + * \param reg register to set + * \param bits bits of register to set + * Powman needs a password for writes, to prevent accidentally writing to it. + * This function implements hw_set_bits with an appropriate password. + */ +static inline void powman_set_bits(volatile uint32_t *reg, uint32_t bits) { + invalid_params_if(HARDWARE_POWMAN, bits >> 16); + hw_set_bits(reg, POWMAN_PASSWORD_BITS | bits); +} + +/*! \brief hw_clear_bits helper function + * \ingroup hardware_powman + * + * Powman needs a password for writes, to prevent accidentally writing to it. + * This function implements hw_clear_bits with an appropriate password. + * + * \param reg register to clear + * \param bits bits of register to clear + */ +static inline void powman_clear_bits(volatile uint32_t *reg, uint32_t bits) { + invalid_params_if(HARDWARE_POWMAN, bits >> 16); + hw_clear_bits(reg, POWMAN_PASSWORD_BITS | bits); +} + +/*! \brief Determine if the powman timer is running + * \ingroup hardware_powman + */ +static inline bool powman_timer_is_running(void) { + return powman_hw->timer & POWMAN_TIMER_RUN_BITS; +} + +/*! \brief Stop the powman timer + * \ingroup hardware_powman + */ +static inline void powman_timer_stop(void) { + powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_RUN_BITS); +} + +/*! \brief Start the powman timer + * \ingroup hardware_powman + */ +static inline void powman_timer_start(void) { + powman_set_bits(&powman_hw->timer, POWMAN_TIMER_RUN_BITS); +} + +/*! \brief Clears the powman alarm + * \ingroup hardware_powman + * + * Note, the alarm must be disabled (see \ref powman_timer_disable_alarm) before clearing the alarm, as the alarm fires if + * the time is greater than equal to the target, so once the time has passed the alarm will always fire while enabled. + */ +static inline void powman_clear_alarm(void) { + powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_BITS); +} + +/*! \brief Power domains of powman + * \ingroup hardware_powman + */ +enum powman_power_domains { + POWMAN_POWER_DOMAIN_SRAM_BANK1 = 0, ///< bank1 includes the top 256K of sram plus sram 8 and 9 (scratch x and scratch y) + POWMAN_POWER_DOMAIN_SRAM_BANK0 = 1, ///< bank0 is bottom 256K of sSRAM + POWMAN_POWER_DOMAIN_XIP_CACHE = 2, ///< XIP cache is 2x8K instances + POWMAN_POWER_DOMAIN_SWITCHED_CORE = 3, ///< Switched core logic (processors, busfabric, peris etc) + POWMAN_POWER_DOMAIN_COUNT = 4, +}; + +typedef uint32_t powman_power_state; + +/*! \brief Get the current power state + * \ingroup hardware_powman + */ +powman_power_state powman_get_power_state(void); + +/*! \brief Set the power state + * \ingroup hardware_powman + * + * Check the desired state is valid. Powman will go to the state if it is valid and there are no pending power up requests. + * + * Note that if you are turning off the switched core then this function will never return as the processor will have + * been turned off at the end. + * + * \param state the power state to go to + * \returns PICO_OK if the state is valid. Misc PICO_ERRORs are returned if not + */ +int powman_set_power_state(powman_power_state state); + +#define POWMAN_POWER_STATE_NONE 0 + +/*! \brief Helper function modify a powman_power_state to turn a domain on + * \ingroup hardware_powman + * \param orig original state + * \param domain domain to turn on + */ +static inline powman_power_state powman_power_state_with_domain_on(powman_power_state orig, enum powman_power_domains domain) { + invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT); + return orig | (1u << domain); +} + +/*! \brief Helper function modify a powman_power_state to turn a domain off + * \ingroup hardware_powman + * \param orig original state + * \param domain domain to turn off + */ +static inline powman_power_state powman_power_state_with_domain_off(powman_power_state orig, enum powman_power_domains domain) { + invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT); + return orig &= ~(1u << domain); +} + +/*! \brief Helper function to check if a domain is on in a given powman_power_state + * \ingroup hardware_powman + * \param state powman_power_state + * \param domain domain to check is on + */ +static inline bool powman_power_state_is_domain_on(powman_power_state state, enum powman_power_domains domain) { + invalid_params_if(HARDWARE_POWMAN, domain >= POWMAN_POWER_DOMAIN_COUNT); + return state & (1u << domain); +} + +/*! \brief Wake up from an alarm at a given time + * \ingroup hardware_powman + * \param alarm_time_ms time to wake up in ms + */ +void powman_enable_alarm_wakeup_at_ms(uint64_t alarm_time_ms); + +/*! \brief Wake up from a gpio + * \ingroup hardware_powman + * \param gpio_wakeup_num hardware wakeup instance to use (0-3) + * \param gpio gpio to wake up from (0-47) + * \param edge true for edge sensitive, false for level sensitive + * \param high true for active high, false active low + */ +void powman_enable_gpio_wakeup(uint gpio_wakeup_num, uint32_t gpio, bool edge, bool high); + +/*! \brief Disable waking up from alarm + * \ingroup hardware_powman + */ +void powman_disable_alarm_wakeup(void); + +/*! \brief Disable wake up from a gpio + * \ingroup hardware_powman + * \param gpio_wakeup_num hardware wakeup instance to use (0-3) + */ +void powman_disable_gpio_wakeup(uint gpio_wakeup_num); + +/*! \brief Disable all wakeup sources + * \ingroup hardware_powman + */ +void powman_disable_all_wakeups(void); + +/*! \brief Configure sleep state and wakeup state + * \ingroup hardware_powman + * \param sleep_state power state powman will go to when sleeping, used to validate the wakeup state + * \param wakeup_state power state powman will go to when waking up. Note switched core and xip always power up. SRAM bank0 and bank1 can be left powered off + * \returns true if the state is valid, false if not + */ +bool powman_configure_wakeup_state(powman_power_state sleep_state, powman_power_state wakeup_state); + +/*! \brief Ignore wake up when the debugger is attached + * \ingroup hardware_powman + * + * Typically, when a debugger is attached it will assert the pwrupreq signal. OpenOCD does not clear this signal, even when you quit. + * This means once you have attached a debugger powman will never go to sleep. This function lets you ignore the debugger + * pwrupreq which means you can go to sleep with a debugger attached. The debugger will error out if you go to turn off the switch core with it attached, + * as the processors have been powered off. + * + * \param ignored should the debugger power up request be ignored + */ +static inline void powman_set_debug_power_request_ignored(bool ignored) { + if (ignored) + powman_set_bits(&powman_hw->dbg_pwrcfg, 1); + else + powman_clear_bits(&powman_hw->dbg_pwrcfg, 0); +} + +#endif \ No newline at end of file diff --git a/src/rp2_common/hardware_powman/powman.c b/src/rp2_common/hardware_powman/powman.c new file mode 100644 index 000000000..b9c556482 --- /dev/null +++ b/src/rp2_common/hardware_powman/powman.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "pico.h" + +#include "hardware/gpio.h" +#include "hardware/powman.h" + +#ifndef PICO_POWMAN_DEBUG +#define PICO_POWMAN_DEBUG 0 +#endif + +#if PICO_POWMAN_DEBUG +bool powman_debug_printf = false; +void powman_enable_debug_printf(void) { + powman_debug_printf = true; +} +#define powman_debug(format, args...) if (powman_debug_printf) printf(format, ## args) +#else +#define powman_debug(...) +#endif + +static inline void powman_write(volatile uint32_t *reg, uint32_t value) { + // Write needs a password in top 16 bits + invalid_params_if(HARDWARE_POWMAN, value >> 16); + *reg = POWMAN_PASSWORD_BITS | value; +} + +void powman_timer_set_ms(uint64_t time_ms) { + bool was_running = powman_timer_is_running(); + if (was_running) powman_timer_stop(); + powman_write(&powman_hw->set_time_15to0, time_ms & 0xffff); + powman_write(&powman_hw->set_time_31to16, (time_ms >> 16) & 0xffff); + powman_write(&powman_hw->set_time_47to32, (time_ms >> 32) & 0xffff); + powman_write(&powman_hw->set_time_63to48, (time_ms >> 48) & 0xffff); + if (was_running) powman_timer_start(); +} + +uint64_t powman_timer_get_ms(void) { + // Need to make sure that the upper 32 bits of the timer + // don't change, so read that first + uint32_t hi = powman_hw->read_time_upper; + uint32_t lo; + do { + // Read the lower 32 bits + lo = powman_hw->read_time_lower; + // Now read the upper 32 bits again and + // check that it hasn't incremented. If it has loop around + // and read the lower 32 bits again to get an accurate value + uint32_t next_hi = powman_hw->read_time_upper; + if (hi == next_hi) break; + hi = next_hi; + } while (true); + return ((uint64_t) hi << 32u) | lo; +} + +void powman_timer_set_1khz_tick_source_lposc(void) { + powman_timer_set_1khz_tick_source_lposc_with_hz(32768); +} + +void powman_timer_set_1khz_tick_source_lposc_with_hz(uint32_t lposc_freq_hz) { + bool was_running = powman_timer_is_running(); + if (was_running) powman_timer_stop(); + uint32_t lposc_freq_khz = lposc_freq_hz / 1000; + uint32_t lposc_freq_khz_frac16 = (lposc_freq_khz % 1000) * 65536 / 1000; + powman_write(&powman_hw->lposc_freq_khz_int, lposc_freq_khz); + powman_write(&powman_hw->lposc_freq_khz_frac, lposc_freq_khz_frac16); + powman_set_bits(&powman_hw->timer, POWMAN_TIMER_USE_LPOSC_BITS); + if (was_running) { + powman_timer_start(); + while(!(powman_hw->timer & POWMAN_TIMER_USING_LPOSC_BITS)); + } +} + +void powman_timer_set_1khz_tick_source_xosc(void) { + powman_timer_set_1khz_tick_source_xosc_with_hz(XOSC_HZ); +} + +void powman_timer_set_1khz_tick_source_xosc_with_hz(uint32_t xosc_freq_hz) { + bool was_running = powman_timer_is_running(); + if (was_running) powman_timer_stop(); + uint32_t xosc_freq_khz = xosc_freq_hz / 1000; + uint32_t xosc_freq_khz_frac16 = (xosc_freq_khz % 1000) * 65536 / 1000; + powman_write(&powman_hw->xosc_freq_khz_int, xosc_freq_khz); + powman_write(&powman_hw->xosc_freq_khz_frac, xosc_freq_khz_frac16); + powman_set_bits(&powman_hw->timer, POWMAN_TIMER_USE_XOSC_BITS); + if (was_running) { + powman_timer_start(); + while(!(powman_hw->timer & POWMAN_TIMER_USING_XOSC_BITS)); + } +} + +static void powman_timer_use_gpio(uint32_t gpio, uint32_t use, uint32_t using) { + bool was_running = powman_timer_is_running(); + if (was_running) powman_timer_stop(); + invalid_params_if(HARDWARE_POWMAN, !((gpio == 12) || (gpio == 14) || (gpio == 20) || (gpio == 22))); + gpio_set_input_enabled(gpio, true); + powman_write(&powman_hw->ext_time_ref, gpio); + powman_set_bits(&powman_hw->timer, use); + if (was_running) { + powman_timer_start(); + while(!(powman_hw->timer & using)); + } +} + +void powman_timer_set_1khz_tick_source_gpio(uint32_t gpio) { + // todo check if we're using the GPIO setup already? + powman_timer_use_gpio(gpio, POWMAN_TIMER_USE_GPIO_1KHZ_BITS, POWMAN_TIMER_USING_GPIO_1KHZ_BITS); +} + +void powman_timer_enable_gpio_1hz_sync(uint32_t gpio) { + // todo check if we're using the GPIO setup already? + powman_timer_use_gpio(gpio, POWMAN_TIMER_USE_GPIO_1HZ_BITS, POWMAN_TIMER_USING_GPIO_1HZ_BITS); +} + +void powman_timer_disable_gpio_1hz_sync(void) { + powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_USE_GPIO_1HZ_BITS); +} + +powman_power_state powman_get_power_state(void) { + uint32_t state_reg = powman_hw->state & POWMAN_STATE_CURRENT_BITS; + // todo we should have hardware/regs/powman.h values for these + static_assert(POWMAN_POWER_DOMAIN_SRAM_BANK1 == 0, ""); + static_assert(POWMAN_POWER_DOMAIN_SRAM_BANK0 == 1, ""); + static_assert(POWMAN_POWER_DOMAIN_XIP_CACHE == 2, ""); + static_assert(POWMAN_POWER_DOMAIN_SWITCHED_CORE == 3, ""); + static_assert(POWMAN_STATE_CURRENT_BITS == 0xf, ""); + return (powman_power_state) state_reg; +} + +// TODO: Should this fail to go to sleep if there is no wakeup alarm +int powman_set_power_state(powman_power_state state) { + // Clear req ignored in case it has been set + powman_clear_bits(&powman_hw->state, POWMAN_STATE_REQ_IGNORED_BITS); + powman_debug("powman: Requesting state %x\n", state); + powman_write(&powman_hw->state, (~state << POWMAN_STATE_REQ_LSB) & POWMAN_STATE_REQ_BITS); + + // Has it been ignored? + if (powman_hw->state & POWMAN_STATE_REQ_IGNORED_BITS) { + powman_debug("State req ignored because of a pending pwrup req: %"PRIx32"\n", powman_hw->current_pwrup_req); + return PICO_ERROR_PRECONDITION_NOT_MET; + } + + bool state_valid = (powman_hw->state & POWMAN_STATE_BAD_SW_REQ_BITS) == 0; + if (!state_valid) { + powman_debug("powman: Requested state invalid\n"); + return PICO_ERROR_INVALID_ARG; + } else { + powman_debug("powman: Requested state valid\n"); + } + if (!powman_power_state_is_domain_on(state, POWMAN_POWER_DOMAIN_SWITCHED_CORE)) { + // If we are turning off switched core then POWMAN_STATE_WAITING_BITS will be + // set because we are waiting for proc to go to sleep, so return ok and then the proc + // can go to sleep + + // Note if the powerdown is being blocked by a pending pwrup request we will break out of this and return a failure + + // Clk pow is slow so can take a few clk_pow cycles for waiting to turn up + for (int i = 0; i < 100; i++) { + if (powman_hw->state & POWMAN_STATE_WAITING_BITS) { + return PICO_OK; + } + } + + // If it hasn't turned up then false + powman_debug("powman: STATE_WAITING hasn't turned up\n"); + return PICO_ERROR_TIMEOUT; + } + // Wait while the state is changing then return true as we will be in the new state + powman_debug("powman: waiting for state change\n"); + while(powman_hw->state & POWMAN_STATE_CHANGING_BITS) tight_loop_contents(); + powman_debug("powman: state changed to %x\n", state); + return PICO_OK; +} + +bool powman_configure_wakeup_state(powman_power_state sleep_state, powman_power_state wakeup_state) { + // When powman wakes up it can keep the state of the sram0 and sram1 banks. Note, it can't + // explicitly + bool valid = powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_XIP_CACHE); + valid &= powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SWITCHED_CORE); + valid &= powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK0) == + powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SRAM_BANK0); + valid &= powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK1) == + powman_power_state_is_domain_on(wakeup_state, POWMAN_POWER_DOMAIN_SRAM_BANK1); + if (valid) { + powman_clear_bits(&powman_hw->seq_cfg, POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS | POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS); + uint32_t seq_cfg_set = 0; + if (!powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK0)) seq_cfg_set |= POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS; + if (!powman_power_state_is_domain_on(sleep_state, POWMAN_POWER_DOMAIN_SRAM_BANK1)) seq_cfg_set |= POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS; + powman_set_bits(&powman_hw->seq_cfg, seq_cfg_set); + } + return valid; +} + +void powman_timer_enable_alarm_at_ms(uint64_t alarm_time_ms) { + powman_set_bits(&powman_hw->inte, POWMAN_INTE_TIMER_BITS); + powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS); + // Alarm must be disabled to set the alarm time + powman_write(&powman_hw->alarm_time_15to0, alarm_time_ms & 0xffff); + powman_write(&powman_hw->alarm_time_31to16, (alarm_time_ms >> 16) & 0xffff); + powman_write(&powman_hw->alarm_time_47to32, (alarm_time_ms >> 32) & 0xffff); + powman_write(&powman_hw->alarm_time_63to48, (alarm_time_ms >> 48) & 0xffff); + powman_clear_alarm(); + // TODO: Assuming pwrup on alarm has no bad side effects if already powered up + powman_set_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS); +} + +void powman_timer_disable_alarm(void) { + powman_clear_bits(&powman_hw->inte, POWMAN_INTE_TIMER_BITS); + powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_ALARM_ENAB_BITS); +} + +void powman_enable_alarm_wakeup_at_ms(uint64_t alarm_time_ms) { + powman_timer_enable_alarm_at_ms(alarm_time_ms); + powman_set_bits(&powman_hw->timer, POWMAN_TIMER_PWRUP_ON_ALARM_BITS); +} + +void powman_disable_alarm_wakeup(void) { + powman_timer_disable_alarm(); + powman_clear_bits(&powman_hw->timer, POWMAN_TIMER_PWRUP_ON_ALARM_BITS); +} + +void powman_enable_gpio_wakeup(uint gpio_wakeup_num, uint32_t gpio, bool edge, bool high) { + invalid_params_if(HARDWARE_POWMAN, gpio_wakeup_num >= count_of(powman_hw->pwrup)); + + // Need to make sure pad is input enabled + gpio_set_input_enabled(gpio, true); + + // Set up gpio hardware for what we want + uint32_t pwrup = (edge ? POWMAN_PWRUP0_MODE_VALUE_EDGE : POWMAN_PWRUP0_MODE_VALUE_LEVEL) << POWMAN_PWRUP0_MODE_LSB; + pwrup |= (high ? POWMAN_PWRUP0_DIRECTION_BITS : 0); + pwrup |= gpio << POWMAN_PWRUP0_SOURCE_LSB; + powman_write(&powman_hw->pwrup[gpio_wakeup_num], pwrup); + + // Clear the status bit in case an edge is already latched + powman_clear_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_STATUS_BITS); + + // Important to enable it separately to allow the gpio to change + powman_set_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_ENABLE_BITS); +} + +void powman_disable_gpio_wakeup(uint gpio_wakeup_num) { + invalid_params_if(HARDWARE_POWMAN, gpio_wakeup_num >= count_of(powman_hw->pwrup)); + powman_clear_bits(&powman_hw->pwrup[gpio_wakeup_num], POWMAN_PWRUP0_ENABLE_BITS); +} + +void powman_disable_all_wakeups(void) { + for (uint i = 0; i < count_of(powman_hw->pwrup); i++) { + powman_disable_gpio_wakeup(i); + } + powman_disable_alarm_wakeup(); +} diff --git a/src/rp2_common/hardware_pwm/BUILD.bazel b/src/rp2_common/hardware_pwm/BUILD.bazel index 9797d60c7..c5c5cd408 100644 --- a/src/rp2_common/hardware_pwm/BUILD.bazel +++ b/src/rp2_common/hardware_pwm/BUILD.bazel @@ -8,8 +8,8 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", ], ) diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h index 50569ee3e..d394c7215 100644 --- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h +++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h @@ -10,14 +10,19 @@ #include "pico.h" #include "hardware/structs/pwm.h" #include "hardware/regs/dreq.h" +#include "hardware/regs/intctrl.h" #ifdef __cplusplus extern "C" { #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hardware_pwm -#ifndef PARAM_ASSERTIONS_ENABLED_PWM -#define PARAM_ASSERTIONS_ENABLED_PWM 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM, Enable/disable assertions in the hardware_pwm module, type=bool, default=0, group=hardware_pwm +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM +#ifdef PARAM_ASSERTIONS_ENABLED_PWM // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM PARAM_ASSERTIONS_ENABLED_PWM +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PWM 0 +#endif #endif /** \file hardware/pwm.h @@ -25,8 +30,8 @@ extern "C" { * * \brief Hardware Pulse Width Modulation (PWM) API * - * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or - * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable + * The RP2040 PWM block has 8 identical slices, the RP2350 has 12. Each slice can drive two PWM output signals, or + * measure the frequency or duty cycle of an input signal. This gives a total of up to 16/24 controllable * PWM outputs. All 30 GPIOs can be driven by the PWM block. * * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a @@ -51,7 +56,7 @@ enum pwm_clkdiv_mode PWM_DIV_FREE_RUNNING = 0, ///< Free-running counting at rate dictated by fractional divider PWM_DIV_B_HIGH = 1, ///< Fractional divider is gated by the PWM B pin PWM_DIV_B_RISING = 2, ///< Fractional divider advances with each rising edge of the PWM B pin - PWM_DIV_B_FALLING = 3 ///< Fractional divider advances with each falling edge of the PWM B pin + PWM_DIV_B_FALLING = 3 ///< Fractional divider advances with each falling edge of the PWM B pin }; enum pwm_chan @@ -66,8 +71,40 @@ typedef struct { uint32_t top; } pwm_config; +/** + * \def PWM_DREQ_NUM(slice_num) + * \ingroup hardware_pwm + * \hideinitializer + * \brief Returns the \ref dreq_num_t used for pacing DMA transfers for a given PWM slice + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PWM_DREQ_NUM +static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, ""); +static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, ""); +#define PWM_DREQ_NUM(slice_num) (DREQ_PWM_WRAP0 + (slice_num)) +#endif + +/** + * \def PWM_GPIO_SLICE_NUM(gpio) + * \ingroup hardware_pwm + * \hideinitializer + * \brief Returns the PWM slice number for a given GPIO number + */ +#ifndef PWM_GPIO_SLICE_NUM +#define PWM_GPIO_SLICE_NUM(gpio) ({ \ + uint slice_num; \ + if ((gpio) < 32) { \ + slice_num = ((gpio) >> 1u) & 7u; \ + } else { \ + slice_num = 8u + (((gpio) >> 1u) & 3u); \ + } \ + slice_num; \ +}) +#endif + static inline void check_slice_num_param(__unused uint slice_num) { - valid_params_if(PWM, slice_num < NUM_PWM_SLICES); + valid_params_if(HARDWARE_PWM, slice_num < NUM_PWM_SLICES); } /** \brief Determine the PWM slice that is attached to the specified GPIO @@ -76,8 +113,8 @@ static inline void check_slice_num_param(__unused uint slice_num) { * \return The PWM slice number that controls the specified GPIO. */ static inline uint pwm_gpio_to_slice_num(uint gpio) { - valid_params_if(PWM, gpio < NUM_BANK0_GPIOS); - return (gpio >> 1u) & 7u; + valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS); + return PWM_GPIO_SLICE_NUM(gpio); } /** \brief Determine the PWM channel that is attached to the specified GPIO. @@ -88,7 +125,7 @@ static inline uint pwm_gpio_to_slice_num(uint gpio) { * \return The PWM channel that controls the specified GPIO. */ static inline uint pwm_gpio_to_channel(uint gpio) { - valid_params_if(PWM, gpio < NUM_BANK0_GPIOS); + valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS); return gpio & 1u; } @@ -117,7 +154,7 @@ static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correc * before passing them on to the PWM counter. */ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) { - valid_params_if(PWM, div >= 1.f && div < 256.f); + valid_params_if(HARDWARE_PWM, div >= 1.f && div < 256.f); c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB)); } @@ -133,8 +170,8 @@ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) { * before passing them on to the PWM counter. */ static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t fract) { - valid_params_if(PWM, integer >= 1); - valid_params_if(PWM, fract < 16); + valid_params_if(HARDWARE_PWM, integer >= 1); + valid_params_if(HARDWARE_PWM, fract < 16); c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB); } @@ -149,7 +186,7 @@ static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer * before passing them on to the PWM counter. */ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { - valid_params_if(PWM, div >= 1 && div < 256); + valid_params_if(HARDWARE_PWM, div >= 1 && div < 256); pwm_config_set_clkdiv_int_frac(c, (uint8_t)div, 0); } @@ -164,7 +201,7 @@ static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) { * high level, rising edge or falling edge of the B pin input. */ static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) { - valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING || + valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING || mode == PWM_DIV_B_RISING || mode == PWM_DIV_B_HIGH || mode == PWM_DIV_B_FALLING); @@ -319,7 +356,7 @@ static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_ * \param level PWM level for this GPIO */ static inline void pwm_set_gpio_level(uint gpio, uint16_t level) { - valid_params_if(PWM, gpio < NUM_BANK0_GPIOS); + valid_params_if(HARDWARE_PWM, gpio < NUM_BANK0_GPIOS); pwm_set_chan_level(pwm_gpio_to_slice_num(gpio), pwm_gpio_to_channel(gpio), level); } @@ -395,8 +432,8 @@ static inline void pwm_retard_count(uint slice_num) { */ static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) { check_slice_num_param(slice_num); - valid_params_if(PWM, integer >= 1); - valid_params_if(PWM, fract < 16); + valid_params_if(HARDWARE_PWM, integer >= 1); + valid_params_if(HARDWARE_PWM, fract < 16); pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB); } @@ -410,7 +447,7 @@ static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint */ static inline void pwm_set_clkdiv(uint slice_num, float divider) { check_slice_num_param(slice_num); - valid_params_if(PWM, divider >= 1.f && divider < 256.f); + valid_params_if(HARDWARE_PWM, divider >= 1.f && divider < 256.f); uint8_t i = (uint8_t)divider; uint8_t f = (uint8_t)((divider - i) * (0x01 << 4)); pwm_set_clkdiv_int_frac(slice_num, i, f); @@ -438,7 +475,7 @@ static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) { */ static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) { check_slice_num_param(slice_num); - valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING || + valid_params_if(HARDWARE_PWM, mode == PWM_DIV_FREE_RUNNING || mode == PWM_DIV_B_RISING || mode == PWM_DIV_B_HIGH || mode == PWM_DIV_B_FALLING); @@ -499,11 +536,40 @@ static inline void pwm_set_mask_enabled(uint32_t mask) { pwm_hw->en = mask; } -/*! \brief Enable PWM instance interrupt +/** + * \def PWM_DEFAULT_IRQ_NUM() + * \ingroup hardware_pwm + * \hideinitializer + * \brief Returns the \ref irq_num_t for the default PWM IRQ. + * + * \if rp2040_specific + * On RP2040, there is only one PWM irq: PWM_IRQ_WRAP + * \endif + * + * \if rp2350_specific + * On RP2350 this returns to PWM_IRQ_WRAP0 + * \endif + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PWM_DEFAULT_IRQ_NUM +#if PICO_RP2040 +#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP +#else +#define PWM_DEFAULT_IRQ_NUM() PWM_IRQ_WRAP_0 +// backwards compatibility with RP2040 +#define PWM_IRQ_WRAP PWM_IRQ_WRAP_0 +#define isr_pwm_wrap isr_pwm_wrap_0 +#endif +#endif + +/*! \brief Enable PWM instance interrupt via the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) * \ingroup hardware_pwm * * Used to enable a single PWM instance interrupt. * + * Note there is only one PWM_IRQ_WRAP on RP2040. + * * \param slice_num PWM block to enable/disable * \param enabled true to enable, false to disable */ @@ -516,21 +582,138 @@ static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) { } } -/*! \brief Enable multiple PWM instance interrupts +/*! \brief Enable PWM instance interrupt via PWM_IRQ_WRAP_0 + * \ingroup hardware_pwm + * + * Used to enable a single PWM instance interrupt. + * + * \param slice_num PWM block to enable/disable + * \param enabled true to enable, false to disable + */ +static inline void pwm_set_irq0_enabled(uint slice_num, bool enabled) { + // irq0 always corresponds to the default IRQ + pwm_set_irq_enabled(slice_num, enabled); +} + +#if NUM_PWM_IRQS > 1 +/*! \brief Enable PWM instance interrupt via PWM_IRQ_WRAP_1 + * \ingroup hardware_pwm + * + * Used to enable a single PWM instance interrupt. + * + * \param slice_num PWM block to enable/disable + * \param enabled true to enable, false to disable + */ +static inline void pwm_set_irq1_enabled(uint slice_num, bool enabled) { + check_slice_num_param(slice_num); + if (enabled) { + hw_set_bits(&pwm_hw->inte1, 1u << slice_num); + } else { + hw_clear_bits(&pwm_hw->inte1, 1u << slice_num); + } +} +#endif + +/*! \brief Enable PWM instance interrupt via either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 + * \ingroup hardware_pwm + * + * Used to enable a single PWM instance interrupt. + * + * Note there is only one PWM_IRQ_WRAP on RP2040. + * + * \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 + * \param slice_num PWM block to enable/disable + * \param enabled true to enable, false to disable + */ +static inline void pwm_irqn_set_slice_enabled(uint irq_index, uint slice_num, bool enabled) { + check_slice_num_param(slice_num); + invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS); + check_slice_num_param(slice_num); + if (enabled) { + hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num); + } else { + hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num); + } +} + +/*! \brief Enable multiple PWM instance interrupts via the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) * \ingroup hardware_pwm * * Use this to enable multiple PWM interrupts at once. * + * Note there is only one PWM_IRQ_WRAP on RP2040. + * * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. * \param enabled true to enable, false to disable */ static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) { - valid_params_if(PWM, slice_mask < 256); + valid_params_if(HARDWARE_PWM, slice_mask < 256); +#if PICO_RP2040 if (enabled) { hw_set_bits(&pwm_hw->inte, slice_mask); } else { hw_clear_bits(&pwm_hw->inte, slice_mask); } +#else + static_assert(PWM_IRQ_WRAP_1 == PWM_IRQ_WRAP_0 + 1); + uint irq_index = PWM_DEFAULT_IRQ_NUM() - PWM_IRQ_WRAP_0; + if (enabled) { + hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); + } else { + hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); + } +#endif +} + +/*! \brief Enable multiple PWM instance interrupts via PWM_IRQ_WRAP_0 + * \ingroup hardware_pwm + * + * Use this to enable multiple PWM interrupts at once. + * + * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. + * \param enabled true to enable, false to disable + */ +static inline void pwm_set_irq0_mask_enabled(uint32_t slice_mask, bool enabled) { + // default irq is irq0 + pwm_set_irq_mask_enabled(slice_mask, enabled); +} + +#if NUM_PWM_IRQS > 1 +/*! \brief Enable multiple PWM instance interrupts via PWM_IRQ_WRAP_1 + * \ingroup hardware_pwm + * + * Use this to enable multiple PWM interrupts at once. + * + * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. + * \param enabled true to enable, false to disable + */ +static inline void pwm_set_irq1_mask_enabled(uint32_t slice_mask, bool enabled) { + if (enabled) { + hw_set_bits(&pwm_hw->inte1, slice_mask); + } else { + hw_clear_bits(&pwm_hw->inte1, slice_mask); + } +} +#endif + +/*! \brief Enable PWM instance interrupts via either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 +* \ingroup hardware_pwm +* +* Used to enable a single PWM instance interrupt. +* +* Note there is only one PWM_IRQ_WRAP on RP2040. +* +* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 +* \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc. +* \param enabled true to enable, false to disable +*/ +static inline void pwm_irqn_set_slice_mask_enabled(uint irq_index, uint slice_mask, bool enabled) { + invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS); + if (enabled) { + hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); + } else { + hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); + } } /*! \brief Clear a single PWM channel interrupt @@ -542,7 +725,7 @@ static inline void pwm_clear_irq(uint slice_num) { pwm_hw->intr = 1u << slice_num; } -/*! \brief Get PWM interrupt status, raw +/*! \brief Get PWM interrupt status, raw for the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) * \ingroup hardware_pwm * * \return Bitmask of all PWM interrupts currently set @@ -551,7 +734,38 @@ static inline uint32_t pwm_get_irq_status_mask(void) { return pwm_hw->ints; } -/*! \brief Force PWM interrupt +/*! \brief Get PWM interrupt status, raw for the PWM_IRQ_WRAP_0 + * \ingroup hardware_pwm + * + * \return Bitmask of all PWM interrupts currently set + */ +static inline uint32_t pwm_get_irq0_status_mask(void) { + return pwm_get_irq_status_mask(); +} + +#if NUM_PWM_IRQS > 1 +/*! \brief Get PWM interrupt status, raw for the PWM_IRQ_WRAP_1 + * \ingroup hardware_pwm + * + * \return Bitmask of all PWM interrupts currently set + */ +static inline uint32_t pwm_get_irq1_status_mask(void) { + return pwm_hw->ints1; +} +#endif + +/*! \brief Get PWM interrupt status, raw for either PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 + * \ingroup hardware_pwm + * +* \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 + * \return Bitmask of all PWM interrupts currently set + */ +static inline uint32_t pwm_irqn_get_status_mask(uint irq_index) { + invalid_params_if(HARDWARE_PWM, irq_index >= NUM_DMA_IRQS); + return pwm_hw->irq_ctrl[irq_index].ints; +} + +/*! \brief Force PWM interrupt for the default PWM IRQ (PWM_IRQ_WRAP_0 on RP2350) * \ingroup hardware_pwm * * \param slice_num PWM slice number @@ -560,16 +774,45 @@ static inline void pwm_force_irq(uint slice_num) { pwm_hw->intf = 1u << slice_num; } +/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0 + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + */ +static inline void pwm_force_irq0(uint slice_num) { + pwm_force_irq(slice_num); +} + +#if NUM_PWM_IRQS > 1 +/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0 + * \ingroup hardware_pwm + * + * \param slice_num PWM slice number + */ +static inline void pwm_force_irq1(uint slice_num) { + pwm_hw->intf1 = 1u << slice_num; +} +#endif + +/*! \brief Force PWM interrupt via PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 + * \ingroup hardware_pwm + * + * \param irq_index the IRQ index; either 0 or 1 for PWM_IRQ_WRAP_0 or PWM_IRQ_WRAP_1 + * \param slice_num PWM slice number + */ +static inline void pwm_irqn_force(uint irq_index, uint slice_num) { + invalid_params_if(HARDWARE_PWM, irq_index >= NUM_PWM_IRQS); + pwm_hw->irq_ctrl[irq_index].intf = 1u << slice_num; +} + /*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice * \ingroup hardware_pwm * * \param slice_num PWM slice number */ static inline uint pwm_get_dreq(uint slice_num) { - static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, ""); - static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, ""); check_slice_num_param(slice_num); - return DREQ_PWM_WRAP0 + slice_num; + return PWM_DREQ_NUM(slice_num); } #ifdef __cplusplus diff --git a/src/rp2_common/hardware_rcp/BUILD.bazel b/src/rp2_common/hardware_rcp/BUILD.bazel new file mode 100644 index 000000000..750ae819e --- /dev/null +++ b/src/rp2_common/hardware_rcp/BUILD.bazel @@ -0,0 +1,11 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_rcp", + hdrs = ["include/hardware/rcp.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = ["//src/rp2_common:pico_platform"], +) diff --git a/src/rp2_common/hardware_rcp/CMakeLists.txt b/src/rp2_common/hardware_rcp/CMakeLists.txt new file mode 100644 index 000000000..eeeace5f2 --- /dev/null +++ b/src/rp2_common/hardware_rcp/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_headers_only_target(rcp) diff --git a/src/rp2_common/hardware_rcp/include/hardware/rcp.h b/src/rp2_common/hardware_rcp/include/hardware/rcp.h new file mode 100644 index 000000000..b75f182d9 --- /dev/null +++ b/src/rp2_common/hardware_rcp/include/hardware/rcp.h @@ -0,0 +1,1005 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_RCP_H +#define _PICO_RCP_H + +#include "pico.h" + +/** \file hardware/rcp.h + * \defgroup hardware_rcp hardware_rcp + * \brief Inline functions and assembly macros for the Redundancy Coprocessor + */ + +// ---------------------------------------------------------------------------- +// RCP instructions (this header is Arm-only) +#if defined(PICO_RP2350) && !defined(__riscv) + +#define RCP_MASK_TRUE _u(0xa500a500) +#define RCP_MASK_FALSE _u(0x00c300c3) +#define RCP_MASK_INTXOR _u(0x96009600) + +// ---------------------------------------------------------------------------- +// Macros and inline functions for use in C files +#ifndef __ASSEMBLER__ + +#define __rcpinline __force_inline + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __riscv // should never do an rcp_asm in risc-v code +#if __ARM_ARCH_8M_MAIN__ +#define rcp_asm pico_default_asm_volatile +#elif __ARM_ARCH_8M_BASE__ +#define rcp_asm(...) ({pico_default_asm_volatile(".cpu cortex-m33\n" __VA_ARGS__); pico_default_asm_volatile(".cpu cortex-m23"); }) +#elif __ARM_ARCH_6M__ +#define rcp_asm(...) ({pico_default_asm_volatile(".cpu cortex-m33\n" __VA_ARGS__); pico_default_asm_volatile(".cpu cortex-m0plus"); }) +#else +#error unknown ARM architecture +#endif + +// Each macro has a default version (e.g. rcp_salt_core0) and a no-delay version +// (e.g. rcp_salt_core0_nodelay). The default version adds an up to 127-cycle +// pseudorandom delay on each coprocessor instruction, whereas the no-delay version +// does not have this delay. The difference in the generated code is whether an MCR +// (e.g.) or MCR2 opcode is emitted. + +// ---------------------------------------------------------------------------- +// RCP Canary instructions + +// Initialise 64-bit salt value for core 0 +static __rcpinline void rcp_salt_core0(uint64_t salt) { + rcp_asm ( + "mcrr p7, #8, %0, %1, c0\n" + : : "r" (salt & 0xffffffffu), "r" (salt >> 32) + ); +} + +static __rcpinline void rcp_salt_core0_nodelay(uint64_t salt) { + rcp_asm ( + "mcrr2 p7, #8, %0, %1, c0\n" + : : "r" (salt & 0xffffffffu), "r" (salt >> 32) + ); +} + +// Initialise 64-bit salt value for core 1 +static __rcpinline void rcp_salt_core1(uint64_t salt) { + rcp_asm ( + "mcrr p7, #8, %0, %1, c1\n" + : : "r" (salt & 0xffffffffu), "r" (salt >> 32) + ); +} + +static __rcpinline void rcp_salt_core1_nodelay(uint64_t salt) { + rcp_asm ( + "mcrr2 p7, #8, %0, %1, c1\n" + : : "r" (salt & 0xffffffffu), "r" (salt >> 32) + ); +} + +// Get a 32-bit canary value. `tag` must be a constant expression. +#define rcp_canary_get(tag) ({ \ + uint32_t __canary_u32; \ + rcp_asm ( \ + "mrc p7, #0, %0, c%c1, c%c2, #1\n" \ + : "=r" (__canary_u32) \ + : "i" ((tag >> 4) & 0xf), "i" (tag & 0xf) \ + ); \ + __canary_u32; \ +}) + +#define rcp_canary_get_nodelay(tag) ({ \ + uint32_t __canary_u32; \ + rcp_asm ( \ + "mrc2 p7, #0, %0, c%c1, c%c2, #1\n" \ + : "=r" (__canary_u32) \ + : "i" (((tag) >> 4) & 0xf), "i" ((tag) & 0xf) \ + ); \ + __canary_u32; \ +}) + +// Assert that canary matches result of rcp_canary_get with the same tags: +#define rcp_canary_check(tag, canary) ({ \ + rcp_asm ( \ + "mcr p7, #0, %0, c%c1, c%c2, #1\n" \ + : : "r" (canary), \ + "i" (((tag) >> 4) & 0xf), "i" ((tag) & 0xf) \ + ); \ +}) + +#define rcp_canary_check_nodelay(tag, canary) ({ \ + rcp_asm ( \ + "mcr2 p7, #0, %0, c%c1, c%c2, #1\n" \ + : : "r" (canary), \ + "i" (((tag) >> 4) & 0xf), "i" ((tag) & 0xf) \ + ); \ +}) + +// Return true/false bit pattern for whether the salt for this core has been +// initialised. (Invoking with Rt=0xf will set the Arm N flag if initialised.) +// If the salt has not been initialised then any operation other than +// initialising the salt or checking the canary status is a hard error. +static __rcpinline uint32_t rcp_canary_status(void) { + uint32_t ret; + rcp_asm ("mrc p7, #1, %0, c0, c0, #0\n" : "=r" (ret)); + return ret; +} + +static __rcpinline uint32_t rcp_canary_status_nodelay(void) { + uint32_t ret; + rcp_asm ("mrc2 p7, #1, %0, c0, c0, #0\n" : "=r" (ret)); + return ret; +} + +// ---------------------------------------------------------------------------- +// RCP Boolean instructions + +// Assert b is a valid boolean (0xa500a500u or 0x00c300c3u) +static __rcpinline void rcp_bvalid(uint32_t b) { + rcp_asm ("mcr p7, #1, %0, c0, c0, #0\n" : : "r" (b)); +} + +static __rcpinline void rcp_bvalid_nodelay(uint32_t b) { + rcp_asm ("mcr2 p7, #1, %0, c0, c0, #0\n" : : "r" (b)); +} + +// Assert b is true (0xa500a500u) +static __rcpinline void rcp_btrue(uint32_t b) { + rcp_asm ("mcr p7, #2, %0, c0, c0, #0\n" : : "r" (b)); +} + +static __rcpinline void rcp_btrue_nodelay(uint32_t b) { + rcp_asm ("mcr2 p7, #2, %0, c0, c0, #0\n" : : "r" (b)); +} + +// Assert b is false (0x00c300c3u) +static __rcpinline void rcp_bfalse(uint32_t b) { + rcp_asm ("mcr p7, #3, %0, c0, c0, #1\n" : : "r" (b)); +} + +static __rcpinline void rcp_bfalse_nodelay(uint32_t b) { + rcp_asm ("mcr2 p7, #3, %0, c0, c0, #1\n" : : "r" (b)); +} + +// Assert b0 and b1 are both valid booleans +static __rcpinline void rcp_b2valid(uint32_t b0, uint32_t b1) { + rcp_asm ("mcrr p7, #0, %0, %1, c8\n" : : "r" (b0), "r" (b1)); +} + +static __rcpinline void rcp_b2valid_nodelay(uint32_t b0, uint32_t b1) { + rcp_asm ("mcrr2 p7, #0, %0, %1, c8\n" : : "r" (b0), "r" (b1)); +} + +// Assert b0 and b1 are both true +static __rcpinline void rcp_b2and(uint32_t b0, uint32_t b1) { + rcp_asm ("mcrr p7, #1, %0, %1, c0\n" : : "r" (b0), "r" (b1)); +} + +static __rcpinline void rcp_b2and_nodelay(uint32_t b0, uint32_t b1) { + rcp_asm ("mcrr2 p7, #1, %0, %1, c0\n" : : "r" (b0), "r" (b1)); +} + +// Assert b0 and b1 are valid, and at least one is true +static __rcpinline void rcp_b2or(uint32_t b0, uint32_t b1) { + rcp_asm ("mcrr p7, #2, %0, %1, c0\n" : : "r" (b0), "r" (b1)); +} + +static __rcpinline void rcp_b2or_nodelay(uint32_t b0, uint32_t b1) { + rcp_asm ("mcrr2 p7, #2, %0, %1, c0\n" : : "r" (b0), "r" (b1)); +} + +// Assert (b ^ mask) is a valid boolean +static __rcpinline void rcp_bxorvalid(uint32_t b, uint32_t mask) { + rcp_asm ("mcrr p7, #3, %0, %1, c8\n" : : "r" (b), "r" (mask)); +} + +static __rcpinline void rcp_bxorvalid_nodelay(uint32_t b, uint32_t mask) { + rcp_asm ("mcrr2 p7, #3, %0, %1, c8\n" : : "r" (b), "r" (mask)); +} + +// Assert (b ^ mask) is true +static __rcpinline void rcp_bxortrue(uint32_t b, uint32_t mask) { + rcp_asm ("mcrr p7, #4, %0, %1, c0\n" : : "r" (b), "r" (mask)); +} + +static __rcpinline void rcp_bxortrue_nodelay(uint32_t b, uint32_t mask) { + rcp_asm ("mcrr2 p7, #4, %0, %1, c0\n" : : "r" (b), "r" (mask)); +} + +// Assert (b ^ mask) is false +static __rcpinline void rcp_bxorfalse(uint32_t b, uint32_t mask) { + rcp_asm ("mcrr p7, #5, %0, %1, c8\n" : : "r" (b), "r" (mask)); +} + +static __rcpinline void rcp_bxorfalse_nodelay(uint32_t b, uint32_t mask) { + rcp_asm ("mcrr2 p7, #5, %0, %1, c8\n" : : "r" (b), "r" (mask)); +} + +// ---------------------------------------------------------------------------- +// RCP Integer instructions + +// Assert (x ^ parity) == 0x96009600u +static __rcpinline void rcp_ivalid(uint32_t x, uint32_t parity) { + rcp_asm ("mcrr p7, #6, %0, %1, c8\n" : : "r" (x), "r" (parity)); +} + +static __rcpinline void rcp_ivalid_nodelay(uint32_t x, uint32_t parity) { + rcp_asm ("mcrr2 p7, #6, %0, %1, c8\n" : : "r" (x), "r" (parity)); +} + +// Assert x == y +static __rcpinline void rcp_iequal(uint32_t x, uint32_t y) { + rcp_asm ("mcrr p7, #7, %0, %1, c0\n" : : "r" (x), "r" (y)); +} + +static __rcpinline void rcp_iequal_nodelay(uint32_t x, uint32_t y) { + rcp_asm ("mcrr2 p7, #7, %0, %1, c0\n" : : "r" (x), "r" (y)); +} + +// ---------------------------------------------------------------------------- +// RCP Random instructions + +// Return a random 8-bit value generated from the upper 24 bits of the 64-bit +// salt value. This is the same PRNG used for random delay values. +static __rcpinline uint8_t rcp_random_byte(void) { + uint8_t ret; + rcp_asm ("mrc2 p7, #2, %0, c0, c0, #0\n" : "=r" (ret)); + return ret; +} + +// Note neither version of this has delay, since the PRNG for the random delay +// is the same as the one read by this MRC instruction (and it's only stepped +// once). +static __rcpinline uint8_t rcp_random_byte_nodelay(void) { + uint8_t ret; + rcp_asm ("mrc2 p7, #2, %0, c0, c0, #0\n" : "=r" (ret)); + return ret; +} + +// ---------------------------------------------------------------------------- +// RCP Sequence count instructions + +// Directly write value cnt to the sequence counter. +// cnt must be a constant expression. +#define rcp_count_set(cnt) rcp_asm ( \ + "mcr p7, #4, r0, c%c0, c%c1, #0\n" \ + : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ +); + +#define rcp_count_set_nodelay(cnt) rcp_asm ( \ + "mcr2 p7, #4, r0, c%c0, c%c1, #0\n" \ + : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ +); + +// Check value cnt against the sequence counter, then increment the counter. +// cnt must be a constant expression. +#define rcp_count_check(cnt) rcp_asm ( \ + "mcr p7, #5, r0, c%c0, c%c1, #1\n" \ + : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ +); + +#define rcp_count_check_nodelay(cnt) rcp_asm ( \ + "mcr2 p7, #5, r0, c%c0, c%c1, #1\n" \ + : : "i"(((cnt) >> 4) & 0xf), "i"((cnt) & 0xf) \ +); + +// ---------------------------------------------------------------------------- +// RCP Panic instructions + +// Stall the coprocessor port. If the coprocessor access goes away, assert NMI + +static __rcpinline __attribute__((noreturn)) void rcp_panic(void) { + rcp_asm("cdp p7, #0, c0, c0, c0, #1"); + __builtin_unreachable(); +} + +// There is no nodelay version. + +#endif // !__riscv +// ---------------------------------------------------------------------------- +// GAS macros for RCP instructions, for direct use in ASM files +#else // __ASSEMBLER__ +#ifndef __riscv + +// Assert b is a valid boolean (0xa500a500u or 0x00c300c3u) +.macro rcp_bvalid r + mcr p7, #1, \r , c0, c0, #0 +.endm + +.macro rcp_bvalid_nodelay r + mcr2 p7, #1, \r , c0, c0, #0 +.endm + +// Assert b is true (0xa500a500u) +.macro rcp_btrue r + mcr p7, #2, \r , c0, c0, #0 +.endm + +.macro rcp_btrue_nodelay r + mcr2 p7, #2, \r , c0, c0, #0 +.endm + +// Assert b is false (0x00c300c3u) +.macro rcp_bfalse r + mcr p7, #3, \r , c0, c0, #1 +.endm + +.macro rcp_bfalse_nodelay r + mcr2 p7, #3, \r , c0, c0, #1 +.endm + +// Assert b0 and b1 are both valid booleans +.macro rcp_b2valid b0, b1 + mcrr p7, #0, \b0 , \b1 , c8 +.endm + +.macro rcp_b2valid_nodelay b0, b1 + mcrr2 p7, #0, \b0 , \b1 , c8 +.endm + +// Assert b0 and b1 are both true +.macro rcp_b2and b0, b1 + mcrr p7, #1, \b0 , \b1 , c0 +.endm + +.macro rcp_b2and_nodelay b0, b1 + mcrr2 p7, #1, \b0 , \b1 , c0 +.endm + +// Assert b0 and b1 are valid, and at least one is true +.macro rcp_b2or b0, b1 + mcrr p7, #2, \b0 , \b1 , c0 +.endm + +.macro rcp_b2or_nodelay b0, b1 + mcrr2 p7, #2, \b0 , \b1 , c0 +.endm + +// Assert (b ^ mask) is a valid boolean +.macro rcp_bxorvalid b, mask + mcrr p7, #3, \b , \mask , c8 +.endm + +.macro rcp_bxorvalid_nodelay b, mask + mcrr2 p7, #3, \b , \mask , c8 +.endm + +// Assert (b ^ mask) is true +.macro rcp_bxortrue b, mask + mcrr p7, #4, \b , \mask , c0 +.endm + +.macro rcp_bxortrue_nodelay b, mask + mcrr2 p7, #4, \b , \mask , c0 +.endm + +// Assert (b ^ mask) is false +.macro rcp_bxorfalse b, mask + mcrr p7, #5, \b , \mask , c8 +.endm + +.macro rcp_bxorfalse_nodelay b, mask + mcrr2 p7, #5, \b , \mask , c8 +.endm + +// Assert (x ^ parity) == 0x96009600u +.macro rcp_ivalid x, parity + mcrr p7, #6, \x , \parity , c8 +.endm + +.macro rcp_ivalid_nodelay x, parity + mcrr2 p7, #6, \x , \parity , c8 +.endm + +// Assert x == y +.macro rcp_iequal x, y + mcrr p7, #7, \x , \y , c0 +.endm + +.macro rcp_iequal_nodelay x, y + mcrr2 p7, #7, \x , \y , c0 +.endm + +// They call this "metaprogramming" I think +.macro rcp_switch_u8_to_ch_cl macro_name, x, args:vararg +.if (\x) == 0 +\macro_name c0, c0, \args +.elseif (\x) == 1 +\macro_name c0, c1, \args +.elseif (\x) == 2 +\macro_name c0, c2, \args +.elseif (\x) == 3 +\macro_name c0, c3, \args +.elseif (\x) == 4 +\macro_name c0, c4, \args +.elseif (\x) == 5 +\macro_name c0, c5, \args +.elseif (\x) == 6 +\macro_name c0, c6, \args +.elseif (\x) == 7 +\macro_name c0, c7, \args +.elseif (\x) == 8 +\macro_name c0, c8, \args +.elseif (\x) == 9 +\macro_name c0, c9, \args +.elseif (\x) == 10 +\macro_name c0, c10, \args +.elseif (\x) == 11 +\macro_name c0, c11, \args +.elseif (\x) == 12 +\macro_name c0, c12, \args +.elseif (\x) == 13 +\macro_name c0, c13, \args +.elseif (\x) == 14 +\macro_name c0, c14, \args +.elseif (\x) == 15 +\macro_name c0, c15, \args +.elseif (\x) == 16 +\macro_name c1, c0, \args +.elseif (\x) == 17 +\macro_name c1, c1, \args +.elseif (\x) == 18 +\macro_name c1, c2, \args +.elseif (\x) == 19 +\macro_name c1, c3, \args +.elseif (\x) == 20 +\macro_name c1, c4, \args +.elseif (\x) == 21 +\macro_name c1, c5, \args +.elseif (\x) == 22 +\macro_name c1, c6, \args +.elseif (\x) == 23 +\macro_name c1, c7, \args +.elseif (\x) == 24 +\macro_name c1, c8, \args +.elseif (\x) == 25 +\macro_name c1, c9, \args +.elseif (\x) == 26 +\macro_name c1, c10, \args +.elseif (\x) == 27 +\macro_name c1, c11, \args +.elseif (\x) == 28 +\macro_name c1, c12, \args +.elseif (\x) == 29 +\macro_name c1, c13, \args +.elseif (\x) == 30 +\macro_name c1, c14, \args +.elseif (\x) == 31 +\macro_name c1, c15, \args +.elseif (\x) == 32 +\macro_name c2, c0, \args +.elseif (\x) == 33 +\macro_name c2, c1, \args +.elseif (\x) == 34 +\macro_name c2, c2, \args +.elseif (\x) == 35 +\macro_name c2, c3, \args +.elseif (\x) == 36 +\macro_name c2, c4, \args +.elseif (\x) == 37 +\macro_name c2, c5, \args +.elseif (\x) == 38 +\macro_name c2, c6, \args +.elseif (\x) == 39 +\macro_name c2, c7, \args +.elseif (\x) == 40 +\macro_name c2, c8, \args +.elseif (\x) == 41 +\macro_name c2, c9, \args +.elseif (\x) == 42 +\macro_name c2, c10, \args +.elseif (\x) == 43 +\macro_name c2, c11, \args +.elseif (\x) == 44 +\macro_name c2, c12, \args +.elseif (\x) == 45 +\macro_name c2, c13, \args +.elseif (\x) == 46 +\macro_name c2, c14, \args +.elseif (\x) == 47 +\macro_name c2, c15, \args +.elseif (\x) == 48 +\macro_name c3, c0, \args +.elseif (\x) == 49 +\macro_name c3, c1, \args +.elseif (\x) == 50 +\macro_name c3, c2, \args +.elseif (\x) == 51 +\macro_name c3, c3, \args +.elseif (\x) == 52 +\macro_name c3, c4, \args +.elseif (\x) == 53 +\macro_name c3, c5, \args +.elseif (\x) == 54 +\macro_name c3, c6, \args +.elseif (\x) == 55 +\macro_name c3, c7, \args +.elseif (\x) == 56 +\macro_name c3, c8, \args +.elseif (\x) == 57 +\macro_name c3, c9, \args +.elseif (\x) == 58 +\macro_name c3, c10, \args +.elseif (\x) == 59 +\macro_name c3, c11, \args +.elseif (\x) == 60 +\macro_name c3, c12, \args +.elseif (\x) == 61 +\macro_name c3, c13, \args +.elseif (\x) == 62 +\macro_name c3, c14, \args +.elseif (\x) == 63 +\macro_name c3, c15, \args +.elseif (\x) == 64 +\macro_name c4, c0, \args +.elseif (\x) == 65 +\macro_name c4, c1, \args +.elseif (\x) == 66 +\macro_name c4, c2, \args +.elseif (\x) == 67 +\macro_name c4, c3, \args +.elseif (\x) == 68 +\macro_name c4, c4, \args +.elseif (\x) == 69 +\macro_name c4, c5, \args +.elseif (\x) == 70 +\macro_name c4, c6, \args +.elseif (\x) == 71 +\macro_name c4, c7, \args +.elseif (\x) == 72 +\macro_name c4, c8, \args +.elseif (\x) == 73 +\macro_name c4, c9, \args +.elseif (\x) == 74 +\macro_name c4, c10, \args +.elseif (\x) == 75 +\macro_name c4, c11, \args +.elseif (\x) == 76 +\macro_name c4, c12, \args +.elseif (\x) == 77 +\macro_name c4, c13, \args +.elseif (\x) == 78 +\macro_name c4, c14, \args +.elseif (\x) == 79 +\macro_name c4, c15, \args +.elseif (\x) == 80 +\macro_name c5, c0, \args +.elseif (\x) == 81 +\macro_name c5, c1, \args +.elseif (\x) == 82 +\macro_name c5, c2, \args +.elseif (\x) == 83 +\macro_name c5, c3, \args +.elseif (\x) == 84 +\macro_name c5, c4, \args +.elseif (\x) == 85 +\macro_name c5, c5, \args +.elseif (\x) == 86 +\macro_name c5, c6, \args +.elseif (\x) == 87 +\macro_name c5, c7, \args +.elseif (\x) == 88 +\macro_name c5, c8, \args +.elseif (\x) == 89 +\macro_name c5, c9, \args +.elseif (\x) == 90 +\macro_name c5, c10, \args +.elseif (\x) == 91 +\macro_name c5, c11, \args +.elseif (\x) == 92 +\macro_name c5, c12, \args +.elseif (\x) == 93 +\macro_name c5, c13, \args +.elseif (\x) == 94 +\macro_name c5, c14, \args +.elseif (\x) == 95 +\macro_name c5, c15, \args +.elseif (\x) == 96 +\macro_name c6, c0, \args +.elseif (\x) == 97 +\macro_name c6, c1, \args +.elseif (\x) == 98 +\macro_name c6, c2, \args +.elseif (\x) == 99 +\macro_name c6, c3, \args +.elseif (\x) == 100 +\macro_name c6, c4, \args +.elseif (\x) == 101 +\macro_name c6, c5, \args +.elseif (\x) == 102 +\macro_name c6, c6, \args +.elseif (\x) == 103 +\macro_name c6, c7, \args +.elseif (\x) == 104 +\macro_name c6, c8, \args +.elseif (\x) == 105 +\macro_name c6, c9, \args +.elseif (\x) == 106 +\macro_name c6, c10, \args +.elseif (\x) == 107 +\macro_name c6, c11, \args +.elseif (\x) == 108 +\macro_name c6, c12, \args +.elseif (\x) == 109 +\macro_name c6, c13, \args +.elseif (\x) == 110 +\macro_name c6, c14, \args +.elseif (\x) == 111 +\macro_name c6, c15, \args +.elseif (\x) == 112 +\macro_name c7, c0, \args +.elseif (\x) == 113 +\macro_name c7, c1, \args +.elseif (\x) == 114 +\macro_name c7, c2, \args +.elseif (\x) == 115 +\macro_name c7, c3, \args +.elseif (\x) == 116 +\macro_name c7, c4, \args +.elseif (\x) == 117 +\macro_name c7, c5, \args +.elseif (\x) == 118 +\macro_name c7, c6, \args +.elseif (\x) == 119 +\macro_name c7, c7, \args +.elseif (\x) == 120 +\macro_name c7, c8, \args +.elseif (\x) == 121 +\macro_name c7, c9, \args +.elseif (\x) == 122 +\macro_name c7, c10, \args +.elseif (\x) == 123 +\macro_name c7, c11, \args +.elseif (\x) == 124 +\macro_name c7, c12, \args +.elseif (\x) == 125 +\macro_name c7, c13, \args +.elseif (\x) == 126 +\macro_name c7, c14, \args +.elseif (\x) == 127 +\macro_name c7, c15, \args +.elseif (\x) == 128 +\macro_name c8, c0, \args +.elseif (\x) == 129 +\macro_name c8, c1, \args +.elseif (\x) == 130 +\macro_name c8, c2, \args +.elseif (\x) == 131 +\macro_name c8, c3, \args +.elseif (\x) == 132 +\macro_name c8, c4, \args +.elseif (\x) == 133 +\macro_name c8, c5, \args +.elseif (\x) == 134 +\macro_name c8, c6, \args +.elseif (\x) == 135 +\macro_name c8, c7, \args +.elseif (\x) == 136 +\macro_name c8, c8, \args +.elseif (\x) == 137 +\macro_name c8, c9, \args +.elseif (\x) == 138 +\macro_name c8, c10, \args +.elseif (\x) == 139 +\macro_name c8, c11, \args +.elseif (\x) == 140 +\macro_name c8, c12, \args +.elseif (\x) == 141 +\macro_name c8, c13, \args +.elseif (\x) == 142 +\macro_name c8, c14, \args +.elseif (\x) == 143 +\macro_name c8, c15, \args +.elseif (\x) == 144 +\macro_name c9, c0, \args +.elseif (\x) == 145 +\macro_name c9, c1, \args +.elseif (\x) == 146 +\macro_name c9, c2, \args +.elseif (\x) == 147 +\macro_name c9, c3, \args +.elseif (\x) == 148 +\macro_name c9, c4, \args +.elseif (\x) == 149 +\macro_name c9, c5, \args +.elseif (\x) == 150 +\macro_name c9, c6, \args +.elseif (\x) == 151 +\macro_name c9, c7, \args +.elseif (\x) == 152 +\macro_name c9, c8, \args +.elseif (\x) == 153 +\macro_name c9, c9, \args +.elseif (\x) == 154 +\macro_name c9, c10, \args +.elseif (\x) == 155 +\macro_name c9, c11, \args +.elseif (\x) == 156 +\macro_name c9, c12, \args +.elseif (\x) == 157 +\macro_name c9, c13, \args +.elseif (\x) == 158 +\macro_name c9, c14, \args +.elseif (\x) == 159 +\macro_name c9, c15, \args +.elseif (\x) == 160 +\macro_name c10, c0, \args +.elseif (\x) == 161 +\macro_name c10, c1, \args +.elseif (\x) == 162 +\macro_name c10, c2, \args +.elseif (\x) == 163 +\macro_name c10, c3, \args +.elseif (\x) == 164 +\macro_name c10, c4, \args +.elseif (\x) == 165 +\macro_name c10, c5, \args +.elseif (\x) == 166 +\macro_name c10, c6, \args +.elseif (\x) == 167 +\macro_name c10, c7, \args +.elseif (\x) == 168 +\macro_name c10, c8, \args +.elseif (\x) == 169 +\macro_name c10, c9, \args +.elseif (\x) == 170 +\macro_name c10, c10, \args +.elseif (\x) == 171 +\macro_name c10, c11, \args +.elseif (\x) == 172 +\macro_name c10, c12, \args +.elseif (\x) == 173 +\macro_name c10, c13, \args +.elseif (\x) == 174 +\macro_name c10, c14, \args +.elseif (\x) == 175 +\macro_name c10, c15, \args +.elseif (\x) == 176 +\macro_name c11, c0, \args +.elseif (\x) == 177 +\macro_name c11, c1, \args +.elseif (\x) == 178 +\macro_name c11, c2, \args +.elseif (\x) == 179 +\macro_name c11, c3, \args +.elseif (\x) == 180 +\macro_name c11, c4, \args +.elseif (\x) == 181 +\macro_name c11, c5, \args +.elseif (\x) == 182 +\macro_name c11, c6, \args +.elseif (\x) == 183 +\macro_name c11, c7, \args +.elseif (\x) == 184 +\macro_name c11, c8, \args +.elseif (\x) == 185 +\macro_name c11, c9, \args +.elseif (\x) == 186 +\macro_name c11, c10, \args +.elseif (\x) == 187 +\macro_name c11, c11, \args +.elseif (\x) == 188 +\macro_name c11, c12, \args +.elseif (\x) == 189 +\macro_name c11, c13, \args +.elseif (\x) == 190 +\macro_name c11, c14, \args +.elseif (\x) == 191 +\macro_name c11, c15, \args +.elseif (\x) == 192 +\macro_name c12, c0, \args +.elseif (\x) == 193 +\macro_name c12, c1, \args +.elseif (\x) == 194 +\macro_name c12, c2, \args +.elseif (\x) == 195 +\macro_name c12, c3, \args +.elseif (\x) == 196 +\macro_name c12, c4, \args +.elseif (\x) == 197 +\macro_name c12, c5, \args +.elseif (\x) == 198 +\macro_name c12, c6, \args +.elseif (\x) == 199 +\macro_name c12, c7, \args +.elseif (\x) == 200 +\macro_name c12, c8, \args +.elseif (\x) == 201 +\macro_name c12, c9, \args +.elseif (\x) == 202 +\macro_name c12, c10, \args +.elseif (\x) == 203 +\macro_name c12, c11, \args +.elseif (\x) == 204 +\macro_name c12, c12, \args +.elseif (\x) == 205 +\macro_name c12, c13, \args +.elseif (\x) == 206 +\macro_name c12, c14, \args +.elseif (\x) == 207 +\macro_name c12, c15, \args +.elseif (\x) == 208 +\macro_name c13, c0, \args +.elseif (\x) == 209 +\macro_name c13, c1, \args +.elseif (\x) == 210 +\macro_name c13, c2, \args +.elseif (\x) == 211 +\macro_name c13, c3, \args +.elseif (\x) == 212 +\macro_name c13, c4, \args +.elseif (\x) == 213 +\macro_name c13, c5, \args +.elseif (\x) == 214 +\macro_name c13, c6, \args +.elseif (\x) == 215 +\macro_name c13, c7, \args +.elseif (\x) == 216 +\macro_name c13, c8, \args +.elseif (\x) == 217 +\macro_name c13, c9, \args +.elseif (\x) == 218 +\macro_name c13, c10, \args +.elseif (\x) == 219 +\macro_name c13, c11, \args +.elseif (\x) == 220 +\macro_name c13, c12, \args +.elseif (\x) == 221 +\macro_name c13, c13, \args +.elseif (\x) == 222 +\macro_name c13, c14, \args +.elseif (\x) == 223 +\macro_name c13, c15, \args +.elseif (\x) == 224 +\macro_name c14, c0, \args +.elseif (\x) == 225 +\macro_name c14, c1, \args +.elseif (\x) == 226 +\macro_name c14, c2, \args +.elseif (\x) == 227 +\macro_name c14, c3, \args +.elseif (\x) == 228 +\macro_name c14, c4, \args +.elseif (\x) == 229 +\macro_name c14, c5, \args +.elseif (\x) == 230 +\macro_name c14, c6, \args +.elseif (\x) == 231 +\macro_name c14, c7, \args +.elseif (\x) == 232 +\macro_name c14, c8, \args +.elseif (\x) == 233 +\macro_name c14, c9, \args +.elseif (\x) == 234 +\macro_name c14, c10, \args +.elseif (\x) == 235 +\macro_name c14, c11, \args +.elseif (\x) == 236 +\macro_name c14, c12, \args +.elseif (\x) == 237 +\macro_name c14, c13, \args +.elseif (\x) == 238 +\macro_name c14, c14, \args +.elseif (\x) == 239 +\macro_name c14, c15, \args +.elseif (\x) == 240 +\macro_name c15, c0, \args +.elseif (\x) == 241 +\macro_name c15, c1, \args +.elseif (\x) == 242 +\macro_name c15, c2, \args +.elseif (\x) == 243 +\macro_name c15, c3, \args +.elseif (\x) == 244 +\macro_name c15, c4, \args +.elseif (\x) == 245 +\macro_name c15, c5, \args +.elseif (\x) == 246 +\macro_name c15, c6, \args +.elseif (\x) == 247 +\macro_name c15, c7, \args +.elseif (\x) == 248 +\macro_name c15, c8, \args +.elseif (\x) == 249 +\macro_name c15, c9, \args +.elseif (\x) == 250 +\macro_name c15, c10, \args +.elseif (\x) == 251 +\macro_name c15, c11, \args +.elseif (\x) == 252 +\macro_name c15, c12, \args +.elseif (\x) == 253 +\macro_name c15, c13, \args +.elseif (\x) == 254 +\macro_name c15, c14, \args +.elseif (\x) == 255 +\macro_name c15, c15, \args +.else +.error "Value outside of range 0-255" +.endif +.endm + +// Directly write 8-bit constant expression cnt to the sequence counter. +.macro rcp_count_set_impl h, l +mcr p7, #4, r0, \h , \l , #0 +.endm +.macro rcp_count_set cnt +rcp_switch_u8_to_ch_cl rcp_count_set_impl, \cnt +.endm + +.macro rcp_count_set_nodelay_impl h, l +mcr2 p7, #4, r0, \h , \l , #0 +.endm +.macro rcp_count_set_nodelay cnt +rcp_switch_u8_to_ch_cl rcp_count_set_nodelay_impl, \cnt +.endm + +// Check 8-bit constant expression cnt against the sequence counter, then +// increment the counter. +.macro rcp_count_check_impl h, l + mcr p7, #5, r0, \h, \l, #1 +.endm +.macro rcp_count_check cnt +rcp_switch_u8_to_ch_cl rcp_count_check_impl, \cnt +.endm + +.macro rcp_count_check_nodelay_impl h, l + mcr2 p7, #5, r0, \h, \l, #1 +.endm +.macro rcp_count_check_nodelay cnt +rcp_switch_u8_to_ch_cl rcp_count_check_nodelay_impl, \cnt +.endm + +// Get a 32-bit canary value. `tag` must be a constant expression. +.macro rcp_canary_get_impl h, l, x + mrc p7, #0, \x, \h, \l, #1 +.endm + +.macro rcp_canary_get x, tag +rcp_switch_u8_to_ch_cl rcp_canary_get_impl \tag, \x +.endm + +// Get a 32-bit canary value. `tag` must be a constant expression. +.macro rcp_canary_get_nodelay_impl h, l, x + mrc2 p7, #0, \x, \h, \l, #1 +.endm + +.macro rcp_canary_get_nodelay x, tag +rcp_switch_u8_to_ch_cl rcp_canary_get_nodelay_impl \tag, \x +.endm + +// Assert that canary matches result of rcp_canary_get with the same tags: +.macro rcp_canary_check_impl h, l, x + mcr p7, #0, \x, \h, \l, #1 +.endm + +.macro rcp_canary_check x, tag +rcp_switch_u8_to_ch_cl rcp_canary_check_impl \tag, \x +.endm + +.macro rcp_canary_check_nodelay_impl h, l, x + mcr2 p7, #0, \x, \h, \l, #1 +.endm + +.macro rcp_canary_check_nodelay x, tag +rcp_switch_u8_to_ch_cl rcp_canary_check_nodelay_impl \tag, \x +.endm + +.macro rcp_panic + cdp p7, #0, c0, c0, c0, #1 +.endm + +#endif // !__riscv +#endif // __ASSEMBLER__ +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/src/rp2_common/hardware_resets/BUILD.bazel b/src/rp2_common/hardware_resets/BUILD.bazel index 2a0fa99de..56c8cdfd8 100644 --- a/src/rp2_common/hardware_resets/BUILD.bazel +++ b/src/rp2_common/hardware_resets/BUILD.bazel @@ -8,7 +8,7 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_resets/include/hardware/resets.h b/src/rp2_common/hardware_resets/include/hardware/resets.h index a5bdb647e..8baef728b 100644 --- a/src/rp2_common/hardware_resets/include/hardware/resets.h +++ b/src/rp2_common/hardware_resets/include/hardware/resets.h @@ -16,7 +16,7 @@ * \brief Hardware Reset API * * The reset controller allows software control of the resets to all of the peripherals that are not - * critical to boot the processor in the RP2040. + * critical to boot the processor in the RP-series microcontroller. * * \subsubsection reset_bitmask * \addtogroup hardware_resets @@ -56,10 +56,32 @@ * \include hello_reset.c */ +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS, Enable/disable assertions in the hardware_resets module, type=bool, default=0, group=hardware_adc +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS +#ifdef PARAM_ASSERTIONS_ENABLED_RESET // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS PARAM_ASSERTIONS_ENABLED_RESET +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_RESETS 0 +#endif +#endif #ifdef __cplusplus extern "C" { #endif +static __force_inline void reset_block_reg_mask(io_rw_32 *reset, uint32_t mask) { + hw_set_bits(reset, mask); +} + +static __force_inline void unreset_block_reg_mask(io_rw_32 *reset, uint32_t mask) { + hw_clear_bits(reset, mask); +} + +static __force_inline void unreset_block_reg_mask_wait_blocking(io_rw_32 *reset, io_ro_32 *reset_done, uint32_t mask) { + hw_clear_bits(reset, mask); + while (~*reset_done & mask) + tight_loop_contents(); +} + /// \tag::reset_funcs[] /*! \brief Reset the specified HW blocks @@ -67,8 +89,8 @@ extern "C" { * * \param bits Bit pattern indicating blocks to reset. See \ref reset_bitmask */ -static inline void reset_block(uint32_t bits) { - hw_set_bits(&resets_hw->reset, bits); +static __force_inline void reset_block_mask(uint32_t bits) { + reset_block_reg_mask(&resets_hw->reset, bits); } /*! \brief bring specified HW blocks out of reset @@ -76,8 +98,8 @@ static inline void reset_block(uint32_t bits) { * * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask */ -static inline void unreset_block(uint32_t bits) { - hw_clear_bits(&resets_hw->reset, bits); +static __force_inline void unreset_block_mask(uint32_t bits) { + unreset_block_reg_mask(&resets_hw->reset, bits); } /*! \brief Bring specified HW blocks out of reset and wait for completion @@ -85,13 +107,70 @@ static inline void unreset_block(uint32_t bits) { * * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask */ -static inline void unreset_block_wait(uint32_t bits) { - hw_clear_bits(&resets_hw->reset, bits); - while (~resets_hw->reset_done & bits) - tight_loop_contents(); +static __force_inline void unreset_block_mask_wait_blocking(uint32_t bits) { + unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, bits); } + /// \end::reset_funcs[] +#ifndef HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY +#define HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY 1 +#endif + +#if HARDWARE_RESETS_ENABLE_SDK1XX_COMPATIBILITY +static __force_inline void reset_block(uint32_t bits) { + reset_block_mask(bits); +} + +static __force_inline void unreset_block(uint32_t bits) { + unreset_block_mask(bits); +} + +static __force_inline void unreset_block_wait(uint32_t bits) { + return unreset_block_mask_wait_blocking(bits); +} +#endif + +/*! \brief Reset the specified HW block + * \ingroup hardware_resets + * + * \param block_num the block number + */ +static inline void reset_block_num(uint32_t block_num) { + reset_block_reg_mask(&resets_hw->reset, 1u << block_num); +} + +/*! \brief bring specified HW block out of reset + * \ingroup hardware_resets + * + * \param block_num the block number + */ +static inline void unreset_block_num(uint block_num) { + invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS); + unreset_block_reg_mask(&resets_hw->reset, 1u << block_num); +} + +/*! \brief Bring specified HW block out of reset and wait for completion + * \ingroup hardware_resets + * + * \param block_num the block number + */ +static inline void unreset_block_num_wait_blocking(uint block_num) { + invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS); + unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, 1u << block_num); +} + +/*! \brief Reset the specified HW block, and then bring at back out of reset and wait for completion + * \ingroup hardware_resets + * + * \param block_num the block number + */ +static inline void reset_unreset_block_num_wait_blocking(uint block_num) { + invalid_params_if(HARDWARE_RESETS, block_num > NUM_RESETS); + reset_block_reg_mask(&resets_hw->reset, 1u << block_num); + unreset_block_reg_mask_wait_blocking(&resets_hw->reset, &resets_hw->reset_done, 1u << block_num); +} + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/hardware_riscv/BUILD.bazel b/src/rp2_common/hardware_riscv/BUILD.bazel new file mode 100644 index 000000000..3532490d8 --- /dev/null +++ b/src/rp2_common/hardware_riscv/BUILD.bazel @@ -0,0 +1,14 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_riscv", + hdrs = ["include/hardware/riscv.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2() + ["@platforms//cpu:riscv32"], + deps = [ + "//src/rp2_common:hardware_regs", + "//src/rp2_common:pico_platform", + ], +) diff --git a/src/rp2_common/hardware_riscv/CMakeLists.txt b/src/rp2_common/hardware_riscv/CMakeLists.txt new file mode 100644 index 000000000..e9c7e3c70 --- /dev/null +++ b/src/rp2_common/hardware_riscv/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_headers_only_target(riscv) diff --git a/src/rp2_common/hardware_riscv/include/hardware/riscv.h b/src/rp2_common/hardware_riscv/include/hardware/riscv.h new file mode 100644 index 000000000..afdd2e55d --- /dev/null +++ b/src/rp2_common/hardware_riscv/include/hardware/riscv.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2022 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_RISCV_ +#define _HARDWARE_RISCV_ + +#include "pico.h" +#include "hardware/regs/rvcsr.h" + +#ifndef __ASSEMBLER__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file hardware/riscv.h + * \defgroup hardware_riscv hardware_riscv + * + * \brief Accessors for standard RISC-V hardware (mainly CSRs) + * + */ + +#define _riscv_read_csr(csrname) ({ \ + uint32_t __csr_tmp_u32; \ + asm volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \ + __csr_tmp_u32; \ +}) + +#define _riscv_write_csr(csrname, data) ({ \ + if (__builtin_constant_p(data) && !((data) & -32u)) { \ + asm volatile ("csrwi " #csrname ", %0" : : "i" (data)); \ + } else { \ + asm volatile ("csrw " #csrname ", %0" : : "r" (data)); \ + } \ +}) + +#define _riscv_set_csr(csrname, data) ({ \ + if (__builtin_constant_p(data) && !((data) & -32u)) { \ + asm volatile ("csrsi " #csrname ", %0" : : "i" (data)); \ + } else { \ + asm volatile ("csrs " #csrname ", %0" : : "r" (data)); \ + } \ +}) + +#define _riscv_clear_csr(csrname, data) ({ \ + if (__builtin_constant_p(data) && !((data) & -32u)) { \ + asm volatile ("csrci " #csrname ", %0" : : "i" (data)); \ + } else { \ + asm volatile ("csrc " #csrname ", %0" : : "r" (data)); \ + } \ +}) + +#define _riscv_read_write_csr(csrname, data) ({ \ + uint32_t __csr_tmp_u32; \ + if (__builtin_constant_p(data) && !((data) & -32u)) { \ + asm volatile ("csrrwi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \ + } else { \ + asm volatile ("csrrw %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \ + } \ + __csr_tmp_u32; \ +}) + +#define _riscv_read_set_csr(csrname, data) ({ \ + uint32_t __csr_tmp_u32; \ + if (__builtin_constant_p(data) && !((data) & -32u)) { \ + asm volatile ("csrrsi %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \ + } else { \ + asm volatile ("csrrs %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \ + } \ + __csr_tmp_u32; \ +}) + +#define _riscv_read_clear_csr(csrname, data) ({ \ + uint32_t __csr_tmp_u32; \ + if (__builtin_constant_p(data) && !((data) & -32u)) { \ + asm volatile ("csrrci %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "i" (data)); \ + } else { \ + asm volatile ("csrrc %0, " #csrname ", %1": "=r" (__csr_tmp_u32) : "r" (data)); \ + } \ + __csr_tmp_u32; \ +}) + +// Argument macro expansion layer (CSR name may be a macro that expands to a +// CSR number, or it may be a bare name that the assembler knows about.) +#define riscv_read_csr(csrname) _riscv_read_csr(csrname) +#define riscv_write_csr(csrname, data) _riscv_write_csr(csrname, data) +#define riscv_set_csr(csrname, data) _riscv_set_csr(csrname, data) +#define riscv_clear_csr(csrname, data) _riscv_clear_csr(csrname, data) +#define riscv_read_write_csr(csrname, data) _riscv_read_write_csr(csrname, data) +#define riscv_read_set_csr(csrname, data) _riscv_read_set_csr(csrname, data) +#define riscv_read_clear_csr(csrname, data) _riscv_read_clear_csr(csrname, data) + +// Helpers for encoding RISC-V immediates + +// U format, e.g. lui +static inline uint32_t riscv_encode_imm_u(uint32_t x) { + return (x >> 12) << 12; +} + +// I format, e.g. addi +static inline uint32_t riscv_encode_imm_i(uint32_t x) { + return (x & 0xfff) << 20; +} + +// The U-format part of a U+I 32-bit immediate: +static inline uint32_t riscv_encode_imm_u_hi(uint32_t x) { + // We will add a signed 12 bit constant to the "lui" value, + // so we need to correct for the carry here. + x += (x & 0x800) << 1; + return riscv_encode_imm_u(x); +} + +// B format, e.g. bgeu +static inline uint32_t riscv_encode_imm_b(uint32_t x) { + return + (((x >> 12) & 0x01) << 31) | + (((x >> 5) & 0x3f) << 25) | + (((x >> 1) & 0x0f) << 8) | + (((x >> 11) & 0x01) << 7); +} + +// S format, e.g. sw +static inline uint32_t riscv_encode_imm_s(uint32_t x) { + return + (((x >> 5) & 0x7f) << 25) | + (((x >> 0) & 0x1f) << 7); +} + +// J format, e.g. jal +static inline uint32_t riscv_encode_imm_j(uint32_t x) { + return + (((x >> 20) & 0x001) << 31) | + (((x >> 1) & 0x3ff) << 21) | + (((x >> 11) & 0x001) << 20) | + (((x >> 12) & 0x0ff) << 12); +} + +// CJ format, e.g. c.jal +static inline uint16_t riscv_encode_imm_cj(uint32_t x) { + return (uint16_t)( + (((x >> 11) & 0x1) << 12) | + (((x >> 4) & 0x1) << 11) | + (((x >> 8) & 0x3) << 9) | + (((x >> 10) & 0x1) << 8) | + (((x >> 6) & 0x1) << 7) | + (((x >> 7) & 0x1) << 6) | + (((x >> 1) & 0x7) << 3) | + (((x >> 5) & 0x1) << 2) + ); +} + +// CB format, e.g. c.beqz +static inline uint16_t riscv_encode_imm_cb(uint32_t x) { + return (uint16_t)( + (((x >> 8) & 0x1) << 12) | + (((x >> 3) & 0x3) << 10) | + (((x >> 6) & 0x3) << 5) | + (((x >> 1) & 0x3) << 3) | + (((x >> 5) & 0x1) << 2) + ); +} + +// CI format, e.g. c.addi +static inline uint16_t riscv_encode_imm_ci(uint32_t x) { + return (uint16_t)( + (((x >> 5) & 0x01) << 12) | + (((x >> 0) & 0x1f) << 2) + ); +} + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/src/rp2_common/hardware_riscv_platform_timer/BUILD.bazel b/src/rp2_common/hardware_riscv_platform_timer/BUILD.bazel new file mode 100644 index 000000000..1ced3e3c7 --- /dev/null +++ b/src/rp2_common/hardware_riscv_platform_timer/BUILD.bazel @@ -0,0 +1,14 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_riscv_platform_timer", + hdrs = ["include/hardware/riscv_platform_timer.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2() + ["@platforms//cpu:riscv32"], + deps = [ + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", + ], +) diff --git a/src/rp2_common/hardware_riscv_platform_timer/CMakeLists.txt b/src/rp2_common/hardware_riscv_platform_timer/CMakeLists.txt new file mode 100644 index 000000000..e317be433 --- /dev/null +++ b/src/rp2_common/hardware_riscv_platform_timer/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_headers_only_target(riscv_platform_timer) diff --git a/src/rp2_common/hardware_riscv_platform_timer/include/hardware/riscv_platform_timer.h b/src/rp2_common/hardware_riscv_platform_timer/include/hardware/riscv_platform_timer.h new file mode 100644 index 000000000..c2dfeccc7 --- /dev/null +++ b/src/rp2_common/hardware_riscv_platform_timer/include/hardware/riscv_platform_timer.h @@ -0,0 +1,145 @@ +#ifndef _HARDWARE_RISCV_PLATFORM_TIMER_ +#define _HARDWARE_RISCV_PLATFORM_TIMER_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "pico.h" +#include "hardware/structs/sio.h" + +/** \file hardware/riscv_platform_timer.h + * \defgroup hardware_riscv_platform_timer hardware_riscv_platform_timer + * + * \brief Accessors for standard RISC-V platform timer (mtime/mtimecmp), available on + * Raspberry Pi microcontrollers with RISC-V processors + * + * Note this header can be used by Arm as well as RISC-V processors, as the + * timer is a memory-mapped peripheral external to the processors. The name + * refers to this timer being a standard RISC-V peripheral. + * + */ + +/*! \brief Enable or disable the RISC-V platform timer + * \ingroup hardware_riscv_platform_timer + * + * This enables and disables the counting of the RISC-V platform timer. It + * does not enable or disable the interrupts, which are asserted + * unconditionally when a given core's mtimecmp/mtimecmph registers are + * greater than the current 64-bit value of the mtime/mtimeh registers. + * + * \param enabled Pass true to enable, false to disable + */ +static inline void riscv_timer_set_enabled(bool enabled) { + if (enabled) { + // Note atomic rwtype is not supported on SIO + sio_hw->mtime_ctrl |= SIO_MTIME_CTRL_EN_BITS; + } else { + sio_hw->mtime_ctrl &= ~SIO_MTIME_CTRL_EN_BITS; + } +} + +/*! \brief Configure the RISC-V platform timer to run at full system clock speed + * \ingroup hardware_riscv_platform_timer + * + * \param fullspeed Pass true to increment at system clock speed, false to + * increment at the frequency defined by the system tick generator + * (the `ticks` block) + */ +static inline void riscv_timer_set_fullspeed(bool fullspeed) { + if (fullspeed) { + sio_hw->mtime_ctrl |= SIO_MTIME_CTRL_FULLSPEED_BITS; + } else { + sio_hw->mtime_ctrl &= ~SIO_MTIME_CTRL_FULLSPEED_BITS; + } +} + +/*! \brief Read the RISC-V platform timer + * \ingroup hardware_riscv_platform_timer + * + * \return Current 64-bit mtime value + */ +static inline uint64_t riscv_timer_get_mtime(void) { + // Read procedure from RISC-V ISA manual to avoid being off by 2**32 on + // low half rollover -- note this loop generally executes only once, and + // should never execute more than twice: + uint32_t h0, l, h1; + do { + h0 = sio_hw->mtimeh; + l = sio_hw->mtime; + h1 = sio_hw->mtimeh; + } while (h0 != h1); + return l | (uint64_t)h1 << 32; +} + +/*! \brief Update the RISC-V platform timer + * \ingroup hardware_riscv_platform_timer + * + * This function should only be called when the timer is disabled via + * riscv_timer_set_enabled(). Note also that unlike the mtimecmp comparison + * values, mtime is *not* core-local, so updates on one core will be visible + * to the other core. + * + * \param mtime New value to set the RISC-V platform timer to + */ +static inline void riscv_timer_set_mtime(uint64_t mtime) { + // This ought really only be done when the timer is stopped, but we can + // make things a bit safer by clearing the low half of the counter, then + // writing high half, then low half. This protects against the low half + // rolling over, and largely avoids getting an intermediate value that is + // higher than either the original or new value, if the timer is running. + // + // Note that on RP2350, mtime is shared between the two cores!(mtimcemp is + // core-local however.) + sio_hw->mtime = 0; + sio_hw->mtimeh = mtime >> 32; + sio_hw->mtime = mtime & 0xffffffffu; +} + +/*! \brief Get the current RISC-V platform timer mtimecmp value for this core + * \ingroup hardware_riscv_platform_timer + * + * Get the current mtimecmp value for the calling core. This function is + * interrupt-safe as long as timer interrupts only increase the value of + * mtimecmp. Otherwise, it must be called with timer interrupts disabled. + * + * \return Current value of mtimecmp + */ +static inline uint64_t riscv_timer_get_mtimecmp(void) { + // Use the same procedure as reading mtime, which should be safe assuming + // mtimecmp increases monotonically with successive interrupts. + uint32_t h0, l, h1; + do { + h0 = sio_hw->mtimecmph; + l = sio_hw->mtimecmp; + h1 = sio_hw->mtimecmph; + } while (h0 != h1); + return l | (uint64_t)h1 << 32; +} + +/*! \brief Set a new RISC-V platform timer interrupt comparison value (mtimecmp) for this core + * \ingroup hardware_riscv_platform_timer + * + * This function updates the mtimecmp value for the current core. The calling + * core's RISC-V platform timer interrupt is asserted whenever the 64-bit + * mtime value (stored in 32-bit mtime/mtimeh registers) is greater than or + * equal to this core's current mtime/mtimecmph value. + * + * \param mtime New value to set the RISC-V platform timer to + */ +static inline void riscv_timer_set_mtimecmp(uint64_t mtimecmp) { + // Use write procedure from RISC-V ISA manual to avoid causing a spurious + // interrupt when updating the two halves of mtimecmp. + // No lower than original: + sio_hw->mtimecmp = -1u; + // No lower than original, no lower than new (assuming new >= original): + sio_hw->mtimecmph = mtimecmp >> 32; + // Equal to new: + sio_hw->mtimecmp = mtimecmp & 0xffffffffu; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/rp2_common/hardware_rtc/BUILD.bazel b/src/rp2_common/hardware_rtc/BUILD.bazel index 31226ec2f..847798cef 100644 --- a/src/rp2_common/hardware_rtc/BUILD.bazel +++ b/src/rp2_common/hardware_rtc/BUILD.bazel @@ -1,5 +1,3 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") - package(default_visibility = ["//visibility:public"]) cc_library( @@ -7,12 +5,13 @@ cc_library( srcs = ["rtc.c"], hdrs = ["include/hardware/rtc.h"], includes = ["include"], - target_compatible_with = compatible_with_rp2(), + # TODO: Only rp2040 has a hardware/structs/rtc.h header. + target_compatible_with = ["//bazel/constraint:rp2040"], deps = [ - "//src/common/pico_base", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_resets", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_rtc/CMakeLists.txt b/src/rp2_common/hardware_rtc/CMakeLists.txt index 354cd8c22..ce96515c5 100644 --- a/src/rp2_common/hardware_rtc/CMakeLists.txt +++ b/src/rp2_common/hardware_rtc/CMakeLists.txt @@ -1,2 +1,2 @@ pico_simple_hardware_target(rtc) -pico_mirrored_target_link_libraries(hardware_rtc INTERFACE hardware_irq hardware_resets hardware_clocks) \ No newline at end of file +pico_mirrored_target_link_libraries(hardware_rtc INTERFACE hardware_irq hardware_resets hardware_clocks) diff --git a/src/rp2_common/hardware_rtc/rtc.c b/src/rp2_common/hardware_rtc/rtc.c index 868aa4e11..f3f61eabf 100644 --- a/src/rp2_common/hardware_rtc/rtc.c +++ b/src/rp2_common/hardware_rtc/rtc.c @@ -25,8 +25,7 @@ void rtc_init(void) { assert(rtc_freq != 0); // Take rtc out of reset now that we know clk_rtc is running - reset_block(RESETS_RESET_RTC_BITS); - unreset_block_wait(RESETS_RESET_RTC_BITS); + reset_unreset_block_num_wait_blocking(RESET_RTC); // Set up the 1 second divider. // If rtc_freq is 400 then clkdiv_m1 should be 399 diff --git a/src/rp2_common/hardware_sha256/BUILD.bazel b/src/rp2_common/hardware_sha256/BUILD.bazel new file mode 100644 index 000000000..41dde0982 --- /dev/null +++ b/src/rp2_common/hardware_sha256/BUILD.bazel @@ -0,0 +1,14 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_sha256", + srcs = ["sha256.c"], + hdrs = ["include/hardware/sha256.h"], + includes = ["include"], + # TODO: RP2350 only, but doesn't appear gated in CMake. + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", + ], +) diff --git a/src/rp2_common/hardware_sha256/CMakeLists.txt b/src/rp2_common/hardware_sha256/CMakeLists.txt new file mode 100644 index 000000000..ccf0742e1 --- /dev/null +++ b/src/rp2_common/hardware_sha256/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(sha256) diff --git a/src/rp2_common/hardware_sha256/include/hardware/sha256.h b/src/rp2_common/hardware_sha256/include/hardware/sha256.h new file mode 100644 index 000000000..db8fca6ff --- /dev/null +++ b/src/rp2_common/hardware_sha256/include/hardware/sha256.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_SHA256_H +#define _HARDWARE_SHA256_H + +#include "pico.h" +#include "hardware/structs/sha256.h" + +/** \file hardware/sha256.h + * \defgroup hardware_sha256 hardware_sha256 + * + * \brief Hardware SHA-256 Accelerator API + * + * RP2350 is equipped with an implementation of the SHA-256 hash algorithm. + * The hardware should first be configured by calling the \ref sha256_set_dma_size and \ref sha256_set_bswap functions. + * To generate a new hash the hardware should first be initialised by calling \ref sha256_start. + * The hardware is ready to accept data when \ref sha256_is_ready returns true, + * at which point the data to be hashed can be written to the address returned by \ref sha256_get_write_addr. + * The hardware requires 64 bytes to be written in one go or else \ref sha256_err_not_ready will indicate an error and + * the hashing process must be restarted. + * \ref sha256_is_sum_valid will return true when there is a valid checksum result which can be retrieved by calling \ref sha256_get_result. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256, Enable/disable hardware_sha256 assertions, type=bool, default=0, group=hardware_sha256 +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 +#ifdef PARAM_ASSERTIONS_ENABLED_SHA256 // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 PARAM_ASSERTIONS_ENABLED_SHA256 +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 0 +#endif +#endif + +/*! \brief Size of a sha256 result in bytes. + * \ingroup hardware_sha256 + */ +#define SHA256_RESULT_BYTES 32 + +/*! \brief SHA-256 endianness definition used in the API + * \ingroup hardware_sha256 + */ +enum sha256_endianness { + SHA256_LITTLE_ENDIAN, ///< Little Endian + SHA256_BIG_ENDIAN, ///< Big Endian +}; + +/*! \brief SHA-256 result generated by the API + * \ingroup hardware_sha256 + */ +typedef union { + uint32_t words[SHA256_RESULT_BYTES/4]; + uint8_t bytes[SHA256_RESULT_BYTES]; +} sha256_result_t; + +/*! \brief Configure the correct DMA data size. + * \ingroup hardware_sha256 + * + * This must be configured before the DMA channel is triggered and ensures the correct number of transfers is requested per block. + * + * \param size_in_bytes Size of DMA transfers, either 1, 2 or 4 bytes only. + */ +static inline void sha256_set_dma_size(uint size_in_bytes) { + uint32_t val; + invalid_params_if(HARDWARE_SHA256, size_in_bytes != 1 && size_in_bytes != 2 && size_in_bytes != 4); + if (size_in_bytes == 1) { + val = SHA256_CSR_DMA_SIZE_VALUE_8BIT; + } else if (size_in_bytes == 2) { + val = SHA256_CSR_DMA_SIZE_VALUE_16BIT; + } else { + val = SHA256_CSR_DMA_SIZE_VALUE_32BIT; + } + hw_write_masked(&sha256_hw->csr, val << SHA256_CSR_DMA_SIZE_LSB, SHA256_CSR_DMA_SIZE_BITS); +} + + +/*! \brief Enable or disable byte swapping of 32-bit values. + * \ingroup hardware_sha256 + * + * The SHA256 algorithm expects bytes in big endian order, but the system bus deals with little endian data, + * so control is provided to convert little endian bus data to big endian internal data. This defaults to true + * + * \param swap false to disable byte swapping + */ +static inline void sha256_set_bswap(bool swap) { + if (swap) { + hw_set_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); + } else { + hw_clear_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); + } +} + +/*! \brief Prepare the hardware for a new checksum. + * \ingroup hardware_sha256 + * + * Called to initialise the hardware before starting the checksum calculation + */ +static inline void sha256_start(void) { + hw_set_bits(&sha256_hw->csr, SHA256_CSR_START_BITS); +} + +/*! \brief Check if a valid checksum has been calculated + * \ingroup hardware_sha256 + * + * The checksum result will be invalid when data is first written to the hardware, + * and then once 64 bytes of data has been written it may take some time to complete the digest of the current block. + * This function can be used to determine when the checksum is valid. + * + * \return True if \ref sha256_get_result would return a valid result + */ +static inline bool sha256_is_sum_valid(void) { + return sha256_hw->csr & SHA256_CSR_SUM_VLD_BITS; +} + +/*! \brief Check if a the hardware is ready to accept more data + * \ingroup hardware_sha256 + * + * After writing 64 bytes of data to the hardware, it will be unable to accept more data for a time. + * Call this to check if the hardware is ready for more data to be written. \see sha256_err_not_ready + * + * \return True if the hardware is ready to receive more data + */ +static inline bool sha256_is_ready(void) { + return sha256_hw->csr & SHA256_CSR_WDATA_RDY_BITS; +} + +/*! \brief Wait until the checksum is valid + * \ingroup hardware_sha256 + * + * When a multiple of 64 bytes of data has been written to the hardware, + * the checksum will be valid once the digest of the current block is complete. + * This function waits until when the checksum result is valid. + */ +static inline void sha256_wait_valid_blocking(void) { + while (!sha256_is_sum_valid()) { + tight_loop_contents(); + } +} + +/*! \brief Wait until the hardware is ready to accept more data + * \ingroup hardware_sha256 + * + * Before writing to the hardware, it's necessary to check it is ready to accept more data. + * This function waits until the hardware is ready to accept more data + */ +static inline void sha256_wait_ready_blocking(void) { + while (!sha256_is_ready()) { + tight_loop_contents(); + } +} + +/*! \brief Get the checksum result + * \ingroup hardware_sha256 + * + * Read the 32 byte result calculated by the hardware. Only valid if \ref sha256_is_sum_valid is True + * + * \param out The checksum result + */ +void sha256_get_result(sha256_result_t *out, enum sha256_endianness endianness); + +/*! \brief Check if data was written before the hardware was ready + * \ingroup hardware_sha256 + * + * Indicates if an error has occurred due to data being written when the hardware is not ready. + * + * \return True if data was written before the hardware was ready + */ +static inline bool sha256_err_not_ready(void) { + return sha256_hw->csr & SHA256_CSR_ERR_WDATA_NOT_RDY_BITS; +} + +/*! \brief Clear the "not ready" error condition + * \ingroup hardware_sha256 + * + * Resets the hardware if a "not ready" error condition is indicated. + */ +static inline void sha256_err_not_ready_clear(void) { + hw_clear_bits(&sha256_hw->csr, SHA256_CSR_ERR_WDATA_NOT_RDY_BITS); +} + +/*! \brief Address to write the data to be hashed + * \ingroup hardware_sha256 + * + * Returns the hardware address where data to be hashed should be written + * + * \return Address to write data to be hashed + */ +static inline volatile void *sha256_get_write_addr(void) { + return &sha256_hw->wdata; +} + +/*! \brief Write one 32bit word of data to the SHA-256 hardware + * \ingroup hardware_sha256 + * + * \param word data to write + */ +static inline void sha256_put_word(uint32_t word) { + sha256_hw->wdata = word; +} + +/*! \brief Write one byte of data to the SHA-256 hardware + * \ingroup hardware_sha256 + * + * \param b data to write + */ +static inline void sha256_put_byte(uint8_t b) { + *((io_rw_8*)&sha256_hw->wdata) = b; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/rp2_common/hardware_sha256/sha256.c b/src/rp2_common/hardware_sha256/sha256.c new file mode 100644 index 000000000..0d13e3bc2 --- /dev/null +++ b/src/rp2_common/hardware_sha256/sha256.c @@ -0,0 +1,15 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/sha256.h" + +void sha256_get_result(sha256_result_t *out, enum sha256_endianness endianness) { + for (uint i = 0; i < count_of(out->words); i++) { + uint32_t data = sha256_hw->sum[i]; + if (endianness == SHA256_BIG_ENDIAN) data = __builtin_bswap32(data); + out->words[i] = data; + } +} diff --git a/src/rp2_common/hardware_spi/BUILD.bazel b/src/rp2_common/hardware_spi/BUILD.bazel index edbc82197..a9f0d9059 100644 --- a/src/rp2_common/hardware_spi/BUILD.bazel +++ b/src/rp2_common/hardware_spi/BUILD.bazel @@ -9,10 +9,10 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_resets", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_spi/include/hardware/spi.h b/src/rp2_common/hardware_spi/include/hardware/spi.h index 9b799fcd7..2f3b84e6b 100644 --- a/src/rp2_common/hardware_spi/include/hardware/spi.h +++ b/src/rp2_common/hardware_spi/include/hardware/spi.h @@ -11,9 +11,13 @@ #include "hardware/structs/spi.h" #include "hardware/regs/dreq.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi -#ifndef PARAM_ASSERTIONS_ENABLED_SPI -#define PARAM_ASSERTIONS_ENABLED_SPI 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI, Enable/disable assertions in the hardware_spi module, type=bool, default=0, group=hardware_spi +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI +#ifdef PARAM_ASSERTIONS_ENABLED_SPI // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI PARAM_ASSERTIONS_ENABLED_SPI +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SPI 0 +#endif #endif #ifdef __cplusplus @@ -25,7 +29,7 @@ extern "C" { * * \brief Hardware SPI API * - * RP2040 has 2 identical instances of the Serial Peripheral Interface (SPI) controller. + * RP-series microcontrollers have 2 identical instances of the Serial Peripheral Interface (SPI) controller. * * The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have * Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces. @@ -35,11 +39,11 @@ extern "C" { * Each controller can be connected to a number of GPIO pins, see the datasheet GPIO function selection table for more information. */ -// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, group=hardware_spi -// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, default=Usually provided via board header, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi +// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, default=Usually provided via board header, group=hardware_spi /** * \brief Opaque type representing an SPI instance. @@ -62,12 +66,73 @@ typedef struct spi_inst spi_inst_t; */ #define spi1 ((spi_inst_t *)spi1_hw) +/** + * \def PICO_DEFAULT_SPI_INSTANCE() + * \ingroup hardware_spi + * \hideinitializer + * \brief Returns the default SPI instance + */ #if !defined(PICO_DEFAULT_SPI_INSTANCE) && defined(PICO_DEFAULT_SPI) -#define PICO_DEFAULT_SPI_INSTANCE (__CONCAT(spi,PICO_DEFAULT_SPI)) +#define PICO_DEFAULT_SPI_INSTANCE() (__CONCAT(spi,PICO_DEFAULT_SPI)) #endif +/** + * \def PICO_DEFAULT_SPI + * \ingroup hardware_spi + * \hideinitializer + * \brief The default SPI instance number + */ + +/** + * \def PICO_DEFAULT_SPI_INSTANCE() + * \ingroup hardware_spi + * \hideinitializer + * \brief Returns the default SPI instance + */ #ifdef PICO_DEFAULT_SPI_INSTANCE -#define spi_default PICO_DEFAULT_SPI_INSTANCE +#define spi_default PICO_DEFAULT_SPI_INSTANCE() +#endif + +/** + * \def SPI_NUM(spi) + * \ingroup hardware_spi + * \hideinitializer + * \brief Returns the SPI number for a SPI instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef SPI_NUM +static_assert(NUM_SPIS == 2, ""); +#define SPI_NUM(spi) ((spi) == spi1) +#endif + +/** + * \def SPI_INSTANCE(spi_num) + * \ingroup hardware_spi + * \hideinitializer + * \brief Returns the SPI instance with the given SPI number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef SPI_INSTANCE +static_assert(NUM_SPIS == 2, ""); +#define SPI_INSTANCE(num) ((num) ? spi1 : spi0) +#endif + +/** + * \def SPI_DREQ_NUM(spi, is_tx) + * \ingroup hardware_spi + * \hideinitializer + * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from this SPI instance. + * If is_tx is true, then it is for transfers to the SPI else for transfers from the SPI. + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef SPI_DREQ_NUM +static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, ""); +static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, ""); +static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, ""); +#define SPI_DREQ_NUM(spi, is_tx) (DREQ_SPI0_TX + SPI_NUM(spi) * 2 + !(is_tx)) #endif /** \brief Enumeration of SPI CPHA (clock phase) values. @@ -115,7 +180,7 @@ uint spi_init(spi_inst_t *spi, uint baudrate); /*! \brief Deinitialise SPI instances * \ingroup hardware_spi * - * Puts the SPI into a disabled state. Init will need to be called to reenable the device + * Puts the SPI into a disabled state. Init will need to be called to re-enable the device * functions. * * \param spi SPI instance specifier, either \ref spi0 or \ref spi1 @@ -151,8 +216,8 @@ uint spi_get_baudrate(const spi_inst_t *spi); * \return Number of SPI, 0 or 1. */ static inline uint spi_get_index(const spi_inst_t *spi) { - invalid_params_if(SPI, spi != spi0 && spi != spi1); - return spi == spi1 ? 1 : 0; + invalid_params_if(HARDWARE_SPI, spi != spi0 && spi != spi1); + return SPI_NUM(spi); } static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) { @@ -177,11 +242,11 @@ static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) { * \param order Must be SPI_MSB_FIRST, no other values supported on the PL022 */ static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order) { - invalid_params_if(SPI, data_bits < 4 || data_bits > 16); + invalid_params_if(HARDWARE_SPI, data_bits < 4 || data_bits > 16); // LSB-first not supported on PL022: - invalid_params_if(SPI, order != SPI_MSB_FIRST); - invalid_params_if(SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1); - invalid_params_if(SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1); + invalid_params_if(HARDWARE_SPI, order != SPI_MSB_FIRST); + invalid_params_if(HARDWARE_SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1); + invalid_params_if(HARDWARE_SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1); // Disable the SPI uint32_t enable_mask = spi_get_hw(spi)->cr1 & SPI_SSPCR1_SSE_BITS; @@ -361,10 +426,7 @@ int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *ds * \param is_tx true for sending data to the SPI instance, false for receiving data from the SPI instance */ static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) { - static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, ""); - static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, ""); - static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, ""); - return DREQ_SPI0_TX + spi_get_index(spi) * 2 + !is_tx; + return SPI_DREQ_NUM(spi, is_tx); } #ifdef __cplusplus diff --git a/src/rp2_common/hardware_spi/spi.c b/src/rp2_common/hardware_spi/spi.c index d20c1dccd..86c79de9e 100644 --- a/src/rp2_common/hardware_spi/spi.c +++ b/src/rp2_common/hardware_spi/spi.c @@ -9,13 +9,13 @@ #include "hardware/spi.h" static inline void spi_reset(spi_inst_t *spi) { - invalid_params_if(SPI, spi != spi0 && spi != spi1); - reset_block(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS); + invalid_params_if(HARDWARE_SPI, spi != spi0 && spi != spi1); + reset_block_num(spi == spi0 ? RESET_SPI0 : RESET_SPI1); } static inline void spi_unreset(spi_inst_t *spi) { - invalid_params_if(SPI, spi != spi0 && spi != spi1); - unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS); + invalid_params_if(HARDWARE_SPI, spi != spi0 && spi != spi1); + unreset_block_num_wait_blocking(spi == spi0 ? RESET_SPI0 : RESET_SPI1); } uint spi_init(spi_inst_t *spi, uint baudrate) { @@ -42,7 +42,7 @@ void spi_deinit(spi_inst_t *spi) { uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) { uint freq_in = clock_get_hz(clk_peri); uint prescale, postdiv; - invalid_params_if(SPI, baudrate > freq_in); + invalid_params_if(HARDWARE_SPI, baudrate > freq_in); // Disable the SPI uint32_t enable_mask = spi_get_hw(spi)->cr1 & SPI_SSPCR1_SSE_BITS; @@ -54,7 +54,7 @@ uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) { if (freq_in < prescale * 256 * (uint64_t) baudrate) break; } - invalid_params_if(SPI, prescale > 254); // Frequency too low + invalid_params_if(HARDWARE_SPI, prescale > 254); // Frequency too low // Find largest post-divide which makes output <= baudrate. Post-divide is // an integer in the range 1 to 256 inclusive. @@ -82,7 +82,7 @@ uint spi_get_baudrate(const spi_inst_t *spi) { // Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst. // Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit) int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) { - invalid_params_if(SPI, 0 > (int)len); + invalid_params_if(HARDWARE_SPI, 0 > (int)len); // Never have more transfers in flight than will fit into the RX FIFO, // else FIFO will overflow if this code is heavily interrupted. @@ -105,7 +105,7 @@ int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t // Write len bytes directly from src to the SPI, and discard any data received back int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, size_t len) { - invalid_params_if(SPI, 0 > (int)len); + invalid_params_if(HARDWARE_SPI, 0 > (int)len); // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX // is full, PL022 inhibits RX pushes, and sets a sticky flag on // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set. @@ -134,7 +134,7 @@ int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, // Generally this can be 0, but some devices require a specific value here, // e.g. SD cards expect 0xff int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len) { - invalid_params_if(SPI, 0 > (int)len); + invalid_params_if(HARDWARE_SPI, 0 > (int)len); const size_t fifo_depth = 8; size_t rx_remaining = len, tx_remaining = len; @@ -154,7 +154,7 @@ int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_ // Write len halfwords from src to SPI. Simultaneously read len halfwords from SPI to dst. int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len) { - invalid_params_if(SPI, 0 > (int)len); + invalid_params_if(HARDWARE_SPI, 0 > (int)len); // Never have more transfers in flight than will fit into the RX FIFO, // else FIFO will overflow if this code is heavily interrupted. const size_t fifo_depth = 8; @@ -176,7 +176,7 @@ int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint // Write len bytes directly from src to the SPI, and discard any data received back int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *src, size_t len) { - invalid_params_if(SPI, 0 > (int)len); + invalid_params_if(HARDWARE_SPI, 0 > (int)len); // Deliberately overflow FIFO, then clean up afterward, to minimise amount // of APB polling required per halfword for (size_t i = 0; i < len; ++i) { @@ -201,7 +201,7 @@ int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *s // Read len halfwords directly from the SPI to dst. // repeated_tx_data is output repeatedly on SO as data is read in from SI. int __not_in_flash_func(spi_read16_blocking)(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len) { - invalid_params_if(SPI, 0 > (int)len); + invalid_params_if(HARDWARE_SPI, 0 > (int)len); const size_t fifo_depth = 8; size_t rx_remaining = len, tx_remaining = len; diff --git a/src/rp2_common/hardware_sync/BUILD.bazel b/src/rp2_common/hardware_sync/BUILD.bazel index ebf7608c6..dda157314 100644 --- a/src/rp2_common/hardware_sync/BUILD.bazel +++ b/src/rp2_common/hardware_sync/BUILD.bazel @@ -3,31 +3,36 @@ load("//bazel:defs.bzl", "compatible_with_rp2") package(default_visibility = ["//visibility:public"]) # This exists to break a dependency cycle between -# this library and //src/rp2_common/hardware_claim. +# this library and //src/common/hardware_claim. # Application code should always use :hardware_sync instead. cc_library( name = "hardware_sync_headers", hdrs = ["include/hardware/sync.h"], includes = ["include"], target_compatible_with = compatible_with_rp2(), - visibility = ["//src/rp2_common/hardware_claim:__pkg__"], + visibility = [ + "//src/common/hardware_claim:__pkg__", + "//src/common/pico_sync:__pkg__", + "//src/rp2_common/hardware_sync_spin_lock:__pkg__", + ], deps = [ - "//src/common/pico_base:pico_base_interface", "//src/rp2_common/hardware_base", - "//src/rp2_common/pico_platform:hardware_regs", ], ) cc_library( name = "hardware_sync", srcs = ["sync.c"], - hdrs = ["include/hardware/sync.h"], - includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", + ":hardware_sync_headers", + "//src/common/hardware_claim", + "//src/common/pico_base_headers", + "//src/common/pico_sync:pico_sync_headers", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", "//src/rp2_common/hardware_base", - "//src/rp2_common/hardware_claim", - "//src/rp2_common/pico_platform:hardware_regs", + "//src/rp2_common/hardware_sync_spin_lock", + "//src/rp2_common/hardware_sync_spin_lock:hardware_sync_spin_lock_headers", ], ) diff --git a/src/rp2_common/hardware_sync/CMakeLists.txt b/src/rp2_common/hardware_sync/CMakeLists.txt index 1c64ed61a..20ecb761a 100644 --- a/src/rp2_common/hardware_sync/CMakeLists.txt +++ b/src/rp2_common/hardware_sync/CMakeLists.txt @@ -1 +1,3 @@ pico_simple_hardware_target(sync) + +pico_mirrored_target_link_libraries(hardware_sync INTERFACE hardware_sync_spin_lock) diff --git a/src/rp2_common/hardware_sync/include/hardware/sync.h b/src/rp2_common/hardware_sync/include/hardware/sync.h index 44bbc302c..474b27936 100644 --- a/src/rp2_common/hardware_sync/include/hardware/sync.h +++ b/src/rp2_common/hardware_sync/include/hardware/sync.h @@ -9,7 +9,10 @@ #include "pico.h" #include "hardware/address_mapped.h" -#include "hardware/regs/sio.h" + +#ifdef __riscv +#include "hardware/hazard3.h" +#endif #ifdef __cplusplus extern "C" { @@ -23,7 +26,7 @@ extern "C" { * Spin Locks * ---------- * - * The RP2040 provides 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software + * The RP-series microcontrollers provide 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software * and hardware resources. * * Generally each spin lock itself is a shared resource, @@ -34,6 +37,11 @@ extern "C" { * methods here (e.g. \ref spin_lock_blocking) always disable interrupts while the lock is held as use by IRQ handlers and user code is common/desirable, * and spin locks are only expected to be held for brief periods. * + * \if rp2350_specific + * RP2350 Warning. Due to erratum RP2350-E2, writes to new SIO registers above an offset of +0x180 alias the spinlocks, causing spurious lock releases. + * This SDK by default uses atomic memory accesses to implement the hardware_sync_spin_lock API, as a workaround on RP2350 A2. + * \endif + * * The SDK uses the following default spin lock assignments, classifying which spin locks are reserved for exclusive/special purposes * vs those suitable for more general shared use: * @@ -45,69 +53,33 @@ extern "C" { * 24-31 | (\ref PICO_SPINLOCK_ID_CLAIM_FREE_FIRST - \ref PICO_SPINLOCK_ID_CLAIM_FREE_LAST). These are reserved for exclusive use and are allocated on a first come first served basis at runtime via \ref spin_lock_claim_unused() */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync -#ifndef PARAM_ASSERTIONS_ENABLED_SYNC -#define PARAM_ASSERTIONS_ENABLED_SYNC 0 -#endif - -/** \brief A spin lock identifier - * \ingroup hardware_sync - */ -typedef volatile uint32_t spin_lock_t; - -// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_IRQ -#define PICO_SPINLOCK_ID_IRQ 9 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_TIMER -#define PICO_SPINLOCK_ID_TIMER 10 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM -#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_RAND, Spinlock ID for Random Number Generator, min=0, max=31, default=12, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_RAND -#define PICO_SPINLOCK_ID_RAND 12 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_OS1 -#define PICO_SPINLOCK_ID_OS1 14 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC, Enable/disable assertions in the hardware_sync module, type=bool, default=0, group=hardware_sync +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC +#ifdef PARAM_ASSERTIONS_ENABLED_SYNC // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC PARAM_ASSERTIONS_ENABLED_SYNC +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SYNC 0 #endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_OS2 -#define PICO_SPINLOCK_ID_OS2 15 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST -#define PICO_SPINLOCK_ID_STRIPED_FIRST 16 -#endif - -// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_STRIPED_LAST -#define PICO_SPINLOCK_ID_STRIPED_LAST 23 #endif -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST -#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 +/*! \brief Insert a NOP instruction in to the code path. + * \ingroup hardware_sync + * + * NOP does nothing for one cycle. On RP2350 Arm binaries this is forced to be + * a 32-bit instruction to avoid dual-issue of NOPs. + */ +__force_inline static void __nop(void) { +#if !__ARM_ARCH_6M__ +#ifdef __riscv + __asm volatile ("nop"); +#else + __asm volatile ("nop.w"); #endif - -#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END -#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST +#else + __asm volatile ("nop"); #endif +} -// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync -#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST -#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31 -#endif /*! \brief Insert a SEV instruction in to the code path. * \ingroup hardware_sync @@ -116,7 +88,11 @@ typedef volatile uint32_t spin_lock_t; */ #if !__has_builtin(__sev) __force_inline static void __sev(void) { +#ifdef __riscv + __hazard3_unblock(); +#else pico_default_asm_volatile ("sev"); +#endif } #endif @@ -128,7 +104,11 @@ __force_inline static void __sev(void) { */ #if !__has_builtin(__wfe) __force_inline static void __wfe(void) { +#ifdef __riscv + __hazard3_block(); +#else pico_default_asm_volatile ("wfe"); +#endif } #endif @@ -150,7 +130,11 @@ __force_inline static void __wfi(void) { * instruction will be observed before any explicit access after the instruction. */ __force_inline static void __dmb(void) { - pico_default_asm_volatile("dmb" : : : "memory"); +#ifdef __riscv + __asm volatile ("fence rw, rw" : : : "memory"); +#else + pico_default_asm_volatile ("dmb" : : : "memory"); +#endif } /*! \brief Insert a DSB instruction in to the code path. @@ -161,7 +145,11 @@ __force_inline static void __dmb(void) { * accesses before this instruction complete. */ __force_inline static void __dsb(void) { - pico_default_asm_volatile("dsb" : : : "memory"); +#ifdef __riscv + __asm volatile ("fence rw, rw" : : : "memory"); +#else + pico_default_asm_volatile ("dsb" : : : "memory"); +#endif } /*! \brief Insert a ISB instruction in to the code path. @@ -172,7 +160,11 @@ __force_inline static void __dsb(void) { * the ISB instruction has been completed. */ __force_inline static void __isb(void) { +#ifdef __riscv + __asm volatile ("fence.i" : : : "memory"); +#else pico_default_asm_volatile("isb" ::: "memory"); +#endif } /*! \brief Acquire a memory fence @@ -213,10 +205,17 @@ __force_inline static void __mem_fence_release(void) { */ __force_inline static uint32_t save_and_disable_interrupts(void) { uint32_t status; - pico_default_asm_volatile( +#ifdef __riscv + pico_default_asm_volatile ( + "csrrci %0, mstatus, 0x8\n" + : "=r" (status) :: "memory" + ); +#else + pico_default_asm_volatile ( "mrs %0, PRIMASK\n" "cpsid i" - : "=r" (status) ::); + : "=r" (status) :: "memory"); +#endif return status; } @@ -226,112 +225,41 @@ __force_inline static uint32_t save_and_disable_interrupts(void) { * \param status Previous interrupt status from save_and_disable_interrupts() */ __force_inline static void restore_interrupts(uint32_t status) { - pico_default_asm_volatile("msr PRIMASK,%0"::"r" (status) : ); -} - -/*! \brief Get HW Spinlock instance from number - * \ingroup hardware_sync - * - * \param lock_num Spinlock ID - * \return The spinlock instance - */ -__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) { - invalid_params_if(SYNC, lock_num >= NUM_SPIN_LOCKS); - return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4); -} - -/*! \brief Get HW Spinlock number from instance - * \ingroup hardware_sync - * - * \param lock The Spinlock instance - * \return The Spinlock ID - */ -__force_inline static uint spin_lock_get_num(spin_lock_t *lock) { - invalid_params_if(SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET || - (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET || - ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0); - return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET)); -} - -/*! \brief Acquire a spin lock without disabling interrupts (hence unsafe) - * \ingroup hardware_sync - * - * \param lock Spinlock instance - */ -__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { - // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run - // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core - // anyway which should be finished soon - while (__builtin_expect(!*lock, 0)) { // read from spinlock register (tries to acquire the lock) - tight_loop_contents(); +#ifdef __riscv + __compiler_memory_barrier(); + if (status & 0x8) { + riscv_set_csr(mstatus, 8); + } else { + riscv_clear_csr(mstatus, 8); } - __mem_fence_acquire(); -} - -/*! \brief Release a spin lock without re-enabling interrupts - * \ingroup hardware_sync - * - * \param lock Spinlock instance - */ -__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) { - __mem_fence_release(); - *lock = 0; // write to spinlock register (release lock) -} - -/*! \brief Acquire a spin lock safely - * \ingroup hardware_sync - * - * This function will disable interrupts prior to acquiring the spinlock - * - * \param lock Spinlock instance - * \return interrupt status to be used when unlocking, to restore to original state - */ -__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { - uint32_t save = save_and_disable_interrupts(); - spin_lock_unsafe_blocking(lock); - return save; -} - -/*! \brief Check to see if a spinlock is currently acquired elsewhere. - * \ingroup hardware_sync - * - * \param lock Spinlock instance - */ -inline static bool is_spin_locked(spin_lock_t *lock) { - check_hw_size(spin_lock_t, 4); - uint lock_num = spin_lock_get_num(lock); - return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num)); + __compiler_memory_barrier(); +#else + pico_default_asm_volatile ("msr PRIMASK,%0"::"r" (status) : "memory" ); +#endif } -/*! \brief Release a spin lock safely +/*! \brief Restore interrupts to a specified state with restricted transitions * \ingroup hardware_sync * - * This function will re-enable interrupts according to the parameters. - * - * \param lock Spinlock instance - * \param saved_irq Return value from the \ref spin_lock_blocking() function. + * This method should only be used when the interrupt state is known to be disabled, + * e.g. when paired with \ref save_and_disable_interrupts() * - * \sa spin_lock_blocking() - */ -__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { - spin_unlock_unsafe(lock); - restore_interrupts(saved_irq); + * \param status Previous interrupt status from save_and_disable_interrupts() + */ +__force_inline static void restore_interrupts_from_disabled(uint32_t status) { +#ifdef __riscv + // on RISC-V this can enable interrupts, but not disable interrupts... which + // is the common case and doesn't require a branch + __compiler_memory_barrier(); + riscv_set_csr(mstatus, status & 8); + __compiler_memory_barrier(); +#else + // on ARM, this behaves the same as restore_interrupts() + pico_default_asm_volatile ("msr PRIMASK,%0"::"r" (status) : "memory" ); +#endif } -/*! \brief Initialise a spin lock - * \ingroup hardware_sync - * - * The spin lock is initially unlocked - * - * \param lock_num The spin lock number - * \return The spin lock instance - */ -spin_lock_t *spin_lock_init(uint lock_num); - -/*! \brief Release all spin locks - * \ingroup hardware_sync - */ -void spin_locks_reset(void); +#include "hardware/sync/spin_lock.h" /*! \brief Return a spin lock number from the _striped_ range * \ingroup hardware_sync @@ -400,7 +328,13 @@ int spin_lock_claim_unused(bool required); bool spin_lock_is_claimed(uint lock_num); // no longer use __mem_fence_acquire here, as it is overkill on cortex M0+ +#if PICO_C_COMPILER_IS_GNU +#define remove_volatile_cast(t, x) (t)(x) +#define remove_volatile_cast_no_barrier(t, x) (t)(x) +#else #define remove_volatile_cast(t, x) ({__compiler_memory_barrier(); Clang_Pragma("clang diagnostic push"); Clang_Pragma("clang diagnostic ignored \"-Wcast-qual\""); (t)(x); Clang_Pragma("clang diagnostic pop"); }) +#define remove_volatile_cast_no_barrier(t, x) ({ Clang_Pragma("clang diagnostic push"); Clang_Pragma("clang diagnostic ignored \"-Wcast-qual\""); (t)(x); Clang_Pragma("clang diagnostic pop"); }) +#endif #ifdef __cplusplus } diff --git a/src/rp2_common/hardware_sync/sync.c b/src/rp2_common/hardware_sync/sync.c index a15c8d623..e0fbd2bb2 100644 --- a/src/rp2_common/hardware_sync/sync.c +++ b/src/rp2_common/hardware_sync/sync.c @@ -12,23 +12,10 @@ static uint8_t striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST; static uint32_t claimed; static void check_lock_num(uint __unused lock_num) { - invalid_params_if(SYNC, lock_num >= 32); + invalid_params_if(HARDWARE_SYNC, lock_num >= 32); } -void spin_locks_reset(void) { - for (uint i = 0; i < NUM_SPIN_LOCKS; i++) { - spin_unlock_unsafe(spin_lock_instance(i)); - } -} - -spin_lock_t *spin_lock_init(uint lock_num) { - assert(lock_num < NUM_SPIN_LOCKS); - spin_lock_t *lock = spin_lock_instance(lock_num); - spin_unlock_unsafe(lock); - return lock; -} - -uint next_striped_spin_lock_num() { +uint next_striped_spin_lock_num(void) { uint rc = striped_spin_lock_num++; if (striped_spin_lock_num > PICO_SPINLOCK_ID_STRIPED_LAST) { striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST; diff --git a/src/rp2_common/hardware_sync_spin_lock/BUILD.bazel b/src/rp2_common/hardware_sync_spin_lock/BUILD.bazel new file mode 100644 index 000000000..87a1edc50 --- /dev/null +++ b/src/rp2_common/hardware_sync_spin_lock/BUILD.bazel @@ -0,0 +1,28 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "hardware_sync_spin_lock_headers", + hdrs = ["include/hardware/sync/spin_lock.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + visibility = [ + "//src/common/pico_sync:__pkg__", + "//src/rp2_common/hardware_sync:__pkg__", + ], + deps = [ + "//src/common/pico_base_headers", + ], +) + +cc_library( + name = "hardware_sync_spin_lock", + srcs = ["sync_spin_lock.c"], + deps = [ + ":hardware_sync_spin_lock_headers", + "//src/common/pico_sync:pico_sync_headers", + "//src/rp2_common/hardware_sync:hardware_sync_headers", + "//src/rp2_common/pico_runtime_init", + ], +) diff --git a/src/rp2_common/hardware_sync_spin_lock/CMakeLists.txt b/src/rp2_common/hardware_sync_spin_lock/CMakeLists.txt new file mode 100644 index 000000000..242771863 --- /dev/null +++ b/src/rp2_common/hardware_sync_spin_lock/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(sync_spin_lock) diff --git a/src/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h b/src/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h new file mode 100644 index 000000000..6885efd79 --- /dev/null +++ b/src/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_SYNC_SPIN_LOCK_H +#define _HARDWARE_SYNC_SPIN_LOCK_H + +#include "pico.h" +#include "hardware/sync.h" + +// PICO_CONFIG: PICO_USE_SW_SPIN_LOCKS, Use software implementation for spin locks, type=bool, default=1 on RP2350 due to errata, group=hardware_sync +#ifndef PICO_USE_SW_SPIN_LOCKS +#if PICO_RP2350 +#define PICO_USE_SW_SPIN_LOCKS 1 +#endif +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_IRQ +#define PICO_SPINLOCK_ID_IRQ 9 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_TIMER +#define PICO_SPINLOCK_ID_TIMER 10 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM +#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_RAND, Spinlock ID for Random Number Generator, min=0, max=31, default=12, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_RAND +#define PICO_SPINLOCK_ID_RAND 12 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_ATOMIC, Spinlock ID for atomics, min=0, max=31, default=13, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_ATOMIC +#define PICO_SPINLOCK_ID_ATOMIC 13 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS1 +#define PICO_SPINLOCK_ID_OS1 14 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_OS2 +#define PICO_SPINLOCK_ID_OS2 15 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST +#define PICO_SPINLOCK_ID_STRIPED_FIRST 16 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_STRIPED_LAST +#define PICO_SPINLOCK_ID_STRIPED_LAST 23 +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST +#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24 +#endif + +#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END +#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST +#endif + +// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync +#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST +#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31 +#endif + +/** \brief A spin lock identifier + * \ingroup hardware_sync + */ +#if !PICO_USE_SW_SPIN_LOCKS +// Hardware lock flag in SIO: +typedef io_rw_32 spin_lock_t; +#else +#ifndef SW_SPIN_LOCK_TYPE +// Byte flag in memory: +#define SW_SPIN_LOCK_TYPE volatile uint8_t +#endif +typedef SW_SPIN_LOCK_TYPE spin_lock_t; +#endif + +#if PICO_USE_SW_SPIN_LOCKS +#ifndef SW_SPIN_LOCK_INSTANCE +#define SW_SPIN_LOCK_INSTANCE(lock_num) ({ \ + extern spin_lock_t _sw_spin_locks[NUM_SPIN_LOCKS]; \ + &_sw_spin_locks[lock_num]; \ + }) +#endif + +#ifndef SW_SPIN_LOCK_NUM +#define SW_SPIN_LOCK_NUM(lock) ({ \ + extern spin_lock_t _sw_spin_locks[NUM_SPIN_LOCKS]; \ + (lock) - _sw_spin_locks; \ + }) +#endif + +#ifndef SW_SPIN_LOCK_IS_LOCKED +#define SW_SPIN_LOCK_IS_LOCKED(lock) ((bool) *(lock)) +#endif + +#ifndef SW_SPIN_LOCK_LOCK +#if __ARM_ARCH_8M_MAIN__ +#define SW_SPIN_LOCK_LOCK(lock) ({ \ + uint32_t _tmp0, _tmp1; \ + pico_default_asm_volatile ( \ + "1:\n" \ + "ldaexb %1, [%2]\n" \ + "movs %0, #1\n" /* fill dependency slot */ \ + "cmp %1, #0\n" \ + /* Immediately retry if lock is seen to be taken */ \ + "bne 1b\n" \ + /* Attempt to claim */ \ + "strexb %1, %0, [%2]\n" \ + "cmp %1, #0\n" \ + /* Claim failed due to intervening write, so retry */ \ + "bne 1b\n" \ + : "=&r" (_tmp0), "=&r" (_tmp1) : "r" (lock) \ + ); \ + __mem_fence_acquire(); \ + }) +#elif __riscv && (defined(__riscv_a) || defined(__riscv_zaamo)) +#define SW_SPIN_LOCK_LOCK(lock) ({ \ + uint32_t _tmp0, _tmp1; \ + pico_default_asm_volatile ( \ + /* Get word address, and bit mask for LSB of the */ \ + /* correct byte within that word -- note shamt is modulo xlen: */ \ + "slli %1, %0, 3\n" \ + "bset %1, zero, %1\n" \ + "andi %0, %0, -4\n" \ + /* Repeatedly set the bit until we see that it was clear at the */ \ + /* point we set it. A set from 0 -> 1 is a successful lock take. */ \ + "1:" \ + "amoor.w.aq %2, %1, (%0)\n" \ + "and %2, %2, %1\n" \ + "bnez %2, 1b\n" \ + : "+r" (lock), "=r" (_tmp0), "=r" (_tmp1) \ + ); \ + __mem_fence_acquire(); \ + }) +#else +#error no SW_SPIN_TRY_LOCK available for PICO_USE_SW_SPIN_LOCK on this platform +#endif +#endif + +#ifndef SW_SPIN_TRY_LOCK +#if __ARM_ARCH_8M_MAIN__ +#define SW_SPIN_TRY_LOCK(lock) ({ \ + uint32_t _tmp0, _tmp1; \ + pico_default_asm_volatile ( \ + "ldaexb %1, [%2]\n" \ + "movs %0, #1\n" /* fill dependency slot */ \ + "cmp %1, #0\n" \ + /* Immediately give up if lock is seen to be taken */ \ + "bne 1f\n" \ + /* Otherwise attempt to claim, once. */ \ + "strexb %1, %0, [%2]\n" \ + "1:\n" \ + : "=&r" (_tmp0), "=&r" (_tmp1) : "r" (lock) \ + ); \ + __mem_fence_acquire(); \ + !_tmp1; \ + }) +#elif __riscv && (defined(__riscv_a) || defined(__riscv_zaamo)) +#define SW_SPIN_TRY_LOCK(lock) ({ \ + uint32_t _tmp0; \ + pico_default_asm_volatile ( \ + /* Get word address, and bit mask for LSB of the */ \ + /* correct byte within that word -- note shamt is modulo xlen: */ \ + "slli %1, %0, 3\n" \ + "bset %1, zero, %1\n" \ + "andi %0, %0, -4\n" \ + /* Set the bit. If it was clear at the point we set it, then we took */ \ + /* the lock. Otherwise the lock was already held, and we give up. */ \ + "amoor.w.aq %0, %1, (%0)\n" \ + "and %1, %1, %0\n" \ + : "+r" (lock), "=r" (_tmp0) \ + ); \ + __mem_fence_acquire(); \ + !_tmp0; \ + }) +#else +#error no SW_SPIN_TRY_LOCK available for PICO_USE_SW_SPIN_LOCK on this platform +#endif +#endif + +#ifndef SW_SPIN_LOCK_UNLOCK +#if __ARM_ARCH_8M_MAIN__ +#define SW_SPIN_LOCK_UNLOCK(lock) ({ \ + /* Release-ordered store is available: use instead of separate fence */ \ + uint32_t zero = 0; \ + pico_default_asm_volatile( \ + "stlb %0, [%1]\n" \ + : : "r" (zero), "r" (lock) \ + ); \ + }) +#elif __riscv +#define SW_SPIN_LOCK_UNLOCK(lock) ({ \ + __mem_fence_release(); \ + *(lock) = 0; /* write to spinlock register (release lock) */ \ + }) +#else +#error no SW_SPIN_TRY_LOCK available for PICO_USE_SW_SPIN_LOCK on this platform +#endif +#endif + +#endif + +/*! \brief Get HW Spinlock instance from number + * \ingroup hardware_sync + * + * \param lock_num Spinlock ID + * \return The spinlock instance + */ +__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) { + invalid_params_if(HARDWARE_SYNC, lock_num >= NUM_SPIN_LOCKS); +#if PICO_USE_SW_SPIN_LOCKS + return SW_SPIN_LOCK_INSTANCE(lock_num); +#else + return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4); +#endif +} + +/*! \brief Get HW Spinlock number from instance + * \ingroup hardware_sync + * + * \param lock The Spinlock instance + * \return The Spinlock ID + */ +__force_inline static uint spin_lock_get_num(spin_lock_t *lock) { +#if PICO_USE_SW_SPIN_LOCKS + uint lock_num = SW_SPIN_LOCK_NUM(lock); + invalid_params_if(HARDWARE_SYNC, lock_num >= (uint)NUM_SPIN_LOCKS); + return lock_num; +#else + invalid_params_if(HARDWARE_SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET || + (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET || + ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0); + return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET)); +#endif +} + +/*! \brief Acquire a spin lock without disabling interrupts (hence unsafe) + * \ingroup hardware_sync + * + * \param lock Spinlock instance + */ +__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) { + // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run + // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core + // anyway which should be finished soon +#if PICO_USE_SW_SPIN_LOCKS + SW_SPIN_LOCK_LOCK(lock); +#else + while (__builtin_expect(!*lock, 0)) { // read from spinlock register (tries to acquire the lock) + tight_loop_contents(); + } + __mem_fence_acquire(); +#endif +} + +__force_inline static bool spin_try_lock_unsafe(spin_lock_t *lock) { +#if PICO_USE_SW_SPIN_LOCKS + return SW_SPIN_TRY_LOCK(lock); +#else + return *lock; +#endif +} +/*! \brief Release a spin lock without re-enabling interrupts + * \ingroup hardware_sync + * + * \param lock Spinlock instance + */ +__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) { +#if PICO_USE_SW_SPIN_LOCKS + SW_SPIN_LOCK_UNLOCK(lock); +#else + __mem_fence_release(); + *lock = 0; // write to spinlock register (release lock) +#endif +} + +/*! \brief Acquire a spin lock safely + * \ingroup hardware_sync + * + * This function will disable interrupts prior to acquiring the spinlock + * + * \param lock Spinlock instance + * \return interrupt status to be used when unlocking, to restore to original state + */ +__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) { + uint32_t save = save_and_disable_interrupts(); + spin_lock_unsafe_blocking(lock); + return save; +} + +/*! \brief Check to see if a spinlock is currently acquired elsewhere. + * \ingroup hardware_sync + * + * \param lock Spinlock instance + */ +inline static bool is_spin_locked(spin_lock_t *lock) { +#if PICO_USE_SW_SPIN_LOCKS + return SW_SPIN_LOCK_IS_LOCKED(lock); +#else + check_hw_size(spin_lock_t, 4); + uint lock_num = spin_lock_get_num(lock); + return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num)); +#endif +} + +/*! \brief Release a spin lock safely + * \ingroup hardware_sync + * + * This function will re-enable interrupts according to the parameters. + * + * \param lock Spinlock instance + * \param saved_irq Return value from the \ref spin_lock_blocking() function. + * + * \sa spin_lock_blocking() + */ +__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) { + spin_unlock_unsafe(lock); + restore_interrupts_from_disabled(saved_irq); +} + +/*! \brief Initialise a spin lock + * \ingroup hardware_sync + * + * The spin lock is initially unlocked + * + * \param lock_num The spin lock number + * \return The spin lock instance + */ +spin_lock_t *spin_lock_init(uint lock_num); + +/*! \brief Release all spin locks + * \ingroup hardware_sync + */ +void spin_locks_reset(void); + +#endif diff --git a/src/rp2_common/hardware_sync_spin_lock/sync_spin_lock.c b/src/rp2_common/hardware_sync_spin_lock/sync_spin_lock.c new file mode 100644 index 000000000..82ac8b9c2 --- /dev/null +++ b/src/rp2_common/hardware_sync_spin_lock/sync_spin_lock.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "hardware/sync/spin_lock.h" + +void spin_locks_reset(void) { + for (uint i = 0; i < NUM_SPIN_LOCKS; i++) { + spin_unlock_unsafe(spin_lock_instance(i)); + } +} + +spin_lock_t *spin_lock_init(uint lock_num) { + assert(lock_num < NUM_SPIN_LOCKS); + spin_lock_t *lock = spin_lock_instance(lock_num); + spin_unlock_unsafe(lock); + return lock; +} + +#if PICO_USE_SW_SPIN_LOCKS +spin_lock_t _sw_spin_locks[NUM_SPIN_LOCKS]; + +#if __ARM_ARCH_8M_MAIN__ && !PICO_SW_SPIN_LOCKS_NO_EXTEXCLALL +#include "pico/runtime_init.h" +#include "hardware/structs/m33.h" + +static void spinlock_set_extexclall(void) { + // Force use of global exclusive monitor for all exclusive load/stores: + // makes multicore exclusives work without adding MPU regions. For + // something more exotic, like having multicore exclusives in internal + // SRAM and also single-core exclusives in external PSRAM (not covered by + // the global monitor on RP2350) you must clear this and add your own + // Shareable regions. + // + // Setting PICO_SW_SPIN_LOCKS_NO_EXTEXCLALL == 1 will disable this code + m33_hw->actlr |= M33_ACTLR_EXTEXCLALL_BITS; +} + +// PICO_RUNTIME_INIT_SPIN_LOCKS_RESET is fine as resetting them does not require EXTEXCLALL +PICO_RUNTIME_INIT_FUNC_PER_CORE(spinlock_set_extexclall, PICO_RUNTIME_INIT_SPIN_LOCKS_RESET); +#endif +#endif + diff --git a/src/rp2_common/hardware_ticks/BUILD.bazel b/src/rp2_common/hardware_ticks/BUILD.bazel new file mode 100644 index 000000000..df4869455 --- /dev/null +++ b/src/rp2_common/hardware_ticks/BUILD.bazel @@ -0,0 +1,25 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +# Break a circular dependency with hardware_watchdog. +cc_library( + name = "hardware_ticks_headers", + hdrs = ["include/hardware/ticks.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + visibility = ["//src/rp2_common/hardware_watchdog:__pkg__"], +) + +cc_library( + name = "hardware_ticks", + srcs = ["ticks.c"], + hdrs = ["include/hardware/ticks.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", + "//src/rp2_common/hardware_watchdog", + ], +) diff --git a/src/rp2_common/hardware_ticks/CMakeLists.txt b/src/rp2_common/hardware_ticks/CMakeLists.txt new file mode 100644 index 000000000..de49a9d78 --- /dev/null +++ b/src/rp2_common/hardware_ticks/CMakeLists.txt @@ -0,0 +1 @@ +pico_simple_hardware_target(ticks) \ No newline at end of file diff --git a/src/rp2_common/hardware_ticks/include/hardware/ticks.h b/src/rp2_common/hardware_ticks/include/hardware/ticks.h new file mode 100644 index 000000000..a7c7d5998 --- /dev/null +++ b/src/rp2_common/hardware_ticks/include/hardware/ticks.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_TICKS_H +#define _HARDWARE_TICKS_H + +/** \file hardware/tick.h + * \defgroup hardware_ticks hardware_ticks + * + * \brief Hardware Tick API + * + * \if rp2040_specific + * RP2040 only has one tick generator, and it is part of the watchdog hardware. + * \endif + * + * \if rp2350_specific + * The RP2350 has a dedicated Tick block that is used to supply ticks to TIMER0, TIMER1, + * RISC-V platform timer, Arm Cortex-M33 0 timer, Arm Cortex-M33 1 timer and the WATCHDOG block. + * \endif + */ + +#include "pico.h" +#if !PICO_RP2040 +#include "hardware/structs/ticks.h" +#else +#include "hardware/watchdog.h" +/*! \brief Tick generator numbers on RP2040 (used as typedef \ref tick_gen_num_t) + * \ingroup hardware_ticks + * + * RP2040 only has one tick generator, and it is part of the watchdog hardware + */ +typedef enum tick_gen_num_rp2040 { + TICK_WATCHDOG = 0, + TICK_COUNT +} tick_gen_num_t; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_TICKS, Enable/disable assertions in the hardware_ticks module, type=bool, default=0, group=hardware_ticks +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_TICKS +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TICKS 0 +#endif + +/*! \brief Start a tick generator + * \ingroup hardware_ticks + * + * \param tick The tick generator number + * \param cycles The number of clock cycles per tick + */ +void tick_start(tick_gen_num_t tick, uint cycles); + + +/*! \brief Stop a tick generator + * \ingroup hardware_ticks + * + * \param tick The tick generator number + */ +void tick_stop(tick_gen_num_t tick); + +/*! \brief Check if a tick genererator is currently running + * \ingroup hardware_ticks + * + * \param tick The tick generator number + * \return true if the specific ticker is running. + */ +bool tick_is_running(tick_gen_num_t tick); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/rp2_common/hardware_ticks/ticks.c b/src/rp2_common/hardware_ticks/ticks.c new file mode 100644 index 000000000..484602838 --- /dev/null +++ b/src/rp2_common/hardware_ticks/ticks.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hardware/ticks.h" + +void tick_start(tick_gen_num_t tick, uint cycles) { + valid_params_if(HARDWARE_TICKS, tick < TICK_COUNT); +#if PICO_RP2040 + ((void)tick); + cycles <<= WATCHDOG_TICK_CYCLES_LSB; + valid_params_if(HARDWARE_TICKS, cycles <= WATCHDOG_TICK_CYCLES_BITS); + // On RP2040, this also provides a tick reference to the timer and SysTick + watchdog_hw->tick = cycles | WATCHDOG_TICK_ENABLE_BITS; +#else + cycles <<= TICKS_WATCHDOG_CYCLES_LSB; + valid_params_if(HARDWARE_TICKS, cycles <= TICKS_WATCHDOG_CYCLES_BITS); + // On later hardware, separate tick generators for every tick destination. + ticks_hw->ticks[tick].cycles = cycles; + ticks_hw->ticks[tick].ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS; +#endif +} + +void tick_stop(tick_gen_num_t tick) { + valid_params_if(HARDWARE_TICKS, tick < TICK_COUNT); +#if PICO_RP2040 + ((void)tick); + hw_clear_bits(&watchdog_hw->tick, WATCHDOG_TICK_ENABLE_BITS); +#else + hw_clear_bits(&ticks_hw->ticks[tick].ctrl, TICKS_WATCHDOG_CTRL_ENABLE_BITS); +#endif +} + +bool tick_is_running(tick_gen_num_t tick) { + valid_params_if(HARDWARE_TICKS, tick < TICK_COUNT); +#if PICO_RP2040 + ((void)tick); + return watchdog_hw->tick & WATCHDOG_TICK_ENABLE_BITS; +#else + // On later hardware, separate tick generators for every tick destination. + return ticks_hw->ticks[tick].ctrl & TICKS_WATCHDOG_CTRL_RUNNING_BITS; +#endif +} \ No newline at end of file diff --git a/src/rp2_common/hardware_timer/BUILD.bazel b/src/rp2_common/hardware_timer/BUILD.bazel index 1b76b7785..2cdfe62b4 100644 --- a/src/rp2_common/hardware_timer/BUILD.bazel +++ b/src/rp2_common/hardware_timer/BUILD.bazel @@ -12,8 +12,8 @@ cc_library( target_compatible_with = compatible_with_rp2(), visibility = ["//src/common/pico_time:__pkg__"], deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", ], ) @@ -24,10 +24,10 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/rp2_common/hardware_claim", + "//src/common/hardware_claim", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_sync", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/hardware_timer/include/hardware/timer.h b/src/rp2_common/hardware_timer/include/hardware/timer.h index 8a63585b3..4f57c2bd8 100644 --- a/src/rp2_common/hardware_timer/include/hardware/timer.h +++ b/src/rp2_common/hardware_timer/include/hardware/timer.h @@ -9,6 +9,7 @@ #include "pico.h" #include "hardware/structs/timer.h" +#include "hardware/regs/intctrl.h" #ifdef __cplusplus extern "C" { @@ -22,13 +23,20 @@ extern "C" { * This API provides medium level access to the timer HW. * See also \ref pico_time which provides higher levels functionality using the hardware timer. * - * The timer peripheral on RP2040 supports the following features: - * - single 64-bit counter, incrementing once per microsecond + * The timer peripheral on RP-series microcontrollers supports the following features: + * - RP2040 single 64-bit counter, incrementing once per microsecond + * - RP2350 two 64-bit counters, ticks generated from the tick block * - Latching two-stage read of counter, for race-free read over 32 bit bus * - Four alarms: match on the lower 32 bits of counter, IRQ on match. * - * By default the timer uses a one microsecond reference that is generated in the Watchdog (see Section 4.8.2) which is derived + * \if rp2040_specific + * On RP2040, by default the timer uses a one microsecond reference that is generated in the Watchdog (see RP2040 Datasheet Section 4.8.2) which is derived * from the clk_ref. + * \endif + * + * \if rp2350_specific + * On RP2350, by default the timer uses a one microsecond reference that is generated by the tick block (see RP2350 Datasheet Section 8.5) + * \endif * * The timer has 4 alarms, and can output a separate interrupt for each alarm. The alarms match on the lower 32 bits of the 64 * bit counter which means they can be fired a maximum of 2^32 microseconds into the future. This is equivalent to: @@ -45,77 +53,286 @@ extern "C" { * \see pico_time */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIMER, Enable/disable assertions in the timer module, type=bool, default=0, group=hardware_timer -#ifndef PARAM_ASSERTIONS_ENABLED_TIMER -#define PARAM_ASSERTIONS_ENABLED_TIMER 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER, Enable/disable assertions in the hardware_timer module, type=bool, default=0, group=hardware_timer +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER +#ifdef PARAM_ASSERTIONS_ENABLED_TIMER // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER PARAM_ASSERTIONS_ENABLED_TIMER +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_TIMER 0 +#endif +#endif + +/** + * \def TIMER_NUM(timer) + * \ingroup hardware_timer + * \hideinitializer + * \brief Returns the timer number for a timer instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef TIMER_NUM +#if NUM_GENERIC_TIMERS == 1 +#define TIMER_NUM(timer) ({ (void) (timer); 0; }) +#elif NUM_GENERIC_TIMERS == 2 +#define TIMER_NUM(timer) ((timer) == timer1_hw) +#endif +#endif + +/** + * \def TIMER_INSTANCE(timer_num) + * \ingroup hardware_timer + * \hideinitializer + * \brief Returns the timer instance with the given timer number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef TIMER_INSTANCE +#if NUM_GENERIC_TIMERS == 1 +#define TIMER_INSTANCE(num) timer_hw +#elif NUM_GENERIC_TIMERS == 2 +#define TIMER_INSTANCE(num) ((num) ? timer1_hw : timer0_hw) +#endif +#endif + +/** + * \def TIMER_ALARM_IRQ_NUM(timer,alarm_num) + * \ingroup hardware_timer + * \hideinitializer + * \brief Returns the \ref irq_num_t for the alarm interrupt from the given alarm on the given timer instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef TIMER_ALARM_IRQ_NUM +#if NUM_GENERIC_TIMERS == 1 +static_assert(TIMER_IRQ_3 == TIMER_IRQ_0 + 3, ""); +#define TIMER_ALARM_IRQ_NUM(timer, alarm_num) (TIMER_IRQ_0 + (alarm_num)) +#else +static_assert(TIMER1_IRQ_3 == TIMER0_IRQ_0 + 7, ""); +#define TIMER_ALARM_IRQ_NUM(timer, alarm_num) (TIMER0_IRQ_0 + TIMER_NUM(timer) * NUM_ALARMS + (alarm_num)) +#endif +#endif + +/** + * \def TIMER_ALARM_NUM_FROM_IRQ(irq_num) + * \ingroup hardware_timer + * \hideinitializer + * \brief Returns the alarm number from an \irq_num_t. See \ref TIMER_INSTANCE_NUM_FROM_IRQ to get the timer instance number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef TIMER_ALARM_NUM_FROM_IRQ +#if NUM_GENERIC_TIMERS == 1 +static_assert(TIMER_IRQ_3 == TIMER_IRQ_0 + 3, ""); +#define TIMER_ALARM_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER_IRQ_0) & 3u) +#else +static_assert(TIMER1_IRQ_3 == TIMER0_IRQ_0 + 7, ""); +#define TIMER_ALARM_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER0_IRQ_0) & 3u) +#endif +#endif + +/** + * \def TIMER_NUM_FROM_IRQ(irq_num) + * \ingroup hardware_timer + * \hideinitializer + * \brief Returns the alarm number from an \irq_num_t. See \ref TIMER_INSTANCE_NUM_FROM_IRQ to get the alarm number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef TIMER_NUM_FROM_IRQ +#if NUM_GENERIC_TIMERS == 1 +static_assert(TIMER_IRQ_3 == TIMER_IRQ_0 + 3, ""); +#define TIMER_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER_IRQ_0) >> 2) +#else +static_assert(TIMER1_IRQ_3 == TIMER0_IRQ_0 + 7, ""); +#define TIMER_NUM_FROM_IRQ(irq_num) (((irq_num) - TIMER0_IRQ_0) >> 2) +#endif +#endif + +// PICO_CONFIG: PICO_DEFAULT_TIMER, Timer instance number to use for RP2040-period hardware_timer APIs that assumed a single timer instance, min=0, max=1, default=0, group=hardware_timer + +/** + * \ingroup hardware_timer + * \brief The default timer instance number of the timer instance used for APIs that don't take an explicit timer instance + * \if rp2040_specific + * On RP2040 this must be 0 as there is only one timer instance + * \endif + * \if rp2350_specific + * On RP2040 this may be set to 0 or 1 + * \endif + */ +#ifndef PICO_DEFAULT_TIMER +#define PICO_DEFAULT_TIMER 0 +#endif + +/** + * \def PICO_DEFAULT_TIMER_INSTANCE() + * \ingroup hardware_timer + * \hideinitializer + * \brief Returns the default timer instance on the platform based on the setting of PICO_DEFAULT_TIMER + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef PICO_DEFAULT_TIMER_INSTANCE +#if NUM_GENERIC_TIMERS == 1 +#if PICO_DEFAULT_TIMER +#error Setting PICO_DEFAULT_TIMER to non zero is meaningless as there is only one TIMER instance on this platform +#endif +#define PICO_DEFAULT_TIMER_INSTANCE() timer_hw +#else +#define PICO_DEFAULT_TIMER_INSTANCE() (__CONCAT(__CONCAT(timer,PICO_DEFAULT_TIMER), _hw)) +// also define timer_hw for backwards compatibility (just accesses the default instance) +#define timer_hw PICO_DEFAULT_TIMER_INSTANCE() +#endif #endif static inline void check_hardware_alarm_num_param(__unused uint alarm_num) { - invalid_params_if(TIMER, alarm_num >= NUM_TIMERS); + invalid_params_if(HARDWARE_TIMER, alarm_num >= NUM_ALARMS); +} + +/*! \brief Return a 32 bit timestamp value in microseconds for a given timer instance +* \ingroup hardware_timer +* +* Returns the low 32 bits of the hardware timer. +* \note This value wraps roughly every 1 hour 11 minutes and 35 seconds. +* +* \param timer the timer instance +* \return the 32 bit timestamp +* \sa time_us_32 +*/ +static inline uint32_t timer_time_us_32(timer_hw_t *timer) { + return timer->timerawl; } -/*! \brief Return a 32 bit timestamp value in microseconds +/*! \brief Return a 32 bit timestamp value in microseconds for the default timer instance * \ingroup hardware_timer * * Returns the low 32 bits of the hardware timer. * \note This value wraps roughly every 1 hour 11 minutes and 35 seconds. * * \return the 32 bit timestamp +* \sa timer_time_us_32 */ static inline uint32_t time_us_32(void) { - return timer_hw->timerawl; + return timer_time_us_32(PICO_DEFAULT_TIMER_INSTANCE()); } -/*! \brief Return the current 64 bit timestamp value in microseconds +/*! \brief Return the current 64 bit timestamp value in microseconds for a given timer instance * \ingroup hardware_timer * * Returns the full 64 bits of the hardware timer. The \ref pico_time and other functions rely on the fact that this * value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps * (we apologize for introducing a potential year 5851444 bug). * +* \param timer the timer instance * \return the 64 bit timestamp +* \sa time_us_64 */ +uint64_t timer_time_us_64(timer_hw_t *timer); + +/*! \brief Return the current 64 bit timestamp value in microseconds for the default timer instance +* \ingroup hardware_timer +* +* Returns the full 64 bits of the hardware timer. The \ref pico_time and other functions rely on the fact that this +* value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps +* (we apologize for introducing a potential year 5851444 bug). +* +* \return the 64 bit timestamp +* \sa timer_time_us_64 +* */ uint64_t time_us_64(void); -/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds +/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds using the given timer instance + * \ingroup hardware_timer + * + * \param timer the timer instance + * \param delay_us delay amount in microseconds + * \sa busy_wait_us_32 + */ +void timer_busy_wait_us_32(timer_hw_t *timer, uint32_t delay_us); + +/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds using the default timer instance * \ingroup hardware_timer * * \param delay_us delay amount in microseconds + * \sa timer_busy_wait_us_32 */ void busy_wait_us_32(uint32_t delay_us); -/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds +/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds using the given timer instance + * \ingroup hardware_timer + * + * \param timer the timer instance + * \param delay_us delay amount in microseconds + * \sa busy_wait_us + */ +void timer_busy_wait_us(timer_hw_t *timer, uint64_t delay_us); + +/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds using the default timer instance * \ingroup hardware_timer * * \param delay_us delay amount in microseconds + * \sa timer_busy_wait_us */ void busy_wait_us(uint64_t delay_us); -/*! \brief Busy wait wasting cycles for the given number of milliseconds +/*! \brief Busy wait wasting cycles for the given number of milliseconds using the given timer instance * \ingroup hardware_timer * + * \param timer the timer instance * \param delay_ms delay amount in milliseconds + * \sa busy_wait_ms + */ +void timer_busy_wait_ms(timer_hw_t *timer, uint32_t delay_ms); + +/*! \brief Busy wait wasting cycles for the given number of milliseconds using the default timer instance + * \ingroup hardware_timer + * + * \param delay_ms delay amount in milliseconds + * \sa timer_busy_wait_ms */ void busy_wait_ms(uint32_t delay_ms); -/*! \brief Busy wait wasting cycles until after the specified timestamp +/*! \brief Busy wait wasting cycles until after the specified timestamp using the given timer instance + * \ingroup hardware_timer + * + * \param timer the timer instance + * \param t Absolute time to wait until + * \sa busy_wait_until + */ +void timer_busy_wait_until(timer_hw_t *timer, absolute_time_t t); + +/*! \brief Busy wait wasting cycles until after the specified timestamp using the default timer instance * \ingroup hardware_timer * * \param t Absolute time to wait until + * \sa timer_busy_wait_until */ void busy_wait_until(absolute_time_t t); -/*! \brief Check if the specified timestamp has been reached +/*! \brief Check if the specified timestamp has been reached on the given timer instance * \ingroup hardware_timer * + * \param timer the timer instance * \param t Absolute time to compare against current time * \return true if it is now after the specified timestamp + * \sa time_reached */ -static inline bool time_reached(absolute_time_t t) { +static inline bool timer_time_reached(timer_hw_t *timer, absolute_time_t t) { uint64_t target = to_us_since_boot(t); uint32_t hi_target = (uint32_t)(target >> 32u); - uint32_t hi = timer_hw->timerawh; - return (hi >= hi_target && (timer_hw->timerawl >= (uint32_t) target || hi != hi_target)); + uint32_t hi = timer->timerawh; + return (hi >= hi_target && (timer->timerawl >= (uint32_t) target || hi != hi_target)); +} + +/*! \brief Check if the specified timestamp has been reached on the default timer instance + * \ingroup hardware_timer + * + * \param t Absolute time to compare against current time + * \return true if it is now after the specified timestamp + * \sa timer_time_reached + */ +static inline bool time_reached(absolute_time_t t) { + return timer_time_reached(PICO_DEFAULT_TIMER_INSTANCE(), t); } /*! Callback function type for hardware alarms @@ -126,44 +343,115 @@ static inline bool time_reached(absolute_time_t t) { */ typedef void (*hardware_alarm_callback_t)(uint alarm_num); -/*! \brief cooperatively claim the use of this hardware alarm_num +/*! \brief cooperatively claim the use of this hardware alarm_num on the given timer instance + * \ingroup hardware_timer + * + * This method hard asserts if the hardware alarm is currently claimed. + * + * \param timer the timer instance + * \param alarm_num the hardware alarm to claim + * \sa hardware_alarm_claim + * \sa hardware_claiming + */ +void timer_hardware_alarm_claim(timer_hw_t *timer, uint alarm_num); + +/*! \brief cooperatively claim the use of this hardware alarm_num on the default timer instance * \ingroup hardware_timer * * This method hard asserts if the hardware alarm is currently claimed. * * \param alarm_num the hardware alarm to claim + * \sa timer_hardware_alarm_claim * \sa hardware_claiming */ void hardware_alarm_claim(uint alarm_num); -/*! \brief cooperatively claim the use of this hardware alarm_num +/*! \brief cooperatively claim the use of a hardware alarm_num on the given timer instance + * \ingroup hardware_timer + * + * This method attempts to claim an unused hardware alarm + * + * \param timer the timer instance + * \param required if true the function will panic if none are available + * \return alarm_num the hardware alarm claimed or -1 if required was false, and none are available + * \sa hardware_alarm_claim_unused + * \sa hardware_claiming + */ +int timer_hardware_alarm_claim_unused(timer_hw_t *timer, bool required); + +/*! \brief cooperatively claim the use of a hardware alarm_num on the default timer instance * \ingroup hardware_timer * * This method attempts to claim an unused hardware alarm * - * \return alarm_num the hardware alarm claimed or -1 if requires was false, and none are available + * \param required if true the function will panic if none are available + * \return alarm_num the hardware alarm claimed or -1 if required was false, and none are available + * \sa timer_hardware_alarm_claim_unused * \sa hardware_claiming */ int hardware_alarm_claim_unused(bool required); -/*! \brief cooperatively release the claim on use of this hardware alarm_num +/*! \brief cooperatively release the claim on use of this hardware alarm_num on the given timer instance + * \ingroup hardware_timer + * + * \param timer the timer instance + * \param alarm_num the hardware alarm to unclaim + * \sa hardware_alarm_unclaim + * \sa hardware_claiming + */ +void timer_hardware_alarm_unclaim(timer_hw_t *timer, uint alarm_num); + +/*! \brief cooperatively release the claim on use of this hardware alarm_num on the default timer instance * \ingroup hardware_timer * * \param alarm_num the hardware alarm to unclaim + * \sa timer_hardware_alarm_unclaim * \sa hardware_claiming */ void hardware_alarm_unclaim(uint alarm_num); -/*! \brief Determine if a hardware alarm has been claimed +/*! \brief Determine if a hardware alarm has been claimed on the given timer instance + * \ingroup hardware_timer + * + * \param timer the timer instance + * \param alarm_num the hardware alarm number + * \return true if claimed, false otherwise + * \sa hardware_alarm_is_claimed + * \sa hardware_alarm_claim + */ +bool timer_hardware_alarm_is_claimed(timer_hw_t *timer, uint alarm_num); + +/*! \brief Determine if a hardware alarm has been claimed on the default timer instance * \ingroup hardware_timer * * \param alarm_num the hardware alarm number * \return true if claimed, false otherwise - * \see hardware_alarm_claim + * \sa timer_hardware_alarm_is_claimed + * \sa hardware_alarm_claim */ bool hardware_alarm_is_claimed(uint alarm_num); -/*! \brief Enable/Disable a callback for a hardware timer on this core +/*! \brief Enable/Disable a callback for a hardware alarm for a given timer instance on this core + * \ingroup hardware_timer + * + * This method enables/disables the alarm IRQ for the specified hardware alarm on the + * calling core, and set the specified callback to be associated with that alarm. + * + * This callback will be used for the timeout set via hardware_alarm_set_target + * + * \note This will install the handler on the current core if the IRQ handler isn't already set. + * Therefore the user has the opportunity to call this up from the core of their choice + * + * \param timer the timer instance + * \param alarm_num the hardware alarm number + * \param callback the callback to install, or NULL to unset + * + * \sa hardware_alarm_set_callback + * \sa timer_hardware_alarm_set_target() + */ +void timer_hardware_alarm_set_callback(timer_hw_t *timer, uint alarm_num, hardware_alarm_callback_t callback); + +/*! \brief Enable/Disable a callback for a hardware alarm on the default timer instance on this core * \ingroup hardware_timer * * This method enables/disables the alarm IRQ for the specified hardware alarm on the @@ -177,32 +465,75 @@ bool hardware_alarm_is_claimed(uint alarm_num); * \param alarm_num the hardware alarm number * \param callback the callback to install, or NULL to unset * + * \sa timer_hardware_alarm_set_callback * \sa hardware_alarm_set_target() */ void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback); /** - * \brief Set the current target for the specified hardware alarm + * \brief Set the current target for a specific hardware alarm on the given timer instance * \ingroup hardware_timer * * This will replace any existing target * - * @param alarm_num the hardware alarm number - * @param t the target timestamp - * @return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set + * \param timer the timer instance + * \param alarm_num the hardware alarm number + * \param t the target timestamp + * \return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set + * \sa hardware_alarm_set_target + */ +bool timer_hardware_alarm_set_target(timer_hw_t *timer, uint alarm_num, absolute_time_t t); + +/** + * \brief Set the current target for the specified hardware alarm on the default timer instance + * \ingroup hardware_timer + * + * This will replace any existing target + * + * \param alarm_num the hardware alarm number + * \param t the target timestamp + * \return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set + * \sa timer_hardware_alarm_set_target */ bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t); /** - * \brief Cancel an existing target (if any) for a given hardware_alarm + * \brief Cancel an existing target (if any) for a specific hardware_alarm on the given timer instance + * \ingroup hardware_timer + * + * \param timer the timer instance + * \param alarm_num the hardware alarm number + * \sa hardware_alarm_cancel + */ +void timer_hardware_alarm_cancel(timer_hw_t *timer, uint alarm_num); + +/** + * \brief Cancel an existing target (if any) for the specified hardware_alarm on the default timer instance * \ingroup hardware_timer * - * @param alarm_num the hardware alarm number + * \param alarm_num the hardware alarm number + * \sa timer_hardware_alarm_cancel */ void hardware_alarm_cancel(uint alarm_num); /** - * \brief Force and IRQ for a specific hardware alarm + * \brief Force and IRQ for a specific hardware alarm on the given timer instance + * \ingroup hardware_timer + * + * This method will forcibly make sure the current alarm callback (if present) for the hardware + * alarm is called from an IRQ context after this call. If an actual callback is due at the same + * time then the callback may only be called once. + * + * Calling this method does not otherwise interfere with regular callback operations. + * + * \param timer the timer instance + * \param alarm_num the hardware alarm number + * \sa hardware_alarm_force_irq + */ +void timer_hardware_alarm_force_irq(timer_hw_t *timer, uint alarm_num); + +/** + * \brief Force and IRQ for a specific hardware alarm on the default timer instance * \ingroup hardware_timer * * This method will forcibly make sure the current alarm callback (if present) for the hardware @@ -211,9 +542,57 @@ void hardware_alarm_cancel(uint alarm_num); * * Calling this method does not otherwise interfere with regular callback operations. * - * @param alarm_num the hardware alarm number + * \param alarm_num the hardware alarm number + * \sa timer_hardware_alarm_force_irq */ void hardware_alarm_force_irq(uint alarm_num); + +/** + * \ingroup hardware_timer + * \brief Returns the \ref irq_num_t for the alarm interrupt from the given alarm on the given timer instance + * \param timer the timer instance + * \param alarm_num the alarm number + * \sa TIMER_ALARM_IRQ_NUM + */ +static inline uint timer_hardware_alarm_get_irq_num(__unused timer_hw_t *timer, uint alarm_num) { + check_hardware_alarm_num_param(alarm_num); + return TIMER_ALARM_IRQ_NUM(timer, alarm_num); +} + +/** + * \ingroup hardware_timer + * \brief Returns the \ref irq_num_t for the alarm interrupt from the given alarm on the default timer instance + * \param timer the timer instance + * \param alarm_num the alarm number + */ +static inline uint hardware_alarm_get_irq_num(timer_hw_t *timer, uint alarm_num) { + return timer_hardware_alarm_get_irq_num(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); +} + +/** + * \ingroup hardware_timer + * \brief Returns the timer number for a timer instance + * + * \param timer the timer instance + * \return the timer number + * \sa TIMER_NUM + */ +static inline uint timer_get_index(timer_hw_t *timer) { + return TIMER_NUM(timer); +} + +/** + * \ingroup hardware_timer + * \brief Returns the timer instance with the given timer number + * + * \param timer_num the timer number + * \return the timer instance + */ +static inline timer_hw_t *timer_get_instance(uint timer_num) { + invalid_params_if(HARDWARE_TIMER, timer_num >= NUM_GENERIC_TIMERS); + return TIMER_INSTANCE(timer_num); +} + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/hardware_timer/timer.c b/src/rp2_common/hardware_timer/timer.c index 836b47caf..e536ef5cd 100644 --- a/src/rp2_common/hardware_timer/timer.c +++ b/src/rp2_common/hardware_timer/timer.c @@ -11,45 +11,61 @@ check_hw_layout(timer_hw_t, ints, TIMER_INTS_OFFSET); -static hardware_alarm_callback_t alarm_callbacks[NUM_TIMERS]; -static uint32_t target_hi[NUM_TIMERS]; -static uint8_t timer_callbacks_pending; +static hardware_alarm_callback_t alarm_callbacks[NUM_GENERIC_TIMERS][NUM_ALARMS]; +static uint32_t target_hi[NUM_GENERIC_TIMERS][NUM_ALARMS]; +static uint8_t timer_callbacks_pending[NUM_GENERIC_TIMERS]; -static_assert(NUM_TIMERS <= 4, ""); -static uint8_t claimed; +static_assert(NUM_ALARMS * NUM_GENERIC_TIMERS <= 8, ""); +static uint8_t claimed[NUM_GENERIC_TIMERS]; + +void timer_hardware_alarm_claim(timer_hw_t *timer, uint alarm_num) { + check_hardware_alarm_num_param(alarm_num); + hw_claim_or_assert(&claimed[timer_get_index(timer)], alarm_num, "Hardware alarm %d already claimed"); +} void hardware_alarm_claim(uint alarm_num) { + timer_hardware_alarm_claim(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); +} + +void timer_hardware_alarm_unclaim(timer_hw_t *timer, uint alarm_num) { check_hardware_alarm_num_param(alarm_num); - hw_claim_or_assert(&claimed, alarm_num, "Hardware alarm %d already claimed"); + hw_claim_clear(&claimed[timer_get_index(timer)], alarm_num); } void hardware_alarm_unclaim(uint alarm_num) { + timer_hardware_alarm_unclaim(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); +} + +bool timer_hardware_alarm_is_claimed(timer_hw_t *timer, uint alarm_num) { check_hardware_alarm_num_param(alarm_num); - hw_claim_clear(&claimed, alarm_num); + return hw_is_claimed(&claimed[timer_get_index(timer)], alarm_num); } bool hardware_alarm_is_claimed(uint alarm_num) { - check_hardware_alarm_num_param(alarm_num); - return hw_is_claimed(&claimed, alarm_num); + return timer_hardware_alarm_is_claimed(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); +} + +int timer_hardware_alarm_claim_unused(timer_hw_t *timer, bool required) { + return hw_claim_unused_from_range(&claimed[timer_get_index(timer)], required, 0, NUM_ALARMS - 1, "No alarms available"); } int hardware_alarm_claim_unused(bool required) { - return hw_claim_unused_from_range(&claimed, required, 0, NUM_TIMERS - 1, "No timers available"); + return timer_hardware_alarm_claim_unused(PICO_DEFAULT_TIMER_INSTANCE(), required); } /// tag::time_us_64[] -uint64_t time_us_64() { +uint64_t timer_time_us_64(timer_hw_t *timer) { // Need to make sure that the upper 32 bits of the timer // don't change, so read that first - uint32_t hi = timer_hw->timerawh; + uint32_t hi = timer->timerawh; uint32_t lo; do { // Read the lower 32 bits - lo = timer_hw->timerawl; + lo = timer->timerawl; // Now read the upper 32 bits again and // check that it hasn't incremented. If it has loop around // and read the lower 32 bits again to get an accurate value - uint32_t next_hi = timer_hw->timerawh; + uint32_t next_hi = timer->timerawh; if (hi == next_hi) break; hi = next_hi; } while (true); @@ -58,12 +74,12 @@ uint64_t time_us_64() { /// end::time_us_64[] /// \tag::busy_wait[] -void busy_wait_us_32(uint32_t delay_us) { +void timer_busy_wait_us_32(timer_hw_t *timer, uint32_t delay_us) { if (0 <= (int32_t)delay_us) { // we only allow 31 bits, otherwise we could have a race in the loop below with // values very close to 2^32 - uint32_t start = timer_hw->timerawl; - while (timer_hw->timerawl - start < delay_us) { + uint32_t start = timer->timerawl; + while (timer->timerawl - start < delay_us) { tight_loop_contents(); } } else { @@ -71,70 +87,89 @@ void busy_wait_us_32(uint32_t delay_us) { } } -void busy_wait_us(uint64_t delay_us) { - uint64_t base = time_us_64(); +void timer_busy_wait_us(timer_hw_t *timer, uint64_t delay_us) { + uint64_t base = timer_time_us_64(timer); uint64_t target = base + delay_us; if (target < base) { target = (uint64_t)-1; } absolute_time_t t; update_us_since_boot(&t, target); - busy_wait_until(t); + timer_busy_wait_until(timer, t); } -void busy_wait_ms(uint32_t delay_ms) +void timer_busy_wait_ms(timer_hw_t *timer, uint32_t delay_ms) { if (delay_ms <= 0x7fffffffu / 1000) { - busy_wait_us_32(delay_ms * 1000); + timer_busy_wait_us_32(timer, delay_ms * 1000); } else { - busy_wait_us(delay_ms * 1000ull); + timer_busy_wait_us(timer, delay_ms * 1000ull); } } -void busy_wait_until(absolute_time_t t) { +void timer_busy_wait_until(timer_hw_t *timer, absolute_time_t t) { uint64_t target = to_us_since_boot(t); uint32_t hi_target = (uint32_t)(target >> 32u); - uint32_t hi = timer_hw->timerawh; + uint32_t hi = timer->timerawh; while (hi < hi_target) { - hi = timer_hw->timerawh; + hi = timer->timerawh; tight_loop_contents(); } - while (hi == hi_target && timer_hw->timerawl < (uint32_t) target) { - hi = timer_hw->timerawh; + while (hi == hi_target && timer->timerawl < (uint32_t) target) { + hi = timer->timerawh; tight_loop_contents(); } } /// \end::busy_wait[] -static inline uint hardware_alarm_irq_number(uint alarm_num) { - return TIMER_IRQ_0 + alarm_num; +uint64_t time_us_64(void) { + return timer_time_us_64(PICO_DEFAULT_TIMER_INSTANCE()); +} + +void busy_wait_us_32(uint32_t delay_us) { + timer_busy_wait_us_32(PICO_DEFAULT_TIMER_INSTANCE(), delay_us); +} + +void busy_wait_us(uint64_t delay_us) { + timer_busy_wait_us(PICO_DEFAULT_TIMER_INSTANCE(), delay_us); +} + +void busy_wait_ms(uint32_t delay_ms) +{ + timer_busy_wait_ms(PICO_DEFAULT_TIMER_INSTANCE(), delay_ms); +} + +void busy_wait_until(absolute_time_t t) { + timer_busy_wait_until(PICO_DEFAULT_TIMER_INSTANCE(), t); } static void hardware_alarm_irq_handler(void) { // Determine which timer this IRQ is for - uint alarm_num = __get_current_exception() - VTABLE_FIRST_IRQ - TIMER_IRQ_0; + uint alarm_num = TIMER_ALARM_NUM_FROM_IRQ(__get_current_exception() - VTABLE_FIRST_IRQ); check_hardware_alarm_num_param(alarm_num); - + uint timer_num = TIMER_NUM_FROM_IRQ(alarm_num); + timer_hw_t *timer = timer_get_instance(timer_num); hardware_alarm_callback_t callback = NULL; spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); uint32_t save = spin_lock_blocking(lock); + // Clear the timer IRQ (inside lock, because we check whether we have handled the IRQ yet in alarm_set by looking at the interrupt status - timer_hw->intr = 1u << alarm_num; + timer->intr = 1u << alarm_num; // Clear any forced IRQ - hw_clear_bits(&timer_hw->intf, 1u << alarm_num); + hw_clear_bits(&timer->intf, 1u << alarm_num); // make sure the IRQ is still valid - if (timer_callbacks_pending & (1u << alarm_num)) { + if (timer_callbacks_pending[timer_num] & (1u << alarm_num)) { // Now check whether we have a timer event to handle that isn't already obsolete (this could happen if we // were already in the IRQ handler before someone else changed the timer setup - if (timer_hw->timerawh >= target_hi[alarm_num]) { + if (timer->timerawh >= target_hi[timer_num][alarm_num]) { // we have reached the right high word as well as low word value - callback = alarm_callbacks[alarm_num]; - timer_callbacks_pending &= (uint8_t)~(1u << alarm_num); + callback = alarm_callbacks[timer_num][alarm_num]; + timer_callbacks_pending[timer_num] &= (uint8_t)~(1u << alarm_num); } else { // try again in 2^32 us - timer_hw->alarm[alarm_num] = timer_hw->alarm[alarm_num]; // re-arm the timer + timer->alarm[alarm_num] = timer->alarm[alarm_num]; // re-arm the timer } } @@ -145,12 +180,13 @@ static void hardware_alarm_irq_handler(void) { } } -void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback) { +void timer_hardware_alarm_set_callback(timer_hw_t *timer, uint alarm_num, hardware_alarm_callback_t callback) { // todo check current core owner // note this should probably be subsumed by irq_set_exclusive_handler anyway, since that // should disallow IRQ handlers on both cores check_hardware_alarm_num_param(alarm_num); - uint irq_num = hardware_alarm_irq_number(alarm_num); + uint timer_num = timer_get_index(timer); + uint irq_num = TIMER_ALARM_IRQ_NUM(timer, alarm_num); spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); uint32_t save = spin_lock_blocking(lock); if (callback) { @@ -160,58 +196,63 @@ void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callb irq_set_exclusive_handler(irq_num, hardware_alarm_irq_handler); irq_set_enabled(irq_num, true); // Enable interrupt in block and at processor - hw_set_bits(&timer_hw->inte, 1u << alarm_num); + hw_set_bits(&timer->inte, 1u << alarm_num); } - alarm_callbacks[alarm_num] = callback; + alarm_callbacks[timer_num][alarm_num] = callback; } else { - alarm_callbacks[alarm_num] = NULL; - timer_callbacks_pending &= (uint8_t)~(1u << alarm_num); + alarm_callbacks[timer_num][alarm_num] = NULL; + timer_callbacks_pending[timer_num] &= (uint8_t)~(1u << alarm_num); irq_remove_handler(irq_num, hardware_alarm_irq_handler); irq_set_enabled(irq_num, false); } spin_unlock(lock, save); } -bool hardware_alarm_set_target(uint alarm_num, absolute_time_t target) { +void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback) { + timer_hardware_alarm_set_callback(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num, callback); +} + +bool timer_hardware_alarm_set_target(timer_hw_t *timer, uint alarm_num, absolute_time_t target) { bool missed; - uint64_t now = time_us_64(); + uint64_t now = timer_time_us_64(timer); uint64_t t = to_us_since_boot(target); if (now >= t) { missed = true; } else { missed = false; + uint timer_num = timer_get_index(timer); // 1) actually set the hardware timer spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); uint32_t save = spin_lock_blocking(lock); - uint8_t old_timer_callbacks_pending = timer_callbacks_pending; - timer_callbacks_pending |= (uint8_t)(1u << alarm_num); - timer_hw->intr = 1u << alarm_num; // clear any IRQ - timer_hw->alarm[alarm_num] = (uint32_t) t; + uint8_t old_timer_callbacks_pending = timer_callbacks_pending[timer_num]; + timer_callbacks_pending[timer_num] |= (uint8_t)(1u << alarm_num); + timer->intr = 1u << alarm_num; // clear any IRQ + timer->alarm[alarm_num] = (uint32_t) t; // Set the alarm. Writing time should arm it - target_hi[alarm_num] = (uint32_t)(t >> 32u); + target_hi[timer_num][alarm_num] = (uint32_t)(t >> 32u); // 2) check for races - if (!(timer_hw->armed & 1u << alarm_num)) { + if (!(timer->armed & 1u << alarm_num)) { // not armed, so has already fired .. IRQ must be pending (we are still under lock) - assert(timer_hw->ints & 1u << alarm_num); + assert(timer->ints & 1u << alarm_num); } else { - if (time_us_64() >= t) { + if (timer_time_us_64(timer) >= t) { // we are already at or past the right time; there is no point in us racing against the IRQ // we are about to generate. note however that, if there was already a timer pending before, // then we still let the IRQ fire, as whatever it was, is not handled by our setting missed=true here missed = true; - if (timer_callbacks_pending != old_timer_callbacks_pending) { + if (timer_callbacks_pending[timer_num] != old_timer_callbacks_pending) { // disarm the timer - timer_hw->armed = 1u << alarm_num; + timer->armed = 1u << alarm_num; // clear the IRQ... - timer_hw->intr = 1u << alarm_num; + timer->intr = 1u << alarm_num; // ... including anything pending on the processor - perhaps unnecessary, but // our timer flag says we aren't expecting anything. - irq_clear(hardware_alarm_irq_number(alarm_num)); + irq_clear(timer_hardware_alarm_get_irq_num(timer, alarm_num)); // and clear our flag so that if the IRQ handler is already active (because it is on // the other core) it will also skip doing anything - timer_callbacks_pending = old_timer_callbacks_pending; + timer_callbacks_pending[timer_num] = old_timer_callbacks_pending; } } } @@ -221,21 +262,33 @@ bool hardware_alarm_set_target(uint alarm_num, absolute_time_t target) { return missed; } -void hardware_alarm_cancel(uint alarm_num) { +bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t) { + return timer_hardware_alarm_set_target(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num, t); +} + +void timer_hardware_alarm_cancel(timer_hw_t *timer, uint alarm_num) { check_hardware_alarm_num_param(alarm_num); spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); uint32_t save = spin_lock_blocking(lock); - timer_hw->armed = 1u << alarm_num; - timer_callbacks_pending &= (uint8_t)~(1u << alarm_num); + timer->armed = 1u << alarm_num; + timer_callbacks_pending[timer_get_index(timer)] &= (uint8_t)~(1u << alarm_num); spin_unlock(lock, save); } -void hardware_alarm_force_irq(uint alarm_num) { +void hardware_alarm_cancel(uint alarm_num) { + timer_hardware_alarm_cancel(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); +} + +void timer_hardware_alarm_force_irq(timer_hw_t *timer, uint alarm_num) { check_hardware_alarm_num_param(alarm_num); spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER); uint32_t save = spin_lock_blocking(lock); - timer_callbacks_pending |= (uint8_t)(1u << alarm_num); + timer_callbacks_pending[timer_get_index(timer)] |= (uint8_t)(1u << alarm_num); spin_unlock(lock, save); - hw_set_bits(&timer_hw->intf, 1u << alarm_num); + hw_set_bits(&timer->intf, 1u << alarm_num); +} + +void hardware_alarm_force_irq(uint alarm_num) { + timer_hardware_alarm_force_irq(PICO_DEFAULT_TIMER_INSTANCE(), alarm_num); } diff --git a/src/rp2_common/hardware_uart/BUILD.bazel b/src/rp2_common/hardware_uart/BUILD.bazel index 42cf90094..f8694bff3 100644 --- a/src/rp2_common/hardware_uart/BUILD.bazel +++ b/src/rp2_common/hardware_uart/BUILD.bazel @@ -9,13 +9,13 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", + "//src/rp2_common:platform_defs", "//src/rp2_common/hardware_base", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_resets", "//src/rp2_common/hardware_timer", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", - "//src/rp2_common/pico_platform:platform_defs", ], ) diff --git a/src/rp2_common/hardware_uart/include/hardware/uart.h b/src/rp2_common/hardware_uart/include/hardware/uart.h index a574150c8..4febe1799 100644 --- a/src/rp2_common/hardware_uart/include/hardware/uart.h +++ b/src/rp2_common/hardware_uart/include/hardware/uart.h @@ -9,11 +9,14 @@ #include "pico.h" #include "hardware/structs/uart.h" -#include "hardware/regs/dreq.h" -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_UART, Enable/disable assertions in the UART module, type=bool, default=0, group=hardware_uart -#ifndef PARAM_ASSERTIONS_ENABLED_UART -#define PARAM_ASSERTIONS_ENABLED_UART 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_UART, Enable/disable assertions in the hardware_uart module, type=bool, default=0, group=hardware_uart +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_UART +#ifdef PARAM_ASSERTIONS_ENABLED_UART // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART PARAM_ASSERTIONS_ENABLED_UART +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_UART 0 +#endif #endif #ifdef __cplusplus @@ -30,9 +33,9 @@ extern "C" { #define PICO_UART_DEFAULT_CRLF 0 #endif -// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, min=0, max=1, group=hardware_uart -// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, group=hardware_uart -// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, group=hardware_uart +// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, min=0, max=1, default=Usually provided via board header, group=hardware_uart +// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, default=Usually provided via board header, group=hardware_uart +// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, default=Usually provided via board header, group=hardware_uart // PICO_CONFIG: PICO_DEFAULT_UART_BAUD_RATE, Define the default UART baudrate, max=921600, default=115200, group=hardware_uart #ifndef PICO_DEFAULT_UART_BAUD_RATE @@ -44,7 +47,7 @@ extern "C" { * * \brief Hardware UART API * - * RP2040 has 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number + * RP-series microcontrollers have 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number * of GPIO pins as defined in the GPIO muxing. * * Only the TX, RX, RTS, and CTS signals are @@ -56,10 +59,11 @@ extern "C" { * \code * int main() { * - * // Set the GPIO pin mux to the UART - 0 is TX, 1 is RX + * // Set the GPIO pin mux to the UART - pin 0 is TX, 1 is RX; note use of UART_FUNCSEL_NUM for the general + * // case where the func sel used for UART depends on the pin number * // Do this before calling uart_init to avoid losing data - * gpio_set_function(0, GPIO_FUNC_UART); - * gpio_set_function(1, GPIO_FUNC_UART); + * gpio_set_function(0, UART_FUNCSEL_NUM(uart0, 0)); + * gpio_set_function(1, UART_FUNCSEL_NUM(uart0, 1)); * * // Initialise UART 0 * uart_init(uart0, 115200); @@ -84,12 +88,125 @@ typedef struct uart_inst uart_inst_t; /** @} */ +/** + * \def PICO_DEFAULT_UART_INSTANCE() + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns the default UART instance based on the value of PICO_DEFAULT_UART + */ #if !defined(PICO_DEFAULT_UART_INSTANCE) && defined(PICO_DEFAULT_UART) -#define PICO_DEFAULT_UART_INSTANCE (__CONCAT(uart,PICO_DEFAULT_UART)) +#define PICO_DEFAULT_UART_INSTANCE() (__CONCAT(uart,PICO_DEFAULT_UART)) #endif +/** + * \def PICO_DEFAULT_UART + * \ingroup hardware_uart + * \hideinitializer + * \brief The default UART instance number + */ + #ifdef PICO_DEFAULT_UART_INSTANCE -#define uart_default PICO_DEFAULT_UART_INSTANCE +#define uart_default PICO_DEFAULT_UART_INSTANCE() +#endif + +/** + * \def UART_NUM(uart) + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns the UART number for a UART instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef UART_NUM +static_assert(NUM_UARTS == 2, ""); +#define UART_NUM(uart) ((uart) == uart1) +#endif + +/** + * \def UART_INSTANCE(uart_num) + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns the UART instance with the given UART number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef UART_INSTANCE +static_assert(NUM_UARTS == 2, ""); +#define UART_INSTANCE(num) ((num) ? uart1 : uart0) +#endif + +/** + * \def UART_DREQ_NUM(uart, is_tx) + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns the \ref dreq_num_t used for pacing DMA transfers to or from this UART instance. + * If is_tx is true, then it is for transfers to the UART else for transfers from the UART. + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef UART_DREQ_NUM +#include "hardware/regs/dreq.h" +static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, ""); +static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, ""); +static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, ""); +#define UART_DREQ_NUM(uart, is_tx) ({ \ + DREQ_UART0_TX + UART_NUM(uart) * 2 + !(is_tx); \ +}) +#endif + +/** + * \def UART_CLOCK_NUM(uart) + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns \ref clock_num_t of the clock for the given UART instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef UART_CLOCK_NUM +#define UART_CLOCK_NUM(uart) clk_peri +#endif + +/** + * \def UART_FUNCSEL_NUM(uart, gpio) + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns \ref gpio_function_t needed to select the UART function for the given UART instance on the given GPIO number. + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef UART_FUNCSEL_NUM +#if PICO_RP2040 +#define UART_FUNCSEL_NUM(uart, gpio) GPIO_FUNC_UART +#else +#define UART_FUNCSEL_NUM(uart, gpio) ((gpio) & 0x2 ? GPIO_FUNC_UART_AUX : GPIO_FUNC_UART) +#endif +#endif + +/** + * \def UART_IRQ_NUM(uart) + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns the \ref irq_num_t for processor interrupts from the given UART instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef UART_IRQ_NUM +#include "hardware/regs/intctrl.h" +static_assert(UART1_IRQ == UART0_IRQ + 1, ""); +#define UART_IRQ_NUM(uart) (UART0_IRQ + UART_NUM(uart)) +#endif + +/** + * \def UART_RESET_NUM(uart) + * \ingroup hardware_uart + * \hideinitializer + * \brief Returns the \ref reset_num_t used to reset a given UART instance + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef UART_RESET_NUM +#include "hardware/resets.h" +#define UART_RESET_NUM(uart) (uart_get_index(uart) ? RESET_UART1 : RESET_UART0) #endif /*! \brief Convert UART instance to hardware instance number @@ -99,16 +216,30 @@ typedef struct uart_inst uart_inst_t; * \return Number of UART, 0 or 1. */ static inline uint uart_get_index(uart_inst_t *uart) { - invalid_params_if(UART, uart != uart0 && uart != uart1); - return uart == uart1 ? 1 : 0; + invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); + return UART_NUM(uart); } -static inline uart_inst_t *uart_get_instance(uint instance) { - static_assert(NUM_UARTS == 2, ""); - invalid_params_if(UART, instance >= NUM_UARTS); - return instance ? uart1 : uart0; +/*! \brief Get the UART instance from an instance number + * \ingroup hardware_uart + * + * \param uart UART instance + * \return Number of UART, 0 or 1 + */ +static inline uart_inst_t *uart_get_instance(uint num) { + invalid_params_if(HARDWARE_UART, num >= NUM_UARTS); + return UART_INSTANCE(num); } +/*! \brief Get the real hardware UART instance from a UART instance + * \ingroup hardware_uart + * + * This extra level of abstraction was added to facilitate adding PIO UARTs in the future. + * It currently does nothing, and costs nothing. + * + * \param uart UART instance + * \return The uart_hw_t pointer to the UART instance registers + */ static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) { uart_get_index(uart); // check it is a hw uart return (uart_hw_t *)uart; @@ -216,17 +347,17 @@ static inline void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts) { */ void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity); -/*! \brief Setup UART interrupts +/*! \brief Enable/Disable UART interrupt outputs * \ingroup hardware_uart * - * Enable the UART's interrupt output. An interrupt handler will need to be installed prior to calling + * Enable/Disable the UART's interrupt outputs. An interrupt handler should be installed prior to calling * this function. * * \param uart UART instance. \ref uart0 or \ref uart1 * \param rx_has_data If true an interrupt will be fired when the RX FIFO contains data. * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data. */ -static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { +static inline void uart_set_irqs_enabled(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { // Both UARTRXINTR (RX) and UARTRTINTR (RX timeout) interrupts are // required for rx_has_data. RX asserts when >=4 characters are in the RX // FIFO (for RXIFLSEL=0). RT asserts when there are >=1 characters and no @@ -246,6 +377,11 @@ static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, boo } } +// backwards compatibility with SDK version < 2.0.0 +static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) { + uart_set_irqs_enabled(uart, rx_has_data, tx_needs_data); +} + /*! \brief Test if specific UART is enabled * \ingroup hardware_uart * @@ -253,7 +389,7 @@ static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, boo * \return true if the UART is enabled */ static inline bool uart_is_enabled(uart_inst_t *uart) { - return !!(uart_get_hw(uart)->cr & UART_UARTCR_UARTEN_BITS); + return uart_get_hw(uart)->cr & UART_UARTCR_UARTEN_BITS; } /*! \brief Enable/Disable the FIFOs on specified UART @@ -452,17 +588,29 @@ static inline void uart_default_tx_wait_blocking(void) { */ bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us); -/*! \brief Return the DREQ to use for pacing transfers to/from a particular UART instance +/*! \brief Return the \ref dreq_num_t to use for pacing transfers to/from a particular UART instance + * \ingroup hardware_uart + * + * \param uart UART instance. \ref uart0 or \ref uart1 + * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance + */ +static inline uint uart_get_dreq_num(uart_inst_t *uart, bool is_tx) { + return UART_DREQ_NUM(uart, is_tx); +} + +/*! \brief Return the \ref reset_num_t to use for pacing transfers to/from a particular UART instance * \ingroup hardware_uart * * \param uart UART instance. \ref uart0 or \ref uart1 * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance */ +static inline uint uart_get_reset_num(uart_inst_t *uart) { + return UART_RESET_NUM(uart); +} + +// backwards compatibility static inline uint uart_get_dreq(uart_inst_t *uart, bool is_tx) { - static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, ""); - static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, ""); - static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, ""); - return DREQ_UART0_TX + uart_get_index(uart) * 2 + !is_tx; + return uart_get_dreq_num(uart, is_tx); } #ifdef __cplusplus diff --git a/src/rp2_common/hardware_uart/uart.c b/src/rp2_common/hardware_uart/uart.c index e40331196..be2df57c5 100644 --- a/src/rp2_common/hardware_uart/uart.c +++ b/src/rp2_common/hardware_uart/uart.c @@ -11,6 +11,11 @@ #include "hardware/structs/uart.h" #include "hardware/resets.h" #include "hardware/clocks.h" + +static inline uint32_t uart_clock_get_hz(__unused uart_inst_t *inst) { + return clock_get_hz(UART_CLOCK_NUM(inst)); +} + #include "hardware/timer.h" #include "pico/assert.h" @@ -25,21 +30,19 @@ short uart_char_to_line_feed[NUM_UARTS]; /// \tag::uart_reset[] static inline void uart_reset(uart_inst_t *uart) { - invalid_params_if(UART, uart != uart0 && uart != uart1); - reset_block(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS); + reset_block_num(uart_get_reset_num(uart)); } static inline void uart_unreset(uart_inst_t *uart) { - invalid_params_if(UART, uart != uart0 && uart != uart1); - unreset_block_wait(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS); + unreset_block_num_wait_blocking(uart_get_reset_num(uart)); } /// \end::uart_reset[] /// \tag::uart_init[] uint uart_init(uart_inst_t *uart, uint baudrate) { - invalid_params_if(UART, uart != uart0 && uart != uart1); + invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); - if (clock_get_hz(clk_peri) == 0) { + if (uart_clock_get_hz(uart) == 0) { return 0; } @@ -80,15 +83,17 @@ uint uart_init(uart_inst_t *uart, uint baudrate) { // Enable the UART, both TX and RX uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS; +#if !PICO_UART_NO_DMACR_ENABLE // Always enable DREQ signals -- no harm in this if DMA is not listening uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS; +#endif return baud; } /// \end::uart_init[] void uart_deinit(uart_inst_t *uart) { - invalid_params_if(UART, uart != uart0 && uart != uart1); + invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); uart_reset(uart); } @@ -127,7 +132,7 @@ static uint32_t uart_disable_before_lcr_write(uart_inst_t *uart) { uint32_t brdiv_ratio = 64u * current_ibrd + current_fbrd; brdiv_ratio <<= 10; // 3662 is ~(15 * 244.14) where 244.14 is 16e6 / 2^16 - uint32_t scaled_freq = clock_get_hz(clk_peri) / 3662ul; + uint32_t scaled_freq = uart_clock_get_hz(uart) / 3662ul; uint32_t wait_time_us = brdiv_ratio / scaled_freq; busy_wait_us(wait_time_us); } @@ -136,7 +141,7 @@ static uint32_t uart_disable_before_lcr_write(uart_inst_t *uart) { } static void uart_write_lcr_bits_masked(uart_inst_t *uart, uint32_t values, uint32_t write_mask) { - invalid_params_if(UART, uart != uart0 && uart != uart1); + invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1); // (Potentially) Cleanly handle disabling the UART before touching LCR uint32_t cr_save = uart_disable_before_lcr_write(uart); @@ -148,8 +153,8 @@ static void uart_write_lcr_bits_masked(uart_inst_t *uart, uint32_t values, uint3 /// \tag::uart_set_baudrate[] uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) { - invalid_params_if(UART, baudrate == 0); - uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate); + invalid_params_if(HARDWARE_UART, baudrate == 0); + uint32_t baud_rate_div = (8 * uart_clock_get_hz(uart) / baudrate) + 1; uint32_t baud_ibrd = baud_rate_div >> 7; uint32_t baud_fbrd; @@ -160,7 +165,7 @@ uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) { baud_ibrd = 65535; baud_fbrd = 0; } else { - baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2; + baud_fbrd = (baud_rate_div & 0x7f) >> 1; } uart_get_hw(uart)->ibrd = baud_ibrd; @@ -171,14 +176,14 @@ uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) { uart_write_lcr_bits_masked(uart, 0, 0); // See datasheet - return (4 * clock_get_hz(clk_peri)) / (64 * baud_ibrd + baud_fbrd); + return (4 * uart_clock_get_hz(uart)) / (64 * baud_ibrd + baud_fbrd); } /// \end::uart_set_baudrate[] void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity) { - invalid_params_if(UART, data_bits < 5 || data_bits > 8); - invalid_params_if(UART, stop_bits != 1 && stop_bits != 2); - invalid_params_if(UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD); + invalid_params_if(HARDWARE_UART, data_bits < 5 || data_bits > 8); + invalid_params_if(HARDWARE_UART, stop_bits != 1 && stop_bits != 2); + invalid_params_if(HARDWARE_UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD); uart_write_lcr_bits_masked(uart, ((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) | diff --git a/src/rp2_common/hardware_vreg/BUILD.bazel b/src/rp2_common/hardware_vreg/BUILD.bazel index 626aa6ca3..a1d381eef 100644 --- a/src/rp2_common/hardware_vreg/BUILD.bazel +++ b/src/rp2_common/hardware_vreg/BUILD.bazel @@ -9,7 +9,8 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_base", ], ) diff --git a/src/rp2_common/hardware_vreg/include/hardware/vreg.h b/src/rp2_common/hardware_vreg/include/hardware/vreg.h index cf4512305..ce6ad0ca6 100644 --- a/src/rp2_common/hardware_vreg/include/hardware/vreg.h +++ b/src/rp2_common/hardware_vreg/include/hardware/vreg.h @@ -8,7 +8,12 @@ #define _HARDWARE_VREG_H #include "pico.h" + +#if PICO_RP2040 #include "hardware/structs/vreg_and_chip_reset.h" +#else +#include "hardware/structs/powman.h" +#endif #ifdef __cplusplus extern "C" { @@ -24,17 +29,45 @@ extern "C" { /** Possible voltage values that can be applied to the regulator */ enum vreg_voltage { - VREG_VOLTAGE_0_85 = 0b0110, ///< 0.85v - VREG_VOLTAGE_0_90 = 0b0111, ///< 0.90v - VREG_VOLTAGE_0_95 = 0b1000, ///< 0.95v - VREG_VOLTAGE_1_00 = 0b1001, ///< 1.00v - VREG_VOLTAGE_1_05 = 0b1010, ///< 1.05v - VREG_VOLTAGE_1_10 = 0b1011, ///< 1.10v - VREG_VOLTAGE_1_15 = 0b1100, ///< 1.15v - VREG_VOLTAGE_1_20 = 0b1101, ///< 1.20v - VREG_VOLTAGE_1_25 = 0b1110, ///< 1.25v - VREG_VOLTAGE_1_30 = 0b1111, ///< 1.30v +#if !PICO_RP2040 + VREG_VOLTAGE_0_55 = 0b00000, + VREG_VOLTAGE_0_60 = 0b00001, + VREG_VOLTAGE_0_65 = 0b00010, + VREG_VOLTAGE_0_70 = 0b00011, + VREG_VOLTAGE_0_75 = 0b00100, + VREG_VOLTAGE_0_80 = 0b00101, +#endif + VREG_VOLTAGE_0_85 = 0b00110, ///< 0.85 V + VREG_VOLTAGE_0_90 = 0b00111, ///< 0.90 V + VREG_VOLTAGE_0_95 = 0b01000, ///< 0.95 V + VREG_VOLTAGE_1_00 = 0b01001, ///< 1.00 V + VREG_VOLTAGE_1_05 = 0b01010, ///< 1.05 V + VREG_VOLTAGE_1_10 = 0b01011, ///< 1.10 V + VREG_VOLTAGE_1_15 = 0b01100, ///< 1.15 V + VREG_VOLTAGE_1_20 = 0b01101, ///< 1.20 V + VREG_VOLTAGE_1_25 = 0b01110, ///< 1.25 V + VREG_VOLTAGE_1_30 = 0b01111, ///< 1.30 V +#if !PICO_RP2040 + // Above this point you will need to set POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT + VREG_VOLTAGE_1_35 = 0b10000, + VREG_VOLTAGE_1_40 = 0b10001, + VREG_VOLTAGE_1_50 = 0b10010, + VREG_VOLTAGE_1_60 = 0b10011, + VREG_VOLTAGE_1_65 = 0b10100, + VREG_VOLTAGE_1_70 = 0b10101, + VREG_VOLTAGE_1_80 = 0b10110, + VREG_VOLTAGE_1_90 = 0b10111, + VREG_VOLTAGE_2_00 = 0b11000, + VREG_VOLTAGE_2_35 = 0b11001, + VREG_VOLTAGE_2_50 = 0b11010, + VREG_VOLTAGE_2_65 = 0b11011, + VREG_VOLTAGE_2_80 = 0b11100, + VREG_VOLTAGE_3_00 = 0b11101, + VREG_VOLTAGE_3_15 = 0b11110, + VREG_VOLTAGE_3_30 = 0b11111, +#endif + // Note the "max" here assumes that VREG_CTRL_DISABLE_VOLTAGE_LIMIT is not set VREG_VOLTAGE_MIN = VREG_VOLTAGE_0_85, ///< Always the minimum possible voltage VREG_VOLTAGE_DEFAULT = VREG_VOLTAGE_1_10, ///< Default voltage on power up. VREG_VOLTAGE_MAX = VREG_VOLTAGE_1_30, ///< Always the maximum possible voltage @@ -48,8 +81,19 @@ enum vreg_voltage { **/ void vreg_set_voltage(enum vreg_voltage voltage); + +/*! \brief Enable use of voltages beyond the safe range of operation + * \ingroup hardware_vreg + * + * This allows voltages beyond VREG_VOLTAGE_MAX to be used, on platforms where + * they are available (e.g. RP2350). Attempting to set a higher voltage + * without first calling this function will result in a voltage of + * VREG_VOLTAGE_MAX. + **/ +void vreg_disable_voltage_limit(void); + #ifdef __cplusplus } #endif -#endif \ No newline at end of file +#endif diff --git a/src/rp2_common/hardware_vreg/vreg.c b/src/rp2_common/hardware_vreg/vreg.c index 501b0d4e0..61fd08042 100644 --- a/src/rp2_common/hardware_vreg/vreg.c +++ b/src/rp2_common/hardware_vreg/vreg.c @@ -8,5 +8,43 @@ #include "hardware/vreg.h" void vreg_set_voltage(enum vreg_voltage voltage) { - hw_write_masked(&vreg_and_chip_reset_hw->vreg, ((uint)voltage) << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, VREG_AND_CHIP_RESET_VREG_VSEL_BITS); +#if PICO_RP2040 + + hw_write_masked( + &vreg_and_chip_reset_hw->vreg, + ((uint)voltage) << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, + VREG_AND_CHIP_RESET_VREG_VSEL_BITS + ); + +#elif PICO_RP2350 + + hw_set_bits(&powman_hw->vreg_ctrl, POWMAN_PASSWORD_BITS | POWMAN_VREG_CTRL_UNLOCK_BITS); + + // Wait for any prior change to finish before making a new change + while (powman_hw->vreg & POWMAN_VREG_UPDATE_IN_PROGRESS_BITS) + tight_loop_contents(); + + hw_write_masked( + &powman_hw->vreg, + POWMAN_PASSWORD_BITS | ((uint)voltage << POWMAN_VREG_VSEL_LSB), + POWMAN_PASSWORD_BITS | POWMAN_VREG_VSEL_BITS + ); + while (powman_hw->vreg & POWMAN_VREG_UPDATE_IN_PROGRESS_BITS) + tight_loop_contents(); + +#else + panic_unsupported(); +#endif +} + +void vreg_disable_voltage_limit(void) { +#if PICO_RP2040 + // The voltage limit can't be disabled on RP2040 (was implemented by + // hardwiring the LDO controls) + return; +#elif PICO_RP2350 + hw_set_bits(&powman_hw->vreg_ctrl, POWMAN_PASSWORD_BITS | POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_BITS); +#else + panic_unsupported(); +#endif } diff --git a/src/rp2_common/hardware_watchdog/BUILD.bazel b/src/rp2_common/hardware_watchdog/BUILD.bazel index a23f3a49c..019079573 100644 --- a/src/rp2_common/hardware_watchdog/BUILD.bazel +++ b/src/rp2_common/hardware_watchdog/BUILD.bazel @@ -9,8 +9,11 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/common/pico_base:pico_platform", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform_internal", + "//src/rp2_common/hardware_base", + "//src/rp2_common/hardware_ticks:hardware_ticks_headers", + "//src/rp2_common/pico_bootrom", ], ) diff --git a/src/rp2_common/hardware_watchdog/CMakeLists.txt b/src/rp2_common/hardware_watchdog/CMakeLists.txt index 43a401b11..2577c75ba 100644 --- a/src/rp2_common/hardware_watchdog/CMakeLists.txt +++ b/src/rp2_common/hardware_watchdog/CMakeLists.txt @@ -1 +1,3 @@ -pico_simple_hardware_target(watchdog) \ No newline at end of file +pico_simple_hardware_target(watchdog) + +pico_mirrored_target_link_libraries(hardware_watchdog INTERFACE hardware_ticks) \ No newline at end of file diff --git a/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h index 86e6963ed..e6adf65af 100644 --- a/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h +++ b/src/rp2_common/hardware_watchdog/include/hardware/watchdog.h @@ -17,7 +17,7 @@ * * Supporting functions for the Pico hardware watchdog timer. * - * The RP2040 has a built in HW watchdog Timer. This is a countdown timer that can restart parts of the chip if it reaches zero. + * The RP-series microcontrollers have a built in HW watchdog Timer. This is a countdown timer that can restart parts of the chip if it reaches zero. * For example, this can be used to restart the processor if the software running on it gets stuck in an infinite loop * or similar. The programmer has to periodically write a value to the watchdog to stop it reaching zero. * @@ -30,9 +30,13 @@ extern "C" { #endif -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_WATCHDOG, Enable/disable assertions in the watchdog module, type=bool, default=0, group=hardware_watchdog -#ifndef PARAM_ASSERTIONS_ENABLED_WATCHDOG -#define PARAM_ASSERTIONS_ENABLED_WATCHDOG 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG, Enable/disable assertions in the hardware_watchdog module, type=bool, default=0, group=hardware_watchdog +#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG +#ifdef PARAM_ASSERTIONS_ENABLED_WATCHDOG // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG PARAM_ASSERTIONS_ENABLED_WATCHDOG +#else +#define PARAM_ASSERTIONS_ENABLED_HARDWARE_WATCHDOG 0 +#endif #endif /*! \brief Define actions to perform at watchdog timeout @@ -82,6 +86,12 @@ void watchdog_update(void); */ void watchdog_enable(uint32_t delay_ms, bool pause_on_debug); +/** + * \brief Disable the watchdog + * \ingroup hardware_watchdog + */ +void watchdog_disable(void); + /** * \brief Did the watchdog cause the last reboot? * \ingroup hardware_watchdog @@ -99,7 +109,7 @@ bool watchdog_caused_reboot(void); * \ref watchdog_enable caused the last reboot. * * This method checks for a special value in watchdog scratch register 4 placed there by \ref watchdog_enable. - * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP2040 bootrom + * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP-series microcontroller bootrom * (e.g. dragging a UF2 onto the RPI-RP2 drive). * * @return true If the watchdog timer or a watchdog force caused (see \ref watchdog_caused_reboot) the last reboot @@ -114,10 +124,18 @@ bool watchdog_enable_caused_reboot(void); * \brief Returns the number of microseconds before the watchdog will reboot the chip. * \ingroup hardware_watchdog * + * \if rp2040_specicifc + * On RP2040 this method returns the last value set instead of the remaining time due to a h/w bug. + * \endif + * * @return The number of microseconds before the watchdog will reboot the chip. */ -uint32_t watchdog_get_count(void); +uint32_t watchdog_get_time_remaining_ms(void); +// backwards compatibility with SDK < 2.0.0 +static inline uint32_t watchdog_get_count(void) { + return watchdog_get_time_remaining_ms(); +} #ifdef __cplusplus } #endif diff --git a/src/rp2_common/hardware_watchdog/watchdog.c b/src/rp2_common/hardware_watchdog/watchdog.c index 723484c76..45528ce43 100644 --- a/src/rp2_common/hardware_watchdog/watchdog.c +++ b/src/rp2_common/hardware_watchdog/watchdog.c @@ -9,12 +9,12 @@ #include "hardware/watchdog.h" #include "hardware/structs/watchdog.h" #include "hardware/structs/psm.h" +#include "hardware/ticks.h" +#include "pico/bootrom.h" /// \tag::watchdog_start_tick[] void watchdog_start_tick(uint cycles) { - valid_params_if(WATCHDOG, cycles <= 0x1ffu); - // Important: This function also provides a tick reference to the timer - watchdog_hw->tick = cycles | WATCHDOG_TICK_ENABLE_BITS; + tick_start(TICK_WATCHDOG, cycles); } /// \end::watchdog_start_tick[] @@ -28,14 +28,20 @@ void watchdog_update(void) { } // end::watchdog_update[] -uint32_t watchdog_get_count(void) { - return (watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS) / 2 ; +uint32_t watchdog_get_time_remaining_ms(void) { + return watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS; } +#if PICO_RP2040 +// Note, we have x2 here as the watchdog HW currently decrements twice per tick +#define WATCHDOG_XFACTOR 2 +#else +#define WATCHDOG_XFACTOR 1 +#endif // tag::watchdog_enable[] // Helper function used by both watchdog_enable and watchdog_reboot void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { - valid_params_if(WATCHDOG, delay_ms <= 8388); // i.e. floor(0xffffff / 2000) + valid_params_if(HARDWARE_WATCHDOG, delay_ms <= WATCHDOG_LOAD_BITS / (1000 * WATCHDOG_XFACTOR)); hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); // Reset everything apart from ROSC and XOSC @@ -54,11 +60,12 @@ void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { if (!delay_ms) { hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS); } else { - // Note, we have x2 here as the watchdog HW currently decrements twice per tick - load_value = delay_ms * 1000 * 2; - - if (load_value > 0xffffffu) - load_value = 0xffffffu; + load_value = delay_ms * 1000; +#if PICO_RP2040 + load_value *= 2; +#endif + if (load_value > WATCHDOG_LOAD_BITS) + load_value = WATCHDOG_LOAD_BITS; watchdog_update(); @@ -76,6 +83,10 @@ void watchdog_enable(uint32_t delay_ms, bool pause_on_debug) { _watchdog_enable(delay_ms, pause_on_debug); } +void watchdog_disable(void) { + hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); +} + void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) { check_hw_layout(watchdog_hw_t, scratch[7], WATCHDOG_SCRATCH7_OFFSET); @@ -83,7 +94,9 @@ void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) { hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); if (pc) { +#ifndef __riscv pc |= 1u; // thumb mode +#endif watchdog_hw->scratch[4] = 0xb007c0d3; watchdog_hw->scratch[5] = pc ^ -0xb007c0d3; watchdog_hw->scratch[6] = sp; @@ -100,7 +113,11 @@ void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) { bool watchdog_caused_reboot(void) { // If any reason bits are set this is true +#if PICO_RP2040 return watchdog_hw->reason; +#else + return watchdog_hw->reason && rom_get_last_boot_type() == BOOT_TYPE_NORMAL; +#endif } bool watchdog_enable_caused_reboot(void) { diff --git a/src/rp2_common/hardware_xosc/BUILD.bazel b/src/rp2_common/hardware_xosc/BUILD.bazel index 8897d4bbd..d4996c61c 100644 --- a/src/rp2_common/hardware_xosc/BUILD.bazel +++ b/src/rp2_common/hardware_xosc/BUILD.bazel @@ -9,11 +9,11 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/common/pico_base:pico_platform", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform_internal", + "//src/rp2_common:platform_defs", "//src/rp2_common/hardware_clocks:hardware_clocks_headers", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", - "//src/rp2_common/pico_platform:platform_defs", ], ) diff --git a/src/rp2_common/hardware_xosc/xosc.c b/src/rp2_common/hardware_xosc/xosc.c index e22602213..d32442ef5 100644 --- a/src/rp2_common/hardware_xosc/xosc.c +++ b/src/rp2_common/hardware_xosc/xosc.c @@ -13,13 +13,13 @@ #include "hardware/regs/xosc.h" #include "hardware/xosc.h" -#if XOSC_KHZ < (1 * KHZ) || XOSC_KHZ > (50 * KHZ) +#if XOSC_HZ < (1 * MHZ) || XOSC_HZ > (50 * MHZ) // Note: Although an external clock can be supplied up to 50 MHz, the maximum frequency the -// XOSC cell is specified to work with a crystal is less, please see the RP2040 Datasheet. -#error XOSC_KHZ must be in the range 1,000-50,000KHz i.e. 1-50MHz XOSC frequency +// XOSC cell is specified to work with a crystal is less, please see the appropriate RP-series datasheet. +#error XOSC_HZ must be in the range 1,000,000-50,000,000 i.e. 1-50MHz XOSC frequency #endif -#define STARTUP_DELAY (((XOSC_KHZ + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER) +#define STARTUP_DELAY ((((XOSC_HZ / KHZ) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER) // The DELAY field in xosc_hw->startup is 14 bits wide. #if STARTUP_DELAY >= (1 << 13) diff --git a/src/rp2_common/pico_aon_timer/BUILD.bazel b/src/rp2_common/pico_aon_timer/BUILD.bazel new file mode 100644 index 000000000..6ceaf2e52 --- /dev/null +++ b/src/rp2_common/pico_aon_timer/BUILD.bazel @@ -0,0 +1,21 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_aon_timer", + srcs = ["aon_timer.c"], + hdrs = ["include/pico/aon_timer.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_util", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_irq", + "//src/rp2_common/hardware_sync", + ] + select({ + "//bazel/constraint:rp2040": ["//src/rp2_common/hardware_rtc"], + "//conditions:default": ["//src/rp2_common/hardware_powman"], + }), +) diff --git a/src/rp2_common/pico_aon_timer/CMakeLists.txt b/src/rp2_common/pico_aon_timer/CMakeLists.txt new file mode 100644 index 000000000..0d2a2d657 --- /dev/null +++ b/src/rp2_common/pico_aon_timer/CMakeLists.txt @@ -0,0 +1,19 @@ +pico_add_library(pico_aon_timer) + +target_sources(pico_aon_timer INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/aon_timer.c +) + +target_include_directories(pico_aon_timer_headers SYSTEM INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/include +) + +pico_mirrored_target_link_libraries(pico_aon_timer INTERFACE pico_util) + +if (TARGET hardware_rtc) + pico_mirrored_target_link_libraries(pico_aon_timer INTERFACE hardware_rtc) +endif() + +if (TARGET hardware_powman) + pico_mirrored_target_link_libraries(pico_aon_timer INTERFACE hardware_powman) +endif() diff --git a/src/rp2_common/pico_aon_timer/aon_timer.c b/src/rp2_common/pico_aon_timer/aon_timer.c new file mode 100644 index 000000000..35173cf89 --- /dev/null +++ b/src/rp2_common/pico_aon_timer/aon_timer.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/aon_timer.h" +#include "hardware/irq.h" +#include "hardware/sync.h" + +static aon_timer_alarm_handler_t aon_timer_alarm_handler; + +#if HAS_RP2040_RTC +#include "hardware/rtc.h" +#include "pico/util/datetime.h" +#elif HAS_POWMAN_TIMER +#include "hardware/powman.h" + +static void powman_timer_irq_handler(void) { + uint irq_num = aon_timer_get_irq_num(); + // we are one-shot, so remove ourselves + irq_set_enabled(irq_num, false); + irq_remove_handler(irq_num, powman_timer_irq_handler); + if (aon_timer_alarm_handler) aon_timer_alarm_handler(); +} +#endif + +void aon_timer_set_time(const struct timespec *ts) { +#if HAS_RP2040_RTC + datetime_t dt; + bool ok = time_to_datetime(ts->tv_sec, &dt); + assert(ok); + if (ok) rtc_set_datetime(&dt); +#elif HAS_POWMAN_TIMER + powman_timer_set_ms(timespec_to_ms(ts)); +#else + panic_unsupported(); +#endif +} + +void aon_timer_get_time(struct timespec *ts) { +#if HAS_RP2040_RTC + datetime_t dt; + rtc_get_datetime(&dt); + time_t t; + bool ok = datetime_to_time(&dt, &t); + assert(ok); + ts->tv_nsec = 0; + if (ok) { + ts->tv_sec = t; + } else { + ts->tv_sec = -1; + } +#elif HAS_POWMAN_TIMER + ms_to_timespec(powman_timer_get_ms(), ts); +#else + panic_unsupported(); +#endif +} + +aon_timer_alarm_handler_t aon_timer_enable_alarm(const struct timespec *ts, aon_timer_alarm_handler_t handler, bool wakeup_from_low_power) { + uint32_t save = save_and_disable_interrupts(); + aon_timer_alarm_handler_t old_handler = aon_timer_alarm_handler; + struct timespec ts_adjusted = *ts; +#if HAS_RP2040_RTC + ((void)wakeup_from_low_power); // don't have a choice + datetime_t dt; + // adjust to after the target time + if (ts_adjusted.tv_nsec) ts_adjusted.tv_sec++; + bool ok = time_to_datetime(ts_adjusted.tv_sec, &dt); + assert(ok); + if (ok) { + rtc_set_alarm(&dt, handler); + } +#elif HAS_POWMAN_TIMER + uint irq_num = aon_timer_get_irq_num(); + powman_timer_disable_alarm(); + // adjust to after the target time + ts_adjusted.tv_nsec += 999999; + if (ts_adjusted.tv_nsec > 1000000000) { + ts_adjusted.tv_nsec -= 1000000000; + ts_adjusted.tv_sec++; + } + if (ts_adjusted.tv_nsec) ts_adjusted.tv_sec++; + if (wakeup_from_low_power) { + powman_enable_alarm_wakeup_at_ms(timespec_to_ms(ts)); + } else { + powman_disable_alarm_wakeup(); + powman_timer_enable_alarm_at_ms(timespec_to_ms(ts)); + } + if (handler) { + irq_set_exclusive_handler(irq_num, powman_timer_irq_handler); + irq_set_enabled(irq_num, true); + } +#else + panic_unsupported(); +#endif + aon_timer_alarm_handler = handler; + restore_interrupts_from_disabled(save); + return old_handler; +} + +void aon_timer_disable_alarm(void) { + irq_set_enabled(aon_timer_get_irq_num(), false); +#if HAS_RP2040_RTC + rtc_disable_alarm(); +#elif HAS_POWMAN_TIMER + powman_timer_disable_alarm(); +#else + panic_unsupported(); +#endif +} + +void aon_timer_start_with_timeofday(void) { + struct timeval tv; + gettimeofday(&tv, NULL); + struct timespec ts; + ts.tv_sec = tv.tv_sec; + ts.tv_nsec = tv.tv_usec * 1000; + aon_timer_start(&ts); +} + +void aon_timer_start(const struct timespec *ts) { +#if HAS_RP2040_RTC + rtc_init(); + aon_timer_set_time(ts); +#elif HAS_POWMAN_TIMER + // todo how best to allow different configurations; this should just be the default + powman_timer_set_1khz_tick_source_xosc(); + powman_timer_set_ms(timespec_to_ms(ts)); + powman_timer_start(); +#else + panic_unsupported(); +#endif +} + +void aon_timer_stop(void) { +#if HAS_RP2040_RTC + hw_clear_bits(&rtc_hw->ctrl, RTC_CTRL_RTC_ENABLE_BITS); +#elif HAS_POWMAN_TIMER + powman_timer_stop(); +#else + panic_unsupported(); +#endif +} + +void aon_timer_get_resolution(struct timespec *ts) { +#if HAS_RP2040_RTC + ts->tv_sec = 1; + ts->tv_nsec = 0; +#elif HAS_POWMAN_TIMER + ts->tv_sec = 0; + ts->tv_nsec = 1000000000 / 1000; +#else + panic_unsupported(); +#endif +} + +bool aon_timer_is_running(void) { +#if HAS_RP2040_RTC + return rtc_running(); +#elif HAS_POWMAN_TIMER + return powman_timer_is_running(); +#else + panic_unsupported(); +#endif +} diff --git a/src/rp2_common/pico_aon_timer/include/pico/aon_timer.h b/src/rp2_common/pico_aon_timer/include/pico/aon_timer.h new file mode 100644 index 000000000..d3f69ade9 --- /dev/null +++ b/src/rp2_common/pico_aon_timer/include/pico/aon_timer.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_AON_TIMER_H +#define _PICO_AON_TIMER_H + +#include "pico.h" +#include +#include "pico/util/datetime.h" +#include "hardware/regs/intctrl.h" + +/** \file pico/aon_timer.h + * \defgroup pico_aon_timer pico_aon_timer + * + * \brief High Level "Always on Timer" Abstraction + * + * \if rp2040_specific + * This library uses the RTC on RP2040. + * \endif + * \if rp2350_specific + * This library uses the RTC on RP2350. + * \endif + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \def AON_TIMER_IRQ_NUM() + * \ingroup pico_aon_timer + * \hideinitializer + * \brief Returns the \ref irq_num_t for interrupts for the actual hardware backing the AON timer abstraction + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef AON_TIMER_IRQ_NUM +#if HAS_RP2040_RTC +#define AON_TIMER_IRQ_NUM() RTC_IRQ +#elif HAS_POWMAN_TIMER +#define AON_TIMER_IRQ_NUM() POWMAN_IRQ_TIMER +#endif +#endif + +typedef void (*aon_timer_alarm_handler_t)(void); + +/** + * \brief Start the AON timer running using the result from the gettimeofday() function as the current time + * \ingroup pico_aon_timer + */ +void aon_timer_start_with_timeofday(void); + +/** + * \brief Start the AON timer running using the specified timespec as the current time + * \ingroup pico_aon_timer + * \param ts the current time + */ +void aon_timer_start(const struct timespec *ts); + +/** + * \brief Stop the AON timer + * \ingroup pico_aon_timer + */ +void aon_timer_stop(void); + +/** + * \brief Update the current time of the AON timer + * \ingroup pico_aon_timer + * \param ts the new current time + */ +void aon_timer_set_time(const struct timespec *ts); + +/** + * \brief Get the current time of the AON timer + * \ingroup pico_aon_timer + * \param ts out value for the current time + */ +void aon_timer_get_time(struct timespec *ts); + +/** + * \brief Get the resolution of the AON timer + * \ingroup pico_aon_timer + * \param ts out value for the resolution of the AON timer + */ +void aon_timer_get_resolution(struct timespec *ts); + +/** + * \brief Enable an AON timer alarm for a specifed time + * \ingroup pico_aon_timer + * + * \if rp2040_specific + * On RP2040 The alarm will not fire if it is in the past + * \endif + * \if rp2350_specific + * On RP2040 The alarm will fire if it is in the past + * \endif + * + * \param ts the alarm time + * \param handler a callback to call when the timer fires (may be NULL for wakeup_from_low_power = true) + * \param wakeup_from_low_power true if the AON timer is to be used to wake up from a DORMANT state + */ +aon_timer_alarm_handler_t aon_timer_enable_alarm(const struct timespec *ts, aon_timer_alarm_handler_t handler, bool wakeup_from_low_power); + +/** + * \brief Disable the currently enabled AON timer alarm if any + * \ingroup pico_aon_timer + */ +void aon_timer_disable_alarm(void); + +/** + * \brief Disable the currently enabled AON timer alarm if any + * \ingroup pico_aon_timer + * \return true if the AON timer is running + */ +bool aon_timer_is_running(void); + +static inline uint aon_timer_get_irq_num(void) { + return AON_TIMER_IRQ_NUM(); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/rp2_common/pico_async_context/BUILD.bazel b/src/rp2_common/pico_async_context/BUILD.bazel index fc7ed33c5..8d57b52fc 100644 --- a/src/rp2_common/pico_async_context/BUILD.bazel +++ b/src/rp2_common/pico_async_context/BUILD.bazel @@ -12,8 +12,8 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:pico_platform", ], ) @@ -28,9 +28,9 @@ cc_library( deps = [ ":pico_async_context", "//bazel/config:PICO_FREERTOS_LIB", - "//src/common/pico_base", "//src/common/pico_sync", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_irq", ], ) @@ -43,9 +43,9 @@ cc_library( target_compatible_with = compatible_with_rp2(), deps = [ ":pico_async_context", - "//src/common/pico_base", "//src/common/pico_sync", "//src/common/pico_time", + "//src/rp2_common:pico_platform", ], ) @@ -57,9 +57,10 @@ cc_library( target_compatible_with = compatible_with_rp2(), deps = [ ":pico_async_context", - "//src/common/pico_base", "//src/common/pico_sync", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_irq", + "//src/rp2_common/pico_multicore", ], ) diff --git a/src/rp2_common/pico_async_context/CMakeLists.txt b/src/rp2_common/pico_async_context/CMakeLists.txt index 5d035809d..cb136aa2e 100644 --- a/src/rp2_common/pico_async_context/CMakeLists.txt +++ b/src/rp2_common/pico_async_context/CMakeLists.txt @@ -1,5 +1,5 @@ pico_add_library(pico_async_context_base NOFLAG) -target_include_directories(pico_async_context_base_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_async_context_base_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_sources(pico_async_context_base INTERFACE ${CMAKE_CURRENT_LIST_DIR}/async_context_base.c ) diff --git a/src/rp2_common/pico_async_context/async_context_freertos.c b/src/rp2_common/pico_async_context/async_context_freertos.c index dce83c7ad..a4304d476 100644 --- a/src/rp2_common/pico_async_context/async_context_freertos.c +++ b/src/rp2_common/pico_async_context/async_context_freertos.c @@ -12,7 +12,7 @@ #include "semphr.h" -#if configNUM_CORES > 1 && !defined(configUSE_CORE_AFFINITY) +#if configNUMBER_OF_CORES > 1 && !defined(configUSE_CORE_AFFINITY) #error async_context_freertos requires configUSE_CORE_AFFINITY under SMP #endif @@ -125,7 +125,7 @@ bool async_context_freertos_init(async_context_freertos_t *self, async_context_f async_context_deinit(&self->core); return false; } -#if configNUM_CORES > 1 +#if configNUMBER_OF_CORES > 1 UBaseType_t core_id = config->task_core_id; if (core_id == (UBaseType_t)-1) { core_id = portGET_CORE_ID(); diff --git a/src/rp2_common/pico_async_context/include/pico/async_context.h b/src/rp2_common/pico_async_context/include/pico/async_context.h index 32b1bad52..6f7c4f0dc 100644 --- a/src/rp2_common/pico_async_context/include/pico/async_context.h +++ b/src/rp2_common/pico_async_context/include/pico/async_context.h @@ -249,7 +249,7 @@ static inline void async_context_lock_check(async_context_t *context) { * * \param context the async_context * \param func the function to call - * \param param the paramter to pass to the function + * \param param the parameter to pass to the function * \return the return value from func */ static inline uint32_t async_context_execute_sync(async_context_t *context, uint32_t (*func)(void *param), void *param) { diff --git a/src/rp2_common/pico_async_context/include/pico/async_context_freertos.h b/src/rp2_common/pico_async_context/include/pico/async_context_freertos.h index f560de4f2..bc5131258 100644 --- a/src/rp2_common/pico_async_context/include/pico/async_context_freertos.h +++ b/src/rp2_common/pico_async_context/include/pico/async_context_freertos.h @@ -35,6 +35,15 @@ extern "C" { typedef struct async_context_freertos async_context_freertos_t; +#if !defined(configNUMBER_OF_CORES) && defined(configNUM_CORES) +#if !portSUPPORT_SMP +#error configNUMBER_OF_CORES is the new name for configNUM_CORES +#else +// portSUPPORT_SMP was defined in old smp branch +#error configNUMBER_OF_CORES is the new name for configNUM_CORES, however it looks like you may need to define both as you are using an old SMP branch of FreeRTOS +#endif +#endif + /** * \brief Configuration object for async_context_freertos instances. */ @@ -51,7 +60,7 @@ typedef struct async_context_freertos_config { * \brief the core ID (see \ref portGET_CORE_ID()) to pin the task to. * This is only relevant in SMP mode. */ -#if configUSE_CORE_AFFINITY && configNUM_CORES > 1 +#if configUSE_CORE_AFFINITY && configNUMBER_OF_CORES > 1 UBaseType_t task_core_id; #endif } async_context_freertos_config_t; @@ -90,7 +99,7 @@ bool async_context_freertos_init(async_context_freertos_t *self, async_context_f async_context_freertos_config_t config = { .task_priority = ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_PRIORITY, .task_stack_size = ASYNC_CONTEXT_DEFAULT_FREERTOS_TASK_STACK_SIZE, -#if configUSE_CORE_AFFINITY && configNUM_CORES > 1 +#if configUSE_CORE_AFFINITY && configNUMBER_OF_CORES > 1 .task_core_id = (UBaseType_t)-1, // none #endif }; diff --git a/src/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h b/src/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h index 394a9fdf2..1b6b1e0b9 100644 --- a/src/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h +++ b/src/rp2_common/pico_async_context/include/pico/async_context_threadsafe_background.h @@ -12,7 +12,7 @@ * \ingroup pico_async_context * * \brief async_context_threadsafe_background provides an implementation of \ref async_context that handles asynchronous - * work in a low priority IRQ, and there is no need for the user to poll for work. + * work in a low priority IRQ, and there is no need for the user to poll for work * * \note The workers used with this async_context MUST be safe to call from an IRQ. */ diff --git a/src/rp2_common/pico_atomic/BUILD.bazel b/src/rp2_common/pico_atomic/BUILD.bazel new file mode 100644 index 000000000..98dae547e --- /dev/null +++ b/src/rp2_common/pico_atomic/BUILD.bazel @@ -0,0 +1,13 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_atomic", + srcs = ["atomic.c"], + hdrs = ["include/stdatomic.h"], + copts = ["-Wno-atomic-alignment"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = ["//src/common/pico_sync"], +) diff --git a/src/rp2_common/pico_atomic/CMakeLists.txt b/src/rp2_common/pico_atomic/CMakeLists.txt new file mode 100644 index 000000000..f04cdba5c --- /dev/null +++ b/src/rp2_common/pico_atomic/CMakeLists.txt @@ -0,0 +1,14 @@ +if (NOT TARGET pico_atomic) + pico_add_library(pico_atomic) + + target_sources(pico_atomic INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/atomic.c + ) + + target_compile_options(pico_atomic INTERFACE +# -Wno-atomic-alignment + ) + target_include_directories(pico_atomic_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_link_libraries(pico_atomic INTERFACE pico_sync) +endif() diff --git a/src/rp2_common/pico_atomic/atomic.c b/src/rp2_common/pico_atomic/atomic.c new file mode 100644 index 000000000..e318356e5 --- /dev/null +++ b/src/rp2_common/pico_atomic/atomic.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "pico/sync.h" + +// We use __builtin_mem* to avoid libc dependency. +#define memcpy __builtin_memcpy +#define memcmp __builtin_memcmp + +static inline uint32_t atomic_lock(__unused const volatile void *ptr) { + uint32_t save = save_and_disable_interrupts(); +// __dmb(); not necessary on RP2040 + return save; +} + +static inline void atomic_unlock(__unused const volatile void *ptr, uint32_t save) { +// __dmb(); not necessary on RP2040 + restore_interrupts_from_disabled(save); +} + +#if PICO_C_COMPILER_IS_GNU + +_Bool __atomic_test_and_set_c(volatile void *mem, __unused int model) { + uint32_t save = atomic_lock(mem); + bool result = *(volatile bool *) mem; + *(volatile bool *) mem = true; + atomic_unlock(mem, save); + return result; +} + +#define __atomic_load_c __atomic_load +#define __atomic_store_c __atomic_store +#define __atomic_exchange_c __atomic_exchange +#define __atomic_compare_exchange_c __atomic_compare_exchange +#define __atomic_is_lock_free_c __atomic_is_lock_free +#else +// Clang objects if you redefine a builtin. +#pragma redefine_extname __atomic_load_c __atomic_load +#pragma redefine_extname __atomic_store_c __atomic_store +#pragma redefine_extname __atomic_exchange_c __atomic_exchange +#pragma redefine_extname __atomic_compare_exchange_c __atomic_compare_exchange +#pragma redefine_extname __atomic_is_lock_free_c __atomic_is_lock_free +#endif + +// Whether atomic operations for the given size (and alignment) are lock-free. +bool __atomic_is_lock_free_c(__unused size_t size, __unused const volatile void *ptr) { +#if !__ARM_ARCH_6M__ + if (size == 1 || size == 2 || size == 4) { + size_t align = size - 1; + return (((uintptr_t)ptr) & align) == 0; + } +#endif + return false; +} + + + +// An atomic load operation. This is atomic with respect to the source pointer only. +void __atomic_load_c(uint size, const volatile void *src, void *dest, __unused int model) { + uint32_t save = atomic_lock(src); + memcpy(dest, remove_volatile_cast_no_barrier(const void *, src), size); + atomic_unlock(src, save); +} + +// An atomic store operation. This is atomic with respect to the destination +// pointer only. +void __atomic_store_c(uint size, volatile void *dest, void *src, __unused int model) { + uint32_t save = atomic_lock(src); + memcpy(remove_volatile_cast_no_barrier(void *, dest), src, size); + atomic_unlock(src, save); +} + +// Atomic compare and exchange operation. If the value at *ptr is identical +// to the value at *expected, then this copies value at *desired to *ptr. If +// they are not, then this stores the current value from *ptr in *expected. +// +// This function returns 1 if the exchange takes place or 0 if it fails. +_Bool __atomic_compare_exchange_c(uint size, volatile void *ptr, void *expected, + void *desired, __unused int success, __unused int failure) { + uint32_t save = atomic_lock(ptr); + if (memcmp(remove_volatile_cast_no_barrier(void *, ptr), expected, size) == 0) { + memcpy(remove_volatile_cast_no_barrier(void *, ptr), desired, size); + atomic_unlock(ptr, save); + return 1; + } + memcpy(expected, remove_volatile_cast_no_barrier(void *, ptr), size); + atomic_unlock(ptr, save); + return 0; +} + +// Performs an atomic exchange operation between two pointers. This is atomic +// with respect to the target address. +void __atomic_exchange_c(uint size, volatile void *ptr, void *val, void *old, __unused int model) { + + uint32_t save = atomic_lock(ptr); + memcpy(old, remove_volatile_cast_no_barrier(void *, ptr), size); + memcpy(remove_volatile_cast_no_barrier(void *, ptr), val, size); + atomic_unlock(ptr, save); +} + +#if __ARM_ARCH_6M__ +#define ATOMIC_OPTIMIZED_CASES \ + ATOMIC_OPTIMIZED_CASE(1, uint8_t) \ + ATOMIC_OPTIMIZED_CASE(2, uint16_t) \ + ATOMIC_OPTIMIZED_CASE(4, uint) \ + ATOMIC_OPTIMIZED_CASE(8, uint64_t) +#else +#define ATOMIC_OPTIMIZED_CASES \ + ATOMIC_OPTIMIZED_CASE(8, uint64_t) +#endif + +#define ATOMIC_OPTIMIZED_CASE(n, type) \ + type __atomic_load_##n(const volatile void *src, __unused int memorder) { \ + uint32_t save = atomic_lock(src); \ + type val = *(const volatile type *)src; \ + atomic_unlock(src, save); \ + return val; \ + } + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE + +#define ATOMIC_OPTIMIZED_CASE(n, type) \ + void __atomic_store_##n(volatile void *dest, type val, __unused int model) { \ + uint32_t save = atomic_lock(dest); \ + *(volatile type *)dest = val; \ + atomic_unlock(dest, save); \ + } + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE + +#define ATOMIC_OPTIMIZED_CASE(n, type) \ + bool __atomic_compare_exchange_##n(volatile void *ptr, void *expected, type desired, \ + __unused bool weak, __unused int success, __unused int failure) { \ + uint32_t save = atomic_lock(ptr); \ + if (*(volatile type *)ptr == *(type *)expected) { \ + *(volatile type *)ptr = desired; \ + atomic_unlock(ptr, save); \ + return true; \ + } \ + *(type *)expected = *(volatile type *)ptr; \ + atomic_unlock(ptr, save); \ + return false; \ + } + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE + +#define ATOMIC_OPTIMIZED_CASE(n, type) \ + type __atomic_exchange_##n(volatile void *dest, type val, __unused int model) { \ + uint32_t save = atomic_lock(dest); \ + type tmp = *(volatile type *)dest; \ + *(volatile type *)dest = val; \ + atomic_unlock(dest, save); \ + return tmp; \ + } + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE + +// Atomic read-modify-write operations for integers of various sizes. + +#define ATOMIC_RMW(n, type, opname, op) \ + type __atomic_fetch_##opname##_##n(volatile void *ptr, type val, __unused int model) { \ + uint32_t save = atomic_lock(ptr); \ + type tmp = *(volatile type *)ptr; \ + *(volatile type *)ptr = tmp op val; \ + atomic_unlock(ptr, save); \ + return tmp; \ + } + +#define ATOMIC_RMW_NAND(n, type) \ + type __atomic_fetch_nand_##n(type *ptr, type val, __unused int model) { \ + uint32_t save = atomic_lock(ptr); \ + type tmp = *ptr; \ + *ptr = ~(tmp & val); \ + atomic_unlock(ptr, save); \ + return tmp; \ + } + +#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, add, +) + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE +#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, sub, -) + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE +#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, and, &) + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE +#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, or, |) + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE +#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW(n, type, xor, ^) + +ATOMIC_OPTIMIZED_CASES + +#undef ATOMIC_OPTIMIZED_CASE + +#if __has_builtin(__c11_atomic_fetch_nand) +#define ATOMIC_OPTIMIZED_CASE(n, type) ATOMIC_RMW_NAND(n, type) +ATOMIC_OPTIMIZED_CASES +#undef ATOMIC_OPTIMIZED_CASE +#endif diff --git a/src/rp2_common/pico_atomic/include/stdatomic.h b/src/rp2_common/pico_atomic/include/stdatomic.h new file mode 100644 index 000000000..f5ec4597c --- /dev/null +++ b/src/rp2_common/pico_atomic/include/stdatomic.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Stephen Street (stephen@redrocketcomputing.com). + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __STDATOMIC_H +#define __STDATOMIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file stdatomic.h + * \defgroup pico_atomic pico_atomic + * + * \brief Helper implementations for C11 atomics + * + * \if rp2040_specific + * On RP2040 a spin lock is used as protection for all atomic operations, since there is no C library support. + * \endif + * + * \if rp2350_specific + * On RP2350 the C-library provides implementations for all 1-byte, 2-byte and 4-byte atomics using processor + * exclusive operations. This library provides a spin-lock protected version for arbitrary-sized atomics (including 64-bit). + * \endif +*/ +#include +#include_next + +// needed for PICO_C_COMPILER_IS_GNU +#include "pico.h" + +#if PICO_RP2040 && PICO_C_COMPILER_IS_GNU +// on GNU without exclusive instructions these don't get routed thru _1 functions for some reason +#undef atomic_flag_test_and_set +#undef atomic_flag_test_and_set_explicit + +extern _Bool __atomic_test_and_set_c(volatile void *mem, int model); + +#define atomic_flag_test_and_set(PTR) __atomic_test_and_set_c((PTR), __ATOMIC_SEQ_CST) +#define atomic_flag_test_and_set_explicit(PTR, MO) __atomic_test_and_set_c((PTR), (MO)) +#endif + +#ifdef __cplusplus +} +#endif +#endif diff --git a/src/rp2_common/pico_bit_ops/BUILD.bazel b/src/rp2_common/pico_bit_ops/BUILD.bazel index 0daadd0a9..66af3fd9e 100644 --- a/src/rp2_common/pico_bit_ops/BUILD.bazel +++ b/src/rp2_common/pico_bit_ops/BUILD.bazel @@ -5,24 +5,26 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "pico_bit_ops", srcs = ["bit_ops_aeabi.S"], - linkopts = [ - "-Wl,--wrap=__clzsi2", - "-Wl,--wrap=__clzsi2", - "-Wl,--wrap=__clzdi2", - "-Wl,--wrap=__ctzsi2", - "-Wl,--wrap=__ctzdi2", - "-Wl,--wrap=__popcountsi2", - "-Wl,--wrap=__popcountdi2", - "-Wl,--wrap=__clz", - "-Wl,--wrap=__clzl", - "-Wl,--wrap=__clzsi2", - "-Wl,--wrap=__clzll", - ], + linkopts = select({ + "//bazel/constraint:rp2040": [ + "-Wl,--wrap=__clzsi2", + "-Wl,--wrap=__clzsi2", + "-Wl,--wrap=__clzdi2", + "-Wl,--wrap=__ctzsi2", + "-Wl,--wrap=__popcountsi2", + "-Wl,--wrap=__popcountdi2", + "-Wl,--wrap=__clz", + "-Wl,--wrap=__clzl", + "-Wl,--wrap=__clzsi2", + "-Wl,--wrap=__clzll", + ], + "//conditions:default": [], + }) + ["-Wl,--wrap=__ctzdi2"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_bit_ops:pico_bit_ops_headers", + "//src/common/pico_bit_ops_headers:pico_bit_ops_interface", + "//src/rp2_common:pico_platform_internal", "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) diff --git a/src/rp2_common/pico_bit_ops/CMakeLists.txt b/src/rp2_common/pico_bit_ops/CMakeLists.txt index ca420078c..a66a441f6 100644 --- a/src/rp2_common/pico_bit_ops/CMakeLists.txt +++ b/src/rp2_common/pico_bit_ops/CMakeLists.txt @@ -21,20 +21,23 @@ if (NOT TARGET pico_bit_ops) target_link_libraries(pico_bit_ops_pico INTERFACE pico_bootrom pico_bit_ops_headers) - # gcc - pico_wrap_function(pico_bit_ops_pico __clzsi2) - pico_wrap_function(pico_bit_ops_pico __clzsi2) - pico_wrap_function(pico_bit_ops_pico __clzdi2) - pico_wrap_function(pico_bit_ops_pico __ctzsi2) + if (NOT PICO_RP2350) + # gcc + pico_wrap_function(pico_bit_ops_pico __clzsi2) + pico_wrap_function(pico_bit_ops_pico __clzsi2) + pico_wrap_function(pico_bit_ops_pico __clzdi2) + pico_wrap_function(pico_bit_ops_pico __ctzsi2) + pico_wrap_function(pico_bit_ops_pico __popcountsi2) + pico_wrap_function(pico_bit_ops_pico __popcountdi2) + + # armclang + pico_wrap_function(pico_bit_ops_pico __clz) + pico_wrap_function(pico_bit_ops_pico __clzl) + pico_wrap_function(pico_bit_ops_pico __clzsi2) + pico_wrap_function(pico_bit_ops_pico __clzll) + endif() + # this is overridden for RP2350 since GCCs impl is bad for both ARM and RISC-V pico_wrap_function(pico_bit_ops_pico __ctzdi2) - pico_wrap_function(pico_bit_ops_pico __popcountsi2) - pico_wrap_function(pico_bit_ops_pico __popcountdi2) - - # armclang - pico_wrap_function(pico_bit_ops_pico __clz) - pico_wrap_function(pico_bit_ops_pico __clzl) - pico_wrap_function(pico_bit_ops_pico __clzsi2) - pico_wrap_function(pico_bit_ops_pico __clzll) macro(pico_set_bit_ops_implementation TARGET IMPL) get_target_property(target_type ${TARGET} TYPE) diff --git a/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S b/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S index 02837dcf3..65a1bb4c9 100644 --- a/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S +++ b/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S @@ -6,6 +6,7 @@ #include "pico/asm_helper.S" #include "pico/bootrom.h" +#include "pico/runtime_init.h" pico_default_asm_setup @@ -17,7 +18,8 @@ pico_default_asm_setup #endif .endm -__pre_init __aeabi_bits_init, 00010 +#if PICO_RP2040 +PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_bits_init, PICO_RUNTIME_INIT_AEABI_BIT_OPS) .section .data.aeabi_bits_funcs .global aeabi_bits_funcs, aeabi_bits_funcs_end @@ -105,21 +107,17 @@ wrapper_func __popcountdi2 add r0, r1 pop {pc} -bits_section reverse32 -regular_func reverse32 - ldr r3, =aeabi_bits_funcs - ldr r3, [r3, #REVERSE32] - bx r3 - bits_section __rev regular_func __rev regular_func __revl +regular_func reverse32 ldr r3, =aeabi_bits_funcs ldr r3, [r3, #REVERSE32] bx r3 bits_section __revll regular_func __revll +regular_func reverse64 push {lr} ldr r3, =aeabi_bits_funcs ldr r3, [r3, #REVERSE32] @@ -130,3 +128,63 @@ regular_func __revll blx r3 mov r1, ip pop {pc} + +#else // RP2350 + +bits_section __rev +regular_func __rev +regular_func __revl +regular_func reverse32 +#ifdef __riscv + rev8 a0, a0 + brev8 a0, a0 + ret +#else + rbit r0, r0 + bx lr +#endif + +bits_section __revll +regular_func __revll +regular_func reverse64 +#ifdef __riscv + rev8 a0, a0 + brev8 a0, a0 + rev8 a1, a1 + brev8 a1, a1 + mv a2, a0 + mv a0, a1 + mv a1, a2 + ret +#else + mov r2, r1 + rbit r1, r0 + rbit r0, r2 + bx lr +#endif + +// todo gcc riscv version is nuts; we'll provide both versions for simplicity in CMakeLists.txt +// (also gcc arm version is a bit pants) +bits_section ctzdi +wrapper_func __ctzdi2 +#ifdef __riscv + beqz a0, 1f + ctz a0, a0 + ret +1: + ctz a0, a1 + addi a0, a0, 32 + ret +#else + cbz r0, 1f + rbit r0, r0 + clz r0, r0 + bx lr +1: + rbit r0, r1 + clz r0, r0 + adds r0, #32 + bx lr +#endif + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_bootrom/BUILD.bazel b/src/rp2_common/pico_bootrom/BUILD.bazel index 586ddd774..5a7060938 100644 --- a/src/rp2_common/pico_bootrom/BUILD.bazel +++ b/src/rp2_common/pico_bootrom/BUILD.bazel @@ -2,17 +2,50 @@ load("//bazel:defs.bzl", "compatible_with_rp2") package(default_visibility = ["//visibility:public"]) +# Picotool needs this, so we can't strictly constrain compatibility. +cc_library( + name = "pico_bootrom_headers", + hdrs = [ + "include/pico/bootrom.h", + "include/pico/bootrom/lock.h", + "include/pico/bootrom/sf_table.h", + "include/pico/bootrom_constants.h", + ], + includes = ["include"], + tags = ["manual"], + visibility = ["@picotool//:__subpackages__"], + deps = [ + "//src/rp2_common/hardware_boot_lock:hardware_boot_lock_headers", + ], +) + cc_library( name = "pico_bootrom", - srcs = ["bootrom.c"], + srcs = [ + "bootrom.c", + "bootrom_lock.c", + ], hdrs = [ "include/pico/bootrom.h", + "include/pico/bootrom/lock.h", "include/pico/bootrom/sf_table.h", + "include/pico/bootrom_constants.h", + ], + implementation_deps = [ + "//src/common/boot_picobin_headers", + "//src/common/boot_picoboot_headers", + "//src/rp2_common/hardware_sync", + "//src/rp2_common/pico_runtime_init", ], includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", - "//src/common/pico_base:pico_platform", - ], + "//src/rp2_common/hardware_boot_lock", + ] + select({ + "//bazel/constraint:host": [ + ], + "//conditions:default": [ + "//src/rp2_common:pico_platform_internal", + ], + }), ) diff --git a/src/rp2_common/pico_bootrom/CMakeLists.txt b/src/rp2_common/pico_bootrom/CMakeLists.txt index da7d91503..0648098b9 100644 --- a/src/rp2_common/pico_bootrom/CMakeLists.txt +++ b/src/rp2_common/pico_bootrom/CMakeLists.txt @@ -1,10 +1,12 @@ pico_add_library(pico_bootrom_headers NOFLAG) -target_include_directories(pico_bootrom_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_bootrom_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) add_library(pico_bootrom INTERFACE) target_sources(pico_bootrom INTERFACE ${CMAKE_CURRENT_LIST_DIR}/bootrom.c + ${CMAKE_CURRENT_LIST_DIR}/bootrom_lock.c ) -pico_mirrored_target_link_libraries(pico_bootrom INTERFACE pico_base) +target_link_libraries(pico_bootrom_headers INTERFACE boot_picoboot_headers) +pico_mirrored_target_link_libraries(pico_bootrom INTERFACE pico_base hardware_boot_lock) diff --git a/src/rp2_common/pico_bootrom/bootrom.c b/src/rp2_common/pico_bootrom/bootrom.c index 011568660..84fbffd06 100644 --- a/src/rp2_common/pico_bootrom/bootrom.c +++ b/src/rp2_common/pico_bootrom/bootrom.c @@ -5,6 +5,8 @@ */ #include "pico/bootrom.h" +#include "boot/picoboot.h" +#include "boot/picobin.h" /// \tag::table_lookup[] @@ -12,11 +14,20 @@ void *rom_func_lookup(uint32_t code) { return rom_func_lookup_inline(code); } +#pragma GCC diagnostic push +// diagnostic: GCC thinks near-zero value is a null pointer member access, but it's not +#pragma GCC diagnostic ignored "-Warray-bounds" void *rom_data_lookup(uint32_t code) { - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); - uint16_t *data_table = (uint16_t *) rom_hword_as_ptr(0x16); +#if PICO_RP2040 + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(BOOTROM_TABLE_LOOKUP_OFFSET); + uint16_t *data_table = (uint16_t *) rom_hword_as_ptr(BOOTROM_DATA_TABLE_OFFSET); return rom_table_lookup(data_table, code); +#else + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET); + return rom_table_lookup(code, RT_FLAG_DATA); +#endif } +#pragma GCC diagnostic pop /// \end::table_lookup[] bool rom_funcs_lookup(uint32_t *table, unsigned int count) { @@ -27,3 +38,65 @@ bool rom_funcs_lookup(uint32_t *table, unsigned int count) { } return ok; } + + +void __attribute__((noreturn)) rom_reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { +#ifdef ROM_FUNC_RESET_USB_BOOT + rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT); + func(usb_activity_gpio_pin_mask, disable_interface_mask); +#elif defined(ROM_FUNC_REBOOT) + uint32_t flags = disable_interface_mask; + if (usb_activity_gpio_pin_mask) { + flags |= BOOTSEL_FLAG_GPIO_PIN_SPECIFIED; + // the parameter is actually the gpio number, but we only care if BOOTSEL_FLAG_GPIO_PIN_SPECIFIED + usb_activity_gpio_pin_mask = (uint32_t)__builtin_ctz(usb_activity_gpio_pin_mask); + } + rom_reboot(REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL | REBOOT2_FLAG_NO_RETURN_ON_SUCCESS, 10, flags, usb_activity_gpio_pin_mask); + __builtin_unreachable(); +#else + panic_unsupported(); +#endif +} + +#if !PICO_RP2040 +bool rom_get_boot_random(uint32_t out[4]) { + uint32_t result[5]; + rom_get_sys_info_fn func = (rom_get_sys_info_fn) rom_func_lookup_inline(ROM_FUNC_GET_SYS_INFO); + if (5 == func(result, count_of(result), SYS_INFO_BOOT_RANDOM)) { + for(uint i=0;i<4;i++) { + out[i] = result[i+1]; + } + return true; + } + return false; +} + +int rom_add_flash_runtime_partition(uint32_t start_offset, uint32_t size, uint32_t permissions) { + if ((start_offset) & 4095 || (size & 4095)) return PICO_ERROR_BAD_ALIGNMENT; + if (!size || start_offset + size > 32 * 1024 * 1024) return PICO_ERROR_INVALID_ARG; + if (permissions & ~PICOBIN_PARTITION_PERMISSIONS_BITS) return PICO_ERROR_INVALID_ARG; + + void **ptr = (void **)rom_data_lookup(ROM_DATA_PARTITION_TABLE_PTR); + assert(ptr); + assert(*ptr); + struct pt { + struct { + uint8_t partition_count; + uint8_t permission_partition_count; // >= partition_count and includes any regions added at runtime + bool loaded; + }; + uint32_t unpartitioned_space_permissions_and_flags; + resident_partition_t partitions[PARTITION_TABLE_MAX_PARTITIONS]; + } *pt = (struct pt *)*ptr; + assert(pt->loaded); // even if empty it should have been populated by the bootrom + if (pt->permission_partition_count < pt->partition_count) pt->permission_partition_count = pt->partition_count; + if (pt->permission_partition_count < PARTITION_TABLE_MAX_PARTITIONS) { + pt->partitions[pt->permission_partition_count].permissions_and_location = permissions | + ((start_offset / 4096) << PICOBIN_PARTITION_LOCATION_FIRST_SECTOR_LSB) | + ((start_offset + size - 4096) / 4096) << PICOBIN_PARTITION_LOCATION_LAST_SECTOR_LSB; + pt->partitions[pt->permission_partition_count].permissions_and_flags = permissions; + return pt->permission_partition_count++; + } + return PICO_ERROR_INSUFFICIENT_RESOURCES; +} +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_bootrom/bootrom_lock.c b/src/rp2_common/pico_bootrom/bootrom_lock.c new file mode 100644 index 000000000..9f59d0504 --- /dev/null +++ b/src/rp2_common/pico_bootrom/bootrom_lock.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/bootrom/lock.h" +#include "pico/runtime_init.h" + +#if PICO_BOOTROM_LOCKING_ENABLED +#if !PICO_RUNTIME_NO_INIT_BOOTROM_LOCKING_ENABLE +#include "hardware/sync.h" +void __weak runtime_init_bootrom_locking_enable(void) { + bootrom_acquire_lock_blocking(BOOTROM_LOCK_ENABLE); +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE +PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_bootrom_locking_enable, PICO_RUNTIME_INIT_BOOTROM_LOCKING_ENABLE); +#endif +#endif diff --git a/src/rp2_common/pico_bootrom/include/pico/bootrom.h b/src/rp2_common/pico_bootrom/include/pico/bootrom.h index e731ffef4..b55e0988a 100644 --- a/src/rp2_common/pico_bootrom/include/pico/bootrom.h +++ b/src/rp2_common/pico_bootrom/include/pico/bootrom.h @@ -8,47 +8,21 @@ #define _PICO_BOOTROM_H #include "pico.h" +#include "pico/bootrom_constants.h" /** \file bootrom.h * \defgroup pico_bootrom pico_bootrom - * \brief Access to functions and data in the RP2040 bootrom + * \brief Access to functions and data in the bootrom * * This header may be included by assembly code */ -// ROM FUNCTIONS - -#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3') -#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3') -#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3') -#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3') -#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S') -#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4') -#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C') -#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4') -#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B') -#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') -#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') -#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') -#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') -#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') -#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') - -/*! \brief Return a bootrom lookup code based on two ASCII characters - * \ingroup pico_bootrom - * - * These codes are uses to lookup data or function addresses in the bootrom - * - * \param c1 the first character - * \param c2 the second character - * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() - */ -#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) - #ifndef __ASSEMBLER__ - +#include +#include "pico/bootrom/lock.h" // ROM FUNCTION SIGNATURES +#if PICO_RP2040 typedef uint32_t (*rom_popcount32_fn)(uint32_t); typedef uint32_t (*rom_reverse32_fn)(uint32_t); typedef uint32_t (*rom_clz32_fn)(uint32_t); @@ -57,7 +31,9 @@ typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t); typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t); typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t); typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t); +#endif typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t); +typedef int (*rom_reboot_fn)(uint32_t flags, uint32_t delay_ms, uint32_t p0, uint32_t p1); typedef rom_reset_usb_boot_fn reset_usb_boot_fn; // kept for backwards compatibility typedef void (*rom_connect_internal_flash_fn)(void); typedef void (*rom_flash_exit_xip_fn)(void); @@ -65,6 +41,67 @@ typedef void (*rom_flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint8_t); typedef void (*rom_flash_range_program_fn)(uint32_t, const uint8_t*, size_t); typedef void (*rom_flash_flush_cache_fn)(void); typedef void (*rom_flash_enter_cmd_xip_fn)(void); +#if !PICO_RP2040 +typedef void (*rom_bootrom_state_reset_fn)(uint32_t flags); +typedef void (*rom_flash_reset_address_trans_fn)(void); +typedef void (*rom_flash_select_xip_read_mode_fn)(bootrom_xip_mode_t mode, uint8_t clkdiv); +typedef int (*rom_get_sys_info_fn)(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t flags); +typedef int (*rom_get_partition_table_info_fn)(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t partition_and_flags); +typedef int (*rom_explicit_buy_fn)(uint8_t *buffer, uint32_t buffer_size); +typedef void* (*rom_validate_ns_buffer_fn)(const void *addr, uint32_t size, uint32_t write, uint32_t *ok); +/** + * @return BOOTROM_OK if successful + * BOOTROM_ERROR_INVALID_ARG if ns_api_num is out of range + */ +typedef intptr_t (*rom_set_rom_callback_fn)(uint callback_num, bootrom_api_callback_generic_t funcptr); +typedef int (*rom_chain_image_fn)(uint8_t *workarea_base, uint32_t workarea_size, uint32_t window_base, uint32_t window_size); +typedef int (*rom_load_partition_table_fn)(uint8_t *workarea_base, uint32_t workarea_size, bool force_reload); +typedef int (*rom_pick_ab_partition_fn)(uint8_t *workarea_base, uint32_t workarea_size, uint partition_a_num, uint32_t flash_update_boot_window_base); +typedef int (*rom_get_b_partition_fn)(uint pi_a); +typedef int (*rom_get_uf2_target_partition_fn)(uint8_t *workarea_base, uint32_t workarea_size, uint32_t family_id, resident_partition_t *partition_out); +typedef int (*rom_func_otp_access_fn)(uint8_t *buf, uint32_t buf_len, otp_cmd_t cmd); +// Apply the address translation currently specified in QMI_ATRANSx ("rolling window" hardware +// translation). Need to take care using this on the boot path, as the QMI may not yet have been +// set up, but this should be suitable for translating system bus addresses into flash storage +// addresses in user callbacks. Returns all-ones for an invalid address, which is also an invalid +// flash storage address, so invalidity is propagated. +typedef intptr_t (*rom_flash_runtime_to_storage_addr_fn)(uintptr_t flash_runtime_addr); + +// Perform the specified erase/program/read operation, translating addresses according to +// QMI_ATRANSx if necessary, and checking flash permissions based on the resident partition table +// and the specified effective security level. `addr` may be either a flash runtime address or a +// flash storage address, depending on the ASPACE given in `flags`. +// +// NOTE: This function does not validate the buffer for NS access. This must be validated before +// calling if the caller is reachable from a Secure Gateway. +typedef int (*rom_flash_op_fn)(cflash_flags_t flags, uintptr_t addr, uint32_t size_bytes, uint8_t *buf); + +#ifndef __riscv +typedef int (*rom_set_ns_api_permission_fn)(uint ns_api_num, bool allowed); +/** + * Note this is not strictly a C function; you must pass the function you are calling in r4 + * @param in_r4 + * `0b0xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx` - a "well known" function selector; do not use for your own methods + * `0b10xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx` - a "unique" function selector intended to be unlikely to clash with others'. + * The lower 30 bits should be chosen at random + * `0b11xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx` - a "private" function selector intended for use by tightly coupled NS and S code + * + * @return whatever the secure call returns + * BOOTROM_ERROR_INVALID_STATE if no secure handler has been set from the secure side + * via rom_set_rom_callback_fn(BOOTROM_API_CALLBACK_secure_call, ...) + */ +typedef int (*rom_func_secure_call)(uintptr_t a0, ...); +#endif + +#ifdef __riscv +typedef struct { + uint32_t *base; + uint32_t size; +} bootrom_stack_t; +// passed in, and out. +typedef int (*rom_set_bootrom_stack_fn)(bootrom_stack_t *stack); +#endif +#endif #ifdef __cplusplus extern "C" { @@ -84,7 +121,7 @@ static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) { } /*! - * \brief Lookup a bootrom function by code + * \brief Lookup a bootrom function by its code * \ingroup pico_bootrom * \param code the code * \return a pointer to the function, or NULL if the code does not match any bootrom function @@ -92,7 +129,7 @@ static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) { void *rom_func_lookup(uint32_t code); /*! - * \brief Lookup a bootrom address by code + * \brief Lookup a bootrom data address by its code * \ingroup pico_bootrom * \param code the code * \return a pointer to the data, or NULL if the code does not match any bootrom function @@ -114,11 +151,15 @@ bool rom_funcs_lookup(uint32_t *table, unsigned int count); // Bootrom function: rom_table_lookup // Returns the 32 bit pointer into the ROM if found or NULL otherwise. +#if PICO_RP2040 typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); +#else +typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask); +#endif #if PICO_C_COMPILER_IS_GNU && (__GNUC__ >= 12) // Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer -static __force_inline void *rom_hword_as_ptr(uint16_t rom_address) { +__force_inline static void *rom_hword_as_ptr(uint16_t rom_address) { #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Warray-bounds" return (void *)(uintptr_t)*(uint16_t *)(uintptr_t)rom_address; @@ -129,17 +170,74 @@ static __force_inline void *rom_hword_as_ptr(uint16_t rom_address) { #define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)(uintptr_t)(rom_address)) #endif +#ifdef __riscv +static __force_inline bool rom_size_is_64k(void) { +#ifdef RASPBERRYPI_AMETHYST_FPGA + // Detect ROM size by testing for bus fault at +32k + uint result; + pico_default_asm_volatile ( + "li %0, 0\n" + // Save and disable IRQs before touching trap vector + "csrr t2, mstatus\n" + "csrci mstatus, 0x8\n" + // Set up trap vector to skip the instruction which sets the %0 flag + "la t0, 1f\n" + "csrrw t0, mtvec, t0\n" + // This load will fault if the bootrom is no larger than 32k: + "li t1, 32 * 1024\n" + "lw t1, (t1)\n" + // No fault, so set return to true + "li %0, 1\n" + ".p2align 2\n" + // Always end up back here, restore the trap table + "1:\n" + "csrw mtvec, t0\n" + // Now safe to restore interrupts + "csrw mstatus, t2\n" + : "=r" (result) + : + : "t0", "t1", "t2" + ); + return result; +#else + return false; +#endif +} +#endif + /*! * \brief Lookup a bootrom function by code. This method is forcibly inlined into the caller for FLASH/RAM sensitive code usage * \ingroup pico_bootrom * \param code the code * \return a pointer to the function, or NULL if the code does not match any bootrom function */ +#pragma GCC diagnostic push +// diagnostic: GCC thinks near-zero value is a null pointer member access, but it's not +#pragma GCC diagnostic ignored "-Warray-bounds" static __force_inline void *rom_func_lookup_inline(uint32_t code) { - rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); - uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14); +#if PICO_RP2040 + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(BOOTROM_TABLE_LOOKUP_OFFSET); + uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(BOOTROM_FUNC_TABLE_OFFSET); return rom_table_lookup(func_table, code); +#else +#ifdef __riscv + uint32_t rom_offset_adjust = rom_size_is_64k() ? 32 * 1024 : 0; + // on RISC-V the code (a jmp) is actually embedded in the table + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET + rom_offset_adjust); + return rom_table_lookup(code, RT_FLAG_FUNC_RISCV); +#else + // on ARM the function pointer is stored in the table, so we dereference it + // via lookup() rather than lookup_entry() + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET); + if (pico_processor_state_is_nonsecure()) { + return rom_table_lookup(code, RT_FLAG_FUNC_ARM_NONSEC); + } else { + return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC); + } +#endif +#endif } +#pragma GCC diagnostic pop /*! * \brief Reboot the device into BOOTSEL mode @@ -158,12 +256,773 @@ static __force_inline void *rom_func_lookup_inline(uint32_t code) { * - 1 To disable the USB Mass Storage Interface * - 2 To disable the USB PICOBOOT Interface */ -static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, - uint32_t disable_interface_mask) { - rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT); - func(usb_activity_gpio_pin_mask, disable_interface_mask); +void __attribute__((noreturn)) rom_reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask); +static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask, uint32_t disable_interface_mask) { + rom_reset_usb_boot(usb_activity_gpio_pin_mask, disable_interface_mask); +} + +/*! + * \brief Connect the SSI/QMI to the QSPI pads + * \ingroup pico_bootrom + * + * Restore all QSPI pad controls to their default state, and connect the SSI/QMI peripheral to the QSPI pads. + * + * \if rp2350_specific + * On RP2350 if a secondary flash chip select GPIO has been configured via OTP OTP_DATA_FLASH_DEVINFO, or by writing to the runtime + * copy of FLASH_DEVINFO in bootram, then this bank 0 GPIO is also initialised and the QMI peripheral is connected. Otherwise, + * bank 0 IOs are untouched. + * \endif + */ +static inline void rom_connect_internal_flash() { + rom_connect_internal_flash_fn func = (rom_connect_internal_flash_fn) rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); + func(); +} + +/*! + * \brief Return the QSPI device from its XIP state to a serial command state + * \ingroup pico_bootrom + * + * \if rp2040_specific + * On RP2040, first set up the SSI for serial-mode operations, then issue the fixed XIP exit sequence described in Section 2.8.1.2 + * of the datasheet. Note that the bootrom code uses the IO forcing logic to drive the CS pin, which must be cleared before returning + * the SSI to XIP mode (e.g. by a call to _flash_flush_cache). This function configures the SSI with a fixed SCK clock divisor of /6. + * \endif + * + * \if rp2350_specific + * On RP2350, Initialise the QMI for serial operations (direct mode), and also initialise a basic XIP mode, where the QMI will perform + * 03h serial read commands at low speed (CLKDIV=12) in response to XIP reads. + * + * Then, issue a sequence to the QSPI device on chip select 0, designed to return it from continuous read mode ("XIP mode") and/or + * QPI mode to a state where it will accept serial commands. This is necessary after system reset to restore the QSPI device to a known + * state, because resetting RP2350 does not reset attached QSPI devices. It is also necessary when user code, having already performed + * some continuous-read-mode or QPI-mode accesses, wishes to return the QSPI device to a state where it will accept the serial erase and + * programming commands issued by the bootrom's flash access functions. + * + * If a GPIO for the secondary chip select is configured via FLASH_DEVINFO, then the XIP exit sequence is also issued to chip select 1. + * + * The QSPI device should be accessible for XIP reads after calling this function; the name flash_exit_xip refers to returning the QSPI + * device from its XIP state to a serial command state. + * \endif + */ +static inline void rom_flash_exit_xip() { + rom_flash_exit_xip_fn func = (rom_flash_exit_xip_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); + func(); +} + +/*! + * \brief Erase bytes in flash + * \ingroup pico_bootrom + * + * Erase count bytes, starting at addr (offset from start of flash). Optionally, pass a block erase command e.g. D8h block erase, + * and the size of the block erased by this command - this function will use the larger block erase where possible, for much higher + * erase speed. addr must be aligned to a 4096-byte sector, and count must be a multiple of 4096 bytes. + * + * This is a low-level flash API, and no validation of the arguments is performed. + * + * \if rp2350_specific + * See rom_flash_op on RP2350 for a higher-level API which checks alignment, flash bounds and partition permissions, and can transparently + * apply a runtime-to-storage address translation. + * + * The QSPI device must be in a serial command state before calling this API, which can be achieved by calling rom_connect_internal_flash() + * followed by rom_flash_exit_xip(). After the erase, the flash cache should be flushed via rom_flash_flush_cache() to ensure the modified + * flash data is visible to cached XIP accesses. + * + * Finally, the original XIP mode should be restored by copying the saved XIP setup function from bootram into SRAM, and executing it: + * the bootrom provides a default function which restores the flash mode/clkdiv discovered during flash scanning, and user programs can + * override this with their own XIP setup function. + * + * For the duration of the erase operation, QMI is in direct mode and attempting to access XIP from DMA, the debugger or the other core will + * return a bus fault. XIP becomes accessible again once the function returns. + * \endif + * + * \param addr the offset from start of flash to be erased + * \param count number of bytes to erase + * \param block_size optional size of block erased by block_cmd + * \param block_cmd optional block erase command e.g. D8h block erase + */ +static inline void rom_flash_range_erase(uint32_t addr, size_t count, uint32_t block_size, uint8_t block_cmd) { + rom_flash_range_erase_fn func = (rom_flash_range_erase_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE); + func(addr, count, block_size, block_cmd); +} + +/*! + * \brief Program bytes in flash + * \ingroup pico_bootrom + * + * Program data to a range of flash addresses starting at addr (offset from the start of flash) and count bytes in size. addr must be + * aligned to a 256-byte boundary, and count must be a multiple of 256. + * + * This is a low-level flash API, and no validation of the arguments is performed. + * + * \if rp2350_specific + * See rom_flash_op on RP2350 for a higher-level API which checks alignment, flash bounds and partition permissions, + * and can transparently apply a runtime-to-storage address translation. + * + * The QSPI device must be in a serial command state before calling this API - see notes on rom_flash_range_erase + * \endif + * + * \param addr the offset from start of flash to be erased + * \param data buffer containing the data to be written + * \param count number of bytes to erase + */ +static inline void rom_flash_range_program(uint32_t addr, const uint8_t *data, size_t count) { + rom_flash_range_program_fn func = (rom_flash_range_program_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM); + func(addr, data, count); +} + +/*! + * \brief Flush the XIP cache + * \ingroup pico_bootrom + * + * \if rp2040_specific + * Flush and enable the XIP cache. Also clears the IO forcing on QSPI CSn, so that the SSI can drive the flash chip select as normal. + * \endif + * + * \if rp2350_specific + * Flush the entire XIP cache, by issuing an invalidate by set/way maintenance operation to every cache line. This ensures that flash + * program/erase operations are visible to subsequent cached XIP reads. + * + * Note that this unpins pinned cache lines, which may interfere with cache-as-SRAM use of the XIP cache. + * + * No other operations are performed. + * \endif + */ +static inline void rom_flash_flush_cache() { + rom_flash_flush_cache_fn func = (rom_flash_flush_cache_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); + func(); +} + +/*! + * \brief Configure the SSI/QMI with a standard command + * \ingroup pico_bootrom + * + * Configure the SSI/QMI to generate a standard 03h serial read command, with 24 address bits, upon each XIP access. This is a slow XIP + * configuration, but is widely supported. CLKDIV is set to 12 on RP2350. The debugger may call this function to ensure that flash is + * readable following a program/erase operation. + * + * Note that the same setup is performed by flash_exit_xip(), and the RP2350 flash program/erase functions do not leave XIP in an + * inaccessible state, so calls to this function are largely redundant on RP2350. It is provided on RP2350 for compatibility with RP2040. + */ +static inline void rom_flash_enter_cmd_xip() { + rom_flash_enter_cmd_xip_fn func = (rom_flash_enter_cmd_xip_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP); + func(); +} + +#if !PICO_RP2040 +#ifdef __riscv +/*! + * \brief Give the bootrom a new stack + * \ingroup pico_bootrom + * + * Most bootrom functions are written just once, in Arm code, to save space. As a result these functions are emulated when + * running under the RISC-V architecture. This is largely transparent to the user, however the stack used by the Arm emulation + * is separate from the calling user's stack, and is stored in boot RAM but is of quite limited size. When using certain of the more + * complex APIs or if nesting bootrom calls from within IRQs, you may need to provide a large stack. + * + * This method allows the caller to specify a region of RAM to use as the stack for the current core by passing a pointer to two values: the word aligned base address, + * and the size in bytes (multiple of 4). + * + * The method fills in the previous base/size values into the passed array before returning. + * + * \param stack bootrom_stack_t struct containing base and size + */ +static inline int rom_set_bootrom_stack(bootrom_stack_t *stack) { + rom_set_bootrom_stack_fn func = (rom_set_bootrom_stack_fn) rom_func_lookup_inline(ROM_FUNC_SET_BOOTROM_STACK); + return func(stack); +} +#endif + +/*! + * \brief Reboot using the watchdog + * \ingroup pico_bootrom + * + * Resets the chip and uses the watchdog facility to restart. + * + * The delay_ms is the millisecond delay before the reboot occurs. Note: by default this method is asynchronous + * (unless NO_RETURN_ON_SUCCESS is set - see below), so the method will return and the reboot will happen this many milliseconds later. + * + * The flags field contains one of the following values: + * + * REBOOT_TYPE_NORMAL - reboot into the normal boot path. + * + * REBOOT_TYPE_BOOTSEL - reboot into BOOTSEL mode. + * p0 - the GPIO number to use as an activity indicator (enabled by flag in p1). + * p1 - a set of flags: + * 0x01 : DISABLE_MSD_INTERFACE - Disable the BOOTSEL USB drive (see <>) + * 0x02 : DISABLE_PICOBOOT_INTERFACE - Disable the {picoboot} interface (see <>). + * 0x10 : GPIO_PIN_ACTIVE_LOW - The GPIO in p0 is active low. + * 0x20 : GPIO_PIN_ENABLED - Enable the activity indicator on the specified GPIO. + * + * REBOOT_TYPE_RAM_IMAGE - reboot into an image in RAM. The region of RAM or XIP RAM is searched for an image to run. This is the type + * of reboot used when a RAM UF2 is dragged onto the BOOTSEL USB drive. + * p0 - the region start address (word-aligned). + * p1 - the region size (word-aligned). + * + * REBOOT_TYPE_FLASH_UPDATE - variant of REBOOT_TYPE_NORMAL to use when flash has been updated. This is the type + * of reboot used after dragging a flash UF2 onto the BOOTSEL USB drive. + * p0 - the address of the start of the region of flash that was updated. If this address matches the start address of a partition or slot, then that + * partition or slot is treated preferentially during boot (when there is a choice). This type of boot facilitates TBYB and version downgrades. + * + * REBOOT_TYPE_PC_SP - reboot to a specific PC and SP. Note: this is not allowed in the ARM-NS variant. + * p0 - the initial program counter (PC) to start executing at. This must have the lowest bit set for Arm and clear for RISC-V + * p1 - the initial stack pointer (SP). + * + * All of the above, can have optional flags ORed in: + * + * REBOOT_TO_ARM - switch both cores to the Arm architecture (rather than leaving them as is). The call will fail with BOOTROM_ERROR_INVALID_STATE if the Arm architecture is not supported. + * REBOOT_TO_RISCV - switch both cores to the RISC-V architecture (rather than leaving them as is). The call will fail with BOOTROM_ERROR_INVALID_STATE if the RISC-V architecture is not supported. + * NO_RETURN_ON_SUCCESS - the watchdog h/w is asynchronous. Setting this bit forces this method not to return if the reboot is successfully initiated. + * + * \param flags the reboot flags, as detailed above + * \param delay_ms millisecond delay before the reboot occurs + * \param p0 parameter 0, depends on flags + * \param p1 parameter 1, depends on flags + */ +static inline int rom_reboot(uint32_t flags, uint32_t delay_ms, uint32_t p0, uint32_t p1) { + rom_reboot_fn func = (rom_reboot_fn) rom_func_lookup_inline(ROM_FUNC_REBOOT); + return func(flags, delay_ms, p0, p1); +} + +bool rom_get_boot_random(uint32_t out[4]); + +/*! + * \brief Reset bootrom state + * \ingroup pico_bootrom + * + * Resets internal bootrom state, based on the following flags: + * + * STATE_RESET_CURRENT_CORE - Resets any internal bootrom state for the current core into a clean state. + * This method should be called prior to calling any other bootrom APIs on the current core, + * and is called automatically by the bootrom during normal boot of core 0 and launch of code on core 1. + * + * STATE_RESET_OTHER_CORE - Resets any internal bootrom state for the other core into a clean state. This is generally called by + * a debugger when resetting the state of one core via code running on the other. + * + * STATE_RESET_GLOBAL_STATE - Resets all non core-specific state, including: + * Disables access to bootrom APIs from ARM-NS + * Unlocks all BOOT spinlocks + * Clears any secure code callbacks + * + * Note: the sdk calls this method on runtime initialisation to put the bootrom into a known state. This + * allows the program to function correctly if it is entered (e.g. from a debugger) without taking the usual boot path (which + * resets the state appropriately itself). + * + * \param flags flags, as detailed above + */ +static inline void rom_bootrom_state_reset(uint32_t flags) { + rom_bootrom_state_reset_fn func = (rom_bootrom_state_reset_fn) rom_func_lookup_inline(ROM_FUNC_BOOTROM_STATE_RESET); + return func(flags); +} + +/*! + * \brief Reset address translation + * \ingroup pico_bootrom + * + * Restore the QMI address translation registers, QMI_ATRANS0 through QMI_ATRANS7, to their reset state. This makes the + * runtime-to-storage address map an identity map, i.e. the mapped and unmapped address are equal, and the entire space is + * fully mapped. + */ +static inline void rom_flash_reset_address_trans(void) { + rom_flash_reset_address_trans_fn func = (rom_flash_reset_address_trans_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RESET_ADDRESS_TRANS); + func(); +} + +/*! + * \brief Configure QMI in a XIP read mode + * \ingroup pico_bootrom + * + * Configure QMI for one of a small menu of XIP read modes supported by the bootrom. This mode is configured for both memory + * windows (both chip selects), and the clock divisor is also applied to direct mode. + * + * \param mode bootrom_xip_mode_t mode to use + * \param clkdiv clock divider + */ +static inline void rom_flash_select_xip_read_mode(bootrom_xip_mode_t mode, uint8_t clkdiv) { + rom_flash_select_xip_read_mode_fn func = (rom_flash_select_xip_read_mode_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_SELECT_XIP_READ_MODE); + func(mode, clkdiv); +} + +/*! + * \brief Perform a flash read, erase, or program operation + * \ingroup pico_bootrom + * + * The flash operation is bounds-checked against the known flash devices specified by the runtime value of FLASH_DEVINFO, + * stored in bootram. This is initialised by the bootrom to the OTP value OTP_DATA_FLASH_DEVINFO, if + * OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set; otherwise it is initialised to 16 MiB for chip select 0 and 0 bytes + * for chip select 1. FLASH_DEVINFO can be updated at runtime by writing to its location in bootram, the pointer to which + * can be looked up in the ROM table. + * + * If a resident partition table is in effect, then the flash operation is also checked against the partition permissions. + * The Secure version of this function can specify the caller's effective security level (Secure, Non-secure, bootloader) + * using the CFLASH_SECLEVEL_BITS bitfield of the flags argument, whereas the Non-secure function is always checked against + * the Non-secure permissions for the partition. Flash operations which span two partitions are not allowed, and will fail + * address validation. + * + * If OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED is set, erase operations will use a D8h 64 kiB block erase command where + * possible (without erasing outside the specified region), for faster erase time. Otherwise, only 20h 4 kiB sector erase + * commands are used. + * + * Optionally, this API can translate addr from flash runtime addresses to flash storage addresses, according to the + * translation currently configured by QMI address translation registers, QMI_ATRANS0 through QMI_ATRANS7. For example, an + * image stored at a +2 MiB offset in flash (but mapped at XIP address 0 at runtime), writing to an offset of +1 MiB into + * the image, will write to a physical flash storage address of 3 MiB. Translation is enabled by setting the + * CFLASH_ASPACE_BITS bitfield in the flags argument. + * + * When translation is enabled, flash operations which cross address holes in the XIP runtime address space (created by + * non-maximum ATRANSx_SIZE) will return an error response. This check may tear: the transfer may be partially performed + * before encountering an address hole and ultimately returning failure. + * + * When translation is enabled, flash operations are permitted to cross chip select boundaries, provided this does not + * span an ATRANS address hole. When translation is disabled, the entire operation must target a single flash chip select + * (as determined by bits 24 and upward of the address), else address validation will fail. + * + * \param flags controls the security level, address space, and flash operation + * \param addr the address of the first flash byte to be accessed, ranging from XIP_BASE to XIP_BASE + 0x1ffffff + * \param size_bytes size of buf, in bytes + * \param buf contains data to be written to flash, for program operations, and data read back from flash, for read operations + */ +static inline int rom_flash_op(cflash_flags_t flags, uintptr_t addr, uint32_t size_bytes, uint8_t *buf) { + rom_flash_op_fn func = (rom_flash_op_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_OP); + if (!bootrom_try_acquire_lock(BOOTROM_LOCK_FLASH_OP)) + return BOOTROM_ERROR_LOCK_REQUIRED; + int rc = func(flags, addr, size_bytes, buf); + bootrom_release_lock(BOOTROM_LOCK_FLASH_OP); + return rc; } +/*! + * \brief Writes data from a buffer into OTP, or reads data from OTP into a buffer + * \ingroup pico_bootrom + * + * The buffer must be aligned to 2 bytes or 4 bytes according to the IS_ECC flag. + * + * This method will read and write rows until the first row it encounters that fails a key or permission check at which + * it will return BOOTROM_ERROR_NOT_PERMITTED. + * + * Writing will also stop at the first row where an attempt is made to set an OTP bit from a 1 to a 0, and + * BOOTROM_ERROR_UNSUPPORTED_MODIFICATION will be returned. + * + * If all rows are read/written successfully, then BOOTROM_OK will be returned. + * + * \param buf buffer to read to/write from + * \param buf_len size of buf + * \param cmd OTP command to execute + * - 0x0000ffff - ROW_NUMBER: 16 low bits are row number (0-4095) + * - 0x00010000 - IS_WRITE: if set, do a write (not a read) + * - 0x00020000 - IS_ECC: if this bit is set, each value in the buffer is 2 bytes and ECC is used when read/writing from 24 + * bit value in OTP. If this bit is not set, each value in the buffer is 4 bytes, the low 24-bits of which are written + * to or read from OTP. + + */ +static inline int rom_func_otp_access(uint8_t *buf, uint32_t buf_len, otp_cmd_t cmd) { + rom_func_otp_access_fn func = (rom_func_otp_access_fn) rom_func_lookup_inline(ROM_FUNC_OTP_ACCESS); + if (!bootrom_try_acquire_lock(BOOTROM_LOCK_OTP)) + return BOOTROM_ERROR_LOCK_REQUIRED; + int rc = func(buf, buf_len, cmd); + bootrom_release_lock(BOOTROM_LOCK_OTP); + return rc; +} + +/*! + * \brief Fills a buffer with information from the partition table + * \ingroup pico_bootrom + * + * Fills a buffer with information from the partition table. Note that this API is also used to return information over the + * picoboot interface. + * + * On success, the buffer is filled, and the number of words filled in the buffer is returned. If the partition table + * has not been loaded (e.g. from a watchdog or RAM boot), then this method will return BOOTROM_ERROR_NO_DATA, and you + * should load the partition table via load_partition_table() first. + * + * Note that not all data from the partition table is kept resident in memory by the bootrom due to size constraints. + * To protect against changes being made in flash after the bootrom has loaded the resident portion, the bootrom keeps + * a hash of the partition table as of the time it loaded it. If the hash has changed by the time this method is called, + * then it will return BOOTROM_ERROR_INVALID_STATE. + * + * The information returned is chosen by the flags_and_partition parameter; the first word in the returned buffer, + * is the (sub)set of those flags that the API supports. You should always check this value before interpreting + * the buffer. + * + * Following the first word, returns words of data for each present flag in order. With the exception of PT_INFO, + * all the flags select "per partition" information, so each field is returned in flag order for one partition after + * the next. The special SINGLE_PARTITION flag indicates that data for only a single partition is required. + * + * \param out_buffer buffer to write data to + * \param out_buffer_word_size size of out_buffer, in words + * \param partition_and_flags partition number and flags + */ +static inline int rom_get_partition_table_info(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t partition_and_flags) { + rom_get_partition_table_info_fn func = (rom_get_partition_table_info_fn) rom_func_lookup_inline(ROM_FUNC_GET_PARTITION_TABLE_INFO); + if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) + return BOOTROM_ERROR_LOCK_REQUIRED; + int rc = func(out_buffer, out_buffer_word_size, partition_and_flags); + bootrom_release_lock(BOOTROM_LOCK_SHA_256); + return rc; +} + +// todo SECURE only +/*! + * \brief Loads the current partition table from flash, if present + * \ingroup pico_bootrom + * + * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. + * As a result it requires a user provided memory buffer as a work area. The work area should byte word-aligned and of sufficient size + * or BOOTROM_ERROR_INSUFFICIENT_RESOURCES will be returned. The work area size currently required is 3064, so 3K is a good choice. + * + * If force_reload is false, then this method will return BOOTROM_OK immediately if the bootrom is loaded, otherwise it will + * reload the partition table if it has been loaded already, allowing for the partition table to be updated in a running program. + * + * \param workarea_base base address of work area + * \param workarea_size size of work area + * \param force_reload force reloading of the partition table + */ +static inline int rom_load_partition_table(uint8_t *workarea_base, uint32_t workarea_size, bool force_reload) { + rom_load_partition_table_fn func = (rom_load_partition_table_fn) rom_func_lookup_inline(ROM_FUNC_LOAD_PARTITION_TABLE); + if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) + return BOOTROM_ERROR_LOCK_REQUIRED; + int rc = func(workarea_base, workarea_size, force_reload); + bootrom_release_lock(BOOTROM_LOCK_SHA_256); + return rc; +} + +// todo SECURE only +/*! + * \brief Pick a partition from an A/B pair + * \ingroup pico_bootrom + * + * Determines which of the partitions has the "better" IMAGE_DEF. In the case of executable images, this is the one that would be booted + * + * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. + * As a result it requires a user provided memory buffer as a work area. The work area should bye word aligned, and of sufficient size + * or BOOTROM_ERROR_INSUFFICIENT_RESOURCES will be returned. The work area size currently required is 3064, so 3K is a good choice. + * + * The passed partition number can be any valid partition number other than the "B" partition of an A/B pair. + * + * This method returns a negative error code, or the partition number of the picked partition if (i.e. partition_a_num or the + * number of its "B" partition if any). + * + * NOTE: This method does not look at owner partitions, only the A partition passed and it's corresponding B partition. + * + * \param workarea_base base address of work area + * \param workarea_size size of work area + * \param partition_a_num the A partition of the pair + * \param flash_update_boot_window_base the flash update base, to pick that partition instead of the normally "better" partition + */ +static inline int rom_pick_ab_partition(uint8_t *workarea_base, uint32_t workarea_size, uint partition_a_num, uint32_t flash_update_boot_window_base) { + rom_pick_ab_partition_fn func = (rom_pick_ab_partition_fn) rom_func_lookup_inline(ROM_FUNC_PICK_AB_PARTITION); + if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) + return BOOTROM_ERROR_LOCK_REQUIRED; + int rc = func(workarea_base, workarea_size, partition_a_num, flash_update_boot_window_base); + bootrom_release_lock(BOOTROM_LOCK_SHA_256); + return rc; +} + +/*! + * \brief Get B partition + * \ingroup pico_bootrom + * + * Returns the index of the B partition of partition A if a partition table is present and loaded, and there is a partition A with a B partition; + * otherwise returns BOOTROM_ERROR_NOT_FOUND. + * + * \param pi_a the A partition number + */ +static inline int rom_get_b_partition(uint pi_a) { + rom_get_b_partition_fn func = (rom_get_b_partition_fn) rom_func_lookup_inline(ROM_FUNC_GET_B_PARTITION); + return func(pi_a); +} + +// todo SECURE only +/*! + * \brief Get UF2 Target Partition + * \ingroup pico_bootrom + * + * This method performs the same operation to decide on a target partition for a UF2 family ID as when a UF2 is dragged onto the USB + * drive in BOOTSEL mode. + * + * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. + * As a result it requires a user provided memory buffer as a work area. The work area should byte word-aligned and of sufficient size + * or `BOOTROM_ERROR_INSUFFICIENT_RESOURCES` will be returned. The work area size currently required is 3064, so 3K is a good choice. + * + * If the partition table + * has not been loaded (e.g. from a watchdog or RAM boot), then this method will return `BOOTROM_ERROR_PRECONDITION_NOT_MET`, and you + * should load the partition table via <> first. + * + * \param workarea_base base address of work area + * \param workarea_size size of work area + * \param family_id the family ID to place + * \param partition_out pointer to the resident_partition_t to fill with the partition data + */ +static inline int rom_get_uf2_target_partition(uint8_t *workarea_base, uint32_t workarea_size, uint32_t family_id, resident_partition_t *partition_out) { + rom_get_uf2_target_partition_fn func = (rom_get_uf2_target_partition_fn) rom_func_lookup_inline(ROM_FUNC_GET_UF2_TARGET_PARTITION); + if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) + return BOOTROM_ERROR_LOCK_REQUIRED; + int rc = func(workarea_base, workarea_size, family_id, partition_out); + bootrom_release_lock(BOOTROM_LOCK_SHA_256); + return rc; +} + +/*! + * \brief Translate runtime to storage address + * \ingroup pico_bootrom + * + * Applies the address translation currently configured by QMI address translation registers. + * + * Translating an address outside of the XIP runtime address window, or beyond the bounds of an ATRANSx_SIZE field, returns BOOTROM_ERROR_INVALID_ADDRESS, + * which is not a valid flash storage address. Otherwise, return the storage address which QMI would access when presented with the runtime address addr. + * This is effectively a virtual-to-physical address translation for QMI. + * + * \param flash_runtime_addr the address to translate + */ +static inline intptr_t rom_flash_runtime_to_storage_addr(uintptr_t flash_runtime_addr) { + rom_flash_runtime_to_storage_addr_fn func = (rom_flash_runtime_to_storage_addr_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR); + return func(flash_runtime_addr); +} + +// todo SECURE only +/*! + * \brief Chain into a launchable image + * \ingroup pico_bootrom + * + * Searches a memory region for a launchable image, and executes it if possible. + * + * The region_base and region_size specify a word-aligned, word-multiple-sized area of RAM, XIP RAM or flash to search. + * The first 4 kiB of the region must contain the start of a Block Loop with an IMAGE_DEF. If the new image is launched, + * the call does not return otherwise an error is returned. + * + * The region_base is signed, as a negative value can be passed, which indicates that the (negated back to positive value) + * is both the region_base and the base of the "flash update" region. + * + * This method potentially requires similar complexity to the boot path in terms of picking amongst versions, checking signatures etc. + * As a result it requires a user provided memory buffer as a work area. The work area should be word aligned, and of sufficient size + * or BOOTROM_ERROR_INSUFFICIENT_RESOURCES will be returned. The work area size currently required is 3064, so 3K is a good choice. + * + * NOTE: This method is primarily expected to be used when implementing bootloaders. + * + * NOTE: When chaining into an image, the OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED flag will not be set, to prevent invalidating a bootloader + * without a rollback version by booting a binary which has one. + * + * \param workarea_base base address of work area + * \param workarea_size size of work area + * \param region_base base address of image + * \param region_size size of window containing image + */ +static inline int rom_chain_image(uint8_t *workarea_base, uint32_t workarea_size, uint32_t region_base, uint32_t region_size) { + rom_chain_image_fn func = (rom_chain_image_fn) rom_func_lookup_inline(ROM_FUNC_CHAIN_IMAGE); + bootrom_release_lock(BOOTROM_LOCK_ENABLE); + int rc = func(workarea_base, workarea_size, region_base, region_size); + bootrom_acquire_lock_blocking(BOOTROM_LOCK_ENABLE); + return rc; +} + +// todo SECURE only +/*! + * \brief Buy an image + * \ingroup pico_bootrom + * + * Perform an "explicit" buy of an executable launched via an IMAGE_DEF which was "explicit buy" flagged. A "flash update" + * boot of such an image is a way to have the image execute once, but only become the "current" image if it calls + * back into the bootrom via this call. + * + * This call may perform the following: + * + * - Erase and rewrite the part of flash containing the "explicit buy" flag in order to clear said flag. + * - Erase the first sector of the other partition in an A/B partition scenario, if this new IMAGE_DEF is a version downgrade + * (so this image will boot again when not doing a "flash update" boot) + * - Update the rollback version in OTP if the chip is secure, and a rollback version is present in the image. + * + * NOTE: The device may reboot while updating the rollback version, if multiple rollback rows need to be written - this occurs + * when the version crosses a multiple of 24 (for example upgrading from version 23 to 25 requires a reboot, but 23 to 24 or 24 to 25 doesn't). + * The application should therefore be prepared to reboot when calling this function, if rollback versions are in use. + * + * Note that the first of the above requires 4 kiB of scratch space, so you should pass a word aligned buffer of at least 4 kiB to this method, + * or it will return BOOTROM_ERROR_INSUFFICIENT_RESOURCES if the "explicit buy" flag needs to be cleared. + * + * \param buffer base address of scratch space + * \param buffer_size size of scratch space + */ +static inline int rom_explicit_buy(uint8_t *buffer, uint32_t buffer_size) { + rom_explicit_buy_fn func = (rom_explicit_buy_fn) rom_func_lookup_inline(ROM_FUNC_EXPLICIT_BUY); + return func(buffer, buffer_size); +} + +#ifndef __riscv +/*! + * \brief Set NS API Permission + * \ingroup pico_bootrom + * + * Allow or disallow the specific NS API (note all NS APIs default to disabled). + * + * ns_api_num configures ARM-NS access to the given API. When an NS API is disabled, + * calling it will return BOOTROM_ERROR_NOT_PERMITTED. + * + * NOTE: All permissions default to disallowed after a reset. + * + * \param ns_api_num ns api number + * \param allowed permission + */ +static inline int rom_set_ns_api_permission(uint ns_api_num, bool allowed) { + rom_set_ns_api_permission_fn func = (rom_set_ns_api_permission_fn) rom_func_lookup_inline(ROM_FUNC_SET_NS_API_PERMISSION); + return func(ns_api_num, allowed); +} +#endif + +// todo SECURE only +/*! + * \brief Validate NS Buffer + * \ingroup pico_bootrom + * + * Utility method that can be used by secure ARM code to validate a buffer passed to it from Non-secure code. + * + * Both the write parameter and the (out) result parameter ok are RCP booleans, so 0xa500a500 for true, and 0x00c300c3 + * for false. This enables hardening of this function, and indeed the write parameter must be one of these values or the RCP + * will hang the system. + * + * For success, the entire buffer must fit in range XIP_BASE -> SRAM_END, and must be accessible by the Non-secure + * caller according to SAU + NS MPU (privileged or not based on current processor IPSR and NS CONTROL flag). Buffers + * in USB RAM are also allowed if access is granted to NS via ACCESSCTRL. + * + * \param addr buffer address + * \param size buffer size + * \param write rcp boolean, true if writeable + * \param ok rcp boolean result + */ +static inline void* rom_validate_ns_buffer(const void *addr, uint32_t size, uint32_t write, uint32_t *ok) { + rom_validate_ns_buffer_fn func = (rom_validate_ns_buffer_fn) rom_func_lookup_inline(ROM_FUNC_VALIDATE_NS_BUFFER); + return func(addr, size, write, ok); +} + +/*! + * \brief Set ROM callback function + * \ingroup pico_bootrom + * + * The only currently supported callback_number is 0 which sets the callback used for the secure_call API. + * + * A callback pointer of 0 deletes the callback function, a positive callback pointer (all valid function pointers are on RP2350) + * sets the callback function, but a negative callback pointer can be passed to get the old value without setting a new value. + * + * If successful, returns >=0 (the existing value of the function pointer on entry to the function). + * + * \param callback_num the callback number to set - only 0 is supported on RP2350 + * \param funcptr pointer to the callback function + */ +static inline intptr_t rom_set_rom_callback(uint callback_num, bootrom_api_callback_generic_t funcptr) { + rom_set_rom_callback_fn func = (rom_set_rom_callback_fn) rom_func_lookup_inline(ROM_FUNC_SET_ROM_CALLBACK); + return func(callback_num, funcptr); +} + +#define BOOT_TYPE_NORMAL 0 +#define BOOT_TYPE_BOOTSEL 2 +#define BOOT_TYPE_RAM_IMAGE 3 +#define BOOT_TYPE_FLASH_UPDATE 4 + +// values 8-15 are secure only +#define BOOT_TYPE_PC_SP 0xd + +// ORed in if a bootloader chained into the image +#define BOOT_TYPE_CHAINED_FLAG 0x80 + +/*! + * \brief Get system information + * \ingroup pico_bootrom + * + * Fills a buffer with various system information. Note that this API is also used to return information over the picoboot interface. + * + * On success, the buffer is filled, and the number of words filled in the buffer is returned. + * + * The information returned is chosen by the flags parameter; the first word in the returned buffer, + * is the (sub)set of those flags that the API supports. You should always check this value before interpreting + * the buffer. + * + * "Boot Diagnostic" information is intended to help identify the cause of a failed boot, or booting into an unexpected binary. + * This information can be retrieved via picoboot after a watchdog reboot, however it will not survive + * a reset via the RUN pin or POWMAN reset. + * + * There is only one word of diagnostic information. What it records is based on the pp selection above, which + * is itself set as a parameter when rebooting programmatically into a normal boot. + * + * To get diagnostic info, pp must refer to a slot or an "A" partition; image diagnostics are automatically selected on boot + * from OTP or RAM image, or when chain_image() is called.) + * + * The diagnostic word thus contains data for either slot 0 and slot 1, or the "A" partition (and its "B" partition if it has one). The low half word + * of the diagnostic word contains information from slot 0 or partition A; the high half word contains information from slot 1 or partition B. + * + * To get a full picture of a failed boot involving slots and multiple partitions, the device can be rebooted + * multiple times to gather the information. + * + * \param out_buffer buffer to write data to + * \param out_buffer_word_size size of out_buffer, in words + * \param flags flags + */ +static inline int rom_get_sys_info(uint32_t *out_buffer, uint32_t out_buffer_word_size, uint32_t flags) { + rom_get_sys_info_fn func = (rom_get_sys_info_fn)rom_func_lookup_inline(ROM_FUNC_GET_SYS_INFO); + return func(out_buffer, out_buffer_word_size, flags); +} + +typedef struct { + union { + struct __packed { + int8_t diagnostic_partition_index; // used BOOT_PARTITION constants + uint8_t boot_type; + int8_t partition; + uint8_t tbyb_and_update_info; + }; + uint32_t boot_word; + }; + uint32_t boot_diagnostic; + uint32_t reboot_params[2]; +} boot_info_t; + +static inline int rom_get_boot_info(boot_info_t *info) { + uint32_t result[5]; + int words_returned = rom_get_sys_info(result, 5, SYS_INFO_BOOT_INFO); + if (words_returned == (sizeof(result)/sizeof(result[0])) && result[0] == SYS_INFO_BOOT_INFO) { + memcpy(info, &result[1], sizeof(boot_info_t)); + return true; + } else { + return false; + } +} + +static inline int rom_get_last_boot_type_with_chained_flag(void) { + uint32_t result[5]; + int words_returned = rom_get_sys_info(result, 5, SYS_INFO_BOOT_INFO); + if (words_returned == count_of(result) && result[0] == SYS_INFO_BOOT_INFO) { + // todo use struct + return (int)((result[1] & 0xff00u) >> 8); + } else { + return PICO_ERROR_INVALID_DATA; + } +} + +// BOOT_TYPE_NORMAL 0x0 +// BOOT_TYPE_BOOTSEL 0x2 +// BOOT_TYPE_RAM_IMAGE 0x3 +// BOOT_TYPE_FLASH_UPDATE 0x4 +// BOOT_TYPE_PC_SP 0xd +static inline int rom_get_last_boot_type(void) { + int rc = rom_get_last_boot_type_with_chained_flag(); + if (rc >= 0) rc &= ~BOOT_TYPE_CHAINED_FLAG; + return rc; +} + +/*! \brief Add a runtime partition to the partition table to specify flash permissions + * \ingroup pico_bootrom + * + * Note that a partition is added to the runtime view of the partition table maintained by the bootrom if there is space to do so + * + * Note that these permissions cannot override the permissions for any pre-existing partitions, as permission matches are made on a first partition found basis. + * + * @param start_offset the start_offset into flash in bytes (must be a multiple of 4K) + * @param size the size in byte (must be a multiple of 4K) + * @param permissions the bitwise OR of permissions from PICOBIN_PARTITION_PERMISSION_ constants, e.g. \ref PICOBIN_PARTITION_PERMISSION_S_R_BITS from boot/picobin.h + * @return >= 0 the partition number added if + * PICO_ERROR_BAD_ALIGNMENT if the start_offset or size aren't multiples of 4K. + * PICO_ERROR_INVALID_ARG if the start_offset or size are out of range, or invalid permission bits are set. + */ +int rom_add_flash_runtime_partition(uint32_t start_offset, uint32_t size, uint32_t permissions); + +#endif + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/pico_bootrom/include/pico/bootrom/lock.h b/src/rp2_common/pico_bootrom/include/pico/bootrom/lock.h new file mode 100644 index 000000000..f436557fa --- /dev/null +++ b/src/rp2_common/pico_bootrom/include/pico/bootrom/lock.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BOOTROM_LOCK_H +#define _PICO_BOOTROM_LOCK_H + +#include "hardware/boot_lock.h" +#include "pico/bootrom_constants.h" + +// PICO_CONFIG: PICO_BOOTROM_LOCKING_ENABLED, Enable/disable locking for bootrom functions that use shared reqsources. If this flag is enabled bootrom lock checking is turned on and BOOT locks are taken around the relevant bootrom functions, type=bool, default=1, group=pico_bootrom +#ifndef PICO_BOOTROM_LOCKING_ENABLED +#if NUM_BOOT_LOCKS > 0 +#define PICO_BOOTROM_LOCKING_ENABLED 1 +#endif +#endif + +/** + * \brief Try to acquire a bootrom lock + * + * If PICO_BOOTROM_LOCKING_ENABLED is false, this method returns true immediately + * + * \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP + * \return true if the lock was acquired + */ +static inline bool bootrom_try_acquire_lock(uint lock_num) { +#if PICO_BOOTROM_LOCKING_ENABLED + // unsafe as this is a long term lock (so no irq disable) + return boot_try_lock_unsafe(boot_lock_instance(lock_num)); +#else + (void)lock_num; + return true; +#endif +} + +/** + * \brief Acquire a bootrom lock. If the lock is unavailable, block until it is available + * + * If PICO_BOOTROM_LOCKING_ENABLED is false, this method does nothing + * + * \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP + */ +static inline void bootrom_acquire_lock_blocking(uint lock_num) { +#if PICO_BOOTROM_LOCKING_ENABLED + // unsafe as this is a long term lock (so no irq disable) + boot_lock_unsafe_blocking(boot_lock_instance(lock_num)); +#else + (void)lock_num; +#endif +} + +/** + * \brief Release a bootrom lock + * + * If PICO_BOOTROM_LOCKING_ENABLED is false, this method does nothing + * + * \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP + */ +static inline void bootrom_release_lock(uint lock_num) { +#if PICO_BOOTROM_LOCKING_ENABLED + boot_unlock_unsafe(boot_lock_instance(lock_num)); +#else + (void)lock_num; +#endif +} + +#endif diff --git a/src/rp2_common/pico_bootrom/include/pico/bootrom_constants.h b/src/rp2_common/pico_bootrom/include/pico/bootrom_constants.h new file mode 100644 index 000000000..924487f8c --- /dev/null +++ b/src/rp2_common/pico_bootrom/include/pico/bootrom_constants.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BOOTROM_CONSTANTS_H +#define _PICO_BOOTROM_CONSTANTS_H + +#ifndef NO_PICO_PLATFORM +#include "pico/platform.h" +#endif + +// ROOT ADDRESSES +#define BOOTROM_MAGIC_OFFSET 0x10 +#define BOOTROM_FUNC_TABLE_OFFSET 0x14 +#if PICO_RP2040 +#define BOOTROM_DATA_TABLE_OFFSET 0x16 +#endif + +#if PICO_RP2040 +#define BOOTROM_VTABLE_OFFSET 0x00 +#define BOOTROM_TABLE_LOOKUP_OFFSET 0x18 +#else +// todo remove this (or #ifdef it for A1/A2) +#define BOOTROM_IS_A2() ((*(volatile uint8_t *)0x13) == 2) +#define BOOTROM_WELL_KNOWN_PTR_SIZE (BOOTROM_IS_A2() ? 2 : 4) +#if defined(__riscv) +#define BOOTROM_ENTRY_OFFSET 0x7dfc +#define BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE) +#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE*2) +#else +#define BOOTROM_VTABLE_OFFSET 0x00 +#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE) +#endif +#endif + +#if !PICO_RP2040 || PICO_COMBINED_DOCS + +#define BOOTROM_OK 0 +//#define BOOTROM_ERROR_TIMEOUT (-1) +//#define BOOTROM_ERROR_GENERIC (-2) +//#define BOOTROM_ERROR_NO_DATA (-3) // E.g. read from an empty buffer/FIFO +#define BOOTROM_ERROR_NOT_PERMITTED (-4) // Permission violation e.g. write to read-only flash partition +#define BOOTROM_ERROR_INVALID_ARG (-5) // Argument is outside of range of supported values` +//#define BOOTROM_ERROR_IO (-6) +//#define BOOTROM_ERROR_BADAUTH (-7) +//#define BOOTROM_ERROR_CONNECT_FAILED (-8) +//#define BOOTROM_ERROR_INSUFFICIENT_RESOURCES (-9) // Dynamic allocation of resources failed +#define BOOTROM_ERROR_INVALID_ADDRESS (-10) // Address argument was out-of-bounds or was determined to be an address that the caller may not access +#define BOOTROM_ERROR_BAD_ALIGNMENT (-11) // Address modulo transfer chunk size was nonzero (e.g. word-aligned transfer with address % 4 != 0) +#define BOOTROM_ERROR_INVALID_STATE (-12) // Something happened or failed to happen in the past, and consequently we (currently) can't service the request +#define BOOTROM_ERROR_BUFFER_TOO_SMALL (-13) // A user-allocated buffer was too small to hold the result or working state of this function +#define BOOTROM_ERROR_PRECONDITION_NOT_MET (-14) // This call failed because another ROM function must be called first +#define BOOTROM_ERROR_MODIFIED_DATA (-15) // Cached data was determined to be inconsistent with the full version of the data it was calculated from +#define BOOTROM_ERROR_INVALID_DATA (-16) // A data structure failed to validate +#define BOOTROM_ERROR_NOT_FOUND (-17) // Attempted to access something that does not exist; or, a search failed +#define BOOTROM_ERROR_UNSUPPORTED_MODIFICATION (-18) // Write is impossible based on previous writes; e.g. attempted to clear an OTP bit +#define BOOTROM_ERROR_LOCK_REQUIRED (-19) // A required lock is not owned +#define BOOTROM_ERROR_LAST (-19) + +#define RT_FLAG_FUNC_RISCV 0x0001 +#define RT_FLAG_FUNC_RISCV_FAR 0x0003 +#define RT_FLAG_FUNC_ARM_SEC 0x0004 +// reserved for 32-bit pointer: 0x0008 +#define RT_FLAG_FUNC_ARM_NONSEC 0x0010 +// reserved for 32-bit pointer: 0x0020 +#define RT_FLAG_DATA 0x0040 +// reserved for 32-bit pointer: 0x0080 + +#define PARTITION_TABLE_MAX_PARTITIONS 16 +// note this is deliberately > MAX_PARTITIONs is likely to be, and also -1 as a signed byte +#define PARTITION_TABLE_NO_PARTITION_INDEX 0xff + +// todo these are duplicated in picoboot_constants.h +// values 0-7 are secure/non-secure +#define BOOT_TYPE_NORMAL 0 +#define BOOT_TYPE_BOOTSEL 2 +#define BOOT_TYPE_RAM_IMAGE 3 +#define BOOT_TYPE_FLASH_UPDATE 4 + +// values 8-15 are secure only +#define BOOT_TYPE_PC_SP 0xd + +// ORed in if a bootloader chained into the image +#define BOOT_TYPE_CHAINED_FLAG 0x80 + +// call from NS to S +#ifndef __riscv +#define BOOTROM_API_CALLBACK_secure_call 0 +#endif +#define BOOTROM_API_CALLBACK_COUNT 1 + +#define BOOTROM_LOCK_SHA_256 0 +#define BOOTROM_LOCK_FLASH_OP 1 +#define BOOTROM_LOCK_OTP 2 +#define BOOTROM_LOCK_MAX 2 + +#define BOOTROM_LOCK_ENABLE 7 + +#define BOOT_PARTITION_NONE (-1) +#define BOOT_PARTITION_SLOT0 (-2) +#define BOOT_PARTITION_SLOT1 (-3) +#define BOOT_PARTITION_WINDOW (-4) + +#define BOOT_DIAGNOSTIC_WINDOW_SEARCHED 0x01 +// note if both BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP and BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP then the block loop was valid +// but it has a PARTITION_TABLE which while it passed the initial verification (and hash/sig) had invalid contents +// (discovered when it was later loaded) +#define BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP 0x02 +#define BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP 0x04 +#define BOOT_DIAGNOSTIC_VALID_IMAGE_DEF 0x08 +#define BOOT_DIAGNOSTIC_HAS_PARTITION_TABLE 0x10 +#define BOOT_DIAGNOSTIC_CONSIDERED 0x20 +#define BOOT_DIAGNOSTIC_CHOSEN 0x40 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_LSB 7 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_MATCHING_KEY_FOR_VERIFY 0x80 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_HASH_FOR_VERIFY 0x100 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_VERIFIED_OK 0x200 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_LSB 10 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_MATCHING_KEY_FOR_VERIFY 0x400 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_HASH_FOR_VERIFY 0x800 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_VERIFIED_OK 0x1000 + +#define BOOT_DIAGNOSTIC_LOAD_MAP_ENTRIES_LOADED 0x2000 +#define BOOT_DIAGNOSTIC_IMAGE_LAUNCHED 0x4000 +#define BOOT_DIAGNOSTIC_IMAGE_CONDITION_FAILURE 0x8000 + +#define BOOT_PARSED_BLOCK_DIAGNOSTIC_MATCHING_KEY_FOR_VERIFY 0x1 // if this is present and VERIFIED_OK isn't the sig check failed +#define BOOT_PARSED_BLOCK_DIAGNOSTIC_HASH_FOR_VERIFY 0x2 // if this is present and VERIFIED_OL isn't then hash check failed +#define BOOT_PARSED_BLOCK_DIAGNOSTIC_VERIFIED_OK 0x4 + +#define BOOT_TBYB_AND_UPDATE_FLAG_BUY_PENDING 0x1 +#define BOOT_TBYB_AND_UPDATE_FLAG_OTP_VERSION_APPLIED 0x2 +#define BOOT_TBYB_AND_UPDATE_FLAG_OTHER_ERASED 0x4 + +#ifndef __ASSEMBLER__ +// Limited to 3 arguments in case of varm multiplex hint (trashes Arm r3) +typedef int (*bootrom_api_callback_generic_t)(uint32_t r0, uint32_t r1, uint32_t r2); +// Return negative for error, else number of bytes transferred: +//typedef int (*bootrom_api_callback_stdout_put_blocking_t)(const uint8_t *buffer, uint32_t size); +//typedef int (*bootrom_api_callback_stdin_get_t)(uint8_t *buffer, uint32_t size); +//typedef void (*bootrom_api_callback_core1_security_setup_t)(void); +#endif + +#endif + +/*! \brief Return a bootrom lookup code based on two ASCII characters + * \ingroup pico_bootrom + * + * These codes are uses to lookup data or function addresses in the bootrom + * + * \param c1 the first character + * \param c2 the second character + * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() + */ +#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) + +// ROM FUNCTIONS + +// RP2040 & RP2350 +#define ROM_DATA_SOFTWARE_GIT_REVISION ROM_TABLE_CODE('G', 'R') +#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') +#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') +#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') +#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') +#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') +#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') + + +#if PICO_RP2040 +// RP2040 only +#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4') +#define ROM_DATA_COPYRIGHT ROM_TABLE_CODE('C', 'R') +#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3') +#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C') +#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S') +#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3') +#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3') +#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4') +#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3') +#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B') +#endif + +#if !PICO_RP2040 || PICO_COMBINED_DOCS +// RP2350 only +#define ROM_FUNC_PICK_AB_PARTITION ROM_TABLE_CODE('A', 'B') +#define ROM_FUNC_CHAIN_IMAGE ROM_TABLE_CODE('C', 'I') +#define ROM_FUNC_EXPLICIT_BUY ROM_TABLE_CODE('E', 'B') +#define ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR ROM_TABLE_CODE('F', 'A') +#define ROM_DATA_FLASH_DEVINFO16_PTR ROM_TABLE_CODE('F', 'D') +#define ROM_FUNC_FLASH_OP ROM_TABLE_CODE('F', 'O') +#define ROM_FUNC_GET_B_PARTITION ROM_TABLE_CODE('G', 'B') +#define ROM_FUNC_GET_PARTITION_TABLE_INFO ROM_TABLE_CODE('G', 'P') +#define ROM_FUNC_GET_SYS_INFO ROM_TABLE_CODE('G', 'S') +#define ROM_FUNC_GET_UF2_TARGET_PARTITION ROM_TABLE_CODE('G', 'U') +#define ROM_FUNC_LOAD_PARTITION_TABLE ROM_TABLE_CODE('L', 'P') +#define ROM_FUNC_OTP_ACCESS ROM_TABLE_CODE('O', 'A') +#define ROM_DATA_PARTITION_TABLE_PTR ROM_TABLE_CODE('P', 'T') +#define ROM_FUNC_FLASH_RESET_ADDRESS_TRANS ROM_TABLE_CODE('R', 'A') +#define ROM_FUNC_REBOOT ROM_TABLE_CODE('R', 'B') +#define ROM_FUNC_SET_ROM_CALLBACK ROM_TABLE_CODE('R', 'C') +#define ROM_FUNC_SECURE_CALL ROM_TABLE_CODE('S', 'C') +#define ROM_FUNC_SET_NS_API_PERMISSION ROM_TABLE_CODE('S', 'P') +#define ROM_FUNC_BOOTROM_STATE_RESET ROM_TABLE_CODE('S', 'R') +#define ROM_FUNC_SET_BOOTROM_STACK ROM_TABLE_CODE('S', 'S') +#define ROM_DATA_SAVED_XIP_SETUP_FUNC_PTR ROM_TABLE_CODE('X', 'F') +#define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE ROM_TABLE_CODE('X', 'M') +#define ROM_FUNC_VALIDATE_NS_BUFFER ROM_TABLE_CODE('V', 'B') +#endif + +// these form a bit set +#define BOOTROM_STATE_RESET_CURRENT_CORE 0x01 +#define BOOTROM_STATE_RESET_OTHER_CORE 0x02 +#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 // reset any global state (e.g. permissions) + +// partition level stuff is returned first (note PT_INFO flags is only 16 bits) + +// 3 words: pt_count, unpartitioned_perm_loc, unpartioned_perm_flags +#define PT_INFO_PT_INFO 0x0001 +#define PT_INFO_SINGLE_PARTITION 0x8000 // marker to just include a single partition in the results) + +// then in order per partition selected + +// 2 words: unpartitioned_perm_loc, unpartioned_perm_flags +#define PT_INFO_PARTITION_LOCATION_AND_FLAGS 0x0010 +// 2 words: id lsb first +#define PT_INFO_PARTITION_ID 0x0020 +// n+1 words: n, family_id... +#define PT_INFO_PARTITION_FAMILY_IDS 0x0040 +// (n+3)/4 words... bytes are: n (len), c0, c1, ... cn-1 padded to word boundary with zeroes +#define PT_INFO_PARTITION_NAME 0x0080 + +// items are returned in order +// 3 words package_id, device_id, wafer_id +#define SYS_INFO_CHIP_INFO 0x0001 +// 1 word: chip specific critical bits +#define SYS_INFO_CRITICAL 0x0002 +// 1 word: bytes: cpu_type, supported_cpu_type_bitfield +#define SYS_INFO_CPU_INFO 0x0004 +// 1 word: same as FLASH_DEVINFO row in OTP +#define SYS_INFO_FLASH_DEV_INFO 0x0008 +// 4 words +#define SYS_INFO_BOOT_RANDOM 0x0010 +// 2 words lsb first +#define SYS_INFO_NONCE 0x0020 +// 4 words boot_info, boot_diagnostic, boot_param0, boot_param1 +#define SYS_INFO_BOOT_INFO 0x0040 + +#define BOOTROM_NS_API_get_sys_info 0 +#define BOOTROM_NS_API_checked_flash_op 1 +#define BOOTROM_NS_API_flash_runtime_to_storage_addr 2 +#define BOOTROM_NS_API_get_partition_table_info 3 +#define BOOTROM_NS_API_secure_call 4 +#define BOOTROM_NS_API_otp_access 5 +#define BOOTROM_NS_API_reboot 6 +#define BOOTROM_NS_API_get_b_partition 7 +#define BOOTROM_NS_API_COUNT 8 + +#ifndef __ASSEMBLER__ + +typedef struct { + uint32_t permissions_and_location; + uint32_t permissions_and_flags; +} resident_partition_t; +static_assert(sizeof(resident_partition_t) == 8, ""); + +#define OTP_CMD_ROW_BITS 0x0000ffffu +#define OTP_CMD_ROW_LSB 0u +#define OTP_CMD_WRITE_BITS 0x00010000u +#define OTP_CMD_ECC_BITS 0x00020000u + +typedef struct otp_cmd { + uint32_t flags; +} otp_cmd_t; + +typedef enum { + BOOTROM_XIP_MODE_03H_SERIAL = 0, + BOOTROM_XIP_MODE_0BH_SERIAL, + BOOTROM_XIP_MODE_BBH_DUAL, + BOOTROM_XIP_MODE_EBH_QUAD, + BOOTROM_XIP_MODE_N_MODES +} bootrom_xip_mode_t; + +// The checked flash API wraps the low-level flash routines from generic_flash, adding bounds +// checking, permission checking against the resident partition table, and simple address +// translation. The low-level API deals with flash offsets (i.e. distance from the start of the +// first flash device, measured in bytes) but the checked flash API accepts one of two types of +// address: +// +// - Flash runtime addresses: the address of some flash-resident data or code in the currently +// running image. The flash addresses your binary is "linked at" by the linker. +// - Flash storage addresses: a flash offset, plus the address base where QSPI hardware is first +// mapped on the system bus (XIP_BASE constant from addressmap.h) +// +// These addresses are one and the same *if* the currently running program is stored at the +// beginning of flash. They are different if the start of your image has been "rolled" by the flash +// boot path to make it appear at the address it was linked at even though it is stored at a +// different location in flash, which is necessary when you have A/B images for example. +// +// The address translation between flash runtime and flash storage addresses is configured in +// hardware by the QMI_ATRANSx registers, and this API assumes those registers contain a valid +// address mapping which it can use to translate runtime to storage addresses. + +typedef struct cflash_flags { + uint32_t flags; +} cflash_flags_t; + +// Bits which are permitted to be set in a flags variable -- any other bits being set is an error +#define CFLASH_FLAGS_BITS 0x00070301u + +// Used to tell checked flash API which space a given address belongs to +#define CFLASH_ASPACE_BITS 0x00000001u +#define CFLASH_ASPACE_LSB 0u +#define CFLASH_ASPACE_VALUE_STORAGE 0u +#define CFLASH_ASPACE_VALUE_RUNTIME 1u + +// Used to tell checked flash APIs the effective security level of a flash access (may be forced to +// one of these values for the NonSecure-exported version of this API) +#define CFLASH_SECLEVEL_BITS 0x00000300u +#define CFLASH_SECLEVEL_LSB 8u +// Zero is not a valid security level: +#define CFLASH_SECLEVEL_VALUE_SECURE 1u +#define CFLASH_SECLEVEL_VALUE_NONSECURE 2u +#define CFLASH_SECLEVEL_VALUE_BOOTLOADER 3u + +#define CFLASH_OP_BITS 0x00070000u +#define CFLASH_OP_LSB 16u +// Erase size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a +// multiple of 4096 bytes (one flash sector). +#define CFLASH_OP_VALUE_ERASE 0u +// Program size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a +// multiple of 256 bytes (one flash page). +#define CFLASH_OP_VALUE_PROGRAM 1u +// Read size_bytes bytes of flash, starting at address addr. There are no alignment restrictions on +// addr or size_bytes. +#define CFLASH_OP_VALUE_READ 2u +#define CFLASH_OP_MAX 2u + +#endif + +#endif diff --git a/src/rp2_common/pico_bootsel_via_double_reset/BUILD.bazel b/src/rp2_common/pico_bootsel_via_double_reset/BUILD.bazel index 49cbf7ac1..90d65ada1 100644 --- a/src/rp2_common/pico_bootsel_via_double_reset/BUILD.bazel +++ b/src/rp2_common/pico_bootsel_via_double_reset/BUILD.bazel @@ -7,9 +7,9 @@ cc_library( srcs = ["pico_bootsel_via_double_reset.c"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", "//src/common/pico_binary_info", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_bootrom", ], ) diff --git a/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c b/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c index 3febe3137..ae86c5bed 100644 --- a/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c +++ b/src/rp2_common/pico_bootsel_via_double_reset/pico_bootsel_via_double_reset.c @@ -5,6 +5,10 @@ */ #include "pico.h" + +// Doesn't make any sense for a RAM only binary +#if !PICO_NO_FLASH + #include "pico/time.h" #include "pico/bootrom.h" #include "pico/binary_info.h" @@ -22,6 +26,8 @@ #endif /** \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset + * + * \brief Optional support to make fast double reset of the system enter BOOTSEL mode * * \brief When the 'pico_bootsel_via_double_reset' library is linked, a function is * injected before main() which will detect when the system has been reset @@ -35,8 +41,6 @@ bi_decl(bi_program_feature("double reset -> BOOTSEL")); #endif -// Doesn't make any sense for a RAM only binary -#if !PICO_NO_FLASH static const uint32_t magic_token[] = { 0xf01681de, 0xbd729b29, 0xd359be7a, }; diff --git a/src/rp2_common/pico_btstack/BUILD.bazel b/src/rp2_common/pico_btstack/BUILD.bazel index 6ae04aecb..0f843b47f 100644 --- a/src/rp2_common/pico_btstack/BUILD.bazel +++ b/src/rp2_common/pico_btstack/BUILD.bazel @@ -42,7 +42,7 @@ cc_library( target_compatible_with = compatible_with_pico_w(), deps = [ ":pico_btstack_base", - "//src/common/pico_base", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_flash", ], ) @@ -67,7 +67,7 @@ cc_library( "//bazel/constraint:pico_btstack_config_unset", ) + compatible_with_pico_w(), deps = [ - "//src/common/pico_base", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_stdio", ], ) diff --git a/src/rp2_common/pico_btstack/CMakeLists.txt b/src/rp2_common/pico_btstack/CMakeLists.txt index f2055ab5b..6a821442a 100644 --- a/src/rp2_common/pico_btstack/CMakeLists.txt +++ b/src/rp2_common/pico_btstack/CMakeLists.txt @@ -20,7 +20,7 @@ if (EXISTS ${PICO_BTSTACK_PATH}/${BTSTACK_TEST_PATH}) pico_register_common_scope_var(PICO_BTSTACK_PATH) pico_add_library(pico_btstack_base NOFLAG) - target_include_directories(pico_btstack_base_headers INTERFACE + target_include_directories(pico_btstack_base_headers SYSTEM INTERFACE ${PICO_BTSTACK_PATH}/src ${PICO_BTSTACK_PATH}/platform/embedded ) @@ -62,7 +62,7 @@ if (EXISTS ${PICO_BTSTACK_PATH}/${BTSTACK_TEST_PATH}) ${PICO_BTSTACK_PATH}/3rd-party/yxml/yxml.c ${CMAKE_CURRENT_LIST_DIR}/btstack_stdin_pico.c ) - target_include_directories(pico_btstack_base_headers INTERFACE + target_include_directories(pico_btstack_base_headers SYSTEM INTERFACE ${PICO_BTSTACK_PATH}/ ${PICO_BTSTACK_PATH}/3rd-party/md5 ${PICO_BTSTACK_PATH}/3rd-party/yxml @@ -161,14 +161,14 @@ if (EXISTS ${PICO_BTSTACK_PATH}/${BTSTACK_TEST_PATH}) target_sources(pico_btstack_flash_bank INTERFACE ${CMAKE_CURRENT_LIST_DIR}/btstack_flash_bank.c ) - target_include_directories(pico_btstack_flash_bank_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_btstack_flash_bank_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_btstack_flash_bank INTERFACE pico_btstack_base pico_flash) pico_add_library(pico_btstack_run_loop_async_context NOFLAG) target_sources(pico_btstack_run_loop_async_context INTERFACE ${CMAKE_CURRENT_LIST_DIR}/btstack_run_loop_async_context.c ) - target_include_directories(pico_btstack_run_loop_async_context_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_btstack_run_loop_async_context_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_btstack_run_loop_async_context INTERFACE pico_btstack_base pico_async_context_base) pico_add_library(pico_btstack_sbc_common NOFLAG) @@ -223,12 +223,12 @@ if (EXISTS ${PICO_BTSTACK_PATH}/${BTSTACK_TEST_PATH}) ${PICO_BTSTACK_PATH}/src/classic/bnep.c ${PICO_BTSTACK_PATH}/platform/lwip/bnep_lwip.c ) - target_include_directories(pico_btstack_bnep_lwip_headers INTERFACE + target_include_directories(pico_btstack_bnep_lwip_headers SYSTEM INTERFACE ${PICO_BTSTACK_PATH}/platform/lwip ) pico_add_library(pico_btstack_bnep_lwip_sys_freertos NOFLAG) - target_include_directories(pico_btstack_bnep_lwip_sys_freertos INTERFACE + target_include_directories(pico_btstack_bnep_lwip_sys_freertos SYSTEM INTERFACE ${PICO_BTSTACK_PATH}/platform/freertos ) pico_mirrored_target_link_libraries(pico_btstack_bnep_lwip_sys_freertos INTERFACE diff --git a/src/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h b/src/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h index d275221a0..6d914f00e 100644 --- a/src/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h +++ b/src/rp2_common/pico_btstack/include/pico/btstack_flash_bank.h @@ -8,6 +8,7 @@ #define _PICO_BTSTACK_FLASH_BANK_H #include "pico.h" +#include "hardware/flash.h" #include "hal_flash_bank.h" #ifdef __cplusplus diff --git a/src/rp2_common/pico_clib_interface/BUILD.bazel b/src/rp2_common/pico_clib_interface/BUILD.bazel new file mode 100644 index 000000000..9bb05a99c --- /dev/null +++ b/src/rp2_common/pico_clib_interface/BUILD.bazel @@ -0,0 +1,121 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +# This is split between the headers and a link-time requirement to fix issues +# with circular dependencies introduced by the implementations. +alias( + name = "pico_clib_interface", + actual = select({ + "//bazel/constraint:pico_clib_llvm_libc_enabled": ":llvm_libc_interface", + "//bazel/constraint:pico_clib_newlib_enabled": ":newlib_interface", + "//bazel/constraint:pico_clib_picolibc_enabled": ":picolibc_interface", + "//conditions:default": ":pico_clib_interface_auto", + }), +) + +alias( + name = "pico_clib_interface_link", + actual = select({ + "//bazel/constraint:pico_clib_llvm_libc_enabled": ":llvm_libc_interface_link", + "//bazel/constraint:pico_clib_newlib_enabled": ":newlib_interface_link", + "//bazel/constraint:pico_clib_picolibc_enabled": ":picolibc_interface_link", + "//conditions:default": ":pico_clib_interface_auto_link", + }), +) + +# TODO: Provide a way to hook up Arm Compiler for Embedded into the automagic +# flow. +alias( + name = "pico_clib_interface_auto", + actual = select({ + "//bazel/constraint:pico_toolchain_clang_enabled": ":llvm_libc_interface", + "//conditions:default": ":newlib_interface", + }), +) + +alias( + name = "pico_clib_interface_auto_link", + actual = select({ + "//bazel/constraint:pico_toolchain_clang_enabled": ":llvm_libc_interface_link", + "//conditions:default": ":newlib_interface_link", + }), +) + +cc_library( + name = "llvm_libc_interface", + hdrs = [ + "include/llvm_libc/sys/cdefs.h", + "include/llvm_libc/sys/stat.h", + "include/llvm_libc/sys/time.h", + "include/llvm_libc/sys/times.h", + "include/llvm_libc/sys/types.h", + "include/llvm_libc/time.h", + "include/llvm_libc/unistd.h", + ], + includes = ["include/llvm_libc"], + # It's hard to properly constrain compatibility since `auto` may select this, + # so just tag as manual. + tags = ["manual"], + target_compatible_with = compatible_with_rp2(), +) + +cc_library( + name = "llvm_libc_interface_link", + srcs = ["llvm_libc_interface.c"], + implementation_deps = [ + ":llvm_libc_interface", + "//src/rp2_common/pico_atomic", + "//src/rp2_common/pico_bootrom", + "//src/rp2_common/pico_runtime_init", + "//src/rp2_common/pico_stdio:pico_stdio_headers", + ], + # It's hard to properly constrain compatibility since `auto` may select this, + # so just tag as manual. + tags = ["manual"], + target_compatible_with = compatible_with_rp2(), +) + +# For now, newlib doesn't need to provide any headers. +alias( + name = "newlib_interface", + actual = "//bazel:empty_cc_lib", +) + +cc_library( + name = "newlib_interface_link", + srcs = ["newlib_interface.c"], + implementation_deps = [ + "//src/common/pico_time", + "//src/rp2_common/pico_bootrom", + "//src/rp2_common/pico_printf", + "//src/rp2_common/pico_runtime_init", + "//src/rp2_common/pico_stdio:pico_stdio_headers", + ], + # It's hard to properly constrain compatibility since `auto` may select this, + # so just tag as manual. + tags = ["manual"], + target_compatible_with = compatible_with_rp2(), +) + +# For now, picolibc doesn't need to provide any headers. +alias( + name = "picolibc_interface", + actual = "//bazel:empty_cc_lib", +) + +cc_library( + name = "picolibc_interface_link", + srcs = ["picolibc_interface.c"], + implementation_deps = [ + "//src/common/pico_time", + "//src/rp2_common/pico_bootrom", + "//src/rp2_common/pico_printf", + "//src/rp2_common/pico_runtime_init", + "//src/rp2_common/pico_stdio:pico_stdio_headers", + ], + # It's hard to properly constrain compatibility since `auto` may select this, + # so just tag as manual. + tags = ["manual"], + target_compatible_with = compatible_with_rp2(), +) diff --git a/src/rp2_common/pico_clib_interface/CMakeLists.txt b/src/rp2_common/pico_clib_interface/CMakeLists.txt new file mode 100644 index 000000000..17af8ba56 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/CMakeLists.txt @@ -0,0 +1,42 @@ +if (NOT TARGET pico_clib_interface) + pico_add_library(pico_clib_interface) + + # ---- newlib ---- + pico_add_library(pico_newlib_interface) + + target_sources(pico_newlib_interface INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/newlib_interface.c + ) + + # ---- picolibc ---- + + pico_add_library(pico_picolibc_interface) + + target_sources(pico_picolibc_interface INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/picolibc_interface.c + ) + + # replacing the functions is fine it seems + #target_compile_definitions(pico_picolibc_interface INTERFACE + # PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS=0 + #) + + # ---- llvm_libc ---- + pico_add_library(pico_llvm_libc_interface) + + target_sources(pico_llvm_libc_interface INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/llvm_libc_interface.c + ) + + target_include_directories(pico_llvm_libc_interface SYSTEM INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/include/llvm_libc + ) + target_link_libraries(pico_llvm_libc_interface INTERFACE pico_atomic) + pico_mirrored_target_link_libraries(pico_llvm_libc_interface INTERFACE pico_stdio) + + if (NOT PICO_CLIB) + set(PICO_CLIB newlib) + endif() + + target_link_libraries(pico_clib_interface INTERFACE pico_${PICO_CLIB}_interface) +endif() diff --git a/src/rp2_common/pico_clib_interface/doc.h b/src/rp2_common/pico_clib_interface/doc.h new file mode 100644 index 000000000..1fa325800 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/doc.h @@ -0,0 +1,4 @@ +/** + * \defgroup pico_clib_interface pico_clib_interface + * \brief Provides the necessary glue code required by the particular C/C++ runtime being used + */ diff --git a/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/cdefs.h b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/cdefs.h new file mode 100644 index 000000000..0047d0bd3 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/cdefs.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PICO_LLVM_LIBC_SYS_CDEFS_H +#define __PICO_LLVM_LIBC_SYS_CDEFS_H + +#if defined(__STDC__) || defined(__cplusplus) + +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x +#define __XSTRING(x) __STRING(x) + +#endif + +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) + +#define __always_inline __inline__ __attribute__((__always_inline__)) +#define __noinline __attribute__((__noinline__)) + +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) + +#endif diff --git a/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/stat.h b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/stat.h new file mode 100644 index 000000000..b34a5c8d3 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/stat.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_LLVM_LIBC_SYS_STAT_H +#define _PICO_LLVM_LIBC_SYS_STAT_H + +typedef int off_t; + +struct stat {}; + +#endif diff --git a/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/time.h b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/time.h new file mode 100644 index 000000000..3d37f1c25 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/time.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_LLVM_LIBC_SYS_TIME_H +#define _PICO_LLVM_LIBC_SYS_TIME_H + +#include <__llvm-libc-common.h> + +#include +#include + +typedef long suseconds_t; + +struct timeval { + time_t tv_sec; + suseconds_t tv_usec; +}; + +struct timezone { + int tz_minuteswest; + int tz_dsttime; +}; + +__BEGIN_C_DECLS + +int gettimeofday(struct timeval *tv, struct timezone *tz); +int settimeofday(const struct timeval *tv, const struct timezone *tz); + +__END_C_DECLS + +#endif // _PICO_LLVM_LIBC_SYS_TIME_H diff --git a/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/times.h b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/times.h new file mode 100644 index 000000000..16dee1e5b --- /dev/null +++ b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/times.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_LLVM_LIBC_SYS_TIMES_H +#define _PICO_LLVM_LIBC_SYS_TIMES_H + +#include + +#define CLOCKS_PER_SEC 100 + +typedef int clock_t; + +struct tms { + clock_t tms_utime; + clock_t tms_stime; + clock_t tms_cutime; + clock_t tms_cstime; +}; + +#endif diff --git a/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/types.h b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/types.h new file mode 100644 index 000000000..33406d9c3 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/include/llvm_libc/sys/types.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_LLVM_LIBC_SYS_TYPES_H +#define _PICO_LLVM_LIBC_SYS_TYPES_H + +#endif diff --git a/src/rp2_common/pico_clib_interface/include/llvm_libc/time.h b/src/rp2_common/pico_clib_interface/include/llvm_libc/time.h new file mode 100644 index 000000000..2115718a1 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/include/llvm_libc/time.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_LLVM_LIBC_TIME_H +#define _PICO_LLVM_LIBC_TIME_H + +#include <__llvm-libc-common.h> + +#include +#include + +__BEGIN_C_DECLS + +time_t mktime(struct tm* arg); +struct tm* localtime_r(const time_t* timer, struct tm* buf); + +__END_C_DECLS + +#include_next + +#endif // _PICO_LLVM_LIBC_TIME_H diff --git a/src/rp2_common/pico_clib_interface/include/llvm_libc/unistd.h b/src/rp2_common/pico_clib_interface/include/llvm_libc/unistd.h new file mode 100644 index 000000000..1322eae94 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/include/llvm_libc/unistd.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_LLVM_LIBC_UNISTD_H +#define _PICO_LLVM_LIBC_UNISTD_H + +#include <__llvm-libc-common.h> + +typedef int pid_t; + +__BEGIN_C_DECLS + +_Noreturn void _exit(int) __NOEXCEPT; + +__END_C_DECLS + +#endif // _PICO_LLVM_LIBC_UNISTD_H diff --git a/src/rp2_common/pico_clib_interface/llvm_libc_interface.c b/src/rp2_common/pico_clib_interface/llvm_libc_interface.c new file mode 100644 index 000000000..da4281335 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/llvm_libc_interface.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include "pico/runtime_init.h" +#include "pico/stdio.h" +#include "pico/time.h" + +#if PICO_ENTER_USB_BOOT_ON_EXIT +#include "pico/bootrom.h" +#endif + +// These functions are defined by POSIX and not C standard. + +static int64_t epoch_time_us_since_boot; + +int gettimeofday(struct timeval *__restrict tv, __unused struct timezone *__restrict tz) { + if (tv) { + int64_t us_since_epoch = ((int64_t)to_us_since_boot(get_absolute_time())) - epoch_time_us_since_boot; + tv->tv_sec = (time_t)(us_since_epoch / 1000000); + tv->tv_usec = (suseconds_t)(us_since_epoch % 1000000); + } + return 0; +} + +int settimeofday(__unused const struct timeval *tv, __unused const struct timezone *tz) { + if (tv) { + int64_t us_since_epoch = tv->tv_sec * 1000000 + tv->tv_usec; + epoch_time_us_since_boot = (int64_t)to_us_since_boot(get_absolute_time()) - us_since_epoch; + } + return 0; +} + +// TODO: This should be a thread-local variable. +int errno; + +int *__llvm_libc_errno(void) { return &errno; } + +struct __llvm_libc_stdio_cookie {}; + +struct __llvm_libc_stdio_cookie __llvm_libc_stdin_cookie; +struct __llvm_libc_stdio_cookie __llvm_libc_stdout_cookie; +struct __llvm_libc_stdio_cookie __llvm_libc_stderr_cookie; + +ssize_t __llvm_libc_stdio_read(__unused void *cookie, char *buf, size_t size) { + for (size_t i = 0; i < size; i++) { + buf[i] = getchar_timeout_us(0); + } + return size; +} + +ssize_t __llvm_libc_stdio_write(__unused void *cookie, const char *buf, size_t size) { + // TODO: We would ideally use `stdio_put_string` from pico_stdio. + for (size_t i = 0; i < size; i++) { + putchar_raw(buf[i]); + } + return size; +} + +void __cxa_finalize(__unused void *dso) {} + +void __attribute__((noreturn)) __llvm_libc_exit(__unused int status) { +#if PICO_ENTER_USB_BOOT_ON_EXIT + reset_usb_boot(0,0); +#else + while (1) { + __breakpoint(); + } +#endif +} + +void _exit(int) __attribute__((noreturn, alias("__llvm_libc_exit"))); + +void runtime_init(void) { +#ifndef NDEBUG + if (__get_current_exception()) { + // crap; started in exception handler + __breakpoint(); + } +#endif + +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD + // install core0 stack guard + extern char __StackBottom; + runtime_init_per_core_install_stack_guard(&__StackBottom); +#endif + + // todo maybe we want to do this in the future, but it does stuff like register_tm_clones + // which we didn't do in previous SDKs + //extern void __libc_init_array(void); + //__libc_init_array(); + + // ... so instead just do the __preinit_array + runtime_run_initializers(); + // ... and the __init_array + extern void (*__init_array_start)(void); + extern void (*__init_array_end)(void); + for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) { + (*p)(); + } +} + diff --git a/src/rp2_common/pico_clib_interface/newlib_interface.c b/src/rp2_common/pico_clib_interface/newlib_interface.c new file mode 100644 index 000000000..8925e5464 --- /dev/null +++ b/src/rp2_common/pico_clib_interface/newlib_interface.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#if PICO_ENTER_USB_BOOT_ON_EXIT +#include "pico/bootrom.h" +#endif +#include "pico/time.h" +#include "pico/runtime_init.h" + +#if LIB_PICO_PRINTF_PICO +#include "pico/printf.h" +#else +#define weak_raw_printf printf +#define weak_raw_vprintf vprintf +#endif +#if LIB_PICO_STDIO +#include "pico/stdio.h" +#endif + +#if PICO_ENTER_USB_BOOT_ON_EXIT +#include "pico/bootrom.h" +#endif + +extern char __StackLimit; /* Set by linker. */ + +#define STDIO_HANDLE_STDIN 0 +#define STDIO_HANDLE_STDOUT 1 +#define STDIO_HANDLE_STDERR 2 + +void __attribute__((noreturn)) __weak _exit(__unused int status) { +#if PICO_ENTER_USB_BOOT_ON_EXIT + reset_usb_boot(0,0); +#else + while (1) { + __breakpoint(); + } +#endif +} + +__weak void *_sbrk(int incr) { + extern char end; /* Set by linker. */ + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + char *next_heap_end = heap_end + incr; + + if (__builtin_expect(next_heap_end > (&__StackLimit), false)) { +#if PICO_USE_OPTIMISTIC_SBRK + if (heap_end == &__StackLimit) { +// errno = ENOMEM; + return (char *) -1; + } + next_heap_end = &__StackLimit; +#else + return (char *) -1; +#endif + } + + heap_end = next_heap_end; + return (void *) prev_heap_end; +} + +static int64_t epoch_time_us_since_boot; + +__weak int _gettimeofday (struct timeval *__restrict tv, __unused void *__restrict tz) { + if (tv) { + int64_t us_since_epoch = ((int64_t)to_us_since_boot(get_absolute_time())) - epoch_time_us_since_boot; + tv->tv_sec = (time_t)(us_since_epoch / 1000000); + tv->tv_usec = (suseconds_t)(us_since_epoch % 1000000); + } + return 0; +} + +__weak int settimeofday(__unused const struct timeval *tv, __unused const struct timezone *tz) { + if (tv) { + int64_t us_since_epoch = tv->tv_sec * 1000000 + tv->tv_usec; + epoch_time_us_since_boot = (int64_t)to_us_since_boot(get_absolute_time()) - us_since_epoch; + } + return 0; +} + +__weak int _times(struct tms *tms) { +#if CLOCKS_PER_SEC >= 1000000 + tms->tms_utime = (clock_t)(to_us_since_boot(get_absolute_time()) * (CLOCKS_PER_SEC / 1000000)); +#else + tms->tms_utime = (clock_t)(to_us_since_boot(get_absolute_time()) / (1000000 / CLOCKS_PER_SEC)); +#endif + tms->tms_stime = 0; + tms->tms_cutime = 0; + tms->tms_cstime = 0; + return 0; +} + +__weak pid_t _getpid(void) { + return 0; +} + +__weak int _kill(__unused pid_t pid, __unused int sig) { + return -1; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int length) { +#if LIB_PICO_STDIO + if (handle == STDIO_HANDLE_STDIN) { + return stdio_get_until(buffer, length, at_the_end_of_time); + } +#endif + return -1; +} + +int __attribute__((weak)) _write(int handle, char *buffer, int length) { +#if LIB_PICO_STDIO + if (handle == STDIO_HANDLE_STDOUT || handle == STDIO_HANDLE_STDERR) { + stdio_put_string(buffer, length, false, true); + return length; + } +#endif + return -1; +} + +int __attribute__((weak)) _open(__unused const char *fn, __unused int oflag, ...) { + return -1; +} + +int __attribute__((weak)) _close(__unused int fd) { + return -1; +} + +off_t __attribute__((weak)) _lseek(__unused int fd, __unused off_t pos, __unused int whence) { + return -1; +} + +int __attribute__((weak)) _fstat(__unused int fd, __unused struct stat *buf) { + return -1; +} + +int __attribute__((weak)) _isatty(int fd) { + return fd == STDIO_HANDLE_STDIN || fd == STDIO_HANDLE_STDOUT || fd == STDIO_HANDLE_STDERR; +} + +// exit is not useful... no desire to pull in __call_exitprocs +void exit(int status) { + _exit(status); +} + +// incorrect warning from GCC 6 +GCC_Pragma("GCC diagnostic push") +GCC_Pragma("GCC diagnostic ignored \"-Wsuggest-attribute=format\"") +void __weak __assert_func(const char *file, int line, const char *func, const char *failedexpr) { + weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", + failedexpr, file, line, func ? ", function: " : "", + func ? func : ""); + + _exit(1); +} +GCC_Pragma("GCC diagnostic pop") + +void runtime_init(void) { +#ifndef NDEBUG + if (__get_current_exception()) { + // crap; started in exception handler + __breakpoint(); + } +#endif + +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD + // install core0 stack guard + extern char __StackBottom; + runtime_init_per_core_install_stack_guard(&__StackBottom); +#endif + + // todo maybe we want to do this in the future, but it does stuff like register_tm_clones + // which we didn't do in previous SDKs + //extern void __libc_init_array(void); + //__libc_init_array(); + + // ... so instead just do the __preinit_array + runtime_run_initializers(); + // ... and the __init_array + extern void (*__init_array_start)(void); + extern void (*__init_array_end)(void); + for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) { + (*p)(); + } +} \ No newline at end of file diff --git a/src/rp2_common/pico_clib_interface/picolibc_interface.c b/src/rp2_common/pico_clib_interface/picolibc_interface.c new file mode 100644 index 000000000..b10bb418d --- /dev/null +++ b/src/rp2_common/pico_clib_interface/picolibc_interface.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include "pico.h" +#if LIB_PICO_STDIO +#include "pico/stdio.h" +#endif + +#if PICO_ENTER_USB_BOOT_ON_EXIT +#include "pico/bootrom.h" +#endif + +#include "pico/time.h" +#include "pico/runtime_init.h" + +#if LIB_PICO_PRINTF_PICO +#include "pico/printf.h" +#else +#define weak_raw_printf printf +#define weak_raw_vprintf vprintf +#endif + +static int picolibc_putc(char c, __unused FILE *file) { +#if LIB_PICO_STDIO + stdio_putchar(c); +#endif + return c; +} + +static int picolibc_getc(__unused FILE *file) { +#if LIB_PICO_STDIO + return stdio_getchar(); +#endif +} + +static int picolibc_flush(__unused FILE *file) { +#if LIB_PICO_STDIO + stdio_flush(); +#endif + return 0; +} + +static FILE __stdio = FDEV_SETUP_STREAM(picolibc_putc, + picolibc_getc, + picolibc_flush, + _FDEV_SETUP_RW); + +FILE *const stdin = &__stdio; __strong_reference(stdin, stdout); __strong_reference(stdin, stderr); + +void __weak __assert_func(const char *file, int line, const char *func, const char *failedexpr) { + weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", + failedexpr, file, line, func ? ", function: " : "", + func ? func : ""); + + _exit(1); +} + + +void __attribute__((noreturn)) __weak _exit(__unused int status) { +#if PICO_ENTER_USB_BOOT_ON_EXIT + reset_usb_boot(0,0); +#else + while (1) { + __breakpoint(); + } +#endif +} + +static int64_t epoch_time_us_since_boot; + +__weak int gettimeofday (struct timeval *__restrict tv, __unused void *__restrict tz) { + if (tv) { + int64_t us_since_epoch = ((int64_t)to_us_since_boot(get_absolute_time())) - epoch_time_us_since_boot; + tv->tv_sec = (time_t)(us_since_epoch / 1000000); + tv->tv_usec = (suseconds_t)(us_since_epoch % 1000000); + } + return 0; +} + +__weak int settimeofday(__unused const struct timeval *tv, __unused const struct timezone *tz) { + if (tv) { + int64_t us_since_epoch = tv->tv_sec * 1000000 + tv->tv_usec; + epoch_time_us_since_boot = (int64_t)to_us_since_boot(get_absolute_time()) - us_since_epoch; + } + return 0; +} + + +void runtime_init(void) { +#ifndef NDEBUG + if (__get_current_exception()) { + // crap; started in exception handler + __breakpoint(); + } +#endif + +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD + // install core0 stack guard + extern char __StackBottom; + runtime_init_per_core_install_stack_guard(&__StackBottom); +#endif + + // piolibc __libc_init_array does __preint_array and __init_array + extern void __libc_init_array(void); + __libc_init_array(); +} + +#if !PICO_RUNTIME_NO_INIT_PER_CORE_TLS_SETUP +__weak void runtime_init_pre_core_tls_setup(void) { + // for now we just set the same global area on both cores + // note: that this is superfluous with the stock picolibc it seems, since it is itself + // using a version of __aeabi_read_tp that returns the same pointer on both cores + extern void __tls_base; + extern void _set_tls(void *tls); + _set_tls(&__tls_base); +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_TLS_SETUP +PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_pre_core_tls_setup, PICO_RUNTIME_INIT_PER_CORE_TLS_SETUP); +#endif + +//// naked as it must preserve everything except r0 and lr +//uint32_t __attribute__((naked)) WRAPPER_FUNC(__aeabi_read_tp)() { +// // note for now we are just returning a shared instance on both cores +// pico_default_asm_volatile( +// "ldr r0, =__tls_base\n" +// "bx lr\n" +// ); +//} \ No newline at end of file diff --git a/src/rp2_common/pico_crt0/BUILD.bazel b/src/rp2_common/pico_crt0/BUILD.bazel new file mode 100644 index 000000000..e9d5fa838 --- /dev/null +++ b/src/rp2_common/pico_crt0/BUILD.bazel @@ -0,0 +1,71 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +alias( + name = "default_linker_script", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2_common/pico_crt0/rp2040:default_linker_script", + "//bazel/constraint:rp2350": "//src/rp2_common/pico_crt0/rp2350:default_linker_script", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "blocked_ram_linker_script", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2_common/pico_crt0/rp2040:blocked_ram_linker_script", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "copy_to_ram_linker_script", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2_common/pico_crt0/rp2040:copy_to_ram_linker_script", + "//bazel/constraint:rp2350": "//src/rp2_common/pico_crt0/rp2350:copy_to_ram_linker_script", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +alias( + name = "no_flash_linker_script", + actual = select({ + "//bazel/constraint:rp2040": "//src/rp2_common/pico_crt0/rp2040:no_flash_linker_script", + "//bazel/constraint:rp2350": "//src/rp2_common/pico_crt0/rp2350:no_flash_linker_script", + "//conditions:default": "//bazel:incompatible_cc_lib", + }), +) + +cc_library( + name = "no_warn_rwx_flag", + linkopts = select({ + "//bazel/constraint:pico_toolchain_gcc_enabled": ["-Wl,--no-warn-rwx-segments"], + "//conditions:default": [], + }), + visibility = [":__subpackages__"], +) + +cc_library( + name = "pico_crt0", + srcs = ["crt0.S"], + hdrs = [ + "embedded_end_block.inc.S", + "embedded_start_block.inc.S", + ], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/boot_picobin_headers", + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:pico_platform_internal", + "//src/rp2_common/cmsis:cmsis_core", + "//src/rp2_common/pico_bootrom", + ], +) + +# TODO: RISC-V support. +filegroup( + name = "crt0_riscv", + srcs = ["crt0_riscv.S"], +) diff --git a/src/rp2_common/pico_crt0/CMakeLists.txt b/src/rp2_common/pico_crt0/CMakeLists.txt new file mode 100644 index 000000000..bd4156932 --- /dev/null +++ b/src/rp2_common/pico_crt0/CMakeLists.txt @@ -0,0 +1,19 @@ +if (NOT TARGET pico_crt0) + pico_add_library(pico_crt0) + + if (PICO_RISCV) + target_sources(pico_crt0 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/crt0_riscv.S) + else() + target_sources(pico_crt0 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/crt0.S) + endif() + + pico_mirrored_target_link_libraries(pico_crt0 INTERFACE hardware_structs hardware_regs) + target_link_libraries(pico_crt0 INTERFACE boot_picobin_headers pico_bootrom_headers) +endif() + +pico_register_common_scope_var(PICO_LINKER_SCRIPT_PATH) +if (NOT PICO_LINKER_SCRIPT_PATH) + set(PICO_LINKER_SCRIPT_PATH ${CMAKE_CURRENT_LIST_DIR}/${PICO_CHIP}) +endif() + +pico_promote_common_scope_vars() \ No newline at end of file diff --git a/src/rp2_common/pico_standard_link/crt0.S b/src/rp2_common/pico_crt0/crt0.S similarity index 68% rename from src/rp2_common/pico_standard_link/crt0.S rename to src/rp2_common/pico_crt0/crt0.S index 7d29f763d..9bf12631a 100644 --- a/src/rp2_common/pico_standard_link/crt0.S +++ b/src/rp2_common/pico_crt0/crt0.S @@ -7,10 +7,13 @@ #include "pico.h" #include "pico/asm_helper.S" -#include "hardware/regs/m0plus.h" +#include "pico/platform/cpu_regs.h" + #include "hardware/regs/addressmap.h" #include "hardware/regs/sio.h" #include "pico/binary_info/defs.h" +#include "boot/picobin.h" +#include "pico/bootrom.h" #ifdef NDEBUG #ifndef COLLAPSE_IRQS @@ -42,38 +45,25 @@ __vectors: .word isr_invalid // Reserved, should never fire .word isr_pendsv .word isr_systick -.word isr_irq0 -.word isr_irq1 -.word isr_irq2 -.word isr_irq3 -.word isr_irq4 -.word isr_irq5 -.word isr_irq6 -.word isr_irq7 -.word isr_irq8 -.word isr_irq9 -.word isr_irq10 -.word isr_irq11 -.word isr_irq12 -.word isr_irq13 -.word isr_irq14 -.word isr_irq15 -.word isr_irq16 -.word isr_irq17 -.word isr_irq18 -.word isr_irq19 -.word isr_irq20 -.word isr_irq21 -.word isr_irq22 -.word isr_irq23 -.word isr_irq24 -.word isr_irq25 -.word isr_irq26 -.word isr_irq27 -.word isr_irq28 -.word isr_irq29 -.word isr_irq30 -.word isr_irq31 +#if PICO_NO_STORED_VECTOR_TABLE && !PICO_NO_FLASH // note in no flash binary, we only have the single RAM vector table anyway +#if PICO_NO_RAM_VECTOR_TABLE +#error Can't specify PICO_NO_STORED_VECTOR_TABLE and PICO_NO_RAM_VECTOR_TABLE +#endif +// we don't include any IRQ vectors; we will initialize them during runtime_init in the RAM vector table +#else + +.altmacro +.macro isr_irqx irq_num +.word isr_irq\irq_num +.endm + +.set irq_num, 0 +.rept NUM_IRQS +isr_irqx %irq_num +.set irq_num, irq_num + 1 +.endr + +#endif // all default exception handlers do nothing, and we can check for them being set to our // default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end @@ -104,44 +94,26 @@ decl_isr_bkpt isr_systick __default_isrs_end: .macro decl_isr name +#if !PICO_NO_STORED_VECTOR_TABLE | PICO_NO_FLASH +// We declare a weak label, so user can override .weak \name +#else +// We declare a strong label, so user can't override (their version would not automatically be used) +#endif .type \name,%function .thumb_func \name: .endm -decl_isr isr_irq0 -decl_isr isr_irq1 -decl_isr isr_irq2 -decl_isr isr_irq3 -decl_isr isr_irq4 -decl_isr isr_irq5 -decl_isr isr_irq6 -decl_isr isr_irq7 -decl_isr isr_irq8 -decl_isr isr_irq9 -decl_isr isr_irq10 -decl_isr isr_irq11 -decl_isr isr_irq12 -decl_isr isr_irq13 -decl_isr isr_irq14 -decl_isr isr_irq15 -decl_isr isr_irq16 -decl_isr isr_irq17 -decl_isr isr_irq18 -decl_isr isr_irq19 -decl_isr isr_irq20 -decl_isr isr_irq21 -decl_isr isr_irq22 -decl_isr isr_irq23 -decl_isr isr_irq24 -decl_isr isr_irq25 -decl_isr isr_irq26 -decl_isr isr_irq27 -decl_isr isr_irq28 -decl_isr isr_irq29 -decl_isr isr_irq30 -decl_isr isr_irq31 +.macro decl_isrx irq_num +decl_isr isr_irq\irq_num +.endm + +.set irq_num, 0 +.rept NUM_IRQS +decl_isrx %irq_num +.set irq_num, irq_num + 1 +.endr // All unhandled USER IRQs fall through to here .global __unhandled_user_irq @@ -171,6 +143,8 @@ binary_info_header: .word BINARY_INFO_MARKER_END #endif +#include "embedded_start_block.inc.S" + // ---------------------------------------------------------------------------- .section .reset, "ax" @@ -194,15 +168,39 @@ binary_info_header: _entry_point: #if PICO_NO_FLASH + // on the NO_FLASH case, we do not do a rest thru bootrom below, so the RCP may or may not have been initialized: + // + // in the normal (e.g. UF2 download etc. case) we will have passed thru bootrom initialization, but if + // a NO_FLASH binary is loaded by the debugger, and run directly after a reset, then we won't have. + // + // we must therefore initialize the RCP if it hasn't already been + +#if HAS_REDUNDANCY_COPROCESSOR + // just enable the RCP which is fine if it already was (we assume no other co-processors are enabled at this point to save space) + ldr r0, = PPB_BASE + M33_CPACR_OFFSET + movs r1, #ARM_CPU_PREFIXED(CPACR_CP7_BITS) + str r1, [r0] + // only initialize canary seeds if they haven't been (as to do so twice is a fault) + mrc p7, #1, apsr_nzcv, c0, c0, #0 + bmi 1f + // i dont think it much matters what we initialized to, as to have gotten here we must have not + // gone thru the bootrom (which a secure boot would have) + mcrr p7, #8, r0, r0, c0 + mcrr p7, #8, r0, r0, c1 + sev +1: +#endif + ldr r0, =__vectors // Vector through our own table (SP, VTOR will not have been set up at // this point). Same path for debugger entry and bootloader entry. - ldr r0, =__vectors #else // Debugger tried to run code after loading, so SSI is in 03h-only mode. // Go back through bootrom + boot2 to properly initialise flash. - movs r0, #0 + ldr r0, =BOOTROM_VTABLE_OFFSET #endif - ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET) + +_enter_vtable_in_r0: + ldr r1, =(PPB_BASE + ARM_CPU_PREFIXED(VTOR_OFFSET)) str r0, [r1] ldmia r0!, {r1, r2} msr msp, r1 @@ -219,13 +217,41 @@ _entry_point: .thumb_func _reset_handler: // Only core 0 should run the C runtime startup code; core 1 is normally - // sleeping in the bootrom at this point but check to be sure + // sleeping in the bootrom at this point but check to be sure (e.g. if + // debugger put core 1 at the ELF entry point for some reason) ldr r0, =(SIO_BASE + SIO_CPUID_OFFSET) ldr r0, [r0] +#if __ARM_ARCH_6M__ cmp r0, #0 - bne hold_non_core0_in_bootrom + beq 1f +#else + cbz r0, 1f +#endif +hold_non_core0_in_bootrom: + // Send back to the ROM to wait for core 0 to launch it. + ldr r0, =BOOTROM_VTABLE_OFFSET + b _enter_vtable_in_r0 +1: - // In a NO_FLASH binary, don't perform .data copy, since it's loaded +#if !PICO_RP2040 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH + // Execute boot2 on the core 0 stack (it also gets copied into BOOTRAM due + // to inclusion in the data copy table below). Note the reference + // to __boot2_entry_point here is what prevents the .boot2 section from + // being garbage-collected. +_copy_xip_setup: + ldr r1, =__boot2_entry_point + mov r3, sp + add sp, #-256 + mov r2, sp + bl data_cpy +_call_xip_setup: + mov r0, sp + adds r0, #1 + blx r0 + add sp, #256 +#endif + + // In a NO_FLASH binary, don't perform .data etc copy, since it's loaded // in-place by the SRAM load. Still need to clear .bss #if !PICO_NO_FLASH adr r4, data_cpy_table @@ -254,6 +280,12 @@ bss_fill_test: platform_entry: // symbol for stack traces // Use 32-bit jumps, in case these symbols are moved out of branch range // (e.g. if main is in SRAM and crt0 in flash) +#if !__ARM_ARCH_6M__ + // Make sure stack limit is 0 - the user can set it themselves + // todo probably worth adding to the EXE_DEF in the future + movs r0, #0 + msr msplim, r0 +#endif ldr r1, =runtime_init blx r1 ldr r1, =main @@ -261,11 +293,11 @@ platform_entry: // symbol for stack traces ldr r1, =exit blx r1 // exit should not return. If it does, hang the core. - // (fall thru into our hang _exit impl 1: // separate label because _exit can be moved out of branch range bkpt #0 b 1b + #if !PICO_NO_FLASH data_cpy_loop: ldm r1!, {r0} @@ -281,6 +313,12 @@ data_cpy: .align 2 data_cpy_table: +#if PICO_RP2350 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH +.word __boot2_start__ +.word BOOTRAM_BASE +.word BOOTRAM_BASE + 256 +#endif + #if PICO_COPY_TO_RAM .word __ram_text_source__ .word __ram_text_start__ @@ -310,17 +348,6 @@ data_cpy_table: runtime_init: bx lr -// ---------------------------------------------------------------------------- -// If core 1 somehow gets into crt0 due to a spectacular VTOR mishap, we need to -// catch it and send back to the sleep-and-launch code in the bootrom. Shouldn't -// happen (it should sleep in the ROM until given an entry point via the -// cross-core FIFOs) but it's good to be defensive. - -hold_non_core0_in_bootrom: - ldr r0, = 'W' | ('V' << 8) - bl rom_func_lookup - bx r0 - // ---------------------------------------------------------------------------- // Stack/heap dummies to set size @@ -350,3 +377,5 @@ spacer_section .heap .p2align 2 .equ HeapSize, PICO_HEAP_SIZE .space HeapSize + +#include "embedded_end_block.inc.S" diff --git a/src/rp2_common/pico_crt0/crt0_riscv.S b/src/rp2_common/pico_crt0/crt0_riscv.S new file mode 100644 index 000000000..0e89ab150 --- /dev/null +++ b/src/rp2_common/pico_crt0/crt0_riscv.S @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico.h" + +#include "hardware/regs/addressmap.h" +#include "hardware/regs/rvcsr.h" +#include "pico/binary_info/defs.h" +#include "boot/picobin.h" +#include "pico/bootrom_constants.h" + +#ifdef NDEBUG +#ifndef COLLAPSE_IRQS +#define COLLAPSE_IRQS +#endif +#endif + +#if !defined(PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM) +#define PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM 1 +#endif + +#ifndef PICO_CRT0_INCLUDE_PICOBIN_BLOCK +#define PICO_CRT0_INCLUDE_PICOBIN_BLOCK PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM +#endif + +#ifndef PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK +#define PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK (PICO_CRT0_INCLUDE_PICOBIN_BLOCK && !PICO_NO_FLASH) +#endif + +// If vectors are in RAM, we put them in the .data section, so that they are +// preloaded by _reset_handler (assuming this is not a loaded-in-place +// binary). +#if PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH +.section .vectors, "ax" +#else +.section .data +#endif + +.p2align 6 +.global __vectors, __VECTOR_TABLE +__VECTOR_TABLE: +__vectors: + +// Hardware vector table for standard RISC-V interrupts, indicated by `mtvec`. + +.option push +.option norvc +.option norelax +j isr_riscv_machine_exception +.word 0 +.word 0 +j isr_riscv_machine_soft_irq +.word 0 +.word 0 +.word 0 +j isr_riscv_machine_timer +.word 0 +.word 0 +.word 0 +// j isr_riscv_machine_external_irq -> inlined below +.option pop + +// External IRQ dispatch, inlined into the last vector table slot. Note if +// this code is modified, the VTABLE_FIRST_IRQ define in platform_defs.h also +// needs to be modified (it identifies the beginning of the soft vector table) +.global isr_riscv_machine_external_irq +.weak isr_riscv_machine_external_irq +isr_riscv_machine_external_irq: + // Save caller saves and exception return state whilst IRQs are disabled. + // We can't be preempted during this time, but if a higher-priority IRQ + // arrives before we read meinext, that will be the one we enter. + addi sp, sp, -80 + sw ra, 0(sp) + sw t0, 4(sp) + sw t1, 8(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + csrr a0, mepc + csrr a1, mstatus + sw a0, 64(sp) + sw a1, 68(sp) +save_meicontext: + // Make sure to set meicontext.clearts to clear+save mie.msie/mtie along + // with ext IRQ context. We don't let these preempt ext IRQs because they + // clear meicontext.mreteirq, which breaks __get_current_exception(). + csrrsi a2, RVCSR_MEICONTEXT_OFFSET, RVCSR_MEICONTEXT_CLEARTS_BITS + sw a2, 72(sp) + +get_first_irq: + // Sample the current highest-priority active IRQ (left-shifted by 2) from + // meinext, and write 1 to meinext.update to update meicontext with the + // preemption priority and IRQ number of this IRQ + csrrsi a0, RVCSR_MEINEXT_OFFSET, RVCSR_MEINEXT_UPDATE_BITS + // MSB will be set if there is no active IRQ at the current priority level + bltz a0, no_more_irqs +dispatch_irq: + // Preemption priority was configured by meinext update, so enable preemption: + csrsi mstatus, 0x8 + // <- from this point we can be preempted by a higher-priority interrupt. + // meinext is pre-shifted by 2, so only an add is required to index table + lui a1, %hi(__soft_vector_table) + add a1, a1, a0 + lw a1, %lo(__soft_vector_table)(a1) + jalr ra, a1 + // Disable IRQs on returning so we can sample the next IRQ + csrci mstatus, 0x8 +get_next_irq: + // Get the next-highest-priority IRQ that is active at this level. If + // there is such an IRQ, update meicontext with new preemption priority. + csrrsi a0, RVCSR_MEINEXT_OFFSET, RVCSR_MEINEXT_UPDATE_BITS + // MSB will be set if there is no active IRQ at the current priority level + bgez a0, dispatch_irq + +no_more_irqs: + // Restore saved context and return from IRQ + lw a0, 64(sp) + lw a1, 68(sp) + lw a2, 72(sp) + csrw mepc, a0 + csrw mstatus, a1 + csrw RVCSR_MEICONTEXT_OFFSET, a2 + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + // skip a0 for now + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + // Before popping the stack frame, check if there is a new IRQ, and if so, + // abandon the mret and take the IRQ. This avoids a worst-case (restore -> + // mret -> enter -> save) latency. Note since we have already restored + // meicontext, we will have to re-save it, to re-clear mtie/msie. +check_irq_before_exit: + csrr a0, RVCSR_MEINEXT_OFFSET + bgez a0, save_meicontext + lw a0, 16(sp) + addi sp, sp, 80 + mret + +// Default software vector table for system interrupts, routed through +// mip.meip. Note this is assumed in e.g. hardware_irq to begin exactly 0x34 +// words after the hardware vector table indicated by mtvec (defined above). +.p2align 4 +.global __soft_vector_table +__soft_vector_table: +.word isr_irq0 +.word isr_irq1 +.word isr_irq2 +.word isr_irq3 +.word isr_irq4 +.word isr_irq5 +.word isr_irq6 +.word isr_irq7 +.word isr_irq8 +.word isr_irq9 +.word isr_irq10 +.word isr_irq11 +.word isr_irq12 +.word isr_irq13 +.word isr_irq14 +.word isr_irq15 +.word isr_irq16 +.word isr_irq17 +.word isr_irq18 +.word isr_irq19 +.word isr_irq20 +.word isr_irq21 +.word isr_irq22 +.word isr_irq23 +.word isr_irq24 +.word isr_irq25 +.word isr_irq26 +.word isr_irq27 +.word isr_irq28 +.word isr_irq29 +.word isr_irq30 +.word isr_irq31 +.word isr_irq32 +.word isr_irq33 +.word isr_irq34 +.word isr_irq35 +.word isr_irq36 +.word isr_irq37 +.word isr_irq38 +.word isr_irq39 +.word isr_irq40 +.word isr_irq41 +.word isr_irq42 +.word isr_irq43 +.word isr_irq44 +.word isr_irq45 +.word isr_irq46 +.word isr_irq47 +.word isr_irq48 +.word isr_irq49 +.word isr_irq50 +.word isr_irq51 + +// all default trap handlers do nothing, and we can check for them being set to our +// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end +.global __default_isrs_start +__default_isrs_start: + +// Declare a weak symbol for each ISR. +// By default, they will fall through to the undefined IRQ handler below (breakpoint), +// but can be overridden by C functions with correct name. + +.macro decl_isr name +.weak \name +\name: +.endm + +.macro decl_isr_bkpt name +.weak \name +\name: + ebreak +.endm + +// hardware_exception on RISC-V defines its own weak handler +#if !PICO_CRT0_NO_ISR_RISCV_MACHINE_EXCEPTION +// Breakpoint will just cause another exception and trash the exception +// state, since there is no double fault lockup on RISC-V. Instead, just +// sleep the core indefinitely, or until debugger connects. +decl_isr isr_riscv_machine_exception +#endif + +// Note the mip.mtip is also available as SIO_IRQ_MTIMECMP, and this may be a +// better option, because it plays nicely with interrupt preemption. +decl_isr_bkpt isr_riscv_machine_timer +decl_isr_bkpt isr_riscv_machine_soft_irq + +decl_isr isr_irq0 +decl_isr isr_irq1 +decl_isr isr_irq2 +decl_isr isr_irq3 +decl_isr isr_irq4 +decl_isr isr_irq5 +decl_isr isr_irq6 +decl_isr isr_irq7 +decl_isr isr_irq8 +decl_isr isr_irq9 +decl_isr isr_irq10 +decl_isr isr_irq11 +decl_isr isr_irq12 +decl_isr isr_irq13 +decl_isr isr_irq14 +decl_isr isr_irq15 +decl_isr isr_irq16 +decl_isr isr_irq17 +decl_isr isr_irq18 +decl_isr isr_irq19 +decl_isr isr_irq20 +decl_isr isr_irq21 +decl_isr isr_irq22 +decl_isr isr_irq23 +decl_isr isr_irq24 +decl_isr isr_irq25 +decl_isr isr_irq26 +decl_isr isr_irq27 +decl_isr isr_irq28 +decl_isr isr_irq29 +decl_isr isr_irq30 +decl_isr isr_irq31 +decl_isr isr_irq32 +decl_isr isr_irq33 +decl_isr isr_irq34 +decl_isr isr_irq35 +decl_isr isr_irq36 +decl_isr isr_irq37 +decl_isr isr_irq38 +decl_isr isr_irq39 +decl_isr isr_irq40 +decl_isr isr_irq41 +decl_isr isr_irq42 +decl_isr isr_irq43 +decl_isr isr_irq44 +decl_isr isr_irq45 +decl_isr isr_irq46 +decl_isr isr_irq47 +decl_isr isr_irq48 +decl_isr isr_irq49 +decl_isr isr_irq50 +decl_isr isr_irq51 + // fall through + +// All unhandled USER IRQs fall through to here. Note there is no way to get +// the "current exception" on RISC-V (as there is no such thing -- the +// hardware does not model the exception lifecycle like on Arm) so instead we +// just pass the IRQ number into the IRQ handler in a0. +.global __unhandled_user_irq +__unhandled_user_irq: +.global unhandled_user_irq_num_in_a0 +unhandled_user_irq_num_in_a0: + // The dispatch code will have left IRQ << 2 in a0 from its meinext read, + // so just need to shift it back down + srli a0, a0, 2 + ebreak + +.global __default_isrs_end +__default_isrs_end: + +// ---------------------------------------------------------------------------- + +.section .binary_info_header, "a" + +// Header must be in first 256 bytes of main image (i.e. excluding flash boot2). +// For flash builds we put it immediately after vector table; for NO_FLASH the +// vectors are at a +0x100 offset because the bootrom enters RAM images directly +// at their lowest address, so we put the header in the VTOR alignment hole. + +#if !PICO_NO_BINARY_INFO +binary_info_header: +.word BINARY_INFO_MARKER_START +.word __binary_info_start +.word __binary_info_end +.word data_cpy_table // we may need to decode pointers that are in RAM at runtime. +.word BINARY_INFO_MARKER_END +#endif + +#include "embedded_start_block.inc.S" + +// ---------------------------------------------------------------------------- + +.section .reset, "ax" + +// On flash builds, the vector table comes first in the image (conventional). +// On NO_FLASH builds, the reset handler section comes first, as the entry +// point is at offset 0 (fixed due to bootrom), and VTOR is highly-aligned. +// Image is entered in various ways: +// +// - NO_FLASH builds are entered from beginning by UF2 bootloader +// +// - Flash builds vector through the table into _reset_handler from boot2 +// +// - Either type can be entered via _entry_point by the debugger, and flash builds +// must then be sent back round the boot sequence to properly initialise flash + +// ELF entry point: +.global _entry_point +_entry_point: + +#if PICO_NO_FLASH + // Go through our own reset handler. Same path for debugger entry and + // bootloader entry. + j _reset_handler +#else + // Debugger tried to run code after loading, so SSI is in 03h-only mode. + // Go back through bootrom + boot2 to properly initialise flash. + j reenter_bootrom +#endif + +// Reset handler: +// - initialises .data +// - clears .bss +// - calls runtime_init +// - calls main +// - calls exit (which should eventually hang the processor via _exit) + +_reset_handler: +.option push +.option norelax + la gp, __global_pointer$ +.option pop + la sp, __StackTop + // Leave interrupts globally disabled for now, we will set that up later + // in runtime_init_per_core_h3_irq_registers. Still worth installing the vector table: + la a0, __vectors + 1 + csrw mtvec, a0 + + // Only core 0 should run the C runtime startup code; core 1 is normally + // sleeping in the bootrom at this point but check to be sure + csrr a0, mhartid + bnez a0, reenter_bootrom + +#if PICO_RP2350 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH + // Execute boot2 on the core 0 stack (it also gets copied into BOOTRAM due + // to inclusion in the data copy table below) +_copy_xip_setup: + mv a2, sp + addi sp, sp, -256 + mv a0, sp + la a1, __boot2_entry_point +1: + // Iterate forward, as sequential flash access is faster + lw a3, (a1) + sw a3, (a0) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a0, a2, 1b +_call_xip_setup: + jalr sp + addi sp, sp, 256 +#endif + + // In a NO_FLASH binary, don't perform .data etc copy, since it's loaded + // in-place by the SRAM load. Still need to clear .bss +#if !PICO_NO_FLASH + la a4, data_cpy_table + + // assume there is at least one entry +1: + lw a1, 0(a4) + beqz a1, 2f + lw a2, 4(a4) + lw a3, 8(a4) + addi a4, a4, 12 + jal data_cpy + j 1b +2: +#endif + + // Zero out the BSS + la a1, __bss_start__ + la a2, __bss_end__ + j bss_fill_test +bss_fill_loop: + sw zero, (a1) + addi a1, a1, 4 +bss_fill_test: + bne a1, a2, bss_fill_loop + +platform_entry: // symbol for stack traces + // Use `call` pseudo-instruction instead of a bare `jal` so that the + // linker can use longer sequences if these are out of `jal` range. Will + // still get relaxed to a `jal` if possible. + // call runtime_init_per_core_h3_irq_registers (now called in runtime_init) + call runtime_init + call main + call exit + // exit should not return. If it does, hang the core. + // (fall thru into our hang _exit impl +1: // separate label because _exit can be moved out of branch range + ebreak + j 1b + +data_cpy_loop: + lw a0, (a1) + sw a0, (a2) + addi a1, a1, 4 + addi a2, a2, 4 +data_cpy: + bltu a2, a3, data_cpy_loop + ret + +.align 2 +data_cpy_table: +#if PICO_RP2350 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH +.word __boot2_start__ +.word BOOTRAM_BASE +.word BOOTRAM_BASE + 256 +#endif +#if PICO_COPY_TO_RAM +.word __ram_text_source__ +.word __ram_text_start__ +.word __ram_text_end__ +#endif +.word __etext +.word __data_start__ +.word __data_end__ + +.word __scratch_x_source__ +.word __scratch_x_start__ +.word __scratch_x_end__ + +.word __scratch_y_source__ +.word __scratch_y_start__ +.word __scratch_y_end__ + +.word 0 // null terminator + +// ---------------------------------------------------------------------------- +// Provide safe defaults for _exit and runtime_init +// Full implementations usually provided by platform.c + +.weak runtime_init +runtime_init: + ret + +// ---------------------------------------------------------------------------- +// If core 1 somehow gets into crt0, we need to catch it and send back to the +// sleep-and-launch code in the bootrom. Shouldn't happen (it should sleep in +// the ROM until given an entry point via the cross-core FIFOs) but it's good +// to be defensive. + +// Enter through the shared reset handler: on core 1 this should quickly reach +// the wait-for-vector code. +reenter_bootrom: + +#ifdef RASPBERRYPI_AMETHYST_FPGA + // todo remove once 64k bootrom support is not required: vvvvvvvvvvvvvvvvvvvvv + // Try jumping 32k higher and see if we get a fault :) + li a0, BOOTROM_ENTRY_OFFSET + 32 * 1024 + la a1, 1f + csrw mtvec, a1 + jr a0 + // Go here if we trapped: +.p2align 2 +1: +#endif + + li a0, BOOTROM_ENTRY_OFFSET + jr a0 + +// ---------------------------------------------------------------------------- +// IRQ register clearing + +// Enable interrupts globally, but disable all interrupt sources. +// +// This is put in the .text section as it is called again on core 1 launch. In +// COPY_TO_RAM binaries, the .reset section is always in flash, whereas .text +// is in SRAM, and we try to avoid running any code from flash after entering +// user code in a COPY_TO_RAM binary. Note because of this we don't call this +// function here in crt0 until after the flash-to-RAM copying is finished. + +.section .text +.global runtime_init_per_core_h3_irq_registers +runtime_init_per_core_h3_irq_registers: + // First clear all IRQ force array bits. Iterate over array registers 0 + // through 3 inclusive, allowing for up to 64 IRQs. Don't clear the + // enable array as earlier (non-per-core) init stages may have already + // set up IRQs. + li a0, 3 +1: + csrw RVCSR_MEIFA_OFFSET, a0 + addi a0, a0, -1 + bgez a0, 1b + // Setting the global external IRQ enable in mie prepares us to enable + // IRQs one-by-one later. Also clear the soft IRQ and timer IRQ enables: + li a0, RVCSR_MIE_MEIE_BITS + csrw mie, a0 + // Set the global IRQ: we will now take any individual interrupt that is + // pending && enabled + csrsi mstatus, RVCSR_MSTATUS_MIE_BITS + // Take this chance to clear mscratch, which is used to detect nested + // exceptions in isr_riscv_machine_exception: + csrw mscratch, zero + ret + +// ---------------------------------------------------------------------------- +// Stack/heap dummies to set size + +// Prior to SDK 1.5.1 these were `.section .stack` without the `, "a"`... Clang linker gives a warning about this, +// however setting it explicitly to `, "a"` makes GCC *now* discard the section unless it is also KEEP. This +// seems like very surprising behavior! +// +// Strictly the most correct thing to do (as .stack and .heap are unreferenced) is to mark them as "a", and also KEEP, which +// works correctly for both GCC and Clang, however doing so may break anyone who already has custom linker scripts without +// the KEEP. Therefore we will only add the "a" on Clang, but will also use KEEP to our own linker scripts. + +.macro spacer_section name +#if PICO_ASSEMBLER_IS_CLANG +.section \name, "a" +#else +.section \name +#endif +.endm + +spacer_section .stack +// align to allow for memory protection (although this alignment is pretty much ignored by linker script) +.p2align 5 + .equ StackSize, PICO_STACK_SIZE +.space StackSize + +spacer_section .heap +.p2align 2 + .equ HeapSize, PICO_HEAP_SIZE +.space HeapSize + +#include "embedded_end_block.inc.S" + diff --git a/src/rp2_common/pico_crt0/doc.h b/src/rp2_common/pico_crt0/doc.h new file mode 100644 index 000000000..c48eb2b18 --- /dev/null +++ b/src/rp2_common/pico_crt0/doc.h @@ -0,0 +1,8 @@ +/** + * \defgroup pico_crt0 pico_crt0 + * \brief Provides the default linker scripts and the program entry/exit point + */ + +// PICO_CONFIG: PICO_EMBED_XIP_SETUP, Embed custom XIP setup (boot2) in an RP2350 binary, type=bool, default=0, group=pico_base +// unused but keeps tooling happy +#define PICO_EMBED_XIP_SETUP 0 \ No newline at end of file diff --git a/src/rp2_common/pico_crt0/embedded_end_block.inc.S b/src/rp2_common/pico_crt0/embedded_end_block.inc.S new file mode 100644 index 000000000..9b56633f2 --- /dev/null +++ b/src/rp2_common/pico_crt0/embedded_end_block.inc.S @@ -0,0 +1,17 @@ +#if PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK +.section .embedded_end_block, "a" +embedded_end_block: +.word PICOBIN_BLOCK_MARKER_START + +.byte PICOBIN_BLOCK_ITEM_2BS_IGNORED +.byte 0x1 // 1 word +.hword 0 + +.byte PICOBIN_BLOCK_ITEM_2BS_LAST +.hword (embedded_end_block_end - embedded_end_block - 16 ) / 4 // total size of all items +.byte 0 +// offset from this block to first block +.word embedded_block - embedded_end_block +.word PICOBIN_BLOCK_MARKER_END +embedded_end_block_end: +#endif diff --git a/src/rp2_common/pico_crt0/embedded_start_block.inc.S b/src/rp2_common/pico_crt0/embedded_start_block.inc.S new file mode 100644 index 000000000..8f1b622d4 --- /dev/null +++ b/src/rp2_common/pico_crt0/embedded_start_block.inc.S @@ -0,0 +1,109 @@ +#if !defined(PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM) +// todo decide whether we want this item for RP2040 by default, probably not (there are a zilloon binaries out there without it) +#if !PICO_RP2040 +#define PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM 1 +#endif +#endif + +#ifndef PICO_CRT0_INCLUDE_PICOBIN_BLOCK +#define PICO_CRT0_INCLUDE_PICOBIN_BLOCK PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM +#endif + +#ifndef PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK +#define PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK (PICO_CRT0_INCLUDE_PICOBIN_BLOCK && !PICO_NO_FLASH) +#endif + +#if PICO_CRT0_IMAGE_TYPE_TBYB +#define CRT0_TBYB_FLAG PICOBIN_IMAGE_TYPE_EXE_TBYB_BITS +#else +#define CRT0_TBYB_FLAG 0 +#endif + +#if defined(PICO_CRT0_VERSION_MINOR) && !defined(PICO_CRT0_VERSION_MAJOR) +#define PICO_CRT0_VERSION_MAJOR 0 +#endif + +#if PICO_CRT0_INCLUDE_PICOBIN_BLOCK +.section .embedded_block, "a" +.p2align 2 +embedded_block: +.word PICOBIN_BLOCK_MARKER_START + +#if PICO_CRT0_INCLUDE_PICOBIN_IMAGE_TYPE_ITEM +// include an IMAGE_TYPE item at the start so this block is a valid IMAGE_DEF block, and can be used as a basis +// for booting the binary with a known type. +.byte PICOBIN_BLOCK_ITEM_1BS_IMAGE_TYPE +.byte 0x1 // 1 word +#ifdef PICO_CRT0_IMAGE_TYPE_ITEM_VALUE +.hword PICO_CRT0_IMAGE_TYPE_ITEM_VALUE +#elif defined(__riscv) +.hword PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(EXE) | \ + PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(RISCV) | \ + PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(RP2350) | \ + CRT0_TBYB_FLAG +#elif defined(PICO_RP2040) +.hword PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(EXE) | \ + PICOBIN_IMAGE_TYPE_EXE_SECURITY_AS_BITS(NS) | \ + PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(ARM) | \ + PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(RP2040) | \ + CRT0_TBYB_FLAG +#else +.hword PICOBIN_IMAGE_TYPE_IMAGE_TYPE_AS_BITS(EXE) | \ + PICOBIN_IMAGE_TYPE_EXE_SECURITY_AS_BITS(S) | \ + PICOBIN_IMAGE_TYPE_EXE_CPU_AS_BITS(ARM) | \ + PICOBIN_IMAGE_TYPE_EXE_CHIP_AS_BITS(RP2350) | \ + CRT0_TBYB_FLAG +#endif +#else +// if no image type, then add ignored item +.byte PICOBIN_BLOCK_ITEM_2BS_IGNORED +.byte 0x1 // 1 word +.hword 0 +#endif + +#ifdef PICO_CRT0_VERSION_MAJOR +.byte PICOBIN_BLOCK_ITEM_1BS_VERSION +.byte 0x2 // 2 words +.hword 0 +#ifdef PICO_CRT0_VERSION_MINOR +.hword PICO_CRT0_VERSION_MINOR +#else +.hword 0 +#endif +.hword PICO_CRT0_VERSION_MAJOR +#endif + +#ifdef __riscv +// On RISC-V the default entry point from bootrom is the start of the binary, but +// we have our vtable at the start, so we must include an entry point +.byte PICOBIN_BLOCK_ITEM_1BS_ENTRY_POINT +.byte 0x3 // word size to next item +.byte 0 // pad +.byte 0 // pad +.word _reset_handler +.word SRAM_END // stack pointer +#endif + +#ifndef PICO_RP2040 +#if PICO_NO_FLASH +// If no_flash bin, then include a vector table item +.byte PICOBIN_BLOCK_ITEM_1BS_VECTOR_TABLE +.byte 0x2 +.hword 0 +.word __vectors +#endif +#endif + +.byte PICOBIN_BLOCK_ITEM_2BS_LAST +.hword (embedded_block_end - embedded_block - 16 ) / 4 // total size of all +.byte 0 +#if PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK +.word embedded_end_block - embedded_block +#else +// offset from this block to next block in loop (since we are a single block loop, we point back to ourselves +// so the offset is 0) +.word 0 +#endif +.word PICOBIN_BLOCK_MARKER_END +embedded_block_end: +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_crt0/rp2040/BUILD.bazel b/src/rp2_common/pico_crt0/rp2040/BUILD.bazel new file mode 100644 index 000000000..d70458677 --- /dev/null +++ b/src/rp2_common/pico_crt0/rp2040/BUILD.bazel @@ -0,0 +1,59 @@ +package(default_visibility = ["//visibility:public"]) + +# It's possible to set linker scripts globally or on a per-binary basis. +# +# Setting globally: +# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_LINKER_SCRIPT to point to your +# desired linker script. +# +# Setting per-binary: +# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_LINKER_SCRIPT=@pico-sdk//bazel:empty_cc_lib +# * Manually add your desired linker script to each cc_binary. +cc_library( + name = "default_linker_script", + linkopts = ["-T$(location memmap_default.ld)"], + target_compatible_with = ["//bazel/constraint:rp2040"], + deps = [ + "memmap_default.ld", + "//src/rp2_common/pico_crt0:no_warn_rwx_flag", + "//src/rp2_common/pico_standard_link:default_flash_region", + ], +) + +# PICO_BUILD_DEFINE: PICO_USE_BLOCKED_RAM, whether this is a 'blocked_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link +cc_library( + name = "blocked_ram_linker_script", + defines = ["PICO_USE_BLOCKED_RAM=1"], + linkopts = ["-T$(location memmap_blocked_ram.ld)"], + target_compatible_with = ["//bazel/constraint:rp2040"], + deps = [ + "memmap_blocked_ram.ld", + "//src/rp2_common/pico_crt0:no_warn_rwx_flag", + "//src/rp2_common/pico_standard_link:default_flash_region", + ], +) + +# PICO_BUILD_DEFINE: PICO_COPY_TO_RAM, whether this is a 'copy_to_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link +cc_library( + name = "copy_to_ram_linker_script", + defines = ["PICO_COPY_TO_RAM=1"], + linkopts = ["-T$(location memmap_copy_to_ram.ld)"], + target_compatible_with = ["//bazel/constraint:rp2040"], + deps = [ + "memmap_copy_to_ram.ld", + "//src/rp2_common/pico_crt0:no_warn_rwx_flag", + "//src/rp2_common/pico_standard_link:default_flash_region", + ], +) + +# PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link +cc_library( + name = "no_flash_linker_script", + defines = ["PICO_NO_FLASH=1"], + linkopts = ["-T$(location memmap_no_flash.ld)"], + target_compatible_with = ["//bazel/constraint:rp2040"], + deps = [ + "memmap_no_flash.ld", + "//src/rp2_common/pico_crt0:no_warn_rwx_flag", + ], +) diff --git a/src/rp2_common/pico_standard_link/memmap_blocked_ram.ld b/src/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld similarity index 85% rename from src/rp2_common/pico_standard_link/memmap_blocked_ram.ld rename to src/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld index 52384e1d6..175312ff9 100644 --- a/src/rp2_common/pico_standard_link/memmap_blocked_ram.ld +++ b/src/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld @@ -23,7 +23,7 @@ MEMORY { - FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + INCLUDE "pico_flash_region.ld" RAM(rwx) : ORIGIN = 0x21000000, LENGTH = 256k SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k @@ -63,6 +63,8 @@ SECTIONS KEEP (*(.vectors)) KEEP (*(.binary_info_header)) __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; KEEP (*(.reset)) /* TODO revisit this now memset/memcpy/float in ROM */ /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from @@ -83,6 +85,27 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + *(.eh_frame*) . = ALIGN(4); } > FLASH @@ -150,54 +173,35 @@ SECTIONS PROVIDE_HIDDEN (__mutex_array_end = .); . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - + *(.jcr) . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); + } > RAM AT> FLASH - *(.jcr) + .tdata : { . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) /* All data end */ - __data_end__ = .; + __tdata_end = .; } > RAM AT> FLASH + PROVIDE(__data_end__ = .); + /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ __etext = LOADADDR(.data); - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) + .tbss (NOLOAD) : { . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); + __tls_end = .; + } > RAM - .bss : { + .bss (NOLOAD) : { . = ALIGN(4); - __bss_start__ = .; + __tbss_end = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) *(COMMON) . = ALIGN(4); @@ -209,9 +213,29 @@ SECTIONS __end__ = .; end = __end__; KEEP(*(.heap*)) + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + . = ORIGIN(RAM) + LENGTH(RAM); __HeapLimit = .; } > RAM + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + /* .stack*_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later @@ -231,6 +255,7 @@ SECTIONS } > SCRATCH_Y .flash_end : { + KEEP(*(.embedded_end_block*)) PROVIDE(__flash_binary_end = .); } > FLASH @@ -242,6 +267,17 @@ SECTIONS __StackBottom = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") diff --git a/src/rp2_common/pico_standard_link/memmap_copy_to_ram.ld b/src/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld similarity index 84% rename from src/rp2_common/pico_standard_link/memmap_copy_to_ram.ld rename to src/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld index 1d7e514f5..78b8a1f2b 100644 --- a/src/rp2_common/pico_standard_link/memmap_copy_to_ram.ld +++ b/src/rp2_common/pico_crt0/rp2040/memmap_copy_to_ram.ld @@ -23,7 +23,7 @@ MEMORY { - FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + INCLUDE "pico_flash_region.ld" RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k @@ -63,6 +63,8 @@ SECTIONS KEEP (*(.vectors)) KEEP (*(.binary_info_header)) __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; KEEP (*(.reset)) } @@ -174,32 +176,33 @@ SECTIONS *(.jcr) . = ALIGN(4); + } > RAM AT> FLASH + + .tdata : { + . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) /* All data end */ - __data_end__ = .; + __tdata_end = .; } > RAM AT> FLASH + PROVIDE(__data_end__ = .); + /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ __etext = LOADADDR(.data); - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) + .tbss (NOLOAD) : { . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); + __tls_end = .; + } > RAM .bss : { . = ALIGN(4); - __bss_start__ = .; + __tbss_end = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) *(COMMON) . = ALIGN(4); @@ -211,9 +214,29 @@ SECTIONS __end__ = .; end = __end__; KEEP(*(.heap*)) + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + . = ORIGIN(RAM) + LENGTH(RAM); __HeapLimit = .; } > RAM + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + /* .stack*_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later @@ -233,7 +256,8 @@ SECTIONS } > SCRATCH_Y .flash_end : { - __flash_binary_end = .; + KEEP(*(.embedded_end_block*)) + PROVIDE(__flash_binary_end = .); } > FLASH /* stack limit is poorly named, but historically is maximum heap ptr */ @@ -244,6 +268,17 @@ SECTIONS __StackBottom = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") diff --git a/src/rp2_common/pico_standard_link/memmap_default.ld b/src/rp2_common/pico_crt0/rp2040/memmap_default.ld similarity index 85% rename from src/rp2_common/pico_standard_link/memmap_default.ld rename to src/rp2_common/pico_crt0/rp2040/memmap_default.ld index b4dadfc0c..aea712a53 100644 --- a/src/rp2_common/pico_standard_link/memmap_default.ld +++ b/src/rp2_common/pico_crt0/rp2040/memmap_default.ld @@ -23,7 +23,7 @@ MEMORY { - FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k + INCLUDE "pico_flash_region.ld" RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k @@ -63,6 +63,8 @@ SECTIONS KEEP (*(.vectors)) KEEP (*(.binary_info_header)) __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; KEEP (*(.reset)) /* TODO revisit this now memset/memcpy/float in ROM */ /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from @@ -83,6 +85,27 @@ SECTIONS *(SORT(.dtors.*)) *(.dtors) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + *(.eh_frame*) . = ALIGN(4); } > FLASH @@ -150,54 +173,35 @@ SECTIONS PROVIDE_HIDDEN (__mutex_array_end = .); . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(SORT(.preinit_array.*))) - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - + *(.jcr) . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - *(SORT(.fini_array.*)) - *(.fini_array) - PROVIDE_HIDDEN (__fini_array_end = .); + } > RAM AT> FLASH - *(.jcr) + .tdata : { . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) /* All data end */ - __data_end__ = .; + __tdata_end = .; } > RAM AT> FLASH + PROVIDE(__data_end__ = .); + /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ __etext = LOADADDR(.data); - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) + .tbss (NOLOAD) : { . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X AT > FLASH - __scratch_x_source__ = LOADADDR(.scratch_x); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y AT > FLASH - __scratch_y_source__ = LOADADDR(.scratch_y); + __tls_end = .; + } > RAM - .bss : { + .bss (NOLOAD) : { . = ALIGN(4); - __bss_start__ = .; + __tbss_end = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) *(COMMON) . = ALIGN(4); @@ -209,9 +213,29 @@ SECTIONS __end__ = .; end = __end__; KEEP(*(.heap*)) + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + . = ORIGIN(RAM) + LENGTH(RAM); __HeapLimit = .; } > RAM + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + /* .stack*_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later @@ -231,6 +255,7 @@ SECTIONS } > SCRATCH_Y .flash_end : { + KEEP(*(.embedded_end_block*)) PROVIDE(__flash_binary_end = .); } > FLASH @@ -242,6 +267,17 @@ SECTIONS __StackBottom = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") diff --git a/src/rp2_common/pico_standard_link/memmap_no_flash.ld b/src/rp2_common/pico_crt0/rp2040/memmap_no_flash.ld similarity index 83% rename from src/rp2_common/pico_standard_link/memmap_no_flash.ld rename to src/rp2_common/pico_crt0/rp2040/memmap_no_flash.ld index 915147f20..b9d3c3763 100644 --- a/src/rp2_common/pico_standard_link/memmap_no_flash.ld +++ b/src/rp2_common/pico_crt0/rp2040/memmap_no_flash.ld @@ -46,8 +46,10 @@ SECTIONS __reset_end = .; KEEP (*(.binary_info_header)) __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; . = ALIGN(256); - KEEP (*(.vectors)) + KEEP (*(.vectors)) *(.time_critical*) *(.text*) . = ALIGN(4); @@ -70,6 +72,7 @@ SECTIONS } > RAM .rodata : { + . = ALIGN(4); *(.rodata*) . = ALIGN(4); *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) @@ -106,7 +109,6 @@ SECTIONS . = ALIGN(4); *(.after_data.*) - . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__mutex_array_start = .); @@ -137,9 +139,15 @@ SECTIONS *(.jcr) . = ALIGN(4); + } > RAM + + .tdata : { + . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) /* All data end */ - __data_end__ = .; + __tdata_end = .; } > RAM + PROVIDE(__data_end__ = .); .uninitialized_data (NOLOAD): { . = ALIGN(4); @@ -148,26 +156,20 @@ SECTIONS /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ __etext = LOADADDR(.data); - /* Start and end symbols must be word-aligned */ - .scratch_x : { - __scratch_x_start__ = .; - *(.scratch_x.*) + .tbss (NOLOAD) : { . = ALIGN(4); - __scratch_x_end__ = .; - } > SCRATCH_X - __scratch_x_source__ = LOADADDR(.scratch_x); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) - .scratch_y : { - __scratch_y_start__ = .; - *(.scratch_y.*) - . = ALIGN(4); - __scratch_y_end__ = .; - } > SCRATCH_Y - __scratch_y_source__ = LOADADDR(.scratch_y); + __tls_end = .; + } > RAM - .bss : { + .bss (NOLOAD) : { . = ALIGN(4); - __bss_start__ = .; + __tbss_end = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) *(COMMON) . = ALIGN(4); @@ -179,9 +181,29 @@ SECTIONS __end__ = .; end = __end__; KEEP(*(.heap*)) + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + . = ORIGIN(RAM) + LENGTH(RAM); __HeapLimit = .; } > RAM + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y + __scratch_y_source__ = LOADADDR(.scratch_y); + /* .stack*_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later @@ -208,6 +230,17 @@ SECTIONS __StackBottom = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") diff --git a/src/rp2_common/pico_crt0/rp2350/BUILD.bazel b/src/rp2_common/pico_crt0/rp2350/BUILD.bazel new file mode 100644 index 000000000..5c13f5a95 --- /dev/null +++ b/src/rp2_common/pico_crt0/rp2350/BUILD.bazel @@ -0,0 +1,46 @@ +package(default_visibility = ["//visibility:public"]) + +# It's possible to set linker scripts globally or on a per-binary basis. +# +# Setting globally: +# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_LINKER_SCRIPT to point to your +# desired linker script. +# +# Setting per-binary: +# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_LINKER_SCRIPT=@pico-sdk//bazel:empty_cc_lib +# * Manually add your desired linker script to each cc_binary. +cc_library( + name = "default_linker_script", + linkopts = ["-T$(location memmap_default.ld)"], + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + "memmap_default.ld", + "//src/rp2_common/pico_crt0:no_warn_rwx_flag", + "//src/rp2_common/pico_standard_link:default_flash_region", + ], +) + +# PICO_BUILD_DEFINE: PICO_COPY_TO_RAM, whether this is a 'copy_to_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link +cc_library( + name = "copy_to_ram_linker_script", + defines = ["PICO_COPY_TO_RAM=1"], + linkopts = ["-T$(location memmap_copy_to_ram.ld)"], + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + "memmap_copy_to_ram.ld", + "//src/rp2_common/pico_crt0:no_warn_rwx_flag", + "//src/rp2_common/pico_standard_link:default_flash_region", + ], +) + +# PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link +cc_library( + name = "no_flash_linker_script", + defines = ["PICO_NO_FLASH=1"], + linkopts = ["-T$(location memmap_no_flash.ld)"], + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + "memmap_no_flash.ld", + "//src/rp2_common/pico_crt0:no_warn_rwx_flag", + ], +) diff --git a/src/rp2_common/pico_crt0/rp2350/memmap_copy_to_ram.ld b/src/rp2_common/pico_crt0/rp2350/memmap_copy_to_ram.ld new file mode 100644 index 000000000..f365682b3 --- /dev/null +++ b/src/rp2_common/pico_crt0/rp2350/memmap_copy_to_ram.ld @@ -0,0 +1,310 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + INCLUDE "pico_flash_region.ld" + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k + SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + /* Second stage bootloader is prepended to the image. It must be 256 bytes big + and checksummed. It is usually built by the boot_stage2 target + in the Raspberry Pi Pico SDK + */ + + .flash_begin : { + __flash_binary_start = .; + } > FLASH + + /* The bootrom will enter the image at the point indicated in your + IMAGE_DEF, which is usually the reset handler of your vector table. + + The debugger will use the ELF entry point, which is the _entry_point + symbol, and in our case is *different from the bootrom's entry point.* + This is used to go back through the bootrom on debugger launches only, + to perform the same initial flash setup that would be performed on a + cold boot. + */ + + .flashtext : { + __logical_binary_start = .; + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; + KEEP (*(.reset)) + . = ALIGN(4); + } > FLASH + + /* Note the boot2 section is optional, and should be discarded if there is + no reference to it *inside* the binary, as it is not called by the + bootrom. (The bootrom performs a simple best-effort XIP setup and + leaves it to the binary to do anything more sophisticated.) However + there is still a size limit of 256 bytes, to ensure the boot2 can be + stored in boot RAM. + + Really this is a "XIP setup function" -- the name boot2 is historic and + refers to its dual-purpose on RP2040, where it also handled vectoring + from the bootrom into the user image. + */ + + .boot2 : { + __boot2_start__ = .; + *(.boot2) + __boot2_end__ = .; + } > FLASH + + ASSERT(__boot2_end__ - __boot2_start__ <= 256, + "ERROR: Pico second stage bootloader must be no more than 256 bytes in size") + + .rodata : { + /* segments not marked as .flashdata are instead pulled into .data (in RAM) to avoid accidental flash accesses */ + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + . = ALIGN(4); + + /* Vector table goes first in RAM, to avoid large alignment hole */ + .ram_vector_table (NOLOAD): { + *(.ram_vector_table) + } > RAM + + .uninitialized_data (NOLOAD): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + .text : { + __ram_text_start__ = .; + *(.init) + *(.text*) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.eh_frame*) + . = ALIGN(4); + __ram_text_end__ = .; + } > RAM AT> FLASH + __ram_text_source__ = LOADADDR(.text); + . = ALIGN(4); + + .data : { + __data_start__ = .; + *(vtable) + + *(.time_critical*) + + . = ALIGN(4); + *(.rodata*) + *(.srodata*) + . = ALIGN(4); + + *(.data*) + *(.sdata*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + } > RAM AT> FLASH + + .tdata : { + . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) + /* All data end */ + __tdata_end = .; + } > RAM AT> FLASH + PROVIDE(__data_end__ = .); + + /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ + __etext = LOADADDR(.data); + + .tbss (NOLOAD) : { + . = ALIGN(4); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + + __tls_end = .; + } > RAM + + .bss : { + . = ALIGN(4); + __tbss_end = .; + + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + PROVIDE(__global_pointer$ = . + 2K); + *(.sbss*) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + . = ORIGIN(RAM) + LENGTH(RAM); + __HeapLimit = .; + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (NOLOAD): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > SCRATCH_Y + + .flash_end : { + KEEP(*(.embedded_end_block*)) + PROVIDE(__flash_binary_end = .); + } > FLASH =0xaa + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") + ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") + + /* todo assert on extra code */ +} + diff --git a/src/rp2_common/pico_crt0/rp2350/memmap_default.ld b/src/rp2_common/pico_crt0/rp2350/memmap_default.ld new file mode 100644 index 000000000..ba8a113e2 --- /dev/null +++ b/src/rp2_common/pico_crt0/rp2350/memmap_default.ld @@ -0,0 +1,303 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + INCLUDE "pico_flash_region.ld" + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k + SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + .flash_begin : { + __flash_binary_start = .; + } > FLASH + + /* The bootrom will enter the image at the point indicated in your + IMAGE_DEF, which is usually the reset handler of your vector table. + + The debugger will use the ELF entry point, which is the _entry_point + symbol, and in our case is *different from the bootrom's entry point.* + This is used to go back through the bootrom on debugger launches only, + to perform the same initial flash setup that would be performed on a + cold boot. + */ + + .text : { + __logical_binary_start = .; + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; + KEEP (*(.reset)) + /* TODO revisit this now memset/memcpy/float in ROM */ + /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from + * FLASH ... we will include any thing excluded here in .data below by default */ + *(.init) + *libgcc.a:cmse_nonsecure_call.o + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.eh_frame*) + . = ALIGN(4); + } > FLASH + + /* Note the boot2 section is optional, and should be discarded if there is + no reference to it *inside* the binary, as it is not called by the + bootrom. (The bootrom performs a simple best-effort XIP setup and + leaves it to the binary to do anything more sophisticated.) However + there is still a size limit of 256 bytes, to ensure the boot2 can be + stored in boot RAM. + + Really this is a "XIP setup function" -- the name boot2 is historic and + refers to its dual-purpose on RP2040, where it also handled vectoring + from the bootrom into the user image. + */ + + .boot2 : { + __boot2_start__ = .; + *(.boot2) + __boot2_end__ = .; + } > FLASH + + ASSERT(__boot2_end__ - __boot2_start__ <= 256, + "ERROR: Pico second stage bootloader must be no more than 256 bytes in size") + + .rodata : { + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) + *(.srodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + . = ALIGN(4); + + .ram_vector_table (NOLOAD): { + *(.ram_vector_table) + } > RAM + + .uninitialized_data (NOLOAD): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + .data : { + __data_start__ = .; + *(vtable) + + *(.time_critical*) + + /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ + *(.text*) + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + + *(.data*) + *(.sdata*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + *(.jcr) + . = ALIGN(4); + } > RAM AT> FLASH + + .tdata : { + . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) + /* All data end */ + __tdata_end = .; + } > RAM AT> FLASH + PROVIDE(__data_end__ = .); + + /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ + __etext = LOADADDR(.data); + + .tbss (NOLOAD) : { + . = ALIGN(4); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + + __tls_end = .; + } > RAM + + .bss (NOLOAD) : { + . = ALIGN(4); + __tbss_end = .; + + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + PROVIDE(__global_pointer$ = . + 2K); + *(.sbss*) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + . = ORIGIN(RAM) + LENGTH(RAM); + __HeapLimit = .; + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (NOLOAD): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > SCRATCH_Y + + .flash_end : { + KEEP(*(.embedded_end_block*)) + PROVIDE(__flash_binary_end = .); + } > FLASH =0xaa + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") + ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") + + /* todo assert on extra code */ +} + diff --git a/src/rp2_common/pico_crt0/rp2350/memmap_no_flash.ld b/src/rp2_common/pico_crt0/rp2350/memmap_no_flash.ld new file mode 100644 index 000000000..2febe5299 --- /dev/null +++ b/src/rp2_common/pico_crt0/rp2350/memmap_no_flash.ld @@ -0,0 +1,257 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k + SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + /* Note unlike RP2040, we start the image with a vector table even for + NO_FLASH builds. On Arm, the bootrom expects a VT at the start of the + image by default; on RISC-V, the default is to enter the image at its + lowest address, so an IMAGEDEF item is required to specify the + nondefault entry point. */ + + .text : { + __logical_binary_start = .; + /* Vectors require 512-byte alignment on v8-M when >48 IRQs are used, + so we would waste RAM if the vector table were not at the + start. */ + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; + __reset_start = .; + KEEP (*(.reset)) + __reset_end = .; + *(.time_critical*) + *(.text*) + . = ALIGN(4); + *(.init) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.eh_frame*) + } > RAM + + .rodata : { + . = ALIGN(4); + *(.rodata*) + *(.srodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > RAM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > RAM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > RAM + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > RAM + __binary_info_end = .; + . = ALIGN(4); + + .data : { + __data_start__ = .; + *(vtable) + *(.data*) + *(.sdata*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.jcr) + . = ALIGN(4); + } > RAM + + .tdata : { + . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) + /* All data end */ + __tdata_end = .; + } > RAM + PROVIDE(__data_end__ = .); + + .uninitialized_data (NOLOAD): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ + __etext = LOADADDR(.data); + + .tbss (NOLOAD) : { + . = ALIGN(4); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + + __tls_end = .; + } > RAM + + .bss (NOLOAD) : { + . = ALIGN(4); + __tbss_end = .; + + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + PROVIDE(__global_pointer$ = . + 2K); + *(.sbss*) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + . = ORIGIN(RAM) + LENGTH(RAM); + __HeapLimit = .; + } > RAM + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y + __scratch_y_source__ = LOADADDR(.scratch_y); + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (NOLOAD): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > SCRATCH_Y + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") + ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") + + /* todo assert on extra code */ +} + diff --git a/src/rp2_common/pico_cxx_options/BUILD.bazel b/src/rp2_common/pico_cxx_options/BUILD.bazel index adcabd9d7..cef710c86 100644 --- a/src/rp2_common/pico_cxx_options/BUILD.bazel +++ b/src/rp2_common/pico_cxx_options/BUILD.bazel @@ -1,8 +1,21 @@ load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel/util:sdk_define.bzl", "pico_sdk_define") package(default_visibility = ["//visibility:public"]) +# PICO_BUILD_DEFINE: PICO_CXX_ENABLE_EXCEPTIONS, value of CMake var PICO_CXX_ENABLE_EXCEPTIONS, type=string, default=0, group=pico_cxx_options +pico_sdk_define( + name = "PICO_CXX_ENABLE_EXCEPTIONS", + define_name = "PICO_CXX_ENABLE_EXCEPTIONS", + from_flag = "//bazel/config:PICO_CXX_ENABLE_EXCEPTIONS", +) + cc_library( name = "pico_cxx_options", + srcs = ["new_delete.cpp"], target_compatible_with = compatible_with_rp2(), + deps = [ + ":PICO_CXX_ENABLE_EXCEPTIONS", + "//src/rp2_common:pico_platform", + ], ) diff --git a/src/rp2_common/pico_cxx_options/CMakeLists.txt b/src/rp2_common/pico_cxx_options/CMakeLists.txt index 4b20e3ab2..500fceb57 100644 --- a/src/rp2_common/pico_cxx_options/CMakeLists.txt +++ b/src/rp2_common/pico_cxx_options/CMakeLists.txt @@ -1,7 +1,11 @@ if (NOT TARGET pico_cxx_options) - add_library(pico_cxx_options INTERFACE) + pico_add_library(pico_cxx_options) - # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_EXCEPTIONS, Enabled CXX exception handling, type=bool, default=0, group=pico_cxx_options + target_sources(pico_cxx_options INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/new_delete.cpp + ) + + # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_EXCEPTIONS, Enable CXX exception handling, type=bool, default=0, group=pico_cxx_options # PICO_BUILD_DEFINE: PICO_CXX_ENABLE_EXCEPTIONS, value of CMake var PICO_CXX_ENABLE_EXCEPTIONS, type=string, default=0, group=pico_cxx_options if (NOT PICO_CXX_ENABLE_EXCEPTIONS) target_compile_definitions( pico_cxx_options INTERFACE PICO_CXX_ENABLE_EXCEPTIONS=0) @@ -11,12 +15,12 @@ if (NOT TARGET pico_cxx_options) target_compile_definitions( pico_cxx_options INTERFACE PICO_CXX_ENABLE_EXCEPTIONS=1) endif() - # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_RTTI, Enabled CXX rtti, type=bool, default=0, group=pico_cxx_options + # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_RTTI, Enable CXX rtti, type=bool, default=0, group=pico_cxx_options if (NOT PICO_CXX_ENABLE_RTTI) target_compile_options( pico_cxx_options INTERFACE $<$:-fno-rtti>) endif() - # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_CXA_ATEXIT, Enabled cxa-atexit, type=bool, default=0, group=pico_cxx_options + # PICO_CMAKE_CONFIG: PICO_CXX_ENABLE_CXA_ATEXIT, Enable cxa-atexit, type=bool, default=0, group=pico_cxx_options if (NOT PICO_CXX_ENABLE_CXA_ATEXIT) target_compile_options( pico_cxx_options INTERFACE $<$:-fno-use-cxa-atexit>) endif() diff --git a/src/rp2_common/pico_standard_link/new_delete.cpp b/src/rp2_common/pico_cxx_options/new_delete.cpp similarity index 100% rename from src/rp2_common/pico_standard_link/new_delete.cpp rename to src/rp2_common/pico_cxx_options/new_delete.cpp diff --git a/src/rp2_common/pico_cyw43_arch/BUILD.bazel b/src/rp2_common/pico_cyw43_arch/BUILD.bazel index a17fc2a64..6484bf5b8 100644 --- a/src/rp2_common/pico_cyw43_arch/BUILD.bazel +++ b/src/rp2_common/pico_cyw43_arch/BUILD.bazel @@ -43,7 +43,7 @@ _CONFIGURATIONS = [ incompatible_with_config("//bazel/constraint:pico_freertos_unset") if kind == "freertos" else [] ), deps = [ - "//src/common/pico_base", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_async_context:pico_async_context_{}".format(kind), "//src/rp2_common/pico_cyw43_driver", "//src/rp2_common/pico_lwip", diff --git a/src/rp2_common/pico_cyw43_arch/CMakeLists.txt b/src/rp2_common/pico_cyw43_arch/CMakeLists.txt index 9ba7f59f8..ae81bccd5 100644 --- a/src/rp2_common/pico_cyw43_arch/CMakeLists.txt +++ b/src/rp2_common/pico_cyw43_arch/CMakeLists.txt @@ -8,7 +8,7 @@ if (PICO_CYW43_SUPPORTED) # set by BOARD=pico-w ${CMAKE_CURRENT_LIST_DIR}/cyw43_arch_freertos.c ) - target_include_directories(pico_cyw43_arch_headers INTERFACE + target_include_directories(pico_cyw43_arch_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_cyw43_arch INTERFACE diff --git a/src/rp2_common/pico_cyw43_arch/cyw43_arch.c b/src/rp2_common/pico_cyw43_arch/cyw43_arch.c index bdfab8c56..024e3aecd 100644 --- a/src/rp2_common/pico_cyw43_arch/cyw43_arch.c +++ b/src/rp2_common/pico_cyw43_arch/cyw43_arch.c @@ -163,12 +163,12 @@ int cyw43_arch_init_with_country(uint32_t country) { } void cyw43_arch_gpio_put(uint wl_gpio, bool value) { - invalid_params_if(CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT); + invalid_params_if(PICO_CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT); cyw43_gpio_set(&cyw43_state, (int)wl_gpio, value); } bool cyw43_arch_gpio_get(uint wl_gpio) { - invalid_params_if(CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT); + invalid_params_if(PICO_CYW43_ARCH, wl_gpio >= CYW43_WL_GPIO_COUNT); bool value = false; cyw43_gpio_get(&cyw43_state, (int)wl_gpio, &value); return value; diff --git a/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h index 1806ea43d..46aa09896 100644 --- a/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h +++ b/src/rp2_common/pico_cyw43_arch/include/pico/cyw43_arch.h @@ -130,9 +130,13 @@ extern "C" { * - Sets \c CYW43_LWIP=0 to disable lwIP support in \c pico_cyw43_arch and \c cyw43_driver */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_CYW43_ARCH, Enable/disable assertions in the pico_cyw43_arch module, type=bool, default=0, group=pico_cyw43_arch -#ifndef PARAM_ASSERTIONS_ENABLED_CYW43_ARCH -#define PARAM_ASSERTIONS_ENABLED_CYW43_ARCH 0 +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH, Enable/disable assertions in the pico_cyw43_arch module, type=bool, default=0, group=pico_cyw43_arch +#ifndef PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH +#ifdef PARAM_ASSERTIONS_ENABLED_CYW43_ARCH // backwards compatibility with SDK < 2.0.0 +#define PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH PARAM_ASSERTIONS_ENABLED_CYW43_ARCH +#else +#define PARAM_ASSERTIONS_ENABLED_PICO_CYW43_ARCH 0 +#endif #endif // PICO_CONFIG: PICO_CYW43_ARCH_DEBUG_ENABLED, Enable/disable some debugging output in the pico_cyw43_arch module, type=bool, default=1 in debug builds, group=pico_cyw43_arch diff --git a/src/rp2_common/pico_cyw43_driver/BUILD.bazel b/src/rp2_common/pico_cyw43_driver/BUILD.bazel index f1286a053..f99018c93 100644 --- a/src/rp2_common/pico_cyw43_driver/BUILD.bazel +++ b/src/rp2_common/pico_cyw43_driver/BUILD.bazel @@ -7,8 +7,8 @@ cc_library( hdrs = ["include/cyw43_configport.h"], includes = ["include"], deps = [ - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_gpio", ], ) @@ -34,7 +34,7 @@ cc_library( ":cyw43_bus_pio", ":cyw43_configport", "//bazel/config:PICO_BTSTACK_CONFIG", - "//src/common/pico_base", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_dma", "//src/rp2_common/hardware_irq", diff --git a/src/rp2_common/pico_cyw43_driver/CMakeLists.txt b/src/rp2_common/pico_cyw43_driver/CMakeLists.txt index 79e609646..eba583328 100644 --- a/src/rp2_common/pico_cyw43_driver/CMakeLists.txt +++ b/src/rp2_common/pico_cyw43_driver/CMakeLists.txt @@ -30,7 +30,7 @@ if (EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE}) ${PICO_CYW43_DRIVER_PATH}/src/cyw43_lwip.c ${PICO_CYW43_DRIVER_PATH}/src/cyw43_ctrl.c ) - target_include_directories(cyw43_driver_headers INTERFACE + target_include_directories(cyw43_driver_headers SYSTEM INTERFACE ${PICO_CYW43_DRIVER_PATH}/src ${PICO_CYW43_DRIVER_PATH}/firmware ) @@ -39,7 +39,7 @@ if (EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE}) pico_add_library(pico_cyw43_driver NOFLAG) target_sources(pico_cyw43_driver INTERFACE cyw43_driver.c) - target_include_directories(pico_cyw43_driver_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_cyw43_driver_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_cyw43_driver INTERFACE cyw43_driver) # cyw43_driver_picow is cyw43_driver plus Pico W specific bus implementation @@ -63,21 +63,21 @@ if (EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE}) ${CMAKE_CURRENT_LIST_DIR}/btstack_hci_transport_cyw43.c ${CMAKE_CURRENT_LIST_DIR}/btstack_chipset_cyw43.c ) - target_include_directories(pico_btstack_hci_transport_cyw43_headers INTERFACE + target_include_directories(pico_btstack_hci_transport_cyw43_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include ) target_compile_definitions(pico_btstack_hci_transport_cyw43_headers INTERFACE CYW43_ENABLE_BLUETOOTH=1 ) - if (TARGET pico_btstack_base) + if (PICO_CYW43_SUPPORTED AND TARGET pico_btstack_base) message("Pico W Bluetooth build support available.") pico_add_library(pico_btstack_cyw43) target_sources(pico_btstack_cyw43 INTERFACE ${CMAKE_CURRENT_LIST_DIR}/btstack_cyw43.c ) - target_include_directories(pico_btstack_cyw43_headers INTERFACE + target_include_directories(pico_btstack_cyw43_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include ) pico_mirrored_target_link_libraries(pico_btstack_cyw43 INTERFACE diff --git a/src/rp2_common/pico_cyw43_driver/cybt_shared_bus/BUILD.bazel b/src/rp2_common/pico_cyw43_driver/cybt_shared_bus/BUILD.bazel new file mode 100644 index 000000000..a1e24b0df --- /dev/null +++ b/src/rp2_common/pico_cyw43_driver/cybt_shared_bus/BUILD.bazel @@ -0,0 +1,14 @@ +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "cybt_shared_bus_driver", + srcs = [ + "cybt_shared_bus.c", + "cybt_shared_bus_driver.c", + ], + hdrs = ["cybt_shared_bus_driver.h"], + includes = ["."], + deps = [ + "@cyw43-driver//:cyw43_driver", + ], +) diff --git a/src/rp2_common/pico_cyw43_driver/cybt_shared_bus/CMakeLists.txt b/src/rp2_common/pico_cyw43_driver/cybt_shared_bus/CMakeLists.txt index fad69cd10..536b71531 100644 --- a/src/rp2_common/pico_cyw43_driver/cybt_shared_bus/CMakeLists.txt +++ b/src/rp2_common/pico_cyw43_driver/cybt_shared_bus/CMakeLists.txt @@ -5,7 +5,7 @@ target_sources(cybt_shared_bus INTERFACE ${CMAKE_CURRENT_LIST_DIR}/cybt_shared_bus.c ${CMAKE_CURRENT_LIST_DIR}/cybt_shared_bus_driver.c ) -target_include_directories(cybt_shared_bus_headers INTERFACE +target_include_directories(cybt_shared_bus_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR} ) diff --git a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c index 29cd50b0d..0339571dd 100644 --- a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c +++ b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c @@ -18,6 +18,7 @@ #include "cyw43_internal.h" #include "cyw43_spi.h" #include "cyw43_debug_pins.h" +#include "pico/cyw43_driver.h" #if CYW43_SPI_PIO #define WL_REG_ON 23 @@ -40,12 +41,19 @@ #define SPI_OFFSET_END __CONCAT(SPI_PROGRAM_NAME, _offset_end) #define SPI_OFFSET_LP1_END __CONCAT(SPI_PROGRAM_NAME, _offset_lp1_end) -#ifdef CYW43_PIO_CLOCK_DIV -#define CLOCK_DIV CYW43_PIO_CLOCK_DIV +#if !CYW43_PIO_CLOCK_DIV_DYNAMIC +#define cyw43_pio_clock_div_int CYW43_PIO_CLOCK_DIV_INT +#define cyw43_pio_clock_div_frac CYW43_PIO_CLOCK_DIV_FRAC #else -#define CLOCK_DIV 2 +static uint16_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT; +static uint8_t cyw43_pio_clock_div_frac = CYW43_PIO_CLOCK_DIV_FRAC; + +void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac) { + cyw43_pio_clock_div_int = clock_div_int; + cyw43_pio_clock_div_frac = clock_div_frac; +} #endif -#define CLOCK_DIV_MINOR 0 + #define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA #if !CYW43_USE_SPI @@ -97,16 +105,21 @@ int cyw43_spi_init(cyw43_int_t *self) { // Only does something if CYW43_LOGIC_DEBUG=1 logic_debug_init(); - static_assert(NUM_PIOS == 2, ""); + static_assert(NUM_PIOS == 2 || NUM_PIOS == 3, ""); - pio_hw_t *pios[2] = {pio0, pio1}; +#if NUM_PIOS == 2 + pio_hw_t *pios[NUM_PIOS] = {pio0, pio1}; +#else + pio_hw_t *pios[NUM_PIOS] = {pio0, pio1, pio2}; +#endif uint pio_index = CYW43_SPI_PIO_PREFERRED_PIO; // Check we can add the program - if (!pio_can_add_program(pios[pio_index], &SPI_PROGRAM_FUNC)) { - pio_index ^= 1; - if (!pio_can_add_program(pios[pio_index], &SPI_PROGRAM_FUNC)) { + for(uint i=1; i < NUM_PIOS;i++) { + if (pio_can_add_program(pios[pio_index], &SPI_PROGRAM_FUNC)) break; + if (i == NUM_PIOS - 1) { return CYW43_FAIL_FAST_CHECK(-CYW43_EIO); } + pio_index = (pio_index + 1 ) % NUM_PIOS; } assert(!self->bus_data); self->bus_data = &bus_data_instance; @@ -126,12 +139,12 @@ int cyw43_spi_init(cyw43_int_t *self) { bus_data->pio_offset = pio_add_program(bus_data->pio, &SPI_PROGRAM_FUNC); pio_sm_config config = SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC(bus_data->pio_offset); - sm_config_set_clkdiv_int_frac(&config, CLOCK_DIV, CLOCK_DIV_MINOR); - hw_write_masked(&padsbank0_hw->io[CLOCK_PIN], + sm_config_set_clkdiv_int_frac(&config, cyw43_pio_clock_div_int, cyw43_pio_clock_div_frac); + hw_write_masked(&pads_bank0_hw->io[CLOCK_PIN], (uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB, PADS_BANK0_GPIO0_DRIVE_BITS ); - hw_write_masked(&padsbank0_hw->io[CLOCK_PIN], + hw_write_masked(&pads_bank0_hw->io[CLOCK_PIN], (uint)1 << PADS_BANK0_GPIO0_SLEWFAST_LSB, PADS_BANK0_GPIO0_SLEWFAST_BITS ); diff --git a/src/rp2_common/pico_cyw43_driver/cyw43_driver.c b/src/rp2_common/pico_cyw43_driver/cyw43_driver.c index c472f0bf4..11d2652e0 100644 --- a/src/rp2_common/pico_cyw43_driver/cyw43_driver.c +++ b/src/rp2_common/pico_cyw43_driver/cyw43_driver.c @@ -9,6 +9,7 @@ #include "pico/unique_id.h" #include "cyw43.h" #include "pico/cyw43_driver.h" +#include "pico/async_context.h" #ifndef CYW43_GPIO_IRQ_HANDLER_PRIORITY #define CYW43_GPIO_IRQ_HANDLER_PRIORITY 0x40 diff --git a/src/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h b/src/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h index 366ea2100..37d3648b7 100644 --- a/src/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h +++ b/src/rp2_common/pico_cyw43_driver/include/pico/btstack_cyw43.h @@ -16,7 +16,7 @@ extern "C" { * \defgroup pico_btstack_cyw43 pico_btstack_cyw43 * \ingroup pico_cyw43_driver * - * \brief Low-level Bluetooth HCI support. + * \brief Low-level Bluetooth HCI support * * This library provides utility functions to initialise and de-initialise BTstack for CYW43, */ diff --git a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h index 4ab39b8d7..d35363ec1 100644 --- a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h +++ b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h @@ -11,16 +11,17 @@ * \defgroup pico_cyw43_driver pico_cyw43_driver * * \brief A wrapper around the lower level cyw43_driver, that integrates it with \ref pico_async_context - * for handling background work. + * for handling background work */ #include "pico.h" -#include "pico/async_context.h" #ifdef __cplusplus extern "C" { #endif +struct async_context; + /*! \brief Initializes the lower level cyw43_driver and integrates it with the provided async_context * \ingroup pico_cyw43_driver * @@ -29,14 +30,38 @@ extern "C" { * \param context the async_context instance that provides the abstraction for handling asynchronous work. * \return true if the initialization succeeded */ -bool cyw43_driver_init(async_context_t *context); +bool cyw43_driver_init(struct async_context *context); /*! \brief De-initialize the lowever level cyw43_driver and unhooks it from the async_context * \ingroup pico_cyw43_driver * * \param context the async_context the cyw43_driver support was added to via \ref cyw43_driver_init */ -void cyw43_driver_deinit(async_context_t *context); +void cyw43_driver_deinit(struct async_context *context); + +// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_DYNAMIC, Enable runtime configuration of the clock divider for communication with the wireless chip, type=bool, default=0, group=pico_cyw43_driver +#ifndef CYW43_PIO_CLOCK_DIV_DYNAMIC +#define CYW43_PIO_CLOCK_DIV_DYNAMIC 0 +#endif + +// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_INT, Integer part of the clock divider for communication with the wireless chip, type=bool, default=2, group=pico_cyw43_driver +#ifndef CYW43_PIO_CLOCK_DIV_INT +// backwards compatibility using old define +#ifdef CYW43_PIO_CLOCK_DIV +#define CYW43_PIO_CLOCK_DIV_INT CYW43_PIO_CLOCK_DIV +#else +#define CYW43_PIO_CLOCK_DIV_INT 2 +#endif +#endif + +// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, Fractional part of the clock divider for communication with the wireless chip, type=bool, default=0, group=pico_cyw43_driver +#ifndef CYW43_PIO_CLOCK_DIV_FRAC +#define CYW43_PIO_CLOCK_DIV_FRAC 0 +#endif + +#if CYW43_PIO_CLOCK_DIV_DYNAMIC +void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac); +#endif #ifdef __cplusplus } diff --git a/src/rp2_common/pico_divider/BUILD.bazel b/src/rp2_common/pico_divider/BUILD.bazel index 074359a65..efd295a55 100644 --- a/src/rp2_common/pico_divider/BUILD.bazel +++ b/src/rp2_common/pico_divider/BUILD.bazel @@ -1,10 +1,37 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") - package(default_visibility = ["//visibility:public"]) -cc_library( +alias( name = "pico_divider", - srcs = ["divider.S"], + actual = select({ + "//bazel/constraint:pico_divider_auto_enabled": ":pico_divider_auto", + "//bazel/constraint:pico_divider_hardware_enabled": ":divider_hardware", + "//conditions:default": ":divider_compiler", + }), +) + +alias( + name = "pico_divider_auto", + actual = select({ + "//bazel/constraint:rp2040": ":divider_hardware", + "//conditions:default": ":divider_compiler", + }), +) + +cc_library( + name = "divider_compiler", + srcs = ["divider_compiler.c"], + target_compatible_with = ["//bazel/constraint:rp2350"], + deps = [ + "//src/common/pico_divider_headers", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_divider", + ], +) + +cc_library( + name = "divider_hardware", + srcs = ["divider_hardware.S"], linkopts = [ "-Wl,--wrap=__aeabi_idiv", "-Wl,--wrap=__aeabi_idivmod", @@ -13,11 +40,12 @@ cc_library( "-Wl,--wrap=__aeabi_uidivmod", "-Wl,--wrap=__aeabi_uldivmod", ], - target_compatible_with = compatible_with_rp2(), + target_compatible_with = ["//bazel/constraint:rp2040"], deps = [ + "//src/common/pico_divider_headers", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_divider", - "//src/rp2_common/pico_platform", - "//src/rp2_common/pico_platform:hardware_regs", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) diff --git a/src/rp2_common/pico_divider/CMakeLists.txt b/src/rp2_common/pico_divider/CMakeLists.txt index 13ce96043..679107320 100644 --- a/src/rp2_common/pico_divider/CMakeLists.txt +++ b/src/rp2_common/pico_divider/CMakeLists.txt @@ -4,24 +4,32 @@ if (NOT TARGET pico_divider) # no custom implementation; falls thru to compiler pico_add_library(pico_divider_compiler) + target_sources(pico_divider_compiler INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/divider_compiler.c + ) + target_link_libraries(pico_divider_compiler_headers INTERFACE pico_divider_headers) - # add alias "default" which is just hardware. + # add alias "default" which is hardware for RP2040 and compiler for RP2350 add_library(pico_divider_default INTERFACE) - target_link_libraries(pico_divider_default INTERFACE pico_divider_hardware) + if (PICO_RP2040) + target_link_libraries(pico_divider_default INTERFACE pico_divider_hardware) + else() + target_link_libraries(pico_divider_default INTERFACE pico_divider_compiler) + endif() set(PICO_DEFAULT_DIVIDER_IMPL pico_divider_default) target_link_libraries(pico_divider INTERFACE $>,$,${PICO_DEFAULT_DIVIDER_IMPL}>) - add_library(pico_divider_hardware_explicit INTERFACE) + pico_add_library(pico_divider_hardware_explicit NOFLAG) target_sources(pico_divider_hardware_explicit INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/divider.S + ${CMAKE_CURRENT_LIST_DIR}/divider_hardware.S ) - target_link_libraries(pico_divider_hardware_explicit INTERFACE + target_link_libraries(pico_divider_hardware_explicit_headers INTERFACE pico_divider_headers - hardware_divider + hardware_divider_headers hardware_regs ) diff --git a/src/rp2_common/pico_divider/divider_compiler.c b/src/rp2_common/pico_divider/divider_compiler.c new file mode 100644 index 000000000..82e43390a --- /dev/null +++ b/src/rp2_common/pico_divider/divider_compiler.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/divider.h" + +// These functions save/restore divider state, so are safe to call from interrupts +int32_t div_s32s32(int32_t a, int32_t b) { + return hw_divider_quotient_s32(a, b); +} + +divmod_result_t divmod_s32s32(int32_t a, int32_t b) { + return hw_divider_divmod_s32(a, b); +} + +uint32_t div_u32u32(uint32_t a, uint32_t b) { + return hw_divider_u32_quotient(a, b); +} + +divmod_result_t divmod_u32u32(uint32_t a, uint32_t b) { + return hw_divider_divmod_u32(a, b); +} + +static inline int __sign_of_64(int64_t v) { + return v > 0 ? 1 : (v < 0 ? -1 : 0); +} + +typedef struct { + uint64_t quotient; + uint64_t remainder; +} qr_u64; + +typedef struct { + int64_t quotient; + int64_t remainder; +} qr_s64; + +// divides unsigned values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 +static inline qr_u64 udiv64(uint64_t a, uint64_t b) { + qr_u64 rc; + if (!b) { + rc.quotient = (uint64_t)-1; // todo check this + rc.remainder = a; + } else { + rc.quotient = a/b; + rc.remainder = a%b; + } + return rc; +} + +// divides signed values a by b... (a/b) returned in low 32 bits, (a%b) in high 32 bits... results undefined for b==0 +static inline qr_s64 div64(int64_t a, int64_t b) { + qr_s64 rc; + if (!b) { + rc.quotient = (uint64_t)(-__sign_of_64(a)); + rc.remainder = a; + } else { + rc.quotient = a/b; + rc.remainder = a%b; + } + return rc; +} + +int64_t div_s64s64(int64_t a, int64_t b) { + qr_s64 qr = div64(a, b); + return qr.quotient; +} + +int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem) { + qr_s64 qr = div64(a, b); + *rem = qr.remainder; + return qr.quotient; +} + +int64_t divmod_s64s64(int64_t a, int64_t b) { + qr_s64 qr = div64(a, b); + return qr.quotient; +} + +uint64_t div_u64u64(uint64_t a, uint64_t b) { + qr_u64 qr = udiv64(a, b); + return qr.quotient; +} + +uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem) { + qr_u64 qr = udiv64(a, b); + *rem = qr.remainder; + return qr.quotient; +} + +uint64_t divmod_u64u64(uint64_t a, uint64_t b) { + qr_u64 qr = udiv64(a, b); + return qr.quotient; +} + +// these functions are slightly faster, but unsafe the divider state, so are not generally safe to be called from interrupts + +int32_t div_s32s32_unsafe(int32_t a, int32_t b) { return div_s32s32(a,b); } +int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem) { return divmod_s32s32_rem(a, b, rem); } +divmod_result_t divmod_s32s32_unsafe(int32_t a, int32_t b) { return divmod_s32s32(a, b); } + +uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b) { return div_u32u32(a, b); } +uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem) { return divmod_u32u32_rem(a, b, rem); } +divmod_result_t divmod_u32u32_unsafe(uint32_t a, uint32_t b) { return divmod_u32u32(a, b); } + +int64_t div_s64s64_unsafe(int64_t a, int64_t b) { return div_s64s64(a, b); } +int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem) { return divmod_s64s64_rem(a, b, rem); } +// todo this doesn't implement the contract +//int64_t divmod_s64s64_unsafe(int64_t a, int64_t b) { return divmod_s64s64(a, b); } + +uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b) { return div_u64u64(a, b); } +uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem) { return divmod_u64u64_rem(a, b, rem); } +// todo this doesn't implement the contract +//uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b) { return divmod_u64u64(a, b); } diff --git a/src/rp2_common/pico_divider/divider.S b/src/rp2_common/pico_divider/divider_hardware.S similarity index 98% rename from src/rp2_common/pico_divider/divider.S rename to src/rp2_common/pico_divider/divider_hardware.S index 493e39ddd..cb3f54162 100644 --- a/src/rp2_common/pico_divider/divider.S +++ b/src/rp2_common/pico_divider/divider_hardware.S @@ -8,6 +8,10 @@ #include "hardware/regs/addressmap.h" #include "hardware/divider_helper.S" +#if !HAS_SIO_DIVIDER +#warning "Building divider_hardware.S on a platform with no SIO divider hardware" +#endif + // PICO_CONFIG: PICO_DIVIDER_DISABLE_INTERRUPTS, Disable interrupts around division such that divider state need not be saved/restored in exception handlers, default=0, group=pico_divider // PICO_CONFIG: PICO_DIVIDER_CALL_IDIV0, Whether 32 bit division by zero should call __aeabi_idiv0, default=1, group=pico_divider @@ -53,7 +57,7 @@ pico_default_asm_setup // note we must read quotient last, and since it isn't the last reg, we'll not use ldmia! ldr r4, [r6, #SIO_DIV_UDIVIDEND_OFFSET] ldr r5, [r6, #SIO_DIV_UDIVISOR_OFFSET] - // No need to wait before reading result as long as preceeding code takes more than 8 cycles + // No need to wait before reading result as long as preceding code takes more than 8 cycles ldr r7, [r6, #SIO_DIV_REMAINDER_OFFSET] ldr r6, [r6, #SIO_DIV_QUOTIENT_OFFSET] .endm @@ -379,7 +383,7 @@ udiv0: .ltorg @ here y occupies more than 32 bits -@ split into cases acccording to the size of x +@ split into cases according to the size of x y64: cmp r3,#0 beq 1f diff --git a/src/rp2_common/pico_double/BUILD.bazel b/src/rp2_common/pico_double/BUILD.bazel index c9cba57af..5e5f73e30 100644 --- a/src/rp2_common/pico_double/BUILD.bazel +++ b/src/rp2_common/pico_double/BUILD.bazel @@ -1,88 +1,162 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel:defs.bzl", "compatible_with_rp2", "incompatible_with_config") package(default_visibility = ["//visibility:public"]) -cc_library( +_WRAP_DOUBLE_FLAGS = [ + "-Wl,--wrap=__aeabi_dadd", + "-Wl,--wrap=__aeabi_ddiv", + "-Wl,--wrap=__aeabi_dmul", + "-Wl,--wrap=__aeabi_drsub", + "-Wl,--wrap=__aeabi_dsub", + "-Wl,--wrap=__aeabi_cdcmpeq", + "-Wl,--wrap=__aeabi_cdrcmple", + "-Wl,--wrap=__aeabi_cdcmple", + "-Wl,--wrap=__aeabi_dcmpeq", + "-Wl,--wrap=__aeabi_dcmplt", + "-Wl,--wrap=__aeabi_dcmple", + "-Wl,--wrap=__aeabi_dcmpge", + "-Wl,--wrap=__aeabi_dcmpgt", + "-Wl,--wrap=__aeabi_dcmpun", + "-Wl,--wrap=__aeabi_i2d", + "-Wl,--wrap=__aeabi_l2d", + "-Wl,--wrap=__aeabi_ui2d", + "-Wl,--wrap=__aeabi_ul2d", + "-Wl,--wrap=__aeabi_d2iz", + "-Wl,--wrap=__aeabi_d2lz", + "-Wl,--wrap=__aeabi_d2uiz", + "-Wl,--wrap=__aeabi_d2ulz", + "-Wl,--wrap=__aeabi_d2f", + "-Wl,--wrap=sqrt", + "-Wl,--wrap=cos", + "-Wl,--wrap=sin", + "-Wl,--wrap=tan", + "-Wl,--wrap=atan2", + "-Wl,--wrap=exp", + "-Wl,--wrap=log", + "-Wl,--wrap=ldexp", + "-Wl,--wrap=copysign", + "-Wl,--wrap=trunc", + "-Wl,--wrap=floor", + "-Wl,--wrap=ceil", + "-Wl,--wrap=round", + "-Wl,--wrap=sincos", + "-Wl,--wrap=asin", + "-Wl,--wrap=acos", + "-Wl,--wrap=atan", + "-Wl,--wrap=sinh", + "-Wl,--wrap=cosh", + "-Wl,--wrap=tanh", + "-Wl,--wrap=asinh", + "-Wl,--wrap=acosh", + "-Wl,--wrap=atanh", + "-Wl,--wrap=exp2", + "-Wl,--wrap=log2", + "-Wl,--wrap=exp10", + "-Wl,--wrap=log10", + "-Wl,--wrap=pow", + "-Wl,--wrap=powint", + "-Wl,--wrap=hypot", + "-Wl,--wrap=cbrt", + "-Wl,--wrap=fmod", + "-Wl,--wrap=drem", + "-Wl,--wrap=remainder", + "-Wl,--wrap=remquo", + "-Wl,--wrap=expm1", + "-Wl,--wrap=log1p", + "-Wl,--wrap=fma", +] + +alias( name = "pico_double", + actual = select({ + "//bazel/constraint:pico_double_auto_enabled": ":pico_double_auto", + "//bazel/constraint:pico_double_compiler_enabled": ":pico_double_auto", + "//bazel/constraint:pico_double_dcp_enabled": ":pico_double_pico", + "//bazel/constraint:pico_double_rp2040_enabled": ":pico_double_pico", + "//conditions:default": ":pico_double_none", + }), +) + +alias( + name = "pico_double_auto", + actual = select({ + "@platforms//cpu:riscv32": ":pico_double_compiler", + "//bazel/constraint:rp2040": ":pico_double_pico", + "//conditions:default": ":pico_double_dcp", + }), +) + +# An empty stub that just lets the compiler handle the implementation. +cc_library( + name = "pico_double_compiler", + hdrs = ["include/pico/double.h"], + defines = ["PICO_DOUBLE_COMPILER=1"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), +) + +cc_library( + name = "pico_double_pico", srcs = [ - "double_aeabi.S", - "double_init_rom.c", + "double_aeabi_rp2040.S", + "double_init_rom_rp2040.c", "double_math.c", - "double_v1_rom_shim.S", + "double_v1_rom_shim_rp2040.S", ], hdrs = ["include/pico/double.h"], + defines = ["LIB_PICO_DOUBLE_PICO=1"], includes = ["include"], - linkopts = [ - "-Wl,--wrap=__aeabi_dadd", - "-Wl,--wrap=__aeabi_ddiv", - "-Wl,--wrap=__aeabi_dmul", - "-Wl,--wrap=__aeabi_drsub", - "-Wl,--wrap=__aeabi_dsub", - "-Wl,--wrap=__aeabi_cdcmpeq", - "-Wl,--wrap=__aeabi_cdrcmple", - "-Wl,--wrap=__aeabi_cdcmple", - "-Wl,--wrap=__aeabi_dcmpeq", - "-Wl,--wrap=__aeabi_dcmplt", - "-Wl,--wrap=__aeabi_dcmple", - "-Wl,--wrap=__aeabi_dcmpge", - "-Wl,--wrap=__aeabi_dcmpgt", - "-Wl,--wrap=__aeabi_dcmpun", - "-Wl,--wrap=__aeabi_i2d", - "-Wl,--wrap=__aeabi_l2d", - "-Wl,--wrap=__aeabi_ui2d", - "-Wl,--wrap=__aeabi_ul2d", - "-Wl,--wrap=__aeabi_d2iz", - "-Wl,--wrap=__aeabi_d2lz", - "-Wl,--wrap=__aeabi_d2uiz", - "-Wl,--wrap=__aeabi_d2ulz", - "-Wl,--wrap=__aeabi_d2f", - "-Wl,--wrap=sqrt", - "-Wl,--wrap=cos", - "-Wl,--wrap=sin", - "-Wl,--wrap=tan", - "-Wl,--wrap=atan2", - "-Wl,--wrap=exp", - "-Wl,--wrap=log", - "-Wl,--wrap=ldexp", - "-Wl,--wrap=copysign", - "-Wl,--wrap=trunc", - "-Wl,--wrap=floor", - "-Wl,--wrap=ceil", - "-Wl,--wrap=round", - "-Wl,--wrap=sincos", - "-Wl,--wrap=asin", - "-Wl,--wrap=acos", - "-Wl,--wrap=atan", - "-Wl,--wrap=sinh", - "-Wl,--wrap=cosh", - "-Wl,--wrap=tanh", - "-Wl,--wrap=asinh", - "-Wl,--wrap=acosh", - "-Wl,--wrap=atanh", - "-Wl,--wrap=exp2", - "-Wl,--wrap=log2", - "-Wl,--wrap=exp10", - "-Wl,--wrap=log10", - "-Wl,--wrap=pow", - "-Wl,--wrap=powint", - "-Wl,--wrap=hypot", - "-Wl,--wrap=cbrt", - "-Wl,--wrap=fmod", - "-Wl,--wrap=drem", - "-Wl,--wrap=remainder", - "-Wl,--wrap=remquo", - "-Wl,--wrap=expm1", - "-Wl,--wrap=log1p", - "-Wl,--wrap=fma", + linkopts = _WRAP_DOUBLE_FLAGS, + target_compatible_with = compatible_with_rp2() + incompatible_with_config("@platforms//cpu:riscv32") + ["//bazel/constraint:rp2040"], + visibility = ["//visibility:private"], + deps = [ + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_divider", + "//src/rp2_common/pico_bootrom", ], - target_compatible_with = compatible_with_rp2(), + alwayslink = True, # Ensures the wrapped symbols are linked in. +) + +cc_library( + name = "pico_double_dcp", + srcs = [ + "double_aeabi_dcp.S", + "double_conv_m33.S", + "double_fma_dcp.S", + "double_math.c", + "double_sci_m33.S", + ], + hdrs = ["include/pico/double.h"], + defines = ["LIB_PICO_DOUBLE_PICO=1"], + includes = ["include"], + linkopts = _WRAP_DOUBLE_FLAGS, + target_compatible_with = compatible_with_rp2() + incompatible_with_config("@platforms//cpu:riscv32") + incompatible_with_config("//bazel/constraint:rp2040"), + visibility = ["//visibility:private"], deps = [ - "//src/common/pico_base", + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_dcp", "//src/rp2_common/hardware_divider", "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) -# TODO: Support double_none.S when the configuration option exists. +cc_library( + name = "pico_double_none", + srcs = ["double_none.S"], + hdrs = ["include/pico/double.h"], + defines = [ + "LIB_PICO_DOUBLE_PICO=0", + "PICO_PRINTF_SUPPORT_FLOAT=0", + ], + includes = ["include"], + linkopts = _WRAP_DOUBLE_FLAGS, + target_compatible_with = compatible_with_rp2(), + visibility = ["//visibility:private"], + deps = [ + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_divider", + "//src/rp2_common/pico_bootrom", + ], + alwayslink = True, # Ensures the wrapped symbols are linked in. +) diff --git a/src/rp2_common/pico_double/CMakeLists.txt b/src/rp2_common/pico_double/CMakeLists.txt index 8c093e727..5fe456304 100644 --- a/src/rp2_common/pico_double/CMakeLists.txt +++ b/src/rp2_common/pico_double/CMakeLists.txt @@ -5,24 +5,41 @@ if (NOT TARGET pico_double) # no custom implementation; falls thru to compiler pico_add_library(pico_double_compiler) - target_include_directories(pico_double_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_double_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) # add alias "default" which is just pico. add_library(pico_double_default INTERFACE) - target_link_libraries(pico_double_default INTERFACE pico_double_pico) + if (PICO_RISCV) + target_link_libraries(pico_double_default INTERFACE pico_double_compiler) + else() + target_link_libraries(pico_double_default INTERFACE pico_double_pico) + endif() - set(PICO_DEFAULT_DOUBLE_IMPL pico_double_default) + if (NOT PICO_DEFAULT_DOUBLE_IMPL) + set(PICO_DEFAULT_DOUBLE_IMPL pico_double_default) + endif() target_link_libraries(pico_double INTERFACE $>,$,${PICO_DEFAULT_DOUBLE_IMPL}>) + # todo maybe this should be pico_double_dcp (note FreeRTOS has a dependency on the LIB_PICO_DOUBLE_FOO) pico_add_library(pico_double_pico) - target_sources(pico_double_pico INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/double_aeabi.S - ${CMAKE_CURRENT_LIST_DIR}/double_init_rom.c - ${CMAKE_CURRENT_LIST_DIR}/double_math.c - ${CMAKE_CURRENT_LIST_DIR}/double_v1_rom_shim.S - ) + if (PICO_RP2040) + target_sources(pico_double_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/double_aeabi_rp2040.S + ${CMAKE_CURRENT_LIST_DIR}/double_init_rom_rp2040.c + ${CMAKE_CURRENT_LIST_DIR}/double_math.c + ${CMAKE_CURRENT_LIST_DIR}/double_v1_rom_shim_rp2040.S + ) + elseif(NOT PICO_RISCV) + target_sources(pico_double_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/double_math.c + ${CMAKE_CURRENT_LIST_DIR}/double_aeabi_dcp.S + ${CMAKE_CURRENT_LIST_DIR}/double_fma_dcp.S + ${CMAKE_CURRENT_LIST_DIR}/double_sci_m33.S + ${CMAKE_CURRENT_LIST_DIR}/double_conv_m33.S + ) + endif() target_link_libraries(pico_double_pico INTERFACE pico_bootrom pico_double_headers hardware_divider) diff --git a/src/rp2_common/pico_double/double_aeabi_dcp.S b/src/rp2_common/pico_double/double_aeabi_dcp.S new file mode 100644 index 000000000..9579c70e4 --- /dev/null +++ b/src/rp2_common/pico_double/double_aeabi_dcp.S @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" + +#if !HAS_DOUBLE_COPROCESSOR +#error attempt to compile double_aeabi_rp2350 when there is no DCP +#else + +#include "hardware/dcp_instr.inc.S" +#include "hardware/dcp_canned.inc.S" + +pico_default_asm_setup + +.macro double_section name +#if PICO_DOUBLE_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro double_wrapper_section func +double_section WRAPPER_FUNC_NAME(\func) +.endm + +// ============== STATE SAVE AND RESTORE =============== + +.macro saving_func type func + // Note we are usually 32-bit aligned already at this point, as most of the + // function bodies contain exactly two 16-bit instructions: bmi and bx lr. + // We want the PCMP word-aligned. +.p2align 2 + // When the engaged flag is set, branch back here to invoke save routine and + // hook lr with the restore routine, then fall back through to the entry + // point. The engaged flag will be clear when checked a second time. +1: + push {lr} // 16-bit instruction + bl generic_save_state // 32-bit instruction + b 1f // 16-bit instruction + // This is the actual entry point: +\type\()_func \func + PCMP apsr_nzcv + bmi 1b +1: +.endm + +.macro saving_func_return + bx lr +.endm + +double_section __rp2350_dcp_engaged_state_save_restore +.thumb_func +generic_save_state: + sub sp, #24 + push {r0, r1} + // do save here + PXMD r0, r1 + strd r0, r1, [sp, #8 + 0] + PYMD r0, r1 + strd r0, r1, [sp, #8 + 8] + REFD r0, r1 + strd r0, r1, [sp, #8 + 16] + pop {r0, r1} + blx lr + // <- wrapped function returns here + // fall through into restore: +.thumb_func +generic_restore_state: + // do restore here + pop {r12, r14} + WXMD r12, r14 + pop {r12, r14} + WYMD r12, r14 + pop {r12, r14} + WEFD r12, r14 + pop {pc} + +// ============== ARITHMETIC FUNCTIONS =============== + +double_wrapper_section __aeabi_dadd +saving_func wrapper __aeabi_dadd + dcp_dadd_m r0,r1,r0,r1,r2,r3 + saving_func_return + +double_wrapper_section __aeabi_dsub +saving_func wrapper __aeabi_dsub + dcp_dsub_m r0,r1,r0,r1,r2,r3 + saving_func_return + +double_wrapper_section __aeabi_drsub +saving_func wrapper __aeabi_drsub + dcp_dsub_m r0,r1,r2,r3,r0,r1 + saving_func_return + +double_wrapper_section __aeabi_dmul +saving_func wrapper __aeabi_dmul + + // todo optimize this based on final decision on saving_func_entry + push {r4,r14} + dcp_dmul_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r4,r12,r14 + // todo optimize this based on final decision on saving_func_entry + pop {r4,lr} + saving_func_return + +double_section ddiv_fast +saving_func regular ddiv_fast + dcp_ddiv_fast_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r12 + saving_func_return + +double_wrapper_section __aeabi_ddiv +saving_func wrapper __aeabi_ddiv +@ with correct rounding + dcp_ddiv_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r12 + saving_func_return + +double_section sqrt_fast +saving_func regular sqrt_fast + dcp_dsqrt_fast_m r0,r1,r0,r1,r0,r1,r2,r3,r12 + saving_func_return + +double_wrapper_section sqrt +saving_func wrapper sqrt +@ with correct rounding + dcp_dsqrt_m r0,r1,r0,r1,r0,r1,r2,r3,r12 + saving_func_return + +// todo not a real thing +double_wrapper_section __aeabi_dclassify +saving_func wrapper __aeabi_dclassify +@ with correct rounding + dcp_dclassify_m apsr_nzcv,r0,r1 + saving_func_return + +// ============== CONVERSION FUNCTIONS =============== + +double_wrapper_section __aeabi_d2f +saving_func wrapper __aeabi_d2f +@ with rounding + dcp_double2float_m r0,r0,r1 + saving_func_return + +double_wrapper_section __aeabi_i2d +saving_func wrapper __aeabi_i2d + dcp_int2double_m r0,r1,r0 + saving_func_return + +double_wrapper_section __aeabi_ui2d +saving_func wrapper __aeabi_ui2d + dcp_uint2double_m r0,r1,r0 + saving_func_return + +double_wrapper_section __aeabi_d2iz +saving_func wrapper __aeabi_d2iz +@ with truncation towards 0 + dcp_double2int_m r0,r0,r1 + saving_func_return + +double_wrapper_section __aeabi_d2uiz +saving_func wrapper __aeabi_d2uiz +@ with truncation towards 0 + dcp_double2uint_m r0,r0,r1 + saving_func_return + +// todo not a real thing +double_wrapper_section __aeabi_d2i_r +saving_func wrapper __aeabi_d2i_r +@ with rounding + dcp_double2int_r_m r0,r0,r1 + saving_func_return + +// todo not a real thing +double_wrapper_section __aeabi_d2ui_r +saving_func wrapper __aeabi_d2ui_r +@ with rounding + dcp_double2uint_r_m r0,r0,r1 + saving_func_return + +// ============== COMPARISON FUNCTIONS =============== + +double_wrapper_section __aeabi_dcmpun +saving_func wrapper __aeabi_dcmpun + dcp_dcmp_m r0,r0,r1,r2,r3 + // extract unordered bit + ubfx r0, r0, #28, #1 + saving_func_return + +double_wrapper_section __aeabi_dcmp + +saving_func wrapper __aeabi_cdrcmple + dcp_dcmp_m apsr_nzcv,r2,r3,r0,r1 // with arguments reversed + bvs cmp_nan + saving_func_return + +// these next two can be the same function in the absence of exceptions +saving_func wrapper __aeabi_cdcmple +//wrapper_func __aeabi_dcmp + dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 + bvs cmp_nan + saving_func_return + +// It is not clear from the ABI documentation whether cdcmpeq must set the C flag +// in the same way as cdcmple. If not, we could save the "bvs" below; but we +// err on the side of caution. +saving_func wrapper __aeabi_cdcmpeq +//wrapper_func __aeabi_dcmp + dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 + bvs cmp_nan + saving_func_return + +// If the result of a flag-setting comparison is "unordered" then we need to set C and clear Z. +// We could conceivably just do lsrs r12,r14,#1, or even cmp r14,r14,lsr#1 as (a) r14 here is a +// return address and r14b0=1 for Thumb mode; (b) we are unlikely to be returning to address 0. +cmp_nan: + movs r12, #3 // r12 does not need to be preserved by the flag-setting comparisons + lsrs r12, #1 // set C, clear Z + saving_func_return + +// int FUNC_NAME(__aeabi_dcmpeq)(double, double) result (1, 0) denotes (=, ?<>) [2], use for C == and != +double_wrapper_section __aeabi_dcmpeq +saving_func wrapper __aeabi_dcmpeq + dcp_dcmp_m r0,r0,r1,r2,r3 + // extract Z + ubfx r0, r0, #30, #1 + saving_func_return + +// int FUNC_NAME(__aeabi_dcmplt)(double, double) result (1, 0) denotes (<, ?>=) [2], use for C < +double_wrapper_section __aeabi_dcmplt +saving_func wrapper __aeabi_dcmplt + dcp_dcmp_m apsr_nzcv,r2,r3,r0,r1 + ite hi + movhi r0,#1 + movls r0,#0 + saving_func_return + +// int FUNC_NAME(__aeabi_dcmple)(double, double) result (1, 0) denotes (<=, ?>) [2], use for C <= +double_wrapper_section __aeabi_dcmple +saving_func wrapper __aeabi_dcmple + dcp_dcmp_m apsr_nzcv,r2,r3,r0,r1 + ite hs + movhs r0,#1 + movlo r0,#0 + saving_func_return + +// int FUNC_NAME(__aeabi_dcmpge)(double, double) result (1, 0) denotes (>=, ?<) [2], use for C >= +double_wrapper_section __aeabi_dcmpge +saving_func wrapper __aeabi_dcmpge + dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 + ite hs + movhs r0,#1 + movlo r0,#0 + saving_func_return + +// int FUNC_NAME(__aeabi_dcmpgt)(double, double) result (1, 0) denotes (>, ?<=) [2], use for C > +double_wrapper_section __aeabi_dcmpgt +saving_func wrapper __aeabi_dcmpgt + dcp_dcmp_m apsr_nzcv,r0,r1,r2,r3 + ite hi + movhi r0,#1 + movls r0,#0 + saving_func_return + +#endif diff --git a/src/rp2_common/pico_double/double_aeabi.S b/src/rp2_common/pico_double/double_aeabi_rp2040.S similarity index 99% rename from src/rp2_common/pico_double/double_aeabi.S rename to src/rp2_common/pico_double/double_aeabi_rp2040.S index 8b0afb4bf..284846fd9 100644 --- a/src/rp2_common/pico_double/double_aeabi.S +++ b/src/rp2_common/pico_double/double_aeabi_rp2040.S @@ -4,13 +4,15 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#if PICO_RP2040 #include "pico/asm_helper.S" +#include "pico/runtime_init.h" #include "pico/bootrom/sf_table.h" #include "hardware/divider_helper.S" pico_default_asm_setup -__pre_init __aeabi_double_init, 00020 +PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_double_init, PICO_RUNTIME_INIT_AEABI_DOUBLE) .macro double_section name #if PICO_DOUBLE_IN_RAM @@ -842,3 +844,4 @@ double_wrapper_section log wrapper_func_d1 log shimmable_table_tail_call SF_TABLE_FLN dln_shim +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_double/double_conv_m33.S b/src/rp2_common/pico_double/double_conv_m33.S new file mode 100644 index 000000000..606cbfc30 --- /dev/null +++ b/src/rp2_common/pico_double/double_conv_m33.S @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#if HAS_DOUBLE_COPROCESSOR + +pico_default_asm_setup + +.macro double_section name +#if PICO_DOUBLE_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro double_wrapper_section func +double_section WRAPPER_FUNC_NAME(\func) +.endm + +double_wrapper_section conv_tod + +@ convert int64 to double, rounding +wrapper_func __aeabi_l2d +regular_func int642double + movs r2,#0 @ fall through +@ convert unsigned 64-bit fix to double, rounding; number of r0:r1 bits after point in r2 +regular_func fix642double + cmp r1,#0 + bge 10f @ positive? can use unsigned code + rsbs r0,#0 + sbc r1,r1,r1,lsl#1 @ make positive + cbz r1,7f @ high word is zero? + clz r3,r1 + subs r3,#11 + bmi 2f + rsbs r12,r3,#32 + lsrs r12,r0,r12 + lsls r0,r3 + lsls r1,r3 + orrs r1,r1,r12 + add r2,r2,r3 + rsbs r2,#0 + add r2,#0x3ff+19+32 + add r1,r1,r2,lsl#20 @ insert exponent + orr r1,#0x80000000 + mov r3,0x7fe + cmp r2,r3 + it lo @ over/underflow? + bxlo r14 + b 3f +7: + mov r1,r2 + b fix2double_neg +2: + add r3,#33 + lsls r12,r0,r3 @ rounding bit in carry, sticky bits in Z + sub r3,#1 + lsl r12,r1,r3 + rsb r3,#32 + lsr r0,r3 + lsr r1,r3 + orr r0,r0,r12 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r2 + add r2,#0x3ff+19+32 + beq 4f @ potential rounding tie? + adcs r0,r0,#0 +5: + adc r1,r1,r2,lsl#20 @ insert exponent, add rounding + orr r1,#0x80000000 + mov r3,0x7fe + cmp r2,r3 + it lo + bxlo r14 +@ over/underflow? +3: + mov r1,#0 + it ge + movtge r1,#0x7ff0 @ overflow + mov r0,#0 + bx r14 +1: + movs r1,#0 + bx r14 +4: + bcc 5b @ not a rounding tie after all + adcs r0,r0,#0 + bic r0,r0,#1 @ force to even + b 5b + +@ convert uint64 to double, rounding +wrapper_func __aeabi_ul2d +regular_func uint642double + movs r2,#0 @ fall through +@ convert unsigned 64-bit fix to double, rounding; number of r0:r1 bits after point in r2 +regular_func ufix642double +10: + cbz r1,7f @ high word zero? + clz r3,r1 + subs r3,#11 + bmi 2f + rsbs r12,r3,#32 + lsrs r12,r0,r12 + lsls r0,r3 + lsls r1,r3 + orrs r1,r1,r12 + add r2,r2,r3 + rsbs r2,#0 + add r2,#0x3ff+19+32 + add r1,r1,r2,lsl#20 @ insert exponent + mov r3,0x7fe + cmp r2,r3 + it lo @ over/underflow? + bxlo r14 + b 3f +7: + mov r1,r2 + b ufix2double +2: + add r3,#33 + lsls r12,r0,r3 @ rounding bit in carry, sticky bits in Z + sub r3,#1 + lsl r12,r1,r3 + rsb r3,#32 + lsr r0,r3 + lsr r1,r3 + orr r0,r0,r12 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r2 + add r2,#0x3ff+19+32 + beq 4f @ potential rounding tie? + adcs r0,r0,#0 +5: + adc r1,r1,r2,lsl#20 @ insert exponent, add rounding + mov r3,0x7fe + cmp r2,r3 + it lo + bxlo r14 +@ over/underflow? +3: + mov r1,#0 + it ge + movtge r1,#0x7ff0 @ overflow + mov r0,#0 + bx r14 +1: + movs r1,#0 + bx r14 +4: + bcc 5b @ not a rounding tie after all + adcs r0,r0,#0 + bic r0,r0,#1 @ force to even + b 5b + +regular_func fix2double + cmp r0,#0 + bge ufix2double @ positive? can use unsigned code + rsbs r0,#0 @ make positive +fix2double_neg: + clz r3,r0 + subs r3,#11 + bmi 2f + lsls r0,r3 + add r2,r1,r3 + rsbs r2,#0 + add r2,#0x3ff+19 + add r1,r0,r2,lsl#20 @ insert exponent + orr r1,#0x80000000 + mov r0,#0 + mov r3,0x7fe + cmp r2,r3 + it lo @ over/underflow? + bxlo r14 + b 3f +2: + rsb r3,#0 + lsrs r12,r0,r3 + rsb r2,r3,#32 + lsls r0,r0,r2 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r1 + add r2,#0x3ff+19 + add r1,r12,r2,lsl#20 @ insert exponent + orr r1,#0x80000000 + mov r3,0x7fe + cmp r2,r3 + it lo + bxlo r14 +@ over/underflow? +3: + mov r1,#0x80000000 + it ge + movtge r1,#0xfff0 @ overflow + mov r0,#0 + bx r14 +1: + movs r1,#0 + bx r14 + +regular_func ufix2double + cbz r0,1f @ zero? return it + clz r3,r0 + subs r3,#11 + bmi 2f + lsls r0,r3 + add r2,r1,r3 + rsbs r2,#0 + add r2,#0x3ff+19 + add r1,r0,r2,lsl#20 @ insert exponent + mov r0,#0 + mov r3,0x7fe + cmp r2,r3 + it lo @ over/underflow? + bxlo r14 + b 3f +2: + rsbs r3,#0 + lsrs r12,r0,r3 + rsb r2,r3,#32 + lsls r0,r0,r2 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r1 + add r2,#0x3ff+19 + add r1,r12,r2,lsl#20 @ insert exponent + mov r3,0x7fe + cmp r2,r3 + it lo + bxlo r14 +@ over/underflow? +3: + mov r1,#0 + it ge + movtge r1,#0x7ff0 @ overflow + mov r0,#0 + bx r14 +1: + movs r1,#0 + bx r14 + +double_wrapper_section conv_dtoi64 + +@ convert double to signed int64, rounding towards 0, clamping +wrapper_func __aeabi_d2lz +regular_func double2int64_z + movs r2,#0 @ fall through +@ convert double in r0:r1 to signed fixed point in r0:r1, clamping +regular_func double2fix64_z + sub r2,#0x3ff+52-1 @ remove exponent bias, compensate for mantissa length + asrs r12,r1,#20 @ sign and exponent + sub r3,r12,#1 + sub r1,r1,r3,lsl#20 @ install implied 1, clear exponent + lsls r3,#21 +@ push {r14} +@ bl dumpreg +@ pop {r14} + cmp r3,#0xffc00000 + bhs 1f @ 0, ∞/NaN? + adds r2,r2,r3,lsr#21 @ offset exponent by fix precision; r1 is now required left shift + bmi 4f @ actually a right shift? + cmp r2,#11 @ overflow? + bge 5f + lsls r1,r2 + rsbs r3,r2,#32 + lsrs r3,r0,r3 + orrs r1,r1,r3 + lsls r0,r2 + cmp r12,#0 + it ge + bxge r14 + rsbs r0,#0 + sbc r1,r1,r1,lsl#1 + bx r14 +4: + adds r2,#32 + ble 6f @ result fits in low word? + lsl r3,r1,r2 + rsbs r2,#32 + lsrs r1,r2 + lsrs r0,r2 + orrs r0,r0,r3 + cmp r12,#0 + it ge + bxge r14 + rsbs r0,#0 + sbc r1,r1,r1,lsl#1 + bx r14 +6: + rsbs r2,#0 + usat r2,#5,r2 @ underflow to 0 + lsrs r0,r1,r2 + movs r1,#0 + cmp r12,#0 + it ge + bxge r14 + rsbs r0,#0 + sbc r1,r1,r1,lsl#1 + bx r14 +1: + beq 3f @ ±∞/±NaN? +2: + movs r0,#0 @ ±0: return 0 + movs r1,#0 + bx r14 +3: + orrs r1,r0,r1,lsl#12 @ mantissa field + it ne @ NaN? + movne r12,#0 @ treat NaNs as +∞ +@ here original argument was ±Inf or we have under/overflow +5: + mvn r1,#0x80000000 + add r1,r1,r12,lsr#31 @ so -Inf → 0x80000000, +Inf → 0x7fffffff + mvn r0,r12,asr#31 + bx r14 + +double_wrapper_section conv_dtoui64 + +@ convert double to unsigned int64, rounding towards -Inf, clamping +wrapper_func __aeabi_d2ulz +regular_func double2uint64 +regular_func double2uint64_z + movs r2,#0 @ fall through +@ convert double in r0:r1 to unsigned fixed point in r0:r1, clamping +regular_func double2ufix64 +regular_func double2ufix64_z + subw r2,r2,#0x3ff+52-1 @ remove exponent bias, compensate for mantissa length + asrs r3,r1,#20 @ sign and exponent + sub r3,#1 + sub r1,r1,r3,lsl#20 @ install implied 1, clear exponent and sign + bmi 7f @ argument negative? + movw r12,#0x7fe + cmp r3,r12 + bhs 1f @ 0, ∞/NaN? + adds r2,r3 @ offset exponent by fix precision; r2 is now required left shift + bmi 2f @ actually a right shift? + cmp r2,#12 @ overflow? + bge 4f + lsls r1,r2 + rsbs r3,r2,#32 + lsrs r3,r0,r3 + lsls r0,r2 + orrs r1,r1,r3 + bx r14 +2: + adds r2,#32 + ble 5f @ result fits in low word? + lsl r3,r1,r2 + rsbs r2,#32 + lsrs r1,r2 + lsrs r0,r2 + orrs r0,r0,r3 + bx r14 +5: + rsbs r2,#0 + usat r2,#5,r2 @ underflow to 0 + lsrs r0,r1,r2 + movs r1,#0 + bx r14 +1: + bhi 3f @ 0? return 0 +4: +@ here overflow has occurred + mvn r0,#0 + mvn r1,#0 + bx r14 +7: + cmp r3,#0xfffffffe + bne 3f @ -0? return 0 + orrs r2,r0,r1,lsl#12 @ mantissa field + bne 4b +3: + movs r0,#0 + movs r1,#0 + bx r14 + +#endif diff --git a/src/rp2_common/pico_double/double_fma_dcp.S b/src/rp2_common/pico_double/double_fma_dcp.S new file mode 100644 index 000000000..30f669bd9 --- /dev/null +++ b/src/rp2_common/pico_double/double_fma_dcp.S @@ -0,0 +1,608 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" + +#if !HAS_DOUBLE_COPROCESSOR +#error attempt to compile double_fma_rp2350 when there is no DCP +#else + +#include "hardware/dcp_instr.inc.S" +#include "hardware/dcp_canned.inc.S" + +pico_default_asm_setup + +// factor out save/restore (there is a copy in float code) + +.macro double_section name +#if PICO_DOUBLE_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro double_wrapper_section func +double_section WRAPPER_FUNC_NAME(\func) +.endm + +// ============== STATE SAVE AND RESTORE =============== + +.macro saving_func_return + bx lr +.endm + +double_section __rp2350_dcp_engaged_state_save_restore_copy +.thumb_func +__dcp_save_state: + sub sp, #24 + push {r0, r1} + // do save here + PXMD r0, r1 + strd r0, r1, [sp, #8 + 0] + PYMD r0, r1 + strd r0, r1, [sp, #8 + 8] + REFD r0, r1 + strd r0, r1, [sp, #8 + 16] + pop {r0, r1} + blx lr + // <- wrapped function returns here + // fall through into restore: +.thumb_func +__dcp_restore_state: + // do restore here + pop {r12, r14} + WXMD r12, r14 + pop {r12, r14} + WYMD r12, r14 + pop {r12, r14} + WEFD r12, r14 + pop {pc} + +double_wrapper_section __dfma +@ cf saving_func macro: but here we need to record the SP before the state save possibly changes it +1: + push {lr} // 16-bit instruction + bl __dcp_save_state // 32-bit instruction + b 1f // 16-bit instruction + +@ compute mn+a with full intermediate precision +@ r0:r1 m +@ r2:r3 n +@ [r13,#0] a +wrapper_func fma + mov r12,sp @ save the SP + PCMP apsr_nzcv @ test the engaged flag + bmi 1b +1: + push {r4-r8,r14} + ldrd r4,r5,[r12,#0] @ fetch a using original SP + ubfx r7,r1,#20,#11 @ r7=em + ubfx r8,r3,#20,#11 @ r8=en + add r8,r7,r8 @ em+en + + eors r6,r1,r3 @ get sign of mn + eors r6,r6,r5 @ set N if mn has opposite sign to a, i.e. if the operation is essentially a subtraction + WXUP r4,r5 @ write a to coprocessor to get its classification + PEFD r14,r12 @ r14=fa + WXUP r0,r1 @ write m and n to coprocessor to get their classifications + WYUP r2,r3 + PEFD r6,r12 @ r6=fm, r12=fn, r14=fa + orr r14,r14,r6 + orr r14,r14,r12 @ OR of all the classification flags, so we can check if any are zero/Inf/NaN + + RXMS r3,r6,0 @ we will almost always need the full product so compute it here (cf dmul macro) + RYMS r7,r12,0 + umull r0,r1,r3,r7 + mov r2,#0 @ seems to be no 16-bit instruction which zeros a register without affecting the flags + umlal r1,r2,r3,r12 + umlal r1,r2,r6,r7 + mov r3,#0 + umlal r2,r3,r6,r12 @ r0:r1:r2:r3: full product mn Q124 1≤mn<4 + + bmi 50f @ mn has opposite sign to a so operation is essentially a subtraction + +@ ======================== ADDITION PATH ======================== + + tst r14,#0x70000000 @ were any of the arguments zero/inf/NaN? + bne 90f @ then use mla path which gives the correct result in all these cases + ubfx r14,r5,#20,#11 @ r14=ea +@ here all operands are finite and non-zero +@ r0:r1:r2:r3: full product mn Q124 1≤mn<4 +@ r4:r5 a IEEE packed +@ r8: em+en [biased +0x3ff*2] +@ r14: ea [biased +0x3ff] + subw r7,r8,#0x3fd + subs r7,r7,r14 @ em+en-ea+2 (debiased) + blt 80f @ branch if |a| is big compared to |mn|, more precisely if ea-(em+en)≥3 so e.g. if ea=0 (hence 1≤a<2) then em+en≤-3 and mn<4.2¯³=1/2 + +@ ======================== ADDITION PATH, RESULT HAS COMPARABLE MAGNITUDE TO mn ======================== + +@ here |mn| is big compared to |a|; e.g. if em+en=0 (so 1≤mn<4) then ea≤2 and a<8 + movs r8,#1 + bfi r5,r8,#20,#12 @ insert implied 1 in a + rsbs r7,r7,#74 @ shift up ≤74 (can be negative) that will be required for a (Q52) to align with mn (Q124, ending in 20 zeros) +@ now add (shifted) a into mn, preserving flags + and r8,r7,#0x1f @ k=shift mod 32 + mov r12,#1 + lsl r12,r12,r8 @ 2^k + umull r5,r6,r5,r12 @ shift up high word: r4:r5:r6 is now a_lo + 2^k a_hi + sub r12,#1 @ 2^k-1 + umlal r4,r5,r4,r12 @ shift up low word, adding in: r4:r5:r6 is now (a_lo + 2^k a_hi) + (2^k-1) a_lo = 2^k (a_lo + a_hi) = a shifted up by k + bmi 91f @ use flags: will a be shifted down? + cmp r7,#64 @ shift up by two more words? + bge 92f + cmp r7,#32 @ shift up by one more word? + bge 93f + adds r0,r0,r4 @ no more word shifts + adcs r1,r1,r5 + adcs r2,r2,r6 + adcs r3,r3,#0 @ r0:r1:r2:r3: mn + a (cf dmul macro) + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD @ as dmul macro tail: exponent computed in coprocessor is correct + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +93: + adds r1,r1,r4 + adcs r2,r2,r5 + adcs r3,r3,r6 @ r0:r1:r2:r3: mn + (a<<32) + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +92: + adds r2,r2,r4 + adcs r3,r3,r5 @ r0:r1:r2:r3: mn + (a<<64); note this cannot overflow as total shift was at most 74 (see above) + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +91: @ case where a (Q52) is shifted down relative to mn (Q124); the mod 32 part of the shift of a has already been done +@ r0:r1:r2:r3: mn +@ r4:r5:r6: a +@ r7: alignment shift required (negative) + cmn r7,#32 @ shift down one word? + bge 94f + cmn r7,#64 @ shift down two words? + bge 95f +@ here a is shifted entirely below the bottom of m + orr r0,r0,#1 @ a is non-zero so ensure we set the sticky bit + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +94: + adds r0,r0,r5 @ one word shift down + adcs r1,r1,r6 + adcs r2,r2,#0 + adcs r3,r3,#0 + orr r0,r0,r4 @ contribution from a to sticky bits + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +95: + adds r0,r0,r6 @ two word shift down + adcs r1,r1,#0 + adcs r2,r2,#0 + adcs r3,r3,#0 + orr r0,r0,r4 @ contribution from a to sticky bits + orr r0,r0,r5 + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +@ ======================== ADDITION PATH, RESULT HAS COMPARABLE MAGNITUDE TO a ======================== + +80: +@ here |mn|<~|a| +@ r0:r1:r2:r3: mn Q124 +@ r4:r5 a IEEE packed +@ r7: -(shift down required to align mn with a), guaranteed negative +@ r8: em+en [biased +0x3ff*2] +@ r14: ea [biased +0x3ff] + tst r3,#0x20000000 + bne 1f @ 2≤mn<4? + adds r2,r2,r2 @ normalise so mn is 2..4 Q124; note that the contents of r0 and r1 are always destined for the sticky bit in this path + adcs r3,r3,r3 + subs r7,r7,#1 @ correction to alignment shift +1: +@ now we construct an IEEE packed value in r2:r3 such that adding it to r4:r5 gives the correct final result +@ observe that the exponent of this constructed value will be at least two less than that of a (by the "|a| is big compared to |mn|" test above) +@ so the alignment shift in the final addition will be by at least two places; thus we can use bit 0 of the constructed +@ value as a sticky bit, and we still have one bit in hand for rounding + subs r7,r7,#2 @ now r7 < -2 + orr r0,r0,r2,lsl#23 @ shift r2:r3 down 9 places, ORing excess into sticky bits + lsrs r2,r2,#9 + orr r2,r2,r3,lsl#23 + lsrs r3,r3,#9 + orrs r0,r0,r1 + it ne + orrne r2,r2,#1 @ sticky bit from bottom 64 bits of mn as shifted +@ r2:r3 mn 2..4 Q51, i.e. 1..2 Q52 +@ r2b0 holds sticky bit; note that for alignment with a in r4:r5, r2:r3 will be shifted down at least one place + + lsrs r6,r5,#31 @ get sign of a (which in this path is the same as the sign of mn, and of the result) + orr r3,r3,r6,lsl#31 @ set sign in mn + + adds r14,r7,r14 @ get exponent for mn relative to a; note this can go negative + add r3,r3,r14,lsl#20 @ note that "implied" 1 is present in r3, giving an offset of 1 in the exponent + bmi 1f @ negative? then we have just constructed a denormal (or less) and the addition will give an incorrect result + dcp_dadd_m r0,r1,r2,r3,r4,r5 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +1: +@ compare with similar code in subtraction path: here we cannot underflow + cmn r7,#64 @ if the alignment shift for mn is very large then the result is just a + ble 82f + add r3,r3,#0x40000000 @ ea cannot be very large (as adding r7 made it negative), so safe to add 1024 to exponents of both a and mn + add r5,r5,#0x40000000 + dcp_dadd_m r0,r1,r2,r3,r4,r5 + sub r1,r1,#0x40000000 @ fix exponent +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +90: +@ dcp_dmul_m tail then dadd ("mla path") + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 + dcp_dadd_m r0,r1,r0,r1,r4,r5 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +82: @ |mn| is very small compared to |a|, so result is a + RDDM r0,r1 @ clear the engaged flag + movs r0,r4 + movs r1,r5 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +@ ======================== SUBTRACTION PATH ======================== + +50: + tst r14,#0x70000000 @ were any of the arguments zero/inf/NaN? + bne 90b @ then use mla path which gives the correct result in all these cases + ubfx r14,r5,#20,#11 @ r14=ea +@ now all operands are finite and non-zero +@ r0:r1:r2:r3: full product mn Q124 1≤mn<4 +@ r4:r5 a IEEE packed (including sign bit; sign of mn is opposite as we are in the subtraction path) +@ r8: em+en [+0x3ff*2] +@ r14: ea [+0x3ff] + subw r8,r8,#0x3fc @ em+en+3 + subs r7,r8,r14 @ em+en-ea+3 (debiased) + blt 80f @ branch if |a| is big compared to |mn|, more precisely if ea-(em+en)≥4 so e.g. if ea=0 then em+en≤-4 and mn<4.2^-4=1/4 + beq 94f @ branch if ea-(em+en)=3 e.g. if ea=0 then em+en=-3 and 1/8=2^-3≤mn<4.2^-3=1/2 +@ in this branch, if e.g. em+en=0 (so 1≤mn<4) then ea≤2 and a<8 + rsbs r7,r7,#75 @ 75-(em+en-ea+3) = 72-(em+en-ea), shift up 0..74 that will be required for a (Q52) to align with mn (Q124, ending in 20 zeros) + mvn r14,r5,lsr#31 @ save complement of sign of a +@ subtract (shifted) a from mn + and r6,r7,#0x1f @ k=shift mod 32 + mov r12,#1 + bfi r5,r12,#20,#12 @ insert implied 1 in a + lsl r12,r12,r6 @ 2^k + umull r5,r6,r5,r12 + sub r12,#1 + umlal r4,r5,r4,r12 @ shift a up by shift amount mod 32 (see comment in addition path) +@ r4:r5:r6: a shifted up by k=shift mod 32 + bmi 91f @ will a be shifted down? + cmp r7,#64 @ shift up by two more words? + bge 92f + cmp r7,#32 @ shift up by one more word? + bge 93f + subs r0,r0,r4 @ no more word shifts; this cannot go negative or have bad cancellation + sbcs r1,r1,r5 + sbcs r2,r2,r6 + sbcs r3,r3,#0 @ r0:r1:r2:r3: mn - a (cf dmul macro) + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD @ as dmul macro tail: exponent and sign computed in coprocessor is correct + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +94: +@ here if ea-(em+en)=3 e.g. if ea=0 then em+en=-3 and 1/8=2^-3≤mn<4.2^-3=1/2 +@ r0:r1:r2:r3: full product mn Q124 1≤mn<4 +@ r4:r5 a IEEE packed (including sign bit; sign of mn is opposite as we are in the subtraction path) + lsls r5,r5,#11 @ convert a to mantissa Q63 in r4:r5 + orrs r5,r5,r4,lsr#21 + lsls r4,r4,#11 + orrs r5,r5,0x80000000 @ implied 1 + movs r6,#0 + subs r0,r6,r0 @ compute |a|-|mn| + sbcs r6,r6,r1 + sbcs r4,r4,r2 + sbcs r5,r5,r3 + WXMS r0,r6 @ write sticky bits + WXMO r4,r5 @ write sticky+result bits + NRDD + RDDM r0,r1 + eor r1,r1,0x80000000 @ sign of result is opposite to that of product as yielded by coprocessor +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +93: + subs r1,r1,r4 @ shifting a up by one word: this cannot go negative or have bad cancellation + sbcs r2,r2,r5 + sbcs r3,r3,r6 + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +92: + subs r2,r2,r4 @ shifting a up by two words: this /can/ go negative or have bad cancellation + sbcs r3,r3,r5 + cmp r3,#0x01000000 @ check we have at least 57 bits of product so that dmul tail will round correctly (this test is slightly conservative - 55 needed?) + blt 1f @ also trap case where result is negative + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +@ heavy cancellation case +@ r0:r1:r2:r3: result Q124, signed +@ r8: em+en+3 +@ r14b0: save complement of sign of a +1: + sub r8,r8,#1 @ em+en+2 + RDDM r6,r7 @ clear engaged flag + blo 2f @ if result is negative... + movs r6,#0 @ ... negate it... + subs r0,r6,r0 + sbcs r1,r6,r1 + sbcs r2,r6,r2 + sbcs r3,r6,r3 + eor r14,r14,#1 @ ... and flip saved sign +2: @ now normalise result + orrs r6,r2,r3 @ shift up by 64 possible? + bne 7f + movs r3,r1 @ do it + movs r2,r0 + movs r1,#0 + movs r0,#0 + sub r8,r8,#64 @ fix exponent +7: + cmp r3,#0 @ shift up by 32 possible? + bne 8f + movs r3,r2 @ do it + movs r2,r1 + movs r1,r0 + movs r0,#0 + sub r8,r8,#32 +8: + cmp r3,#0 @ is result zero? return it + beq 9f + clz r6,r3 @ k=amount of final shift + subs r8,r8,r6 @ final exponent + movs r7,#1 + lsls r7,r7,r6 @ r7=2^k + muls r3,r3,r7 + subs r7,r7,#1 @ 2^k-1 + umlal r2,r3,r2,r7 + umlal r1,r2,r1,r7 + umlal r0,r1,r0,r7 @ r0:r1:r2:r3: normalised result + orrs r0,r0,r1 @ any sticky bits below top 64? + it ne + orrne r2,r2,#1 @ or into sticky bit + lsrs r0,r2,#11 @ align to mantissa position for IEEE format + lsrs r1,r3,#11 + orr r0,r0,r3,lsl#21 + lsls r2,r2,#22 @ rounding bit in C, sticky bit in ~Z + bcc 10f @ no rounding? + beq 11f @ rounding tie? + adcs r0,r0,#0 @ round up (C is set) + adcs r1,r1,#0 + adds r8,r8,r1,lsr#20 @ candidate for exponent field + ble 12f @ underflow? overflow cannot occur here as the result is smaller in magnitude than a + bfi r1,r8,#20,#11 @ insert exponent + orr r1,r1,r14,lsl#31 @ or in sign +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +11: + adcs r0,r0,#0 @ round up as above + adcs r1,r1,#0 + bic r0,r0,#1 @ to even + adds r8,r8,r1,lsr#20 @ candidate for exponent field + ble 12f @ underflow? + bfi r1,r8,#20,#11 @ insert exponent + orr r1,r1,r14,lsl#31 @ or in sign +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +10: + adds r8,r8,r1,lsr#20 @ candidate for exponent field + ble 12f @ underflow? + bfi r1,r8,#20,#11 @ insert exponent + orr r1,r1,r14,lsl#31 @ or in sign +9: +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +12: + mov r1,r14,lsl#31 @ underflow: return signed zero + movs r0,#0 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +91: @ case where a (Q52) is shifted down relative to mn (Q124); the mod 32 part of the shift of a has already been done +@ r0:r1:r2:r3: mn +@ r4:r5:r6: a +@ r7: alignment shift required (negative) + cmn r7,#32 @ shift down one word? + bge 94f + cmn r7,#64 @ shift down two words? + bge 95f +@ here a is shifted entirely below the bottom of m + subs r0,r0,#1 @ subtract an epsilon (a is non-zero) + sbcs r1,r1,#0 + sbcs r2,r2,#0 + sbcs r3,r3,#0 + orr r0,r0,#1 @ ensure the sticky bit is set (a is non-zero) + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +94: + rsbs r4,r4,#0 @ one word shift down + sbcs r0,r0,r5 + sbcs r1,r1,r6 + sbcs r2,r2,#0 + sbcs r3,r3,#0 + orr r0,r0,r4 @ sticky bits + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +95: + movs r7,#0 @ two words shift down + subs r4,r7,r4 + sbcs r5,r7,r5 + sbcs r0,r0,r6 + sbcs r1,r1,r7 + sbcs r2,r2,r7 + sbcs r3,r3,r7 + orrs r0,r0,r4 @ sticky bits + orrs r0,r0,r5 + WXMS r0,r1 @ write sticky bits + WXMO r2,r3 @ write sticky+result bits + NRDD + RDDM r0,r1 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +80: +@ here |a| is big compared to |mn|, more precisely ea-(em+en)≥4 so e.g. if ea=0 then em+en≤-4 and mn<4.2^-4=1/4 +@ r0:r1:r2:r3: mn Q124 +@ r4:r5: a IEEE packed +@ r7<0, em+en-ea+3 (debiased) +@ r14: ea [+0x3ff] + lsrs r6,r3,#29 + bne 1f @ 2≤mn<4? + adds r2,r2,r2 @ shift up one place + adcs r3,r3,r3 + subs r7,r7,#1 @ fix exponent +1: @ now r2:r3 is mn Q61, sticky bits in r0:r1 + subs r7,r7,#3 +@ r7=emn-ea <-3 + orr r0,r0,r2,lsl#23 @ gather sticky bits + lsrs r2,r2,#9 @ adjust mn to Q52 ready to create packed IEEE version of mn + orr r2,r2,r3,lsl#23 + lsrs r3,r3,#9 + orrs r0,r0,r1 @ or of all sticky bits + it ne + orrne r2,r2,#1 @ sticky bit from bottom 64 bits of mn + + mvn r6,r5,lsr#31 @ complement of sign of a + orr r3,r3,r6,lsl#31 @ fix sign of mn so we do a subtraction + + adds r14,r7,r14 @ this can go negative; r14 is now at most ea[+0x3ff]-4 + add r3,r3,r14,lsl#20 +@ the exponent field in r2:r3 (mn) is now at most ea[+0x3ff]-3 +@ that means that in the dadd operation that follows, mn will be shifted down at least three places to align with a, +@ and a post-normalisation shift up of at most one place will be needed +@ therefore in the worst case r2b2 affects b0 of the result; r2b1 affects the rounding of the result; and r2b0 can be used as a sticky bit + bmi 1f @ did exponent go negative? + + dcp_dadd_m r0,r1,r2,r3,r4,r5 +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + +1: + cmn r7,#64 @ is mn being shifted well below the bottom of a? + ble 82b @ then result is just a + add r3,r3,#0x40000000 @ otherwise offset exponents by +1024 + add r5,r5,#0x40000000 + dcp_dadd_m r0,r1,r2,r3,r4,r5 + ubfx r2,r1,#20,#11 @ get exponent + cmp r2,#0x400 @ too small? + itte ls + andls r1,r1,0x80000000 @ flush to signed zero + movls r0,#0 + subhi r1,r1,#0x40000000 @ else fix exponent of result +// todo optimize this based on final decision on saving_func_entry + pop {r4-r8,lr} + saving_func_return + + +double_wrapper_section __dmla +@ cf saving_func macro: but here we need to record the SP before the state save possibly changes it +1: + push {lr} // 16-bit instruction + bl __dcp_save_state // 32-bit instruction + b 1f // 16-bit instruction + +@ r0:r1 m +@ r2:r3 n +@ [r13,#0] a +regular_func mla + mov r12,sp @ save the SP + PCMP apsr_nzcv @ test the engaged flag + bmi 1b +1: + push {r4,r5,r14} + dcp_dmul_m r0,r1,r0,r1,r2,r3,r0,r1,r2,r3,r4,r5,r14 + ldrd r2,r3,[r12,#0] @ fetch a using original SP + dcp_dadd_m r0,r1,r0,r1,r2,r3 +// todo optimize this based on final decision on saving_func_entry + pop {r4,r5,r14} + saving_func_return + +#endif diff --git a/src/rp2_common/pico_double/double_init_rom.c b/src/rp2_common/pico_double/double_init_rom_rp2040.c similarity index 88% rename from src/rp2_common/pico_double/double_init_rom.c rename to src/rp2_common/pico_double/double_init_rom_rp2040.c index eec56c4c0..af958358c 100644 --- a/src/rp2_common/pico_double/double_init_rom.c +++ b/src/rp2_common/pico_double/double_init_rom_rp2040.c @@ -46,9 +46,11 @@ void __aeabi_double_init(void) { } #endif if (rom_version >= 2) { - void *rom_table = rom_data_lookup(rom_table_code('S', 'D')); - assert(*((uint8_t *)rom_data_lookup(rom_table_code('S', 'F'))-2) * 4 >= SF_TABLE_V2_SIZE); - memcpy(&sd_table, rom_table, SF_TABLE_V2_SIZE); + void *rom_table_double = rom_data_lookup(rom_table_code('S', 'D')); + void *rom_table_float = rom_data_lookup(rom_table_code('S', 'F')); + assert(*((uint8_t *)(((void *)rom_table_float)-2)) * 4 >= SF_TABLE_V2_SIZE); + (void)rom_table_float; + memcpy(&sd_table, rom_table_double, SF_TABLE_V2_SIZE); if (rom_version == 2) { #ifndef NDEBUG if (*(uint16_t *)0x3854 != 0xb500 || // this is dsincos(_internal) diff --git a/src/rp2_common/pico_double/double_math.c b/src/rp2_common/pico_double/double_math.c index 6d2a48ec6..26ff1f40c 100644 --- a/src/rp2_common/pico_double/double_math.c +++ b/src/rp2_common/pico_double/double_math.c @@ -342,9 +342,11 @@ double WRAPPER_FUNC(exp10)(double x) { check_nan_d1(x); return pow(10,x); } double WRAPPER_FUNC(log10)(double x) { check_nan_d1(x); return log(x)*LOG10E; } // todo these are marked as lofi -double WRAPPER_FUNC(expm1(double x) { check_nan_d1(x); return exp)(x)-1; } -double WRAPPER_FUNC(log1p(double x) { check_nan_d1(x); return log)(1+x); } +double WRAPPER_FUNC(expm1)(double x) { check_nan_d1(x); return exp(x)-1; } +double WRAPPER_FUNC(log1p)(double x) { check_nan_d1(x); return log(1+x); } +#if !HAS_DOUBLE_COPROCESSOR double WRAPPER_FUNC(fma)(double x,double y,double z) { check_nan_d1(x); return x*y+z; } +#endif // general power, x>0, finite static double dpow_1(double x,double y) { diff --git a/src/rp2_common/pico_double/double_none.S b/src/rp2_common/pico_double/double_none.S index 89fb1177b..3ff0b3080 100644 --- a/src/rp2_common/pico_double/double_none.S +++ b/src/rp2_common/pico_double/double_none.S @@ -72,9 +72,14 @@ pico_default_asm_setup wrapper_func log1p wrapper_func fma +#ifdef __riscv + la a0, str + j panic +#else push {lr} // keep stack trace sane ldr r0, =str bl panic +#endif str: .asciz "double support is disabled" \ No newline at end of file diff --git a/src/rp2_common/pico_double/double_sci_m33.S b/src/rp2_common/pico_double/double_sci_m33.S new file mode 100644 index 000000000..bb41975aa --- /dev/null +++ b/src/rp2_common/pico_double/double_sci_m33.S @@ -0,0 +1,1518 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !PICO_RP2040 +#include "pico/asm_helper.S" + +pico_default_asm_setup + +.macro double_section name +#if PICO_DOUBLE_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro double_wrapper_section func +double_section WRAPPER_FUNC_NAME(\func) +.endm + +.global rtwopi +.global logtab0 +.global exptab0 +.global exptab1 +.global exptab2 +.global trigtab + +@ load a 32-bit constant n into register rx +.macro movlong rx,n + movw \rx,#(\n)&0xffff + movt \rx,#((\n)>>16)&0xffff +.endm + +double_section rtwopi + +// 1/2π to plenty of accuracy, 256 bits per line +.long 0 @ this allows values of e down to -32 +rtwopi: +.long 0,0 +.long 0x28BE60DB, 0x9391054A, 0x7F09D5F4, 0x7D4D3770, 0x36D8A566, 0x4F10E410, 0x7F9458EA, 0xF7AEF158 +.long 0x6DC91B8E, 0x909374B8, 0x01924BBA, 0x82746487, 0x3F877AC7, 0x2C4A69CF, 0xBA208D7D, 0x4BAED121 +.long 0x3A671C09, 0xAD17DF90, 0x4E64758E, 0x60D4CE7D, 0x272117E2, 0xEF7E4A0E, 0xC7FE25FF, 0xF7816603 +.long 0xFBCBC462, 0xD6829B47, 0xDB4D9FB3, 0xC9F2C26D, 0xD3D18FD9, 0xA797FA8B, 0x5D49EEB1, 0xFAF97C5E +.long 0xCF41CE7D, 0xE294A4BA, 0x9AFED7EC, 0x47E35742, 0x1580CC11 + +double_section drrcore + +@ input: +@ r0:r1 mantissa m Q52 +@ r2 exponent e>=-32, typically offset by +12 +@ r3 pointer to rtwopi table +@ output: +@ r0..r2 preserved +@ r7:r8 range reduced result +@ r3,r4,r5,r6,r9,r10 trashed +.thumb_func +drr_core: + ldr r3,=rtwopi + and r5,r2,#31 @ s=e%32 + mov r7,#1 + lsls r7,r7,r5 @ 1< +2 quadrants + ands r12,#4 + b 1f + +wrapper_func cos + movs r12,#2 @ cos -> +1 quadrant +1: + ubfx r3,r1,#20,#11 @ get exponent + sub r2,r3,#0x3ff + cmp r2,#0x400 + beq 10b @ Inf or NaN? + cmn r2,#32 + blt 32b @ very small argument? + movs r3,#1 + bfi r1,r3,#20,#12 @ fix implied 1 in mantissa + push {r4-r10,r14} + add r2,#12 @ e+12 + bl drr_core +@ r7:r8 θ/2π 0..1 Q64 + lsrs r4,r8,#30 @ quadrant count + adc r4,r4,#0 @ rounded + sub r8,r8,r4,lsl#30 @ now -0.125≤r7:r8<+0.125 Q64 + add r12,r12,r4,lsl#1 + orr r12,r12,r8,lsr#31 @ sign into r12b0 +@ r12b2..1: quadrant count +@ r12b0: sign of reduced angle + eors r7,r7,r8,asr#31 + eors r8,r8,r8,asr#31 @ absolute value of reduced angle 0≤r7:r8<0.125 Q64 + cmp r8,#1<<22 @ < 2^-10? + blo 40b + +@ 2π=6.487ED511 0B4611A6 (2633...) + movlong r9,0x0B4611A6 @ 2π Q64 low fractional word + umull r10,r0,r8,r9 + movlong r9,0x487ED511 @ 2π Q64 high fractional word + umull r10,r1,r7,r9 + umaal r0,r1,r8,r9 + movs r9,#6 @ 2π integer part + umlal r0,r1,r7,r9 + mla r1,r8,r9,r1 +@ r0:r1 range reduced angle θ 0..π/4 Q64 + + cmp r1,#1<<25 @ θ < 2^-7? + blo 30b + lsrs r2,r1,#27 + ldr r3,=trigtab + add r3,r3,r2,lsl#4 + ldmia r3,{r2-r5} +31: + subs r0,r0,r2 + sbcs r1,r1,r3 @ ε=Θ-φ Q64 + bmi 2f @ ε negative? + + asrs r6,r12,#1 + bmi 5f @ doing dsincos? + asrs r6,#1 + bcs 3f @ need cosine? + +@ here ε is positive, we need the sin of θ and the sign of the result is r12b0^r12b2 + bl dsc_h0 + bl dsc_h0s + bl dpack_q63 +21: + eors r12,r12,r12,lsr#2 + orrs r1,r1,r12,lsl#31 @ insert sign + pop {r4-r10,r15} + +2: + asrs r6,r12,#1 + bmi 6f @ doing dsincos? + asrs r6,#1 + bcs 4f @ need cosine? + +@ here ε is negative, we need the sin of θ and the sign of the result is r12b0^r12b2 + bl dsc_h1 + bl dsc_h1s + bl dnegpack_q63 + eors r12,r12,r12,lsr#2 + orrs r1,r1,r12,lsl#31 @ insert sign + pop {r4-r10,r15} + +@ here ε is positive, we need the cos of θ and the sign of the result is r12b2 +3: + bl dsc_h0 + bl dsc_h0c + bl dnegpack_q63 +22: + ands r12,#4 + orrs r1,r1,r12,lsl#29 @ insert sign + pop {r4-r10,r15} + +@ here ε is negative, we need the cos of θ and the sign of the result is r12b2 +4: + bl dsc_h1 + bl dsc_h1c +15: + bl dpack_q63 + ands r12,#4 + orrs r1,r1,r12,lsl#29 @ insert sign + pop {r4-r10,r15} + +5: +@ dsincos, ε positive + bl dsc_h0 + push {r2-r7} + bl dsc_h0c + bl dnegpack_q63 + ands r4,r12,#4 + eors r1,r1,r4,lsl#29 @ negate cosine in quadrants 2 and 3 + pop {r2-r7} + push {r0,r1} + bl dsc_h0s + bl dpack_q63 +20: + eors r4,r12,r12,lsr#1 + eors r4,r4,r12,lsr#2 + eors r1,r1,r4,lsl#31 @ negate sine on b0^b1^b2 + tst r12,#2 @ exchange sine and cosine in odd quadrants + ittte ne + movne r2,r0 + movne r3,r1 + popne {r0,r1} + popeq {r2,r3} + ands r4,r12,#1<<30 + eors r1,r1,r4,lsl#1 @ negate sine result if argument was negative + pop {r4-r10,r15} + +6: +@ dsincos, ε negative + bl dsc_h1 + push {r2-r7} + bl dsc_h1c + bl dpack_q63 + ands r4,r12,#4 + eors r1,r1,r4,lsl#29 @ negate cosine in quadrants 2 and 3 + pop {r2-r7} + push {r0,r1} + bl dsc_h1s + bl dnegpack_q63 + b 20b + +@ sin/cos power series for negative ε +dsc_h1: + rsbs r0,r0,#0 + sbc r1,r1,r1,lsl#1 +@ drop into positive ε code + +@ sin/cos power series for positive ε +dsc_h0: +@ r0:r1 ε Q64 +@ r4: sin φ Q32 +@ r5: cos φ Q32 + umull r6,r7,r1,r1 + umull r2,r3,r0,r1 + lsrs r7,#1 + rrx r6,r6 + adds r2,r6,r3 + adc r3,r7,#0 +@ r2:r3 ε²/2 Q64 + umull r7,r6,r3,r0 + umlal r7,r6,r2,r1 + movs r7,#0 + umlal r6,r7,r3,r1 +@ r6:r7 ε³/2 Q64 + mov r8,#0x55555555 + umull r9,r6,r6,r8 + mov r9,#0 + umlal r6,r9,r7,r8 + adds r6,r6,r9 + adcs r7,r9,#0 +@ r6:r7 ε³/6 Q64 + subs r6,r0,r6 + sbcs r7,r1,r7 +@ r6:r7 ε-ε³/6 Q64 + mov r0,r3,lsl#12 @ ε²/2 Q44 + orr r0,r0,r2,lsr#20 + umull r0,r9,r0,r0 @ r9: ε⁴/4 Q88-32=Q56 = ε⁴/32 Q59 + umlal r0,r9,r9,r8 @ r9: ε⁴/24 Q59 + + umull r0,r8,r9,r1 @ ε⁵/24 Q59 + mov r0,#0x33333333 + umull r0,r8,r8,r0 @ r8: ε⁵/120 Q59 +@ r6:r7 ε-ε³/6+ε⁵/120 Q64 + smmulr r10,r8,r1 @ r10: ε⁶/120 Q59 + movlong r0,0x2aaaaaaa + smmlsr r9,r0,r10,r9 @ ε⁴/24-ε⁶/720 + subs r2,r2,r9,lsl#5 + sbcs r3,r3,r9,lsr#27 +@ r2:r3 ε²/2-ε⁴/24+ε⁶/720 Q64 + smmulr r10,r10,r1 @ r10: ε⁷/120 Q59 + mov r0,#0x6180000 @ 1/42 Q64 + smmlsr r8,r10,r0,r8 @ r8: ε⁵/120-ε⁷/5040 Q59 + adds r6,r6,r8,lsl#5 + adcs r7,r7,r8,lsr#27 + bx r14 + +dsc_h0s: +@ postprocess for sine, positive ε +@ r2:r3 1-cos |ε| Q64 +@ r4: sin φ Q31 +@ r5: cos φ Q31 +@ r6:r7 sin |ε| Q64 + umull r8,r0,r2,r4 + mov r1,#0 + umlal r0,r1,r3,r4 +@ r0:r1 sin φ(1-cos ε) + umull r8,r3,r6,r5 + umlal r3,r4,r7,r5 +@ r3:r4 sin φ+cos φ.sin ε + subs r0,r3,r0 + sbc r1,r4,r1 +@ r0:r1 sin φ+cos φ.sin ε - sin φ(1-cos ε) = sin φ.cos ε + cos φ.sin ε = sin(φ+ε) + bx r14 + +dsc_h1s: +@ postprocess for sine, negative ε +@ r2:r3 1-cos |ε| Q64 +@ r4: sin φ Q31 +@ r5: cos φ Q31 +@ r6:r7 sin |ε| Q64 + umull r8,r0,r2,r4 + mov r1,#0 + umlal r0,r1,r3,r4 +@ r0:r1 sin φ(1-cos ε) + umull r8,r3,r6,r5 + rsbs r4,r4,#0 + umlal r3,r4,r7,r5 +@ r3:r4 -sin φ-cos φ.sin ε + adds r0,r3,r0 + adc r1,r4,r1 +@ r0:r1 -sin φ-cos φ.sin ε + sin φ(1-cos ε) = -sin φ.cos ε - cos φ.sin ε = -sin(φ+ε) + bx r14 + +dsc_h0c: +@ postprocess for cosine, positive ε +@ r2:r3 1-cos |ε| Q64 +@ r4: sin φ Q32 +@ r5: cos φ Q32 +@ r6:r7 sin |ε| Q64 + umull r8,r0,r2,r5 + mov r1,#0 + umlal r0,r1,r3,r5 +@ r0:r1 cos φ(1-cos ε) + umull r8,r3,r6,r4 + rsbs r5,#0 + umlal r3,r5,r7,r4 +@ r3:r5 -cos φ+sin φ.sin ε + adds r0,r3,r0 + adc r1,r5,r1 +@ r0:r1 -cos φ+sin φ.sin ε + cos φ(1-cos ε) = - cos φ.cos ε + sin φ.sin ε = -cos(φ+ε) + bx r14 + +dsc_h1c: +@ postprocess for cosine, negative ε +@ r2:r3 1-cos |ε| Q64 +@ r4: sin φ Q32 +@ r5: cos φ Q32 +@ r6:r7 sin |ε| Q64 + umull r8,r0,r2,r5 + mov r1,#0 + umlal r0,r1,r3,r5 +@ r0:r1 cos φ(1-cos ε) + umull r8,r3,r6,r4 + umlal r3,r5,r7,r4 +@ r3:r5 cos φ-sin φ.sin ε + subs r0,r3,r0 + sbc r1,r5,r1 +@ r0:r1 cos φ-sin φ.sin ε - cos φ(1-cos ε) = cos φ.cos ε - sin φ.sin ε = cos(φ+ε) + bx r14 + +double_section dpack + +@ dnegpack: negate and pack +@ dpack_q63: +@ input +@ r0:r1 Q63 result, must not be zero +@ r4 exponent offset [dpack_q only] +@ output +@ r0:r1 IEEE double +@ trashes r2,r3,r4 +.thumb_func +dnegpack_q63: + rsbs r0,r0,#0 + sbc r1,r1,r1,lsl#1 +.thumb_func +dpack_q63: + mov r4,#0x3ff-12 @ exponent +.thumb_func +dpack_q: + clz r2,r1 + cmp r2,#12 + bhs 1f + adds r2,#21 + lsls r3,r1,r2 + rsb r2,#32 + lsrs r0,r0,r2 @ save rounding bit in carry + lsr r1,r1,r2 + add r2,r2,r4 + adcs r0,r0,r3 @ with rounding + adc r1,r1,r2,lsl#20 @ insert exponent + bx r14 + +1: + cbz r1,2f + rsb r2,#43 + lsrs r3,r0,r2 + rsb r2,#32 + lsls r1,r1,r2 + lsls r0,r0,r2 + orrs r1,r3 + sub r2,r4,r2 + add r1,r1,r2,lsl#20 + bx r14 + +2: + movs r1,r0 + mov r0,#0 + sub r4,#32 + bne dpack_q + bx r14 + + + +double_section dreduce + +@ input: +@ r0:r1 x, double (only mantissa bits used) +@ r2 quotient offset +@ r3 exponent e of x with 0x3ff bias removed, -32≤e<12 so 2^-32≤x<2^12 +@ r4:r5 r Q64, 0.5≤r<1 +@ r6 1/r underestimate Q31 +@ output: +@ r0:r1 x mod r Q64 [possibly slightly > r?] +@ r2 quotient+offset +@ r4:r5 r preserved +@ trashes r7,r8 +@ increases r2 by up to 2^13 +@ this version only used by dexp +.thumb_func +dreduce: + movs r7,#1 + bfi r1,r7,#20,#12 @ insert implied 1, clear exponent and sign + lsls r8,r7,r3 + beq 1f @ e<0, x<1 + umull r0,r7,r0,r8 + mla r1,r1,r8,r7 +@ r0:r1 x Q52 + umull r7,r8,r1,r6 @ Q83-32=Q51 + lsrs r6,r8,#19 @ q Q0 + adds r2,r2,r6 + umull r7,r8,r6,r4 + mla r8,r6,r5,r8 @ r7:r8 q*r Q64 + lsls r1,#12 + orrs r1,r1,r0,lsr#20 + rsbs r0,r7,r0,lsl#12 + sbc r1,r1,r8 @ x-qr Q64 +@ check we never return slightly more than r + cmp r1,r5 @ quick comparison + it lo + bxlo r14 + b 2f + +1: + adds r3,#12 + movs r7,#1 + lsls r8,r7,r3 + beq 1f @ e<-12 + umull r0,r7,r0,r8 + mla r1,r1,r8,r7 @ x Q64 + cmp r1,r5 @ quick comparison + it lo + bxlo r14 +2: + it eq + cmpeq r0,r4 + it lo + bxlo r14 + subs r0,r0,r4 @ subtract one r + sbc r1,r1,r5 + adds r2,#1 + bx r14 + +1: +@ here e<-12, have to shift r0:r1 down by -r3 places + add r3,#32 + lsls r6,r1,r3 + rsbs r3,#32 + lsrs r0,r0,r3 + lsrs r1,r1,r3 + orrs r0,r0,r6 + bx r14 + +double_section exptab + +.align 2 +exptab0: +.quad 0x0000000000000000,0x0f85186008b15304,0x1e27076e2af2e5c8,0x2f57120421b2120d +.quad 0x3f7230dabc7c5512,0x4e993155a517a717,0x5fabe0ee0abf0d9d,0x6fad36769c6defe3 +.quad 0x7ebd623de3cc7b69,0x8f42faf3820681f0,0x9ec813538ab7d537,0xaf70154920b3ab7f +exptab1: +.quad 0x0000000000000000,0x00ff805515885e02,0x01fe02a6b1067890,0x02fb88ebf0214edc +.quad 0x03f815161f807c7a,0x04f3a910d1a95d3c,0x05ee46c1f56c46aa,0x06e7f009ebe465ff +.quad 0x07e0a6c39e0cc013,0x08d86cc491ecbfe1,0x09cf43dcff5eafd5,0x0ac52dd7e4726a46 +.quad 0x0bba2c7b196e7e23,0x0cae41876471f5bf,0x0da16eb88cb8df61,0x0e93b5c56d85a909 +.quad 0x0f85186008b15331,0x1075983598e47130 +exptab2: +.quad 0x000fff8005551559,0x002ffb808febc309,0x004ff3829a0e91b1,0x006fe78722fde71f +.quad 0x008fd78f299aa0c3,0x00afc39bac66434f,0x00cfabada9832a41,0x00ef8fc61eb4b74f +.quad 0x010f6fe6095f81b6,0x012f4c0e66898567,0x014f244032da521a,0x016ef87c6a9b3a48 +.quad 0x018ec8c409b781ff,0x01ae95180bbc8d9c,0x01ce5d796bda1070,0x01ee21e924e23b3a +logtab0: +.quad 0xa0ec7f4233957338,0x918986bdf5fa1431,0x8391f2e0e6fa026b,0x7751a813071282e6 +.quad 0x6a73b26a68212621,0x5fabe0ee0abf0d9d,0x546ab61cb7e0b419,0x48a507ef3de59695 +.quad 0x3c4e0edc55e5cbd1,0x32a4b539e8ad68ce,0x289a56d996fa3ccb,0x21aefcf9a11cb2c9 +.quad 0x16f0d28ae56b4b86,0x0f85186008b15304,0x07e0a6c39e0cc002,0x0000000000000000 + +.align 2 +exprrdata: +.quad 0xB17217F7D1CF79AC @ ln2 Q64 +.long 0xB8AA3B29 @ 1/ln2 Q31, rounded down + +double_wrapper_section exp + +2: +@ could use dadd macro to calculate x+1 here + lsl r0,r1,#11 + orr r0,#0x80000000 + lsls r1,#1 + adc r3,r3,#32 + movlong r1,0x3ff00000 + rsb r3,#11 + lsr r0,r3 + it cc + bxcc r14 + rsbs r0,#0 + sbc r1,r1,#0 + bx r14 + +wrapper_func exp + movs r12,r1,lsr#31 @ save sign + ubfx r3,r1,#20,#11 @ get exponent + sub r3,r3,#0x3ff + cmp r3,#12 + bge 20f @ overflow, Inf or NaN? + cmn r3,#0x20 + ble 2b @ <2^-32? return x+1 + push {r4-r8,r14} + ldr r4,=exprrdata + ldmia r4,{r4-r6} + mov r2,#0 + bl dreduce + tst r12,#1 + beq 1f + mvn r2,r2 @ quotient is now signed + subs r0,r4,r0 + sbc r1,r5,r1 +1: + add r12,r2,#0x3fe @ exponent offset + mov r3,#0x7fe + cmp r12,r3 + bhs 1f @ under/overflow + lsrs r2,r1,#28 + ldr r3,=exptab0 + add r3,r3,r2,lsl#3 + ldmia r3,{r2-r3} + and r5,r2,#63 + orr r5,#64 @ y=(t&0x3f)+0x40; Q6 + subs r0,r2 + sbcs r1,r3 + lsrs r2,r1,#24 + ldr r3,=exptab1 + add r3,r3,r2,lsl#3 + ldmia r3,{r3-r4} + add r2,#256 + muls r5,r5,r2 @ y Q14 + subs r0,r3 + sbcs r1,r4 + lsrs r2,r1,#21 + ldr r3,=exptab2 + add r3,r3,r2,lsl#3 + ldmia r3,{r3-r4} + add r2,r2,r2 + add r2,#4096 + mla r5,r5,r2,r5 @ y Q26 + subs r0,r3 + sbcs r1,r4 + + movs r2,r1,lsl#10 + orrs r2,r2,r0,lsr#22 + adc r2,r2,#0 @ ε Q42, rounded + smull r3,r4,r2,r2 @ ε² Q84-32=Q52 + lsrs r3,#21 + orrs r3,r3,r4,lsl#11 + adds r0,r0,r3 + adc r1,r1,r4,lsr#21 @ ε+ε²/2 Q64 + smull r3,r4,r4,r2 @ Q52*Q42=Q94; Q94-32=Q62 + mov r3,#0x55555555 @ 1/6 Q33 + smull r3,r4,r3,r4 @ ε³/6 Q63 + smmulr r3,r4,r1 @ ε⁴/6+ε⁵/12 Q63+Q32-32=Q63 + add r4,r4,r3,lsr#2 + adds r2,r0,r4,lsl#1 + adc r3,r1,r4,asr#31 + lsls r1,r5,#3 @ y Q29 + umull r4,r0,r1,r2 @ εlo * y Q61+32 + smlal r0,r1,r1,r3 @ εhi * y + y Q61 +@ assert result is in range 1..2 + lsrs r0,#9 + adcs r0,r0,r1,lsl#23 + lsr r1,#9 + adcs r1,r1,r12,lsl#20 + pop {r4-r8,r15} + +20: +@ process Inf/NaN for dexp + cmp r3,#0x400 + bne 22f + orrs r2,r0,r1,lsl#12 + ite eq + biceq r1,r1,r1,asr#31 @ +Inf -> + Inf; -Inf -> +0 + orrne r1,r1,#0x00080000 + bx r14 + +22: + movs r0,#0 + movs r1,#0 + tst r12,#1 + it eq + movteq r1,0x7ff0 + bx r14 + +1: @ under/overflow + mov r0,#0 + mov r1,#0 + it ge + movtge r1,#0x7ff0 + pop {r4-r8,r15} + + + + +double_wrapper_section log + +1: + movlong r1,0xfff00000 @ return -Inf + movs r0,#0 + bx r14 + +4: + orrs r2,r0,r1,lsl#12 + it ne + orrne r1,#0x00080000 + bx r14 + +10: + mvns r5,r6,asr#22 @ very small argument? + bne 10f + mov r4,#4096 + b 11f + +@ check for argument near 1: here +@ r1 : mantissa +@ r12: exponent, -1 or 0 +12: + eor r3,r12,r1,lsr#12 + lsls r3,r3,#24 @ check 8 bits of mantissa + bne 12f @ not very close to 1 + cmp r12,#0 + bne 13f +@ argument is 1+ε, result will be positive + lsls r1,#19 + orrs r1,r1,r0,lsr#13 + lsls r0,#19 +@ r0:r1 ε Q71 0≤ε<2^-8 + clz r4,r1 @ r4≥1 + cmp r4,#32 + bhs 14f + movs r5,#1 + lsls r5,r4 + umull r2,r3,r0,r5 + mla r3,r1,r5,r3 @ r2:r3 ε Q71+r4 + umull r12,r5,r0,r3 + umull r12,r6,r1,r2 + umaal r5,r6,r1,r3 @ r5:r6 ε² Q142+r4-64 = Q78+r4 + + subs r2,r2,r5,lsr#8 + sbc r3,r3,#0 + subs r2,r2,r6,lsl#24 + sbcs r3,r3,r6,lsr#8 + + umull r12,r7,r0,r6 + umull r12,r8,r1,r5 + umaal r7,r8,r1,r6 @ r7:r8 ε³ Q149+r4-64 = Q85+r4: when ε is nearly 2^-8, r4=1 and Q86, so r8<0x40000000 + mov r5,#0x55555555 @ ~1/3 Q32 + + umull r12,r6,r7,r5 + movs r12,#0 + umlal r6,r12,r8,r5 + adds r6,r6,r12 + adc r12,r12,#0 @ multiply by 0x5555555555555555 + + adds r2,r2,r6,lsr#14 + adc r3,r3,#0 + adds r2,r2,r12,lsl#18 + adc r3,r3,r12,lsr#14 + + smmulr r5,r8,r1 @ ε⁴ Q53+r4+Q71-Q64=Q60+r4 ~ 2^-32 + movs r7,#0x33333333 @ 1/5 Q32 + smmulr r6,r5,r1 @ ε⁵ Q60+r4+q71-Q64=Q67+r4 ~ 2^-40 + smmulr r8,r6,r7 @ ε⁵/5 Q67+r4 ~ 2^-42 + sub r7,r5,r8,lsr#5 + smmulr r5,r6,r1 @ ε⁶ Q67+r4+q71-Q64=Q74+r4 ~ 2^-48 + movt r6,#0x2a80 @ 1/6 Q32 fiddled slightly (PMC) + smmulr r5,r6,r5 @ ε⁶/6 Q75+r4 ~ 2^-50 + add r7,r7,r5,lsr#12 + + subs r0,r2,r7,lsl#9 + sbc r1,r3,r7,lsr#23 + + rsb r4,#0x400 + sub r4,#0x15 + bl dpack_q + pop {r4-r8,r15} + +@ here we have positive ε sufficiently small we need (at most) a quadratic term +14: +@ here r0=ε Q71, 0≤ε<2^-40 + clz r4,r0 + lsls r1,r0,r4 @ ε Q71+r4 + umull r2,r3,r0,r1 @ ε² Q142+r4 + mov r0,#0 + subs r0,r0,r3,lsr#8 + sbc r1,r1,#0 + rsb r4,#0x400 + sub r4,#0x35 + bl dpack_q + pop {r4-r8,r15} + + + +13: @ argument is 1-ε, result will be negative + movs r1,r1,lsl#18 + orrs r1,r1,r0,lsr#14 + movs r0,r0,lsl#18 + rsbs r0,#0 + sbc r1,r1,r1,lsl#1 +@ r0:r1 -ε Q71 -2^-9≤ε<0 + clz r4,r1 + cmp r4,#32 + bhs 15f + subs r4,#1 @ 0≤r4<31 + movs r5,#1 + lsls r5,r4 + umull r2,r3,r0,r5 + mla r3,r1,r5,r3 @ r2:r3 ε Q71+r4 + umull r12,r5,r0,r3 + umull r12,r6,r1,r2 + umaal r5,r6,r1,r3 @ r5:r6 ε² Q142+r4-64 = Q78+r4 + + adds r2,r2,r5,lsr#8 + adc r3,r3,#0 + adds r2,r2,r6,lsl#24 + adcs r3,r3,r6,lsr#8 + + umull r12,r7,r0,r6 + umull r12,r8,r1,r5 + umaal r7,r8,r1,r6 @ r7:r8 ε³ Q149+r4-64 = Q85+r4: when ε is nearly 2^-8, r4=0 and Q85, so r8<0x20000000 + mov r5,#0x55555555 @ ~1/3 Q32 + + umull r12,r6,r7,r5 + movs r12,#0 + umlal r6,r12,r8,r5 + adds r6,r6,r12 + adc r12,r12,#0 @ multiply by 0x5555555555555555 + + adds r2,r2,r6,lsr#14 + adc r3,r3,#0 + adds r2,r2,r12,lsl#18 + adc r3,r3,r12,lsr#14 + + smmulr r5,r8,r1 @ ε⁴ Q53+r4+Q71-Q64=Q60+r4 ~ 2^-32 + movs r7,#0x33333333 @ 1/5 Q32 + smmulr r6,r5,r1 @ ε⁵ Q60+r4+q71-Q64=Q67+r4 ~ 2^-40 + smmulr r8,r6,r7 @ ε⁵/5 Q67+r4 ~ 2^-42 + add r7,r5,r8,lsr#5 + smmulr r5,r6,r1 @ ε⁶ Q67+r4+q71-Q64=Q74+r4 ~ 2^-48 + movt r6,#0x2a80 @ 1/6 Q32 fiddled slightly (PMC) + smmulr r5,r6,r5 @ ε⁶/6 Q75+r4 ~ 2^-50 + add r7,r7,r5,lsr#12 + + adds r0,r2,r7,lsl#9 + adc r1,r3,r7,lsr#23 + + rsb r4,#0x400 + sub r4,#0x15 + bl dpack_q + orr r1,r1,#1<<31 + pop {r4-r8,r15} + +@ here we have negative ε sufficiently small we need (at most) a quadratic term +@ here r0=ε Q71, |ε|<2^-41 +15: + clz r4,r0 + lsls r1,r0,r4 @ ε Q71+r4 + umull r2,r3,r0,r1 @ ε² Q142+r4 + mov r0,r3,lsr#8 + rsb r4,#0x400 + sub r4,#0x35 + bl dpack_q + eors r1,r1,#0x80000000 + pop {r4-r8,r15} + +wrapper_func log + lsls r12,r1,#1 + bcs 1b @ x<0? + lsrs r12,#21 + beq 1b @ x==0/denormal? + sub r12,#0x3ff + cmp r12,#0x400 @ +Inf/NaN? + beq 4b + movs r2,#1 + bfi r1,r2,#20,#12 @ set implied 1, clear exponent Q52 + push {r4-r8,r14} + cmp r12,r12,asr#31 @ exponent = -1 or 0? + beq 12b +12: + lsrs r4,r1,#16 + ldr r5,=logtab0-16*8 + add r5,r5,r4,lsl#3 + ldmia r5,{r2-r3} + and r5,r2,#63 + add r5,#64 + umull r0,r6,r5,r0 + mla r1,r5,r1,r6 @ Q59 + + mvn r4,r1,asr#19 + and r4,#31 + ldr r5,=exptab1 + add r5,r5,r4,lsl#3 + ldmia r5,{r5-r6} + adds r2,r2,r5 + adc r3,r3,r6 + add r4,#256 + umull r0,r6,r4,r0 + mla r6,r4,r1,r6 @ r0:r6 Q67 + + mvns r4,r6,asr#24 + beq 10b @ small argument at this stage? +10: + ldr r5,=exptab2 + add r5,r5,r4,lsl#3 + ldmia r5,{r1,r5} + adds r2,r2,r1 + adc r3,r3,r5 + mov r5,#4097 + add r4,r5,r4,lsl#1 @ 4097+2k +11: + lsls r4,#17 + umull r5,r0,r4,r0 + rsb r1,r4,r4,lsl#3 + umlal r0,r1,r4,r6 @ Q96=Q64 + +@ r0:r1 ε Q64 +@ r2:r3 y Q64 + + eor r4,r0,r1,asr#31 + eor r5,r1,r1,asr#31 @ r4:r5 |ε| Q64 + umull r6,r7,r5,r5 + umull r4,r8,r4,r5 + lsrs r7,#1 + rrx r6,r6 + adds r6,r6,r8 + adc r7,r7,#0 @ r6:r7 ε²/2 Q64 + + movs r4,r1,lsl#10 + orrs r4,r4,r0,lsr#22 + adc r4,r4,#0 @ ε Q42, rounded + + subs r0,r0,r6 + sbc r1,r1,r7 @ r0:r1 ε-ε²/2 Q64 + + smmulr r5,r4,r4 @ ε² Q42+42-32=Q52 + smmulr r6,r5,r4 @ ε³ Q52+42-32=Q62 + smmulr r7,r5,r5 @ ε⁴ Q52+52-32=Q72 ε⁴/4 Q74 + mov r4,#0x55555555 @ 1/3 Q32 + smmulr r6,r6,r4 @ ε³/3 Q62 + subs r6,r6,r7,lsr#12 @ ε³/3-ε⁴/4 Q62 + + adds r0,r0,r6,lsl#2 @ Q64 + adc r1,r1,r6,asr#30 + + subs r0,r2,r0 + sbc r1,r3,r1 + ldr r2,=exprrdata + ldmia r2,{r2,r5} + adds r12,#1 + ble 1f +@ positive result + umull r2,r3,r2,r12 + movs r4,#0 + umlal r3,r4,r5,r12 + subs r2,r2,r0 + sbcs r3,r3,r1 + sbc r4,r4,#0 + movs r1,#0x40000000 + b 2f @ to pack result + +@ negative result +1: + rsbs r12,#0 + umull r2,r3,r2,r12 + movs r4,#0 + umlal r3,r4,r5,r12 + adds r2,r0,r2 + adcs r3,r1,r3 + adc r4,r4,#0 + movs r1,#0xc0000000 +2: + cbnz r4,2f + movs r4,r3 + movs r3,r2 + movs r2,#0 + subs r1,#32<<20 +1: +@ here r3:r4 is guaranteed nonzero + cbnz r4,2f + movs r4,r3 + movs r3,#0 + subs r1,#32<<20 +2: + clz r5,r4 + sub r6,r5,#0x1d + sub r1,r1,r6,lsl#20 + lsls r4,r5 + lsls r0,r3,r5 + rsb r5,#32 + lsrs r3,r5 + orrs r4,r4,r3 + lsrs r2,r5 + orrs r0,r0,r2 +@ now r0:r4 is normalised to Q63 + lsrs r0,#11 + adcs r0,r0,r4,lsl#21 @ with rounding + adc r1,r1,r4,lsr#11 + pop {r4-r8,r15} + +@=========================================== + +double_section trigtab +trigtab: +// φ Q64 lo φ Q64 hi sin φ Q31 cos φ Q31 +.long 0x25735c0b, 0x03f574a9, 0x01fab529, 0x7ffc1500 +.long 0x00aa2feb, 0x0c44d954, 0x0621d2c8, 0x7fda601f +.long 0x42e86336, 0x13d9d3cf, 0x09ea5e3c, 0x7f9d88f0 +.long 0x046dc42f, 0x1c0a86d9, 0x0dfe171f, 0x7f3b9ed0 +.long 0xec509ba7, 0x23ebf53e, 0x11e6e7bc, 0x7ebdefc7 +.long 0x039c1cd2, 0x2bf112b2, 0x15dcf546, 0x7e1e7749 +.long 0x3d7a05ca, 0x33f293f4, 0x19cbc014, 0x7d5fac9c +.long 0x7aefa0a0, 0x3c19321d, 0x1dc6221d, 0x7c7d2f2f +.long 0x12fb0fb5, 0x4450ef70, 0x21c10c53, 0x7b782235 +.long 0x476b8d5c, 0x4bf1a045, 0x256adc18, 0x7a68ad16 +.long 0x576940c1, 0x53ead96d, 0x29361639, 0x792f2d3c +.long 0xd34eeadf, 0x5bb34289, 0x2ce039d6, 0x77e02625 +.long 0x31ea5069, 0x641107d9, 0x30c4d3c0, 0x76586270 +.long 0xf36756cb, 0x6bfda2b3, 0x34687e1c, 0x74c77a22 +.long 0x2f7aed0e, 0x73e07531, 0x37fae7cc, 0x731c1127 +.long 0xfcc48ec0, 0x7c14790e, 0x3ba3a70e, 0x7141cd8e +.long 0x3b04b713, 0x83547b8f, 0x3ed289d4, 0x6f85d8eb +.long 0x135b369a, 0x8c0b6fd9, 0x4294ead4, 0x6d51efa3 +.long 0x4aca525f, 0x9439d326, 0x460a6e70, 0x6b230540 +.long 0x41c44083, 0x9c0e0b34, 0x4948b03d, 0x68f1ef07 +.long 0xa36d08bf, 0xa47961fd, 0x4cb1f285, 0x667a849d +.long 0xc8f81636, 0xabe547d2, 0x4fa2221e, 0x6436622f +.long 0xd0c8c9ad, 0xb3feade1, 0x52c37024, 0x61a4af86 +.long 0x64730e73, 0xbbfe356a, 0x55c5f028, 0x5f02a3a3 +.long 0xb08ca5c6, 0xc412b955, 0x58ba9208, 0x5c4194a3 +.long 0x54530090, 0xcbb02d37, 0x5b6ef419, 0x59938ed8 +.long 0xa18d7c36, 0xd3aa3c6e, 0x5e2e0225, 0x56af32fc +.long 0x48a2c7d0, 0xdbff19f6, 0x60f35332, 0x5392ed7e +.long 0x7aad9a94, 0xe422ade1, 0x638edfca, 0x50732bc7 +.long 0x19ef15ff, 0xebfb85bd, 0x65fa18bb, 0x4d5c61c7 +.long 0x7e0f96bd, 0xf44c4b49, 0x686f81f7, 0x4a0217e6 +.long 0x1def09eb, 0xfc4dbdfd, 0x6ab2d2c4, 0x46b4e413 +// maximum e=0.002617 = 0.167497*2^-6 + +double_wrapper_section atan2 + +@ datan small reduced angle case I +20: +@ r0:r1 has z=y/x in IEEE format, <2^-11 +@ r2 e+11 + rsbs r12,r2,#0 @ shift down of mantissa required to get to Q63 >0 + subs r10,r12,#32 + bge 1f @ very small reduced angle? + bfi r1,r3,#20,#12 @ fix up mantissa + cmp r7,#4 + bhs 2f @ at least one quadrant to add? then don't need extreme accuracy +@ otherwise we need to do a power series for accuracy + + rsbs r10,#0 + lsr r3,r1,r12 + lsr r2,r0,r12 + lsl r9,r1,r10 + orr r2,r9 +@ r2:r3 z Q63 (with r12 bits of loss of precision) + lsls r1,#11 + orrs r1,r1,r0,lsr#21 + lsls r0,#11 +@ r0:r1 z Q74+r12 + umull r9,r4,r2,r3 + umull r9,r5,r2,r3 + umaal r4,r5,r3,r3 +@ r4:r5 z² Q62 < 2^-22 + umull r9,r2,r0,r5 + umull r9,r3,r1,r4 + umaal r2,r3,r1,r5 +@ r2:r3 z³ Q72+r12 <2^-33 + umull r9,r6,r2,r5 + umull r9,r8,r3,r4 + umaal r6,r8,r3,r5 +@ r6:r8 z⁵ Q70+r12 <2^-55; in fact r8 is always 0 + mov r9,#0xaaaaaaaa @ 2/3 Q32 + umull r10,r4,r2,r9 + movs r5,#0 + umlal r4,r5,r3,r9 + adds r4,r4,r5 + adcs r5,r5,#0 +@ r4:r5 z³*2/3 Q72+r12 = z³/3 Q73+r12 + mov r9,#0x33333333 @ 1/5 Q32 + umull r2,r3,r6,r9 +@ r3 z⁵*1/5 Q70+r12 + subs r4,r4,r3,lsl#3 + sbc r5,r5,#0 +@ r4:r5 z³/3-z⁵/5 Q73+r12 + subs r0,r0,r4,lsl#1 + sbc r1,r1,r5,lsl#1 + sub r1,r1,r4,lsr#31 +@ r0:r1 z-z³/3+z⁵/5 Q74+r12 + rsb r4,r12,#0x400 + sub r4,#24 + b 60f @ pack and return + +2: + rsbs r10,#0 + lsls r4,r1,r10 + lsrs r0,r0,r12 + lsrs r1,r1,r12 + orrs r0,r0,r4 @ shift down r12 places + b 50f + + +1: + cmp r7,#4 + bhs 2f @ at least one quadrant to add? + eors r1,r1,r7,lsl#31 @ no: return y/x with the correct sign + pop {r4-r11,r15} + +2: + bfi r1,r3,#20,#12 @ fix up mantissa + usat r10,#6,r10 @ saturate r10 to 63 + lsrs r0,r1,r10 + movs r1,#0 @ shift down 32+r10 places + b 40f + +@ datan small reduced angle case II +10: + lsrs r1,#1 + rrxs r0,r0 + movs r2,#0 + movs r3,#0 + movs r6,#0 + mov r7,#1<<30 + b 11f + +@ case where reduced (x',y') has x' infinite +71: + sbfx r4,r1,#20,#11 + movs r0,#0 + movs r1,#0 + cmn r4,#1 @ y' also infinite? + bne 80f + movt r1,#0x3ff0 @ both infinite: pretend ∞/∞=1 + b 80f + +@ case where reduced (x',y') has y' zero +70: + ubfx r4,r3,#20,#11 + movs r0,#0 + movs r1,#0 + cbnz r4,80f @ x' also zero? + tst r7,#4 + beq 80f @ already in quadrants 0/±2? then 0/0 result will be correct + tst r7,#2 + ite eq + addeq r7,#6 + subne r7,#6 @ fix up when in quadrants ±0 + b 80f + +90: + movs r0,r2 + movs r1,r3 +91: + orrs r1,r1,#0x00080000 + bx r14 + +wrapper_func atan2 + cmp r2,#1 @ set C if low word is non-zero + adc r12,r3,r3 + cmn r12,#0x00200000 @ y NaN? + bhi 90b + cmp r0,#1 @ set C if low word is non-zero + adc r12,r1,r1 + cmn r12,#0x00200000 @ x NaN? + bhi 91b + push {r4-r11,r14} + lsrs r7,r1,#31 @ b31..2: quadrant count; b1: sign to apply before addition; b0: sign to apply after addition + bic r1,#1<<31 +@ y now positive + movs r3,r3 + bpl 1f + +@ here y positive, x negative + adds r7,#10 + bic r3,r3,#1<<31 + cmp r3,r1 + bhi 4f @ |x| > y: 3rd octant +@ |x| < y: 2nd octant + subs r7,#6 + b 3f + +1: +@ here x and y positive + cmp r3,r1 + bhi 4f +@ x < y: 1st octant + adds r7,#6 +3: + movs r4,r2 @ exchange x and y + movs r5,r3 + movs r2,r0 + movs r3,r1 + movs r0,r4 + movs r1,r5 +4: + +@ here +@ r0:r1 y' +@ r2:r3 x' +@ where both x' and y' are positive, y'/x' < 1+δ, and the final result is +@ ± (Q.π/2 ± atn y/x) where 0≤Q≤2 is a quadrant count in r7b3..2, the inner negation +@ is given by r7b1 and the outer negation by r7b0. x' can be infinite, or both x' and +@ y' can be infinite, but not y' alone. + + sbfx r4,r3,#20,#11 + cmn r4,#1 + beq 71b @ x' infinite? + ubfx r4,r1,#20,#11 + cmp r4,#0 + beq 70b @ y' zero? + bl __aeabi_ddiv +80: +@ r0:r1 y/x in IEEE format, 0..1 + lsr r2,r1,#20 @ exponent + movs r3,#1 + subs r2,#0x3ff-11 + bmi 20b + bfi r1,r3,#20,#12 @ fix up mantissa + movs r3,#1 + lsl r3,r2 + umull r0,r4,r0,r3 + mla r1,r1,r3,r4 +50: + push {r7} @ save flags + +@ from here atan2(y,1) where 1 implied +@ r0:r1 y Q63 0≤y<1+δ + + lsrs r2,r1,#16 + cmp r2,#0x100 + blo 10b @ small angle? + mul r3,r2,r2 @ y^2 + movw r4,#0x895c + muls r2,r2,r4 @ y*0x895c + movw r5,#0x1227 + lsrs r3,#14 + mls r2,r3,r5,r2 + subs r2,#0x330000 @ Chebyshev approximation to atn(y) + lsrs r2,#25 + ldr r3,=trigtab + add r3,r3,r2,lsl#4 + ldmia r3,{r2-r5} + lsrs r3,#1 + rrxs r2,r2 +@ r2:r3 phi0 Q63 +@ r4 sphi0 +@ r5 cphi0 + umull r12,r6,r4,r0 + movs r7,#0 + umlal r6,r7,r4,r1 + adds r6,r6,r5,lsl#31 + adc r7,r7,r5,lsr#1 @ x0= ((i128)cphi0<<31)+(((i128)sphi0*(i128)y)>>32); // Q62 +@ r6:r7 x0 + umull r12,r0,r5,r0 + movs r8,#0 + umlal r0,r8,r5,r1 + subs r0,r0,r4,lsl#31 + sbc r1,r8,r4,lsr#1 @ y0=-((i128)sphi0<<31)+(((i128)cphi0*(i128)y)>>32); // Q62 +11: +@ r0:r1 y0 +@ r2:r3 phi0 +@ r6:r7 x0 + + lsls r4,r1,#6 + orr r4,r4,r0,lsr#26 + lsrs r5,r7,#15 + sdiv r4,r4,r5 @ t2=(y0>>26)/(x0>>47); // Q62-26/Q62-47=Q21 + + mul r5,r4,r4 @ t2_2 Q42 + add r3,r3,r4,lsl#10 @ phi0+t2 + smull r8,r9,r4,r5 @ t2_3 Q63 + mov r10,r9,lsl#16 + orr r10,r10,r8,lsr#16 + smmulr r10,r10,r5 @ t2_5 Q57 + mov r12,#0x66666666 @ 1/5 Q33 + smmulr r11,r10,r5 @ t2_7 Q67 + smmulr r10,r10,r12 @ t2_5/5 Q57+33-32=Q58 + + movlong r12,0x124925 @ 1/7 Q23 + smmulr r11,r11,r12 @ t2_7/7 Q67+23-32=Q58 + mov r12,#0x55555555 + sub r11,r11,r11,asr#12 @ Q58 PMC correction + sub r10,r10,r11 + + adds r2,r2,r10,lsl#5 + adc r3,r3,r10,asr#27 @ Q63 phi0 + t_2 + t2_5/5 - t2_7/7 + t2_7/7/4096 + umull r5,r10,r8,r12 + mov r11,#0 + smlal r10,r11,r9,r12 @ t2_3 * 0x55555555 + adds r10,r10,r11 + adc r11,r11,r11,asr#31 @ t2_3/3 Q63 + subs r2,r2,r10 + sbc r3,r3,r11 @ Q63 phi0+phi1 + + lsls r4,r4,#11 @ t2 Q32 + umull r5,r8,r4,r0 @ t2*y0l + it mi + submi r8,r8,r0 @ correction if t2 is negative + mov r9,r8,asr#31 @ sign extend + smlal r8,r9,r4,r1 @ t2*y0h +@ r8:r9 (t2*y0)<<11 + + umull r5,r10,r4,r6 @ t2*x0l + it mi + submi r10,r10,r6 @ correction if t2 is negative + mov r11,r10,asr#31 @ sign extend + smlal r10,r11,r4,r7 +@ r10:r11 (t2*x0)<<11 + + adds r6,r8 + adc r7,r7,r9 + subs r0,r10 + sbc r1,r1,r11 +@ r0:r1 y1=y0-t2*x0 +@ r2:r3 phi0+phi1 +@ r6:r7 x1=x0+t2*y0 + + mov r4,#0xffffffff + lsrs r5,r7,#14 + udiv r4,r4,r5 @ rx1 Q16 + lsrs r5,r0,#11 + orrs r5,r5,r1,lsl#21 @ N set according to y1, hence also t3 + smmul r5,r4,r5 @ t3=(y1>>11)*rx1 Q35 + lsr r6,r6,#3 + orr r6,r6,r7,lsl#29 + umull r11,r8,r5,r6 @ t3*x1l + lsr r10,r7,#3 + it mi + submi r8,r8,r6 @ correction if t3 is negative + mla r8,r5,r10,r8 + adds r2,r2,r5,lsl#28 + adc r3,r3,r5,asr#4 + sub r0,r0,r8 +@ r0: y2 +@ r2:r3 phi0+phi1+phi2 +@ r4: rx1 +@ r5: t3 + + smull r8,r9,r0,r4 @ y2*rx1 +@ stall + lsrs r8,#14 + orr r8,r8,r9,lsl#18 @ t4 + smmlsr r0,r8,r7,r0 + adds r2,r2,r8,asr#1 + adc r3,r3,r8,asr#31 +@ r0: y3 +@ r4: rx1 + mul r4,r4,r0 + adds r0,r2,r4,asr#15 + adc r1,r3,r4,asr#31 +@ r0:r1 result over reduced range Q63 + pop {r7} @ restore flags +40: + lsrs r1,#1 + rrxs r0,r0 +@ r0:r1 result over reduced range Q62 + lsl r6,r7,#30 @ b1 -> b31 + eor r0,r0,r6,asr#31 @ negate if required + eor r1,r1,r6,asr#31 + movlong r2,0x10B4611A @ π/2 Q62 low word + movlong r3,0x6487ED51 @ π/2 Q62 high word + lsr r6,r7,#2 @ quadrants to add + umlal r0,r1,r6,r2 + mla r1,r6,r3,r1 + mov r4,#0x400-12 @ for packing Q62 +60: + bl dpack_q + eors r1,r1,r7,lsl#31 + pop {r4-r11,r15} + +#endif diff --git a/src/rp2_common/pico_double/double_v1_rom_shim.S b/src/rp2_common/pico_double/double_v1_rom_shim_rp2040.S similarity index 99% rename from src/rp2_common/pico_double/double_v1_rom_shim.S rename to src/rp2_common/pico_double/double_v1_rom_shim_rp2040.S index 88ffc0095..dc0207f4c 100644 --- a/src/rp2_common/pico_double/double_v1_rom_shim.S +++ b/src/rp2_common/pico_double/double_v1_rom_shim_rp2040.S @@ -1687,6 +1687,7 @@ dsincos_internal: bne 1b pop {r15} +.thumb_func dcos_finish: @ here @ r0:r1 ε (residual ω, where θ=α+ε) Q62, |ε|≤2^-32 (so fits in r0) @@ -1710,6 +1711,7 @@ dcos_finish: movs r2,#62 b fix642double_shim +.thumb_func dsin_finish: @ here @ r0:r1 ε (residual ω, where θ=α+ε) Q62, |ε|≤2^-32 (so fits in r0) diff --git a/src/rp2_common/pico_double/include/pico/double.h b/src/rp2_common/pico_double/include/pico/double.h index e3e8b75a3..f8c2b4dd5 100644 --- a/src/rp2_common/pico_double/include/pico/double.h +++ b/src/rp2_common/pico_double/include/pico/double.h @@ -29,32 +29,51 @@ extern "C" { * * The following additional optimized functions are also provided: * -* - fix2double, ufix2double, fix642double, ufix642double, double2fix, double2ufix, double2fix64, double2ufix64, double2int, double2int64, double2int_z, double2int64_z +* - int2double, uint2double, int642double, uint642double, fix2double, ufix2double, fix642double, ufix642double +* - double2fix, double2ufix, double2fix64, double2ufix64, double2int, double2uint, double2int64, double2uint64, double2int_z, double2int64_z, +* - exp10, sincos, powint +* +* On RP2350 the following additional functions are available; the _fast methods are faster but do not round correctly" +* +* - ddiv_fast, sqrt_fast */ +double int2double(int32_t i); +double uint2double(uint32_t u); +double int642double(int64_t i); +double uint642double(uint64_t u); double fix2double(int32_t m, int e); double ufix2double(uint32_t m, int e); double fix642double(int64_t m, int e); double ufix642double(uint64_t m, int e); // These methods round towards -Infinity. -int32_t double2fix(double f, int e); -uint32_t double2ufix(double f, int e); -int64_t double2fix64(double f, int e); -uint64_t double2ufix64(double f, int e); -int32_t double2int(double f); -int64_t double2int64(double f); +int32_t double2fix(double d, int e); +uint32_t double2ufix(double d, int e); +int64_t double2fix64(double d, int e); +uint64_t double2ufix64(double d, int e); +int32_t double2int(double d); +uint32_t double2uint(double d); +int64_t double2int64(double d); +uint64_t double2uint64(double d); // These methods round towards 0. -int32_t double2int_z(double f); -int64_t double2int64_z(double f); +int32_t double2int_z(double d); +int64_t double2int64_z(double d); double exp10(double x); void sincos(double x, double *sinx, double *cosx); double powint(double x, int y); +#if !PICO_RP2040 +double ddiv_fast(double n, double d); +double sqrt_fast(double d); +double mla(double x, double y, double z); // note this is not fused +#endif + #ifdef __cplusplus } #endif -#endif \ No newline at end of file +#endif + diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/BUILD.bazel b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/BUILD.bazel index 01b91c7a1..9a1b09366 100644 --- a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/BUILD.bazel +++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/BUILD.bazel @@ -9,9 +9,9 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_gpio", - "//src/rp2_common/pico_platform:hardware_structs", ], ) diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt index aa1a13366..b390e9578 100644 --- a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt +++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/CMakeLists.txt @@ -4,6 +4,6 @@ target_sources(pico_fix_rp2040_usb_device_enumeration INTERFACE ${CMAKE_CURRENT_LIST_DIR}/rp2040_usb_device_enumeration.c ) -target_include_directories(pico_fix_rp2040_usb_device_enumeration_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_fix_rp2040_usb_device_enumeration_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_fix_rp2040_usb_device_enumeration INTERFACE hardware_structs hardware_gpio pico_time) \ No newline at end of file diff --git a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c index 2fefb80c7..91315d193 100644 --- a/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c +++ b/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/rp2040_usb_device_enumeration.c @@ -8,8 +8,8 @@ #include "pico/time.h" #include "hardware/structs/usb.h" #include "hardware/gpio.h" -#include "hardware/structs/iobank0.h" -#include "hardware/structs/padsbank0.h" +#include "hardware/structs/io_bank0.h" +#include "hardware/structs/pads_bank0.h" #include "pico/fix/rp2040_usb_device_enumeration.h" #define LS_SE0 0b00 @@ -92,16 +92,16 @@ static void hw_enumeration_fix_force_ls_j(void) { hard_assert(gpio_get_function(dm) != 8); // Before changing any pin state, take a copy of the current gpio control register - gpio_ctrl_prev = iobank0_hw->io[dp].ctrl; + gpio_ctrl_prev = io_bank0_hw->io[dp].ctrl; // Also take a copy of the pads register - pad_ctrl_prev = padsbank0_hw->io[dp]; + pad_ctrl_prev = pads_bank0_hw->io[dp]; // Enable bus keep and force pin to tristate, so USB DP muxing doesn't affect // pin state gpio_set_pulls(dp, true, true); gpio_set_oeover(dp, GPIO_OVERRIDE_LOW); // Select function 8 (USB debug muxing) without disturbing other controls - hw_write_masked(&iobank0_hw->io[dp].ctrl, + hw_write_masked(&io_bank0_hw->io[dp].ctrl, 8 << IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB, IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS); // J state is a differential 1 for a full speed device so @@ -142,9 +142,9 @@ static void hw_enumeration_fix_finish(void) { hw_clear_bits(&usb_hw->phy_direct_override, USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS); // Finally, restore the gpio ctrl value back to GPIO15 - iobank0_hw->io[dp].ctrl = gpio_ctrl_prev; + io_bank0_hw->io[dp].ctrl = gpio_ctrl_prev; // Restore the pad ctrl value - padsbank0_hw->io[dp] = pad_ctrl_prev; + pads_bank0_hw->io[dp] = pad_ctrl_prev; } #else diff --git a/src/rp2_common/pico_flash/BUILD.bazel b/src/rp2_common/pico_flash/BUILD.bazel index 358049890..2edc05968 100644 --- a/src/rp2_common/pico_flash/BUILD.bazel +++ b/src/rp2_common/pico_flash/BUILD.bazel @@ -6,11 +6,15 @@ cc_library( name = "pico_flash", srcs = ["flash.c"], hdrs = ["include/pico/flash.h"], + defines = select({ + "//bazel/constraint:pico_freertos_unset": ["PICO_FREERTOS_LIB=0"], + "//conditions:default": ["PICO_FREERTOS_LIB=1"], + }), includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_exception", "//src/rp2_common/hardware_flash", "//src/rp2_common/hardware_sync", diff --git a/src/rp2_common/pico_flash/CMakeLists.txt b/src/rp2_common/pico_flash/CMakeLists.txt index e06b74fa9..d8e7db1be 100644 --- a/src/rp2_common/pico_flash/CMakeLists.txt +++ b/src/rp2_common/pico_flash/CMakeLists.txt @@ -4,7 +4,7 @@ target_sources(pico_flash INTERFACE ${CMAKE_CURRENT_LIST_DIR}/flash.c ) -target_include_directories(pico_flash_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_flash_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) # just include multicore headers, as we don't want to pull in the lib if it isn't pulled in already target_link_libraries(pico_flash INTERFACE pico_multicore_headers) diff --git a/src/rp2_common/pico_flash/flash.c b/src/rp2_common/pico_flash/flash.c index 038c84811..0d5606748 100644 --- a/src/rp2_common/pico_flash/flash.c +++ b/src/rp2_common/pico_flash/flash.c @@ -14,7 +14,7 @@ #include "task.h" // now we have FreeRTOS header we can check core count... we can only use FreeRTOS SMP mechanism // with two cores -#if configNUM_CORES == 2 +#if configNUMBER_OF_CORES == 2 #if configUSE_CORE_AFFINITY #define PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP 1 #else @@ -30,7 +30,7 @@ // 3. FreeRTOS on core 0, no use of core 1 - we just want to disable IRQs // 4. FreeRTOS SMP on both cores - we need to schedule a high priority task on the other core to disable IRQs. // 5. FreeRTOS on one core, but application is using the other core. ** WE CANNOT SUPPORT THIS TODAY ** without -// the equivalent PICO_FLASH_ASSUME_COREx_SAFE (i.e. the user mkaing sure the other core is fine) +// the equivalent PICO_FLASH_ASSUME_COREx_SAFE (i.e. the user making sure the other core is fine) static bool default_core_init_deinit(bool init); static int default_enter_safe_zone_timeout_ms(uint32_t timeout_ms); @@ -199,7 +199,7 @@ static int default_enter_safe_zone_timeout_ms(__unused uint32_t timeout_ms) { static int default_exit_safe_zone_timeout_ms(__unused uint32_t timeout_ms) { // assume if we're exiting we're called then entry happened successfully - restore_interrupts(irq_state[get_core_num()]); + restore_interrupts_from_disabled(irq_state[get_core_num()]); if (!use_irq_only()) { #if PICO_FLASH_SAFE_EXECUTE_USE_FREERTOS_SMP uint core_num = get_core_num(); diff --git a/src/rp2_common/pico_flash/include/pico/flash.h b/src/rp2_common/pico_flash/include/pico/flash.h index 9b0e66fd0..ae16d76d9 100644 --- a/src/rp2_common/pico_flash/include/pico/flash.h +++ b/src/rp2_common/pico_flash/include/pico/flash.h @@ -23,7 +23,7 @@ * the other core, then it has to be asked, nicely, to avoid flash for a bit. This is hard to do if you don't have * complete control of the code running on that core at all times. * - * This library provides a \ref flash_safe_execute method which calls a function back having sucessfully gotten + * This library provides a \ref flash_safe_execute method which calls a function back having successfully gotten * into a state where interrupts are disabled, and the other core is not executing or reading from flash. * * How it does this is dependent on the supported environment (Free RTOS SMP or pico_multicore). Additionally diff --git a/src/rp2_common/pico_float/BUILD.bazel b/src/rp2_common/pico_float/BUILD.bazel index 5383da1be..eac08eb87 100644 --- a/src/rp2_common/pico_float/BUILD.bazel +++ b/src/rp2_common/pico_float/BUILD.bazel @@ -1,88 +1,184 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel:defs.bzl", "compatible_with_rp2", "incompatible_with_config") package(default_visibility = ["//visibility:public"]) -cc_library( +_WRAP_FLOAT_AEABI_FLAGS = [ + "-Wl,--wrap=__aeabi_fadd", + "-Wl,--wrap=__aeabi_fdiv", + "-Wl,--wrap=__aeabi_fmul", + "-Wl,--wrap=__aeabi_frsub", + "-Wl,--wrap=__aeabi_fsub", + "-Wl,--wrap=__aeabi_cfcmpeq", + "-Wl,--wrap=__aeabi_cfrcmple", + "-Wl,--wrap=__aeabi_cfcmple", + "-Wl,--wrap=__aeabi_fcmpeq", + "-Wl,--wrap=__aeabi_fcmplt", + "-Wl,--wrap=__aeabi_fcmple", + "-Wl,--wrap=__aeabi_fcmpge", + "-Wl,--wrap=__aeabi_fcmpgt", + "-Wl,--wrap=__aeabi_fcmpun", + "-Wl,--wrap=__aeabi_i2f", + "-Wl,--wrap=__aeabi_l2f", + "-Wl,--wrap=__aeabi_ui2f", + "-Wl,--wrap=__aeabi_ul2f", + "-Wl,--wrap=__aeabi_f2iz", + "-Wl,--wrap=__aeabi_f2lz", + "-Wl,--wrap=__aeabi_f2uiz", + "-Wl,--wrap=__aeabi_f2ulz", + "-Wl,--wrap=__aeabi_f2d", + "-Wl,--wrap=sqrtf", +] + +_WRAP_FLOAT_SCI_FLAGS = [ + "-Wl,--wrap=cosf", + "-Wl,--wrap=sinf", + "-Wl,--wrap=tanf", + "-Wl,--wrap=atan2f", + "-Wl,--wrap=expf", + "-Wl,--wrap=logf", + "-Wl,--wrap=ldexpf", + "-Wl,--wrap=copysignf", + "-Wl,--wrap=truncf", + "-Wl,--wrap=floorf", + "-Wl,--wrap=ceilf", + "-Wl,--wrap=roundf", + "-Wl,--wrap=sincosf", # gnu + "-Wl,--wrap=asinf", + "-Wl,--wrap=acosf", + "-Wl,--wrap=atanf", + "-Wl,--wrap=sinhf", + "-Wl,--wrap=coshf", + "-Wl,--wrap=tanhf", + "-Wl,--wrap=asinhf", + "-Wl,--wrap=acoshf", + "-Wl,--wrap=atanhf", + "-Wl,--wrap=exp2f", + "-Wl,--wrap=log2f", + "-Wl,--wrap=exp10f", + "-Wl,--wrap=log10f", + "-Wl,--wrap=powf", + "-Wl,--wrap=powintf", # gnu + "-Wl,--wrap=hypotf", + "-Wl,--wrap=cbrtf", + "-Wl,--wrap=fmodf", + "-Wl,--wrap=dremf", + "-Wl,--wrap=remainderf", + "-Wl,--wrap=remquof", + "-Wl,--wrap=expm1f", + "-Wl,--wrap=log1pf", + "-Wl,--wrap=fmaf", +] + +alias( name = "pico_float", - srcs = [ - "float_aeabi.S", - "float_init_rom.c", - "float_math.c", - "float_v1_rom_shim.S", - ], + actual = select({ + "//bazel/constraint:pico_float_auto_enabled": ":pico_float_platform_default", + "//bazel/constraint:pico_float_compiler_enabled": ":pico_float_compiler", + "//bazel/constraint:pico_float_dcp_enabled": ":pico_float_dcp", + "//bazel/constraint:pico_float_rp2040_enabled": ":pico_float_pico", + "//bazel/constraint:pico_float_vfp_enabled": ":pico_float_vfp", + "//conditions:default": ":pico_float_none", + }), +) + +alias( + name = "pico_float_platform_default", + actual = select({ + "//bazel/constraint:rp2040": ":pico_float_pico", + "@platforms//cpu:armv8-m": ":pico_float_vfp", + "//conditions:default": ":pico_float_compiler", + }), + visibility = ["//visibility:private"], +) + +# An empty stub that just lets the compiler use M33 FPU instructions. +cc_library( + name = "pico_float_compiler", hdrs = ["include/pico/float.h"], includes = ["include"], - linkopts = [ - "-Wl,--wrap=__aeabi_fadd", - "-Wl,--wrap=__aeabi_fdiv", - "-Wl,--wrap=__aeabi_fmul", - "-Wl,--wrap=__aeabi_frsub", - "-Wl,--wrap=__aeabi_fsub", - "-Wl,--wrap=__aeabi_cfcmpeq", - "-Wl,--wrap=__aeabi_cfrcmple", - "-Wl,--wrap=__aeabi_cfcmple", - "-Wl,--wrap=__aeabi_fcmpeq", - "-Wl,--wrap=__aeabi_fcmplt", - "-Wl,--wrap=__aeabi_fcmple", - "-Wl,--wrap=__aeabi_fcmpge", - "-Wl,--wrap=__aeabi_fcmpgt", - "-Wl,--wrap=__aeabi_fcmpun", - "-Wl,--wrap=__aeabi_i2f", - "-Wl,--wrap=__aeabi_l2f", - "-Wl,--wrap=__aeabi_ui2f", - "-Wl,--wrap=__aeabi_ul2f", - "-Wl,--wrap=__aeabi_f2iz", - "-Wl,--wrap=__aeabi_f2lz", - "-Wl,--wrap=__aeabi_f2uiz", - "-Wl,--wrap=__aeabi_f2ulz", - "-Wl,--wrap=__aeabi_f2d", - "-Wl,--wrap=sqrtf", - "-Wl,--wrap=cosf", - "-Wl,--wrap=sinf", - "-Wl,--wrap=tanf", - "-Wl,--wrap=atan2f", - "-Wl,--wrap=expf", - "-Wl,--wrap=logf", - "-Wl,--wrap=ldexpf", - "-Wl,--wrap=copysignf", - "-Wl,--wrap=truncf", - "-Wl,--wrap=floorf", - "-Wl,--wrap=ceilf", - "-Wl,--wrap=roundf", - "-Wl,--wrap=sincosf", - "-Wl,--wrap=asinf", - "-Wl,--wrap=acosf", - "-Wl,--wrap=atanf", - "-Wl,--wrap=sinhf", - "-Wl,--wrap=coshf", - "-Wl,--wrap=tanhf", - "-Wl,--wrap=asinhf", - "-Wl,--wrap=acoshf", - "-Wl,--wrap=atanhf", - "-Wl,--wrap=exp2f", - "-Wl,--wrap=log2f", - "-Wl,--wrap=exp10f", - "-Wl,--wrap=log10f", - "-Wl,--wrap=powf", - "-Wl,--wrap=powintf", - "-Wl,--wrap=hypotf", - "-Wl,--wrap=cbrtf", - "-Wl,--wrap=fmodf", - "-Wl,--wrap=dremf", - "-Wl,--wrap=remainderf", - "-Wl,--wrap=remquof", - "-Wl,--wrap=expm1f", - "-Wl,--wrap=log1pf", - "-Wl,--wrap=fmaf", - ], target_compatible_with = compatible_with_rp2(), +) + +# This highlights the differences between the various float implementations. +# Most of the cc_library attributes are shared, so this prevents significant +# duplication. +_PICO_FLOAT_IMPLS = [ + { + "name": "pico", # RP2040-specific float implementation. + "srcs": [ + "float_aeabi_rp2040.S", + "float_init_rom_rp2040.c", + "float_math.c", + "float_v1_rom_shim_rp2040.S", + ], + "compatibility": incompatible_with_config("@platforms//cpu:riscv32") + ["//bazel/constraint:rp2040"], + "extra_deps": [], + "linkopts": _WRAP_FLOAT_AEABI_FLAGS + _WRAP_FLOAT_SCI_FLAGS, + }, + { + "name": "dcp", + "srcs": [ + "float_aeabi_dcp.S", + "float_conv_m33.S", + "float_math.c", + "float_sci_m33.S", + ], + "compatibility": compatible_with_rp2() + incompatible_with_config("@platforms//cpu:riscv32") + incompatible_with_config("//bazel/constraint:rp2040"), + "extra_deps": ["//src/rp2_common/hardware_dcp"], + "linkopts": _WRAP_FLOAT_SCI_FLAGS, + }, + { + "name": "vfp", + "srcs": [ + "float_sci_m33_vfp.S", + "float_conv_m33.S", + "float_math.c", + ], + "compatibility": compatible_with_rp2() + incompatible_with_config("@platforms//cpu:riscv32") + incompatible_with_config("//bazel/constraint:rp2040"), + "extra_deps": ["//src/rp2_common/hardware_dcp"], + "linkopts": _WRAP_FLOAT_SCI_FLAGS, + }, +] + +# Creates: +# * pico_float_pico +# * pico_float_dcp +# * pico_float_vfp +[ + cc_library( + name = "pico_float_{}".format(impl["name"]), + srcs = impl["srcs"], + hdrs = ["include/pico/float.h"], + defines = [ + "LIB_PICO_FLOAT_PICO=1", + "LIB_PICO_FLOAT_PICO_{}=1".format(impl["name"].upper()), + ], + includes = ["include"], + linkopts = impl["linkopts"], + target_compatible_with = impl["compatibility"], + visibility = ["//visibility:private"], + deps = [ + "//src/rp2_common:pico_platform", + "//src/rp2_common/hardware_divider", + "//src/rp2_common/pico_bootrom", + ] + impl["extra_deps"], + alwayslink = True, # Ensures the wrapped symbols are linked in. + ) + for impl in _PICO_FLOAT_IMPLS +] + +cc_library( + name = "pico_float_none", + srcs = ["float_none.S"], + hdrs = ["include/pico/float.h"], + defines = ["LIB_PICO_FLOAT_PICO=0"], + includes = ["include"], + linkopts = _WRAP_FLOAT_AEABI_FLAGS + _WRAP_FLOAT_SCI_FLAGS, + target_compatible_with = compatible_with_rp2(), + visibility = ["//visibility:private"], deps = [ - "//src/common/pico_base", - "//src/rp2_common/hardware_divider", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) - -# TODO: Support float_none.S when the configuration option exists. diff --git a/src/rp2_common/pico_float/CMakeLists.txt b/src/rp2_common/pico_float/CMakeLists.txt index 0f3107ded..086628221 100644 --- a/src/rp2_common/pico_float/CMakeLists.txt +++ b/src/rp2_common/pico_float/CMakeLists.txt @@ -1,105 +1,135 @@ -if (NOT TARGET pico_float) + if (NOT TARGET pico_float) # library to be depended on - we make this depend on particular implementations using per target generator expressions pico_add_library(pico_float) # no custom implementation; falls thru to compiler pico_add_library(pico_float_compiler) - target_include_directories(pico_float_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_float_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) - # add alias "default" which is just rom. + + # add alias "default" which is just pico. add_library(pico_float_default INTERFACE) - target_link_libraries(pico_float_default INTERFACE pico_float_pico) + if (PICO_RISCV) + target_link_libraries(pico_float_default INTERFACE pico_float_compiler) + else() + target_link_libraries(pico_float_default INTERFACE pico_float_pico) + endif() set(PICO_DEFAULT_FLOAT_IMPL pico_float_default) target_link_libraries(pico_float INTERFACE $>,$,${PICO_DEFAULT_FLOAT_IMPL}>) - pico_add_library(pico_float_pico) - target_sources(pico_float_pico INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/float_aeabi.S - ${CMAKE_CURRENT_LIST_DIR}/float_init_rom.c - ${CMAKE_CURRENT_LIST_DIR}/float_math.c - ${CMAKE_CURRENT_LIST_DIR}/float_v1_rom_shim.S - ) + function(wrap_float_functions TARGET) + cmake_parse_arguments(WRAP_FLOAT "NO_WRAP_AEABI;NO_WRAP_SCI" "" "" ${ARGN} ) + if (NOT WRAP_FLOAT_NO_WRAP_AEABI) + pico_wrap_function(${TARGET} __aeabi_fadd) + pico_wrap_function(${TARGET} __aeabi_fdiv) + pico_wrap_function(${TARGET} __aeabi_fmul) + pico_wrap_function(${TARGET} __aeabi_frsub) + pico_wrap_function(${TARGET} __aeabi_fsub) + pico_wrap_function(${TARGET} __aeabi_cfcmpeq) + pico_wrap_function(${TARGET} __aeabi_cfrcmple) + pico_wrap_function(${TARGET} __aeabi_cfcmple) + pico_wrap_function(${TARGET} __aeabi_fcmpeq) + pico_wrap_function(${TARGET} __aeabi_fcmplt) + pico_wrap_function(${TARGET} __aeabi_fcmple) + pico_wrap_function(${TARGET} __aeabi_fcmpge) + pico_wrap_function(${TARGET} __aeabi_fcmpgt) + pico_wrap_function(${TARGET} __aeabi_fcmpun) + pico_wrap_function(${TARGET} __aeabi_i2f) + pico_wrap_function(${TARGET} __aeabi_l2f) + pico_wrap_function(${TARGET} __aeabi_ui2f) + pico_wrap_function(${TARGET} __aeabi_ul2f) + pico_wrap_function(${TARGET} __aeabi_f2iz) + pico_wrap_function(${TARGET} __aeabi_f2lz) + pico_wrap_function(${TARGET} __aeabi_f2uiz) + pico_wrap_function(${TARGET} __aeabi_f2ulz) + pico_wrap_function(${TARGET} __aeabi_f2d) + pico_wrap_function(${TARGET} sqrtf) + endif() + if (NOT WRAP_FLOAT_NO_WRAP_SCI) + pico_wrap_function(${TARGET} cosf) + pico_wrap_function(${TARGET} sinf) + pico_wrap_function(${TARGET} tanf) + pico_wrap_function(${TARGET} atan2f) + pico_wrap_function(${TARGET} expf) + pico_wrap_function(${TARGET} logf) - target_link_libraries(pico_float_pico INTERFACE pico_bootrom pico_float_headers hardware_divider) + pico_wrap_function(${TARGET} ldexpf) + pico_wrap_function(${TARGET} copysignf) + pico_wrap_function(${TARGET} truncf) + pico_wrap_function(${TARGET} floorf) + pico_wrap_function(${TARGET} ceilf) + pico_wrap_function(${TARGET} roundf) + pico_wrap_function(${TARGET} sincosf) # gnu + pico_wrap_function(${TARGET} asinf) + pico_wrap_function(${TARGET} acosf) + pico_wrap_function(${TARGET} atanf) + pico_wrap_function(${TARGET} sinhf) + pico_wrap_function(${TARGET} coshf) + pico_wrap_function(${TARGET} tanhf) + pico_wrap_function(${TARGET} asinhf) + pico_wrap_function(${TARGET} acoshf) + pico_wrap_function(${TARGET} atanhf) + pico_wrap_function(${TARGET} exp2f) + pico_wrap_function(${TARGET} log2f) + pico_wrap_function(${TARGET} exp10f) + pico_wrap_function(${TARGET} log10f) + pico_wrap_function(${TARGET} powf) + pico_wrap_function(${TARGET} powintf) #gnu + pico_wrap_function(${TARGET} hypotf) + pico_wrap_function(${TARGET} cbrtf) + pico_wrap_function(${TARGET} fmodf) + pico_wrap_function(${TARGET} dremf) + pico_wrap_function(${TARGET} remainderf) + pico_wrap_function(${TARGET} remquof) + pico_wrap_function(${TARGET} expm1f) + pico_wrap_function(${TARGET} log1pf) + pico_wrap_function(${TARGET} fmaf) + endif() + endfunction() pico_add_library(pico_float_none) target_sources(pico_float_none INTERFACE ${CMAKE_CURRENT_LIST_DIR}/float_none.S - ) + ) target_link_libraries(pico_float_none INTERFACE pico_float_headers) + wrap_float_functions(pico_float_none) - function(wrap_float_functions TARGET) - pico_wrap_function(${TARGET} __aeabi_fadd) - pico_wrap_function(${TARGET} __aeabi_fdiv) - pico_wrap_function(${TARGET} __aeabi_fmul) - pico_wrap_function(${TARGET} __aeabi_frsub) - pico_wrap_function(${TARGET} __aeabi_fsub) - pico_wrap_function(${TARGET} __aeabi_cfcmpeq) - pico_wrap_function(${TARGET} __aeabi_cfrcmple) - pico_wrap_function(${TARGET} __aeabi_cfcmple) - pico_wrap_function(${TARGET} __aeabi_fcmpeq) - pico_wrap_function(${TARGET} __aeabi_fcmplt) - pico_wrap_function(${TARGET} __aeabi_fcmple) - pico_wrap_function(${TARGET} __aeabi_fcmpge) - pico_wrap_function(${TARGET} __aeabi_fcmpgt) - pico_wrap_function(${TARGET} __aeabi_fcmpun) - pico_wrap_function(${TARGET} __aeabi_i2f) - pico_wrap_function(${TARGET} __aeabi_l2f) - pico_wrap_function(${TARGET} __aeabi_ui2f) - pico_wrap_function(${TARGET} __aeabi_ul2f) - pico_wrap_function(${TARGET} __aeabi_f2iz) - pico_wrap_function(${TARGET} __aeabi_f2lz) - pico_wrap_function(${TARGET} __aeabi_f2uiz) - pico_wrap_function(${TARGET} __aeabi_f2ulz) - pico_wrap_function(${TARGET} __aeabi_f2d) - pico_wrap_function(${TARGET} sqrtf) - pico_wrap_function(${TARGET} cosf) - pico_wrap_function(${TARGET} sinf) - pico_wrap_function(${TARGET} tanf) - pico_wrap_function(${TARGET} atan2f) - pico_wrap_function(${TARGET} expf) - pico_wrap_function(${TARGET} logf) + pico_add_library(pico_float_pico) + if (PICO_RP2040) + target_sources(pico_float_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/float_aeabi_rp2040.S + ${CMAKE_CURRENT_LIST_DIR}/float_init_rom_rp2040.c + ${CMAKE_CURRENT_LIST_DIR}/float_math.c + ${CMAKE_CURRENT_LIST_DIR}/float_v1_rom_shim_rp2040.S + ) + wrap_float_functions(pico_float_pico) + target_link_libraries(pico_float_pico INTERFACE pico_bootrom pico_float_headers hardware_divider) + elseif(NOT PICO_RISCV) + pico_add_library(pico_float_pico_dcp) + target_sources(pico_float_pico_dcp INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/float_math.c + ${CMAKE_CURRENT_LIST_DIR}/float_aeabi_dcp.S + ${CMAKE_CURRENT_LIST_DIR}/float_sci_m33.S + ${CMAKE_CURRENT_LIST_DIR}/float_conv_m33.S + ) - pico_wrap_function(${TARGET} ldexpf) - pico_wrap_function(${TARGET} copysignf) - pico_wrap_function(${TARGET} truncf) - pico_wrap_function(${TARGET} floorf) - pico_wrap_function(${TARGET} ceilf) - pico_wrap_function(${TARGET} roundf) - pico_wrap_function(${TARGET} sincosf) # gnu - pico_wrap_function(${TARGET} asinf) - pico_wrap_function(${TARGET} acosf) - pico_wrap_function(${TARGET} atanf) - pico_wrap_function(${TARGET} sinhf) - pico_wrap_function(${TARGET} coshf) - pico_wrap_function(${TARGET} tanhf) - pico_wrap_function(${TARGET} asinhf) - pico_wrap_function(${TARGET} acoshf) - pico_wrap_function(${TARGET} atanhf) - pico_wrap_function(${TARGET} exp2f) - pico_wrap_function(${TARGET} log2f) - pico_wrap_function(${TARGET} exp10f) - pico_wrap_function(${TARGET} log10f) - pico_wrap_function(${TARGET} powf) - pico_wrap_function(${TARGET} powintf) #gnu - pico_wrap_function(${TARGET} hypotf) - pico_wrap_function(${TARGET} cbrtf) - pico_wrap_function(${TARGET} fmodf) - pico_wrap_function(${TARGET} dremf) - pico_wrap_function(${TARGET} remainderf) - pico_wrap_function(${TARGET} remquof) - pico_wrap_function(${TARGET} expm1f) - pico_wrap_function(${TARGET} log1pf) - pico_wrap_function(${TARGET} fmaf) - endfunction() + wrap_float_functions(pico_float_pico_dcp NO_WRAP_AEABI) + pico_add_library(pico_float_pico_vfp) + target_sources(pico_float_pico_vfp INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/float_math.c + ${CMAKE_CURRENT_LIST_DIR}/float_sci_m33_vfp.S + ${CMAKE_CURRENT_LIST_DIR}/float_conv_m33.S + ) + wrap_float_functions(pico_float_pico_vfp NO_WRAP_AEABI) + target_link_libraries(pico_float_pico INTERFACE + pico_float_pico_vfp) + endif() - wrap_float_functions(pico_float_pico) - wrap_float_functions(pico_float_none) macro(pico_set_float_implementation TARGET IMPL) get_target_property(target_type ${TARGET} TYPE) diff --git a/src/rp2_common/pico_float/float_aeabi_dcp.S b/src/rp2_common/pico_float/float_aeabi_dcp.S new file mode 100644 index 000000000..61c240919 --- /dev/null +++ b/src/rp2_common/pico_float/float_aeabi_dcp.S @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#if HAS_DOUBLE_COPROCESSOR +#include "hardware/dcp_instr.inc.S" +#include "hardware/dcp_canned.inc.S" + +pico_default_asm_setup + +// todo alignment +//__pre_init __aeabi_float_init, 00020 +// factor out save/restore (there is a copy in double code) + +.macro float_section name +#if PICO_FLOAT_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro float_wrapper_section func +float_section WRAPPER_FUNC_NAME(\func) +.endm + +// ============== STATE SAVE AND RESTORE =============== + +.macro saving_func func + // Note we are usually 32-bit aligned already at this point, as most of the + // function bodies contain exactly two 16-bit instructions: bmi and bx lr. + // We want the PCMP word-aligned. +.p2align 2 + // When the engaged flag is set, branch back here to invoke save routine and + // hook lr with the restore routine, then fall back through to the entry + // point. The engaged flag will be clear when checked a second time. +1: + push {lr} // 16-bit instruction + bl generic_save_state // 32-bit instruction + b 1f // 16-bit instruction + // This is the actual entry point: +wrapper_func \func + PCMP apsr_nzcv + bmi 1b +1: +.endm + +.macro saving_func_return + bx lr +.endm + +float_section __rp2350_dcp_engaged_state_save_restore +.thumb_func +generic_save_state: + sub sp, #24 + push {r0, r1} + // do save here + PXMD r0, r1 + strd r0, r1, [sp, #8 + 0] + PYMD r0, r1 + strd r0, r1, [sp, #8 + 8] + REFD r0, r1 + strd r0, r1, [sp, #8 + 16] + pop {r0, r1} + blx lr + // <- wrapped function returns here + // fall through into restore: +.thumb_func +generic_restore_state: + // do restore here + pop {r12, r14} + WXMD r12, r14 + pop {r12, r14} + WYMD r12, r14 + pop {r12, r14} + WEFD r12, r14 + pop {pc} + +// ============== ARITHMETIC FUNCTIONS =============== + +float_wrapper_section __aeabi_fadd +saving_func __aeabi_fadd + dcp_fadd_m r0,r0,r1 + saving_func_return + +float_wrapper_section __aeabi_fsub +saving_func __aeabi_fsub + dcp_fsub_m r0,r0,r1 + saving_func_return + +float_wrapper_section __aeabi_frsub +saving_func __aeabi_frsub + dcp_fsub_m r0,r1,r0 + saving_func_return + +float_wrapper_section __aeabi_fmul +saving_func __aeabi_fmul + dcp_fmul_m r0,r0,r1,r0,r1 + saving_func_return + +float_section fdiv_fast +saving_func fdiv_fast + dcp_fdiv_fast_m r0,r0,r1,r0,r1,r2 + saving_func_return + +float_wrapper_section __aeabi_fdiv +saving_func __aeabi_fdiv +@ with correct rounding + dcp_fdiv_m r0,r0,r1,r0,r1,r2,r3 + saving_func_return + +float_section sqrtf_fast +saving_func sqrtf_fast + dcp_fsqrt_fast_m r0,r0,r0,r1,r2,r3 + saving_func_return + +float_wrapper_section sqrtf +saving_func sqrtf +@ with correct rounding + dcp_fsqrt_m r0,r0,r0,r1,r2,r3 + saving_func_return + +// todo not a real thing +float_wrapper_section __aeabi_fclassify +saving_func __aeabi_fclassify + dcp_fclassify_m apsr_nzcv,r0 + saving_func_return + +// ============== CONVERSION FUNCTIONS =============== + +float_wrapper_section __aeabi_f2d +saving_func __aeabi_f2d + dcp_float2double_m r0,r1,r0 + saving_func_return + +float_wrapper_section __aeabi_i2f +saving_func __aeabi_i2f +@ with rounding + dcp_int2float_m r0,r0 + saving_func_return + +float_wrapper_section __aeabi_ui2f +saving_func __aeabi_ui2f +@ with rounding + dcp_uint2float_m r0,r0 + saving_func_return + +float_wrapper_section __aeabi_f2iz +saving_func __aeabi_f2iz +@ with truncation towards 0 + dcp_float2int_m r0,r0 + saving_func_return + +float_wrapper_section __aeabi_f2uiz +saving_func __aeabi_f2uiz +@ with truncation towards 0 + dcp_float2uint_m r0,r0 + saving_func_return + +// todo not a real thing +float_wrapper_section __aeabi_f2i_r +saving_func __aeabi_f2i_r +@ with rounding + dcp_float2int_r_m r0,r0 + saving_func_return + +// todo not a real thing +float_wrapper_section __aeabi_f2ui_r +saving_func __aeabi_f2ui_r +@ with rounding + dcp_float2uint_r_m r0,r0 + saving_func_return + +// ============== COMPARISON FUNCTIONS =============== + +float_wrapper_section __aeabi_fcmpun +saving_func __aeabi_fcmpun + dcp_fcmp_m r0,r0,r1 + // extract unordered bit + ubfx r0, r0, #28, #1 + saving_func_return + +float_wrapper_section __aeabi_fcmp +saving_func __aeabi_cfrcmple + dcp_fcmp_m apsr_nzcv,r1,r0 // with arguments reversed + bvs cmp_nan + saving_func_return + +// these next two can be the same function in the absence of exceptions +saving_func __aeabi_cfcmple + dcp_fcmp_m apsr_nzcv,r0,r1 + bvs cmp_nan + saving_func_return + +// It is not clear from the ABI documentation whether cfcmpeq must set the C flag +// in the same way as cfcmple. If not, we could save the "bvs" below; but we +// err on the side of caution. +saving_func __aeabi_cfcmpeq + dcp_fcmp_m apsr_nzcv,r0,r1 + bvs cmp_nan + saving_func_return + +// If the result of a flag-setting comparison is "unordered" then we need to set C and clear Z. +// We could conceivably just do lsrs r12,r14,#1, or even cmp r14,r14,lsr#1 as (a) r14 here is a +// return address and r14b0=1 for Thumb mode; (b) we are unlikely to be returning to address 0. +cmp_nan: + movs r12, #3 // r12 does not need to be preserved by the flag-setting comparisons + lsrs r12, #1 // set C, clear Z + saving_func_return + +float_wrapper_section __aeabi_fcmpeq +saving_func __aeabi_fcmpeq + dcp_fcmp_m r0,r0,r1 + // extract Z + ubfx r0, r0, #30, #1 + saving_func_return + +float_wrapper_section __aeabi_fcmplt +saving_func __aeabi_fcmplt + dcp_fcmp_m apsr_nzcv,r1,r0 + ite hi + movhi r0,#1 + movls r0,#0 + saving_func_return + +float_wrapper_section __aeabi_fcmple +saving_func __aeabi_fcmple + dcp_fcmp_m apsr_nzcv,r1,r0 + ite hs + movhs r0,#1 + movlo r0,#0 + saving_func_return + +float_wrapper_section __aeabi_fcmpge +saving_func __aeabi_fcmpge + dcp_fcmp_m apsr_nzcv,r0,r1 + ite hs + movhs r0,#1 + movlo r0,#0 + saving_func_return + +float_wrapper_section __aeabi_fcmpgt +saving_func __aeabi_fcmpgt + dcp_fcmp_m apsr_nzcv,r0,r1 + ite hi + movhi r0,#1 + movls r0,#0 + saving_func_return + +#endif diff --git a/src/rp2_common/pico_float/float_aeabi.S b/src/rp2_common/pico_float/float_aeabi_rp2040.S similarity index 98% rename from src/rp2_common/pico_float/float_aeabi.S rename to src/rp2_common/pico_float/float_aeabi_rp2040.S index e2862b5ce..8eb83fc22 100644 --- a/src/rp2_common/pico_float/float_aeabi.S +++ b/src/rp2_common/pico_float/float_aeabi_rp2040.S @@ -5,10 +5,11 @@ */ #include "pico/asm_helper.S" +#include "pico/runtime_init.h" #include "pico/bootrom/sf_table.h" #include "hardware/divider_helper.S" -__pre_init __aeabi_float_init, 00020 +PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_float_init, PICO_RUNTIME_INIT_AEABI_FLOAT) pico_default_asm_setup @@ -364,6 +365,7 @@ wrapper_func __aeabi_fcmpun // float FUNC_NAME(__aeabi_ui2f)(unsigned) unsigned to float (single precision) conversion float_wrapper_section __aeabi_ui2f wrapper_func __aeabi_ui2f +regular_func uint2float subs r1, r1 cmp r0, #0 bne __aeabi_i2f_main @@ -373,6 +375,7 @@ wrapper_func __aeabi_ui2f float_wrapper_section __aeabi_i2f // float FUNC_NAME(__aeabi_i2f)(int) integer to float (single precision) conversion wrapper_func __aeabi_i2f +regular_func int2float lsrs r1, r0, #31 lsls r1, #31 bpl 1f @@ -479,6 +482,7 @@ regular_func float2ufix // unsigned FUNC_NAME(__aeabi_f2uiz)(float) float (single precision) to unsigned C-style conversion [3] float_wrapper_section __aeabi_f2uiz wrapper_func __aeabi_f2uiz +regular_func float2uint_z table_tail_call SF_TABLE_FLOAT2UINT float_section fix2float @@ -503,6 +507,7 @@ float_wrapper_section __aeabi_l2f ldr r2, =__aeabi_i2f bx r2 wrapper_func __aeabi_l2f +regular_func int642float asrs r2, r0, #31 cmp r1, r2 beq 1b @@ -514,6 +519,7 @@ float_wrapper_section __aeabi_ul2f ldr r2, =__aeabi_ui2f bx r2 wrapper_func __aeabi_ul2f +regular_func uint642float cmp r1, #0 beq 1b shimmable_table_tail_call SF_TABLE_UINT642FLOAT uint642float_shim @@ -553,6 +559,7 @@ regular_func float2fix64 // unsigned long long FUNC_NAME(__aeabi_f2ulz)(float) float to unsigned long long C-style conversion [3] float_wrapper_section __aeabi_f2ulz wrapper_func __aeabi_f2ulz +regular_func float2uint64_z shimmable_table_tail_call SF_TABLE_FLOAT2UINT64 float2uint64_shim float_section float2ufix64 diff --git a/src/rp2_common/pico_float/float_conv_m33.S b/src/rp2_common/pico_float/float_conv_m33.S new file mode 100644 index 000000000..dd47a939e --- /dev/null +++ b/src/rp2_common/pico_float/float_conv_m33.S @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !PICO_RP2040 +#include "pico/asm_helper.S" + +pico_default_asm_setup + +.macro float_section name +#if PICO_FLOAT_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro float_wrapper_section func +float_section WRAPPER_FUNC_NAME(\func) +.endm + +float_wrapper_section conv_tof + +@ convert int64 to float, rounding +wrapper_func __aeabi_l2f +regular_func int642float + movs r2,#0 @ fall through +@ convert signed 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 +regular_func fix642float + cmp r1,#0 + bge 10f @ positive? use unsigned code + rsbs r0,#0 + sbc r1,r1,r1,lsl#1 @ make positive + cbz r1,7f @ high word is zero? + clz r3,r1 + subs r3,#8 + bmi 2f + lsls r1,r3 + lsls r12,r0,r3 @ bits that will be lost + rsb r3,#32 + lsr r0,r3 + orr r0,r0,r1 + sub r2,r2,r3 + rsb r2,#149 + adds r12,r12,r12 @ rounding bit into carry + adc r0,r0,r2,lsl#23 @ insert exponent, add rounding + orr r0,r0,#0x80000000 + beq 4f @ potential rounding tie? + cmp r2,#0xfe + bhs 3f @ over/underflow? + bx r14 +2: + add r3,#33 + lsls r12,r1,r3 @ rounding bit in carry, sticky bits in r12 + orrs r12,r12,r0 @ all of low word into sticky bits: affects Z but not C + rsb r3,#33 + lsr r0,r1,r3 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r2 + add r2,#22+127+32 + adc r0,r0,r2,lsl#23 @ insert exponent, add rounding + orr r0,r0,#0x80000000 + beq 4f @ potential rounding tie? + cmp r2,#0xfe + it lo + bxlo r14 +@ over/underflow? +3: + mov r0,#0x80000000 @ underflow + it ge + movtge r0,#0xff80 @ overflow +1: + bx r14 +7: + mov r1,r2 + b fix2float_neg +4: + it cs @ rounding tie? + biccs r0,r0,#1 @ force to even if we rounded up + cmp r2,#0xfe + it lo + bxlo r14 + b 3b + +@ convert signed 32-bit fix to float, rounding; number of r0 bits after point in r1 +.thumb_func +regular_func fix2float + cmp r0,#0 + bge ufix2float @ positive? can use unsigned code + rsbs r0,#0 @ make positive +fix2float_neg: + clz r3,r0 + subs r3,#8 + bmi 2f + lsls r0,r3 + add r2,r1,r3 + rsb r2,#149 + add r0,r0,r2,lsl#23 @ insert exponent + orr r0,#0x80000000 + cmp r2,#0xfe + it lo @ over/underflow? + bxlo r14 + b 3f +2: + add r3,#33 + lsls r12,r0,r3 @ rounding bit in carry, sticky bits in r12 + rsb r3,#33 + lsr r0,r3 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r1 + add r2,#22+127 + adc r0,r0,r2,lsl#23 @ insert exponent + orr r0,#0x80000000 + beq 4f @ potential rounding tie? + cmp r2,#0xfe + it lo + bxlo r14 +@ over/underflow? +3: + mov r0,#0x80000000 @ underflow + it ge + orrge r0,#0x7f800000 @ overflow +1: + bx r14 +4: + it cs @ rounding tie? + biccs r0,r0,#1 @ force to even if we rounded up + cmp r2,#0xfe + it lo + bxlo r14 + b 3b + +@ convert unsigned 32-bit fix to float, rounding; number of r0 bits after point in r1 +regular_func ufix2float + cbz r0,1f @ zero? return it + clz r3,r0 + subs r3,#8 + bmi 2f + lsls r0,r3 + add r2,r1,r3 + rsb r2,#149 + add r0,r0,r2,lsl#23 @ insert exponent +@ push {r14} +@ bl dumpreg +@ pop {r14} + cmp r2,#0xfe + it lo @ over/underflow? + bxlo r14 + b 3f +2: + add r3,#33 + lsls r12,r0,r3 @ rounding bit in carry, sticky bits in r12 + rsb r3,#33 + lsr r0,r3 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r1 + add r2,#22+127 + adc r0,r0,r2,lsl#23 @ insert exponent + beq 4f @ potential rounding tie? + cmp r2,#0xfe + it lo + bxlo r14 +@ over/underflow? +3: + ite ge + movge r0,#0x7f800000 @ overflow + movlt r0,#0x00000000 @ underflow +1: + bx r14 +4: + it cs @ rounding tie? + biccs r0,r0,#1 @ force to even if we rounded up + cmp r2,#0xfe + it lo + bxlo r14 + b 3b + +@ convert uint64 to float, rounding +wrapper_func __aeabi_ul2f +regular_func uint642float + movs r2,#0 @ fall through +@ convert unsigned 64-bit fix to float, rounding; number of r0:r1 bits after point in r2 +regular_func ufix642float +10: + cbz r1,7f @ high word is zero? + clz r3,r1 + subs r3,#8 + bmi 2f + lsls r1,r3 + lsls r12,r0,r3 @ bits that will be lost + rsb r3,#32 + lsr r0,r3 + orr r0,r0,r1 + sub r2,r2,r3 + rsb r2,#149 + adds r12,r12,r12 @ rounding bit into carry + adc r0,r0,r2,lsl#23 @ insert exponent, add rounding + beq 4f @ potential rounding tie? + cmp r2,#0xfe + bhs 3f @ over/underflow? + bx r14 +2: + add r3,#33 + lsls r12,r1,r3 @ rounding bit in carry, sticky bits in r12 + orrs r12,r12,r0 @ all of low word into sticky bits: affects Z but not C + rsb r3,#33 + lsr r0,r1,r3 +@ push {r14} +@ bl dumpreg +@ pop {r14} + sub r2,r3,r2 + add r2,#22+127+32 + adc r0,r0,r2,lsl#23 @ insert exponent, add rounding + beq 4f @ potential rounding tie? + cmp r2,#0xfe + it lo + bxlo r14 +@ over/underflow? +3: + ite ge + movge r0,#0x7f800000 @ overflow + movlt r0,#0x00000000 @ underflow +1: + bx r14 +7: + mov r1,r2 + b ufix2float +4: + it cs @ rounding tie? + biccs r0,r0,#1 @ force to even if we rounded up + cmp r2,#0xfe + it lo + bxlo r14 + b 3b + +float_wrapper_section conv_ftoi64 + +@ convert float to signed int64, rounding towards 0, clamping +wrapper_func __aeabi_f2lz +regular_func float2int64_z + movs r1,#0 @ fall through +@ convert float in r0 to signed fixed point in r0:r1, clamping +regular_func float2fix64_z + subs r1,#0x95 @ remove exponent bias, compensate for mantissa length + asrs r2,r0,#23 @ sign and exponent + sub r3,r2,#1 + sub r0,r0,r3,lsl#23 @ install implied 1, clear exponent + uxtb r3,r3 + cmp r3,#0xfe + bhs 1f @ 0 or Inf/NaN? + adds r1,r3 @ offset exponent by fix precision; r1 is now required left shift + bmi 4f @ actually a right shift? + subs r3,r1,#32 @ result fits in high 32 bits only? + bge 8f + subs r3,r1,#8 @ result fits in low 32 bits only? + ble 7f + lsls r0,#8 + rsbs r1,r3,#32 + lsrs r1,r0,r1 + lsls r0,r3 + cmp r2,#0 + it ge + bxge r14 + rsbs r0,#0 @ negate if necessary + sbcs r1,r1,r1,lsl#1 + bx r14 +7: + lsls r0,r0,r1 + movs r1,r2,asr#31 @ sign extend + eors r0,r0,r1 @ negate if necessary + subs r0,r0,r1 + bx r14 +8: + cmp r3,#8 @ overflow? + bge 5f + lsls r0,r0,r3 + eor r1,r0,r2,asr#31 @ negate if necessary + add r1,r1,r2,lsr#31 + movs r0,#0 + bx r14 +1: + bhi 3f @ 0? + lsls r1,r0,#9 @ mantissa field + it ne @ NaN? + movne r2,#0 @ treat NaNs as +∞ +5: + mvn r1,#0x80000000 @ = 0x7fffffff + add r1,r1,r2,lsr#31 @ so -Inf → 0x80000000, +Inf → 0x7fffffff + mvn r0,r2,asr#31 + bx r14 +3: + movs r0,#0 + movs r1,#0 + bx r14 +4: + rsbs r1,#0 + usat r1,#5,r1 + lsrs r0,r0,r1 + eors r0,r0,r2,asr#31 @ negate if necessary + adds r0,r0,r2,lsr#31 + movs r1,r0,asr#31 @ sign extend + bx r14 + +float_wrapper_section conv_ftoui64 + +@ convert float to unsigned int64, rounding towards -Inf, clamping +wrapper_func __aeabi_f2ulz +regular_func float2uint64 +regular_func float2uint64_z + movs r1,#0 @ fall through +@ convert float in r0 to unsigned fixed point in r0:r1, clamping +regular_func float2ufix64 +//regular_func float2ufix64_z + subs r1,#0x96 @ remove exponent bias, compensate for mantissa length + asrs r2,r0,#23 @ sign and exponent + sub r3,r2,#1 + cmp r3,#0xfe + bhs 1f @ -ve, 0 or Inf/NaN? + sub r0,r0,r3,lsl#23 @ install implied 1, clear exponent + adds r1,r2 @ offset exponent by fix precision; r1 is now required left shift + bmi 4f @ actually a right shift? + subs r2,r1,#7 + ble 7f @ result (easily) fits in lo 32 bits? + subs r3,r1,#32 + bge 8f @ results might fit in hi 32 bits? + lsls r0,r0,#7 + rsbs r3,r2,#32 + lsrs r1,r0,r3 + lsls r0,r0,r2 + bx r14 +7: + lsls r0,r1 + movs r1,#0 + bx r14 +8: + cmp r1,#32+9 @ overflow? + bge 5f + lsls r1,r0,r3 + movs r0,#0 + bx r14 +5: + mvn r0,#0 @ = 0xffffffff + mvn r1,#0 @ = 0xffffffff + bx r14 +4: + rsbs r1,#0 + usat r1,#5,r1 @ if shift is long return 0 + lsrs r0,r0,r1 + movs r1,#0 + bx r14 +1: + cmp r0,#0xff800000 + bhi 5b @ -NaN, return 0xffffffff + cmp r0,#0x00800000 + bgt 5b @ +Inf or +NaN, return 0xfffffff +2: + movs r0,#0 @ return 0 + movs r1,#0 + bx r14 + +#endif diff --git a/src/rp2_common/pico_float/float_init_rom.c b/src/rp2_common/pico_float/float_init_rom_rp2040.c similarity index 100% rename from src/rp2_common/pico_float/float_init_rom.c rename to src/rp2_common/pico_float/float_init_rom_rp2040.c diff --git a/src/rp2_common/pico_float/float_none.S b/src/rp2_common/pico_float/float_none.S index 5b1916a7e..ad0df2f9b 100644 --- a/src/rp2_common/pico_float/float_none.S +++ b/src/rp2_common/pico_float/float_none.S @@ -70,9 +70,13 @@ wrapper_func remquof wrapper_func expm1f wrapper_func log1pf wrapper_func fmaf +#ifdef __riscv + la a0, str + j panic +#else push {lr} // keep stack trace sane ldr r0, =str bl panic - +#endif str: .asciz "float support is disabled" \ No newline at end of file diff --git a/src/rp2_common/pico_float/float_sci_m33.S b/src/rp2_common/pico_float/float_sci_m33.S new file mode 100644 index 000000000..f4648a35d --- /dev/null +++ b/src/rp2_common/pico_float/float_sci_m33.S @@ -0,0 +1,801 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !PICO_RP2040 +#include "pico/asm_helper.S" + +pico_default_asm_setup + +.macro float_section name +#if PICO_FLOAT_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro float_wrapper_section func +float_section WRAPPER_FUNC_NAME(\func) +.endm + +.extern rtwopi +.extern logtab0 +.extern exptab0 +.extern exptab1 +.extern exptab2 +.extern trigtab + +@ load a 32-bit constant n into register rx +.macro movlong rx,n + movw \rx,#(\n)&0xffff + movt \rx,#((\n)>>16)&0xffff +.endm + +float_section frrcore + +@ input: +@ r0 mantissa m Q23 +@ r1 exponent e>=-32, typically offset by +9 +@ output: +@ r0..r1 preserved +@ r6 range reduced result +@ r2,r3,r4,r5 trashed +frr_core: + ldr r2,=rtwopi + asrs r3,r1,#5 @ k=e/32, k<=5 for e offsets up to 9+32 + add r2,r2,r3,lsl#2 @ p + and r3,r1,#31 @ s=e%32 + mov r4,#1 + lsls r4,r4,r3 @ 1< + Inf; -Inf -> +0 + orrne r0,r0,#0x00400000 + bx r14 + +23: + ands r12,r12,#1<<31 +22: + eors r0,r12,#1<<31 + subs r0,r0,r0,lsr#8 @ overflow: convert to +0 or +Inf + bx r14 + + + + +float_wrapper_section logf + +1: + movlong r0,0xff800000 @ return -Inf + bx r14 + +4: + lsls r1,r0,#9 + it ne + orrne r0,r0,#0x00400000 + bx r14 + +@ here result may be close to zero +5: + sub r1,r0,#0x3f800000 + bmi 7f + cmp r1,#0x8000 + bge 6f @ |ε|>~2^-8? +@ here ε positive + clz r12,r1 + sub r3,r12,#1 + b 8f + +7: + rsbs r2,r1,#0 + cmp r2,#0x8000 + bge 6f @ |ε|>~2^-8? +@ here ε negative +@ r1: x Q24 + clz r12,r2 + sub r3,r12,#2 +8: + sub r12,#10 + lsls r0,r1,r3 @ ε Q24+r3 + beq 10f @ ε=0? + smmulr r1,r0,r0 + asrs r1,r1,r12 + sub r0,r0,r1,asr#1 @ - ε²/2 + smmulr r1,r1,r0 + asrs r2,r1,r12 + movs r3,#0x55 + mul r2,r2,r3 + adds r0,r0,r2,asr#8 @ + ~ ε³/3 + rsb r1,r12,#117 + b 9f + +wrapper_func logf + lsls r3,r0,#1 + bcs 1b @ x<0? + lsrs r3,#24 + beq 1b @ x==0/denormal? + sub r12,r3,#0x7e + cmp r12,#0x81 @ +Inf/NaN? + beq 4b + push {r14} + cmp r12,#1 @ result will be near zero? + bls 5b +6: + movs r2,#1 + bfi r0,r2,#23,#9 @ set implied 1, clear exponent Q52 + + lsls r0,#8 + + lsrs r1,r0,#27 + ldr r2,=logtab0-16*8 + add r2,r2,r1,lsl#3 + ldmia r2,{r2-r3} + lsls r2,#26 + umlal r2,r0,r2,r0 + + mvn r1,r0,asr#24 + ldr r2,=exptab1+4 + ldr r2,[r2,r1,lsl#3] + add r3,r3,r2 + lsls r1,#24 + umlal r1,r0,r1,r0 + + ldr r2,=exptab2+4 + mvn r1,r0,asr#21 + ldr r2,[r2,r1,lsl#3] + lsls r1,#21 + orr r1,#0x00100000 + umlal r1,r0,r1,r0 + add r3,r3,r2 + +@ r0: ε Q32 +@ r3: log y + smmulr r1,r0,r0 @ ε² Q32 + sub r3,r0 + add r3,r3,r1,lsr#1 @ log u - ε + ε²/2 Q32 + movlong r2,0xb17218 @ ln2 Q24, but accurate to 2^-29 or so + cmp r12,#1 @ result will be near zero? + bls 2f + mul r2,r2,r12 + mov r1,#125 + add r3,#255 @ reduce systematic error + subs r0,r2,r3,lsr#8 +9: + bmi 1f + bl fpack_q +10: + pop {r15} + +2: + mov r1,#117 + bne 3f @ r12=0? +@ here r12=1 + movlong r2,0xb17217f8 + sub r0,r2,r3 + bl fpack_q + pop {r15} + +3: + mov r0,r3 + bl fpack_q + orrs r0,r0,#1<<31 + pop {r15} + +1: + rsbs r0,#0 + bl fpack_q + orrs r0,r0,#1<<31 + pop {r15} + + +float_wrapper_section atan2f + +@ fatan small reduced angle case +@ r0 y/x in IEEE format, 0..2^-8 +@ r2 e+6 <0 +@ r3 #1 +@ r6 flags +20: + rsbs r4,r2,#0 @ -e-6 = shift down of mantissa required to get to Q29 >0 + cmp r4,#7 @ -e-6 ≥ 7 [ e ≤ -13 ] + bge 1f @ very small reduced angle? atn θ ~ θ +@ do a power series + bfi r0,r3,#23,#9 @ fix up mantissa Q23-e + lsls r0,#7 @ Q30-e + smmulr r1,r0,r0 @ θ² Q60-2e-Q32=Q28-2e + lsrs r1,r4 @ Q28-2e + (e+6) = Q34-e + smmulr r1,r1,r0 @ θ³ Q34-e+Q30-e-Q32=Q32-2e + mov r3,#0x55555555 @ 1/3 Q32 + lsrs r1,r4 @ Q32-2e + e+6 = Q38-e + smmulr r1,r1,r3 @ θ³/3 Q38-e + sub r0,r0,r1,lsr#8 @ Q30-e + cmp r6,#4 @ at least one quadrant to add? + bhs 2f + add r1,r2,#113 + bl fpack_q + eors r0,r0,r6,lsl#31 @ fix sign + pop {r4-r6,r15} + +@ here reduced angle is < 2^-12 +1: + cmp r6,#4 + bhs 3f @ at least one quadrant to add? + eors r0,r0,r6,lsl#31 @ no: return y/x with the correct sign + pop {r4-r6,r15} + +3: + bfi r0,r3,#23,#9 @ fix up mantissa + lsrs r0,r4 @ Q29 + lsls r0,#1 @ Q30 + b 40f + +2: + lsrs r0,r4 @ Q30-e + e+6 = Q36 + lsrs r0,#6 @ Q30 + b 40f + +@ case where reduced (x',y') has x' infinite +71: + sbfx r4,r0,#23,#8 + movs r0,#0 + cmn r4,#1 @ y' also infinite? + bne 80f + mov r0,#0x3f800000 @ both infinite: pretend ∞/∞=1 + b 80f + +@ case where reduced (x',y') has y' zero +70: + ubfx r4,r1,#23,#8 + movs r0,#0 + cbnz r4,80f @ x' also zero? + tst r6,#4 + beq 80f @ already in quadrants 0/±2? then 0/0 result will be correct + tst r6,#2 + ite eq + addeq r6,#6 + subne r6,#6 @ fix up when in quadrants ±0 + b 80f + +90: + movs r0,r1 +91: + orrs r0,r0,#0x00400000 + pop {r4-r6,r15} + +wrapper_func atan2f + push {r4-r6,r14} + lsls r4,r1,#1 + cmp r4,#0xff000000 + bhi 90b @ y NaN? + lsls r4,r0,#1 + cmp r4,#0xff000000 + bhi 91b @ x NaN? + lsrs r6,r0,#31 @ b31..2: quadrant count; b1: sign to apply before addition; b0: sign to apply after addition + bic r0,#1<<31 +@ y now positive + movs r1,r1 + bpl 1f + +@ here y positive, x negative + adds r6,#10 + bic r1,r1,#1<<31 + cmp r1,r0 + bhi 4f @ |x| > y: 3rd octant +@ |x| < y: 2nd octant + subs r6,#6 + b 3f + +1: +@ here x and y positive + cmp r1,r0 + bhs 4f +@ x < y: 1st octant + adds r6,#6 +3: + movs r2,r1 @ exchange x and y + movs r1,r0 + movs r0,r2 +4: +@ here +@ r0 y' +@ r1 x' +@ where both x' and y' are positive, y'/x' < 1+δ, and the final result is +@ ± (Q.π/2 ± atn y/x) where 0≤Q≤2 is a quadrant count in r6b3..2, the inner negation +@ is given by r6b1 and the outer negation by r6b0. x' can be infinite, or both x' and +@ y' can be infinite, but not y' alone. + + sbfx r2,r1,#23,#8 + cmn r2,#1 + beq 71b @ x' infinite? + ubfx r2,r0,#23,#8 + cmp r2,#0 + beq 70b @ y' zero? + bl __aeabi_fdiv +80: + @ r0 y/x in IEEE format, 0..1 + lsr r2,r0,#23 @ exponent + movs r3,#1 + subs r2,#0x7f-6 + bmi 20b + bfi r0,r3,#23,#9 @ fix up mantissa + lsls r0,r2 + lsls r0,#2 +50: + +@ from here atan2(y,1) where 1 implied +@ r0 y Q31 0≤y<1+δ + + lsrs r2,r0,#16 + mul r3,r2,r2 @ y^2 + movw r4,#0x895c + muls r2,r2,r4 @ y*0x895c + movw r5,#0x1227 + lsrs r3,#14 + mls r2,r3,r5,r2 + subs r2,#0x330000 @ Chebyshev approximation to atn(y) + lsrs r2,#25 + ldr r3,=trigtab+4 + add r3,r3,r2,lsl#4 + ldmia r3,{r3-r5} +@ r0 y Q30 +@ r3 phi0 Q32 +@ r4 sphi0 Q31 +@ r5 cphi0 Q31 +@ r6 flags +@ x0= cphi0 + sphi0*y +@ y0=-sphi0 + cphi0*y + umull r12,r1,r0,r4 @ sphi0*y + umull r12,r2,r0,r5 @ cphi0*y + add r1,r1,r5,lsr#1 @ x0 Q30 + sub r2,r2,r4,lsr#1 @ y0 Q30 +11: +@ r1 x0 Q30 +@ r2 y0 Q30 +@ r3 phi0 Q32 +@ r6 flags + mov r0,#0xffffffff + lsrs r4,r1,#15 + udiv r12,r0,r4 @ rx0 Q17 + lsls r4,r2,#6 @ y0 Q36 + smmul r4,r4,r12 @ t2=y0*rx0 Q21 + lsls r5,r4,#11 @ t2 Q32 + smmlar r0,r5,r2,r1 + smmlsr r1,r5,r1,r2 +@ r0 x1 Q30 +@ r1 y1 Q30 +@ r3 phi0 +@ r4 r2 Q21 +@ r12 rx0 Q17 + mul r5,r4,r4 @ t2_2 Q42 + smull r2,r5,r4,r5 @ t2_3 Q63 + add r3,r3,r4,lsl#11 @ Q32 + lsls r5,#1 @ Q32 + mov r2,#0x55555555 @ 1/3 + smmlsr r3,r2,r5,r3 @ t2_3/3 + +@ r0 x1 Q30 +@ r1 y1 Q30 +@ r3 phi0+phi1 Q32 +@ r12 rx0 Q17 + mul r0,r1,r12 @ y1*rx0 Q30+Q17=Q47 + add r3,r3,r0,asr#15 +@ r3 phi0+phi1+phi2, result over reduced range Q32 +@ r6 flags + + lsrs r0,r3,#2 @ Q30 +@ adc r0,#0 @ rounding +40: + lsl r5,r6,#30 @ b1 -> b31 + eor r0,r0,r5,asr#31 @ negate if required + movlong r1,0x6487ED51 @ π/2 Q30 + + lsr r5,r6,#2 @ quadrants to add + mla r0,r5,r1,r0 + mov r1,#0x80-9 @ for packing Q30 +60: + bl fpack_q + eors r0,r0,r6,lsl#31 + pop {r4-r6,r15} + +@======================================= + +float_wrapper_section fpack + +@ fnegpack: negate and pack +@ fpack_q31: +@ input +@ r0 Q31 result, must not be zero +@ r1 exponent offset [fpack_q only] +@ output +@ r0 IEEE single +@ trashes (r1,)r2 +fnegpack_q31: + rsbs r0,r0,#0 +fpack_q31: + mov r1,#0x7f-9 @ exponent +fpack_q: + clz r2,r0 + rsbs r2,#8 + bmi 1f + lsrs r0,r0,r2 @ save rounding bit in carry + add r2,r2,r1 + adc r0,r0,r2,lsl#23 @ insert exponent + bx r14 + +1: + rsb r2,#0 + lsls r0,r0,r2 + sub r2,r1,r2 + add r0,r0,r2,lsl#23 + bx r14 + +float_wrapper_section tanf + +wrapper_func tanf + push {r14} + bl sincosf_raw + bl __aeabi_fdiv + pop {r15} + +float_wrapper_section fsin_fcos + +10: @ process Inf/NaN for sinf and fcos + lsls r1,r0,#9 + it eq + orreq r0,#0x80000000 + orr r0,#0x00400000 @ turn Inf into NaN + movs r1,r0 @ copy result to cosine output + bx r14 + +@ case where angle is very small (<2^-32) before reduction +32: + adds r1,r1,#0x7f + it eq + moveq r0,#0 @ flush denormal to zero + + movs r1,0x3f800000 @ return x for sine, 1 for cosine + tst r12,#2 + it ne + movne r0,r1 @ calculating cosine? move to result registers + bx r14 + +40: +@ case where range-reduced angle is very small +@ here +@ r0 mantissa +@ r1 exponent+9 +@ r6 abs range-reduced angle / 2π < 2^-7 Q32 +@ r12b31: dsincos flag +@ r12b30: original argument sign +@ r12b2..1: quadrant count +@ r12b0: sign of reduced angle + push {r12} + movs r12,#0 +2: + add r12,#2 + add r1,#2 + bl frr_core @ repeat range reduction with extra factor of 2^2 (, 2^4, 2^6, 2^8,...) + eors r4,r6,r6,asr#31 @ we want to keep the sign in r6b31 for later + cmp r4,#1<<26 @ ≥ 2^-6? + bhs 1f @ loop until the result is big enough + cmp r12,#32 @ safety net + bne 2b +1: +@ here r4 is the abs range-reduced angle Q32+r12, 2^-6..2^-4 in Q32 terms + +@ 2π=6.487ED511 (0B4611A6...) + movlong r5,0x487ED511 @ 2π Q64 high fractional word + umull r2,r0,r4,r5 + movs r5,#6 @ 2π integer part + mla r0,r4,r5,r0 + +@ here +@ r0 θ, abs range reduced angle θ 0..π/4 Q32+r12, 2π * 2^-6..2^-4 in Q32 terms (so top bit is clear) +@ r6b31: sign of reduced angle +@ r12: excess exponent ≥2, multiple of 2 +@ r0 / 2^r12 < ~ 2π * 2^-7 so for sin we need to go to term in x^3 + + smmulr r1,r0,r0 @ θ² Q32+2*r12 + lsrs r1,r1,r12 @ θ² Q32+r12 + lsrs r1,r1,r12 @ θ² Q32 + movs r4,#0x55555555 @ 1/3 Q32 + smmulr r4,r1,r4 @ θ²/3 Q32 + smmulr r2,r4,r1 @ θ⁴/3 Q32 + rsb r3,r1,r2,lsr#2 @ -θ²+θ⁴/12) Q32 + asrs r3,#9 @ -θ²/2+θ⁴/24 Q24 + adc r3,r3,#0x3f800000 @ IEEE single with rounding + + smmulr r2,r4,r0 @ θ³/3 Q32+r12 + sub r0,r0,r2,lsr#1 @ θ-θ³/6 Q32+r12 + rsb r1,r12,#117 + bl fpack_q +@ here +@ r0 packed sin +@ r3 packed cos +@ r6b31: sign of reduced angle + pop {r12} @ get flags + lsrs r6,#31 + bfi r12,r6,#0,#1 + + asrs r2,r12,#1 + bmi 23f @ doing sincos? + asrs r2,#1 + bcc 21f @ need sine? +@ need cosine: + ands r12,#4 + orrs r0,r3,r12,lsl#29 @ insert sign + pop {r4-r6,r15} + +21: + eors r12,r12,r12,lsr#2 + orrs r0,r0,r12,lsl#31 @ insert sign + pop {r4-r6,r15} + +23: + ands r2,r12,#4 + orrs r3,r3,r2,lsl#29 @ insert sign + push {r3} +@ drop into sincosf code below... + b 20f + +wrapper_func sincosf + push {r1, r2, lr} + bl sincosf_raw + pop {r2, r3} + str r0, [r2] + str r1, [r3] + pop {pc} + +sincosf_raw: + ands r12,r0,#1<<31 + lsrs r12,#1 @ save argument sign in r12b30 + orrs r12,r12,#1<<31 @ flag we want both results in r12b31 + b 1f + +wrapper_func sinf + lsrs r12,r0,#29 @ negative argument -> +2 quadrants + ands r12,#4 + b 1f + +wrapper_func cosf + movs r12,#2 @ cos -> +1 quadrant +1: + ubfx r1,r0,#23,#8 @ get exponent + sub r1,r1,#0x7f + cmp r1,#0x80 + beq 10b @ Inf or NaN? + cmn r1,#32 + blt 32b @ very small argument? + movs r3,#1 + bfi r0,r3,#23,#9 @ fix implied 1 in mantissa + push {r4-r6,r14} + add r1,#9 @ e+9 + bl frr_core +@ r6 θ/2π 0..1 Q64 + lsrs r4,r6,#30 @ quadrant count + adc r4,r4,#0 @ rounded + sub r6,r6,r4,lsl#30 @ now -0.125≤r6<+0.125 Q32 + add r12,r12,r4,lsl#1 + orr r12,r12,r6,lsr#31 @ sign into r12b0 +@ r12b2..1: quadrant count +@ r12b0: sign of reduced angle + eors r6,r6,r6,asr#31 @ absolute value of reduced angle 0≤r7<0.125 Q32 + cmp r6,#1<<25 @ θ / 2π < 2^-7? + blo 40b + +@ 2π=6.487ED511 (0B4611A6...) + movlong r5,0x487ED511 @ 2π Q64 high fractional word + umull r2,r0,r6,r5 + movs r5,#6 @ 2π integer part + mla r0,r6,r5,r0 +@ r0 range reduced angle θ 0..π/4 Q32 + lsrs r2,r0,#27 + ldr r3,=trigtab+4 + add r3,r3,r2,lsl#4 + ldmia r3,{r1-r3} + subs r0,r1 +@ r0: ε Q32 |ε| < 1.17*2^-6 +@ r2: sin φ Q31 +@ r3: cos φ Q31 + asrs r1,r12,#1 + bmi 5f @ doing sincosf? + asrs r1,#1 + bcs 3f @ need cosine? +@ here need sine + smmulr r1,r0,r0 @ ε² Q32 + mov r4,#0x55555555 @ 1/3 Q32 + asrs r1,#1 + smmlsr r2,r1,r2,r2 @ sin φ - ε²/2*sin φ ~ sin φ cos ε + smmulr r1,r1,r0 @ ε³/2 + smmlsr r1,r1,r4,r0 @ ε - ε³/6 + + smmlar r0,r1,r3,r2 @ sin φ cos ε + cos φ (ε - ε³/6) ~ sin (φ+ε) +@ the sign of the result is r12b0^r12b2 + bl fpack_q31 + eors r12,r12,r12,lsr#2 + orrs r0,r0,r12,lsl#31 @ insert sign + pop {r4-r6,r15} + +3: +@ here need cosine + smmulr r1,r0,r0 @ ε² Q32 + mov r4,#0x55555555 @ 1/3 Q32 + asrs r1,#1 + smmlsr r3,r1,r3,r3 @ cos φ - ε²/2*cos φ ~ cos φ cos ε + smmulr r1,r1,r0 @ ε³/2 + smmlsr r1,r1,r4,r0 @ ε - ε³/6 + + smmlsr r0,r1,r2,r3 @ cos φ cos ε - sin φ (ε - ε³/6) ~ cos (φ+ε) +@ the sign of the result is r12b2 + bl fpack_q31 + ands r12,#4 + orrs r0,r0,r12,lsl#29 @ insert sign + pop {r4-r6,r15} + +5: +@ here doing sincosf + smmulr r1,r0,r0 @ ε² Q32 + mov r6,#0x55555555 @ 1/3 Q32 + asrs r1,#1 + smmlsr r4,r1,r2,r2 @ sin φ - ε²/2*sin φ ~ sin φ cos ε + smmlsr r5,r1,r3,r3 @ cos φ - ε²/2*cos φ ~ cos φ cos ε + smmulr r1,r1,r0 @ ε³/2 + smmlsr r6,r1,r6,r0 @ ε - ε³/6 +@ here +@ r2 sin φ +@ r3 cos φ +@ r4 sin φ cos ε +@ r5 cos φ cos ε +@ r6 ε - ε³/6 ~ sin ε + smmlsr r0,r6,r2,r5 @ cos φ cos ε - sin φ (ε - ε³/6) ~ cos (φ+ε) + bl fpack_q31 + ands r5,r12,#4 + eors r0,r0,r5,lsl#29 @ negate cosine in quadrants 2 and 3 + push {r0} + smmlar r0,r6,r3,r4 @ sin φ cos ε + cos φ (ε - ε³/6) ~ sin (φ+ε) + bl fpack_q31 +20: + eors r4,r12,r12,lsr#1 + eors r4,r4,r12,lsr#2 + ands r5,r12,#1<<30 + tst r12,#2 @ exchange sine and cosine in odd quadrants + beq 1f + eors r1,r0,r4,lsl#31 @ negate sine on b0^b1^b2 + pop {r0} + eors r0,r0,r5,lsl#1 @ negate sine result if argument was negative + pop {r4-r6,r15} +1: + pop {r1} + eors r0,r0,r4,lsl#31 @ negate sine on b0^b1^b2 + eors r0,r0,r5,lsl#1 @ negate sine result if argument was negative + pop {r4-r6,r15} + +#endif diff --git a/src/rp2_common/pico_float/float_sci_m33_vfp.S b/src/rp2_common/pico_float/float_sci_m33_vfp.S new file mode 100644 index 000000000..86e8b2750 --- /dev/null +++ b/src/rp2_common/pico_float/float_sci_m33_vfp.S @@ -0,0 +1,856 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if !PICO_RP2040 +#include "pico/asm_helper.S" + +pico_default_asm_setup + +.macro float_section name +#if PICO_FLOAT_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +.macro float_wrapper_section func +float_section WRAPPER_FUNC_NAME(\func) +.endm + +@ load a 32-bit constant n into register rx +.macro movlong rx,n + movw \rx,#(\n)&0xffff + movt \rx,#((\n)>>16)&0xffff +.endm + +float_section frrcore_v + +// 1/2π to plenty of accuracy +.long 0 @ this allows values of e down to -32 +rtwopi: +.long 0,0 +.long 0x28BE60DB, 0x9391054A, 0x7F09D5F4, 0x7D4D3770, 0x36D8A566, 0x4F10E410 + +@ input: +@ r0 mantissa m Q23 +@ r1 exponent e>=-32, typically offset by +9 +@ output: +@ r0..r1 preserved +@ r6 range reduced result in revolutions Q32 +@ r2,r3,r4,r5 trashed +.thumb_func +frr_core: + adr r2,rtwopi + asrs r3,r1,#5 @ k=e/32, k<=5 for e offsets up to 9+32 + add r2,r2,r3,lsl#2 @ p + and r3,r1,#31 @ s=e%32 + mov r4,#1 + lsls r4,r4,r3 @ 1<>19 rounded, preserving flags + bic r3,#7 + + ldrd r2,r3,[r3] + mul r0,r0,r2 @ ε + vmov s0,s1,r3,r0 @ s0=-log u, s1=ε + + vcvt.f32.s32 s1,s1,#32 + vmul.f32 s2,s1,s1 @ power series in ε + sbc r1,r1,#0x7e @ ... and here + vmul.f32 s3,s1,s2 + lsls r1,#23 @ e Q23 + vmul.f32 s4,s2,s2 @ to ε⁴ +@ movlong r2,0x58b90bfc @ log 2 Q31, more accurate than we deserve + movw r2,0x0bfc + vmul.f32 s2,s2,s8 + movt r2,0x58b9 + vmul.f32 s3,s3,s9 + smmulr r1,r1,r2 @ Q22 + vmul.f32 s4,s4,s10 + vmov s7,r1 + vsub.f32 s3,s3,s4 + vcvt.f32.s32 s7,s7,#22 + vsub.f32 s2,s2,s3 + vsub.f32 s1,s1,s2 + vadd.f32 s0,s0,s1 @ log ε - log u + vadd.f32 s0,s0,s7 @ e log 2 + log ε - log u + vmov r0,s0 + bx r14 + +1: + bgt 3f @ +NaN? + beq 10f @ +Inf? +2: + cmp r0,#0x80800000 @ -0? + blo 11f + cmp r0,#0xff800000 @ -NaN/-Inf? +3: + orr r0,#0x00400000 + bhi 10f + movlong r0,0xffc00000 +10: + bx r14 +11: + movlong r0,0xff800000 + bx r14 + +.align 3 +k_log3: +.float 0.5 +.float 0.333333333333333 +.float 0.25 +.float 0 @ alignment + +logtab3: +@ u=64/[48:2:96]; u Q8, -log u F32 +.word 0x0155,0xbe92cb01 @ 00003e9b..00004145 +.word 0x0148,0xbe7dc8c3 @ 00003ec8..00004158 +.word 0x013b,0xbe545f68 @ 00003ec1..00004137 +.word 0x012f,0xbe2c99c7 @ 00003ebb..00004119 +.word 0x0125,0xbe0a3c2c @ 00003ef3..0000413d +.word 0x011a,0xbdc61a2f @ 00003eca..000040fe +.word 0x0111,0xbd83acc2 @ 00003eeb..0000410d +.word 0x0108,0xbcfc14d8 @ 00003ee8..000040f8 +.word 0x0100,0x00000000 @ 00003f00..00004100 +.word 0x00f8,0x3d020aec @ 00003ef8..000040e8 +.word 0x00f1,0x3d77518e @ 00003f13..000040f5 +.word 0x00ea,0x3db80698 @ 00003f12..000040e6 +.word 0x00e4,0x3ded393b @ 00003f3c..00004104 +.word 0x00dd,0x3e168b08 @ 00003f05..000040bf +.word 0x00d8,0x3e2dfa03 @ 00003f48..000040f8 +.word 0x00d2,0x3e4ad2d7 @ 00003f2a..000040ce +.word 0x00cd,0x3e637fde @ 00003f43..000040dd +.word 0x00c8,0x3e7cc8e3 @ 00003f48..000040d8 +.word 0x00c3,0x3e8b5ae6 @ 00003f39..000040bf +.word 0x00bf,0x3e95f784 @ 00003f6b..000040e9 +.word 0x00ba,0x3ea38c6e @ 00003f36..000040aa +.word 0x00b6,0x3eaeadef @ 00003f46..000040b2 +.word 0x00b2,0x3eba0ec4 @ 00003f46..000040aa +.word 0x00ae,0x3ec5b1cd @ 00003f36..00004092 +.word 0x00ab,0x3ece995f @ 00003f75..000040cb + +float_wrapper_section fsin_fcos + +30: + lsls r1,r0,#9 + bne 1f @ NaN? return it + orrs r0,r0,#0x80000000 @ Inf: make a NaN +1: + orrs r0,r0,#0x00400000 @ set top mantissa bit of NaN + bx r14 + +@ heavy-duty range reduction +@ here x≥256, -e in r1 +40: + push {r4-r7,r14} + movs r3,#1 + bfi r0,r3,#23,#9 @ insert implied 1 in mantissa, clear sign + rsb r1,#9 @ e+9 + mov r7,#0x7e @ this will be the exponent of the reduced angle - 1 +42: + bl frr_core +@ here r6 is revolutions Q32 + lsrs r3,r6,#30 @ quadrant count + adcs r3,r3,#0 @ rounded + add r12,r12,r3 + subs r6,r6,r3,lsl#30 @ reduced angle/2π Q32 -.125≤x<+.125 +@ comment out from here... + lsls r2,r6,#2 @ Q34 + it cs + rsbcs r2,r2,#0 @ absolute value + cmp r2,#1<<28 @ big enough for accuracy? + bhs 41f +@ ... to here for slightly better accuracy +43: + adds r1,r1,#2 @ try again with increased exponent + bl frr_core + eors r2,r6,r6,asr#32 @ absolute value + adc r2,r2,#0 + cmp r2,#1<<28 @ big enough yet? + bhs 44f + subs r7,r7,#2 + bpl 43b @ safety net +44: + +41: + ldr r4,=0xC90FDAA2 @ 2π Q29 + umull r2,r4,r2,r4 @ r4 has reduced angle Q34+Q29-Q32=Q31 +@ add r4,r4,r2,lsr#31 + clz r2,r4 @ normalise + lsls r4,r4,r2 + lsrs r4,r4,#8 + sub r2,r7,r2 + adc r0,r4,r2,lsl#23 @ with rounding + lsrs r1,r0,#23 @ re-extract exponent as there may have been a carry into it + rsbs r1,r1,#0x7f @ prepare exponent for re-entry + lsrs r6,r6,#31 + add r3,r0,r6,lsl#31 @ apply sign of reduced angle + pop {r4-r7,r14} + b 5f @ re-enter with no risk of looping + +.ltorg + +@ light-duty range reduction +@ here argument ≥1 +@ r0: argument +@ r1: -e +@ r12: quadrant count +@ required result is sin(r0+r12*π/2) +10: + cmn r1,#0x80 + beq 30b @ Inf/NaN + bics r2,r0,r12,lsl#31 @ negative argument,doing sin -> +2 quadrants + it mi + addmi r12,r12,#2 + bic r0,r0,#0x80000000 @ make positive: original sign is now captured in quadrant count in r12 + +@ this may not actually be faster than doing it in integer registers + vmov s0,r0 + adr r2,k_sc4 + vldmia r2!,{s5-s7} +@ vmul.f32 s4,s4,s0 @ this accurate calculation of the quadrant count does not seem necessary +@ vfma.f32 s4,s5,s0 + vmul.f32 s4,s5,s0 @ this is BALGE + cmn r1,#8 @ ≥256? + vrintn.f32.f32 s4,s4 @ round to quadrant count: x<256 so count≤163 + ble 40b @ then do heavy-duty range reduction + vfms.f32 s0,s4,s7 + vfms.f32 s0,s4,s6 + vmov r3,s0 @ reduced angle + vcvt.s32.f32 s3,s4 + ubfx r2,r3,#23,#8 @ get exponent + cmp r2,#0x78 + blo 40b @ very small result? use heavy-duty reduction to get a more accurate answer + rsbs r1,r2,#0x7f @ ready for re-entry + vmov r2,s3 @ integer quadrant count + add r12,r12,r2 +@ prepare to re-enter with no risk of looping + b 5f + +k_sc4: +@ 2/π=0.A2F9836E4E441529FC... +.word 0x3f22f983 @ 2/π +@ π/2=1.921FB54442D1846989... +.word 0xb695777a,0x3fc91000 @ these two add up to π/2 with error ~1.6e-13 + +wrapper_func sincosf + + push {r0-r2,r14} + ubfx r1,r0,#23,#8 + cmp r1,#0xff @ Inf/NaN? + beq 2f + bl cosf_entry @ this will exit via 1f or 2f... + pop {r1-r2,r14} + str r0,[r14] +@ here C is still set from lsrs r12,r12,#1 + bcs 1f + mvns r1,r1 + eor r12,r12,r1,lsr#31 +@ this is fsc_costail: +@ here calculate cos φ+ε = cosθ + vmul.f32 s5,s7,s1 @ sinφ sinε + vfma.f32 s5,s2,s6 @ sinφ sinε + cosφ(1-cosε) + vsub.f32 s5,s6,s5 @ cosφ - (sinφ sinε + cosφ(1-cosε)) = cosφ cosε - sinφ sinε + vmov.f32 r0,s5 + eor r0,r0,r12,lsl#31 + str r0,[r2] + pop {r15} + +1: + eor r12,r12,r1,lsr#31 +@ this is fsc_sintail: +@ here calculate sin φ+ε = sinθ + vmul.f32 s4,s2,s7 @ sinφ(1-cosε) + vfms.f32 s4,s6,s1 @ sinφ(1-cosε) - cosφ sinε + eor r1,r12,r3,lsr#31 @ flip sign if (reduced) argument was negative + vsub.f32 s4,s7,s4 @ cosφ sinε + sinφ cosε + vmov.f32 r0,s4 + eor r0,r0,r1,lsl#31 + str r0,[r2] @ save cos result + pop {r15} + +@ sincos of Inf or NaN +2: + lsls r1,r0,#9 + pop {r1-r3,r14} + bne 1f @ NaN? return it + orrs r0,r0,#0x80000000 @ Inf: make a NaN +1: + orrs r0,r0,#0x00400000 @ set top mantissa bit of NaN + str r0,[r2] @ both sin and cos results + str r0,[r3] + bx r14 + +wrapper_func sinf +@ r12b1..0: quadrant count + movs r12,#0 + b 1f + +wrapper_func cosf +.thumb_func +cosf_entry: + movs r12,#1 @ cos -> +1 quadrant +1: + ubfx r1,r0,#23,#8 @ get exponent + cbz r1,20f @ 0/denormal? +22: + rsbs r1,r1,#0x7f + bls 10b @ argument ≥1? needs reduction; also Inf/NaN handling + bic r3,r0,r12,lsl#31 @ this would mess up NaNs so do it here +5: +@ here we have a quadrant count in r12 and a signed offset r0 from r12*π/2 + bic r0,r3,#0x80000000 @ this would mess up NaNs so do it here + vmov s0,r0 + ubfx r0,r0,#18,#5 @ extract top of mantissa + adds r0,r0,#32 @ insert implied 1 + lsrs r1,r0,r1 @ to fixed point Q5 + ldr r2,=k_sc3 + adcs r1,r1,#0 @ rounding + vldmia r2!,{s8-s9} + add r2,r2,r1,lsl#2 @ 12 bytes per entry + add r2,r2,r1,lsl#3 + + vldmia r2,{s5-s7} @ φ, cosφ, sinφ + vsub.f32 s1,s0,s5 @ ε + vmul.f32 s2,s1,s1 @ ε² + lsrs r12,r12,#1 @ computing cosine? + vmul.f32 s3,s2,s1 @ ε³ + bcs 2f + + vmul.f32 s2,s2,s8 @ ε²/2! ~ 1-cosε + vmul.f32 s3,s3,s9 @ ε³/3! + vsub.f32 s1,s1,s3 @ ε-ε³/3! ~ sinε + +@ here: +@ s1: sinε +@ s2: 1-cosε +@ s6: cosφ +@ s7: sinφ +@ r12: quadrant count +fsc_sintail: +@ here calculate sin φ+ε = sinθ + vmul.f32 s4,s2,s7 @ sinφ(1-cosε) + vfms.f32 s4,s6,s1 @ sinφ(1-cosε) - cosφ sinε + eor r1,r12,r3,lsr#31 @ flip sign if (reduced) argument was negative + vsub.f32 s4,s7,s4 @ cosφ sinε + sinφ cosε + vmov.f32 r0,s4 + eor r0,r0,r1,lsl#31 + bx r14 + +20: + and r0,r0,#0x80000000 @ make signed zero + b 22b + +.align 2 +2: + vmul.f32 s3,s3,s9 @ ε³/3! + vsub.f32 s1,s1,s3 @ ε-ε³/3! ~ sinε + vmul.f32 s2,s2,s8 @ ε²/2! ~ 1-cosε +fsc_costail: +@ here calculate cos φ+ε = cosθ + vmul.f32 s5,s7,s1 @ sinφ sinε + vfma.f32 s5,s2,s6 @ sinφ sinε + cosφ(1-cosε) + vsub.f32 s5,s6,s5 @ cosφ - (sinφ sinε + cosφ(1-cosε)) = cosφ cosε - sinφ sinε + vmov.f32 r0,s5 + eor r0,r0,r12,lsl#31 + bx r14 + +.align 3 +k_sc3: +.word 0x3EFFFEC1 @ ~ 1/2! with PMC +.word 0x3e2aaa25 @ ~ 1/3! with PMC + +trigtab2: +// φ cos φ sin φ +.word 0x00000000,0x3f800000,0x00000000 +.word 0x3cfcc961,0x3f7fe0cd,0x3cfcbf1c @ φ=0.03085774 : cos φ=3feffc199ff28ef4 33.3b; sin φ=3f9f97e38006c678 39.2b +.word 0x3d810576,0x3f7f7dfe,0x3d80ef9e @ φ=0.06299870 : cos φ=3fefefbfc00d6b6d 33.3b; sin φ=3fb01df3c000dfd5 40.2b +.word 0x3dbf0c09,0x3f7ee30f,0x3dbec522 @ φ=0.09328467 : cos φ=3fefdc61dff4f58e 33.5b; sin φ=3fb7d8a43ffdf9ac 39.0b +.word 0x3dff24b6,0x3f7e0414,0x3dfe7be2 @ φ=0.12458174 : cos φ=3fefc0827fdaf90f 31.8b; sin φ=3fbfcf7c3ff9dd0c 37.4b +.word 0x3e1f0713,0x3f7ceb48,0x3e1e63a0 @ φ=0.15530042 : cos φ=3fef9d68ffe680a0 32.3b; sin φ=3fc3cc73fffa6d09 36.5b +.word 0x3e40306d,0x3f7b811d,0x3e3f1015 @ φ=0.18768473 : cos φ=3fef70239fe32301 32.1b; sin φ=3fc7e2029ffdbc2c 37.8b +.word 0x3e60ada2,0x3f79dccf,0x3e5ee13e @ φ=0.21941236 : cos φ=3fef3b99e023f5aa 31.8b; sin φ=3fcbdc27bffe216d 38.1b +.word 0x3e800d7b,0x3f7808fa,0x3e7d7196 @ φ=0.25010285 : cos φ=3fef011f401572a6 32.6b; sin φ=3fcfae32c00328bb 37.3b +.word 0x3e8f986e,0x3f75ff65,0x3e8db868 @ φ=0.28045982 : cos φ=3feebfeca0aaaf99 29.6b; sin φ=3fd1b70cfffc1468 36.0b +.word 0x3e9fe1f4,0x3f739e93,0x3e9d4bfd @ φ=0.31227076 : cos φ=3fee73d25fbf733b 31.0b; sin φ=3fd3a97fa0002ced 40.5b +.word 0x3eb054c6,0x3f70f7ae,0x3eacddb3 @ φ=0.34439677 : cos φ=3fee1ef5bfcf70cb 31.4b; sin φ=3fd59bb65fff5c30 38.6b +.word 0x3ebf89c5,0x3f6e4b60,0x3ebb1a0a @ φ=0.37409797 : cos φ=3fedc96bffdebb8a 31.9b; sin φ=3fd763414003344b 36.3b +.word 0x3ecfc426,0x3f6b35ca,0x3eca1c63 @ φ=0.40579337 : cos φ=3fed66b93fe27dc6 32.1b; sin φ=3fd9438c5ffe5d45 37.3b +.word 0x3ee054f2,0x3f67d166,0x3ed93907 @ φ=0.43814808 : cos φ=3fecfa2cbffc16e9 35.0b; sin φ=3fdb2720dffef5b6 37.9b +.word 0x3eeff0dd,0x3f64664b,0x3ee74116 @ φ=0.46863452 : cos φ=3fec8cc95f714272 29.8b; sin φ=3fdce822c00479ad 35.8b +.word 0x3f002b31,0x3f609488,0x3ef5c30f @ φ=0.50065905 : cos φ=3fec1290ffc99208 31.2b; sin φ=3fdeb861dfff3932 38.4b +.word 0x3f07e407,0x3f5cc5a2,0x3f01992b @ φ=0.53082317 : cos φ=3feb98b44034cd46 31.3b; sin φ=3fe033255ffff628 41.7b +.word 0x3f101fc5,0x3f587d8f,0x3f08a165 @ φ=0.56298476 : cos φ=3feb0fb1e0ceda6f 29.3b; sin φ=3fe1142c9ffd5ae4 35.6b +.word 0x3f17f68a,0x3f5434b5,0x3f0f31ca @ φ=0.59360564 : cos φ=3fea8696a038a06f 31.2b; sin φ=3fe1e639400269fb 35.7b +.word 0x3f1fffe2,0x3f4f9b59,0x3f15c8d7 @ φ=0.62499821 : cos φ=3fe9f36b1f428363 29.4b; sin φ=3fe2b91ae001d55d 36.1b +.word 0x3f280646,0x3f4acf6b,0x3f1c37c4 @ φ=0.65634573 : cos φ=3fe959ed61449f08 28.7b; sin φ=3fe386f87ffd9617 35.7b +.word 0x3f303041,0x3f45b9e0,0x3f229ae4 @ φ=0.68823630 : cos φ=3fe8b73c0047ae7a 30.8b; sin φ=3fe4535c7ffdf1ac 36.0b +.word 0x3f381da7,0x3f4098ca,0x3f28a620 @ φ=0.71920246 : cos φ=3fe81319402ae6e1 31.6b; sin φ=3fe514c3ffff423c 37.4b +.word 0x3f3fc72f,0x3f3b76ac,0x3f2e564a @ φ=0.74913305 : cos φ=3fe76ed5809d419f 29.7b; sin φ=3fe5cac93fffaf1d 38.7b +.word 0x3f4813db,0x3f35b6cc,0x3f34526b @ φ=0.78155297 : cos φ=3fe6b6d9800e8b52 33.1b; sin φ=3fe68a4d5ffe89fc 36.5b +.word 0x3f4fc779,0x3f30352f,0x3f39b4d0 @ φ=0.81163746 : cos φ=3fe606a5dfdc2b5b 31.8b; sin φ=3fe73699fffd7fc8 35.7b +.word 0x3f57dd52,0x3f2a4170,0x3f3f2d91 @ φ=0.84322083 : cos φ=3fe5482e011ba752 28.9b; sin φ=3fe7e5b21ffcb223 35.3b +.word 0x3f5fce26,0x3f243e9f,0x3f445dc3 @ φ=0.87423933 : cos φ=3fe487d3e0b9864b 29.5b; sin φ=3fe88bb85ffde6d5 35.9b +.word 0x3f6825f1,0x3f1dc250,0x3f499d1c @ φ=0.90682894 : cos φ=3fe3b849ffea9b8f 32.6b; sin φ=3fe933a38002730d 35.7b +.word 0x3f703be1,0x3f175041,0x3f4e7ebf @ φ=0.93841368 : cos φ=3fe2ea0820791b4e 30.1b; sin φ=3fe9cfd7e0053e65 34.6b +.word 0x3f781078,0x3f10ed71,0x3f5306af @ φ=0.96900129 : cos φ=3fe21dae1fdea23e 31.9b; sin φ=3fea60d5e001b90b 36.2b +.word 0x3f7ff4d4,0x3f0a5aa7,0x3f57649b @ φ=0.99982953 : cos φ=3fe14b54deeaa407 28.9b; sin φ=3feaec9360012825 36.8b + +float_wrapper_section tanf + +wrapper_func tanf + push {r0,r14} + ubfx r1,r0,#23,#8 + cmp r1,#0xff @ Inf/NaN? + beq 2f + bl cosf_entry @ this will exit via sintail or costail... + ldr r1,[sp,#0] +@ here C is still set from lsrs r12,r12,#1 + bcs 1f +@ we exited via sintail +@ this is fsc_costail: +@ here calculate cos φ+ε = cosθ + vmul.f32 s5,s7,s1 @ sinφ sinε + vfma.f32 s5,s2,s6 @ sinφ sinε + cosφ(1-cosε) + eors r1,r1,r3 + vsub.f32 s5,s6,s5 @ cosφ - (sinφ sinε + cosφ(1-cosε)) = cosφ cosε - sinφ sinε + vdiv.f32 s0,s5,s4 + vmov.f32 r0,s0 + it pl + eorpl r0,r0,#0x80000000 + pop {r1,r15} + +1: +@ we exited via costail +@ this is fsc_sintail: +@ here calculate sin φ+ε = sinθ + vmul.f32 s4,s2,s7 @ sinφ(1-cosε) + vfms.f32 s4,s6,s1 @ sinφ(1-cosε) - cosφ sinε + eors r1,r1,r3 + vsub.f32 s4,s7,s4 @ cosφ sinε + sinφ cosε + vdiv.f32 s0,s4,s5 + vmov.f32 r0,s0 + it mi + eormi r0,r0,#0x80000000 + pop {r1,r15} + +@ tan of Inf or NaN +2: + lsls r1,r0,#9 + bne 1f @ NaN? return it + orrs r0,r0,#0x80000000 @ Inf: make a NaN +1: + orrs r0,r0,#0x00400000 @ set top mantissa bit of NaN + pop {r3,r15} + + +float_wrapper_section atan2f + +50: +60: + orrs r0,r1,#0x00400000 + bx r14 + +51: + bne 52f @ NaN? + cmp r3,#0x7f800000 @ y an infinity; x an infinity too? + bne 55f @ no: carry on +@ here x and y are both infinities + b 66f + +52: +62: + orrs r0,r0,#0x00400000 + bx r14 + +61: + bne 62b @ NaN? + cmp r3,#0x7f800000 @ y an infinity; x an infinity too? + bne 65f @ no: carry on +66: +@ here x and y are both infinities + subs r0,r0,#1 @ make both finite (and equal) with same sign and retry + subs r1,r1,#1 + b 86f + +70: + and r3,#0x80000000 + cmp r2,#0x00800000 + bhs 72f @ y 0 or denormal? +@ here both x and y are zeros + b 85f +71: + and r2,#0x80000000 +72: + vmov s0,s1,r2,r3 + vdiv.f32 s2,s0,s1 @ restart the division + b 73f @ and go back and check for NaNs + +80: + and r3,#0x80000000 + cmp r2,#0x00800000 + bhs 82f @ y 0 or denormal? +85: +@ here both x and y are zeros + orr r1,r1,0x3f800000 @ retry with x replaced by ~1 with appropriate sign + b 86f + +81: + and r2,#0x80000000 +82: + vmov s0,s1,r2,r3 + vdiv.f32 s2,s1,s0 @ restart the division + b 83f @ and go back and check for NaNs + +wrapper_func atan2f +86: + bic r2,r0,#0x80000000 + bic r3,r1,#0x80000000 + vmov s0,s1,r2,r3 + cmp r2,r3 @ |y| vs. |x| + bhi 1f +@ here |x|≥|y| so we need |y|/|x|; octant/xs/ys: 0++,3-+,4--,7+- + vdiv.f32 s2,s0,s1 @ get this division started; result ≤1 + cmp r3,#0x00800000 + blo 70b @ x 0 or denormal? + cmp r2,#0x00800000 + blo 71b @ y 0 or denormal? +73: + cmp r3,#0x7f800000 + bhi 50b @ x NaN? + cmp r2,#0x7f800000 + bhs 51b @ y Inf or NaN? +55: + cmp r1,#0 + ite mi + ldrmi r12,pi @ if x<0, need two extra quadrants + movpl r12,#0 + @ inner negation is the sign of x + b 2f + +1: +@ here |x|<|y| so we need |x|/|y|; octant/xs/ys: 1++,2-+,5--,6+- + vdiv.f32 s2,s1,s0 @ result <1 + cmp r3,#0x00800000 + blo 80b @ x 0 or denormal? + cmp r2,#0x00800000 + blo 81b @ y 0 or denormal? +83: + cmp r3,#0x7f800000 + bhi 60b @ x NaN? + cmp r2,#0x7f800000 + bhs 61b @ y Inf or NaN? +65: + ldr r12,piover2 @ always one extra quadrant in this path + eors r1,r1,#0x80000000 @ inner negation is the complement of the sign of x + +2: +@ here +@ r0 y +@ r1 ±x +@ r2 |y| +@ r3 |x| +@ s0,s1 = |x|,|y| +@ s2=s0/s1 or s1/s0, 0≤s2≤1 +@ r12=quadrant count * π/2 +@ where the final result is +@ ± (r12 ± atn s2) where the inner negation is given by r1b31 and the outer negation by r0b31 + + adr r2,trigtab3 + vmov.f32 s3,s2 + vcvt.u32.f32 s3,s3,#6 + vmov.f32 r3,s3 + lsrs r3,r3,#1 + adcs r3,r3,#0 @ rounding; set Z if in φ==0 case + add r2,r2,r3,lsl#3 + vldr s5,[r2,#4] @ t=tanφ + vmul.f32 s0,s5,s2 @ ty + vsub.f32 s1,s2,s5 @ y-t + vmov.f32 s5,#1.0 + vadd.f32 s0,s5,s0 @ 1+ty + beq 9f @ did we look up zeroth table entry? + +@ now (s0,s1) = (x,y) + vdiv.f32 s0,s1,s0 @ ε + ldr r2,[r2] @ φ Q29 +@ result is now ±(r12±(r2+atn(s0)) + cmp r1,#0 @ inner negation + it mi + rsbmi r2,r2,#0 + add r2,r12,r2 @ Q29 + cmp r0,#0 @ outer negation + it mi + rsbmi r2,r2,#0 + cmp r2,#0 + bpl 1f + rsbs r2,r2,#0 + clz r3,r2 + lsls r2,r2,r3 + beq 3f + rsb r3,#0x180 + b 2f +1: + clz r3,r2 + lsls r2,r2,r3 + beq 3f + rsb r3,#0x80 +2: + lsrs r2,r2,#8 @ rounding bit to carry + adc r2,r2,r3,lsl#23 @ with rounding +3: + vmul.f32 s2,s0,s0 @ ε² + vldr.f32 s3,onethird + vmul.f32 s2,s2,s0 @ ε³ + teq r0,r1 + vmul.f32 s2,s2,s3 @ ε³/3 + vmov.f32 s4,r2 + vsub.f32 s0,s0,s2 @ ~atn(ε) + ite pl + vaddpl.f32 s0,s4,s0 + vsubmi.f32 s0,s4,s0 + vmov.f32 r0,s0 + bx r14 + +9: @ we looked up the zeroth table entry; we could generate slightly more accurate results here +@ now (s0,s1) = (x,y) + vdiv.f32 s0,s1,s0 @ ε +@ result is now ±(r12±(0+atn(s0)) + mov r2,r12 @ Q29; in fact r12 is only ±π/2 or ±π so can probably simplify this + cmp r0,#0 @ outer negation + it mi + rsbmi r2,r2,#0 + cmp r2,#0 + bpl 1f + rsbs r2,r2,#0 + clz r3,r2 + lsls r2,r2,r3 + beq 3f + rsb r3,#0x180 + b 2f +1: + clz r3,r2 + lsls r2,r2,r3 + beq 3f + rsb r3,#0x80 +2: + lsrs r2,r2,#8 @ rounding bit to carry + adc r2,r2,r3,lsl#23 @ with rounding +3: + vmul.f32 s2,s0,s0 @ ε² + vldr.f32 s3,onethird + vmul.f32 s2,s2,s0 @ ε³ + teq r0,r1 + vmul.f32 s2,s2,s3 @ ε³/3 + vmov.f32 s4,r2 + vsub.f32 s0,s0,s2 @ ~atn(ε) + ite pl + vaddpl.f32 s0,s4,s0 + vsubmi.f32 s0,s4,s0 + vmov.f32 r0,s0 + tst r0,#0x7f800000 @ about to return a denormal? + it ne + bxne r14 + and r0,r0,#0x80000000 @ make it zero + bx r14 + +piover2: .word 0x3243f6a9 @ Q29 +pi: .word 0x6487ed51 @ Q29 +onethird: .float 0.33333333 + +trigtab3: +// φ Q29 tan φ SP +.word 0x00000000,0x00000000 +.word 0x00ffee23,0x3d0001bb @ φ=0.03124148 : tan φ=3fa000375fffff9d 50.4b +.word 0x01fe88dc,0x3d7f992a @ φ=0.06232112 : tan φ=3faff3253fffea1f 44.5b +.word 0x02fe0a70,0x3dc01203 @ φ=0.09351084 : tan φ=3fb8024060002522 42.8b +.word 0x03fad228,0x3e000368 @ φ=0.12436779 : tan φ=3fc0006cfffffc90 45.2b +.word 0x04f5ab70,0x3e1ffdea @ φ=0.15498897 : tan φ=3fc3ffbd400014d5 42.6b +.word 0x05ed56f8,0x3e3fdddc @ φ=0.18522213 : tan φ=3fc7fbbb80000beb 43.4b +.word 0x06e4cfa0,0x3e601425 @ φ=0.21543103 : tan φ=3fcc02849fffe817 42.4b +.word 0x07d8d3e0,0x3e80215d @ φ=0.24521822 : tan φ=3fd0042b9ffff89f 43.1b +.word 0x08c60460,0x3e9000a5 @ φ=0.27417201 : tan φ=3fd20014a000182b 41.4b +.word 0x09b26770,0x3ea01492 @ φ=0.30302784 : tan φ=3fd402923ffff932 43.2b +.word 0x0a996d50,0x3eb01377 @ φ=0.33122888 : tan φ=3fd6026ee0001062 42.0b +.word 0x0b7a6d10,0x3ebff4a0 @ φ=0.35869458 : tan φ=3fd7fe93ffff8c38 39.1b +.word 0x0c593ce0,0x3ed0019f @ φ=0.38589329 : tan φ=3fda0033e0001354 41.7b +.word 0x0d33ebd0,0x3ee01bbc @ φ=0.41258803 : tan φ=3fdc0377800162a1 37.5b +.word 0x0e087ab0,0x3ef01fbd @ φ=0.43853506 : tan φ=3fde03f79fffddf2 40.9b +.word 0x0ed56180,0x3effef98 @ φ=0.46354747 : tan φ=3fdffdf30000767d 39.1b +.word 0x0fa1de80,0x3f080ebf @ φ=0.48850942 : tan φ=3fe101d7dfffb9fc 38.9b +.word 0x10639d00,0x3f0fec31 @ φ=0.51215982 : tan φ=3fe1fd862000aad5 37.6b +.word 0x112690e0,0x3f180cfd @ φ=0.53595775 : tan φ=3fe3019fa00069ea 38.3b +.word 0x11e014c0,0x3f200065 @ φ=0.55860364 : tan φ=3fe4000ca00022e5 39.9b +.word 0x129651e0,0x3f2808be @ φ=0.58084959 : tan φ=3fe50117c00015a7 40.6b +.word 0x1346d400,0x3f300a7d @ φ=0.60239601 : tan φ=3fe6014f9fffa020 38.4b +.word 0x13efc7c0,0x3f37ee2f @ φ=0.62302005 : tan φ=3fe6fdc5dfff98d7 38.3b +.word 0x14988960,0x3f400c32 @ φ=0.64362019 : tan φ=3fe801863fffff81 46.0b +.word 0x1537a8c0,0x3f47ef42 @ φ=0.66304433 : tan φ=3fe8fde8400062a4 38.4b +.word 0x15d4cc60,0x3f4ff630 @ φ=0.68222636 : tan φ=3fe9fec5ffff76e2 37.9b +.word 0x166ef280,0x3f581534 @ φ=0.70104337 : tan φ=3feb02a680004e91 38.7b +.word 0x16ff75c0,0x3f5fef1e @ φ=0.71868408 : tan φ=3febfde3c0001404 40.7b +.word 0x179116a0,0x3f68184d @ φ=0.73646098 : tan φ=3fed03099ffed6e5 36.8b +.word 0x181b5aa0,0x3f701722 @ φ=0.75333911 : tan φ=3fee02e43fffd351 39.5b +.word 0x18a10560,0x3f781071 @ φ=0.76965588 : tan φ=3fef020e20005c05 38.5b +.word 0x19214060,0x3f7ff451 @ φ=0.78530902 : tan φ=3feffe8a1fffe11b 40.1b + +#endif diff --git a/src/rp2_common/pico_float/float_v1_rom_shim.S b/src/rp2_common/pico_float/float_v1_rom_shim_rp2040.S similarity index 100% rename from src/rp2_common/pico_float/float_v1_rom_shim.S rename to src/rp2_common/pico_float/float_v1_rom_shim_rp2040.S diff --git a/src/rp2_common/pico_float/include/pico/float.h b/src/rp2_common/pico_float/include/pico/float.h index cbfc724df..70730279d 100644 --- a/src/rp2_common/pico_float/include/pico/float.h +++ b/src/rp2_common/pico_float/include/pico/float.h @@ -30,9 +30,19 @@ extern "C" { * * The following additional optimized functions are also provided: * -* - fix2float, ufix2float, fix642float, ufix642float, float2fix, float2ufix, float2fix64, float2ufix64, float2int, float2int64, float2int_z, float2int64_z +* - int2float, uint2float, int642float, uint642float, fix2float, ufix2float, fix642float, ufix642float +* - float2fix, float2ufix, float2fix64, float2ufix64, float2int, float2uint, float2int64, float2uint64, float2int_z, float2int64_z, float2uint_z, float2uint64_z +* - exp10f, sincosf, powintf +* +* On RP2350 the following additional functions are available; the _fast methods are faster but do not round correctly +* +* - float2fix64_z, fdiv_fast, fsqrt_fast, */ +float int2float(int32_t f); +float uint2float(uint32_t f); +float int642float(int64_t f); +float uint642float(uint64_t f); float fix2float(int32_t m, int e); float ufix2float(uint32_t m, int e); float fix642float(int64_t m, int e); @@ -44,18 +54,28 @@ uint32_t float2ufix(float f, int e); int64_t float2fix64(float f, int e); uint64_t float2ufix64(float f, int e); int32_t float2int(float f); +uint32_t float2uint(float f); int64_t float2int64(float f); +uint64_t float2uint64(float f); // These methods round towards 0. int32_t float2int_z(float f); int64_t float2int64_z(float f); +int32_t float2uint_z(float f); +int64_t float2uint64_z(float f); float exp10f(float x); void sincosf(float x, float *sinx, float *cosx); float powintf(float x, int y); +#if !PICO_RP2040 || PICO_COMBINED_DOCS +int64_t float2fix64_z(float f, int e); +float fdiv_fast(float n, float d); +float fsqrt_fast(float f); +#endif + #ifdef __cplusplus } #endif -#endif \ No newline at end of file +#endif diff --git a/src/rp2_common/pico_i2c_slave/CMakeLists.txt b/src/rp2_common/pico_i2c_slave/CMakeLists.txt index f0f246d2c..c4549c4c2 100644 --- a/src/rp2_common/pico_i2c_slave/CMakeLists.txt +++ b/src/rp2_common/pico_i2c_slave/CMakeLists.txt @@ -4,7 +4,7 @@ if (NOT TARGET pico_i2c_slave) target_sources(pico_i2c_slave INTERFACE ${CMAKE_CURRENT_LIST_DIR}/i2c_slave.c) - target_include_directories(pico_i2c_slave_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_i2c_slave_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_i2c_slave INTERFACE hardware_i2c hardware_irq) endif() diff --git a/src/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h b/src/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h index a1c38250d..ddae0dca5 100644 --- a/src/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h +++ b/src/rp2_common/pico_i2c_slave/include/pico/i2c_slave.h @@ -17,7 +17,7 @@ extern "C" { /** \file pico/i2c_slave.h * \defgroup pico_i2c_slave pico_i2c_slave * - * \brief Functions providing an interrupt driven I2C slave interface. + * \brief Functions providing an interrupt driven I2C slave interface * * This I2C slave helper library configures slave mode and hooks the relevant I2C IRQ * so that a user supplied handler is called with enumerated I2C events. @@ -34,7 +34,7 @@ typedef enum i2c_slave_event_t { I2C_SLAVE_RECEIVE, ///< Data from master is available for reading. Slave must read from Rx FIFO. I2C_SLAVE_REQUEST, ///< Master is requesting data. Slave must write into Tx FIFO. - I2C_SLAVE_FINISH, ///< Master has sent a Stop or Restart signal. Slave may prepare for the next transfer. + I2C_SLAVE_FINISH, ///< Master has sent a Stop or Restart signal. Slave may prepare for the next transfer. } i2c_slave_event_t; /** diff --git a/src/rp2_common/pico_int64_ops/BUILD.bazel b/src/rp2_common/pico_int64_ops/BUILD.bazel index a72dc17db..58685318e 100644 --- a/src/rp2_common/pico_int64_ops/BUILD.bazel +++ b/src/rp2_common/pico_int64_ops/BUILD.bazel @@ -10,8 +10,7 @@ cc_library( linkopts = ["-Wl,--wrap=__aeabi_lmul"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", - "//src/rp2_common/pico_platform", + "//src/rp2_common:pico_platform", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) diff --git a/src/rp2_common/pico_int64_ops/CMakeLists.txt b/src/rp2_common/pico_int64_ops/CMakeLists.txt index cdb4607f5..3c33c8aa7 100644 --- a/src/rp2_common/pico_int64_ops/CMakeLists.txt +++ b/src/rp2_common/pico_int64_ops/CMakeLists.txt @@ -8,7 +8,11 @@ if (NOT TARGET pico_int64_ops) # add alias "default" which is just pico. add_library(pico_int64_ops_default INTERFACE) - target_link_libraries(pico_int64_ops_default INTERFACE pico_int64_ops_pico) + if (PICO_RP2040) + target_link_libraries(pico_int64_ops_default INTERFACE pico_int64_ops_pico) + else() + target_link_libraries(pico_int64_ops_default INTERFACE pico_int64_ops_compiler) + endif() set(PICO_DEFAULT_INT64_OPS_IMPL pico_int64_ops_default) @@ -16,7 +20,7 @@ if (NOT TARGET pico_int64_ops) $>,$,${PICO_DEFAULT_INT64_OPS_IMPL}>) pico_add_library(pico_int64_ops_pico) - target_include_directories(pico_int64_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_int64_ops_pico SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_int64_ops_pico INTERFACE pico_base) target_sources(pico_int64_ops_pico INTERFACE diff --git a/src/rp2_common/pico_lwip/BUILD.bazel b/src/rp2_common/pico_lwip/BUILD.bazel index 8b7e9ec60..5c98e5415 100644 --- a/src/rp2_common/pico_lwip/BUILD.bazel +++ b/src/rp2_common/pico_lwip/BUILD.bazel @@ -7,7 +7,7 @@ cc_library( hdrs = ["include/arch/cc.h"], includes = ["include"], deps = [ - "//src/common/pico_base", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_rand", ], ) @@ -20,8 +20,8 @@ cc_library( target_compatible_with = compatible_with_pico_w(), deps = [ ":pico_lwip", - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_async_context", "//src/rp2_common/pico_rand", ], @@ -34,8 +34,8 @@ cc_library( target_compatible_with = compatible_with_pico_w(), deps = [ ":pico_lwip", - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_async_context", "//src/rp2_common/pico_rand", ], diff --git a/src/rp2_common/pico_lwip/CMakeLists.txt b/src/rp2_common/pico_lwip/CMakeLists.txt index 0ea863869..1a523b781 100644 --- a/src/rp2_common/pico_lwip/CMakeLists.txt +++ b/src/rp2_common/pico_lwip/CMakeLists.txt @@ -47,7 +47,7 @@ if (EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH}) ${PICO_LWIP_PATH}/src/core/timeouts.c ${PICO_LWIP_PATH}/src/core/udp.c ) - target_include_directories(pico_lwip_core_headers INTERFACE + target_include_directories(pico_lwip_core_headers SYSTEM INTERFACE ${PICO_LWIP_PATH}/src/include) pico_add_library(pico_lwip_core4 NOFLAG) @@ -262,7 +262,7 @@ if (EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH}) # our arch/cc.h pico_add_library(pico_lwip_arch NOFLAG) - target_include_directories(pico_lwip_arch_headers INTERFACE + target_include_directories(pico_lwip_arch_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_lwip_arch INTERFACE pico_rand) @@ -286,7 +286,7 @@ if (EXISTS ${PICO_LWIP_PATH}/${LWIP_TEST_PATH}) target_sources(pico_lwip_contrib_freertos INTERFACE ${PICO_LWIP_CONTRIB_PATH}/ports/freertos/sys_arch.c ) - target_include_directories(pico_lwip_contrib_freertos_headers INTERFACE + target_include_directories(pico_lwip_contrib_freertos_headers SYSTEM INTERFACE ${PICO_LWIP_CONTRIB_PATH}/ports/freertos/include ) pico_mirrored_target_link_libraries(pico_lwip_contrib_freertos INTERFACE diff --git a/src/rp2_common/pico_lwip/include/pico/lwip_freertos.h b/src/rp2_common/pico_lwip/include/pico/lwip_freertos.h index b1b9ab508..72d6ccf62 100644 --- a/src/rp2_common/pico_lwip/include/pico/lwip_freertos.h +++ b/src/rp2_common/pico_lwip/include/pico/lwip_freertos.h @@ -17,8 +17,9 @@ extern "C" { /** \file pico/lwip_freertos.h * \defgroup pico_lwip_freertos pico_lwip_freertos * \ingroup pico_lwip -* \brief Glue library for integration lwIP in \c NO_SYS=0 mode with the SDK. Simple \c init and \c deinit -* are all that is required to hook up lwIP (with full blocking API support) via an \ref async_context instance. +* \brief Glue library for integration lwIP in \c NO_SYS=0 mode with the SDK +* +* Simple \c init and \c deinit are all that is required to hook up lwIP (with full blocking API support) via an \ref async_context instance */ /*! \brief Initializes lwIP (NO_SYS=0 mode) support support for FreeRTOS using the provided async_context diff --git a/src/rp2_common/pico_lwip/include/pico/lwip_nosys.h b/src/rp2_common/pico_lwip/include/pico/lwip_nosys.h index cdde9ab05..e87ddf3c4 100644 --- a/src/rp2_common/pico_lwip/include/pico/lwip_nosys.h +++ b/src/rp2_common/pico_lwip/include/pico/lwip_nosys.h @@ -17,8 +17,9 @@ extern "C" { /** \file pico/lwip_nosys.h * \defgroup pico_lwip_nosys pico_lwip_nosys * \ingroup pico_lwip -* \brief Glue library for integration lwIP in \c NO_SYS=1 mode with the SDK. Simple \c init and \c deinit -* are all that is required to hook up lwIP via an \ref async_context instance. +* \brief Glue library for integration lwIP in \c NO_SYS=1 mode with the SDK +* +* Simple \c init and \c deinit are all that is required to hook up lwIP via an \ref async_context instance. */ /*! \brief Initializes lwIP (NO_SYS=1 mode) support support using the provided async_context diff --git a/src/rp2_common/pico_lwip/lwip_freertos.c b/src/rp2_common/pico_lwip/lwip_freertos.c index 8f178d199..7d28d9716 100644 --- a/src/rp2_common/pico_lwip/lwip_freertos.c +++ b/src/rp2_common/pico_lwip/lwip_freertos.c @@ -4,8 +4,6 @@ * SPDX-License-Identifier: BSD-3-Clause */ -// todo graham #ifdef for LWIP inclusion? - #include "pico/async_context.h" #include "pico/time.h" #include "lwip/tcpip.h" diff --git a/src/rp2_common/pico_malloc/BUILD.bazel b/src/rp2_common/pico_malloc/BUILD.bazel index 09e852cbd..944fc1d5e 100644 --- a/src/rp2_common/pico_malloc/BUILD.bazel +++ b/src/rp2_common/pico_malloc/BUILD.bazel @@ -4,7 +4,7 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "pico_malloc", - srcs = ["pico_malloc.c"], + srcs = ["malloc.c"], hdrs = ["include/pico/malloc.h"], includes = ["include"], linkopts = [ @@ -15,8 +15,9 @@ cc_library( ], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", "//src/common/pico_sync", + "//src/rp2_common:pico_platform", + "//src/rp2_common/pico_multicore", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) diff --git a/src/rp2_common/pico_malloc/CMakeLists.txt b/src/rp2_common/pico_malloc/CMakeLists.txt index d6f2a1225..a2a524e9a 100644 --- a/src/rp2_common/pico_malloc/CMakeLists.txt +++ b/src/rp2_common/pico_malloc/CMakeLists.txt @@ -3,10 +3,10 @@ if (NOT TARGET pico_malloc) pico_add_library(pico_malloc) target_sources(pico_malloc INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/pico_malloc.c + ${CMAKE_CURRENT_LIST_DIR}/malloc.c ) - target_include_directories(pico_malloc_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_malloc_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_wrap_function(pico_malloc malloc) pico_wrap_function(pico_malloc calloc) diff --git a/src/rp2_common/pico_malloc/pico_malloc.c b/src/rp2_common/pico_malloc/malloc.c similarity index 80% rename from src/rp2_common/pico_malloc/pico_malloc.c rename to src/rp2_common/pico_malloc/malloc.c index 5d09d93f3..ca5411fc3 100644 --- a/src/rp2_common/pico_malloc/pico_malloc.c +++ b/src/rp2_common/pico_malloc/malloc.c @@ -41,7 +41,9 @@ void *WRAPPER_FUNC(malloc)(size_t size) { mutex_exit(&malloc_mutex); #endif #if PICO_DEBUG_MALLOC - if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { + if (!rc) { + printf("malloc %d failed to allocate memory\n", (uint) size); + } else if (((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { printf("malloc %d %p->%p\n", (uint) size, rc, ((uint8_t *) rc) + size); } #endif @@ -58,11 +60,13 @@ void *WRAPPER_FUNC(calloc)(size_t count, size_t size) { mutex_exit(&malloc_mutex); #endif #if PICO_DEBUG_MALLOC - if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { + if (!rc) { + printf("calloc %d failed to allocate memory\n", (uint) (count * size)); + } else if (((uint8_t *)rc) + count * size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { printf("calloc %d %p->%p\n", (uint) (count * size), rc, ((uint8_t *) rc) + size); } #endif - check_alloc(rc, size); + check_alloc(rc, count * size); return rc; } @@ -75,7 +79,9 @@ void *WRAPPER_FUNC(realloc)(void *mem, size_t size) { mutex_exit(&malloc_mutex); #endif #if PICO_DEBUG_MALLOC - if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { + if (!rc) { + printf("realloc %d failed to allocate memory\n", (uint) size); + } else if (((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) { printf("realloc %p %d->%p\n", mem, (uint) size, rc); } #endif diff --git a/src/rp2_common/pico_mbedtls/BUILD.bazel b/src/rp2_common/pico_mbedtls/BUILD.bazel index e812524b8..c339941cd 100644 --- a/src/rp2_common/pico_mbedtls/BUILD.bazel +++ b/src/rp2_common/pico_mbedtls/BUILD.bazel @@ -5,9 +5,13 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "pico_mbedtls", srcs = ["pico_mbedtls.c"], + hdrs = ["include/sha256_alt.h"], + includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/rp2_common/pico_platform", + "//bazel/config:PICO_MBEDTLS_LIB", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_rand", + "//src/rp2_common/pico_sha256", ], ) diff --git a/src/rp2_common/pico_mbedtls/CMakeLists.txt b/src/rp2_common/pico_mbedtls/CMakeLists.txt index 303a03a76..13976d6fb 100644 --- a/src/rp2_common/pico_mbedtls/CMakeLists.txt +++ b/src/rp2_common/pico_mbedtls/CMakeLists.txt @@ -136,8 +136,11 @@ if (EXISTS ${PICO_MBEDTLS_PATH}/${MBEDTLS_TEST_PATH}) else() target_compile_definitions(pico_mbedtls_headers INTERFACE MBEDTLS_CONFIG_FILE="mbedtls_config.h") endif() + if (TARGET pico_sha256) + pico_mirrored_target_link_libraries(pico_mbedtls INTERFACE pico_sha256) + endif() target_sources(pico_mbedtls INTERFACE ${CMAKE_CURRENT_LIST_DIR}/pico_mbedtls.c) - target_include_directories(pico_mbedtls_headers INTERFACE ${PICO_MBEDTLS_PATH}/include/ ${PICO_MBEDTLS_PATH}/library/) + target_include_directories(pico_mbedtls_headers SYSTEM INTERFACE ${PICO_MBEDTLS_PATH}/include/ ${PICO_MBEDTLS_PATH}/library/ ${CMAKE_CURRENT_LIST_DIR}/include/) function(suppress_mbedtls_warnings) set_source_files_properties( diff --git a/src/rp2_common/pico_mbedtls/include/sha256_alt.h b/src/rp2_common/pico_mbedtls/include/sha256_alt.h new file mode 100644 index 000000000..b6658b2a7 --- /dev/null +++ b/src/rp2_common/pico_mbedtls/include/sha256_alt.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PICO_MBEDTLS_SHA256_ALT_H +#define PICO_MBEDTLS_SHA256_ALT_H + +#if LIB_PICO_SHA256 +#include "pico/sha256.h" + +typedef struct pico_sha256_state mbedtls_sha256_context; +#endif // PICO_RP2350 + +#endif diff --git a/src/rp2_common/pico_mbedtls/pico_mbedtls.c b/src/rp2_common/pico_mbedtls/pico_mbedtls.c index 58789567a..3279a42d1 100644 --- a/src/rp2_common/pico_mbedtls/pico_mbedtls.c +++ b/src/rp2_common/pico_mbedtls/pico_mbedtls.c @@ -1,6 +1,14 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + #include -#include "pico/platform.h" +#include "pico.h" #include "pico/rand.h" +#include "mbedtls/sha256.h" +#include "common.h" /* Function to feed mbedtls entropy. */ int mbedtls_hardware_poll(void *data __unused, unsigned char *output, size_t len, size_t *olen) { @@ -13,3 +21,37 @@ int mbedtls_hardware_poll(void *data __unused, unsigned char *output, size_t len } return 0; } + +#ifdef MBEDTLS_SHA256_ALT +#if !LIB_PICO_SHA256 +#error SHA256 hardware acceleration not supported +#endif + +// PICO_CONFIG: PICO_MBEDTLS_SHA256_ALT_USE_DMA, Whether to use DMA for writing to hardware for the mbedtls SHA-256 hardware acceleration, type=int, default=1, group=pico_stdlib +#ifndef PICO_MBEDTLS_SHA256_ALT_USE_DMA +#define PICO_MBEDTLS_SHA256_ALT_USE_DMA 1 +#endif + +void mbedtls_sha256_init(__unused mbedtls_sha256_context *ctx) { +} + +void mbedtls_sha256_free(__unused mbedtls_sha256_context *ctx) { +} + +int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224) { + hard_assert(!is224); // that's annoying + return pico_sha256_start_blocking(ctx, SHA256_BIG_ENDIAN, PICO_MBEDTLS_SHA256_ALT_USE_DMA); +} + +int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) { + pico_sha256_update_blocking(ctx, input, ilen); + return 0; +} + +int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32]) { + sha256_result_t result; + pico_sha256_finish(ctx, &result); + memcpy(output, result.bytes, 32); + return 0; +} +#endif // MBEDTLS_SHA256_ALT diff --git a/src/rp2_common/pico_mem_ops/BUILD.bazel b/src/rp2_common/pico_mem_ops/BUILD.bazel index e890d8eac..495347c26 100644 --- a/src/rp2_common/pico_mem_ops/BUILD.bazel +++ b/src/rp2_common/pico_mem_ops/BUILD.bazel @@ -2,8 +2,27 @@ load("//bazel:defs.bzl", "compatible_with_rp2") package(default_visibility = ["//visibility:public"]) -cc_library( +alias( name = "pico_mem_ops", + actual = select({ + "//bazel/constraint:rp2040": ":pico_mem_ops_pico", + "//conditions:default": ":pico_mem_ops_compiler", + }), +) + +cc_library( + name = "pico_mem_ops_compiler", + hdrs = ["include/pico/mem_ops.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + visibility = ["//visibility:private"], + deps = [ + "//src/rp2_common:pico_platform_internal", + ], +) + +cc_library( + name = "pico_mem_ops_pico", srcs = [ "mem_ops.c", "mem_ops_aeabi.S", @@ -21,10 +40,10 @@ cc_library( "-Wl,--wrap=__aeabi_memset8", ], target_compatible_with = compatible_with_rp2(), + visibility = ["//visibility:private"], deps = [ - "//src/common/pico_base", + "//src/rp2_common:pico_platform_internal", "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) diff --git a/src/rp2_common/pico_mem_ops/CMakeLists.txt b/src/rp2_common/pico_mem_ops/CMakeLists.txt index 8d66bc637..320aa6878 100644 --- a/src/rp2_common/pico_mem_ops/CMakeLists.txt +++ b/src/rp2_common/pico_mem_ops/CMakeLists.txt @@ -7,7 +7,13 @@ if (NOT TARGET pico_mem_ops) # add alias "default" which is just pico. add_library(pico_mem_ops_default INTERFACE) - target_link_libraries(pico_mem_ops_default INTERFACE pico_mem_ops_pico) + if (PICO_RP2040) + # RP2040 bootrom has optimized versions + target_link_libraries(pico_mem_ops_default INTERFACE pico_mem_ops_pico) + else() + # beware commpiler memcpy cannot be used for unaligned copies in peripheral space + target_link_libraries(pico_mem_ops_default INTERFACE pico_mem_ops_compiler) + endif() set(PICO_DEFAULT_MEM_OPS_IMPL pico_mem_ops_default) @@ -18,10 +24,10 @@ if (NOT TARGET pico_mem_ops) target_sources(pico_mem_ops_pico INTERFACE ${CMAKE_CURRENT_LIST_DIR}/mem_ops_aeabi.S ) - target_include_directories(pico_mem_ops_pico_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_mem_ops_pico_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_mem_ops_pico INTERFACE pico_base) - target_link_libraries(pico_mem_ops INTERFACE pico_bootrom) + target_link_libraries(pico_mem_ops_pico INTERFACE pico_bootrom) pico_wrap_function(pico_mem_ops_pico memcpy) pico_wrap_function(pico_mem_ops_pico memset) diff --git a/src/rp2_common/pico_mem_ops/include/pico/mem_ops.h b/src/rp2_common/pico_mem_ops/include/pico/mem_ops.h index 9f13d6a09..978d3b308 100644 --- a/src/rp2_common/pico_mem_ops/include/pico/mem_ops.h +++ b/src/rp2_common/pico_mem_ops/include/pico/mem_ops.h @@ -12,8 +12,9 @@ /** \file mem_ops.h * \defgroup pico_mem_ops pico_mem_ops * - * \brief Provides optimized replacement implementations of the compiler built-in memcpy, memset and related functions: + * \brief Provides optimized replacement implementations of the compiler built-in memcpy, memset and related functions * + * The functions include: * - memset, memcpy * - __aeabi_memset, __aeabi_memset4, __aeabi_memset8, __aeabi_memcpy, __aeabi_memcpy4, __aeabi_memcpy8 * diff --git a/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S b/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S index cb9bc89fd..3af1378b0 100644 --- a/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S +++ b/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S @@ -6,10 +6,11 @@ #include "pico/asm_helper.S" #include "pico/bootrom.h" +#include "pico/runtime_init.h" pico_default_asm_setup -__pre_init __aeabi_mem_init, 00001 +PICO_RUNTIME_INIT_FUNC_RUNTIME(__aeabi_mem_init, PICO_RUNTIME_INIT_AEABI_MEM_OPS) .macro mem_section name #if PICO_MEM_IN_RAM diff --git a/src/rp2_common/pico_multicore/BUILD.bazel b/src/rp2_common/pico_multicore/BUILD.bazel index 73f5002ac..4e8a704ab 100644 --- a/src/rp2_common/pico_multicore/BUILD.bazel +++ b/src/rp2_common/pico_multicore/BUILD.bazel @@ -1,21 +1,44 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel:defs.bzl", "compatible_with_config", "compatible_with_rp2", "incompatible_with_config") package(default_visibility = ["//visibility:public"]) -cc_library( +alias( name = "pico_multicore", + actual = select({ + "//bazel/constraint:pico_multicore_enabled": ":pico_multicore_enabled", + "//conditions:default": ":pico_multicore_disabled", + }), +) + +cc_library( + name = "pico_multicore_enabled", srcs = ["multicore.c"], hdrs = ["include/pico/multicore.h"], + defines = ["LIB_PICO_MULTICORE=1"], includes = ["include"], - target_compatible_with = compatible_with_rp2(), + target_compatible_with = compatible_with_rp2() + compatible_with_config("//bazel/constraint:pico_multicore_enabled"), deps = [ - "//src/common/pico_base", + "//src/common/hardware_claim", "//src/common/pico_sync", - "//src/rp2_common/hardware_claim", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_sync", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", "//src/rp2_common/pico_runtime", ], ) + +# Stub library that does NOT link in multicore support libs. +cc_library( + name = "pico_multicore_disabled", + hdrs = ["include/pico/multicore.h"], + defines = ["LIB_PICO_MULTICORE=0"], + includes = ["include"], + target_compatible_with = compatible_with_rp2() + incompatible_with_config("//bazel/constraint:pico_multicore_enabled"), + deps = [ + "//src/common/pico_sync", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", + ], +) diff --git a/src/rp2_common/pico_multicore/CMakeLists.txt b/src/rp2_common/pico_multicore/CMakeLists.txt index d796c7090..ab0c628d3 100644 --- a/src/rp2_common/pico_multicore/CMakeLists.txt +++ b/src/rp2_common/pico_multicore/CMakeLists.txt @@ -1,6 +1,6 @@ if (NOT TARGET pico_multicore) pico_add_library(pico_multicore) - target_include_directories(pico_multicore_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_multicore_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_sources(pico_multicore INTERFACE ${CMAKE_CURRENT_LIST_DIR}/multicore.c) @@ -8,6 +8,10 @@ if (NOT TARGET pico_multicore) pico_mirrored_target_link_libraries(pico_multicore INTERFACE pico_sync hardware_irq) + + if (PICO_RISCV) + pico_mirrored_target_link_libraries(pico_multicore INTERFACE hardware_riscv) + endif() endif() diff --git a/src/rp2_common/pico_multicore/include/pico/multicore.h b/src/rp2_common/pico_multicore/include/pico/multicore.h index ae624284a..a45f2a6c7 100644 --- a/src/rp2_common/pico_multicore/include/pico/multicore.h +++ b/src/rp2_common/pico_multicore/include/pico/multicore.h @@ -15,16 +15,21 @@ extern "C" { #endif +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PICO_MULTICORE, Enable/disable assertions in the pico_multicore module, type=bool, default=0, group=pico_multicore +#ifndef PARAM_ASSERTIONS_ENABLED_PICO_MULTICORE +#define PARAM_ASSERTIONS_ENABLED_PICO_MULTICORE 0 +#endif + /** \file multicore.h - * \defgroup pico_multicore pico_multicore - * \brief Adds support for running code on the second processor core (core 1) + * \defgroup pico_multicore pico_multicore + * \brief Adds support for running code on, and interacting with the second processor core (core 1). * * \subsection multicore_example Example * \addtogroup pico_multicore * \include multicore.c */ -// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore +// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Minimum amount of stack space reserved in the linker script for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore #ifndef PICO_CORE1_STACK_SIZE #ifdef PICO_STACK_SIZE #define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE @@ -33,6 +38,31 @@ extern "C" { #endif #endif +/** + * \def SIO_FIFO_IRQ_NUM(core) + * \ingroup pico_multicore + * \hideinitializer + * \brief Returns the \ref irq_num_t for the FIFO IRQ on the given core. + * + * \if rp2040_specific + * On RP2040 each core has a different IRQ number: `SIO_IRQ_PROC0` and `SIO_IRQ_PROC1`. + * \endif + * \if rp2350_specific + * On RP2350 both cores share the same irq number (`SIO_IRQ_PROC`) just with a different SIO + * interrupt output routed to that IRQ input on each core. + * \endif + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef SIO_FIFO_IRQ_NUM +#if !PICO_RP2040 +#define SIO_FIFO_IRQ_NUM(core) SIO_IRQ_FIFO +#else +static_assert(SIO_IRQ_PROC1 == SIO_IRQ_PROC0 + 1, ""); +#define SIO_FIFO_IRQ_NUM(core) (SIO_IRQ_PROC0 + (core)) +#endif +#endif + /*! \brief Reset core 1 * \ingroup pico_multicore * @@ -94,15 +124,15 @@ void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vect * \ingroup pico_multicore * \brief Functions for the inter-core FIFOs * - * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits - * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written - * by core 1, and read by core 0. + * RP-series microcontrollers contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO + * is 32 bits wide, and 8 entries deep on the RP2040, and 4 entries deep on the RP2350. One of the FIFOs can only be written by + * core 0, and read by core 1. The other can only be written by core 1, and read by core 0. * * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully - * well handled by using a \ref queue + * well handled by using a \ref queue */ /*! \brief Check the read FIFO to see if there is data available (sent by the other core) @@ -113,7 +143,7 @@ void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vect * \return true if the FIFO has data in it, false otherwise */ static inline bool multicore_fifo_rvalid(void) { - return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS); + return sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS; } /*! \brief Check the write FIFO to see if it has space for more data @@ -124,14 +154,14 @@ static inline bool multicore_fifo_rvalid(void) { * @return true if the FIFO has room for more data, false otherwise */ static inline bool multicore_fifo_wready(void) { - return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS); + return sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS; } /*! \brief Push data on to the write FIFO (data to the other core). * \ingroup multicore_fifo * * This function will block until there is space for the data to be sent. - * Use multicore_fifo_wready() to check if it is possible to write to the + * Use \ref multicore_fifo_wready() to check if it is possible to write to the * FIFO if you don't want to block. * * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs @@ -140,6 +170,28 @@ static inline bool multicore_fifo_wready(void) { */ void multicore_fifo_push_blocking(uint32_t data); +/*! \brief Push data on to the write FIFO (data to the other core). + * \ingroup multicore_fifo + * + * This function will block until there is space for the data to be sent. + * Use multicore_fifo_wready() to check if it is possible to write to the + * FIFO if you don't want to block. + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \param data A 32 bit value to push on to the FIFO + */ +static inline void multicore_fifo_push_blocking_inline(uint32_t data) { + // We wait for the fifo to have some space + while (!multicore_fifo_wready()) + tight_loop_contents(); + + sio_hw->fifo_wr = data; + + // Fire off an event to the other core + __sev(); +} + /*! \brief Push data on to the write FIFO (data to the other core) with timeout. * \ingroup multicore_fifo * @@ -165,6 +217,26 @@ bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us); */ uint32_t multicore_fifo_pop_blocking(void); +/*! \brief Pop data from the read FIFO (data from the other core). + * \ingroup multicore_fifo + * + * This function will block until there is data ready to be read + * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't + * want to block. + * + * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs + * + * \return 32 bit data from the read FIFO. + */ +static inline uint32_t multicore_fifo_pop_blocking_inline(void) { + // If nothing there yet, we wait for an event first, + // to try and avoid too much busy waiting + while (!multicore_fifo_rvalid()) + __wfe(); + + return sio_hw->fifo_rd; +} + /*! \brief Pop data from the read FIFO (data from the other core) with timeout. * \ingroup multicore_fifo * @@ -222,10 +294,130 @@ static inline uint32_t multicore_fifo_get_status(void) { return sio_hw->fifo_st; } +/*! + * \defgroup multicore_doorbell doorbell + * \ingroup pico_multicore + * \brief Functions related to doorbells which a core can use to raise IRQs on itself or the other core. + * + * \if (rp2040_specific && !combined_docs) + * The doorbell functionality is not available on RP2040. + * \endif + */ + +#if NUM_DOORBELLS +static inline void check_doorbell_num_param(__unused uint doorbell_num) { + invalid_params_if(PICO_MULTICORE, doorbell_num >= NUM_DOORBELLS); +} + +/*! \brief Cooperatively claim the use of this hardware alarm_num + * \ingroup multicore_doorbell + * + * This method hard asserts if the hardware alarm is currently claimed. + * + * \param doorbell_num the doorbell number to claim + * \param core_mask 0b01: core 0, 0b10: core 1, 0b11 both core 0 and core 1 + * \sa hardware_claiming + */ +void multicore_doorbell_claim(uint doorbell_num, uint core_mask); + +/*! \brief Cooperatively claim the use of this hardware alarm_num + * \ingroup multicore_doorbell + * + * This method attempts to claim an unused hardware alarm + * + * \param core_mask 0b01: core 0, 0b10: core 1, 0b11 both core 0 and core 1 + * \param required if true the function will panic if none are available + * \return the doorbell number claimed or -1 if required was false, and none are available + * \sa hardware_claiming + */ +int multicore_doorbell_claim_unused(uint core_mask, bool required); + +/*! \brief Cooperatively release the claim on use of this hardware alarm_num + * \ingroup multicore_doorbell + * + * \param doorbell_num the doorbell number to unclaim + * \param core_mask 0b01: core 0, 0b10: core 1, 0b11 both core 0 and core 1 + * \sa hardware_claiming + */ +void multicore_doorbell_unclaim(uint doorbell_num, uint core_mask); + +/*! \brief Activate the given doorbell on the other core + * \ingroup multicore_doorbell + * \param doorbell_num the doorbell number + */ +static inline void multicore_doorbell_set_other_core(uint doorbell_num) { + check_doorbell_num_param(doorbell_num); + sio_hw->doorbell_out_set = 1u << doorbell_num; +} + +/*! \brief Deactivate the given doorbell on the other core + * \ingroup multicore_doorbell + * \param doorbell_num the doorbell number + */ +static inline void multicore_doorbell_clear_other_core(uint doorbell_num) { + check_doorbell_num_param(doorbell_num); + sio_hw->doorbell_out_clr = 1u << doorbell_num; +} + +/*! \brief Activate the given doorbell on this core + * \ingroup multicore_doorbell + * \param doorbell_num the doorbell number + */ +static inline void multicore_doorbell_set_current_core(uint doorbell_num) { + check_doorbell_num_param(doorbell_num); + sio_hw->doorbell_in_set = 1u << doorbell_num; +} + +/*! \brief Deactivate the given doorbell on this core + * \ingroup multicore_doorbell + * \param doorbell_num the doorbell number + */ +static inline void multicore_doorbell_clear_current_core(uint doorbell_num) { + check_doorbell_num_param(doorbell_num); + sio_hw->doorbell_in_clr = 1u << doorbell_num; +} + +/*! \brief Determine if the given doorbell is active on the other core + * \ingroup multicore_doorbell + * \param doorbell_num the doorbell number + */ +static inline bool multicore_doorbell_is_set_current_core(uint doorbell_num) { + check_doorbell_num_param(doorbell_num); + return sio_hw->doorbell_in_set & (1u << doorbell_num); +} + +/*! \brief Determine if the given doorbell is active on the this core + * \ingroup multicore_doorbell + * \param doorbell_num the doorbell number + */ +static inline bool multicore_doorbell_is_set_other_core(uint doorbell_num) { + check_doorbell_num_param(doorbell_num); + return sio_hw->doorbell_out_set & (1u << doorbell_num); +} + +/** + * \def DOORBELL_IRQ_NUM(doorbell_num) + * \ingroup multicore_doorbell + * \hideinitializer + * \brief Returns the \ref irq_num_t for processor interrupts for the given doorbell number + * + * Note this macro is intended to resolve at compile time, and does no parameter checking + */ +#ifndef DOORBELL_IRQ_NUM +#define DOORBELL_IRQ_NUM(doorbell_num) SIO_IRQ_BELL +#endif + +static inline uint multicore_doorbell_irq_num(uint doorbell_num) { + check_doorbell_num_param(doorbell_num); + return DOORBELL_IRQ_NUM(doorbell_num); +} + +#endif + /*! * \defgroup multicore_lockout lockout * \ingroup pico_multicore - * \brief Functions to enable one core to force the other core to pause execution in a known state. + * \brief Functions to enable one core to force the other core to pause execution in a known state * * Sometimes it is useful to enter a critical section on both cores at once. On a single * core system a critical section can trivially be entered by disabling interrupts, however on a multi-core diff --git a/src/rp2_common/pico_multicore/multicore.c b/src/rp2_common/pico_multicore/multicore.c index d24f36752..58c2ee289 100644 --- a/src/rp2_common/pico_multicore/multicore.c +++ b/src/rp2_common/pico_multicore/multicore.c @@ -7,12 +7,20 @@ #include "pico/multicore.h" #include "hardware/sync.h" #include "hardware/irq.h" +#include "pico/runtime_init.h" +#ifdef __riscv +#include "hardware/riscv.h" +#else #include "hardware/structs/scb.h" +#endif #include "hardware/structs/sio.h" #include "hardware/regs/psm.h" #include "hardware/claim.h" -#if PICO_USE_STACK_GUARDS -#include "pico/runtime.h" + +#if !PICO_RP2040 +#ifndef __riscv +#include "hardware/structs/m33.h" +#endif #endif // note that these are not reset by core reset, however for now, I think people resetting cores @@ -23,17 +31,6 @@ // and means pulling in this array even if multicore_lockout is not used. static bool lockout_victim_initialized[NUM_CORES]; -static inline void multicore_fifo_push_blocking_inline(uint32_t data) { - // We wait for the fifo to have some space - while (!multicore_fifo_wready()) - tight_loop_contents(); - - sio_hw->fifo_wr = data; - - // Fire off an event to the other core - __sev(); -} - void multicore_fifo_push_blocking(uint32_t data) { multicore_fifo_push_blocking_inline(data); } @@ -53,16 +50,7 @@ bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us) { return true; } -static inline uint32_t multicore_fifo_pop_blocking_inline(void) { - // If nothing there yet, we wait for an event first, - // to try and avoid too much busy waiting - while (!multicore_fifo_rvalid()) - __wfe(); - - return sio_hw->fifo_rd; -} - -uint32_t multicore_fifo_pop_blocking() { +uint32_t multicore_fifo_pop_blocking(void) { return multicore_fifo_pop_blocking_inline(); } @@ -82,21 +70,34 @@ bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out) { static uint32_t __attribute__((section(".stack1"))) core1_stack[PICO_CORE1_STACK_SIZE / sizeof(uint32_t)]; static void __attribute__ ((naked)) core1_trampoline(void) { - pico_default_asm ("pop {r0, r1, pc}"); +#ifdef __riscv + // Do not add function calls here, because we want to preserve the return + // address pointing back to the bootrom launch routine. + pico_default_asm( + "lw a0, 0(sp)\n" + "lw a1, 4(sp)\n" + "lw a2, 8(sp)\n" + "lw gp, 12(sp)\n" + "addi sp, sp, 16\n" + "jr a2\n" + ); +#else + pico_default_asm("pop {r0, r1, pc}"); +#endif } int core1_wrapper(int (*entry)(void), void *stack_base) { -#if PICO_USE_STACK_GUARDS +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD // install core1 stack guard - runtime_install_stack_guard(stack_base); + runtime_init_per_core_install_stack_guard(stack_base); #else - __unused void *ignore = stack_base; + (void)stack_base; #endif - irq_init_priorities(); + runtime_run_per_core_initializers(); return (*entry)(); } -void multicore_reset_core1() { +void multicore_reset_core1(void) { // Use atomic aliases just in case core 1 is also manipulating some PSM state io_rw_32 *power_off = (io_rw_32 *) (PSM_BASE + PSM_FRCE_OFF_OFFSET); io_rw_32 *power_off_set = hw_set_alias(power_off); @@ -110,9 +111,10 @@ void multicore_reset_core1() { // Allow for the fact that the caller may have already enabled the FIFO IRQ for their // own purposes (expecting FIFO content after core 1 is launched). We must disable - // the IRQ during the handshake, then restore afterwards. - bool enabled = irq_is_enabled(SIO_IRQ_PROC0); - irq_set_enabled(SIO_IRQ_PROC0, false); + // the IRQ during the handshake, then restore afterward + uint irq_num = SIO_FIFO_IRQ_NUM(0); + bool enabled = irq_is_enabled(irq_num); + irq_set_enabled(irq_num, false); // Bring core 1 back out of reset. It will drain its own mailbox FIFO, then push // a 0 to our mailbox to tell us it has done this. @@ -124,22 +126,30 @@ void multicore_reset_core1() { (void) value; // silence warning // restore interrupt state - irq_set_enabled(SIO_IRQ_PROC0, enabled); + irq_set_enabled(irq_num, enabled); } void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes) { assert(!(stack_size_bytes & 3u)); uint32_t *stack_ptr = stack_bottom + stack_size_bytes / sizeof(uint32_t); - // push 2 values onto top of stack for core1_trampoline + // Push values onto top of stack for core1_trampoline +#ifdef __riscv + // On RISC-V we also need to initialise the global pointer + stack_ptr -= 4; + uint32_t vector_table = riscv_read_csr(mtvec); + asm volatile ("mv %0, gp" : "=r"(stack_ptr[3])); +#else stack_ptr -= 3; + uint32_t vector_table = scb_hw->vtor; +#endif stack_ptr[0] = (uintptr_t) entry; stack_ptr[1] = (uintptr_t) stack_bottom; stack_ptr[2] = (uintptr_t) core1_wrapper; #if PICO_VTABLE_PER_CORE -#warning PICO_VTABLE_PER_CORE==1 is not currently supported in pico_multicore + #warning PICO_VTABLE_PER_CORE==1 is not currently supported in pico_multicore panic_unsupported(); #endif - multicore_launch_core1_raw(core1_trampoline, stack_ptr, scb_hw->vtor); + multicore_launch_core1_raw(core1_trampoline, stack_ptr, vector_table); } void multicore_launch_core1(void (*entry)(void)) { @@ -154,8 +164,9 @@ void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vect // Allow for the fact that the caller may have already enabled the FIFO IRQ for their // own purposes (expecting FIFO content after core 1 is launched). We must disable // the IRQ during the handshake, then restore afterwards. - bool enabled = irq_is_enabled(SIO_IRQ_PROC0); - irq_set_enabled(SIO_IRQ_PROC0, false); + uint irq_num = SIO_FIFO_IRQ_NUM(0); + bool enabled = irq_is_enabled(irq_num); + irq_set_enabled(irq_num, false); // Values to be sent in order over the FIFO from core 0 to core 1 // @@ -180,14 +191,12 @@ void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vect seq = cmd == response ? seq + 1 : 0; } while (seq < count_of(cmd_sequence)); - irq_set_enabled(SIO_IRQ_PROC0, enabled); + irq_set_enabled(irq_num, enabled); } #define LOCKOUT_MAGIC_START 0x73a8831eu #define LOCKOUT_MAGIC_END (~LOCKOUT_MAGIC_START) -static_assert(SIO_IRQ_PROC1 == SIO_IRQ_PROC0 + 1, ""); - static mutex_t lockout_mutex; static bool lockout_in_progress; @@ -202,7 +211,7 @@ static void __isr __not_in_flash_func(multicore_lockout_handler)(void) { while (multicore_fifo_pop_blocking_inline() != LOCKOUT_MAGIC_END) { tight_loop_contents(); // not tight but endless potentially } - restore_interrupts(save); + restore_interrupts_from_disabled(save); multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_END); } } @@ -219,14 +228,17 @@ static void check_lockout_mutex_init(void) { void multicore_lockout_victim_init(void) { check_lockout_mutex_init(); + // On platforms other than RP2040, these are actually the same IRQ number + // (each core only sees its own IRQ, always at the same IRQ number). uint core_num = get_core_num(); - irq_set_exclusive_handler(SIO_IRQ_PROC0 + core_num, multicore_lockout_handler); - irq_set_enabled(SIO_IRQ_PROC0 + core_num, true); + uint fifo_irq_this_core = SIO_FIFO_IRQ_NUM(core_num); + irq_set_exclusive_handler(fifo_irq_this_core, multicore_lockout_handler); + irq_set_enabled(fifo_irq_this_core, true); lockout_victim_initialized[core_num] = true; } static bool multicore_lockout_handshake(uint32_t magic, absolute_time_t until) { - uint irq_num = SIO_IRQ_PROC0 + get_core_num(); + uint irq_num = SIO_FIFO_IRQ_NUM(get_core_num()); bool enabled = irq_is_enabled(irq_num); if (enabled) irq_set_enabled(irq_num, false); bool rc = false; @@ -296,4 +308,78 @@ void multicore_lockout_end_blocking(void) { bool multicore_lockout_victim_is_initialized(uint core_num) { return lockout_victim_initialized[core_num]; -} \ No newline at end of file +} + +#if NUM_DOORBELLS + +static uint8_t doorbell_claimed[NUM_CORES][(NUM_DOORBELLS + 7) >> 3]; + +static inline bool is_bit_claimed(const uint8_t *bits, uint bit_index) { + return (bits[bit_index >> 3u] & (1u << (bit_index & 7u))); +} + +static inline void set_claimed_bit(uint8_t *bits, uint bit_index) { + bits[bit_index >> 3u] |= ( uint8_t ) ( 1u << ( bit_index & 7u )); +} + +static inline void clear_claimed_bit(uint8_t *bits, uint bit_index) { + bits[bit_index >> 3u] &= ( uint8_t ) ~( 1u << ( bit_index & 7u )); +} + +static bool multicore_doorbell_claim_under_lock(uint doorbell_num, uint core_mask, bool required) { + static_assert(NUM_CORES == 2, ""); + uint claimed_cores_for_doorbell = (uint) (is_bit_claimed(doorbell_claimed[0], doorbell_num) | + (is_bit_claimed(doorbell_claimed[1], doorbell_num + 1u) << 1)); + if (claimed_cores_for_doorbell & core_mask) { + if (required) { + panic( "Multicoore doorbell %d already claimed on core mask 0x%x; requested core mask 0x%x\n", + claimed_cores_for_doorbell, core_mask); + } + return false; + } else { + for(uint i=0; i=0; i--) { + if (multicore_doorbell_claim_under_lock((uint) i, core_mask, false)) { + rc = i; + break; + } + } + if (required && rc < 0) { + panic("No free doorbells"); + } + hw_claim_unlock(save); + return rc; +} + +void multicore_doorbell_unclaim(uint doorbell_num, uint core_mask) { + check_doorbell_num_param(doorbell_num); + uint32_t save = hw_claim_lock(); + for(uint i=0; i < NUM_CORES; i++) { + if (core_mask & (1u << i)) { + assert(is_bit_claimed(doorbell_claimed[i], doorbell_num)); + clear_claimed_bit(doorbell_claimed[i], doorbell_num); + } + } + hw_claim_unlock(save); +} + + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_platform/BUILD.bazel b/src/rp2_common/pico_platform/BUILD.bazel deleted file mode 100644 index a81029733..000000000 --- a/src/rp2_common/pico_platform/BUILD.bazel +++ /dev/null @@ -1,61 +0,0 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") - -package(default_visibility = ["//visibility:public"]) - -alias( - name = "platform_defs", - actual = select({ - "//bazel/constraint:rp2040": "//src/rp2040/hardware_regs:platform_defs", - }), - target_compatible_with = compatible_with_rp2(), -) - -alias( - name = "hardware_regs", - actual = select({ - "//bazel/constraint:rp2040": "//src/rp2040/hardware_regs:hardware_regs", - }), - target_compatible_with = compatible_with_rp2(), -) - -alias( - name = "hardware_structs", - actual = select({ - "//bazel/constraint:rp2040": "//src/rp2040/hardware_structs:hardware_structs", - }), - target_compatible_with = compatible_with_rp2(), -) - -cc_library( - name = "pico_platform", - srcs = ["platform.c"], - hdrs = [ - "include/pico/asm_helper.S", - "include/pico/platform.h", - ], - includes = ["include"], - target_compatible_with = compatible_with_rp2(), - deps = [ - ":hardware_regs", - ":platform_defs", - "//src/common/pico_base:pico_base_interface", - "//src/rp2_common/hardware_base", - ], -) - -cc_library( - name = "platform_link_deps", - target_compatible_with = compatible_with_rp2(), - deps = select({ - # When PICO_BARE_METAL is enabled, don't automagically add link-time - # dependencies. - "//bazel/constraint:pico_baremetal_enabled": [], - "//conditions:default": [ - "//bazel/config:PICO_BOOT_STAGE2_LINK_IMAGE", - "//bazel/config:PICO_CMSIS_PATH", - "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_runtime", - "//src/rp2_common/pico_standard_link", - ], - }), -) diff --git a/src/rp2_common/pico_platform/include/pico/platform.h b/src/rp2_common/pico_platform/include/pico/platform.h deleted file mode 100644 index 7fe20aa4b..000000000 --- a/src/rp2_common/pico_platform/include/pico/platform.h +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PICO_PLATFORM_H -#define _PICO_PLATFORM_H - -/** \file platform.h - * \defgroup pico_platform pico_platform - * - * \brief Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture - * to provide a common abstraction over low level compiler / platform specifics. - * - * This header may be included by assembly code - */ - -#include "hardware/platform_defs.h" -#include "hardware/regs/addressmap.h" -#include "hardware/regs/sio.h" - -// Marker for builds targeting the RP2040 -#define PICO_RP2040 1 - -// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_platform -#ifndef PICO_STACK_SIZE -#define PICO_STACK_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_platform -#ifndef PICO_HEAP_SIZE -#define PICO_HEAP_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform -#ifndef PICO_NO_RAM_VECTOR_TABLE -#define PICO_NO_RAM_VECTOR_TABLE 0 -#endif - -// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_RP2040_B0_SUPPORTED -#define PICO_RP2040_B0_SUPPORTED 1 -#endif - -// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_FLOAT_SUPPORT_ROM_V1 -#define PICO_FLOAT_SUPPORT_ROM_V1 1 -#endif - -// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_DOUBLE_SUPPORT_ROM_V1 -#define PICO_DOUBLE_SUPPORT_ROM_V1 1 -#endif - - -// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_RP2040_B1_SUPPORTED -#define PICO_RP2040_B1_SUPPORTED 1 -#endif - -// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform -#ifndef PICO_RP2040_B2_SUPPORTED -#define PICO_RP2040_B2_SUPPORTED 1 -#endif - -// --- remainder of file is not included by assembly code --- - -#ifndef __ASSEMBLER__ - -#if defined __GNUC__ -#include -// note LLVM defines __GNUC__ -#ifdef __clang__ -#define PICO_C_COMPILER_IS_CLANG 1 -#else -#define PICO_C_COMPILER_IS_GNU 1 -#endif -#elif defined __ICCARM__ -#ifndef __aligned -#define __aligned(x) __attribute__((__aligned__(x))) -#endif -#ifndef __always_inline -#define __always_inline __attribute__((__always_inline__)) -#endif -#ifndef __noinline -#define __noinline __attribute__((__noinline__)) -#endif -#ifndef __packed -#define __packed __attribute__((__packed__)) -#endif -#ifndef __printflike -#define __printflike(a, b) -#endif -#ifndef __unused -#define __unused __attribute__((__unused__)) -#endif -#ifndef __used -#define __used __attribute__((__used__)) -#endif -#ifndef __CONCAT1 -#define __CONCAT1(a, b) a ## b -#endif -#ifndef __CONCAT -#define __CONCAT(a, b) __CONCAT1(a, b) -#endif -#ifndef __STRING -#define __STRING(a) #a -#endif -/* Compatible definitions of GCC builtins */ - -static inline uint __builtin_ctz(uint x) { - extern uint32_t __ctzsi2(uint32_t); - return __ctzsi2(x); -} -#define __builtin_expect(x, y) (x) -#define __builtin_isnan(x) __iar_isnan(x) -#else -#error Unsupported toolchain -#endif - -#include "pico/types.h" - -// GCC_Like_Pragma(x) is a pragma on GNUC compatible compilers -#ifdef __GNUC__ -#define GCC_Like_Pragma _Pragma -#else -#define GCC_Like_Pragma(x) -#endif - -// Clang_Pragma(x) is a pragma on Clang only -#ifdef __clang__ -#define Clang_Pragma _Pragma -#else -#define Clang_Pragma(x) -#endif - -// GCC_Pragma(x) is a pragma on GCC only -#if PICO_C_COMPILER_IS_GNU -#define GCC_Pragma _Pragma -#else -#define GCC_Pragma(x) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/*! \brief Marker for an interrupt handler - * \ingroup pico_platform - * - * For example an IRQ handler function called my_interrupt_handler: - * - * void __isr my_interrupt_handler(void) { - */ -#define __isr - -/*! \brief Section attribute macro for placement in RAM after the `.data` section - * \ingroup pico_platform - * - * For example a 400 element `uint32_t` array placed after the .data section - * - * uint32_t __after_data("my_group_name") a_big_array[400]; - * - * The section attribute is `.after_data.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#define __after_data(group) __attribute__((section(".after_data." group))) - -/*! \brief Section attribute macro for placement not in flash (i.e in RAM) - * \ingroup pico_platform - * - * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`) - * - * static const uint32_t __not_in_flash("my_group_name") an_array[3]; - * - * The section attribute is `.time_critical.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#define __not_in_flash(group) __attribute__((section(".time_critical." group))) - -/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X") - * \ingroup pico_platform - * - * Scratch X is commonly used for critical data and functions accessed only by one core (when only - * one core is accessing the RAM bank, there is no opportunity for stalls) - * - * For example a `uint32_t` variable placed in "scratch X" - * - * uint32_t __scratch_x("my_group_name") foo = 23; - * - * The section attribute is `.scratch_x.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#define __scratch_x(group) __attribute__((section(".scratch_x." group))) - -/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y") - * \ingroup pico_platform - * - * Scratch Y is commonly used for critical data and functions accessed only by one core (when only - * one core is accessing the RAM bank, there is no opportunity for stalls) - * - * For example a `uint32_t` variable placed in "scratch Y" - * - * uint32_t __scratch_y("my_group_name") foo = 23; - * - * The section attribute is `.scratch_y.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#define __scratch_y(group) __attribute__((section(".scratch_y." group))) - -/*! \brief Section attribute macro for data that is to be left uninitialized - * \ingroup pico_platform - * - * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss - * section) is initialized to zero during runtime initialization - * - * For example a `uint32_t` foo that will retain its value if the program is restarted by reset. - * - * uint32_t __uninitialized_ram(foo); - * - * The section attribute is `.uninitialized_data.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#define __uninitialized_ram(group) __attribute__((section(".uninitialized_data." #group))) group - -/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary - * \ingroup pico_platform - * - * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!) - * - * uint32_t __in_flash("my_group_name") foo = 23; - * - * The section attribute is `.flashdata.` - * - * \param group a string suffix to use in the section name to distinguish groups that can be linker - * garbage-collected independently - */ -#define __in_flash(group) __attribute__((section(".flashdata." group))) - -/*! \brief Indicates a function should not be stored in flash - * \ingroup pico_platform - * - * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined - * into a flash function by the compiler) - * - * For example a function called my_func taking an int parameter: - * - * void __not_in_flash_func(my_func)(int some_arg) { - * - * The function is placed in the `.time_critical.` linker section - * - * \see __no_inline_not_in_flash_func - */ -#define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name - -/*! \brief Indicates a function is time/latency critical and should not run from flash - * \ingroup pico_platform - * - * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined - * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical - * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func` - * may in the future be treated more specially to reduce the overhead when calling such function from a flash - * function. - * - * For example a function called my_func taking an int parameter: - * - * void __time_critical(my_func)(int some_arg) { - * - * The function is placed in the `.time_critical.` linker section - * - * \see __not_in_flash_func - */ -#define __time_critical_func(func_name) __not_in_flash_func(func_name) - -/*! \brief Indicate a function should not be stored in flash and should not be inlined - * \ingroup pico_platform - * - * Decorates a function name, such that the function will execute from RAM, explicitly marking it as - * noinline to prevent it being inlined into a flash function by the compiler - * - * For example a function called my_func taking an int parameter: - * - * void __no_inline_not_in_flash_func(my_func)(int some_arg) { - * - * The function is placed in the `.time_critical.` linker section - */ -#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name) - -#define __packed_aligned __packed __aligned(4) - -/*! \brief Attribute to force inlining of a function regardless of optimization level - * \ingroup pico_platform - * - * For example my_function here will always be inlined: - * - * int __force_inline my_function(int x) { - * - */ - -#if PICO_C_COMPILER_IS_GNU && (__GNUC__ <= 6 || (__GNUC__ == 7 && (__GNUC_MINOR__ < 3 || !defined(__cplusplus)))) -#define __force_inline inline __always_inline -#else -#define __force_inline __always_inline -#endif - -/*! \brief Macro to determine the number of elements in an array - * \ingroup pico_platform - */ -#ifndef count_of -#define count_of(a) (sizeof(a)/sizeof((a)[0])) -#endif - -/*! \brief Macro to return the maximum of two comparable values - * \ingroup pico_platform - */ -#ifndef MAX -#define MAX(a, b) ((a)>(b)?(a):(b)) -#endif - -/*! \brief Macro to return the minimum of two comparable values - * \ingroup pico_platform - */ -#ifndef MIN -#define MIN(a, b) ((b)>(a)?(a):(b)) -#endif - -#define pico_default_asm(...) __asm (".syntax unified\n" __VA_ARGS__) -#define pico_default_asm_volatile(...) __asm volatile (".syntax unified\n" __VA_ARGS__) - -/*! \brief Execute a breakpoint instruction - * \ingroup pico_platform - */ -static inline void __breakpoint(void) { - pico_default_asm ("bkpt #0"); -} - -/*! \brief Ensure that the compiler does not move memory access across this method call - * \ingroup pico_platform - * - * For example in the following code: - * - * *some_memory_location = var_a; - * __compiler_memory_barrier(); - * uint32_t var_b = *some_other_memory_location - * - * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise - * might - even above the memory store!) - */ -__force_inline static void __compiler_memory_barrier(void) { - pico_default_asm_volatile ("" : : : "memory"); -} - -/*! \brief Macro for converting memory addresses to 32 bit addresses suitable for DMA - * \ingroup pico_platform - * - * This is just a cast to `uintptr_t` on the RP2040, however you may want to use this when developing code - * that also runs in "host" mode. If the host mode is 64 bit and you are embedding data pointers - * in other data (e.g. DMA chaining), then there is a need in "host" mode to convert a 64 bit native - * pointer to a 32 bit value for storage, which can be done using this macro. - */ -#define host_safe_hw_ptr(x) ((uintptr_t)(x)) -#define native_safe_hw_ptr(x) host_safe_hw_ptr(x) - - -/*! \brief Panics with the message "Unsupported" - * \ingroup pico_platform - * \see panic - */ -void __attribute__((noreturn)) panic_unsupported(void); - -/*! \brief Displays a panic message and halts execution - * \ingroup pico_platform - * - * An attempt is made to output the message to all registered STDOUT drivers - * after which this method executes a BKPT instruction. - * - * @param fmt format string (printf-like) - * @param ... printf-like arguments - */ -void __attribute__((noreturn)) panic(const char *fmt, ...); - -#ifdef NDEBUG -#define panic_compact(...) panic(__VA_ARGS__) -#else -#define panic_compact(...) panic("") -#endif - -// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=0, advanced=true, group=pico_runtime -#ifndef PICO_NO_FPGA_CHECK -#define PICO_NO_FPGA_CHECK 0 -#endif - -#if PICO_NO_FPGA_CHECK -static inline bool running_on_fpga(void) {return false;} -#else -bool running_on_fpga(void); -#endif - -/*! \brief Returns the RP2040 chip revision number - * \ingroup pico_platform - * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2) - */ -uint8_t rp2040_chip_version(void); - -/*! \brief Returns the RP2040 rom version number - * \ingroup pico_platform - * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2) - */ -static inline uint8_t rp2040_rom_version(void) { -GCC_Pragma("GCC diagnostic push") -GCC_Pragma("GCC diagnostic ignored \"-Warray-bounds\"") - return *(uint8_t*)0x13; -GCC_Pragma("GCC diagnostic pop") -} - -/*! \brief No-op function for the body of tight loops - * \ingroup pico_platform - * - * No-op function intended to be called by any tight hardware polling loop. Using this ubiquitously - * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup - * debugging might be added - */ -static __force_inline void tight_loop_contents(void) {} - -/*! \brief Multiply two integers using an assembly `MUL` instruction - * \ingroup pico_platform - * - * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler - * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation. - * - * \param a the first operand - * \param b the second operand - * \return a * b - */ -__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) { - pico_default_asm ("muls %0, %1" : "+l" (a) : "l" (b) : ); - return a; -} - -/*! \brief multiply two integer values using the fastest method possible - * \ingroup pico_platform - * - * Efficiently multiplies value a by possibly constant value b. - * - * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default - * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable - * and will be used - * - * \param a the first operand - * \param b the second operand - * \return a * b - */ -#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \ -(__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \ -(a)*(b)) - -/*! \brief Utility macro to assert two types are equivalent. - * \ingroup pico_platform - * - * This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type - * (or that a single parameter is of an expected type) - */ -#define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b)); - -/*! \brief Get the current exception level on this core - * \ingroup pico_platform - * - * \return the exception number if the CPU is handling an exception, or 0 otherwise - */ -static __force_inline uint __get_current_exception(void) { - uint exception; - pico_default_asm( "mrs %0, ipsr" : "=l" (exception)); - return exception; -} - -#define WRAPPER_FUNC(x) __wrap_ ## x -#define REAL_FUNC(x) __real_ ## x - -/*! \brief Helper method to busy-wait for at least the given number of cycles - * \ingroup pico_platform - * - * This method is useful for introducing very short delays. - * - * This method busy-waits in a tight loop for the given number of system clock cycles. The total wait time is only accurate to within 2 cycles, - * and this method uses a loop counter rather than a hardware timer, so the method will always take longer than expected if an - * interrupt is handled on the calling core during the busy-wait; you can of course disable interrupts to prevent this. - * - * You can use \ref clock_get_hz(clk_sys) to determine the number of clock cycles per second if you want to convert an actual - * time duration to a number of cycles. - * - * \param minimum_cycles the minimum number of system clock cycles to delay for - */ -static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) { - pico_default_asm_volatile( - "1: subs %0, #3\n" - "bcs 1b\n" - : "+l" (minimum_cycles) : : "memory" - ); -} - -/*! \brief Get the current core number - * \ingroup pico_platform - * - * \return The core number the call was made from - */ -__force_inline static uint get_core_num(void) { - return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET)); -} - -#ifdef __cplusplus -} -#endif - -#else // __ASSEMBLER__ - -#if defined __GNUC__ -// note LLVM defines __GNUC__ -#ifdef __clang__ -#define PICO_ASSEMBLER_IS_CLANG 1 -#else -#define PICO_ASSEMBLER_IS_GNU 1 -#endif -#elif defined __ICCARM__ -#else -#error Unsupported toolchain -#endif - -#define WRAPPER_FUNC_NAME(x) __wrap_##x -#define SECTION_NAME(x) .text.##x -#define RAM_SECTION_NAME(x) .time_critical.##x - -#endif // !__ASSEMBLER__ - -#endif diff --git a/src/rp2_common/pico_platform_compiler/BUILD.bazel b/src/rp2_common/pico_platform_compiler/BUILD.bazel new file mode 100644 index 000000000..aa6486708 --- /dev/null +++ b/src/rp2_common/pico_platform_compiler/BUILD.bazel @@ -0,0 +1,14 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_platform_compiler", + hdrs = ["include/pico/platform/compiler.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/rp2_common:platform_defs", + "//src/rp2_common/pico_clib_interface", + ], +) diff --git a/src/rp2_common/pico_platform_compiler/CMakeLists.txt b/src/rp2_common/pico_platform_compiler/CMakeLists.txt new file mode 100644 index 000000000..195e3bc3b --- /dev/null +++ b/src/rp2_common/pico_platform_compiler/CMakeLists.txt @@ -0,0 +1,7 @@ +if (NOT TARGET pico_platform_compiler) + pico_add_library(pico_platform_compiler) + + target_include_directories(pico_platform_compiler_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + + target_link_libraries(pico_platform_compiler_headers INTERFACE hardware_regs) +endif() diff --git a/src/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h b/src/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h new file mode 100644 index 000000000..cd1ad526f --- /dev/null +++ b/src/rp2_common/pico_platform_compiler/include/pico/platform/compiler.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_PLATFORM_COMPILER_H +#define _PICO_PLATFORM_COMPILER_H + +/** \file platform_compiler.h + * \defgroup pico_platform pico_platform + * + * \brief Macros and definitions (and functions when included by non assembly code) to adapt for different compilers + * + * This header may be included by assembly code + */ + +#include "hardware/platform_defs.h" + +#ifndef __ASSEMBLER__ + +#if defined __GNUC__ +#include +// note LLVM defines __GNUC__ +#ifdef __clang__ +#define PICO_C_COMPILER_IS_CLANG 1 +#else +#define PICO_C_COMPILER_IS_GNU 1 +#endif +#elif defined __ICCARM__ +#ifndef __aligned +#define __aligned(x) __attribute__((__aligned__(x))) +#endif +#ifndef __always_inline +#define __always_inline __attribute__((__always_inline__)) +#endif +#ifndef __noinline +#define __noinline __attribute__((__noinline__)) +#endif +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif +#ifndef __printflike +#define __printflike(a, b) +#endif +#ifndef __unused +#define __unused __attribute__((__unused__)) +#endif +#ifndef __used +#define __used __attribute__((__used__)) +#endif +#ifndef __CONCAT1 +#define __CONCAT1(a, b) a ## b +#endif +#ifndef __CONCAT +#define __CONCAT(a, b) __CONCAT1(a, b) +#endif +#ifndef __STRING +#define __STRING(a) #a +#endif +/* Compatible definitions of GCC builtins */ + +static inline uint __builtin_ctz(uint x) { + extern uint32_t __ctzsi2(uint32_t); + return __ctzsi2(x); +} +#define __builtin_expect(x, y) (x) +#define __builtin_isnan(x) __iar_isnan(x) +#else +#error Unsupported toolchain +#endif + +#define __weak __attribute__((weak)) + +#include "pico/types.h" + +// GCC_Like_Pragma(x) is a pragma on GNUC compatible compilers +#ifdef __GNUC__ +#define GCC_Like_Pragma _Pragma +#else +#define GCC_Like_Pragma(x) +#endif + +// Clang_Pragma(x) is a pragma on Clang only +#ifdef __clang__ +#define Clang_Pragma _Pragma +#else +#define Clang_Pragma(x) +#endif + +// GCC_Pragma(x) is a pragma on GCC only +#if PICO_C_COMPILER_IS_GNU +#define GCC_Pragma _Pragma +#else +#define GCC_Pragma(x) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief Marker for an interrupt handler + * \ingroup pico_platform + * + * For example an IRQ handler function called my_interrupt_handler: + * + * void __isr my_interrupt_handler(void) { + */ +#define __isr + +#define __packed_aligned __packed __aligned(4) + +/*! \brief Attribute to force inlining of a function regardless of optimization level + * \ingroup pico_platform + * + * For example my_function here will always be inlined: + * + * int __force_inline my_function(int x) { + * + */ + +#if PICO_C_COMPILER_IS_GNU && (__GNUC__ <= 6 || (__GNUC__ == 7 && (__GNUC_MINOR__ < 3 || !defined(__cplusplus)))) +#define __force_inline inline __always_inline +#else +#define __force_inline __always_inline +#endif + +/*! \brief Macro to determine the number of elements in an array + * \ingroup pico_platform + */ +#ifndef count_of +#define count_of(a) (sizeof(a)/sizeof((a)[0])) +#endif + +/*! \brief Macro to return the maximum of two comparable values + * \ingroup pico_platform + */ +#ifndef MAX +#define MAX(a, b) ((a)>(b)?(a):(b)) +#endif + +/*! \brief Macro to return the minimum of two comparable values + * \ingroup pico_platform + */ +#ifndef MIN +#define MIN(a, b) ((b)>(a)?(a):(b)) +#endif + +#ifdef __ARM_ARCH_ISA_THUMB +#define pico_default_asm(...) __asm (".syntax unified\n" __VA_ARGS__) +#define pico_default_asm_volatile(...) __asm volatile (".syntax unified\n" __VA_ARGS__) +#define pico_default_asm_goto(...) __asm goto (".syntax unified\n" __VA_ARGS__) +#else +#define pico_default_asm(...) __asm (__VA_ARGS__) +#define pico_default_asm_volatile(...) __asm volatile (__VA_ARGS__) +#define pico_default_asm_goto(...) __asm goto (__VA_ARGS__) +#endif + +/*! \brief Ensure that the compiler does not move memory access across this method call + * \ingroup pico_platform + * + * For example in the following code: + * + * *some_memory_location = var_a; + * __compiler_memory_barrier(); + * uint32_t var_b = *some_other_memory_location + * + * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise + * might - even above the memory store!) + */ +__force_inline static void __compiler_memory_barrier(void) { + pico_default_asm_volatile ("" : : : "memory"); +} + +/*! \brief Utility macro to assert two types are equivalent. + * \ingroup pico_platform + * + * This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type + * (or that a single parameter is of an expected type) + */ +#define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b)); + +#define WRAPPER_FUNC(x) __wrap_ ## x +#define REAL_FUNC(x) __real_ ## x + +#ifdef __cplusplus +} +#endif + +#else // __ASSEMBLER__ + +#if defined __GNUC__ +// note LLVM defines __GNUC__ +#ifdef __clang__ +#define PICO_ASSEMBLER_IS_CLANG 1 +#else +#define PICO_ASSEMBLER_IS_GNU 1 +#endif +#elif defined __ICCARM__ +#else +#error Unsupported toolchain +#endif + +#define WRAPPER_FUNC_NAME(x) __wrap_##x + +#endif // !__ASSEMBLER__ + +#endif diff --git a/src/rp2_common/pico_platform_panic/BUILD.bazel b/src/rp2_common/pico_platform_panic/BUILD.bazel new file mode 100644 index 000000000..8ad2b997f --- /dev/null +++ b/src/rp2_common/pico_platform_panic/BUILD.bazel @@ -0,0 +1,30 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +# This exists to break a dependency cycle between +# this library and //src/rp2_common/pico_printf. +# Application code should always use :pico_platform_panic instead. +cc_library( + name = "pico_platform_panic_headers", + hdrs = ["include/pico/platform/panic.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + visibility = [ + "//src/rp2040/pico_platform:__pkg__", + "//src/rp2350/pico_platform:__pkg__", + ], + deps = ["//src/rp2_common/pico_clib_interface"], +) + +cc_library( + name = "pico_platform_panic", + srcs = ["panic.c"], + hdrs = ["include/pico/platform/panic.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/rp2_common/pico_printf", + ], + alwayslink = True, +) diff --git a/src/rp2_common/pico_platform_panic/CMakeLists.txt b/src/rp2_common/pico_platform_panic/CMakeLists.txt new file mode 100644 index 000000000..0ebdb17ca --- /dev/null +++ b/src/rp2_common/pico_platform_panic/CMakeLists.txt @@ -0,0 +1,9 @@ +if (NOT TARGET pico_platform_panic) + pico_add_library(pico_platform_panic) + + target_sources(pico_platform_panic INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/panic.c + ) + + target_include_directories(pico_platform_panic_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +endif() \ No newline at end of file diff --git a/src/rp2_common/pico_platform_panic/include/pico/platform/panic.h b/src/rp2_common/pico_platform_panic/include/pico/platform/panic.h new file mode 100644 index 000000000..a358e1700 --- /dev/null +++ b/src/rp2_common/pico_platform_panic/include/pico/platform/panic.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_PLATFORM_PANIC_H +#define _PICO_PLATFORM_PANIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __ASSEMBLER__ + +/*! \brief Panics with the message "Unsupported" + * \ingroup pico_platform + * \see panic + */ +void __attribute__((noreturn)) panic_unsupported(void); + +/*! \brief Displays a panic message and halts execution + * \ingroup pico_platform + * + * An attempt is made to output the message to all registered STDOUT drivers + * after which this method executes a BKPT instruction. + * + * @param fmt format string (printf-like) + * @param ... printf-like arguments + */ +void __attribute__((noreturn)) panic(const char *fmt, ...); + +#ifdef NDEBUG +#define panic_compact(...) panic(__VA_ARGS__) +#else +#define panic_compact(...) panic("") +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_platform_panic/panic.c b/src/rp2_common/pico_platform_panic/panic.c new file mode 100644 index 000000000..7d076da90 --- /dev/null +++ b/src/rp2_common/pico_platform_panic/panic.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include "pico/platform/panic.h" + +#if LIB_PICO_PRINTF_PICO +#include "pico/printf.h" +#else +#define weak_raw_printf printf +#define weak_raw_vprintf vprintf +#endif + +void __attribute__((noreturn)) panic_unsupported(void) { + panic("not supported"); +} + +// PICO_CONFIG: PICO_PANIC_FUNCTION, Name of a function to use in place of the stock panic function or empty string to simply breakpoint on panic, group=pico_runtime +// note the default is not "panic" it is undefined +#ifdef PICO_PANIC_FUNCTION +#define PICO_PANIC_FUNCTION_EMPTY (__CONCAT(PICO_PANIC_FUNCTION, 1) == 1) +#if !PICO_PANIC_FUNCTION_EMPTY +extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__unused const char *fmt, ...); +#endif +// Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler +void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) { + // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION! + pico_default_asm ( +#ifdef __riscv + +#if !PICO_PANIC_FUNCTION_EMPTY + "jal " __XSTRING(PICO_PANIC_FUNCTION) "\n" +#endif + "ebreak\n" + "1: j 1b\n" + +#else + + "push {lr}\n" +#if !PICO_PANIC_FUNCTION_EMPTY + "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n" +#endif + "bkpt #0\n" + "1: b 1b\n" // loop for ever as we are no return + +#endif + : + : + : + ); +} +#else +// todo consider making this try harder to output if we panic early +// right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC") +// more importantly there may be no stdout/UART initialized yet +// todo we may want to think about where we print panic messages to; writing to USB appears to work +// though it doesn't seem like we can expect it to... fine for now +void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) { + puts("\n*** PANIC ***\n"); + if (fmt) { +#if LIB_PICO_PRINTF_NONE + puts(fmt); +#else + va_list args; + va_start(args, fmt); +#if PICO_PRINTF_ALWAYS_INCLUDED + vprintf(fmt, args); +#else + weak_raw_vprintf(fmt, args); +#endif + va_end(args); + puts("\n"); +#endif + } + + _exit(1); +} +#endif diff --git a/src/rp2_common/pico_platform_sections/BUILD.bazel b/src/rp2_common/pico_platform_sections/BUILD.bazel new file mode 100644 index 000000000..1553854f6 --- /dev/null +++ b/src/rp2_common/pico_platform_sections/BUILD.bazel @@ -0,0 +1,10 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_platform_sections", + hdrs = ["include/pico/platform/sections.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), +) diff --git a/src/rp2_common/pico_platform_sections/CMakeLists.txt b/src/rp2_common/pico_platform_sections/CMakeLists.txt new file mode 100644 index 000000000..f0c36bd06 --- /dev/null +++ b/src/rp2_common/pico_platform_sections/CMakeLists.txt @@ -0,0 +1,5 @@ +if (NOT TARGET pico_platform_sections) + pico_add_library(pico_platform_sections) + + target_include_directories(pico_platform_sections_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +endif() diff --git a/src/rp2_common/pico_platform_sections/include/pico/platform/sections.h b/src/rp2_common/pico_platform_sections/include/pico/platform/sections.h new file mode 100644 index 000000000..752e752a9 --- /dev/null +++ b/src/rp2_common/pico_platform_sections/include/pico/platform/sections.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_PLATFORM_SECTION_MACROS_H +#define _PICO_PLATFORM_SECTION_MACROS_H + +#ifndef __ASSEMBLER__ + +/*! \brief Section attribute macro for placement in RAM after the `.data` section + * \ingroup pico_platform + * + * For example a 400 element `uint32_t` array placed after the .data section + * + * uint32_t __after_data("my_group_name") a_big_array[400]; + * + * The section attribute is `.after_data.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#ifndef __after_data +#define __after_data(group) __attribute__((section(".after_data." group))) +#endif + +/*! \brief Section attribute macro for placement not in flash (i.e in RAM) + * \ingroup pico_platform + * + * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`) + * + * static const uint32_t __not_in_flash("my_group_name") an_array[3]; + * + * The section attribute is `.time_critical.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#ifndef __not_in_flash +#define __not_in_flash(group) __attribute__((section(".time_critical." group))) +#endif + +/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X") + * \ingroup pico_platform + * + * Scratch X is commonly used for critical data and functions accessed only by one core (when only + * one core is accessing the RAM bank, there is no opportunity for stalls) + * + * For example a `uint32_t` variable placed in "scratch X" + * + * uint32_t __scratch_x("my_group_name") foo = 23; + * + * The section attribute is `.scratch_x.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#ifndef __scratch_x +#define __scratch_x(group) __attribute__((section(".scratch_x." group))) +#endif + +/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y") + * \ingroup pico_platform + * + * Scratch Y is commonly used for critical data and functions accessed only by one core (when only + * one core is accessing the RAM bank, there is no opportunity for stalls) + * + * For example a `uint32_t` variable placed in "scratch Y" + * + * uint32_t __scratch_y("my_group_name") foo = 23; + * + * The section attribute is `.scratch_y.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#ifndef __scratch_y +#define __scratch_y(group) __attribute__((section(".scratch_y." group))) +#endif + +/*! \brief Section attribute macro for data that is to be left uninitialized + * \ingroup pico_platform + * + * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss + * section) is initialized to zero during runtime initialization + * + * For example a `uint32_t` foo that will retain its value if the program is restarted by reset. + * + * uint32_t __uninitialized_ram(foo); + * + * The section attribute is `.uninitialized_data.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#ifndef __uninitialized_ram +#define __uninitialized_ram(group) __attribute__((section(".uninitialized_data." #group))) group +#endif + +/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary + * \ingroup pico_platform + * + * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!) + * + * uint32_t __in_flash("my_group_name") foo = 23; + * + * The section attribute is `.flashdata.` + * + * \param group a string suffix to use in the section name to distinguish groups that can be linker + * garbage-collected independently + */ +#ifndef __in_flash +#define __in_flash(group) __attribute__((section(".flashdata." group))) +#endif + +/*! \brief Indicates a function should not be stored in flash + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined + * into a flash function by the compiler) + * + * For example a function called my_func taking an int parameter: + * + * void __not_in_flash_func(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + * + * \see __no_inline_not_in_flash_func + */ +#ifndef __not_in_flash_func +#define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name +#endif + +/*! \brief Indicates a function is time/latency critical and should not run from flash + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined + * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical + * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func` + * may in the future be treated more specially to reduce the overhead when calling such function from a flash + * function. + * + * For example a function called my_func taking an int parameter: + * + * void __time_critical(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + * + * \see __not_in_flash_func + */ +#ifndef __time_critical_func +#define __time_critical_func(func_name) __not_in_flash_func(func_name) +#endif + +/*! \brief Indicate a function should not be stored in flash and should not be inlined + * \ingroup pico_platform + * + * Decorates a function name, such that the function will execute from RAM, explicitly marking it as + * noinline to prevent it being inlined into a flash function by the compiler + * + * For example a function called my_func taking an int parameter: + * + * void __no_inline_not_in_flash_func(my_func)(int some_arg) { + * + * The function is placed in the `.time_critical.` linker section + */ +#ifndef __no_inline_not_in_flash_func +#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name) +#endif + +#else + +#ifndef RAM_SECTION_NAME +#define RAM_SECTION_NAME(x) .time_critical.##x +#endif + +#ifndef SECTION_NAME +#define SECTION_NAME(x) .text.##x +#endif + +#endif // !__ASSEMBLER__ + +#endif + diff --git a/src/rp2_common/pico_printf/BUILD.bazel b/src/rp2_common/pico_printf/BUILD.bazel index 95d1b247c..b18f00167 100644 --- a/src/rp2_common/pico_printf/BUILD.bazel +++ b/src/rp2_common/pico_printf/BUILD.bazel @@ -2,13 +2,54 @@ load("//bazel:defs.bzl", "compatible_with_rp2") package(default_visibility = ["//visibility:public"]) -cc_library( +alias( name = "pico_printf", - srcs = [ - "printf.c", + actual = select({ + "//bazel/constraint:pico_printf_pico_enabled": ":pico_printf_pico", + "//bazel/constraint:pico_printf_compiler_enabled": ":pico_printf_compiler", + "//conditions:default": ":pico_printf_none", + }), +) + +cc_library( + name = "pico_printf_pico", + srcs = ["printf.c"], + hdrs = ["include/pico/printf.h"], + defines = ["LIB_PICO_PRINTF_PICO=1"], + includes = ["include"], + linkopts = [ + "-Wl,--wrap=sprintf", + "-Wl,--wrap=snprintf", + "-Wl,--wrap=vsnprintf", ], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/rp2_common:pico_platform_internal", + ], + alwayslink = True, # Ensures the wrapped symbols are linked in. +) + +cc_library( + name = "pico_printf_compiler", hdrs = ["include/pico/printf.h"], includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/rp2_common:pico_platform_internal", + ], +) + +cc_library( + name = "pico_printf_none", + srcs = ["printf_none.S"], + hdrs = ["include/pico/printf.h"], + defines = [ + "LIB_PICO_PRINTF_PICO=0", + "LIB_PICO_PRINTF_NONE=1", + ], + includes = ["include"], linkopts = [ "-Wl,--wrap=sprintf", "-Wl,--wrap=snprintf", @@ -16,11 +57,9 @@ cc_library( ], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", + "//src/common/pico_base_headers", + "//src/rp2_common:pico_platform_internal", "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform", ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) - -# TODO: Support printf_none.S when the configuration option exists. diff --git a/src/rp2_common/pico_printf/CMakeLists.txt b/src/rp2_common/pico_printf/CMakeLists.txt index a5b95ff4f..c77bb08c8 100644 --- a/src/rp2_common/pico_printf/CMakeLists.txt +++ b/src/rp2_common/pico_printf/CMakeLists.txt @@ -5,7 +5,7 @@ if (NOT TARGET pico_printf) # no custom implementation; falls thru to compiler pico_add_library(pico_printf_compiler) - target_include_directories(pico_printf_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_printf_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) # add alias "default" which is just pico. add_library(pico_printf_default INTERFACE) @@ -38,6 +38,10 @@ if (NOT TARGET pico_printf) wrap_printf_functions(pico_printf_pico) wrap_printf_functions(pico_printf_none) + # always hook printf for printf_none with out weak impl, as it is handled by pico_stdio + # but that library may not be included + pico_wrap_function(pico_printf_none printf) + macro(pico_set_printf_implementation TARGET IMPL) get_target_property(target_type ${TARGET} TYPE) if ("EXECUTABLE" STREQUAL "${target_type}") diff --git a/src/rp2_common/pico_stdio/LICENSE b/src/rp2_common/pico_printf/LICENSE similarity index 100% rename from src/rp2_common/pico_stdio/LICENSE rename to src/rp2_common/pico_printf/LICENSE diff --git a/src/rp2_common/pico_printf/printf_none.S b/src/rp2_common/pico_printf/printf_none.S index 212c1c50f..0148f265f 100644 --- a/src/rp2_common/pico_printf/printf_none.S +++ b/src/rp2_common/pico_printf/printf_none.S @@ -12,10 +12,18 @@ pico_default_asm_setup wrapper_func sprintf wrapper_func snprintf wrapper_func vsnprintf +// pico_stdio may itself overwrite printf, so we want to support that (hence weak), but override it +// here to in case pico_stdio is not used +weak_wrapper_func printf regular_func printf_none_assert +#ifndef __riscv push {lr} // keep stack trace sane ldr r0, =str bl panic +#else + la a0, str + call panic +#endif str: .asciz "printf support is disabled" \ No newline at end of file diff --git a/src/rp2_common/pico_rand/BUILD.bazel b/src/rp2_common/pico_rand/BUILD.bazel index c24e6a951..19473e1e8 100644 --- a/src/rp2_common/pico_rand/BUILD.bazel +++ b/src/rp2_common/pico_rand/BUILD.bazel @@ -9,11 +9,11 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", "//src/common/pico_time", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_sync", - "//src/rp2_common/pico_platform:hardware_structs", "//src/rp2_common/pico_unique_id", ], ) diff --git a/src/rp2_common/pico_rand/CMakeLists.txt b/src/rp2_common/pico_rand/CMakeLists.txt index 0e72bb5ab..9af7d470d 100644 --- a/src/rp2_common/pico_rand/CMakeLists.txt +++ b/src/rp2_common/pico_rand/CMakeLists.txt @@ -1,13 +1,14 @@ pico_add_library(pico_rand) target_sources(pico_rand INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/rand.c + ${CMAKE_CURRENT_LIST_DIR}/rand.c ) -target_include_directories(pico_rand_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_rand_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_rand INTERFACE pico_unique_id hardware_clocks hardware_timer - hardware_sync) + hardware_sync +) diff --git a/src/rp2_common/pico_rand/include/pico/rand.h b/src/rp2_common/pico_rand/include/pico/rand.h index 02a6e4aaf..f2953162e 100644 --- a/src/rp2_common/pico_rand/include/pico/rand.h +++ b/src/rp2_common/pico_rand/include/pico/rand.h @@ -63,44 +63,74 @@ extern "C" { // ENTROPY SOURCES // --------------- -// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_ROSC, Enable/disable use of ROSC as an entropy source, type=bool, default=1, group=pico_rand +// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_ROSC, Enable/disable use of ROSC as an entropy source, type=bool, default=1 if no hardware TRNG, group=pico_rand #ifndef PICO_RAND_ENTROPY_SRC_ROSC +#if !HAS_RP2350_TRNG #define PICO_RAND_ENTROPY_SRC_ROSC 1 #endif +#endif + +// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_TRNG, Enable/disable use of hardware TRNG as an entropy source, type=bool, default=1 if no hardware TRNG, group=pico_rand +#ifndef PICO_RAND_ENTROPY_SRC_TRNG +#if HAS_RP2350_TRNG +#define PICO_RAND_ENTROPY_SRC_TRNG 1 +#endif +#endif // PICO_CONFIG: PICO_RAND_ENTROPY_SRC_TIME, Enable/disable use of hardware timestamp as an entropy source, type=bool, default=1, group=pico_rand #ifndef PICO_RAND_ENTROPY_SRC_TIME #define PICO_RAND_ENTROPY_SRC_TIME 1 #endif -// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER, Enable/disable use of a bus performance counter as an entropy source, type=bool, default=1, group=pico_rand +// PICO_CONFIG: PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER, Enable/disable use of a bus performance counter as an entropy source, type=bool, default=1 if no hardware TRNG, group=pico_rand #ifndef PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER +#if !HAS_RP2350_TRNG #define PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER 1 #endif +#endif // -------------------- // SEED ENTROPY SOURCES // -------------------- -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_ROSC, Enable/disable use of ROSC as an entropy source for the random seed, type=bool, default=1, group=pico_rand +// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_ROSC, Enable/disable use of ROSC as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_ROSC, group=pico_rand #ifndef PICO_RAND_SEED_ENTROPY_SRC_ROSC #define PICO_RAND_SEED_ENTROPY_SRC_ROSC PICO_RAND_ENTROPY_SRC_ROSC #endif -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_TIME, Enable/disable use of hardware timestamp as an entropy source for the random seed, type=bool, default=1, group=pico_rand +// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_TRNG, Enable/disable use of hardware TRNG as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_TRNG, group=pico_rand +#if !defined(PICO_RAND_SEED_ENTROPY_SRC_TRNG) && HAS_RP2350_TRNG +#define PICO_RAND_SEED_ENTROPY_SRC_TRNG PICO_RAND_ENTROPY_SRC_TRNG +#endif + +// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_TIME, Enable/disable use of hardware timestamp as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_TIME, group=pico_rand #ifndef PICO_RAND_SEED_ENTROPY_SRC_TIME #define PICO_RAND_SEED_ENTROPY_SRC_TIME PICO_RAND_ENTROPY_SRC_TIME #endif -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID, Enable/disable use of board id as part of the random seed, type=bool, default=1, group=pico_rand +// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_BUF_PERF_COUNTER, Enable/disable use of a bus performance counter as an entropy source for the random seed, type=bool, default=PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER, group=pico_rand +#ifndef PICO_RAND_SEED_ENTROPY_SRC_BUF_PERF_COUNTER +#define PICO_RAND_SEED_ENTROPY_SRC_BUF_PERF_COUNTER PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER +#endif + +// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM, Enable/disable use of the per boot random number as an entropy source for the random seed, type=bool, default=0 on RP2040 which has none, group=pico_rand +#ifndef PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM +#if !PICO_RP2040 +#define PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM 1 +#endif +#endif + +// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID, Enable/disable use of board id as part of the random seed, type=bool, default=not PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM, group=pico_rand #ifndef PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID -#define PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID 1 +#define PICO_RAND_SEED_ENTROPY_SRC_BOARD_ID (!PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM) #endif -// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH, Enable/disable use of a RAM hash as an entropy source for the random seed, type=bool, default=1, group=pico_rand +// PICO_CONFIG: PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH, Enable/disable use of a RAM hash as an entropy source for the random seed, type=bool, default=1 if no hardware TRNG, group=pico_rand #ifndef PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH +#if !HAS_RP2350_TRNG #define PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH 1 #endif +#endif // --------------------------------- // PICO_RAND_ENTROPY_SRC_ROSC CONFIG @@ -121,9 +151,11 @@ extern "C" { // PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER CONFIG // --------------------------------------------- -// PICO_CONFIG: PICO_RAND_BUS_PERF_COUNTER_INDEX, Bus performance counter index to use for sourcing entropy, min=0, max=3, group=pico_rand +// PICO_CONFIG: PICO_RAND_BUS_PERF_COUNTER_INDEX, Bus performance counter index to use for sourcing entropy, min=0, max=3, default=Undefined meaning pick one that is not counting any valid event already, group=pico_rand // this is deliberately undefined by default, meaning the code will pick that appears unused -//#define PICO_RAND_BUS_PERF_COUNTER_INDEX 0 +#if 0 // make tooling checks happy +#define PICO_RAND_BUS_PERF_COUNTER_INDEX 0 +#endif // PICO_CONFIG: PICO_RAND_BUS_PERF_COUNTER_EVENT, Bus performance counter event to use for sourcing entropy, default=arbiter_sram5_perf_event_access, group=pico_rand #ifndef PICO_RAND_BUS_PERF_COUNTER_EVENT @@ -134,11 +166,11 @@ extern "C" { // PICO_RAND_SEED_ENTROPY_SRC_RAM_HASH CONFIG // ------------------------------------------ -// PICO_CONFIG: PICO_RAND_RAM_HASH_END, end of address in RAM (non-inclusive) to hash during pico_rand seed initialization, default=SRAM_END, group=pico_rand +// PICO_CONFIG: PICO_RAND_RAM_HASH_END, End of address in RAM (non-inclusive) to hash during pico_rand seed initialization, default=SRAM_END, group=pico_rand #ifndef PICO_RAND_RAM_HASH_END #define PICO_RAND_RAM_HASH_END SRAM_END #endif -// PICO_CONFIG: PICO_RAND_RAM_HASH_START, start of address in RAM (inclusive) to hash during pico_rand seed initialization, default=PICO_RAND_RAM_HASH_END - 1024, group=pico_rand +// PICO_CONFIG: PICO_RAND_RAM_HASH_START, Start of address in RAM (inclusive) to hash during pico_rand seed initialization, default=PICO_RAND_RAM_HASH_END - 1024, group=pico_rand #ifndef PICO_RAND_RAM_HASH_START #define PICO_RAND_RAM_HASH_START (PICO_RAND_RAM_HASH_END - 1024u) #endif diff --git a/src/rp2_common/pico_rand/rand.c b/src/rp2_common/pico_rand/rand.c index e1cde58e8..5d07fef42 100644 --- a/src/rp2_common/pico_rand/rand.c +++ b/src/rp2_common/pico_rand/rand.c @@ -29,7 +29,7 @@ #include "pico/time.h" #include "hardware/clocks.h" #include "hardware/structs/rosc.h" -#include "hardware/structs/bus_ctrl.h" +#include "hardware/structs/busctrl.h" #include "hardware/sync.h" static bool rng_initialised = false; @@ -118,6 +118,60 @@ static uint64_t sdbm_hash64_sram(uint64_t hash) { } #endif +#if PICO_RAND_SEED_ENTROPY_SRC_TRNG | PICO_RAND_ENTROPY_SRC_TRNG +#if !HAS_RP2350_TRNG +#error PICO_RAND_SEED_ENTROPY_SRC_TRNG and PICO_RAND_ENTROPY_SRC_TRNG are only valid on RP2350 +#endif +#include "hardware/structs/trng.h" + +uint32_t trng_sample_words[count_of(trng_hw->ehr_data)]; +static_assert(count_of(trng_hw->ehr_data) >= 2 && count_of(trng_hw->ehr_data) < 255, ""); +uint8_t trng_sample_word_count; + +static uint64_t capture_additional_trng_samples(void) { + spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_RAND); + uint32_t save = spin_lock_blocking(lock); + if (trng_sample_word_count < 2) { + // Sample one ROSC bit into EHR every cycle, subject to CPU keeping up. + // More temporal resolution to measure ROSC phase noise is better, if we + // use a high quality hash function instead of naive VN decorrelation. + // (Also more metastability events, which are a secondary noise source) + // + // This is out of the loop because writing to this register seems to + // restart the sampling, slowing things down. We don't care if this write + // is skipped as that would just make sampling take longer. + trng_hw->sample_cnt1 = 0; + + // TRNG setup is inside loop in case it is skipped. Disable checks and + // bypass decorrelators, to stream raw TRNG ROSC samples: + trng_hw->trng_debug_control = -1u; + // Start ROSC if it is not already started + trng_hw->rnd_source_enable = -1u; + // Clear all interrupts (including EHR_VLD) -- we will check this + // later, after seeding RCP. + trng_hw->rng_icr = -1u; + + // Wait for 192 ROSC samples to fill EHR, this should take constant time: + while (trng_hw->trng_busy); + + for (uint i = 0; i < count_of(trng_sample_words); i++) { + trng_sample_words[i] = trng_hw->ehr_data[i]; + } + trng_sample_word_count = count_of(trng_sample_words); + + // TRNG is now sampling again, having started after we read the last + // EHR word. Grab some random bits and use them to modulate + // the chain length, to reduce chance of injection locking: + trng_hw->trng_config = rng_state.r[0]; + } + trng_sample_word_count -= 2; + uint64_t rc = trng_sample_words[trng_sample_word_count] | + (((uint64_t)trng_sample_words[trng_sample_word_count + 1]) << 32); + spin_unlock(lock, save); + return rc; +} + +#endif #if PICO_RAND_SEED_ENTROPY_SRC_ROSC | PICO_RAND_ENTROPY_SRC_ROSC /* gather an additional n bits of entropy, and shift them into the 64 bit entropy counter */ static uint64_t capture_additional_rosc_samples(uint n) { @@ -172,6 +226,10 @@ static uint64_t capture_additional_rosc_samples(uint n) { } #endif +#if PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM +#include "pico/bootrom.h" +#endif + static void initialise_rand(void) { rng_128_t local_rng_state = local_rng_state; uint which = 0; @@ -211,18 +269,33 @@ static void initialise_rand(void) { which ^= 1; #endif +#if PICO_RAND_SEED_ENTROPY_SRC_BOOT_RANDOM + // Mix in boot random. + union { + uint64_t u64[2]; + uint32_t u32[4]; + } br; + rom_get_boot_random(br.u32); + local_rng_state.r[which] ^= splitmix64(br.u64[0]); + local_rng_state.r[which ^ 1] ^= splitmix64(br.u64[1]); +#endif + #if PICO_RAND_SEED_ENTROPY_SRC_TIME // Mix in hashed time. This is [possibly] predictable boot-to-boot // but will vary application-to-application. local_rng_state.r[which] ^= splitmix64(time_us_64()); which ^= 1; #endif +#if PICO_RAND_SEED_ENTROPY_SRC_TRNG + local_rng_state.r[which] ^= splitmix64(capture_additional_trng_samples()); + which ^= 1; +#endif spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_RAND); uint32_t save = spin_lock_blocking(lock); if (!rng_initialised) { -#if PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER -#if !PICO_RAND_BUSCTRL_COUNTER_INDEX +#if PICO_RAND_SEED_ENTROPY_SRC_BUS_PERF_COUNTER +#if !PICO_RAND_BUS_PERF_COUNTER_INDEX int idx = -1; for(uint i = 0; i < count_of(bus_ctrl_hw->counter); i++) { if (bus_ctrl_hw->counter[i].sel == BUSCTRL_PERFSEL0_RESET) { @@ -233,7 +306,7 @@ static void initialise_rand(void) { hard_assert(idx != -1); bus_counter_idx = (uint8_t)idx; #else - bus_counter_idx = (uint8_t)PICO_RAND_BUSCTRL_COUNTER_INDEX; + bus_counter_idx = (uint8_t)PICO_RAND_BUS_PERF_COUNTER_INDEX; #endif bus_ctrl_hw->counter[bus_counter_idx].sel = PICO_RAND_BUS_PERF_COUNTER_EVENT; #endif @@ -266,11 +339,16 @@ uint64_t get_rand_64(void) { local_rng_state.r[which] ^= splitmix64(capture_additional_rosc_samples(PICO_RAND_ROSC_BIT_SAMPLE_COUNT)); which ^= 1; #endif +#if PICO_RAND_ENTROPY_SRC_TRNG + uint64_t foo = capture_additional_trng_samples(); + local_rng_state.r[which] ^= splitmix64(foo); + which ^= 1; +#endif #if PICO_RAND_ENTROPY_SRC_BUS_PERF_COUNTER - uint32_t bus_counter_value = bus_ctrl_hw->counter[bus_counter_idx].value; + uint32_t bus_counter_value = busctrl_hw->counter[bus_counter_idx].value; // counter is saturating, so clear it if it has reached saturation if (bus_counter_value == BUSCTRL_PERFCTR0_BITS) { - bus_ctrl_hw->counter[bus_counter_idx].value = 0; + busctrl_hw->counter[bus_counter_idx].value = 0; } local_rng_state.r[which] ^= splitmix64(bus_counter_value); which ^= 1; diff --git a/src/rp2_common/pico_runtime/BUILD.bazel b/src/rp2_common/pico_runtime/BUILD.bazel index 32e4473d5..4cffb2c06 100644 --- a/src/rp2_common/pico_runtime/BUILD.bazel +++ b/src/rp2_common/pico_runtime/BUILD.bazel @@ -2,22 +2,36 @@ load("//bazel:defs.bzl", "compatible_with_rp2") package(default_visibility = ["//visibility:public"]) +# This library creates a bunch of circular dependencies, so just rely on +# the implementation getting pulled in as a link dep (i.e. invert the usual +# interface pattern). cc_library( name = "pico_runtime", + hdrs = ["include/pico/runtime.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + ], +) + +cc_library( + name = "pico_runtime_link", srcs = ["runtime.c"], hdrs = ["include/pico/runtime.h"], includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base:pico_base_interface", + "//src/common/pico_base_headers", "//src/common/pico_sync", "//src/common/pico_time", + "//src/rp2_common:hardware_regs", + "//src/rp2_common:hardware_structs", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_resets", "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform:hardware_regs", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/rp2_common/pico_clib_interface:pico_clib_interface_link", "//src/rp2_common/pico_printf", ], alwayslink = True, diff --git a/src/rp2_common/pico_runtime/CMakeLists.txt b/src/rp2_common/pico_runtime/CMakeLists.txt index 9879ba1dc..3665cd805 100644 --- a/src/rp2_common/pico_runtime/CMakeLists.txt +++ b/src/rp2_common/pico_runtime/CMakeLists.txt @@ -4,41 +4,46 @@ target_sources(pico_runtime INTERFACE ${CMAKE_CURRENT_LIST_DIR}/runtime.c ) -target_include_directories(pico_runtime_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_runtime_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_runtime INTERFACE - hardware_uart - hardware_clocks - hardware_irq - pico_printf - pico_sync - ) + pico_base + pico_runtime_init +) -if (TARGET pico_bit_ops) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_bit_ops) -endif() -if (TARGET pico_divider) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_divider) -endif() -if (TARGET pico_double) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_double) -endif() -if (TARGET pico_int64_ops) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_int64_ops) -endif() -if (TARGET pico_float) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_float) -endif() -if (TARGET pico_malloc) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_malloc) +if (TARGET hardware_gpio_headers) + target_link_libraries(pico_runtime INTERFACE hardware_gpio_headers) # to determine if we should init GPIO copro endif() -if (TARGET pico_mem_ops) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_mem_ops) -endif() -if (TARGET pico_standard_link) - pico_mirrored_target_link_libraries(pico_runtime INTERFACE pico_standard_link) +if (TARGET hardware_riscv_headers) + target_link_libraries(pico_runtime INTERFACE hardware_riscv_headers) endif() +set(PICO_RUNTIME_LIBRARIES + hardware_uart + pico_bit_ops + pico_divider + pico_double + pico_int64_ops + pico_float + pico_malloc + pico_mem_ops + pico_atomic + pico_cxx_options + pico_standard_binary_info + pico_standard_link + pico_sync + pico_printf + pico_crt0 + pico_clib_interface + pico_stdio +) + +foreach(LIB IN LISTS PICO_RUNTIME_LIBRARIES) + if (TARGET ${LIB}) + pico_mirrored_target_link_libraries(pico_runtime INTERFACE ${LIB}) + endif() +endforeach() + # todo is this correct/needed? if (PICO_C_COMPILER_IS_GNU) target_link_options(pico_runtime INTERFACE "--specs=nosys.specs") @@ -46,3 +51,70 @@ elseif (PICO_C_COMPILER_IS_CLANG) # target_link_options(pico_runtime INTERFACE "-nostdlib") endif() +# pico_minimize_runtime((INCLUDE ...) (EXCLUDE ...)) +# +# INCLUDE/EXCLUDE can contain any of the following (all defaulting to not included) +# +# DEFAULT_ALARM_POOL - default alarm pool setup +# PRINTF - full printf support +# PRINTF_MINIMAL - printf support without the following +# PRINTF_FLOAT - to control float support if printf is enabled +# PRINTF_EXPONENTIAL +# PRINTF_LONG_LONG +# PRINTF_PTRDIFF_T +# FLOAT - support for single-precision floating point +# DOUBLE - support for double-precision floating point +# FPGA_CHECK - checks for FPGA which allows Raspberry Pi to run your binary on FPGA +function(pico_minimize_runtime TARGET) + cmake_parse_arguments(RUNTIME "" "" + "INCLUDE;EXCLUDE" ${ARGN} ) + foreach (INCL_EXCL IN ITEMS INCLUDE EXCLUDE) + if (INCL_EXCL STREQUAL "INCLUDE") + set(VAL 1) + else() + set(VAL 0) + endif() + foreach(VAR IN LISTS RUNTIME_${INCL_EXCL}) + set(RUNTIME_INCLUDE_${VAR} ${VAL}) + endforeach () + endforeach () + if (NOT RUNTIME_INCLUDE_DEFAULT_ALARM_POOL) + target_compile_definitions(${TARGET} PRIVATE PICO_TIME_DEFAULT_ALARM_POOL_DISABLED=1) + endif() + if (NOT RUNTIME_INCLUDE_FLOAT) + pico_set_float_implementation(${TARGET} none) + endif() + if (NOT RUNTIME_INCLUDE_DOUBLE) + pico_set_double_implementation(${TARGET} none) + endif() + if (NOT RUNTIME_INCLUDE_AUTO_INIT_MUTEX) + target_compile_definitions(${TARGET} PRIVATE PICO_RUNTIME_SKIP_INIT_MUTEX=1) + endif() + + if (RUNTIME_INCLUDE_PRINTF) + if (NOT RUNTIME_INCLUDE_PRINTF_MINIMAL) + set( RUNTIME_INCLUDE_PRINTF_FLOAT 1) + set( RUNTIME_INCLUDE_PRINTF_EXPONENTIAL 1) + set( RUNTIME_INCLUDE_PRINTF_LONG_LONG 1) + set( RUNTIME_INCLUDE_PRINTF_PTRDIFF_T 1) + endif() + if (NOT RUNTIME_INCLUDE_PRINTF_FLOAT) + target_compile_definitions(${TARGET} PRIVATE PICO_PRINTF_SUPPORT_FLOAT=0) + endif() + if (NOT RUNTIME_INCLUDE_PRINTF_EXPONENTIAL) + target_compile_definitions(${TARGET} PRIVATE PICO_PRINTF_SUPPORT_EXPONENTIAL=0) + endif() + if (NOT RUNTIME_INCLUDE_PRINTF_LONG_LONG) + target_compile_definitions(${TARGET} PRIVATE PICO_PRINTF_SUPPORT_LONG_LONG=0) + endif() + if (NOT RUNTIME_INCLUDE_PRINTF_PTRDIFF_T) + target_compile_definitions(${TARGET} PRIVATE PICO_PRINTF_SUPPORT_PTRDIFF_T=0) + endif() + else() + pico_set_printf_implementation(${TARGET} none) + endif() + + if (NOT RUNTIME_INCLUDE_FPGA_CHECK) + target_compile_definitions(${TARGET} PRIVATE PICO_NO_FPGA_CHECK=1) + endif() +endfunction() \ No newline at end of file diff --git a/src/rp2_common/pico_runtime/include/pico/runtime.h b/src/rp2_common/pico_runtime/include/pico/runtime.h index 3706399e8..35d871d92 100644 --- a/src/rp2_common/pico_runtime/include/pico/runtime.h +++ b/src/rp2_common/pico_runtime/include/pico/runtime.h @@ -7,17 +7,61 @@ #ifndef _PICO_RUNTIME_H #define _PICO_RUNTIME_H +#include "pico.h" + +/** \file runtime.h +* \defgroup pico_runtime pico_runtime +* \brief Basic runtime support for running pre-main initializers provided by other libraries +* +* This library aggregates the following other libraries (if available): +* +* * \ref hardware_uart +* * \ref pico_bit_ops +* * \ref pico_divider +* * \ref pico_double +* * \ref pico_int64_ops +* * \ref pico_float +* * \ref pico_malloc +* * \ref pico_mem_ops +* * \ref pico_atomic +* * \ref pico_cxx_options +* * \ref pico_standard_binary_info +* * \ref pico_standard_link +* * \ref pico_sync +* * \ref pico_printf +* * \ref pico_crt0 +* * \ref pico_clib_interface +* * \ref pico_stdio +*/ + #ifdef __cplusplus extern "C" { #endif -/** \file runtime.h -* \defgroup pico_runtime pico_runtime -* \brief Aggregate runtime support including @ref pico_bit_ops, @ref pico_divider, @ref pico_double, @ref pico_int64_ops, @ref pico_float, @ref pico_malloc, @ref pico_mem_ops and @ref pico_standard_link -*/ +#ifndef __ASSEMBLER__ +/*! \brief Run all the initializations that are usually called by crt0.S before entering main + * \ingroup pico_runtime + * + * This method is useful to set up the runtime after performing a watchdog or powman reboot + * via scratch vector. + */ +void runtime_init(void); +void runtime_run_initializers(void); +void runtime_run_per_core_initializers(void); -void runtime_install_stack_guard(void *stack_bottom); +#ifndef PICO_RUNTIME_INIT_FUNC +#define PICO_RUNTIME_INIT_FUNC(func, priority_string) uintptr_t __used __attribute__((section(".preinit_array." priority_string))) __pre_init_ ## func = (uintptr_t)(void (*)(void)) (func) +#endif +#else +#ifndef PICO_RUNTIME_INIT_FUNC +#define PICO_RUNTIME_INIT_FUNC(func, priority_string) __pre_init func, priority_string +#endif +#endif +#define PICO_RUNTIME_INIT_FUNC_HW(func, priority_string) PICO_RUNTIME_INIT_FUNC(func, priority_string) +#define PICO_RUNTIME_INIT_FUNC_RUNTIME(func, priority_string) PICO_RUNTIME_INIT_FUNC(func, priority_string) +// priority strings are of the form 00000->99999; we want the per core stuff all at the end, so prefix with ZZZZZ which is clearly after 99999 +#define PICO_RUNTIME_INIT_FUNC_PER_CORE(func, priority_string) PICO_RUNTIME_INIT_FUNC(func, "ZZZZZ." priority_string) #ifdef __cplusplus } diff --git a/src/rp2_common/pico_runtime/runtime.c b/src/rp2_common/pico_runtime/runtime.c index 144ace1bd..42452e5bb 100644 --- a/src/rp2_common/pico_runtime/runtime.c +++ b/src/rp2_common/pico_runtime/runtime.c @@ -4,328 +4,47 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include -#include -#include -#include -#include -#include "pico.h" +#include "pico/runtime.h" +#include "pico/runtime_init.h" -#include "hardware/regs/m0plus.h" -#include "hardware/regs/resets.h" -#include "hardware/structs/mpu.h" -#include "hardware/structs/scb.h" -#include "hardware/structs/padsbank0.h" -#include "hardware/clocks.h" -#include "hardware/irq.h" -#include "hardware/resets.h" - -#include "pico/mutex.h" -#include "pico/time.h" - -#if LIB_PICO_PRINTF_PICO -#include "pico/printf.h" -#else -#define weak_raw_printf printf -#define weak_raw_vprintf vprintf -#endif - -#if PICO_ENTER_USB_BOOT_ON_EXIT -#include "pico/bootrom.h" -#endif - -extern char __StackLimit; /* Set by linker. */ - -uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[48]; - -// this is called for each thread since they have their own MPU -void runtime_install_stack_guard(void *stack_bottom) { - // this is called b4 runtime_init is complete, so beware printf or assert - - // make sure no one is using the MPU yet - if (mpu_hw->ctrl) { - // Note that it would be tempting to change this to a panic, but it happens so early, printing is not a good idea - __breakpoint(); - } - - uintptr_t addr = (uintptr_t) stack_bottom; - // the minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will - // just shorten the valid stack range a tad - addr = (addr + 31u) & ~31u; - - // mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want - uint32_t subregion_select = 0xffu ^ (1u << ((addr >> 5u) & 7u)); - mpu_hw->ctrl = 5; // enable mpu with background default map - mpu_hw->rbar = (addr & (uint)~0xff) | M0PLUS_MPU_RBAR_VALID_BITS | 0; - mpu_hw->rasr = 1 // enable region - | (0x7 << 1) // size 2^(7 + 1) = 256 - | (subregion_select << 8) - | 0x10000000; // XN = disable instruction fetch; no other bits means no permissions +void __weak hard_assertion_failure(void) { + panic("Hard assert"); } -void runtime_init(void) { - // Reset all peripherals to put system into a known state, - // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash - // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot - // - and USB, syscfg, as this disturbs USB-to-SWD on core 1 - reset_block(~( - RESETS_RESET_IO_QSPI_BITS | - RESETS_RESET_PADS_QSPI_BITS | - RESETS_RESET_PLL_USB_BITS | - RESETS_RESET_USBCTRL_BITS | - RESETS_RESET_SYSCFG_BITS | - RESETS_RESET_PLL_SYS_BITS - )); - - // Remove reset from peripherals which are clocked only by clk_sys and - // clk_ref. Other peripherals stay in reset until we've configured clocks. - unreset_block_wait(RESETS_RESET_BITS & ~( - RESETS_RESET_ADC_BITS | - RESETS_RESET_RTC_BITS | - RESETS_RESET_SPI0_BITS | - RESETS_RESET_SPI1_BITS | - RESETS_RESET_UART0_BITS | - RESETS_RESET_UART1_BITS | - RESETS_RESET_USBCTRL_BITS - )); - - // pre-init runs really early since we need it even for memcpy and divide! - // (basically anything in aeabi that uses bootrom) +static void runtime_run_initializers_from(uintptr_t *from) { // Start and end points of the constructor list, // defined by the linker script. - extern void (*__preinit_array_start)(void); - extern void (*__preinit_array_end)(void); + extern uintptr_t __preinit_array_end; - // Call each function in the list. + // Call each function in the list, based on the mask // We have to take the address of the symbols, as __preinit_array_start *is* - // the first function pointer, not the address of it. - for (void (**p)(void) = &__preinit_array_start; p < &__preinit_array_end; ++p) { - (*p)(); - } - - // After calling preinit we have enough runtime to do the exciting maths - // in clocks_init - clocks_init(); - - // Peripheral clocks should now all be running - unreset_block_wait(RESETS_RESET_BITS); - -#if !PICO_IE_26_29_UNCHANGED_ON_RESET - // after resetting BANK0 we should disable IE on 26-29 - padsbank0_hw_t *padsbank0_hw_clear = (padsbank0_hw_t *)hw_clear_alias_untyped(padsbank0_hw); - padsbank0_hw_clear->io[26] = padsbank0_hw_clear->io[27] = - padsbank0_hw_clear->io[28] = padsbank0_hw_clear->io[29] = PADS_BANK0_GPIO0_IE_BITS; -#endif - - // this is an array of either mutex_t or recursive_mutex_t (i.e. not necessarily the same size) - // however each starts with a lock_core_t, and the spin_lock is initialized to address 1 for a recursive - // spinlock and 0 for a regular one. - - static_assert(!(sizeof(mutex_t)&3), ""); - static_assert(!(sizeof(recursive_mutex_t)&3), ""); - static_assert(!offsetof(mutex_t, core), ""); - static_assert(!offsetof(recursive_mutex_t, core), ""); - extern lock_core_t __mutex_array_start; - extern lock_core_t __mutex_array_end; - - for (lock_core_t *l = &__mutex_array_start; l < &__mutex_array_end; ) { - if (l->spin_lock) { - assert(1 == (uintptr_t)l->spin_lock); // indicator for a recursive mutex - recursive_mutex_t *rm = (recursive_mutex_t *)l; - recursive_mutex_init(rm); - l = &rm[1].core; // next - } else { - mutex_t *m = (mutex_t *)l; - mutex_init(m); - l = &m[1].core; // next - } - } - -#if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH) - __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, sizeof(ram_vector_table)); - scb_hw->vtor = (uintptr_t) ram_vector_table; -#endif - -#ifndef NDEBUG - if (__get_current_exception()) { - // crap; started in exception handler - __breakpoint(); - } -#endif - -#if PICO_USE_STACK_GUARDS - // install core0 stack guard - extern char __StackBottom; - runtime_install_stack_guard(&__StackBottom); -#endif - - spin_locks_reset(); - irq_init_priorities(); - alarm_pool_init_default(); - - // Start and end points of the constructor list, - // defined by the linker script. - extern void (*__init_array_start)(void); - extern void (*__init_array_end)(void); - - // Call each function in the list. - // We have to take the address of the symbols, as __init_array_start *is* - // the first function pointer, not the address of it. - for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) { - (*p)(); - } - -} - -void __attribute__((noreturn)) __attribute__((weak)) _exit(__unused int status) { -#if PICO_ENTER_USB_BOOT_ON_EXIT - reset_usb_boot(0,0); -#else - while (1) { - __breakpoint(); - } -#endif -} - -__attribute__((weak)) void *_sbrk(int incr) { - extern char end; /* Set by linker. */ - static char *heap_end; - char *prev_heap_end; - - if (heap_end == 0) - heap_end = &end; - - prev_heap_end = heap_end; - char *next_heap_end = heap_end + incr; - - if (__builtin_expect(next_heap_end > (&__StackLimit), false)) { -#if PICO_USE_OPTIMISTIC_SBRK - if (heap_end == &__StackLimit) { -// errno = ENOMEM; - return (char *) -1; - } - next_heap_end = &__StackLimit; -#else - return (char *) -1; -#endif - } - - heap_end = next_heap_end; - return (void *) prev_heap_end; -} - -static int64_t epoch_time_us_since_boot; - -__attribute__((weak)) int _gettimeofday (struct timeval *__restrict tv, __unused void *__restrict tz) { - if (tv) { - int64_t us_since_epoch = ((int64_t)to_us_since_boot(get_absolute_time())) - epoch_time_us_since_boot; - tv->tv_sec = (time_t)(us_since_epoch / 1000000); - tv->tv_usec = (suseconds_t)(us_since_epoch % 1000000); - } - return 0; -} - -__attribute((weak)) int settimeofday(__unused const struct timeval *tv, __unused const struct timezone *tz) { - if (tv) { - int64_t us_since_epoch = tv->tv_sec * 1000000 + tv->tv_usec; - epoch_time_us_since_boot = (int64_t)to_us_since_boot(get_absolute_time()) - us_since_epoch; - } - return 0; -} - -__attribute((weak)) int _times(struct tms *tms) { -#if CLOCKS_PER_SEC >= 1000000 - tms->tms_utime = (clock_t)(to_us_since_boot(get_absolute_time()) * (CLOCKS_PER_SEC / 1000000)); -#else - tms->tms_utime = (clock_t)(to_us_since_boot(get_absolute_time()) / (1000000 / CLOCKS_PER_SEC)); -#endif - tms->tms_stime = 0; - tms->tms_cutime = 0; - tms->tms_cstime = 0; - return 0; -} - -__attribute((weak)) pid_t _getpid(void) { - return 0; -} - -__attribute((weak)) int _kill(__unused pid_t pid, __unused int sig) { - return -1; -} - -// exit is not useful... no desire to pull in __call_exitprocs -void exit(int status) { - _exit(status); -} - -// incorrect warning from GCC 6 -GCC_Pragma("GCC diagnostic push") -GCC_Pragma("GCC diagnostic ignored \"-Wsuggest-attribute=format\"") -void __assert_func(const char *file, int line, const char *func, const char *failedexpr) { - weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n", - failedexpr, file, line, func ? ", function: " : "", - func ? func : ""); - - _exit(1); -} -GCC_Pragma("GCC diagnostic pop") - -void __attribute__((noreturn)) panic_unsupported(void) { - panic("not supported"); -} - -// PICO_CONFIG: PICO_PANIC_FUNCTION, Name of a function to use in place of the stock panic function or empty string to simply breakpoint on panic, group=pico_runtime -// note the default is not "panic" it is undefined -#ifdef PICO_PANIC_FUNCTION -#define PICO_PANIC_FUNCTION_EMPTY (__CONCAT(PICO_PANIC_FUNCTION, 1) == 1) -#if !PICO_PANIC_FUNCTION_EMPTY -extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__unused const char *fmt, ...); -#endif -// Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler -void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) { - // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION! - pico_default_asm ( - "push {lr}\n" -#if !PICO_PANIC_FUNCTION_EMPTY - "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n" -#endif - "bkpt #0\n" - "1: b 1b\n" // loop for ever as we are no return - : - : - : - ); -} -#else -// todo consider making this try harder to output if we panic early -// right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC") -// more importantly there may be no stdout/UART initialized yet -// todo we may want to think about where we print panic messages to; writing to USB appears to work -// though it doesn't seem like we can expect it to... fine for now -void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) { - puts("\n*** PANIC ***\n"); - if (fmt) { -#if LIB_PICO_PRINTF_NONE - puts(fmt); -#else - va_list args; - va_start(args, fmt); -#if PICO_PRINTF_ALWAYS_INCLUDED - vprintf(fmt, args); -#else - weak_raw_vprintf(fmt, args); -#endif - va_end(args); - puts("\n"); -#endif - } - - _exit(1); -} -#endif - -void hard_assertion_failure(void) { - panic("Hard assert"); -} + // the first function value, not the address of it. + for (uintptr_t *p = from; p < &__preinit_array_end; p++) { + uintptr_t val = *p; + ((void (*)(void))val)(); + } +} + +void runtime_run_initializers(void) { + extern uintptr_t __preinit_array_start; + runtime_run_initializers_from(&__preinit_array_start); +} + +// We keep the per-core initializers in the standard __preinit_array so a standard C library +// initialization will force the core 0 initialization, however we also want to be able to find +// them after the fact so that we can run them on core 1. Per core initializers have sections +// __preinit_array.ZZZZZ.nnnnn i.e. the ZZZZZ sorts below all the standard __preinit_array.nnnnn +// values, and then we sort within the ZZZZZ. +// +// We create a dummy initializer in __preinit_array.YYYYY (between the standard initializers +// and the per core initializers), so we find the first per core initializer. Whilst we could +// have done this via an entry in the linker script, we want to preserve backwards compatibility +// with RP2040 custom linker scripts. +static void first_per_core_initializer(void) {} +PICO_RUNTIME_INIT_FUNC(first_per_core_initializer, "YYYYY"); + +void runtime_run_per_core_initializers(void) { + runtime_run_initializers_from(&__pre_init_first_per_core_initializer); +} \ No newline at end of file diff --git a/src/rp2_common/pico_runtime_init/BUILD.bazel b/src/rp2_common/pico_runtime_init/BUILD.bazel new file mode 100644 index 000000000..ec5c40205 --- /dev/null +++ b/src/rp2_common/pico_runtime_init/BUILD.bazel @@ -0,0 +1,41 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +# This library creates a bunch of circular dependencies, so just rely on +# the implementation getting pulled in as a link dep (i.e. invert the usual +# interface pattern). +cc_library( + name = "pico_runtime_init", + hdrs = ["include/pico/runtime_init.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/rp2_common:pico_platform_internal", + "//src/rp2_common/pico_runtime", + ], +) + +cc_library( + name = "pico_runtime_init_link", + srcs = [ + "runtime_init.c", + "runtime_init_clocks.c", + "runtime_init_stack_guard.c", + ], + hdrs = ["include/pico/runtime_init.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform_internal", + "//src/rp2_common/hardware_base", + "//src/rp2_common/hardware_clocks", + "//src/rp2_common/hardware_ticks", + "//src/rp2_common/pico_bootrom", + "//src/rp2_common/pico_runtime", + ], + alwayslink = True, +) diff --git a/src/rp2_common/pico_runtime_init/CMakeLists.txt b/src/rp2_common/pico_runtime_init/CMakeLists.txt new file mode 100644 index 000000000..4d43bc555 --- /dev/null +++ b/src/rp2_common/pico_runtime_init/CMakeLists.txt @@ -0,0 +1,17 @@ +pico_add_library(pico_runtime_init) + +target_sources(pico_runtime_init INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/runtime_init.c + ${CMAKE_CURRENT_LIST_DIR}/runtime_init_clocks.c + ${CMAKE_CURRENT_LIST_DIR}/runtime_init_stack_guard.c +) + +target_include_directories(pico_runtime_init_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +pico_mirrored_target_link_libraries(pico_runtime_init INTERFACE + pico_base +) + +if (TARGET hardware_clocks) + pico_mirrored_target_link_libraries(pico_runtime_init INTERFACE hardware_clocks) +endif() diff --git a/src/rp2_common/pico_runtime_init/include/pico/runtime_init.h b/src/rp2_common/pico_runtime_init/include/pico/runtime_init.h new file mode 100644 index 000000000..c6ed4cf8e --- /dev/null +++ b/src/rp2_common/pico_runtime_init/include/pico/runtime_init.h @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_RUNTIME_INITS_H +#define _PICO_RUNTIME_INITS_H + +#include "pico.h" +#include "pico/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file pico/runtime_init.h + * \defgroup pico_runtime_init pico_runtime_init + * + * \brief Main runtime initialization functions required to set up the runtime environment before entering main + * + * The runtime initialization is registration based: + * + * For each step of the initialization there is a 5 digit ordinal which indicates + * the ordering (alphabetic increasing sort of the 5 digits) of the steps. + * + * e.g. for the step "bootrom_reset", there is: + * + * \code + * #ifndef PICO_RUNTIME_INIT_BOOTROM_RESET + * #define PICO_RUNTIME_INIT_BOOTROM_RESET "00050" + * #endif + * \endcode + * + * The user can override the order if they wish, by redefining PICO_RUNTIME_INIT_BOOTROM_RESET + * + * For each step, the automatic initialization may be skipped by defining (in this case) + * PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET = 1. The user can then choose to either omit the step + * completely or register their own replacement initialization. + * + * The default method used to perform the initialization is provided, in case the user + * wishes to call it manually; in this case: + * + * \code + * void runtime_init_bootrom_reset(void); + * \endcode + * + * If PICO_RUNTIME_NO_INIT_BOOTOROM_RESET define is set (NO vs SKIP above), then the function + * is not defined, allowing the user to provide a replacement (and also avoiding + * cases where the default implementation won't compile due to missing dependencies) + */ + +// must have no dependency on any other initialization code +#define PICO_RUNTIME_INIT_EARLIEST "00001" + +// ----------------------------------------------------------------------------------------------- +// Reset of global bootrom state (can be skipped if boot path was via bootrom); not used on RP2040 +// ----------------------------------------------------------------------------------------------- +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET, Skip calling of `runtime_init_bootrom_reset` function during runtime init, type=bool, default=1 on RP2040, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_BOOTROM_RESET, Do not include SDK implementation of `runtime_init_bootrom_reset` function, type=bool, default=1 on RP2040, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_BOOTROM_RESET +#define PICO_RUNTIME_INIT_BOOTROM_RESET "00050" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET +#if PICO_RP2040 || (!LIB_PICO_MULTICORE && PICO_NO_FLASH) +#define PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET 1 +#endif +#endif + +#ifndef PICO_RUNTIME_NO_INIT_BOOTROM_RESET +#if PICO_RP2040 || (!LIB_PICO_MULTICORE && PICO_NO_FLASH) +#define PICO_RUNTIME_NO_INIT_BOOTROM_RESET 1 +#endif +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_bootrom_reset(void); +#endif + +// --------------------------------------------------------------------------------------- +// Non-boot core eset of bootrom state, not needed if only using core 0 not used on RP2040 +// --------------------------------------------------------------------------------------- +#ifndef PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET +#define PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET "00051" +#endif + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET, Skip calling of `runtime_init_per_core_bootrom_reset` function during per-core init, type=bool, default=1 on RP2040, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET, Do not include SDK implementation of `runtime_init_per_core_bootrom_reset` function, type=bool, default=1 on RP2040, group=pico_runtime_init +#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET +#if PICO_RP2040 +#define PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET 1 +#endif +#endif + +#ifndef PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET +#if PICO_RP2040 +#define PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET 1 +#endif +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_per_core_bootrom_reset(void); +#endif + +// --------------------------- +// Hazard3 processor IRQ setup +// --------------------------- + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS, Skip calling of `runtime_init_per_core_h3_irq_registers` function during per-core init, type=bool, default=1 on non RISC-V, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_PER_CORE_H3_IRQ_REGISTERS +#define PICO_RUNTIME_INIT_PER_CORE_H3_IRQ_REGISTERS "00060" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS +#ifndef __riscv +#define PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS 1 +#endif +#endif + +// ------------------------------- +// Earliest resets (no clocks yet) +// ------------------------------- +#ifndef PICO_RUNTIME_INIT_EARLY_RESETS +#define PICO_RUNTIME_INIT_EARLY_RESETS "00100" +#endif + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_EARLY_RESETS, Skip calling of `runtime_init_early_resets` function during runtime init, type=bool, default=1 on RP2040, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_EARLY_RESETS, Do not include SDK implementation of `runtime_init_early_resets` function, type=bool, default=1 on RP2040, group=pico_runtime_init +#ifndef PICO_RUNTIME_SKIP_INIT_EARLY_RESETS +#define PICO_RUNTIME_SKIP_INIT_EARLY_RESETS 0 +#endif + +#ifndef PICO_RUNTIME_NO_INIT_EARLY_RESETS +#define PICO_RUNTIME_NO_INIT_EARLY_RESETS 0 +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_early_resets(void); +#endif + +// -------------- +// USB power down +// -------------- +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN, Skip calling of `runtime_init_usb_power_down` function during runtime init, type=bool, default=0, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_USB_POWER_DOWN, Do not include SDK implementation of `runtime_init_usb_power_down` function, type=bool, default=0, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_USB_POWER_DOWN +#define PICO_RUNTIME_INIT_USB_POWER_DOWN "00101" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN +#define PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN 0 +#endif + +#ifndef PICO_RUNTIME_NO_INIT_USB_POWER_DOWN +#define PICO_RUNTIME_NO_INIT_USB_POWER_DOWN 0 +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_usb_power_down(void); +#endif + +// ------------------------------------ +// per core co-processor initialization +// ------------------------------------ + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS, Skip calling of `runtime_init_per_core_enable_coprocessors` function during per-core init, type=bool, default=1 on RP2040 or RISC-V, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS, Do not include SDK implementation of `runtime_init_per_core_enable_coprocessors` function, type=bool, default=1 on RP2040 or RISC-V, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS +#define PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS "00200" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS +#if PICO_RP2040 || defined(__riscv) +#define PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS 1 +#endif +#endif + +#ifndef PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS +#if PICO_RP2040 || defined(__riscv) +#define PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS 1 +#endif +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_per_core_enable_coprocessors(void); +#endif + +// AEABI init; this initialization is auto-injected byte pico_aeebi_mem_ops if present +#ifndef PICO_RUNTIME_INIT_AEABI_MEM_OPS +// on RP2040 we need to get memcpy and memset hooked up to bootrom +#define PICO_RUNTIME_INIT_AEABI_MEM_OPS "00300" +#endif + +// AEABI init; this initialization is auto-injected byte pico_aeebi_bit_ops if present +#ifndef PICO_RUNTIME_INIT_AEABI_BIT_OPS +#define PICO_RUNTIME_INIT_AEABI_BIT_OPS "00275" +#endif + +// AEABI init; this initialization is auto-injected byte pico_aeebi_float if present +#ifndef PICO_RUNTIME_INIT_AEABI_FLOAT +#define PICO_RUNTIME_INIT_AEABI_FLOAT "00350" +#endif + +// AEABI init; this initialization is auto-injected byte pico_aeebi_double if present +#ifndef PICO_RUNTIME_INIT_AEABI_DOUBLE +#define PICO_RUNTIME_INIT_AEABI_DOUBLE "00350" +#endif + +// ------------------------ +// Initialization of clocks +// ------------------------ +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_CLOCKS, Skip calling of `runtime_init_clocks` function during runtime init, type=bool, default=0, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_CLOCKS, Do not include SDK implementation of `runtime_init_clocks` function, type=bool, default=0, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_CLOCKS +// on RP2040 we need some of the AEABI init by this point to do clock math +#define PICO_RUNTIME_INIT_CLOCKS "00500" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_CLOCKS +#define PICO_RUNTIME_SKIP_INIT_CLOCKS 0 +#endif + +#ifndef PICO_RUNTIME_NO_INIT_CLOCKS +#define PICO_RUNTIME_NO_INIT_CLOCKS 0 +#endif +#ifndef __ASSEMBLER__ +void runtime_init_clocks(void); + +/*! \brief Initialise the clock hardware + * \ingroup pico_runtime_init + * + * Must be called before any other clock function. + */ +static inline void clocks_init(void) { + // backwards compatibility with earlier SDK + runtime_init_clocks(); +} +#endif + +// ---------------------------------------- +// Remaining h/w initialization post clocks +// ---------------------------------------- +#ifndef PICO_RUNTIME_INIT_POST_CLOCK_RESETS +#define PICO_RUNTIME_INIT_POST_CLOCK_RESETS "00600" +#endif + +// PICO_RUNTIME_INIT_POST_CLOCKS_RESETS defaults to 0 +#ifndef __ASSEMBLER__ +void runtime_init_post_clock_resets(void); +#endif + +// ---------------------------------------- +// RP2040 IE disable for GPIO 26-29 +// ---------------------------------------- + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE, Skip calling of `runtime_init_rp2040_gpio_ie_disable` function during runtime init, type=bool, default=0 on RP2040, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE, Do not include SDK implementation of `runtime_init_rp2040_gpio_ie_disable` function, type=bool, default=0 on RP2040, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE +#define PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE "00700" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE +#if !PICO_RP2040 || PICO_IE_26_29_UNCHANGED_ON_RESET +#define PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE 1 +#endif +#endif +#ifndef PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE +#if !PICO_RP2040 +#define PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE 1 +#endif +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_rp2040_gpio_ie_disable(void); +#endif + +// ----------------------------- +// Reset all spin SIO spin locks +// ----------------------------- + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET, Skip calling of `runtime_init_spin_locks_reset` function during runtime init, type=bool, default=0, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET, Do not include SDK implementation of `runtime_init_spin_locks_reset` function, type=bool, default=0, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_SPIN_LOCKS_RESET +// clearing of all spin locks +#define PICO_RUNTIME_INIT_SPIN_LOCKS_RESET "01000" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET +#define PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET 0 +#endif + +#ifndef PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET +#define PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET 0 +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_spin_locks_reset(void); +#endif + +// ----------------------------- +// Reset all bootram boot locks +// ----------------------------- + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET, Skip calling of `runtime_init_boot_locks_reset` function during runtime init, type=bool, default=0, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_BOOT_LOCKS_RESET +// clearing of all spin locks +#define PICO_RUNTIME_INIT_BOOT_LOCKS_RESET "01000" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET +#define PICO_RUNTIME_SKIP_INIT_BOOT_LOCKS_RESET 0 +#endif +#ifndef __ASSEMBLER__ +void runtime_init_boot_locks_reset(void); +#endif + +// ------------------------------ +// Enable bootrom locking support +// ------------------------------ +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE, Skip calling of `runtime_init_bootrom_locking_enable` function during runtime init, type=bool, default=0, group=pico_runtime_init +#ifndef PICO_RUNTIME_INIT_BOOTROM_LOCKING_ENABLE +// clearing of all spin locks +#define PICO_RUNTIME_INIT_BOOTROM_LOCKING_ENABLE "01010" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE +#define PICO_RUNTIME_SKIP_INIT_BOOTROM_LOCKING_ENABLE 0 +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_bootrom_locking_enable(void); +#endif + +// PICO_RUNTIME_INIT_MUTEX is registered automatically by pico_sync +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_MUTEX, Skip calling of `runtime_init_mutex` function during runtime init, type=bool, default=0, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_MUTEX, Do not include SDK implementation of `runtime_init_mutex` function, type=bool, default=0, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_MUTEX +// depends on SPIN_LOCKS +// initialize auto_init mutexes +#define PICO_RUNTIME_INIT_MUTEX "01100" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_MUTEX +#define PICO_RUNTIME_SKIP_INIT_MUTEX 0 +#endif + +#ifndef PICO_RUNTIME_NO_INIT_MUTEX +#define PICO_RUNTIME_NO_INIT_MUTEX 0 +#endif + +// ------------------------------------------------------------ +// Initialization of IRQs, added by hardware_irq +// ------------------------------------------------------------ + +#ifndef PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES +#define PICO_RUNTIME_INIT_PER_CORE_IRQ_PRIORITIES "01200" +#endif + +// PICO_RUNTIME_SKIP_INIT_PER_CORE_TLS_SETUP defaults to 0 +#ifndef PICO_RUNTIME_INIT_PER_CORE_TLS_SETUP +#define PICO_RUNTIME_INIT_PER_CORE_TLS_SETUP "10060" +#endif + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE, Skip calling of `runtime_init_install_ram_vector_table` function during runtime init, type=bool, default=0 unless RISC-V or RAM binary, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE, Do not include SDK implementation of `runtime_init_install_ram_vector_table` function, type=bool, default=0 unless RISC-V or RAM binary, group=pico_runtime_init +#ifndef PICO_RUNTIME_INIT_INSTALL_RAM_VECTOR_TABLE +#define PICO_RUNTIME_INIT_INSTALL_RAM_VECTOR_TABLE "10080" +#endif + +// ------------------------------------------------------ +// Copy of ROM vector table to RAM; not used on RISC-V or +// no_flash which has a RAM vector table anyway +// ------------------------------------------------------ + +#ifndef PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE +#if PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH || defined(__riscv) +#define PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE 1 +#endif +#endif + +#ifndef PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE +#if PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH || defined(__riscv) +#define PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE 1 +#endif +#endif + +// ------------------------------------------------------------ +// Default alarm pool initialization, added by pico_time unless +// PICO_TIME_DEFAULT_ALARM_POOL_DISABLED == 1 +// ------------------------------------------------------------ +#ifndef PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL +#define PICO_RUNTIME_INIT_DEFAULT_ALARM_POOL "11000" +#endif + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL, Skip calling of `runtime_init_default_alarm_pool` function during runtime init, type=bool, default=1 if `PICO_TIME_DEFAULT_ALARM_POOL_DISABLED` is 1, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL, Do not include SDK implementation of `runtime_init_default_alarm_pool` function, type=bool, default=1 if `PICO_TIME_DEFAULT_ALARM_POOL_DISABLED` is , group=pico_runtime_init +#ifndef PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL +#if PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +#define PICO_RUNTIME_SKIP_INIT_DEFAULT_ALARM_POOL 1 +#endif +#endif + +#ifndef PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL +#if PICO_TIME_DEFAULT_ALARM_POOL_DISABLED +#define PICO_RUNTIME_NO_INIT_DEFAULT_ALARM_POOL 1 +#endif +#endif + +// ------------------------------------------------------------------------------------------------ +// stack guard; these are a special case as they take a parameter; however the normal defines apply +// ------------------------------------------------------------------------------------------------ + +// PICO_CONFIG: PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD, Skip calling of `runtime_init_per_core_install_stack_guard` function during runtime init, type=bool, default=1 unless `PICO_USE_STACK_GUARDS` is 1, group=pico_runtime_init +// PICO_CONFIG: PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD, Do not include SDK implementation of `runtime_init_per_core_install_stack_guard` function, type=bool, default=1 unless `PICO_USE_STACK_GUARDS` is 1, group=pico_runtime_init + +#ifndef PICO_RUNTIME_INIT_PER_CORE_INSTALL_STACK_GUARD +#define PICO_RUNTIME_INIT_PER_CORE_INSTALL_STACK_GUARD "10050" +#endif + +#ifndef PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD +#if !PICO_USE_STACK_GUARDS +#define PICO_RUNTIME_SKIP_INIT_PER_CORE_INSTALL_STACK_GUARD 1 +#endif +#endif + +#ifndef PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD +#if !PICO_USE_STACK_GUARDS +#define PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD 1 +#endif +#endif + +#ifndef __ASSEMBLER__ +void runtime_init_per_core_install_stack_guard(void *stack_bottom); +// backwards compatibility +static __force_inline void runtime_install_stack_guard(void *stack_bottom) { + runtime_init_per_core_install_stack_guard(stack_bottom); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_runtime_init/runtime_init.c b/src/rp2_common/pico_runtime_init/runtime_init.c new file mode 100644 index 000000000..2b69c8069 --- /dev/null +++ b/src/rp2_common/pico_runtime_init/runtime_init.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/runtime_init.h" + +// This file is sorted in the order of initialization + +// ------------------------------------- +// 00050 PICO_RUNTIME_INIT_BOOTROM_RESET +// ------------------------------------- +#if !PICO_RUNTIME_NO_INIT_BOOTROM_RESET +#include "pico/bootrom.h" +void __weak runtime_init_bootrom_reset(void) { + // todo can we tell if we came in thru the bootrom where this is not necessary (this is necessary for debugger) + rom_bootrom_state_reset_fn state_reset = rom_func_lookup(ROM_FUNC_BOOTROM_STATE_RESET); + state_reset(BOOTROM_STATE_RESET_GLOBAL_STATE); +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_BOOTROM_RESET +PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_bootrom_reset, PICO_RUNTIME_INIT_BOOTROM_RESET); +#endif + +// ---------------------------------------------- +// 00051 PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET +// ---------------------------------------------- +#if !PICO_RUNTIME_NO_INIT_PER_CORE_BOOTROM_RESET +#include "pico/bootrom.h" +void __weak runtime_init_per_core_bootrom_reset(void) { + // todo can we tell if we came in thru the bootrom where this is not necessary (this is necessary for debugger) + rom_bootrom_state_reset_fn state_reset = rom_func_lookup(ROM_FUNC_BOOTROM_STATE_RESET); + state_reset(BOOTROM_STATE_RESET_CURRENT_CORE); +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_BOOTROM_RESET +PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_bootrom_reset, PICO_RUNTIME_INIT_PER_CORE_BOOTROM_RESET); +#endif + +// ------------------------------------ +// 00060 PICO_RUNTIME_INIT_H3_IRQ_REGISTERS +// ------------------------------------ +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_H3_IRQ_REGISTERS +extern void runtime_init_per_core_h3_irq_registers(void); +PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_h3_irq_registers, PICO_RUNTIME_INIT_PER_CORE_H3_IRQ_REGISTERS); +#endif + +// ------------------------------------ +// 00100 PICO_RUNTIME_INIT_EARLY_RESETS +// ------------------------------------ +#if !PICO_RUNTIME_NO_INIT_EARLY_RESETS +#include "hardware/resets.h" +void __weak runtime_init_early_resets(void) { + static_assert(NUM_RESETS <= 32, ""); + // Reset all peripherals to put system into a known state, + // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash + // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot + // - and USB, syscfg, as this disturbs USB-to-SWD on core 1 + reset_block_mask(~( + (1u << RESET_IO_QSPI) | + (1u << RESET_PADS_QSPI) | + (1u << RESET_PLL_USB) | + (1u << RESET_USBCTRL) | + (1u << RESET_SYSCFG) | + (1u << RESET_PLL_SYS) + )); + + // Remove reset from peripherals which are clocked only by clk_sys and + // clk_ref. Other peripherals stay in reset until we've configured clocks. + unreset_block_mask_wait_blocking(RESETS_RESET_BITS & ~( +#if !PICO_RP2040 + (1u << RESET_HSTX) | + #endif + (1u << RESET_ADC) | + #if PICO_RP2040 + (1u << RESET_RTC) | + #endif + (1u << RESET_SPI0) | + (1u << RESET_SPI1) | + (1u << RESET_UART0) | + (1u << RESET_UART1) | + (1u << RESET_USBCTRL) + )); + +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_EARLY_RESETS +PICO_RUNTIME_INIT_FUNC_HW(runtime_init_early_resets, PICO_RUNTIME_INIT_EARLY_RESETS); +#endif + +#if !PICO_RUNTIME_NO_INIT_USB_POWER_DOWN +#include "hardware/structs/usb.h" +void __weak runtime_init_usb_power_down(void) { + // Ensure USB PHY is in low-power state -- must be cleared before beginning USB operations. Only + // do this if USB appears to be in the reset state, to avoid breaking core1-as-debugger. + if (usb_hw->sie_ctrl == USB_SIE_CTRL_RESET) { + hw_set_bits(&usb_hw->sie_ctrl, USB_SIE_CTRL_TRANSCEIVER_PD_BITS); + } +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_USB_POWER_DOWN +PICO_RUNTIME_INIT_FUNC_HW(runtime_init_usb_power_down, PICO_RUNTIME_INIT_USB_POWER_DOWN); +#endif + +#if !PICO_RUNTIME_NO_INIT_PER_CORE_ENABLE_COPROCESSORS +#include "hardware/gpio.h" // PICO_USE_GPIO_COPROCESSOR is defined here +#include "hardware/structs/m33.h" +// ---------------------------------------------------- +// 00200 PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS +// ---------------------------------------------------- +void __weak runtime_init_per_core_enable_coprocessors(void) { + // VFP copro (float) + uint32_t cpacr = M33_CPACR_CP10_BITS; +#if HAS_DOUBLE_COPROCESSOR + cpacr |= M33_CPACR_CP4_BITS; +#endif +#if PICO_USE_GPIO_COPROCESSOR + cpacr |= M33_CPACR_CP0_BITS; +#endif + arm_cpu_hw->cpacr |= cpacr; +#if HAS_DOUBLE_COPROCESSOR + asm volatile ("mrc p4,#0,r0,c0,c0,#1" : : : "r0"); // clear engaged flag via RCMP +#endif +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_PER_CORE_ENABLE_COPROCESSORS +PICO_RUNTIME_INIT_FUNC_PER_CORE(runtime_init_per_core_enable_coprocessors, PICO_RUNTIME_INIT_PER_CORE_ENABLE_COPROCESSORS); +#endif + +// ---------------------------------------------------- +// 00500 PICO_RUNTIME_INIT_CLOCKS +// ---------------------------------------------------- +#if !PICO_RUNTIME_SKIP_INIT_CLOCKS +PICO_RUNTIME_INIT_FUNC_HW(runtime_init_clocks, PICO_RUNTIME_INIT_CLOCKS); +#endif + +// ---------------------------------------------------- +// 00600 PICO_RUNTIME_INIT_POST_CLOCK_RESETS +// ---------------------------------------------------- +#if !PICO_RUNTIME_NO_INIT_POST_CLOCK_RESETS +#include "hardware/resets.h" +void __weak runtime_init_post_clock_resets(void) { + // Peripheral clocks should now all be running + static_assert(NUM_RESETS <= 32, ""); + unreset_block_mask_wait_blocking(RESETS_RESET_BITS); +} +#endif + +#if !PICO_RUNTIME_SKIP_POST_CLOCK_RESETS +PICO_RUNTIME_INIT_FUNC_HW(runtime_init_post_clock_resets, PICO_RUNTIME_INIT_POST_CLOCK_RESETS); +#endif + +// ---------------------------------------------------- +// 00700 PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE +// ---------------------------------------------------- + +#if !PICO_RUNTIME_NO_INIT_RP2040_GPIO_IE_DISABLE +#include "hardware/structs/pads_bank0.h" +void __weak runtime_init_rp2040_gpio_ie_disable(void) { +#if PICO_RP2040 && !PICO_IE_26_29_UNCHANGED_ON_RESET + // after resetting BANK0 we should disable IE on 26-29 as these may have mid-rail voltages when + // ADC is in use (on RP2040 B2 and later, and non-RP2040 chips, ADC pins should already have + // the correct reset state): + pads_bank0_hw_t *pads_bank0_hw_clear = (pads_bank0_hw_t *)hw_clear_alias_untyped(pads_bank0_hw); + pads_bank0_hw_clear->io[26] = pads_bank0_hw_clear->io[27] = + pads_bank0_hw_clear->io[28] = pads_bank0_hw_clear->io[29] = PADS_BANK0_GPIO0_IE_BITS; +#endif +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_RP2040_GPIO_IE_DISABLE +PICO_RUNTIME_INIT_FUNC_HW(runtime_init_rp2040_gpio_ie_disable, PICO_RUNTIME_INIT_RP2040_GPIO_IE_DISABLE); +#endif + +#if !PICO_RUNTIME_NO_INIT_SPIN_LOCKS_RESET +#include "hardware/sync.h" +void __weak runtime_init_spin_locks_reset(void) { + spin_locks_reset(); +} +#endif + +#if !PICO_RUNTIME_SKIP_INIT_SPIN_LOCKS_RESET +PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_spin_locks_reset, PICO_RUNTIME_INIT_SPIN_LOCKS_RESET); +#endif + +// On RISC-V the vector table is not relocatable since it contains PC-relative +// jump instructions, so rather than copying it into a RAM-resident array, we +// just link it in an initialised RAM section. Note there is no requirement on +// RISC-V to have an initial flash-resident vector table at a well-known +// location, unlike Cortex-M which can take an NMI on cycle 0. +#ifndef __riscv + +#if !PICO_RUNTIME_NO_INIT_INSTALL_RAM_VECTOR_TABLE +uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[PICO_RAM_VECTOR_TABLE_SIZE]; + +#include "hardware/structs/scb.h" +void runtime_init_install_ram_vector_table(void) { + // Note on RISC-V the RAM vector table is initialised during crt0 +#if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH) && !defined(__riscv) +#if !PICO_NO_STORED_VECTOR_TABLE + __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, sizeof(ram_vector_table)); +#else + __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, MIN(VTABLE_FIRST_IRQ, sizeof(ram_vector_table))); + for(uint i = VTABLE_FIRST_IRQ; ivtor = (uintptr_t) ram_vector_table; +#endif +} +#endif +#endif + +#if !PICO_RUNTIME_SKIP_INIT_INSTALL_RAM_VECTOR_TABLE +// todo this wants to be per core if we decide to support per core vector tables +PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_install_ram_vector_table, PICO_RUNTIME_INIT_INSTALL_RAM_VECTOR_TABLE); +#endif diff --git a/src/rp2_common/pico_runtime_init/runtime_init_clocks.c b/src/rp2_common/pico_runtime_init/runtime_init_clocks.c new file mode 100644 index 000000000..435a80166 --- /dev/null +++ b/src/rp2_common/pico_runtime_init/runtime_init_clocks.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/runtime_init.h" +#if !PICO_RUNTIME_NO_INIT_CLOCKS + +#include "hardware/clocks.h" +#include "hardware/pll.h" +#include "hardware/ticks.h" +#include "hardware/xosc.h" +#if PICO_RP2040 +#include "hardware/regs/rtc.h" +#endif + +#if PICO_RP2040 +// The RTC clock frequency is 48MHz divided by power of 2 (to ensure an integer +// division ratio will be used in the clocks block). A divisor of 1024 generates +// an RTC clock tick of 46875Hz. This frequency is relatively close to the +// customary 32 or 32.768kHz 'slow clock' crystals and provides good timing resolution. +#define RTC_CLOCK_FREQ_HZ (USB_CLK_HZ / 1024) +#endif + +static void start_all_ticks(void) { + uint32_t cycles = clock_get_hz(clk_ref) / MHZ; + // Note RP2040 has a single tick generator in the watchdog which serves + // watchdog, system timer and M0+ SysTick; The tick generator is clocked from clk_ref + // but is now adapted by the hardware_ticks library for compatibility with RP2350 + // npte: hardware_ticks library now provides an adapter for RP2040 + + for (int i = 0; i < (int)TICK_COUNT; ++i) { + tick_start((tick_gen_num_t)i, cycles); + } +} + +void __weak runtime_init_clocks(void) { + // Note: These need setting *before* the ticks are started + if (running_on_fpga()) { + for (uint i = 0; i < CLK_COUNT; i++) { + clock_set_reported_hz(i, 48 * MHZ); + } + // clk_ref is 12MHz in both RP2040 and RP2350 FPGA + clock_set_reported_hz(clk_ref, 12 * MHZ); + // RP2040 has an extra clock, the rtc +#if HAS_RP2040_RTC + clock_set_reported_hz(clk_rtc, RTC_CLOCK_FREQ_HZ); +#endif + } else { + // Disable resus that may be enabled from previous software + clocks_hw->resus.ctrl = 0; + + // Enable the xosc + xosc_init(); + + // Before we touch PLLs, switch sys and ref cleanly away from their aux sources. + hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); + while (clocks_hw->clk[clk_sys].selected != 0x1) + tight_loop_contents(); + hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); + while (clocks_hw->clk[clk_ref].selected != 0x1) + tight_loop_contents(); + + /// \tag::pll_init[] + pll_init(pll_sys, PLL_SYS_REFDIV, PLL_SYS_VCO_FREQ_HZ, PLL_SYS_POSTDIV1, PLL_SYS_POSTDIV2); + pll_init(pll_usb, PLL_USB_REFDIV, PLL_USB_VCO_FREQ_HZ, PLL_USB_POSTDIV1, PLL_USB_POSTDIV2); + /// \end::pll_init[] + + // Configure clocks + + // RP2040 CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz + // RP2350 CLK_REF = XOSC (XOSC_MHZ) / N (1,2,4) = 12MHz + + // clk_ref aux select is 0 because: + // + // - RP2040: no aux mux on clk_ref, so this field is don't-care. + // + // - RP2350: there is an aux mux, but we are selecting one of the + // non-aux inputs to the glitchless mux, so the aux select doesn't + // matter. The value of 0 here happens to be the sys PLL. + + clock_configure_undivided(clk_ref, + CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, + 0, + XOSC_HZ); + + /// \tag::configure_clk_sys[] + // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz + clock_configure_undivided(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, + SYS_CLK_HZ); + /// \end::configure_clk_sys[] + + // CLK USB = PLL USB 48MHz / 1 = 48MHz + clock_configure_undivided(clk_usb, + 0, // No GLMUX + CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + USB_CLK_HZ); + + // CLK ADC = PLL USB 48MHZ / 1 = 48MHz + clock_configure_undivided(clk_adc, + 0, // No GLMUX + CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + USB_CLK_HZ); + +#if HAS_RP2040_RTC + // CLK RTC = PLL USB 48MHz / 1024 = 46875Hz +#if (USB_CLK_HZ % RTC_CLOCK_FREQ_HZ == 0) + // this doesn't pull in 64 bit arithmetic + clock_configure_int_divider(clk_rtc, + 0, // No GLMUX + CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + USB_CLK_HZ, + USB_CLK_HZ / RTC_CLOCK_FREQ_HZ); + +#else + clock_configure(clk_rtc, + 0, // No GLMUX + CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, + USB_CLK_HZ, + RTC_CLOCK_FREQ_HZ); + +#endif +#endif + + // CLK PERI = clk_sys. Used as reference clock for UART and SPI serial. + clock_configure_undivided(clk_peri, + 0, + CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, + SYS_CLK_HZ); + +#if HAS_HSTX + // CLK_HSTX = clk_sys. Transmit bit clock for the HSTX peripheral. + clock_configure_undivided(clk_hstx, + 0, + CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS, + SYS_CLK_HZ); +#endif + } + + // Finally, all clocks are configured so start the ticks + // The ticks use clk_ref so now that is configured we can start them + start_all_ticks(); +} + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_runtime_init/runtime_init_stack_guard.c b/src/rp2_common/pico_runtime_init/runtime_init_stack_guard.c new file mode 100644 index 000000000..27480f2ce --- /dev/null +++ b/src/rp2_common/pico_runtime_init/runtime_init_stack_guard.c @@ -0,0 +1,77 @@ +#include "pico/runtime.h" + +#if !PICO_RUNTIME_NO_INIT_PER_CORE_INSTALL_STACK_GUARD +#if PICO_RP2040 +#include "hardware/structs/mpu.h" +#elif defined(__riscv) +#include "hardware/riscv.h" +#endif +// this is called for each thread since they have their own MPU +void runtime_init_per_core_install_stack_guard(void *stack_bottom) { + // this is called b4 runtime_init is complete, so beware printf or assert + + uintptr_t addr = (uintptr_t) stack_bottom; + // the minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will + // just shorten the valid stack range a tad + addr = (addr + 31u) & ~31u; + +#if PICO_RP2040 + // Armv6-M MPU + // make sure no one is using the MPU yet + if (mpu_hw->ctrl) { + // Note that it would be tempting to change this to a panic, but it happens so early, printing is not a good idea + __breakpoint(); + } + // mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want + uint32_t subregion_select = 0xffu ^ (1u << ((addr >> 5u) & 7u)); + mpu_hw->ctrl = 5; // enable mpu with background default map + mpu_hw->rbar = (addr & (uint)~0xff) | M0PLUS_MPU_RBAR_VALID_BITS | 0; + mpu_hw->rasr = 1 // enable region + | (0x7 << 1) // size 2^(7 + 1) = 256 + | (subregion_select << 8) + | 0x10000000; // XN = disable instruction fetch; no other bits means no permissions + +#elif defined(__riscv) + #if !PICO_RP2350 +#error "Check PMP configuration for new platform" +#endif + // RISC-V PMP, RP2350 configuration of Hazard3: 8 non-hardwired regions, + // NAPOT only, 32-byte granule, with nonstandard PMPCFGM0 register to + // apply regions to M-mode without locking them. + // Make sure no one is using the PMP yet + bool dirty_pmp = + riscv_read_csr(pmpcfg0) != 0 || + riscv_read_csr(pmpcfg1) != 0 || + riscv_read_csr(RVCSR_PMPCFGM0_OFFSET) != 0; + + if (dirty_pmp) { + __breakpoint(); + } + + // Note pmpaddr is in units of 4 bytes, so right-shift 2. + riscv_write_csr(pmpaddr0, (addr | 0x0fu) >> 2); + // Make this region inaccessible in both M-mode and U-mode (but don't lock it) + riscv_write_csr(RVCSR_PMPCFGM0_OFFSET, 0x1u); + riscv_write_csr(pmpcfg0, RVCSR_PMPCFG0_R0_A_VALUE_NAPOT << RVCSR_PMPCFG0_R0_A_LSB); + +#else +// // Armv8-M MPU +// // make sure no one is using the MPU yet +// if (mpu_hw->ctrl) { +// __breakpoint(); +// } +// mpu_hw->rnr = 0; +// // Read-only, privileged-only, nonexecutable. (Good enough because stack +// // is usually written first, on a stack push) +// mpu_hw->rbar = addr | (2u << M33_MPU_RBAR_AP_LSB) | (M33_MPU_RBAR_XN_BITS); +// mpu_hw->rlar = addr | M33_MPU_RLAR_EN_BITS; +// // Enable MPU (and leave default attributes applied even for privileged software) +// mpu_hw->ctrl = M33_MPU_CTRL_PRIVDEFENA_BITS | M33_MPU_CTRL_ENABLE_BITS; + pico_default_asm_volatile( + "msr msplim, %0" + : + : "r" (stack_bottom)); +#endif +} + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_sha256/BUILD.bazel b/src/rp2_common/pico_sha256/BUILD.bazel new file mode 100644 index 000000000..e2882d117 --- /dev/null +++ b/src/rp2_common/pico_sha256/BUILD.bazel @@ -0,0 +1,19 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_sha256", + srcs = ["sha256.c"], + hdrs = ["include/pico/sha256.h"], + defines = ["LIB_PICO_SHA256=1"], + implementation_deps = ["//src/rp2_common/pico_bootrom"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_time", + "//src/rp2_common:hardware_structs", + "//src/rp2_common/hardware_dma", + "//src/rp2_common/hardware_sha256", + ], +) diff --git a/src/rp2_common/pico_sha256/CMakeLists.txt b/src/rp2_common/pico_sha256/CMakeLists.txt new file mode 100644 index 000000000..1d6e078da --- /dev/null +++ b/src/rp2_common/pico_sha256/CMakeLists.txt @@ -0,0 +1,19 @@ +if (NOT TARGET hardware_sha256) + return() +endif() + +pico_add_library(pico_sha256) + +target_sources(pico_sha256 INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/sha256.c +) + +target_include_directories(pico_sha256_headers SYSTEM INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/include +) + +pico_mirrored_target_link_libraries(pico_sha256 INTERFACE + hardware_dma + hardware_sha256 + pico_sync + ) diff --git a/src/rp2_common/pico_sha256/include/pico/sha256.h b/src/rp2_common/pico_sha256/include/pico/sha256.h new file mode 100644 index 000000000..80aa5af37 --- /dev/null +++ b/src/rp2_common/pico_sha256/include/pico/sha256.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_SHA256_H +#define _PICO_SHA256_H + +#include "pico/time.h" +#include "hardware/dma.h" +#include "hardware/sha256.h" + +/** \file pico/sha256.h + * \defgroup pico_sha256 pico_sha256 + * + * \brief SHA-256 Hardware Accelerated implementation + * + * RP2350 is equipped with a hardware accelerated implementation of the SHA-256 hash algorithm. + * This should be much quicker than performing a SHA-256 checksum in software. + * + * \code + * pico_sha256_state_t state; + * if (pico_sha256_try_start(&state, SHA256_BIG_ENDIAN, true) == PICO_OK) { + * sha256_result_t result; + * pico_sha256_update(&state, some_data, sizeof(some_data)); + * pico_sha256_update(&state, some_more_data, sizeof(some_more_data)); + * pico_sha256_finish(&state, &result); + * for (int i = 0; i < SHA256_RESULT_BYTES; i++) { + * printf("%02x", result.bytes[i]); + * } + * } + * \endcode + * + * \subsection sha256_example Example + * \addtogroup pico_sha256 + * + * \include hello_sha256.c + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \brief SHA-256 state used by the API + * \ingroup pico_sha256 + */ +typedef struct pico_sha256_state { + enum sha256_endianness endianness; + int8_t channel; + bool locked; + uint8_t cache_used; + union { + uint32_t word; + uint8_t bytes[4]; + } cache; + dma_channel_config config; + size_t total_data_size; +} pico_sha256_state_t; + +/*! \brief Start a SHA-256 calculation returning immediately with an error if the SHA-256 hardware is not available + * \ingroup pico_sha256 + * + * Initialises the hardware and state ready to start a new SHA-256 calculation. + * Only one instance can be started at any time. + * + * @param state A pointer to a pico_sha256_state_t instance + * @param endianness SHA256_BIG_ENDIAN or SHA256_LITTLE_ENDIAN for data in and data out + * @param use_dma Set to true to use DMA internally to copy data to hardware. This is quicker at the expense of hardware DMA resources. + * @return Returns PICO_OK if the hardware was available for use and the sha256 calculation could be started, otherwise an error is returned + */ +int pico_sha256_try_start(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma); + +/*! \brief Start a SHA-256 calculation waiting for a defined period for the SHA-256 hardware to be available + * \ingroup pico_sha256 + * + * Initialises the hardware and state ready to start a new SHA-256 calculation. + * Only one instance can be started at any time. + * + * @param state A pointer to a pico_sha256_state_t instance + * @param endianness SHA256_BIG_ENDIAN or SHA256_LITTLE_ENDIAN for data in and data out + * @param use_dma Set to true to use DMA internally to copy data to hardware. This is quicker at the expense of hardware DMA resources. + * @param until How long to wait for the SHA hardware to be available + * @return Returns PICO_OK if the hardware was available for use and the sha256 calculation could be started in time, otherwise an error is returned + */ +int pico_sha256_start_blocking_until(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma, absolute_time_t until); + +/*! \brief Start a SHA-256 calculation, blocking forever waiting until the SHA-256 hardware is available + * \ingroup pico_sha256 + * + * Initialises the hardware and state ready to start a new SHA-256 calculation. + * Only one instance can be started at any time. + * + * @param state A pointer to a pico_sha256_state_t instance + * @param endianness SHA256_BIG_ENDIAN or SHA256_LITTLE_ENDIAN for data in and data out + * @param use_dma Set to true to use DMA internally to copy data to hardware. This is quicker at the expense of hardware DMA resources. + * @return Returns PICO_OK if the hardware was available for use and the sha256 calculation could be started, otherwise an error is returned + */ +static inline int pico_sha256_start_blocking(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma) { + return pico_sha256_start_blocking_until(state, endianness, use_dma, at_the_end_of_time); +} + +/*! \brief Add byte data to be SHA-256 calculation + * \ingroup pico_sha256 + * + * Add byte data to be SHA-256 calculation + * You may call this as many times as required to add all the data needed. + * You must have called pico_sha256_try_start (or equivalent) already. + * + * @param state A pointer to a pico_sha256_state_t instance + * @param data Pointer to the data to be added to the calculation + * @param data_size_bytes Amount of data to add + * + * @note This function may return before the copy has completed in which case the data passed to the function must remain valid and + * unchanged until a further call to pico_sha256_update or pico_sha256_finish. If this is not done, corrupt data may be used for the + * SHA-256 calculation giving an unexpected result. + */ +void pico_sha256_update(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes); + +/*! \brief Add byte data to be SHA-256 calculation + * \ingroup pico_sha256 + * + * Add byte data to be SHA-256 calculation + * You may call this as many times as required to add all the data needed. + * You must have called pico_sha256_try_start already. + * + * @param state A pointer to a pico_sha256_state_t instance + * @param data Pointer to the data to be added to the calculation + * @param data_size_bytes Amount of data to add + * + * @note This function will only return when the data passed in is no longer required, so it can be freed or changed on return. + */ +void pico_sha256_update_blocking(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes); + +/*! \brief Finish the SHA-256 calculation and return the result + * \ingroup pico_sha256 + * + * Ends the SHA-256 calculation freeing the hardware for use by another caller. + * You must have called pico_sha256_try_start already. + * + * @param state A pointer to a pico_sha256_state_t instance + * @param out The SHA-256 checksum + */ +void pico_sha256_finish(pico_sha256_state_t *state, sha256_result_t *out); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/rp2_common/pico_sha256/sha256.c b/src/rp2_common/pico_sha256/sha256.c new file mode 100644 index 000000000..e0cc73974 --- /dev/null +++ b/src/rp2_common/pico_sha256/sha256.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "hardware/sha256.h" +#include "pico/bootrom/lock.h" +#include "pico/sha256.h" +#include "pico/time.h" + +// We add one 0x80 byte, then 8 bytes for the size +#define SHA256_PADDING_DATA_BYTES 9 +#define SHA256_BLOCK_SIZE_BYTES 64 + +bool __weak pico_sha256_lock(pico_sha256_state_t *state) { + if (!bootrom_try_acquire_lock(BOOTROM_LOCK_SHA_256)) + return false; + state->locked = true; + return true; +} + +void __weak pico_sha256_unlock(pico_sha256_state_t *state) { + assert(state->locked); + bootrom_release_lock(BOOTROM_LOCK_SHA_256); + state->locked = false; +} + +int pico_sha256_try_start(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma) { + memset(state, 0, sizeof(*state)); + if (!pico_sha256_lock(state)) return PICO_ERROR_RESOURCE_IN_USE; + state->endianness = endianness; + if (use_dma) { + state->channel = (int8_t)dma_claim_unused_channel(false); + if (state->channel < 0) { + pico_sha256_unlock(state); + return PICO_ERROR_INSUFFICIENT_RESOURCES; + } + state->config = dma_channel_get_default_config(state->channel); + channel_config_set_transfer_data_size(&state->config, DMA_SIZE_8); + channel_config_set_read_increment(&state->config, true); + channel_config_set_write_increment(&state->config, false); + channel_config_set_dreq(&state->config, DREQ_SHA256); + sha256_set_dma_size(1); + } else { + state->channel = -1; + } + sha256_err_not_ready_clear(); + sha256_set_bswap(endianness == SHA256_BIG_ENDIAN); + sha256_start(); + state->total_data_size = 0; + return PICO_OK; +} + +int pico_sha256_start_blocking_until(pico_sha256_state_t *state, enum sha256_endianness endianness, bool use_dma, absolute_time_t until) { + int rc; + do { + rc = pico_sha256_try_start(state, endianness, use_dma); + if (rc != PICO_ERROR_RESOURCE_IN_USE) break; + if (time_reached(until)) { + rc = PICO_ERROR_TIMEOUT; + break; + } + } while (true); + return rc; +} + +static void write_to_hardware(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { + if (state->channel >= 0) { + dma_channel_wait_for_finish_blocking(state->channel); + assert(!sha256_err_not_ready()); + sha256_wait_ready_blocking(); + dma_channel_configure( + state->channel, + &state->config, + sha256_get_write_addr(), + data, + data_size_bytes, + true + ); + } else { + if (!state->cache_used && !(((uintptr_t)data)&3u)) { + GCC_Like_Pragma("GCC diagnostic ignored \"-Wcast-align\"") + const uint32_t *data32 = (const uint32_t *)data; + // aligned writes + while (data_size_bytes >= 4) { + // write a whole word + sha256_wait_ready_blocking(); + sha256_put_word(*data32++); + data_size_bytes -= 4; + } + data = (const uint8_t *)data32; + } + while (data_size_bytes--) { + state->cache.bytes[state->cache_used++] = *data++; + if (state->cache_used == 4) { + state->cache_used = 0; + sha256_wait_ready_blocking(); + sha256_put_word(state->cache.word); + } + } + } +} + +static void update_internal(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { + assert(state->locked); + // must finish off the last 64 byte block first or else sha256_err_not_ready will be true + size_t bytes_left = ((state->total_data_size + (SHA256_BLOCK_SIZE_BYTES - 1)) & ~(SHA256_BLOCK_SIZE_BYTES - 1)) - state->total_data_size; + if (bytes_left > data_size_bytes) bytes_left = data_size_bytes; + if (bytes_left > 0) { + write_to_hardware(state, data, bytes_left); + state->total_data_size += bytes_left; + data_size_bytes -= bytes_left; + data += bytes_left; + } + // Write the rest of the data + if (data_size_bytes > 0) { + write_to_hardware(state, data, data_size_bytes); + state->total_data_size += data_size_bytes; + } +} + +static void add_zero_bytes(pico_sha256_state_t *state, size_t data_size_bytes) { + uint32_t zero = 0; + // todo: can be done a bit more efficiently with dma? + assert(data_size_bytes < INT32_MAX); + while((int32_t)data_size_bytes > 0) { + update_internal(state, (uint8_t *)&zero, MIN(4, data_size_bytes)); + data_size_bytes -= 4; + } +} + +void pico_sha256_update(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { + update_internal(state, data, data_size_bytes); +} + +void pico_sha256_update_blocking(pico_sha256_state_t *state, const uint8_t *data, size_t data_size_bytes) { + update_internal(state, data, data_size_bytes); + if (state->channel >= 0) { + dma_channel_wait_for_finish_blocking(state->channel); + } +} + +// write the SHA-256 padding to hardware +static void write_padding(pico_sha256_state_t *state) { + // Has to be a multiple of 64 bytes + uint64_t size = (state->total_data_size + SHA256_PADDING_DATA_BYTES + (SHA256_BLOCK_SIZE_BYTES - 1)) & ~(SHA256_BLOCK_SIZE_BYTES - 1); + const size_t user_data_size = state->total_data_size; + const size_t padding_size_bytes = size - state->total_data_size; + + // append a single '1' bit + const uint8_t one_bit = 0x80; + update_internal(state, &one_bit, 1); + + // Zero unused padding + add_zero_bytes(state, padding_size_bytes - SHA256_PADDING_DATA_BYTES); + + // Add size in bits, big endian + size = __builtin_bswap64(user_data_size * 8); + update_internal(state, (uint8_t*)&size, sizeof(uint64_t)); // last write +} + +void pico_sha256_finish(pico_sha256_state_t *state, sha256_result_t *out) { + assert(state->locked); + // pass NULL to abandon the current hash in case of an error + if (out) { + write_padding(state); + if (state->channel >= 0) { + dma_channel_wait_for_finish_blocking(state->channel); + assert(!sha256_err_not_ready()); + } + sha256_wait_valid_blocking(); + sha256_get_result(out, state->endianness); + } + if (state->channel >= 0) { + dma_channel_cleanup(state->channel); + dma_channel_unclaim(state->channel); + state->channel = -1; + } + pico_sha256_unlock(state); +} diff --git a/src/rp2_common/pico_standard_binary_info/BUILD.bazel b/src/rp2_common/pico_standard_binary_info/BUILD.bazel new file mode 100644 index 000000000..79bcf96ab --- /dev/null +++ b/src/rp2_common/pico_standard_binary_info/BUILD.bazel @@ -0,0 +1,39 @@ +load("//bazel/util:sdk_define.bzl", "pico_sdk_define") +load("//src/common/pico_binary_info:binary_info.bzl", "custom_pico_binary_info") + +package(default_visibility = ["//visibility:public"]) + +# This is exposed so that custom_pico_binary_info targets can find the required +# source files. +filegroup( + name = "binary_info_srcs", + srcs = ["standard_binary_info.c"], +) + +# PICO_BUILD_DEFINE: PICO_CMAKE_BUILD_TYPE, The type of build (e.g. Debug or Release) to embed in binary info, type=string, default=pico, group=build +pico_sdk_define( + name = "PICO_BAZEL_BUILD_TYPE", + # WARNING: The actual define is named after CMake, so that define + # is reused for compatibility. + define_name = "PICO_CMAKE_BUILD_TYPE", + from_flag = "//bazel/config:PICO_BAZEL_BUILD_TYPE", +) + +# With custom_pico_binary_info, it's possible to set binary info globally or +# on a per-binary basis. +# +# Setting globally: +# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_BINARY_INFO to point to your +# custom custom_pico_binary_info. +# +# Setting per-binary: +# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_BINARY_INFO=@pico-sdk//bazel:empty_cc_lib +# * Copy this cc_library, and manually set the values as you wish. +# * Add custom_pico_binary_info to each cc_binary individually. +custom_pico_binary_info( + name = "default_binary_info", + program_description = None, + program_name = None, + program_url = None, + program_version_string = None, +) diff --git a/src/rp2_common/pico_standard_binary_info/CMakeLists.txt b/src/rp2_common/pico_standard_binary_info/CMakeLists.txt new file mode 100644 index 000000000..41c2b1f5d --- /dev/null +++ b/src/rp2_common/pico_standard_binary_info/CMakeLists.txt @@ -0,0 +1,9 @@ +if (NOT TARGET pico_standard_binary_info) + pico_add_library(pico_standard_binary_info) + + target_sources(pico_standard_binary_info INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/standard_binary_info.c + ) + + pico_mirrored_target_link_libraries(pico_standard_binary_info INTERFACE pico_binary_info) +endif() \ No newline at end of file diff --git a/src/rp2_common/pico_standard_binary_info/doc.h b/src/rp2_common/pico_standard_binary_info/doc.h new file mode 100644 index 000000000..e24741ec1 --- /dev/null +++ b/src/rp2_common/pico_standard_binary_info/doc.h @@ -0,0 +1,19 @@ +/** + * \defgroup pico_standard_binary_info pico_standard_binary_info + * \brief Includes default information about the binary that can be displayed by picotool + * + * Information is included only if `PICO_NO_BINARY_INFO` and `PICO_NO_PROGRAM_INFO` are both false. + * + * This library adds the following information to the binary: + * + * * The program name if defined (unless `PICO_NO_BINARY_SIZE=1`). The value is `PICO_PROGRAM_NAME` or `PICO_TARGET_NAME` if the former isn't defined + * * The value of PICO_BOARD (unless `PICO_NO_BI_PICO_BOARD=1`) + * * The SDK version (unless `PICO_NO_BI_SDK_VERSION=1`) + * * The program version string if defined (unless `PICO_NO_BI_PROGRAM_VERSION_STRING=1`). The value is `PICO_PROGRAM_VERSION_STRING`` + * * The program description if defined (unless `PICO_NO_BI_PROGRAM_DESCRIPTION=1`). The value is `PICO_PROGRAM_DESCRIPTION` + * * The program url if defined (unless `PICO_NO_BI_PROGRAM_URL=1`). The value is `PICO_PROGRAM_URL` + * * The boot stage 2 used if any (unless `PICO_NO_BI_BOOT_STAGE2_NAME=1`). The value is `PICO_BOOT_STAGE2_NAME` + * * The program build date (unless `PICO_NO_BI_PROGRAM_BUILD_DATE=1). The value defaults to the C preprocessor value `__DATE__`, but can be overridden with `PICO_PROGRAM_BUILD_DATE`. Note you should do a clean build if you want to be sure this value is up to date. + * * The program build type (unless `PICO_NO_BI_BUILD_TYPE=1`). The value is `PICO_CMAKE_BUILD_TYPE` which comes from the CMake build - e.g. Release, Debug, RelMinSize + * * The binary size (unless `PICO_NO_BI_BINARY_SIZE=1`) + */ diff --git a/src/rp2_common/pico_standard_link/binary_info.c b/src/rp2_common/pico_standard_binary_info/standard_binary_info.c similarity index 74% rename from src/rp2_common/pico_standard_link/binary_info.c rename to src/rp2_common/pico_standard_binary_info/standard_binary_info.c index aa67ac4c5..2ebc33805 100644 --- a/src/rp2_common/pico_standard_link/binary_info.c +++ b/src/rp2_common/pico_standard_binary_info/standard_binary_info.c @@ -7,19 +7,23 @@ #if !PICO_NO_BINARY_INFO && !PICO_NO_PROGRAM_INFO #include "pico/binary_info.h" -#if !PICO_NO_FLASH +#if LIB_PICO_BOOT_STAGE2_HEADERS && !PICO_NO_FLASH #include "boot_stage2/config.h" #endif -// Note we put at most 4 pieces of binary info in the reset section because that's how much spare space we had -// (picked the most common ones)... if there is a link failure because of .reset section overflow then move -// more out. -#define reset_section_attr __attribute__((section(".reset"))) +// Note we put at most 4 pieces of binary info in the binary_info_header section because that's how much spare space we +// have before the vector table in a RAM binary (we use the attribute for the most common ones since the choice is static)... +// if there is a link failure because of .reset section overflow then move more out. +#if PICO_NO_FLASH +#define section_hack_attr __attribute__((section(".binary_info_header"))) +#else +#define section_hack_attr +#endif #if !PICO_NO_FLASH #ifndef PICO_NO_BI_BINARY_SIZE extern char __flash_binary_end; -bi_decl_with_attr(bi_binary_end((intptr_t)&__flash_binary_end), reset_section_attr) +bi_decl_with_attr(bi_binary_end((intptr_t)&__flash_binary_end), section_hack_attr) #endif #endif @@ -27,7 +31,7 @@ bi_decl_with_attr(bi_binary_end((intptr_t)&__flash_binary_end), reset_section_at #ifndef PICO_PROGRAM_BUILD_DATE #define PICO_PROGRAM_BUILD_DATE __DATE__ #endif -bi_decl_with_attr(bi_program_build_date_string(PICO_PROGRAM_BUILD_DATE), reset_section_attr); +bi_decl_with_attr(bi_program_build_date_string(PICO_PROGRAM_BUILD_DATE), section_hack_attr); #endif #if !PICO_NO_BI_PROGRAM_NAME @@ -35,7 +39,7 @@ bi_decl_with_attr(bi_program_build_date_string(PICO_PROGRAM_BUILD_DATE), reset_s #define PICO_PROGRAM_NAME PICO_TARGET_NAME #endif #ifdef PICO_PROGRAM_NAME -bi_decl_with_attr(bi_program_name(PICO_PROGRAM_NAME), reset_section_attr) +bi_decl_with_attr(bi_program_name(PICO_PROGRAM_NAME), section_hack_attr) #endif #endif @@ -47,7 +51,7 @@ bi_decl(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PICO_BOARD, PI #if !PICO_NO_BI_SDK_VERSION #ifdef PICO_SDK_VERSION_STRING -bi_decl_with_attr(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_SDK_VERSION, PICO_SDK_VERSION_STRING),reset_section_attr) +bi_decl_with_attr(bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_SDK_VERSION, PICO_SDK_VERSION_STRING), section_hack_attr) #endif #endif @@ -57,7 +61,6 @@ bi_decl(bi_program_version_string(PICO_PROGRAM_VERSION_STRING)) #endif #endif - #if !PICO_NO_BI_PROGRAM_DESCRIPTION #ifdef PICO_PROGRAM_DESCRIPTION bi_decl(bi_program_description(PICO_PROGRAM_DESCRIPTION)) diff --git a/src/rp2_common/pico_standard_link/BUILD.bazel b/src/rp2_common/pico_standard_link/BUILD.bazel index 536909e66..d2449f5d1 100644 --- a/src/rp2_common/pico_standard_link/BUILD.bazel +++ b/src/rp2_common/pico_standard_link/BUILD.bazel @@ -1,105 +1,42 @@ load("//bazel:defs.bzl", "compatible_with_rp2") -load("//bazel/util:sdk_define.bzl", "pico_sdk_define") -load("//src/common/pico_binary_info:binary_info.bzl", "custom_pico_binary_info") +load("pico_flash_region.bzl", "generated_pico_flash_region") package(default_visibility = ["//visibility:public"]) -# This is exposed so that custom_pico_binary_info targets can find the required -# source files. -filegroup( - name = "binary_info_srcs", - srcs = ["binary_info.c"], -) - -# PICO_BUILD_DEFINE: PICO_CXX_ENABLE_EXCEPTIONS, value of CMake var PICO_CXX_ENABLE_EXCEPTIONS, type=string, default=0, group=pico_cxx_options -pico_sdk_define( - name = "PICO_CXX_ENABLE_EXCEPTIONS", - define_name = "PICO_CXX_ENABLE_EXCEPTIONS", - from_flag = "//bazel/config:PICO_CXX_ENABLE_EXCEPTIONS", -) - -# PICO_BUILD_DEFINE: PICO_CMAKE_BUILD_TYPE, The type of build (e.g. Debug or Release) to embed in binary info, type=string, default=pico, group=build -pico_sdk_define( - name = "PICO_BAZEL_BUILD_TYPE", - # WARNING: The actual define is named after CMake, so that define - # is reused for compatibility. - define_name = "PICO_CMAKE_BUILD_TYPE", - from_flag = "//bazel/config:PICO_BAZEL_BUILD_TYPE", -) - -# With custom_pico_binary_info, it's possible to set binary info globally or -# on a per-binary basis. -# -# Setting globally: -# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_BINARY_INFO to point to your -# custom custom_pico_binary_info. -# -# Setting per-binary: -# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_BINARY_INFO=@pico-sdk//bazel:empty_cc_lib -# * Copy this cc_library, and manually set the values as you wish. -# * Add custom_pico_binary_info to each cc_binary individually. -custom_pico_binary_info( - name = "default_binary_info", - program_description = None, - program_name = None, - program_url = None, - program_version_string = None, -) - -# It's possible to set linker scripts globally or on a per-binary basis. +# This produces a small fragment of a linker script that is INCLUDEed from +# the other linker scripts. For example: # -# Setting globally: -# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_LINKER_SCRIPT to point to your -# desired linker script. +# FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 4194304 # -# Setting per-binary: -# * Set --@pico-sdk//bazel/config:PICO_DEFAULT_LINKER_SCRIPT=@pico-sdk//bazel:empty_cc_lib -# * Manually add your desired linker script to each cc_binary. -cc_library( - name = "default_linker_script", - linkopts = ["-T$(location memmap_default.ld)"], - deps = ["memmap_default.ld"], -) - -# PICO_BUILD_DEFINE: PICO_USE_BLOCKED_RAM, whether this is a 'blocked_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link -cc_library( - name = "blocked_ram_linker_script", - defines = ["PICO_USE_BLOCKED_RAM=1"], - linkopts = ["-T$(location memmap_blocked_ram.ld)"], - deps = ["memmap_blocked_ram.ld"], -) - -# PICO_BUILD_DEFINE: PICO_COPY_TO_RAM, whether this is a 'copy_to_ram' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link -cc_library( - name = "copy_to_ram_linker_script", - defines = ["PICO_COPY_TO_RAM=1"], - linkopts = ["-T$(location memmap_copy_to_ram.ld)"], - deps = ["memmap_copy_to_ram.ld"], -) - -# PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link -cc_library( - name = "no_flash_linker_script", - defines = ["PICO_NO_FLASH=1"], - linkopts = ["-T$(location memmap_no_flash.ld)"], - deps = ["memmap_no_flash.ld"], +# TODO: Make this a configurable flag. +generated_pico_flash_region( + name = "default_flash_region", + flash_region_size = select({ + "//bazel/constraint:rp2350": 4 * 1024 * 1024, + "//conditions:default": 2 * 1024 * 1024, + }), ) cc_library( name = "pico_standard_link", - srcs = [ - "crt0.S", - "new_delete.cpp", - ], target_compatible_with = compatible_with_rp2(), - deps = [ - ":PICO_CXX_ENABLE_EXCEPTIONS", - "//bazel/config:PICO_DEFAULT_BINARY_INFO", - "//bazel/config:PICO_DEFAULT_LINKER_SCRIPT", - "//src/common/pico_base:pico_base_interface", - "//src/rp2_common/cmsis:cmsis_core", - "//src/rp2_common/pico_bootrom", - "//src/rp2_common/pico_platform", - "//src/rp2_common/pico_platform:hardware_regs", - ], + deps = select({ + # When PICO_BARE_METAL is enabled, don't automagically add link-time + # dependencies. + "//bazel/constraint:pico_baremetal_enabled": [], + "//conditions:default": [ + "//bazel/config:PICO_BOOT_STAGE2_LINK_IMAGE", + "//bazel/config:PICO_CMSIS_PATH", + "//bazel/config:PICO_DEFAULT_BINARY_INFO", + "//bazel/config:PICO_DEFAULT_LINKER_SCRIPT", + "//src/rp2_common/pico_bit_ops", + "//src/rp2_common/pico_bootrom", + "//src/rp2_common/pico_clib_interface:pico_clib_interface_link", + "//src/rp2_common/pico_crt0", + "//src/rp2_common/pico_cxx_options:PICO_CXX_ENABLE_EXCEPTIONS", + "//src/rp2_common/pico_mem_ops", + "//src/rp2_common/pico_runtime:pico_runtime_link", + "//src/rp2_common/pico_runtime_init:pico_runtime_init_link", + ], + }), ) diff --git a/src/rp2_common/pico_standard_link/CMakeLists.txt b/src/rp2_common/pico_standard_link/CMakeLists.txt index 432ae356c..a428eb69d 100644 --- a/src/rp2_common/pico_standard_link/CMakeLists.txt +++ b/src/rp2_common/pico_standard_link/CMakeLists.txt @@ -1,21 +1,9 @@ if (NOT TARGET pico_standard_link) pico_add_library(pico_standard_link) - target_sources(pico_standard_link INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/crt0.S - ${CMAKE_CURRENT_LIST_DIR}/new_delete.cpp - ${CMAKE_CURRENT_LIST_DIR}/binary_info.c - ) - - pico_add_map_output(pico_standard_link) - - # todo revisit when we do Clang - if (PICO_C_COMPILER_IS_CLANG) -# target_link_options(pico_standard_link INTERFACE "LINKER:-fuse-ld=lld") - endif () - - pico_mirrored_target_link_libraries(pico_standard_link INTERFACE hardware_regs pico_bootrom pico_binary_info) - target_link_libraries(pico_standard_link INTERFACE pico_cxx_options boot_stage2_headers) + if (TARGET boot_stage2_headers) + target_link_libraries(pico_standard_link INTERFACE boot_stage2_headers) + endif() function(pico_add_link_depend TARGET dependency) get_target_property(target_type ${TARGET} TYPE) @@ -36,28 +24,51 @@ if (NOT TARGET pico_standard_link) # need this because cmake does not appear to have a way to override an INTERFACE variable function(pico_set_linker_script TARGET LDSCRIPT) set_target_properties(${TARGET} PROPERTIES PICO_TARGET_LINKER_SCRIPT ${LDSCRIPT}) - pico_add_link_depend(${TARGET} ${LDSCRIPT}) endfunction() function(pico_set_binary_type TARGET TYPE) set_target_properties(${TARGET} PROPERTIES PICO_TARGET_BINARY_TYPE ${TYPE}) endfunction() - if (PICO_NO_FLASH) - set(PICO_DEFAULT_BINARY_TYPE no_flash) - elseif (PICO_USE_BLOCKED_RAM) - set(PICO_DEFAULT_BINARY_TYPE blocked_ram) - elseif (PICO_COPY_TO_RAM) - set(PICO_DEFAULT_BINARY_TYPE copy_to_ram) - else() - set(PICO_DEFAULT_BINARY_TYPE default) + if (NOT PICO_DEFAULT_BINARY_TYPE) + if (PICO_NO_FLASH) + set(PICO_DEFAULT_BINARY_TYPE no_flash) + elseif (PICO_USE_BLOCKED_RAM) + set(PICO_DEFAULT_BINARY_TYPE blocked_ram) + elseif (PICO_COPY_TO_RAM) + set(PICO_DEFAULT_BINARY_TYPE copy_to_ram) + else() + set(PICO_DEFAULT_BINARY_TYPE default) + endif() + endif() + + # todo only needed if not using a custom linker script + if (NOT PICO_LINKER_SCRIPT_PATH) + set(PICO_LINKER_SCRIPT_PATH "THIS_IS_THE_UNSET_PICO_LINKER_SCRIPT_PATH") + endif() + # configure the flash size in pico_flash_region.ld + if (NOT PICO_FLASH_SIZE_BYTES) + if (PICO_DEFAULT_FLASH_SIZE_BYTES) + set(PICO_FLASH_SIZE_BYTES ${PICO_DEFAULT_FLASH_SIZE_BYTES}) + else() + set(PICO_FLASH_SIZE_BYTES "2 * 1024 * 1024") + endif() endif() + # since linker script can handle expressions; may as well leave it as one + #math(EXPR PICO_FLASH_SIZE_BYTES_STRING "${PICO_FLASH_SIZE_BYTES}" OUTPUT_FORMAT HEXADECIMAL) + set(PICO_FLASH_SIZE_BYTES_STRING "${PICO_FLASH_SIZE_BYTES}") + configure_file(${CMAKE_CURRENT_LIST_DIR}/pico_flash_region.template.ld ${CMAKE_BINARY_DIR}/pico_flash_region.ld) + # add include path for linker scripts + target_link_options(pico_standard_link INTERFACE "LINKER:-L${CMAKE_BINARY_DIR}") # LINKER script will be PICO_TARGET_LINKER_SCRIPT if set on target, or ${CMAKE_CURRENT_LIST_DIR}/memmap_foo.ld # if PICO_TARGET_BINARY_TYPE is set to foo on the target, otherwise ${CMAKE_CURRENT_LIST_DIR}/memmap_${PICO_DEFAULT_BINARY_TYPE).ld + set(_LINKER_SCRIPT_EXPRESSION "$>,$,${PICO_LINKER_SCRIPT_PATH}/memmap_$,>,${PICO_DEFAULT_BINARY_TYPE},$>.ld>") target_link_options(pico_standard_link INTERFACE - "LINKER:--script=$>,$,${CMAKE_CURRENT_LIST_DIR}/memmap_$,>,${PICO_DEFAULT_BINARY_TYPE},$>.ld>" - ) + "LINKER:--script=${_LINKER_SCRIPT_EXPRESSION}" + ) + pico_add_link_depend(pico_standard_link ${_LINKER_SCRIPT_EXPRESSION}) + unset(_LINKER_SCRIPT_EXPRESSION) # PICO_NO_FLASH will be set based on PICO_TARGET_BUILD_TYPE target property being equal to no_flash if set, otherwise to the value of the PICO_NO_FLASH cmake variable unless PICO_TARGET_TYPE is set to something else # PICO_BUILD_DEFINE: PICO_NO_FLASH, whether this is a 'no_flash' build, type=bool, default=0, but dependent on CMake options, group=pico_standard_link @@ -77,8 +88,10 @@ if (NOT TARGET pico_standard_link) # this (arguably wrong) code is restored for 1.5.1 as setting -nostartfiles on many C++ binaries causes link errors. see issue #1368 # -nostartfiles will be added if PICO_NO_FLASH would be defined to 1 target_link_options(pico_standard_link INTERFACE $<$,no_flash>,1,$,$>>>:-nostartfiles>) - # boot_stage2 will be linked if PICO_NO_FLASH would be defined to 0 - target_link_libraries(pico_standard_link INTERFACE $<$,no_flash>,1,$,$>>>>:$>,$,bs2_default>_library>) + # boot_stage2 will be linked if PICO_NO_FLASH would be defined to 0; note if boot_stage2 headers not present, then boot_stage2 is omitted from build anyway + if (TARGET boot_stage2_headers) + target_link_libraries(pico_standard_link INTERFACE $<$,no_flash>,1,$,$>>>>:$>,$,bs2_default>_library>) + endif() # PICO_CMAKE_CONFIG: PICO_USE_DEFAULT_MAX_PAGE_SIZE, Don't shrink linker max page to 4096, type=bool, default=0, advanced=true, group=pico_standard_link if (NOT PICO_USE_DEFAULT_MAX_PAGE_SIZE) @@ -90,7 +103,7 @@ if (NOT TARGET pico_standard_link) # this line occasionally useful for debugging ... todo maybe make a PICO_ var # target_compile_options(pico_standard_link INTERFACE --save-temps) #debugging only - # PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable -ffunction-sections -fdata-sections and --gc-sections, type=bool, default=0, advanced=true, group=pico_standard_link + # PICO_CMAKE_CONFIG: PICO_NO_GC_SECTIONS, Disable `-ffunction-sections` `-fdata-sections` and `--gc-sections`, type=bool, default=0, advanced=true, group=pico_standard_link if (NOT PICO_NO_GC_SECTIONS) target_compile_options(pico_standard_link INTERFACE -ffunction-sections -fdata-sections) target_link_options(pico_standard_link INTERFACE "LINKER:--gc-sections") diff --git a/src/rp2_common/pico_standard_link/doc.h b/src/rp2_common/pico_standard_link/doc.h index d8ce3d490..b413fb382 100644 --- a/src/rp2_common/pico_standard_link/doc.h +++ b/src/rp2_common/pico_standard_link/doc.h @@ -1,6 +1,6 @@ /** * \defgroup pico_standard_link pico_standard_link - * \brief Standard link step providing the basics for creating a runnable binary + * \brief Setup for link options for a standard SDK executable * * This includes * - C runtime initialization diff --git a/src/rp2_common/pico_standard_link/pico_flash_region.bzl b/src/rp2_common/pico_standard_link/pico_flash_region.bzl new file mode 100644 index 000000000..3d1e5c468 --- /dev/null +++ b/src/rp2_common/pico_standard_link/pico_flash_region.bzl @@ -0,0 +1,32 @@ +load("@bazel_tools//tools/cpp:toolchain_utils.bzl", "use_cpp_toolchain") + +def _generated_pico_flash_region_impl(ctx): + flash_region_linker_fragment = ctx.actions.declare_file(ctx.label.name + "/ldinclude/pico_flash_region.ld") + link_include_dir = flash_region_linker_fragment.dirname + + file_contents = "\n".join(( + "FLASH(rx) : ORIGIN = 0x10000000, LENGTH = " + str(ctx.attr.flash_region_size), + )) + ctx.actions.write(flash_region_linker_fragment, file_contents) + linking_inputs = cc_common.create_linker_input( + owner = ctx.label, + user_link_flags = depset( + direct = ["-L" + str(link_include_dir)], + ), + additional_inputs = depset( + direct = [flash_region_linker_fragment], + ), + ) + return [ + DefaultInfo(files = depset([flash_region_linker_fragment])), + CcInfo(linking_context = cc_common.create_linking_context(linker_inputs = depset(direct = [linking_inputs]))), + ] + +generated_pico_flash_region = rule( + implementation = _generated_pico_flash_region_impl, + attrs = { + "flash_region_size": attr.int(mandatory = True), + }, + toolchains = use_cpp_toolchain(), + fragments = ["cpp"], +) diff --git a/src/rp2_common/pico_standard_link/pico_flash_region.template.ld b/src/rp2_common/pico_standard_link/pico_flash_region.template.ld new file mode 100644 index 000000000..123bd56c2 --- /dev/null +++ b/src/rp2_common/pico_standard_link/pico_flash_region.template.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = ${PICO_FLASH_SIZE_BYTES_STRING} \ No newline at end of file diff --git a/src/rp2_common/pico_stdio/BUILD.bazel b/src/rp2_common/pico_stdio/BUILD.bazel index 1bc967f22..3aeed0f1e 100644 --- a/src/rp2_common/pico_stdio/BUILD.bazel +++ b/src/rp2_common/pico_stdio/BUILD.bazel @@ -1,35 +1,7 @@ load("//bazel:defs.bzl", "compatible_with_rp2") -load("//bazel/util:sdk_define.bzl", "pico_sdk_define") package(default_visibility = ["//visibility:public"]) -pico_sdk_define( - name = "LIB_PICO_STDIO_UART", - define_name = "LIB_PICO_STDIO_UART", - from_flag = "//bazel/config:PICO_STDIO_UART", -) - -pico_sdk_define( - name = "LIB_PICO_STDIO_USB", - define_name = "LIB_PICO_STDIO_USB", - from_flag = "//bazel/config:PICO_STDIO_USB", -) - -pico_sdk_define( - name = "LIB_PICO_STDIO_SEMIHOSTING", - define_name = "LIB_PICO_STDIO_SEMIHOSTING", - from_flag = "//bazel/config:PICO_STDIO_SEMIHOSTING", -) - -cc_library( - name = "stdio_defines", - deps = [ - ":LIB_PICO_STDIO_SEMIHOSTING", - ":LIB_PICO_STDIO_UART", - ":LIB_PICO_STDIO_USB", - ], -) - # This exists to break dependency cycles between # this library and the stdio implementations. # Application code should always use :pico_stdio instead. @@ -39,25 +11,28 @@ cc_library( "include/pico/stdio.h", "include/pico/stdio/driver.h", ], + defines = ["LIB_PICO_STDIO=1"], includes = ["include"], target_compatible_with = compatible_with_rp2(), visibility = [ + "//src/rp2_common/pico_clib_interface:__pkg__", + "//src/rp2_common/pico_stdio_rtt:__pkg__", "//src/rp2_common/pico_stdio_semihosting:__pkg__", "//src/rp2_common/pico_stdio_uart:__pkg__", "//src/rp2_common/pico_stdio_usb:__pkg__", "//src/rp2_common/tinyusb:__pkg__", ], - deps = [":stdio_defines"], + # Ensure these defines are always present. + deps = [ + "//src/rp2_common/pico_stdio_semihosting:LIB_PICO_STDIO_SEMIHOSTING", + "//src/rp2_common/pico_stdio_uart:LIB_PICO_STDIO_UART", + "//src/rp2_common/pico_stdio_usb:LIB_PICO_STDIO_USB", + ], ) cc_library( name = "pico_stdio", srcs = ["stdio.c"], - hdrs = [ - "include/pico/stdio.h", - "include/pico/stdio/driver.h", - ], - includes = ["include"], linkopts = [ "-Wl,--wrap=printf", "-Wl,--wrap=vprintf", @@ -67,20 +42,17 @@ cc_library( ], target_compatible_with = compatible_with_rp2(), deps = [ - ":stdio_defines", - "//src/common/pico_base", + ":pico_stdio_headers", "//src/common/pico_sync", "//src/common/pico_time", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_printf", - ] + select({ - "//bazel/constraint:pico_stdio_semihosting_enabled": ["//src/rp2_common/pico_stdio_semihosting"], - "//conditions:default": [], - }) + select({ - "//bazel/constraint:pico_stdio_uart_enabled": ["//src/rp2_common/pico_stdio_uart"], - "//conditions:default": [], - }) + select({ - "//bazel/constraint:pico_stdio_usb_enabled": ["//src/rp2_common/pico_stdio_usb"], - "//conditions:default": [], - }), + "//src/rp2_common/pico_stdio_semihosting", + "//src/rp2_common/pico_stdio_semihosting:LIB_PICO_STDIO_SEMIHOSTING", + "//src/rp2_common/pico_stdio_uart", + "//src/rp2_common/pico_stdio_uart:LIB_PICO_STDIO_UART", + "//src/rp2_common/pico_stdio_usb", + "//src/rp2_common/pico_stdio_usb:LIB_PICO_STDIO_USB", + ], alwayslink = True, # Ensures the wrapped symbols are linked in. ) diff --git a/src/rp2_common/pico_stdio/CMakeLists.txt b/src/rp2_common/pico_stdio/CMakeLists.txt index 831f58d75..5798b8d24 100644 --- a/src/rp2_common/pico_stdio/CMakeLists.txt +++ b/src/rp2_common/pico_stdio/CMakeLists.txt @@ -1,14 +1,23 @@ +# PICO_CMAKE_CONFIG: PICO_STDIO_UART, Option to globally enable stdio UART for all targets by default, type=bool, default=1, group=pico_stdlib +option(PICO_STDIO_UART "Globally enable stdio UART" 1) +# PICO_CMAKE_CONFIG: PICO_STDIO_USB, Option to globally enable stdio USB for all targets by default, type=bool, default=0, group=pico_stdlib +option(PICO_STDIO_USB "Globally enable stdio USB" 0) +# PICO_CMAKE_CONFIG: PICO_STDIO_SEMIHOSTING, Option to globally enable stdio semi-hosting for all targets by default, type=bool, default=0, group=pico_stdlib +option(PICO_STDIO_SEMIHOSTING "Globally enable stdio semi-hosting" 0) +# PICO_CMAKE_CONFIG: PICO_STDIO_RTT, Option to globally enable stdio RTT for all targets by default, type=bool, default=0, group=pico_stdlib +option(PICO_STDIO_RTT "Globally enable stdio RTT" 0) + if (NOT TARGET pico_stdio) pico_add_library(pico_stdio) - target_include_directories(pico_stdio_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + target_include_directories(pico_stdio_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_sources(pico_stdio INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdio.c ) - pico_wrap_function(pico_stdio printf) - pico_wrap_function(pico_stdio vprintf) + pico_wrap_function(pico_stdio printf) # here not pico_printf as we do mutex + pico_wrap_function(pico_stdio vprintf) # here not pico_printf as we do mutex pico_wrap_function(pico_stdio puts) pico_wrap_function(pico_stdio putchar) pico_wrap_function(pico_stdio getchar) @@ -16,4 +25,41 @@ if (NOT TARGET pico_stdio) if (TARGET pico_printf) pico_mirrored_target_link_libraries(pico_stdio INTERFACE pico_printf) endif() + + function(pico_enable_stdio_uart TARGET ENABLED) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_UART ${ENABLED}) + endfunction() + + function(pico_enable_stdio_usb TARGET ENABLED) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_USB ${ENABLED}) + endfunction() + + function(pico_enable_stdio_semihosting TARGET ENABLED) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_SEMIHOSTING ${ENABLED}) + endfunction() + + function(pico_enable_stdio_rtt TARGET ENABLED) + set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_RTT ${ENABLED}) + endfunction() + + if (TARGET pico_stdio_uart) + target_link_libraries(pico_stdio INTERFACE $,>,${PICO_STDIO_UART},$>>,pico_stdio_uart,>) + target_link_libraries(pico_stdio_headers INTERFACE $,>,${PICO_STDIO_UART},$>>,pico_stdio_uart_headers,>) + endif() + + if (TARGET pico_stdio_usb) + target_link_libraries(pico_stdio INTERFACE $,>,${PICO_STDIO_USB},$>>,pico_stdio_usb,>) + target_link_libraries(pico_stdio_headers INTERFACE $,>,${PICO_STDIO_USB},$>>,pico_stdio_usb_headers,>) + endif() + + if (TARGET pico_stdio_semihosting) + target_link_libraries(pico_stdio INTERFACE $,>,${PICO_STDIO_SEMIHOSTING},$>>,pico_stdio_semihosting,>) + target_link_libraries(pico_stdio_headers INTERFACE $,>,${PICO_STDIO_SEMIHOSTING},$>>,pico_stdio_semihosting_headers,>) + endif() + + if (TARGET pico_stdio_rtt) + target_link_libraries(pico_stdio INTERFACE $,>,${PICO_STDIO_RTT},$>>,pico_stdio_rtt,>) + target_link_libraries(pico_stdio_headers INTERFACE $,>,${PICO_STDIO_RTT},$>>,pico_stdio_rtt_headers,>) + endif() + endif() \ No newline at end of file diff --git a/src/rp2_common/pico_stdio/include/pico/stdio.h b/src/rp2_common/pico_stdio/include/pico/stdio.h index 3b8e60379..cba3b27c4 100644 --- a/src/rp2_common/pico_stdio/include/pico/stdio.h +++ b/src/rp2_common/pico_stdio/include/pico/stdio.h @@ -9,7 +9,7 @@ /** \file stdio.h * \defgroup pico_stdio pico_stdio -* \brief Customized stdio support allowing for input and output from UART, USB, semi-hosting etc. +* \brief Customized stdio support allowing for input and output from UART, USB, semi-hosting etc * * Note the API for adding additional input output devices is not yet considered stable */ @@ -41,10 +41,16 @@ #define PICO_STDIO_DEADLOCK_TIMEOUT_MS 1000 #endif +// PICO_CONFIG: PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS, Directly replace common stdio functions such as putchar from the C-library to avoid pulling in lots of c library code for simple output, type=bool, default=1, advanced=true, group=pico_stdio +#ifndef PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS +#define PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS 1 +#endif + #ifdef __cplusplus extern "C" { #endif +#include typedef struct stdio_driver stdio_driver_t; @@ -62,6 +68,16 @@ typedef struct stdio_driver stdio_driver_t; */ bool stdio_init_all(void); +/*! \brief Deinitialize all of the present standard stdio types that are linked into the binary. + * \ingroup pico_stdio + * + * This method currently only supports stdio_uart and stdio_semihosting + * + * \return true if all outputs was successfully deinitialized, false otherwise. + * \see stdio_uart, stdio_usb, stdio_semihosting, stdio_rtt + */ +bool stdio_deinit_all(void); + /*! \brief Flushes any buffered output. * \ingroup pico_stdio */ @@ -73,7 +89,14 @@ void stdio_flush(void); * \param timeout_us the timeout in microseconds, or 0 to not wait for a character if none available. * \return the character from 0-255 or PICO_ERROR_TIMEOUT if timeout occurs */ -int getchar_timeout_us(uint32_t timeout_us); +int stdio_getchar_timeout_us(uint32_t timeout_us); + +/*! \brief Alias for \ref stdio_getchar_timeout_us for backwards compatibility + * \ingroup pico_stdio + */ +static inline int getchar_timeout_us(uint32_t timeout_us) { + return stdio_getchar_timeout_us(timeout_us); +} /*! \brief Adds or removes a driver from the list of active drivers used for input/output * \ingroup pico_stdio @@ -107,12 +130,26 @@ void stdio_set_translate_crlf(stdio_driver_t *driver, bool translate); /*! \brief putchar variant that skips any CR/LF conversion if enabled * \ingroup pico_stdio */ -int putchar_raw(int c); +int stdio_putchar_raw(int c); + +/*! \brief Alias for \ref stdio_putchar_raw for backwards compatibility + * \ingroup pico_stdio + */ +static inline int putchar_raw(int c) { + return stdio_putchar_raw(c); +} /*! \brief puts variant that skips any CR/LF conversion if enabled * \ingroup pico_stdio */ -int puts_raw(const char *s); +int stdio_puts_raw(const char *s); + +/*! \brief Alias for \ref stdio_puts_raw for backwards compatibility + * \ingroup pico_stdio + */ +static inline int puts_raw(const char *s) { + return stdio_puts_raw(s); +} /*! \brief get notified when there are input characters available * \ingroup pico_stdio @@ -122,6 +159,68 @@ int puts_raw(const char *s); */ void stdio_set_chars_available_callback(void (*fn)(void*), void *param); +/*! \brief Waits until a timeout to reard at least one character into a buffer + * \ingroup pico_stdio + * + * This method returns as soon as input is available, but more characters may + * be returned up to the end of the buffer. + * + * \param buf the buffer to read into + * \param len the length of the buffer + * \return the number of characters read or PICO_ERROR_TIMEOUT + * \param until the time after which to return PICO_ERROR_TIMEOUT if no characters are available + */ +int stdio_get_until(char *buf, int len, absolute_time_t until); + +/*! \brief Prints a buffer to stdout with optional newline and carriage return insertion + * \ingroup pico_stdio + * + * This method returns as soon as input is available, but more characters may + * be returned up to the end of the buffer. + * + * \param s the characters to print + * \param len the length of s + * \param newline true if a newline should be added after the string + * \param cr_translation true if line feed to carriage return translation should be performed + * \return the number of characters written + */ +int stdio_put_string(const char *s, int len, bool newline, bool cr_translation); + +/*! \brief stdio_getchar Alias for \ref getchar that definitely does not go thru the implementation + * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 + * + * \ingroup pico_stdio + */ +int stdio_getchar(void); + +/*! \brief stdio_getchar Alias for \ref putchar that definitely does not go thru the implementation + * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 + * + * \ingroup pico_stdio + */ +int stdio_putchar(int); + +/*! \brief stdio_getchar Alias for \ref puts that definitely does not go thru the implementation + * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 + * + * \ingroup pico_stdio + */ +int stdio_puts(const char *s); + +/*! \brief stdio_getchar Alias for \ref vprintf that definitely does not go thru the implementation + * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 + * + * \ingroup pico_stdio + */ +int stdio_vprintf(const char *format, va_list va); + +/*! \brief stdio_getchar Alias for \ref printf that definitely does not go thru the implementation + * in the standard C library even when \ref PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS == 0 + * + * \ingroup pico_stdio + */ +int __printflike(1, 0) stdio_printf(const char* format, ...); + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/pico_stdio/stdio.c b/src/rp2_common/pico_stdio/stdio.c index 1c7040692..d2ce14556 100644 --- a/src/rp2_common/pico_stdio/stdio.c +++ b/src/rp2_common/pico_stdio/stdio.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "pico.h" #if LIB_PICO_PRINTF_PICO @@ -36,10 +35,6 @@ #include "pico/stdio_rtt.h" #endif -#define STDIO_HANDLE_STDIN 0 -#define STDIO_HANDLE_STDOUT 1 -#define STDIO_HANDLE_STDERR 2 - static stdio_driver_t *drivers; static stdio_driver_t *filter; @@ -94,15 +89,15 @@ static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) #endif } -static bool stdio_put_string(const char *s, int len, bool newline, bool no_cr) { +int stdio_put_string(const char *s, int len, bool newline, bool cr_translation) { bool serialized = stdout_serialize_begin(); if (!serialized) { #if PICO_STDIO_IGNORE_NESTED_STDOUT - return false; + return 0; #endif } if (len == -1) len = (int)strlen(s); - void (*out_func)(stdio_driver_t *, const char *, int) = no_cr ? stdio_out_chars_no_crlf : stdio_out_chars_crlf; + void (*out_func)(stdio_driver_t *, const char *, int) = cr_translation ? stdio_out_chars_crlf : stdio_out_chars_no_crlf; for (stdio_driver_t *driver = drivers; driver; driver = driver->next) { if (!driver->out_chars) continue; if (filter && filter != driver) continue; @@ -118,7 +113,7 @@ static bool stdio_put_string(const char *s, int len, bool newline, bool no_cr) { return len; } -static int stdio_get_until(char *buf, int len, absolute_time_t until) { +int stdio_get_until(char *buf, int len, absolute_time_t until) { do { // todo round robin might be nice on each call, but then again hopefully // no source will starve the others @@ -140,67 +135,19 @@ static int stdio_get_until(char *buf, int len, absolute_time_t until) { } while (true); } -int WRAPPER_FUNC(putchar)(int c) { +int stdio_putchar_raw(int c) { char cc = (char)c; stdio_put_string(&cc, 1, false, false); return c; } -int WRAPPER_FUNC(puts)(const char *s) { +int stdio_puts_raw(const char *s) { int len = (int)strlen(s); stdio_put_string(s, len, true, false); stdio_flush(); return len; } -int putchar_raw(int c) { - char cc = (char)c; - stdio_put_string(&cc, 1, false, true); - return c; -} - -int puts_raw(const char *s) { - int len = (int)strlen(s); - stdio_put_string(s, len, true, true); - stdio_flush(); - return len; -} - -int __attribute__((weak)) _read(int handle, char *buffer, int length) { - if (handle == STDIO_HANDLE_STDIN) { - return stdio_get_until(buffer, length, at_the_end_of_time); - } - return -1; -} - -int __attribute__((weak)) _write(int handle, char *buffer, int length) { - if (handle == STDIO_HANDLE_STDOUT || handle == STDIO_HANDLE_STDERR) { - stdio_put_string(buffer, length, false, false); - return length; - } - return -1; -} - -int __attribute__((weak)) _open(__unused const char *fn, __unused int oflag, ...) { - return -1; -} - -int __attribute__((weak)) _close(__unused int fd) { - return -1; -} - -off_t __attribute__((weak)) _lseek(__unused int fd, __unused off_t pos, __unused int whence) { - return -1; -} - -int __attribute__((weak)) _fstat(__unused int fd, __unused struct stat *buf) { - return -1; -} - -int __attribute__((weak)) _isatty(int fd) { - return fd == STDIO_HANDLE_STDIN || fd == STDIO_HANDLE_STDOUT || fd == STDIO_HANDLE_STDERR; -} - void stdio_set_driver_enabled(stdio_driver_t *driver, bool enable) { stdio_driver_t **prev = &drivers; while (*prev) { @@ -218,12 +165,13 @@ void stdio_set_driver_enabled(stdio_driver_t *driver, bool enable) { } } -void stdio_flush() { +void stdio_flush(void) { for (stdio_driver_t *d = drivers; d; d = d->next) { if (d->out_flush) d->out_flush(); } } +#if LIB_PICO_PRINTF_PICO typedef struct stdio_stack_buffer { int used; char buf[PICO_STDIO_STACK_BUFFER_SIZE]; @@ -247,42 +195,7 @@ static void stdio_buffered_printer(char c, void *arg) { } buffer->buf[buffer->used++] = c; } - -int WRAPPER_FUNC(vprintf)(const char *format, va_list va) { - bool serialzed = stdout_serialize_begin(); - if (!serialzed) { -#if PICO_STDIO_IGNORE_NESTED_STDOUT - return 0; #endif - } - int ret; -#if LIB_PICO_PRINTF_PICO - struct stdio_stack_buffer buffer; - buffer.used = 0; - ret = vfctprintf(stdio_buffered_printer, &buffer, format, va); - stdio_stack_buffer_flush(&buffer); - stdio_flush(); -#elif LIB_PICO_PRINTF_NONE - extern void printf_none_assert(); - printf_none_assert(); -#else - extern int REAL_FUNC(vprintf)(const char *format, va_list va); - ret = REAL_FUNC(vprintf)(format, va); -#endif - if (serialzed) { - stdout_serialize_end(); - } - return ret; -} - -int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...) -{ - va_list va; - va_start(va, format); - int ret = vprintf(format, va); - va_end(va); - return ret; -} bool stdio_init_all(void) { // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway @@ -310,15 +223,36 @@ bool stdio_init_all(void) { return rc; } -int WRAPPER_FUNC(getchar)(void) { - char buf[1]; - int len = stdio_get_until(buf, 1, at_the_end_of_time); - if (len < 0) return len; - assert(len == 1); - return (uint8_t)buf[0]; +bool stdio_deinit_all(void) { + // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway + // These are well known ones + + // First flush, to make sure everything is printed + stdio_flush(); + + bool rc = false; +#if LIB_PICO_STDIO_UART + stdio_uart_deinit(); + rc = true; +#endif + +#if LIB_PICO_STDIO_SEMIHOSTING + stdio_semihosting_deinit(); + rc = true; +#endif + +#if LIB_PICO_STDIO_RTT + stdio_rtt_deinit(); + rc = true; +#endif + +#if LIB_PICO_STDIO_USB + rc = stdio_usb_deinit(); +#endif + return rc; } -int getchar_timeout_us(uint32_t timeout_us) { +int stdio_getchar_timeout_us(uint32_t timeout_us) { char buf[1]; int rc = stdio_get_until(buf, sizeof(buf), make_timeout_time_us(timeout_us)); if (rc < 0) return rc; @@ -350,3 +284,108 @@ void stdio_set_chars_available_callback(void (*fn)(void*), void *param) { if (s->set_chars_available_callback) s->set_chars_available_callback(fn, param); } } + +#if PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS +#define PRIMARY_STDIO_FUNC(x) WRAPPER_FUNC(x) +#else +#define PRIMARY_STDIO_FUNC(x) stdio_ ## x +#endif + +int PRIMARY_STDIO_FUNC(getchar)(void) { + char buf[1]; + int len = stdio_get_until(buf, 1, at_the_end_of_time); + if (len < 0) return len; + assert(len == 1); + return (uint8_t)buf[0]; +} + +int PRIMARY_STDIO_FUNC(putchar)(int c) { + char cc = (char)c; + stdio_put_string(&cc, 1, false, true); + return c; +} + +int PRIMARY_STDIO_FUNC(puts)(const char *s) { + int len = (int)strlen(s); + stdio_put_string(s, len, true, true); + stdio_flush(); + return len; +} + +int REAL_FUNC(vprintf)(const char *format, va_list va); + +int PRIMARY_STDIO_FUNC(vprintf)(const char *format, va_list va) { + bool serialzed = stdout_serialize_begin(); + if (!serialzed) { +#if PICO_STDIO_IGNORE_NESTED_STDOUT + return 0; +#endif + } + int ret; +#if LIB_PICO_PRINTF_PICO + struct stdio_stack_buffer buffer; + buffer.used = 0; + ret = vfctprintf(stdio_buffered_printer, &buffer, format, va); + stdio_stack_buffer_flush(&buffer); + stdio_flush(); +#elif LIB_PICO_PRINTF_NONE + ((void)format); + ((void)va); + extern void printf_none_assert(void); + printf_none_assert(); + ret = 0; +#else + ret = REAL_FUNC(vprintf)(format, va); +#endif + if (serialzed) { + stdout_serialize_end(); + } + return ret; +} + +int __printflike(1, 0) PRIMARY_STDIO_FUNC(printf)(const char* format, ...) +{ + va_list va; + va_start(va, format); + int ret = vprintf(format, va); + va_end(va); + return ret; +} + +#if PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS +// define the stdio_ versions to be the same as our wrappers +int stdio_getchar(void) __attribute__((alias(__XSTRING(WRAPPER_FUNC(getchar))))); +int stdio_putchar(int) __attribute__((alias(__XSTRING(WRAPPER_FUNC(putchar))))); +int stdio_puts(const char *s) __attribute__((alias(__XSTRING(WRAPPER_FUNC(puts))))); +int stdio_vprintf(const char *format, va_list va) __attribute__((alias(__XSTRING(WRAPPER_FUNC(vprintf))))); +int __printflike(1, 0) stdio_printf(const char* format, ...) __attribute__((alias(__XSTRING(WRAPPER_FUNC(printf))))); +#else +// todo there is no easy way to avoid the wrapper functions since they are in the CMake, so lets just forward for now + +int REAL_FUNC(getchar)(void); +int REAL_FUNC(putchar)(int); +int REAL_FUNC(puts)(const char *s); +int __printflike(1, 0) REAL_FUNC(printf)(const char* format, ...); + +int WRAPPER_FUNC(getchar)(void) { + return REAL_FUNC(getchar)(); +} +int WRAPPER_FUNC(putchar)(int c) { + return REAL_FUNC(putchar)(c); +} +int WRAPPER_FUNC(puts)(const char *s) { + return REAL_FUNC(puts)(s); +} +int WRAPPER_FUNC(vprintf)(const char *format, va_list va) { + return REAL_FUNC(vprintf)(format, va); +} +int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...) { + va_list va; + va_start(va, format); + int ret = REAL_FUNC(vprintf)(format, va); + va_end(va); + return ret; +} +#endif + + diff --git a/src/rp2_common/pico_stdio_rtt/BUILD.bazel b/src/rp2_common/pico_stdio_rtt/BUILD.bazel new file mode 100644 index 000000000..5cec66808 --- /dev/null +++ b/src/rp2_common/pico_stdio_rtt/BUILD.bazel @@ -0,0 +1,64 @@ +load("//bazel:defs.bzl", "compatible_with_config", "compatible_with_rp2", "incompatible_with_config") +load("//bazel/util:sdk_define.bzl", "pico_sdk_define") + +package(default_visibility = ["//visibility:public"]) + +alias( + name = "pico_stdio_rtt", + actual = select({ + "//bazel/constraint:pico_stdio_rtt_enabled": ":pico_stdio_rtt_enabled", + "//conditions:default": ":pico_stdio_rtt_disabled", + }), +) + +pico_sdk_define( + name = "LIB_PICO_STDIO_RTT", + define_name = "LIB_PICO_STDIO_RTT", + from_flag = "//bazel/config:PICO_STDIO_RTT", +) + +cc_library( + name = "pico_stdio_rtt_enabled", + srcs = [ + "SEGGER/RTT/SEGGER_RTT.c", + "stdio_rtt.c", + ], + hdrs = [ + "SEGGER/Config/SEGGER_RTT_Conf.h", + "SEGGER/RTT/SEGGER_RTT.h", + "include/pico/stdio_rtt.h", + ], + includes = [ + "SEGGER/RTT", + "include", + ], + target_compatible_with = compatible_with_rp2() + compatible_with_config( + "//bazel/constraint:pico_stdio_rtt_enabled", + ), + deps = [ + ":LIB_PICO_STDIO_RTT", + "//src/common/pico_binary_info", + "//src/rp2_common/pico_stdio:pico_stdio_headers", + ], +) + +# Stub library that does NOT link in stdio rtt support libs. +cc_library( + name = "pico_stdio_rtt_disabled", + hdrs = [ + "SEGGER/Config/SEGGER_RTT_Conf.h", + "SEGGER/RTT/SEGGER_RTT.h", + "include/pico/stdio_rtt.h", + ], + includes = [ + "SEGGER/RTT", + "include", + ], + target_compatible_with = compatible_with_rp2() + incompatible_with_config( + "//bazel/constraint:pico_stdio_rtt_enabled", + ), + deps = [ + ":LIB_PICO_STDIO_RTT", + "//src/rp2_common/pico_stdio:pico_stdio_headers", + ], +) diff --git a/src/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h b/src/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h index 3fc1759c6..2ed08e25a 100644 --- a/src/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h +++ b/src/rp2_common/pico_stdio_rtt/include/pico/stdio_rtt.h @@ -35,6 +35,13 @@ extern stdio_driver_t stdio_rtt; */ void stdio_rtt_init(void); +/*! \brief Explicitly deinitialize stdin/stdout over RTT and remove it from the current set of stdin/stdout drivers + * \ingroup pico_stdio_rtt + * + * \note this method is automatically called by \ref stdio_deinit_all() if `pico_stdio_rtt` is included in the build + */ +void stdio_rtt_deinit(void); + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/pico_stdio_rtt/stdio_rtt.c b/src/rp2_common/pico_stdio_rtt/stdio_rtt.c index 379289378..2dc75579a 100644 --- a/src/rp2_common/pico_stdio_rtt/stdio_rtt.c +++ b/src/rp2_common/pico_stdio_rtt/stdio_rtt.c @@ -21,6 +21,10 @@ void stdio_rtt_init(void) { stdio_bi_decl_if_func_used(bi_program_feature("RTT stdin / stdout")); } +void stdio_rtt_deinit(void) { + stdio_set_driver_enabled(&stdio_rtt, false); +} + static void stdio_rtt_out_chars(const char *buf, int length) { SEGGER_RTT_Write(0, buf, length); } diff --git a/src/rp2_common/pico_stdio_semihosting/BUILD.bazel b/src/rp2_common/pico_stdio_semihosting/BUILD.bazel index 473e37aef..115f1f0d7 100644 --- a/src/rp2_common/pico_stdio_semihosting/BUILD.bazel +++ b/src/rp2_common/pico_stdio_semihosting/BUILD.bazel @@ -1,15 +1,47 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel:defs.bzl", "compatible_with_config", "compatible_with_rp2", "incompatible_with_config") +load("//bazel/util:sdk_define.bzl", "pico_sdk_define") package(default_visibility = ["//visibility:public"]) -cc_library( +alias( name = "pico_stdio_semihosting", + actual = select({ + "//bazel/constraint:pico_stdio_semihosting_enabled": ":pico_stdio_semihosting_enabled", + "//conditions:default": ":pico_stdio_semihosting_disabled", + }), +) + +pico_sdk_define( + name = "LIB_PICO_STDIO_SEMIHOSTING", + define_name = "LIB_PICO_STDIO_SEMIHOSTING", + from_flag = "//bazel/config:PICO_STDIO_SEMIHOSTING", +) + +cc_library( + name = "pico_stdio_semihosting_enabled", srcs = ["stdio_semihosting.c"], hdrs = ["include/pico/stdio_semihosting.h"], includes = ["include"], - target_compatible_with = compatible_with_rp2(), + target_compatible_with = compatible_with_rp2() + compatible_with_config( + "//bazel/constraint:pico_stdio_semihosting_enabled", + ), deps = [ + ":LIB_PICO_STDIO_SEMIHOSTING", "//src/common/pico_binary_info", "//src/rp2_common/pico_stdio:pico_stdio_headers", ], ) + +# Stub library that does NOT link in stdio semihosting support libs. +cc_library( + name = "pico_stdio_semihosting_disabled", + hdrs = ["include/pico/stdio_semihosting.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2() + incompatible_with_config( + "//bazel/constraint:pico_stdio_semihosting_enabled", + ), + deps = [ + ":LIB_PICO_STDIO_SEMIHOSTING", + "//src/rp2_common/pico_stdio:pico_stdio_headers", + ], +) diff --git a/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt b/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt index 48d3b9230..2ff40b2e9 100644 --- a/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt +++ b/src/rp2_common/pico_stdio_semihosting/CMakeLists.txt @@ -4,6 +4,6 @@ target_sources(pico_stdio_semihosting INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdio_semihosting.c ) -target_include_directories(pico_stdio_semihosting_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_stdio_semihosting_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) -pico_mirrored_target_link_libraries(pico_stdio_semihosting INTERFACE pico_stdio) \ No newline at end of file +pico_mirrored_target_link_libraries(pico_stdio_semihosting INTERFACE pico_stdio) diff --git a/src/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h b/src/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h index ca66417e5..de46997d1 100644 --- a/src/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h +++ b/src/rp2_common/pico_stdio_semihosting/include/pico/stdio_semihosting.h @@ -35,6 +35,13 @@ extern stdio_driver_t stdio_semihosting; */ void stdio_semihosting_init(void); +/*! \brief Explicitly deinitialize stdout over semihosting and add it to the current set of stdout targets + * \ingroup pico_stdio_semihosting + * + * \note this method is automatically called by \ref stdio_deinit_all() if `pico_stdio_semihosting` is included in the build + */ +void stdio_semihosting_deinit(void); + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c b/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c index 7a7910ff6..94c43fc8d 100644 --- a/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c +++ b/src/rp2_common/pico_stdio_semihosting/stdio_semihosting.c @@ -26,15 +26,36 @@ static void stdio_semihosting_out_chars(const char *buf, int length) { args.len = length; pico_default_asm ( - // r1 must contain a pointer to the arguments - "movs r1, %[args]\n" - // semihosting call number 0x05 = SYS_WRITE - "movs r0, #5\n" - // make the semihosting call: https://developer.arm.com/documentation/dui0375/g/What-is-Semihosting-/The-semihosting-interface - "bkpt 0xab\n" - : - : [args] "r" (&args) - : "r0", "r1"); +#ifdef __riscv + // a0 encodes the semihosting call number, 0x05 = SYS_WRITE + "li a0, 0x05\n" + // a1 points to the arguments + "mv a1, %[args]\n" + // Magic three-instruction sequence, containing a breakpoint. Note the + // RISC-V unpriv spec implies the final instruction might encode the + // call number (passed in a1) but openocd source shows this is just a + // constant value of 0x07. These instructions must be uncompressed: + ".option push\n" + ".option norvc\n" + "slli x0, x0, 0x1f\n" + "ebreak\n" + "srai x0, x0, 0x07\n" + ".option pop\n" + : + : [args] "r" (&args) + : "a0", "a1" +#else + // r1 must contain a pointer to the arguments + "movs r1, %[args]\n" + // semihosting call number 0x05 = SYS_WRITE + "movs r0, #5\n" + // make the semihosting call: https://developer.arm.com/documentation/dui0375/g/What-is-Semihosting-/The-semihosting-interface + "bkpt 0xab\n" + : + : [args] "r" (&args) + : "r0", "r1", "cc", "memory" +#endif + ); } stdio_driver_t stdio_semihosting = { @@ -44,10 +65,13 @@ stdio_driver_t stdio_semihosting = { #endif }; -void stdio_semihosting_init() { +void stdio_semihosting_init(void) { #if !PICO_NO_BI_STDIO_SEMIHOSTING bi_decl_if_func_used(bi_program_feature("semihosting stdout")); #endif stdio_set_driver_enabled(&stdio_semihosting, true); } +void stdio_semihosting_deinit(void) { + stdio_set_driver_enabled(&stdio_semihosting, false); +} diff --git a/src/rp2_common/pico_stdio_uart/BUILD.bazel b/src/rp2_common/pico_stdio_uart/BUILD.bazel index c32993540..b178cbaab 100644 --- a/src/rp2_common/pico_stdio_uart/BUILD.bazel +++ b/src/rp2_common/pico_stdio_uart/BUILD.bazel @@ -1,17 +1,46 @@ -load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel:defs.bzl", "compatible_with_config", "compatible_with_rp2", "incompatible_with_config") +load("//bazel/util:sdk_define.bzl", "pico_sdk_define") package(default_visibility = ["//visibility:public"]) -cc_library( +alias( name = "pico_stdio_uart", + actual = select({ + "//bazel/constraint:pico_stdio_uart_enabled": ":pico_stdio_uart_enabled", + "//conditions:default": ":pico_stdio_uart_disabled", + }), +) + +pico_sdk_define( + name = "LIB_PICO_STDIO_UART", + define_name = "LIB_PICO_STDIO_UART", + from_flag = "//bazel/config:PICO_STDIO_UART", +) + +cc_library( + name = "pico_stdio_uart_enabled", srcs = ["stdio_uart.c"], hdrs = ["include/pico/stdio_uart.h"], includes = ["include"], - target_compatible_with = compatible_with_rp2(), + target_compatible_with = compatible_with_rp2() + compatible_with_config("//bazel/constraint:pico_stdio_uart_enabled"), deps = [ + ":LIB_PICO_STDIO_UART", "//src/common/pico_binary_info", "//src/rp2_common/hardware_gpio", "//src/rp2_common/hardware_uart", "//src/rp2_common/pico_stdio:pico_stdio_headers", ], ) + +# Stub library that does NOT link in stdio UART support libs. +cc_library( + name = "pico_stdio_uart_disabled", + hdrs = ["include/pico/stdio_uart.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2() + incompatible_with_config("//bazel/constraint:pico_stdio_uart_enabled"), + deps = [ + ":LIB_PICO_STDIO_UART", + "//src/rp2_common/hardware_uart", + "//src/rp2_common/pico_stdio:pico_stdio_headers", + ], +) diff --git a/src/rp2_common/pico_stdio_uart/CMakeLists.txt b/src/rp2_common/pico_stdio_uart/CMakeLists.txt index 4639b02c5..11d625871 100644 --- a/src/rp2_common/pico_stdio_uart/CMakeLists.txt +++ b/src/rp2_common/pico_stdio_uart/CMakeLists.txt @@ -4,6 +4,6 @@ target_sources(pico_stdio_uart INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdio_uart.c ) -target_include_directories(pico_stdio_uart_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_stdio_uart_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_stdio_uart INTERFACE pico_stdio) \ No newline at end of file diff --git a/src/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h b/src/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h index f3accd623..504837fbc 100644 --- a/src/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h +++ b/src/rp2_common/pico_stdio_uart/include/pico/stdio_uart.h @@ -68,6 +68,39 @@ void stdin_uart_init(void); */ void stdio_uart_init_full(uart_inst_t *uart, uint baud_rate, int tx_pin, int rx_pin); +/*! \brief Explicitly deinitialize stdin/stdout over UART and remove it from the current set of stdin/stdout drivers + * \ingroup pico_stdio_uart + * + * This method disables PICO_DEFAULT_UART_TX_PIN for UART output (if defined), PICO_DEFAULT_UART_RX_PIN for input (if defined) + * and leaves the pads isolated. + * + * \note this method is automatically called by \ref stdio_deinit_all() if `pico_stdio_uart` is included in the build + */ +void stdio_uart_deinit(void); + +/*! \brief Explicitly deinitialize stdout only (no stdin) over UART and remove it from the current set of stdout drivers + * \ingroup pico_stdio_uart + * + * This method disables PICO_DEFAULT_UART_TX_PIN for UART output (if defined), and leaves the pad isolated + */ +void stdout_uart_deinit(void); + +/*! \brief Explicitly deinitialize stdin only (no stdout) over UART and remove it from the current set of stdin drivers + * \ingroup pico_stdio_uart + * + * This method disables PICO_DEFAULT_UART_RX_PIN for UART input (if defined), and leaves the pads isolated + */ +void stdin_uart_deinit(void); + +/*! \brief Perform custom deinitialization deinitialize stdin/stdout over UART and remove it from the current set of stdin/stdout drivers + * \ingroup pico_stdio_uart + * + * \param uart the uart instance to use, \ref uart0 or \ref uart1 + * \param tx_pin the UART pin to use for stdout (or -1 for no stdout) + * \param rx_pin the UART pin to use for stdin (or -1 for no stdin) + */ +void stdio_uart_deinit_full(uart_inst_t *uart, int tx_pin, int rx_pin); + #ifdef __cplusplus } #endif diff --git a/src/rp2_common/pico_stdio_uart/stdio_uart.c b/src/rp2_common/pico_stdio_uart/stdio_uart.c index c77bb4730..620e25d15 100644 --- a/src/rp2_common/pico_stdio_uart/stdio_uart.c +++ b/src/rp2_common/pico_stdio_uart/stdio_uart.c @@ -22,7 +22,19 @@ static void *chars_available_param; #define stdio_bi_decl_if_func_used bi_decl_if_func_used #endif -void stdio_uart_init() { +#ifdef PICO_DEFAULT_UART_TX_PIN +#if (PICO_DEFAULT_UART_TX_PIN & 0x1) || (PICO_RP2040 && (PICO_DEFAULT_UART_TX_PIN & 0x2)) +#error "Specified PICO_DEFAULT_UART_TX_PIN does not support UART TX" +#endif +#endif + +#ifdef PICO_DEFAULT_UART_RX_PIN +#if !(PICO_DEFAULT_UART_RX_PIN & 0x1) || (PICO_RP2040 && (PICO_DEFAULT_UART_TX_PIN & 0x2)) +#error "Specified PICO_DEFAULT_UART_RX_PIN does not support UART RX" +#endif +#endif + +void stdio_uart_init(void) { #ifdef uart_default int tx_pin = -1; int rx_pin = -1; @@ -31,7 +43,12 @@ void stdio_uart_init() { #ifdef PICO_DEFAULT_UART_RX_PIN rx_pin = PICO_DEFAULT_UART_RX_PIN; stdio_bi_decl_if_func_used(bi_program_feature("UART stdin / stdout")); - bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART)); +#if PICO_DEFAULT_UART_TX_PIN == PICO_DEFAULT_UART_RX_PIN + bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, uart_get_funcsel(uart_default, PICO_DEFAULT_UART_RX_PIN))); +#else + bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_TX_PIN))); + bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_RX_PIN))); +#endif #else stdio_bi_decl_if_func_used(bi_program_feature("UART stdout")); bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART)); @@ -49,9 +66,9 @@ void stdio_uart_init() { #endif } -void stdout_uart_init() { +void stdout_uart_init(void) { #if defined(uart_default) && defined(PICO_DEFAULT_UART_TX_PIN) - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART)); + bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_TX_PIN))); #if !defined(PICO_DEFAULT_UART_BAUD_RATE) panic("UART baud rate undefined"); #else @@ -61,9 +78,9 @@ void stdout_uart_init() { #endif } -void stdin_uart_init() { +void stdin_uart_init(void) { #if defined(uart_default) && defined(PICO_DEFAULT_UART_RX_PIN) - bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART)); + bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, UART_FUNCSEL_NUM(uart_default, PICO_DEFAULT_UART_RX_PIN))); #if !defined(PICO_DEFAULT_UART_BAUD_RATE) panic("UART baud rate undefined"); #else @@ -75,12 +92,52 @@ void stdin_uart_init() { void stdio_uart_init_full(struct uart_inst *uart, uint baud_rate, int tx_pin, int rx_pin) { uart_instance = uart; - if (tx_pin >= 0) gpio_set_function((uint)tx_pin, GPIO_FUNC_UART); - if (rx_pin >= 0) gpio_set_function((uint)rx_pin, GPIO_FUNC_UART); + if (tx_pin >= 0) gpio_set_function((uint)tx_pin, UART_FUNCSEL_NUM(uart, tx_pin)); + if (rx_pin >= 0) gpio_set_function((uint)rx_pin, UART_FUNCSEL_NUM(uart, rx_pin)); uart_init(uart_instance, baud_rate); stdio_set_driver_enabled(&stdio_uart, true); } +void stdio_uart_deinit(void) { +#ifdef uart_default + int tx_pin = -1; + int rx_pin = -1; +#ifdef PICO_DEFAULT_UART_TX_PIN + tx_pin = PICO_DEFAULT_UART_TX_PIN; +#endif +#ifdef PICO_DEFAULT_UART_RX_PIN + rx_pin = PICO_DEFAULT_UART_RX_PIN; +#endif + stdio_uart_deinit_full(uart_default, tx_pin, rx_pin); +#endif +} + +void stdout_uart_deinit(void) { +#if defined(uart_default) && defined(PICO_DEFAULT_UART_TX_PIN) + stdio_uart_deinit_full(uart_default, PICO_DEFAULT_UART_TX_PIN, -1); +#endif +} + +void stdin_uart_deinit(void) { +#if defined(uart_default) && defined(PICO_DEFAULT_UART_RX_PIN) + stdio_uart_deinit_full(uart_default, -1, PICO_DEFAULT_UART_RX_PIN); +#endif +} + +void stdio_uart_deinit_full(struct uart_inst *uart, int tx_pin, int rx_pin) { + uart_instance = uart; + stdio_set_driver_enabled(&stdio_uart, false); + uart_deinit(uart_instance); +#if PICO_RP2040 + ((void)tx_pin); + ((void)rx_pin); +#else + // Leave pads isolated + if (tx_pin >= 0) hw_set_bits(&pads_bank0_hw->io[tx_pin], PADS_BANK0_GPIO0_ISO_BITS); + if (rx_pin >= 0) hw_set_bits(&pads_bank0_hw->io[rx_pin], PADS_BANK0_GPIO0_ISO_BITS); +#endif +} + static void stdio_uart_out_chars(const char *buf, int length) { for (int i = 0; i bRequest == 1 && request->wIndex == 7) { + // Get Microsoft OS 2.0 compatible descriptor + return tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_ms_os_20, sizeof(desc_ms_os_20)); + } else { + return false; + } + + // stall unknown request + return false; +} +#endif + static void resetd_init(void) { } diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb.c b/src/rp2_common/pico_stdio_usb/stdio_usb.c index 2895be72c..0f9e3188d 100644 --- a/src/rp2_common/pico_stdio_usb/stdio_usb.c +++ b/src/rp2_common/pico_stdio_usb/stdio_usb.c @@ -50,8 +50,12 @@ static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) { } else { repeat_time = PICO_STDIO_USB_TASK_INTERVAL_US; } - irq_set_pending(low_priority_irq_num); - return repeat_time; + if (irq_is_enabled(low_priority_irq_num)) { + irq_set_pending(low_priority_irq_num); + return repeat_time; + } else { + return 0; // don't repeat + } } static void low_priority_worker_irq(void) { @@ -126,6 +130,16 @@ static void stdio_usb_out_chars(const char *buf, int length) { mutex_exit(&stdio_usb_mutex); } +static void stdio_usb_out_flush(void) { + if (!mutex_try_enter_block_until(&stdio_usb_mutex, make_timeout_time_ms(PICO_STDIO_DEADLOCK_TIMEOUT_MS))) { + return; + } + do { + tud_task(); + } while (tud_cdc_write_flush()); + mutex_exit(&stdio_usb_mutex); +} + int stdio_usb_in_chars(char *buf, int length) { // note we perform this check outside the lock, to try and prevent possible deadlock conditions // with printf in IRQs (which we will escape through timeouts elsewhere, but that would be less graceful). @@ -161,6 +175,7 @@ void stdio_usb_set_chars_available_callback(void (*fn)(void*), void *param) { stdio_driver_t stdio_usb = { .out_chars = stdio_usb_out_chars, + .out_flush = stdio_usb_out_flush, .in_chars = stdio_usb_in_chars, #if PICO_STDIO_USB_SUPPORT_CHARS_AVAILABLE_CALLBACK .set_chars_available_callback = stdio_usb_set_chars_available_callback, @@ -189,7 +204,7 @@ bool stdio_usb_init(void) { assert(tud_inited()); // we expect the caller to have initialized if they are using TinyUSB #endif - mutex_init(&stdio_usb_mutex); + if (!mutex_is_initialized(&stdio_usb_mutex)) mutex_init(&stdio_usb_mutex); bool rc = true; #if !LIB_TINYUSB_DEVICE #ifdef PICO_STDIO_USB_LOW_PRIORITY_IRQ @@ -201,13 +216,13 @@ bool stdio_usb_init(void) { irq_set_enabled(low_priority_irq_num, true); if (irq_has_shared_handler(USBCTRL_IRQ)) { + critical_section_init_with_lock_num(&one_shot_timer_crit_sec, spin_lock_claim_unused(true)); // we can use a shared handler to notice when there may be work to do irq_add_shared_handler(USBCTRL_IRQ, usb_irq, PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY); - critical_section_init_with_lock_num(&one_shot_timer_crit_sec, next_striped_spin_lock_num()); } else { - rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true) >= 0; // we use initialization state of the one_shot_timer_critsec as a flag memset(&one_shot_timer_crit_sec, 0, sizeof(one_shot_timer_crit_sec)); + rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true) >= 0; } #endif if (rc) { @@ -232,6 +247,40 @@ bool stdio_usb_init(void) { return rc; } +bool stdio_usb_deinit(void) { + if (get_core_num() != alarm_pool_core_num(alarm_pool_get_default())) { + // included an assertion here rather than just returning false, as this is likely + // a coding bug, rather than anything else. + assert(false); + return false; + } + + assert(tud_inited()); // we expect the caller to have initialized when calling sdio_usb_init + + bool rc = true; + + stdio_set_driver_enabled(&stdio_usb, false); + +#if PICO_STDIO_USB_DEINIT_DELAY_MS != 0 + sleep_ms(PICO_STDIO_USB_DEINIT_DELAY_MS); +#endif + +#if !LIB_TINYUSB_DEVICE + if (irq_has_shared_handler(USBCTRL_IRQ)) { + spin_lock_unclaim(spin_lock_get_num(one_shot_timer_crit_sec.spin_lock)); + critical_section_deinit(&one_shot_timer_crit_sec); + // we can use a shared handler to notice when there may be work to do + irq_remove_handler(USBCTRL_IRQ, usb_irq); + } else { + // timer is disabled by disabling the irq + } + + irq_set_enabled(low_priority_irq_num, false); + user_irq_unclaim(low_priority_irq_num); +#endif + return rc; +} + bool stdio_usb_connected(void) { #if PICO_STDIO_USB_CONNECTION_WITHOUT_DTR return tud_ready(); diff --git a/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c index 2fb861669..7ecfdffe7 100644 --- a/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c +++ b/src/rp2_common/pico_stdio_usb/stdio_usb_descriptors.c @@ -37,7 +37,11 @@ #endif #ifndef USBD_PID -#define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC +#if PICO_RP2040 +#define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC for RP2040 +#else +#define USBD_PID (0x0009) // Raspberry Pi Pico SDK CDC +#endif #endif #ifndef USBD_MANUFACTURER @@ -88,7 +92,7 @@ static const tusb_desc_device_t usbd_desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, + .bcdUSB = 0x0210, .bDeviceClass = TUSB_CLASS_MISC, .bDeviceSubClass = MISC_SUBCLASS_COMMON, .bDeviceProtocol = MISC_PROTOCOL_IAD, diff --git a/src/rp2_common/pico_stdlib/BUILD.bazel b/src/rp2_common/pico_stdlib/BUILD.bazel index c7a712813..f4a15d985 100644 --- a/src/rp2_common/pico_stdlib/BUILD.bazel +++ b/src/rp2_common/pico_stdlib/BUILD.bazel @@ -8,17 +8,13 @@ cc_library( target_compatible_with = compatible_with_rp2(), deps = [ "//src/common/pico_binary_info", - "//src/common/pico_stdlib:pico_stdlib_interface", + "//src/common/pico_stdlib_headers", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_pll", - ] + select({ - "//bazel/constraint:pico_stdio_semihosting_enabled": ["//src/rp2_common/pico_stdio_semihosting"], - "//conditions:default": [], - }) + select({ - "//bazel/constraint:pico_stdio_uart_enabled": ["//src/rp2_common/pico_stdio_uart"], - "//conditions:default": [], - }) + select({ - "//bazel/constraint:pico_stdio_usb_enabled": ["//src/rp2_common/pico_stdio_usb"], - "//conditions:default": [], - }), + "//src/rp2_common/pico_stdio", + "//src/rp2_common/pico_stdio_semihosting", + "//src/rp2_common/pico_stdio_uart", + "//src/rp2_common/pico_stdio_usb", + ], ) diff --git a/src/rp2_common/pico_stdlib/CMakeLists.txt b/src/rp2_common/pico_stdlib/CMakeLists.txt index 510319cce..24cce4ef0 100644 --- a/src/rp2_common/pico_stdlib/CMakeLists.txt +++ b/src/rp2_common/pico_stdlib/CMakeLists.txt @@ -1,18 +1,10 @@ -# PICO_CMAKE_CONFIG: PICO_STDIO_UART, OPTION: Globally enable stdio UART, type=bool, default=1, group=pico_stdlib -option(PICO_STDIO_UART "Globally enable stdio UART" 1) -# PICO_CMAKE_CONFIG: PICO_STDIO_USB, OPTION: Globally enable stdio USB, type=bool, default=0, group=pico_stdlib -option(PICO_STDIO_USB "Globally enable stdio USB" 0) -# PICO_CMAKE_CONFIG: PICO_STDIO_SEMIHOSTING, OPTION: Globally enable stdio semihosting, type=bool, default=0, group=pico_stdlib -option(PICO_STDIO_SEMIHOSTING "Globally enable stdio semi-hosting" 0) -# PICO_CMAKE_CONFIG: PICO_STDIO_RTT, OPTION: Globally enable stdio RTT, type=bool, default=0, group=pico_stdlib -option(PICO_STDIO_RTT "Globally enable stdio RTT" 0) - if (NOT TARGET pico_stdlib) pico_add_impl_library(pico_stdlib) target_sources(pico_stdlib INTERFACE ${CMAKE_CURRENT_LIST_DIR}/stdlib.c ) - pico_mirrored_target_link_libraries(pico_stdlib INTERFACE + + set(PICO_STDLIB_LIBRARIES hardware_gpio hardware_uart hardware_divider @@ -22,41 +14,9 @@ if (NOT TARGET pico_stdlib) pico_runtime pico_stdio ) - - function(pico_enable_stdio_uart TARGET ENABLED) - set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_UART ${ENABLED}) - endfunction() - - function(pico_enable_stdio_usb TARGET ENABLED) - set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_USB ${ENABLED}) - endfunction() - - function(pico_enable_stdio_semihosting TARGET ENABLED) - set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_SEMIHOSTING ${ENABLED}) - endfunction() - - function(pico_enable_stdio_rtt TARGET ENABLED) - set_target_properties(${TARGET} PROPERTIES PICO_TARGET_STDIO_RTT ${ENABLED}) - endfunction() - - if (TARGET pico_stdio_uart) - target_link_libraries(pico_stdlib INTERFACE $,>,${PICO_STDIO_UART},$>>,pico_stdio_uart,>) - target_link_libraries(pico_stdlib_headers INTERFACE $,>,${PICO_STDIO_UART},$>>,pico_stdio_uart_headers,>) - endif() - - if (TARGET pico_stdio_usb) - target_link_libraries(pico_stdlib INTERFACE $,>,${PICO_STDIO_USB},$>>,pico_stdio_usb,>) - target_link_libraries(pico_stdlib_headers INTERFACE $,>,${PICO_STDIO_USB},$>>,pico_stdio_usb_headers,>) - endif() - - if (TARGET pico_stdio_semihosting) - target_link_libraries(pico_stdlib INTERFACE $,>,${PICO_STDIO_SEMIHOSTING},$>>,pico_stdio_semihosting,>) - target_link_libraries(pico_stdlib_headers INTERFACE $,>,${PICO_STDIO_SEMIHOSTING},$>>,pico_stdio_semihosting_headers,>) - endif() - - if (TARGET pico_stdio_rtt) - target_link_libraries(pico_stdlib INTERFACE $,>,${PICO_STDIO_RTT},$>>,pico_stdio_rtt,>) - target_link_libraries(pico_stdlib_headers INTERFACE $,>,${PICO_STDIO_RTT},$>>,pico_stdio_rtt_headers,>) - endif() - + foreach(LIB IN LISTS PICO_STDLIB_LIBRARIES) + if (TARGET ${LIB}) + pico_mirrored_target_link_libraries(pico_stdlib INTERFACE ${LIB}) + endif() + endforeach() endif() diff --git a/src/rp2_common/pico_stdlib/stdlib.c b/src/rp2_common/pico_stdlib/stdlib.c index 0c783b6e4..f61b34b56 100644 --- a/src/rp2_common/pico_stdlib/stdlib.c +++ b/src/rp2_common/pico_stdlib/stdlib.c @@ -5,107 +5,13 @@ */ #include "pico/stdlib.h" -#include "hardware/pll.h" -#include "hardware/clocks.h" #if LIB_PICO_STDIO_UART #include "pico/stdio_uart.h" #else #include "pico/binary_info.h" #endif -// everything running off the USB oscillator -void set_sys_clock_48mhz() { - if (!running_on_fpga()) { - // Change clk_sys to be 48MHz. The simplest way is to take this from PLL_USB - // which has a source frequency of 48MHz - clock_configure(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_KHZ * KHZ, - USB_CLK_KHZ * KHZ); - - // Turn off PLL sys for good measure - pll_deinit(pll_sys); - - // CLK peri is clocked from clk_sys so need to change clk_peri's freq - clock_configure(clk_peri, - 0, - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, - USB_CLK_KHZ * KHZ, - USB_CLK_KHZ * KHZ); - } -} - -// PICO_CONFIG: PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK, When the SYS clock PLL is changed keep the peripheral clock attached to it, type=bool, default=0, advanced=true, group=hardware_clocks -#ifndef PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK -// By default, when reconfiguring the system clock PLL settings after runtime initialization, -// the peripheral clock is switched to the 48MHz USB clock to ensure continuity of peripheral operation. -// Setting this value to 1 changes the behavior to have the peripheral clock re-configured -// to the system clock at it's new frequency. -#define PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK 0 -#endif - -void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2) { - if (!running_on_fpga()) { - clock_configure(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_KHZ * KHZ, - USB_CLK_KHZ * KHZ); - - pll_init(pll_sys, PLL_COMMON_REFDIV, vco_freq, post_div1, post_div2); - uint32_t freq = vco_freq / (post_div1 * post_div2); - - // Configure clocks - // CLK_REF is the XOSC source - clock_configure(clk_ref, - CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, - 0, // No aux mux - XOSC_KHZ * KHZ, - XOSC_KHZ * KHZ); - - // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz - clock_configure(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, - freq, freq); - -#if PICO_CLOCK_AJDUST_PERI_CLOCK_WITH_SYS_CLOCK - clock_configure(clk_peri, - 0, - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, - freq, freq); -#else - clock_configure(clk_peri, - 0, // Only AUX mux on ADC - CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, - USB_CLK_KHZ * KHZ, - USB_CLK_KHZ * KHZ); -#endif - } -} - -bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv2_out) { - uint reference_freq_khz = XOSC_KHZ / PLL_COMMON_REFDIV; - for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) { - uint vco_khz = fbdiv * reference_freq_khz; - if (vco_khz < PICO_PLL_VCO_MIN_FREQ_KHZ || vco_khz > PICO_PLL_VCO_MAX_FREQ_KHZ) continue; - for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) { - for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) { - uint out = vco_khz / (postdiv1 * postdiv2); - if (out == freq_khz && !(vco_khz % (postdiv1 * postdiv2))) { - *vco_out = vco_khz * KHZ; - *postdiv1_out = postdiv1; - *postdiv2_out = postdiv2; - return true; - } - } - } - } - return false; -} - -void setup_default_uart() { +void setup_default_uart(void) { #if LIB_PICO_STDIO_UART stdio_uart_init(); #elif defined(PICO_DEFAULT_UART_BAUD_RATE) && defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) diff --git a/src/rp2_common/pico_time_adapter/BUILD.bazel b/src/rp2_common/pico_time_adapter/BUILD.bazel new file mode 100644 index 000000000..3cbc845f4 --- /dev/null +++ b/src/rp2_common/pico_time_adapter/BUILD.bazel @@ -0,0 +1,15 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "pico_time_adapter", + hdrs = ["include/pico/time_adapter.h"], + includes = ["include"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/common/pico_base_headers", + "//src/rp2_common/hardware_irq", + "//src/rp2_common/hardware_timer", + ], +) diff --git a/src/rp2_common/pico_time_adapter/CMakeLists.txt b/src/rp2_common/pico_time_adapter/CMakeLists.txt new file mode 100644 index 000000000..8edb7c4dd --- /dev/null +++ b/src/rp2_common/pico_time_adapter/CMakeLists.txt @@ -0,0 +1,5 @@ +pico_add_library(pico_time_adapter) + +target_include_directories(pico_time_adapter_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) + +pico_mirrored_target_link_libraries(pico_time INTERFACE pico_time_adapter) \ No newline at end of file diff --git a/src/rp2_common/pico_time_adapter/include/pico/time_adapter.h b/src/rp2_common/pico_time_adapter/include/pico/time_adapter.h new file mode 100644 index 000000000..bb25cc040 --- /dev/null +++ b/src/rp2_common/pico_time_adapter/include/pico/time_adapter.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_TIME_ADAPTER_H +#define _PICO_TIME_ADAPTER_H + +#include "hardware/irq.h" +#include "hardware/timer.h" +#include "pico/assert.h" + +#define TA_NUM_TIMERS NUM_GENERIC_TIMERS +#define TA_NUM_TIMER_ALARMS NUM_ALARMS + +#define timer_hw_from_timer(t) ((timer_hw_t *)(t)) + +static inline void ta_force_irq(alarm_pool_timer_t *timer, uint alarm_num) { + hw_set_bits(&timer_hw_from_timer(timer)->intf, 1u << alarm_num); +} + +static inline void ta_clear_force_irq(alarm_pool_timer_t *timer, uint alarm_num) { + hw_clear_bits(&timer_hw_from_timer(timer)->intf, 1u << alarm_num); +} + +static inline void ta_clear_irq(alarm_pool_timer_t *timer, uint alarm_num) { + timer_hw_from_timer(timer)->intr = 1u << alarm_num; +} + +static inline alarm_pool_timer_t *ta_from_current_irq(uint *alarm_num) { + uint irq_num = __get_current_exception() - VTABLE_FIRST_IRQ; + alarm_pool_timer_t *timer = timer_get_instance(TIMER_NUM_FROM_IRQ(irq_num)); + *alarm_num = TIMER_ALARM_NUM_FROM_IRQ(irq_num); + return timer; +} + +static inline void ta_set_timeout(alarm_pool_timer_t *timer, uint alarm_num, int64_t target) { + timer_hw_from_timer(timer)->alarm[alarm_num] = (uint32_t) target; +} + +static inline uint64_t ta_time_us_64(alarm_pool_timer_t *timer) { + return timer_time_us_64(timer_hw_from_timer(timer)); +} + +static inline void ta_enable_irq_handler(alarm_pool_timer_t *timer, uint alarm_num, irq_handler_t irq_handler) { + // disarm the timer + uint irq_num = timer_hardware_alarm_get_irq_num(timer, alarm_num); + timer_hw_from_timer(timer)->armed = 1u << alarm_num; + irq_set_exclusive_handler(irq_num, irq_handler); + irq_set_enabled(irq_num, true); + hw_set_bits(&timer_hw_from_timer(timer)->inte, 1u << alarm_num); +} + +static inline void ta_disable_irq_handler(alarm_pool_timer_t *timer, uint alarm_num, irq_handler_t irq_handler) { + uint irq_num = timer_hardware_alarm_get_irq_num(timer, alarm_num); + hw_clear_bits(&timer_hw_from_timer(timer)->inte, 1u << alarm_num); + irq_set_enabled(irq_num, true); + irq_remove_handler(irq_num, irq_handler); + hardware_alarm_unclaim(alarm_num); +} + +static inline void ta_hardware_alarm_claim(alarm_pool_timer_t *timer, uint hardware_alaram_num) { + timer_hardware_alarm_claim(timer_hw_from_timer(timer), hardware_alaram_num); +} + +static inline int ta_hardware_alarm_claim_unused(alarm_pool_timer_t *timer, bool required) { + return timer_hardware_alarm_claim_unused(timer, required); +} + +static inline alarm_pool_timer_t *ta_timer_instance(uint timer_num) { + return timer_get_instance(timer_num); +} + +static inline uint ta_timer_num(alarm_pool_timer_t *timer) { + return timer_get_index(timer_hw_from_timer(timer)); +} + +static inline alarm_pool_timer_t *ta_default_timer_instance(void) { + return PICO_DEFAULT_TIMER_INSTANCE(); +} +#endif diff --git a/src/rp2_common/pico_unique_id/BUILD.bazel b/src/rp2_common/pico_unique_id/BUILD.bazel index 9c6e9f27d..7a8c557ea 100644 --- a/src/rp2_common/pico_unique_id/BUILD.bazel +++ b/src/rp2_common/pico_unique_id/BUILD.bazel @@ -9,7 +9,7 @@ cc_library( includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_flash", ], ) diff --git a/src/rp2_common/pico_unique_id/CMakeLists.txt b/src/rp2_common/pico_unique_id/CMakeLists.txt index b8b63f579..a86d19168 100644 --- a/src/rp2_common/pico_unique_id/CMakeLists.txt +++ b/src/rp2_common/pico_unique_id/CMakeLists.txt @@ -4,6 +4,6 @@ target_sources(pico_unique_id INTERFACE ${CMAKE_CURRENT_LIST_DIR}/unique_id.c ) -target_include_directories(pico_unique_id_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(pico_unique_id_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) pico_mirrored_target_link_libraries(pico_unique_id INTERFACE hardware_flash) diff --git a/src/rp2_common/pico_unique_id/unique_id.c b/src/rp2_common/pico_unique_id/unique_id.c index 2e652c8f6..5406f3691 100644 --- a/src/rp2_common/pico_unique_id/unique_id.c +++ b/src/rp2_common/pico_unique_id/unique_id.c @@ -5,6 +5,7 @@ */ #include "hardware/flash.h" +#include "pico/bootrom.h" #include "pico/unique_id.h" static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES == FLASH_UNIQUE_ID_SIZE_BYTES, "Board ID size must match flash ID size"); @@ -12,14 +13,27 @@ static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES == FLASH_UNIQUE_ID_SIZE_BYTES, "Bo static pico_unique_board_id_t retrieved_id; static void __attribute__((constructor)) _retrieve_unique_id_on_boot(void) { -#if PICO_NO_FLASH - // The hardware_flash call will panic() if called directly on a NO_FLASH - // build. Since this constructor is pre-main it would be annoying to - // debug, so just produce something well-defined and obviously wrong. - for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++) - retrieved_id.id[i] = 0xee; +#if PICO_RP2040 + #if PICO_NO_FLASH + // The hardware_flash call will panic() if called directly on a NO_FLASH + // build. Since this constructor is pre-main it would be annoying to + // debug, so just produce something well-defined and obviously wrong. + for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++) + retrieved_id.id[i] = 0xee; + #else + flash_get_unique_id(retrieved_id.id); + #endif #else - flash_get_unique_id(retrieved_id.id); + rom_get_sys_info_fn func = (rom_get_sys_info_fn) rom_func_lookup(ROM_FUNC_GET_SYS_INFO); + union { + uint32_t words[9]; + uint8_t bytes[9 * 4]; + } out; + __unused int rc = func(out.words, 9, SYS_INFO_CHIP_INFO); + assert(rc == 4); + for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++) { + retrieved_id.id[i] = out.bytes[PICO_UNIQUE_BOARD_ID_SIZE_BYTES - 1 + 2 * 4 - i]; + } #endif } diff --git a/src/rp2_common/tinyusb/BUILD.bazel b/src/rp2_common/tinyusb/BUILD.bazel index 3e397ab45..4accbb5ef 100644 --- a/src/rp2_common/tinyusb/BUILD.bazel +++ b/src/rp2_common/tinyusb/BUILD.bazel @@ -4,18 +4,22 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "tinyusb_port", + hdrs = [ + "include/bsp/board.h", + ], defines = [ "CFG_TUSB_DEBUG=0", "CFG_TUSB_MCU=OPT_MCU_RP2040", "CFG_TUSB_OS=OPT_OS_PICO", ], + includes = ["include"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_base", "//src/common/pico_binary_info", - "//src/common/pico_stdlib:pico_stdlib_interface", + "//src/common/pico_stdlib_headers", "//src/common/pico_sync", "//src/common/pico_time:pico_time_headers", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_gpio", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_resets", @@ -23,15 +27,10 @@ cc_library( "//src/rp2_common/hardware_uart", "//src/rp2_common/pico_fix/rp2040_usb_device_enumeration", "//src/rp2_common/pico_stdio:pico_stdio_headers", + "//src/rp2_common/pico_stdio_semihosting", + "//src/rp2_common/pico_stdio_uart", "//src/rp2_common/pico_stdio_usb:pico_stdio_usb_headers", "//src/rp2_common/pico_stdio_usb:tusb_config", - ] + select({ - # If enabled, these headers may need to be visible. - "//bazel/constraint:pico_stdio_semihosting_enabled": ["//src/rp2_common/pico_stdio_semihosting"], - "//conditions:default": [], - }) + select({ - # If enabled, these headers may need to be visible. - "//bazel/constraint:pico_stdio_uart_enabled": ["//src/rp2_common/pico_stdio_uart"], - "//conditions:default": [], - }), + "//src/rp2_common/pico_unique_id", + ], ) diff --git a/src/rp2_common/tinyusb/CMakeLists.txt b/src/rp2_common/tinyusb/CMakeLists.txt index 3b9316333..e305b36c0 100644 --- a/src/rp2_common/tinyusb/CMakeLists.txt +++ b/src/rp2_common/tinyusb/CMakeLists.txt @@ -44,6 +44,7 @@ if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) target_link_libraries(tinyusb_host INTERFACE tinyusb_host_base tinyusb_common) pico_add_library(tinyusb_board) + target_include_directories(tinyusb_board INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) target_link_libraries(tinyusb_board INTERFACE tinyusb_bsp) # Override suppress_tinyusb_warnings to add suppression of (falsely) reported GCC 11.2 warnings @@ -54,6 +55,13 @@ if (EXISTS ${PICO_TINYUSB_PATH}/${TINYUSB_TEST_PATH}) ${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c PROPERTIES COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds") + # suppress warning in our copy of LWIP in case it is used by TinyUSB + set_source_files_properties( + ${PICO_LWIP_PATH}/src/core/tcp_in.c + ${PICO_LWIP_PATH}/src/core/tcp_out.c + ${PICO_LWIP_PATH}/src/core/pbuf.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion") endif() endfunction() diff --git a/src/rp2_common/tinyusb/include/bsp/board.h b/src/rp2_common/tinyusb/include/bsp/board.h new file mode 100644 index 000000000..0ebb6ba13 --- /dev/null +++ b/src/rp2_common/tinyusb/include/bsp/board.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// TinyUSB changed the location of this file, so we'll redirect to be friendly to end users +#ifndef _BSP_BOARD_H +#define _BSP_BOARD_H +#include "bsp/board_api.h" +#endif diff --git a/src/rp2_common/tinyusb/tinyusb.BUILD b/src/rp2_common/tinyusb/tinyusb.BUILD index dc1696b6d..ea0a5c3ed 100644 --- a/src/rp2_common/tinyusb/tinyusb.BUILD +++ b/src/rp2_common/tinyusb/tinyusb.BUILD @@ -8,7 +8,6 @@ exports_files( cc_library( name = "tinyusb", srcs = [ - "hw/bsp/board.h", "hw/bsp/rp2040/family.c", "src/class/audio/audio_device.c", "src/class/cdc/cdc_device.c", diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 207cb72e8..81647ee93 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -9,6 +9,8 @@ if (PICO_ON_DEVICE) add_subdirectory(kitchen_sink) add_subdirectory(hardware_irq_test) add_subdirectory(hardware_pwm_test) + add_subdirectory(hardware_sync_spin_lock_test) add_subdirectory(cmsis_test) add_subdirectory(pico_sem_test) + add_subdirectory(pico_sha256_test) endif() diff --git a/test/cmsis_test/BUILD.bazel b/test/cmsis_test/BUILD.bazel index 551aedb5c..3b9a4d7de 100644 --- a/test/cmsis_test/BUILD.bazel +++ b/test/cmsis_test/BUILD.bazel @@ -9,6 +9,7 @@ cc_binary( target_compatible_with = compatible_with_rp2(), deps = [ "//bazel/config:PICO_CMSIS_PATH", - "//src/common/pico_stdlib", + "//src/rp2_common:pico_platform", + "//src/rp2_common/pico_stdlib", ], ) diff --git a/test/cmsis_test/CMakeLists.txt b/test/cmsis_test/CMakeLists.txt index da8ecbf8c..ca992eeaf 100644 --- a/test/cmsis_test/CMakeLists.txt +++ b/test/cmsis_test/CMakeLists.txt @@ -1,4 +1,7 @@ -add_executable(cmsis_test cmsis_test.c) +# todo remove check +if (NOT PICO_RISCV) + add_executable(cmsis_test cmsis_test.c) -target_link_libraries(cmsis_test PRIVATE pico_stdlib cmsis_core) -pico_add_extra_outputs(cmsis_test) \ No newline at end of file + target_link_libraries(cmsis_test PRIVATE pico_stdlib cmsis_core) + pico_add_extra_outputs(cmsis_test) +endif() \ No newline at end of file diff --git a/test/cmsis_test/cmsis_test.c b/test/cmsis_test/cmsis_test.c index a436391dd..bb0bebda6 100644 --- a/test/cmsis_test/cmsis_test.c +++ b/test/cmsis_test/cmsis_test.c @@ -1,6 +1,10 @@ #include +#if PICO_RP2040 #include "RP2040.h" +#else +#include "RP2350.h" +#endif #include "pico/stdio.h" __STATIC_FORCEINLINE int some_function(int i) { diff --git a/test/hardware_irq_test/BUILD.bazel b/test/hardware_irq_test/BUILD.bazel index ea4697d3c..8787b7b38 100644 --- a/test/hardware_irq_test/BUILD.bazel +++ b/test/hardware_irq_test/BUILD.bazel @@ -8,11 +8,11 @@ cc_binary( srcs = ["hardware_irq_test.c"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_stdlib", "//src/common/pico_time", + "//src/rp2_common:hardware_structs", "//src/rp2_common/hardware_dma", "//src/rp2_common/hardware_irq", - "//src/rp2_common/pico_platform:hardware_structs", + "//src/rp2_common/pico_stdlib", "//test/pico_test", ], ) diff --git a/test/hardware_irq_test/hardware_irq_test.c b/test/hardware_irq_test/hardware_irq_test.c index ed46a3270..c9daf8c2b 100644 --- a/test/hardware_irq_test/hardware_irq_test.c +++ b/test/hardware_irq_test/hardware_irq_test.c @@ -63,13 +63,26 @@ void __isr handler3(void) { } static inline irq_handler_t *get_vtable(void) { +#ifdef __riscv + return (irq_handler_t *) (riscv_read_csr(RVCSR_MTVEC_OFFSET) & ~0x3u); +#else return (irq_handler_t *) scb_hw->vtor; +#endif } +// Only used for dumping the chain for post-mortem: +#define SLOT_SIZE 12 +extern uint8_t irq_handler_chain_slots[SLOT_SIZE * PICO_MAX_SHARED_IRQ_HANDLERS]; +#ifdef __riscv +#define SLOT_LINK_OFFSET 10 +#else +#define SLOT_LINK_OFFSET 6 +#endif + int dma_check(int expected, ...) { if (expected == 0) { // doing the DMA if there are no IRQ handlers will cause a hard fault, so we just check we are pointing at the handler which does this. - PICOTEST_CHECK_AND_ABORT(get_vtable()[16 + DMA_IRQ_0] == __unhandled_user_irq, "Expected there to be no IRQ handlers"); + PICOTEST_CHECK_AND_ABORT(get_vtable()[VTABLE_FIRST_IRQ + DMA_IRQ_0] == __unhandled_user_irq, "Expected there to be no IRQ handlers"); return 0; } fire_count = 0; @@ -101,6 +114,23 @@ int dma_check(int expected, ...) { printf("%d", fired[i]); } printf("\n"); + printf("Dump of slot chain:\n"); + uint8_t *head = (uint8_t*)get_vtable()[VTABLE_FIRST_IRQ + DMA_IRQ_0]; + printf(" Head at %p\n", head); + while (head >= irq_handler_chain_slots && head <= &irq_handler_chain_slots[SLOT_SIZE * (PICO_MAX_SHARED_IRQ_HANDLERS - 1)]) { + printf( + " %p (slot %3u): %02x%02x %02x%02x %02x%02x %02x%02x %02x%02x %02x%02x\n", + head, ((uintptr_t)head - (uintptr_t)irq_handler_chain_slots) / SLOT_SIZE, + head[1], head[0], + head[3], head[2], + head[5], head[4], + head[7], head[6], + head[9], head[8], + head[11], head[10] + ); + head = &irq_handler_chain_slots[head[SLOT_LINK_OFFSET] * SLOT_SIZE]; + } + printf("Handlers at: %p, %p, %p\n", handler1, handler2, handler3); return -1; } return 0; diff --git a/test/hardware_pwm_test/BUILD.bazel b/test/hardware_pwm_test/BUILD.bazel index 700fd1ade..9c8a32c80 100644 --- a/test/hardware_pwm_test/BUILD.bazel +++ b/test/hardware_pwm_test/BUILD.bazel @@ -8,11 +8,11 @@ cc_binary( srcs = ["hardware_pwm_test.c"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_stdlib", "//src/common/pico_time", "//src/rp2_common/hardware_irq", "//src/rp2_common/hardware_pwm", "//src/rp2_common/hardware_resets", + "//src/rp2_common/pico_stdlib", "//test/pico_test", ], ) diff --git a/test/hardware_pwm_test/hardware_pwm_test.c b/test/hardware_pwm_test/hardware_pwm_test.c index aa5d5bbe2..cf370eeab 100644 --- a/test/hardware_pwm_test/hardware_pwm_test.c +++ b/test/hardware_pwm_test/hardware_pwm_test.c @@ -32,8 +32,7 @@ void on_pwm_wrap() { } int main() { - reset_block(RESETS_RESET_PWM_BITS); - unreset_block_wait(RESETS_RESET_PWM_BITS); + reset_unreset_block_num_wait_blocking(RESET_PWM); setup_default_uart(); @@ -135,8 +134,8 @@ int main() { PICOTEST_START_SECTION("PWM IRQ tests"); - irq_set_exclusive_handler(PWM_IRQ_WRAP, on_pwm_wrap); - irq_set_enabled(PWM_IRQ_WRAP, true); + irq_set_exclusive_handler(PWM_DEFAULT_IRQ_NUM(), on_pwm_wrap); + irq_set_enabled(PWM_DEFAULT_IRQ_NUM(), true); config = pwm_get_default_config(); @@ -151,14 +150,13 @@ int main() { } // Now enable all the PWM at the same time. - pwm_set_mask_enabled(0xff); - + pwm_set_mask_enabled((1 << NUM_PWM_SLICES) - 1); sleep_ms(1000); int err = 0; for (int p = 0; p < NUM_PWM_SLICES; p++) { - PICOTEST_CHECK_CHANNEL(p, interrupt_states[p].count != 0, "No interrupts detected from PWM %d\n"); + PICOTEST_CHECK_CHANNEL(p, interrupt_states[p].count != 0, "No interrupts detected from PWM\n"); } PICOTEST_END_SECTION(); diff --git a/test/hardware_sync_spin_lock_test/BUILD.bazel b/test/hardware_sync_spin_lock_test/BUILD.bazel new file mode 100644 index 000000000..8e35cfa11 --- /dev/null +++ b/test/hardware_sync_spin_lock_test/BUILD.bazel @@ -0,0 +1,26 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel/util:transition.bzl", "extra_copts_for_all_deps") + +package(default_visibility = ["//visibility:public"]) + +cc_binary( + name = "hardware_sync_spin_lock_test_actual", + testonly = True, + srcs = ["hardware_sync_spin_lock_test.c"], + tags = ["manual"], + deps = [ + "//src/rp2_common/hardware_sync", + "//src/rp2_common/hardware_sync_spin_lock", + "//src/rp2_common/pico_multicore", + "//src/rp2_common/pico_stdio", + "//test/pico_test", + ], +) + +extra_copts_for_all_deps( + name = "hardware_sync_spin_lock_test", + testonly = True, + src = ":hardware_sync_spin_lock_test_actual", + extra_copts = ["-DPICO_STDOUT_MUTEX=0"], + target_compatible_with = compatible_with_rp2(), +) diff --git a/test/hardware_sync_spin_lock_test/CMakeLists.txt b/test/hardware_sync_spin_lock_test/CMakeLists.txt new file mode 100644 index 000000000..36edf813c --- /dev/null +++ b/test/hardware_sync_spin_lock_test/CMakeLists.txt @@ -0,0 +1,8 @@ +add_executable(hardware_sync_spin_lock_test hardware_sync_spin_lock_test.c) + +target_link_libraries(hardware_sync_spin_lock_test PRIVATE pico_test hardware_sync pico_multicore) +pico_add_extra_outputs(hardware_sync_spin_lock_test) + +target_compile_definitions(hardware_sync_spin_lock_test PRIVATE + PICO_STDOUT_MUTEX=0 + ) diff --git a/test/hardware_sync_spin_lock_test/hardware_sync_spin_lock_test.c b/test/hardware_sync_spin_lock_test/hardware_sync_spin_lock_test.c new file mode 100644 index 000000000..7ff8db0f5 --- /dev/null +++ b/test/hardware_sync_spin_lock_test/hardware_sync_spin_lock_test.c @@ -0,0 +1,229 @@ +#include "pico/test.h" +#include "pico/test/xrand.h" + +#include "hardware/sync.h" +#include "hardware/sync/spin_lock.h" +#include "pico/multicore.h" +#include "pico/stdio.h" + +#include + +uint counter_local[NUM_CORES][NUM_SPIN_LOCKS]; +uint counter_shared[NUM_SPIN_LOCKS]; + +typedef struct test { + const char *name; + void (*prepare)(); + void (*run_per_core)(); + // Return true for ok: + bool (*check)(); +} test_t; + +// Increase until fear turns to boredom: +static const uint ITERATIONS = 0x40000; + +void prepare_clear_counters(void) { + __mem_fence_acquire(); + for (int i = 0; i < NUM_SPIN_LOCKS; ++i) { + for (int j = 0; j < NUM_CORES; ++j) { + counter_local[j][i] = 0; + } + counter_shared[i] = 0; + } + __mem_fence_release(); +} + +bool check_counter_sums(void) { + __mem_fence_acquire(); + bool all_ok = true; + uint full_sum = 0; + for (int i = 0; i < NUM_SPIN_LOCKS; ++i) { + uint per_lock_sum = 0; + for (int j = 0; j < NUM_CORES; ++j) { + per_lock_sum += counter_local[j][i]; + if (counter_local[j][i] > ITERATIONS) { + printf("Impossible local counter value %d on core %d: %08x (max %08x)\n", + i, j, counter_local[j][i], ITERATIONS); + all_ok = false; + } + } + if (per_lock_sum != counter_shared[i]) { + printf("Failed sum check for lock %d: expected %08x, actual %08x\n", + i, per_lock_sum, counter_shared[i] + ); + all_ok = false; + } + if (counter_shared[i] > ITERATIONS * NUM_CORES) { + printf("Impossible shared counter value %d: %08x (max %08x)\n", + i, counter_shared[i], ITERATIONS * NUM_CORES); + all_ok = false; + } + full_sum += per_lock_sum; + } + if (full_sum != ITERATIONS * NUM_CORES) { + printf("Incorrect counter total: expected %08x, got %08x\n", + ITERATIONS, full_sum); + all_ok = false; + } + return all_ok; +} + +void counter_test_per_core(uint lock_index_mask) { + // Each lock has a global counter. Repeatedly, randomly select a lock and + // write to its counter while holding the lock. Also increment a per-core + // counter for that lock, so we can check at the end that the per-core + // values add up. + xrand_state_t state = XRAND_DEFAULT_INIT; + uint core_num = get_core_num(); + for (uint i = 0; i < core_num; ++i) { + xrand_jump(&state); + } + for (uint i = 0; i < ITERATIONS; ++i) { + uint lock_index = xrand_next(&state) & lock_index_mask; + spin_lock_t *lock = spin_lock_instance(lock_index); + uint32_t flags = spin_lock_blocking(lock); + counter_shared[lock_index]++; + spin_unlock(lock, flags); + counter_local[core_num][lock_index]++; + busy_wait_at_least_cycles(xrand_next(&state) & 0xffu); + } +} + +void counter_try_test_per_core(uint lock_index_mask) { + // Same as counter_test but use the try_lock variant -- worth testing as + // it may be a different asm implementation altogether. + xrand_state_t state = XRAND_DEFAULT_INIT; + uint core_num = get_core_num(); + for (uint i = 0; i < core_num; ++i) { + xrand_jump(&state); + } + for (uint i = 0; i < ITERATIONS; ++i) { + uint lock_index = xrand_next(&state) & lock_index_mask; + spin_lock_t *lock = spin_lock_instance(lock_index); + // Assume this test runs without IRQs active + while (!spin_try_lock_unsafe(lock)) + ; + counter_shared[lock_index]++; + spin_unlock_unsafe(lock); + counter_local[core_num][lock_index]++; + busy_wait_at_least_cycles(xrand_next(&state) & 0xffu); + } +} + + +// Test with successively fewer locks to increase contention +void counter_test1(void) { + counter_test_per_core(NUM_SPIN_LOCKS - 1); +} + +void counter_test2(void) { + counter_test_per_core((NUM_SPIN_LOCKS - 1) >> 1); +} + +void counter_test3(void) { + counter_test_per_core((NUM_SPIN_LOCKS - 1) >> 2); +} + +void counter_test4(void) { + counter_test_per_core((NUM_SPIN_LOCKS - 1) >> 3); +} + +void counter_test5(void) { + counter_test_per_core((NUM_SPIN_LOCKS - 1) >> 4); +} + +void counter_try_test1(void) { + counter_try_test_per_core(NUM_SPIN_LOCKS - 1); +} + +void counter_try_test2(void) { + counter_try_test_per_core((NUM_SPIN_LOCKS - 1) >> 4); +} + +void counter_test_with_irqs(void) { + +} + + +static const test_t tests[] = { + { + "counter test, all locks\n", + prepare_clear_counters, + counter_test1, + check_counter_sums + }, + { + "counter test, half of locks\n", + prepare_clear_counters, + counter_test2, + check_counter_sums + }, + { + "counter test, 1/4 of locks\n", + prepare_clear_counters, + counter_test3, + check_counter_sums + }, + { + "counter test, 1/8 of locks\n", + prepare_clear_counters, + counter_test4, + check_counter_sums + }, + { + "counter test, 1/16 of locks\n", + prepare_clear_counters, + counter_test5, + check_counter_sums + }, + { + "counter test with try_lock, all locks\n", + prepare_clear_counters, + counter_try_test1, + check_counter_sums + }, + { + "counter test with try_lock, 1/16 of locks\n", + prepare_clear_counters, + counter_try_test2, + check_counter_sums + }, +}; + +void core1_main(void) { + while (true) { + void (*f)() = (void(*)())multicore_fifo_pop_blocking(); + f(); + multicore_fifo_push_blocking(0); + } +} + +int main() { + stdio_init_all(); + printf("Hello world\n"); + multicore_launch_core1(core1_main); + uint failed = 0; + for (int i = 0; i < count_of(tests); ++i) { + const test_t *t = &tests[i]; + printf(">>> Starting test: %s\n", t->name); + spin_locks_reset(); + t->prepare(); + multicore_fifo_push_blocking((uintptr_t)t->run_per_core); + t->run_per_core(); + (void)multicore_fifo_pop_blocking(); + printf(">>> Finished test: %s\n", t->name); + if (t->check()) { + printf("OK.\n"); + } else { + printf("Failed.\n"); + ++failed; + } + } + if (failed == 0u) { + printf("All tests passed.\n"); + return 0; + } else { + printf("%u tests failed. Review log for details.\n", failed); + return -1; + } +} diff --git a/test/kitchen_sink/BUILD.bazel b/test/kitchen_sink/BUILD.bazel index c9e604069..ec3ea9fcf 100644 --- a/test/kitchen_sink/BUILD.bazel +++ b/test/kitchen_sink/BUILD.bazel @@ -32,15 +32,15 @@ cc_library( hdrs = ["kitchen_sink.c"], target_compatible_with = compatible_with_rp2(), deps = [ + "//src/common/hardware_claim", "//src/common/pico_binary_info", - "//src/common/pico_bit_ops", - "//src/common/pico_divider", - "//src/common/pico_stdlib", + "//src/common/pico_bit_ops_headers", "//src/common/pico_sync", "//src/common/pico_time", "//src/common/pico_util", + "//src/rp2_common:hardware_structs", + "//src/rp2_common:pico_platform", "//src/rp2_common/hardware_adc", - "//src/rp2_common/hardware_claim", "//src/rp2_common/hardware_clocks", "//src/rp2_common/hardware_divider", "//src/rp2_common/hardware_dma", @@ -54,7 +54,6 @@ cc_library( "//src/rp2_common/hardware_pll", "//src/rp2_common/hardware_pwm", "//src/rp2_common/hardware_resets", - "//src/rp2_common/hardware_rtc", "//src/rp2_common/hardware_spi", "//src/rp2_common/hardware_sync", "//src/rp2_common/hardware_timer", @@ -62,7 +61,9 @@ cc_library( "//src/rp2_common/hardware_vreg", "//src/rp2_common/hardware_watchdog", "//src/rp2_common/hardware_xosc", + "//src/rp2_common/pico_aon_timer", "//src/rp2_common/pico_bootrom", + "//src/rp2_common/pico_divider", "//src/rp2_common/pico_double", "//src/rp2_common/pico_fix/rp2040_usb_device_enumeration", "//src/rp2_common/pico_flash", @@ -72,14 +73,21 @@ cc_library( "//src/rp2_common/pico_malloc", "//src/rp2_common/pico_mem_ops", "//src/rp2_common/pico_multicore", - "//src/rp2_common/pico_platform", "//src/rp2_common/pico_printf", "//src/rp2_common/pico_rand", "//src/rp2_common/pico_runtime", "//src/rp2_common/pico_stdio", + "//src/rp2_common/pico_stdlib", "//src/rp2_common/pico_unique_id", "//test/pico_test", - ], + ] + select({ + "//bazel/constraint:rp2350": [ + "//src/rp2_common/hardware_sha256", + ], + "//conditions:default": [ + "//src/rp2_common/hardware_rtc", + ], + }), ) cc_binary( diff --git a/test/kitchen_sink/CMakeLists.txt b/test/kitchen_sink/CMakeLists.txt index 60ca0a216..5395129d6 100644 --- a/test/kitchen_sink/CMakeLists.txt +++ b/test/kitchen_sink/CMakeLists.txt @@ -1,5 +1,6 @@ add_library(kitchen_sink_libs INTERFACE) -target_link_libraries(kitchen_sink_libs INTERFACE + +set(KITCHEN_SINK_LIBS hardware_adc hardware_clocks hardware_divider @@ -11,17 +12,20 @@ target_link_libraries(kitchen_sink_libs INTERFACE hardware_interp hardware_irq hardware_pio + hardware_powman hardware_pll hardware_pwm hardware_resets hardware_rtc hardware_spi hardware_sync + hardware_ticks hardware_timer hardware_uart hardware_vreg hardware_watchdog hardware_xosc + pico_aon_timer pico_bit_ops pico_bootrom pico_bootsel_via_double_reset @@ -37,6 +41,7 @@ target_link_libraries(kitchen_sink_libs INTERFACE pico_multicore pico_platform pico_rand + pico_sha256 pico_stdlib pico_sync pico_time @@ -44,6 +49,12 @@ target_link_libraries(kitchen_sink_libs INTERFACE pico_util ) +foreach(LIB IN LISTS KITCHEN_SINK_LIBS) + if (TARGET ${LIB}) + target_link_libraries(kitchen_sink_libs INTERFACE ${LIB}) + endif() +endforeach () + add_library(kitchen_sink_options INTERFACE) target_compile_options(kitchen_sink_options INTERFACE @@ -56,26 +67,19 @@ target_compile_options(kitchen_sink_options INTERFACE -Wuninitialized -Wunused -Wcast-align - -Wall -Wcast-qual -Wfloat-equal -Wmissing-format-attribute #-Wconversion -Wsign-compare $<$:-Wstrict-prototypes> + # todo we have some of these in usb_device_tiny to try to make it more readable.. perhaps doxygen would help here instead + -Wredundant-decls -Wno-inline # todo not sure these are true, but investigate #-Wpacked - # todo we have some of these in usb_device_tiny to try to make it more readable.. perhaps doxygen would help here instead - -Wredundant-decls - - -Wno-shadow - -Wno-missing-field-initializers - -Wno-missing-braces - -Wno-multichar - # todo useful but fix later #-Wundef ) @@ -89,6 +93,7 @@ if (PICO_C_COMPILER_IS_CLANG) endif() target_compile_definitions(kitchen_sink_libs INTERFACE + PICO_FORBID_ARM_HEADERS_ON_RISCV=1 PARAM_ASSERTIONS_ENABLE_ALL=1 # want to check all the assertions for compilation warnings PICO_AUDIO_DMA_IRQ=1 ) @@ -97,6 +102,7 @@ add_executable(kitchen_sink ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) target_link_libraries(kitchen_sink kitchen_sink_libs kitchen_sink_options) pico_set_program_name(kitchen_sink "Wombat tentacles") pico_add_extra_outputs(kitchen_sink) +target_compile_definitions(kitchen_sink PRIVATE KITCHEN_SINK_ID="regular binary") add_executable(kitchen_sink_extra_stdio ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) if (COMMAND suppress_tinyusb_warnings) @@ -119,20 +125,43 @@ pico_add_extra_outputs(kitchen_sink_extra_stdio) pico_enable_stdio_usb(kitchen_sink_extra_stdio 1) pico_enable_stdio_semihosting(kitchen_sink_extra_stdio 1) +add_executable(kitchen_sink_printf_compiler ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) +target_link_libraries(kitchen_sink_printf_compiler kitchen_sink_libs kitchen_sink_options) +pico_add_extra_outputs(kitchen_sink_printf_compiler) +pico_set_printf_implementation(kitchen_sink_printf_compiler compiler) + +add_executable(kitchen_sink_printf_compiler_no_shortcircuit ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) +target_link_libraries(kitchen_sink_printf_compiler_no_shortcircuit kitchen_sink_libs kitchen_sink_options) +pico_add_extra_outputs(kitchen_sink_printf_compiler_no_shortcircuit) +pico_set_printf_implementation(kitchen_sink_printf_compiler_no_shortcircuit compiler) +target_compile_definitions(kitchen_sink_printf_compiler_no_shortcircuit PRIVATE PICO_STDIO_SHORT_CIRCUIT_CLIB_FUNCS=0) + + +add_executable(kitchen_sink_printf_none ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) +target_link_libraries(kitchen_sink_printf_none kitchen_sink_libs kitchen_sink_options) +pico_add_extra_outputs(kitchen_sink_printf_none) +pico_set_printf_implementation(kitchen_sink_printf_none none) + add_executable(kitchen_sink_copy_to_ram ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) pico_set_binary_type(kitchen_sink_copy_to_ram copy_to_ram) target_link_libraries(kitchen_sink_copy_to_ram kitchen_sink_libs kitchen_sink_options) pico_add_extra_outputs(kitchen_sink_copy_to_ram) +target_compile_definitions(kitchen_sink_copy_to_ram PRIVATE KITCHEN_SINK_ID="copy-to-ram binary") add_executable(kitchen_sink_no_flash ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) pico_set_binary_type(kitchen_sink_no_flash no_flash) target_link_libraries(kitchen_sink_no_flash kitchen_sink_libs kitchen_sink_options) pico_add_extra_outputs(kitchen_sink_no_flash) - -add_executable(kitchen_sink_blocked_ram ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) -pico_set_binary_type(kitchen_sink_blocked_ram blocked_ram) -target_link_libraries(kitchen_sink_blocked_ram kitchen_sink_libs kitchen_sink_options) -pico_add_extra_outputs(kitchen_sink_blocked_ram) +target_compile_definitions(kitchen_sink_no_flash PRIVATE KITCHEN_SINK_ID="no-flash binary") + +if (NOT PICO_RP2350) + # RP2350 does not have blocked ram + add_executable(kitchen_sink_blocked_ram ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink.c) + pico_set_binary_type(kitchen_sink_blocked_ram blocked_ram) + target_link_libraries(kitchen_sink_blocked_ram kitchen_sink_libs kitchen_sink_options) + pico_add_extra_outputs(kitchen_sink_blocked_ram) + target_compile_definitions(kitchen_sink_blocked_ram PRIVATE KITCHEN_SINK_ID="blocked-ram binary") +endif() add_executable(kitchen_sink_cpp ${CMAKE_CURRENT_LIST_DIR}/kitchen_sink_cpp.cpp) target_link_libraries(kitchen_sink_cpp kitchen_sink_libs kitchen_sink_options) diff --git a/test/kitchen_sink/kitchen_sink.c b/test/kitchen_sink/kitchen_sink.c index 29dda2bfb..73417d5a5 100644 --- a/test/kitchen_sink/kitchen_sink.c +++ b/test/kitchen_sink/kitchen_sink.c @@ -22,14 +22,21 @@ #include "hardware/pll.h" #include "hardware/pwm.h" #include "hardware/resets.h" +#if PICO_RP2040 #include "hardware/rtc.h" +#endif +#if !PICO_RP2040 +#include "hardware/sha256.h" +#endif #include "hardware/spi.h" #include "hardware/sync.h" #include "hardware/timer.h" +#include "hardware/ticks.h" #include "hardware/uart.h" #include "hardware/vreg.h" #include "hardware/watchdog.h" #include "hardware/xosc.h" +#include "pico/aon_timer.h" #include "pico/binary_info.h" #include "pico/bit_ops.h" #include "pico/bootrom.h" @@ -37,19 +44,29 @@ #include "pico/cyw43_arch.h" #endif #include "pico/divider.h" +// todo we should have this but right now double.h is only present with double_implementation == pico +#if PICO_RP2040 #include "pico/double.h" +#endif #include "pico/fix/rp2040_usb_device_enumeration.h" #include "pico/flash.h" +// todo we should have this but right now float.h is only present with float_implementation == pico +#if PICO_RP2040 #include "pico/float.h" +#endif #include "pico/i2c_slave.h" +#if LIB_PICO_INT64_OPS_PICO #include "pico/int64_ops.h" +#endif #include "pico/malloc.h" -#include "pico/mem_ops.h" #include "pico/multicore.h" #include "pico/platform.h" #include "pico/printf.h" #include "pico/rand.h" #include "pico/runtime.h" +#if LIB_PICO_SHA256 +#include "pico/sha256.h" +#endif #include "pico/stdio.h" #include "pico/stdlib.h" #include "pico/sync.h" @@ -60,34 +77,52 @@ #include "pico/util/queue.h" #include "hardware/structs/adc.h" -#include "hardware/structs/bus_ctrl.h" +#include "hardware/structs/busctrl.h" #include "hardware/structs/clocks.h" #include "hardware/structs/dma.h" #include "hardware/structs/i2c.h" #include "hardware/structs/interp.h" -#include "hardware/structs/iobank0.h" -#include "hardware/structs/ioqspi.h" +#include "hardware/structs/io_bank0.h" +#include "hardware/structs/io_qspi.h" +#ifndef __riscv #include "hardware/structs/mpu.h" #include "hardware/structs/nvic.h" -#include "hardware/structs/padsbank0.h" +#endif +#include "hardware/structs/pads_bank0.h" #include "hardware/structs/pads_qspi.h" #include "hardware/structs/pio.h" #include "hardware/structs/pll.h" +#if PICO_RP2350 +#include "hardware/structs/powman.h" +#endif #include "hardware/structs/psm.h" #include "hardware/structs/pwm.h" #include "hardware/structs/resets.h" #include "hardware/structs/rosc.h" +#if PICO_RP2040 #include "hardware/structs/rtc.h" +#endif +#ifndef __riscv #include "hardware/structs/scb.h" +#endif #include "hardware/structs/sio.h" +#if !PICO_RP2040 +#include "hardware/structs/sha256.h" +#endif #include "hardware/structs/spi.h" +#if PICO_RP2040 #include "hardware/structs/ssi.h" +#endif #include "hardware/structs/syscfg.h" +#ifndef __riscv #include "hardware/structs/systick.h" +#endif #include "hardware/structs/timer.h" #include "hardware/structs/uart.h" #include "hardware/structs/usb.h" +#if PICO_RP2040 #include "hardware/structs/vreg_and_chip_reset.h" +#endif #include "hardware/structs/watchdog.h" #include "hardware/structs/xip_ctrl.h" #include "hardware/structs/xosc.h" @@ -128,6 +163,11 @@ __force_inline int something_inlined(int x) { auto_init_mutex(mutex); auto_init_recursive_mutex(recursive_mutex); +float __attribute__((noinline)) foox(float x, float b) { + return x * b; +} + + int main(void) { spiggle(); @@ -140,11 +180,21 @@ int main(void) { printf("main at %p\n", (void *)main); static uint x[2]; printf("x[0] = %p, x[1] = %p\n", x, x+1); +#ifdef __riscv + printf("RISC-V\n"); +#else + printf("ARM\n"); +#endif +#ifdef KITCHEN_SINK_ID + puts(KITCHEN_SINK_ID); +#endif hard_assert(mutex_try_enter(&mutex, NULL)); hard_assert(!mutex_try_enter(&mutex, NULL)); hard_assert(recursive_mutex_try_enter(&recursive_mutex, NULL)); hard_assert(recursive_mutex_try_enter(&recursive_mutex, NULL)); + printf("%f\n", foox(1.3f, 2.6f)); +#ifndef __riscv // this should compile as we are Cortex M0+ pico_default_asm ("SVC #3"); - +#endif } diff --git a/test/pico_divider_test/BUILD.bazel b/test/pico_divider_test/BUILD.bazel index b349dda0f..e5f2e93b9 100644 --- a/test/pico_divider_test/BUILD.bazel +++ b/test/pico_divider_test/BUILD.bazel @@ -8,8 +8,8 @@ cc_binary( srcs = ["pico_divider_test.c"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_divider", - "//src/common/pico_stdlib", + "//src/rp2_common/pico_divider", + "//src/rp2_common/pico_stdlib", ] + select({ "//bazel/constraint:host": [], "//conditions:default": [ @@ -26,8 +26,8 @@ cc_binary( srcs = ["pico_divider_nesting_test.c"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_divider", - "//src/common/pico_stdlib", + "//src/rp2_common/pico_divider", + "//src/rp2_common/pico_stdlib", ] + select({ "//bazel/constraint:host": [], "//conditions:default": [ diff --git a/test/pico_divider_test/CMakeLists.txt b/test/pico_divider_test/CMakeLists.txt index d2ab0120e..b180b9d77 100644 --- a/test/pico_divider_test/CMakeLists.txt +++ b/test/pico_divider_test/CMakeLists.txt @@ -7,7 +7,9 @@ if (PICO_ON_DEVICE) target_link_libraries(pico_divider_test pico_stdlib) - pico_set_divider_implementation(pico_divider_test hardware_explicit) # want to compare against compiler impl + if (PICO_RP2040) + pico_set_divider_implementation(pico_divider_test hardware_explicit) # want to compare against compiler impl + endif() pico_add_extra_outputs(pico_divider_test) @@ -25,14 +27,18 @@ if (PICO_ON_DEVICE) add_executable(pico_divider_nesting_test_with_dirty_check) target_link_libraries(pico_divider_nesting_test_with_dirty_check pico_divider_nesting_test_core) - pico_set_divider_implementation(pico_divider_nesting_test_with_dirty_check hardware) + if (PICO_RP2040) + pico_set_divider_implementation(pico_divider_nesting_test_with_dirty_check hardware) + endif() pico_add_extra_outputs(pico_divider_nesting_test_with_dirty_check) add_executable(pico_divider_nesting_test_with_disable_irq) target_link_libraries(pico_divider_nesting_test_with_disable_irq pico_divider_nesting_test_core) target_compile_definitions(pico_divider_nesting_test_with_disable_irq PRIVATE PICO_DIVIDER_DISABLE_INTERRUPTS=1) - pico_set_divider_implementation(pico_divider_nesting_test_with_disable_irq hardware) + if (PICO_RP2040) + pico_set_divider_implementation(pico_divider_nesting_test_with_disable_irq hardware) + endif() pico_add_extra_outputs(pico_divider_nesting_test_with_disable_irq) endif() \ No newline at end of file diff --git a/test/pico_divider_test/pico_divider_nesting_test.c b/test/pico_divider_test/pico_divider_nesting_test.c index cf1b95006..dfcdafc42 100644 --- a/test/pico_divider_test/pico_divider_nesting_test.c +++ b/test/pico_divider_test/pico_divider_nesting_test.c @@ -10,6 +10,7 @@ #include "pico/stdlib.h" #include "hardware/dma.h" #include "hardware/irq.h" +#include "hardware/sync.h" volatile bool failed; volatile uint32_t count[3]; @@ -18,9 +19,12 @@ volatile bool done; #define FAILED() ({ failed = true; }) //#define FAILED() ({ failed = true; __breakpoint(); }) +//#define DOUBLE_ONLY 1 + bool timer_callback(repeating_timer_t *t) { count[0]++; static int z; +#if !DOUBLE_ONLY for (int i=0; i<100;i++) { z += 23; int a = z / 7; @@ -34,19 +38,30 @@ bool timer_callback(repeating_timer_t *t) { FAILED(); } } - float fz = (float)z; +#else + for(int i=0;i<10;i++) { +#endif + float fz = (float) z; float fa = fz / 11.0f; - float fb = fmodf(fz, 11.0f); - if (fabs(fz - (fa * 11.0 + fb)) > 1e-9) { +// float fb = fmodf(fz, 11.0f); +// if (fabs(fz - (fa * 11.0f + fb)) > 1e-9f) { +// FAILED(); +// } + if (fabsf(fz - fa * 11.0f) > 1e-3f) { FAILED(); } double dz = z; double da = dz / 11.0; - double db = fmod(dz, 11.0); - if (fabs(dz - (da * 11.0 + db)) > 1e-9) { +// double db = fmod(dz, 11.0); +// if (abs(dz - (da * 11.0 + db)) > 1e-9) { +// FAILED(); +// } + if (fabs(dz - da * 11.0) > 1e-6f) { FAILED(); } - +#if DOUBLE_ONLY + } +#endif return !done; } @@ -65,18 +80,26 @@ void do_dma_start(uint ch) { double d0c, d0s, d0t, dz; float f0c, f0s, f0t, fz; +double flarn = 25.5; +double zzd = 13.3; + void test_irq_handler0() { count[1]++; dma_hw->ints0 |= 1u; static uint z; static uint dz; for (int i=0; i<80;i++) { +#if !DOUBLE_ONLY z += 31; uint a = z / 11; uint b = z % 11; if (z != a * 11 + b) { FAILED(); } +#else + zzd += flarn/(flarn + 1.35); + break; +#endif } if (done) dma_channel_abort(0); else do_dma_start(0); @@ -87,6 +110,7 @@ void test_irq_handler1() { dma_hw->ints1 |= 2u; count[2]++; for (int i=0; i<130;i++) { +#if !DOUBLE_ONLY z += 47; uint a = z / -13; uint b = z % -13; @@ -100,6 +124,10 @@ void test_irq_handler1() { if (z64 != a64 * -13 + b64) { FAILED(); } +#else + zzd += flarn/123.3; + break; +#endif } if (done) dma_channel_abort(1); @@ -174,8 +202,24 @@ void test_nesting() { FAILED(); } cd++; + static float zf = 1.f; + float ff = zf / -13635.f; + if (fabsf(zf - ff * -13635.f) > 1e-2f) { + FAILED(); + } + zf += 0.0331f; + z += (int)ff; + static double zd = 1.0; + double dd = zd / -13635.0; + if (fabs(zd - dd * -13635.0) > 1e-6) { + FAILED(); + } + zd += 0.331; + z += (int)dd; } + // todo this still seems broken on RP2350 +#if PICO_RP2040 // these use the divider for(uint i=0;i<=100;i+=20) { // both in and out bootrom range (we perform mod in wrapper code if necessarry) @@ -186,12 +230,13 @@ void test_nesting() { d0c = cos(i * 1000); d0s = sin(i * 1000); } +#endif count_local++; } done = true; cancel_repeating_timer(&timer); printf("%d: %d %d %d\n", count_local, (int)count[0], (int)count[1], (int)count[2]); - + printf("%d\n", z); // make sure all the IRQs ran if (!(count_local && count[0] && count[1] && count[2])) { printf("DID NOT RUN\n"); diff --git a/test/pico_divider_test/pico_divider_test.c b/test/pico_divider_test/pico_divider_test.c index 6f0984eed..5a7848222 100644 --- a/test/pico_divider_test/pico_divider_test.c +++ b/test/pico_divider_test/pico_divider_test.c @@ -193,6 +193,7 @@ void test_random() { #endif uint32_t __attribute__((naked)) time_32(uint32_t a, uint32_t b, uint32_t (*func)(uint32_t a, uint32_t b)) { +#ifndef __riscv pico_default_asm ( "push {r4, r5, lr}\n" "ldr r4, =0xe000e018\n" @@ -204,9 +205,15 @@ uint32_t __attribute__((naked)) time_32(uint32_t a, uint32_t b, uint32_t (*func) "asrs r0, #8\n" "pop {r4, r5, pc}\n" ); +#else + pico_default_asm ( + "li a0, 0\n" + ); +#endif } uint32_t __attribute__((naked)) time_64(uint64_t a, uint64_t b, uint64_t (*func64)(uint64_t a, uint64_t b)) { +#ifndef __riscv pico_default_asm ( "push {r4-r6, lr}\n" "ldr r6, [sp, #16]\n" @@ -219,6 +226,11 @@ uint32_t __attribute__((naked)) time_64(uint64_t a, uint64_t b, uint64_t (*func6 "asrs r0, #8\n" "pop {r4-r6, pc}\n" ); +#else + pico_default_asm ( + "li a0, 0\n" + ); +#endif } uint32_t compiler_div_s32(uint32_t a, uint32_t b) { diff --git a/test/pico_float_test/BUILD.bazel b/test/pico_float_test/BUILD.bazel index 16e74779c..ce35a9d74 100644 --- a/test/pico_float_test/BUILD.bazel +++ b/test/pico_float_test/BUILD.bazel @@ -1,4 +1,5 @@ load("//bazel:defs.bzl", "compatible_with_rp2") +load("//bazel/util:transition.bzl", "pico_float_test_binary") package(default_visibility = ["//visibility:public"]) @@ -13,14 +14,15 @@ cc_binary( includes = ["llvm"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_stdlib", + "//src/rp2_common:pico_platform", + "//src/rp2_common/pico_double", "//src/rp2_common/pico_float", - "//src/rp2_common/pico_platform", + "//src/rp2_common/pico_stdlib", ], ) cc_binary( - name = "pico_double_test", + name = "pico_double_test_actual", testonly = True, srcs = [ "llvm/call_apsr.S", @@ -28,10 +30,35 @@ cc_binary( "pico_double_test.c", ], includes = ["llvm"], + tags = ["manual"], target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_stdlib", + "//src/rp2_common:pico_platform", "//src/rp2_common/pico_double", - "//src/rp2_common/pico_platform", + "//src/rp2_common/pico_stdlib", + ], +) + +pico_float_test_binary( + name = "pico_double_test", + testonly = True, + src = ":pico_double_test_actual", + extra_copts = [ + "-DPICO_USE_CRT_PRINTF=1", + "-DPICO_FLOAT_PROPAGATE_NANS=1", + "-DPICO_DOUBLE_PROPAGATE_NANS=1", ], + pico_printf_impl = select({ + # raw compiler printf on llvm_libc doesn't currently have floating point + "//bazel/constraint:pico_clib_llvm_libc_enabled": "pico", + "//bazel/constraint:pico_toolchain_clang_enabled": "pico", + "//conditions:default": "compiler", + }), + target_compatible_with = compatible_with_rp2(), +) + +# TODO: Marked in CMake as to-be-removed. +filegroup( + name = "m33", + srcs = ["m33.c"], ) diff --git a/test/pico_float_test/CMakeLists.txt b/test/pico_float_test/CMakeLists.txt index 26204d3b9..e0e0a814a 100644 --- a/test/pico_float_test/CMakeLists.txt +++ b/test/pico_float_test/CMakeLists.txt @@ -1,42 +1,67 @@ PROJECT(pico_float_test) -add_executable(pico_float_test - pico_float_test.c - llvm/call_apsr.S - ) - -add_executable(pico_double_test - pico_double_test.c - llvm/call_apsr.S - ) - - -#todo split out variants with different flags -target_compile_definitions(pico_float_test PRIVATE - PICO_USE_CRT_PRINTF=1 # want full precision output -# PICO_FLOAT_PROPAGATE_NANS=1 -# PICO_DIVIDER_DISABLE_INTERRUPTS=1 -) - -#todo split out variants with different flags -target_compile_definitions(pico_double_test PRIVATE - PICO_USE_CRT_PRINTF=1 # want full precision output +# todo revist this test for +if (NOT PICO_RISCV) + add_executable(pico_float_test + pico_float_test.c + llvm/call_apsr.S + ) + + add_executable(pico_double_test + pico_double_test.c + llvm/call_apsr.S + ) + + + #todo split out variants with different flags + target_compile_definitions(pico_float_test PRIVATE + # PICO_FLOAT_PROPAGATE_NANS=1 + # PICO_DIVIDER_DISABLE_INTERRUPTS=1 + ) + + #todo split out variants with different flags + target_compile_definitions(pico_double_test PRIVATE + PICO_USE_CRT_PRINTF=1 # want full precision output + PICO_FLOAT_PROPAGATE_NANS=1 + PICO_DOUBLE_PROPAGATE_NANS=1 + #PICO_DIVIDER_DISABLE_INTERRUPTS=1 + ) + if (NOT PICO_CLIB STREQUAL "llvm_libc") + # raw compiler printf on llvm_libc doesn't currently have floating point + pico_set_printf_implementation(pico_double_test compiler) # want full precision output + endif() + + # handy for testing we aren't pulling in extra stuff + #target_link_options(pico_float_test PRIVATE -nodefaultlibs) + + target_include_directories(pico_float_test PRIVATE ${CMAKE_CURRENT_LIST_DIR}/llvm) + target_link_libraries(pico_float_test pico_float pico_stdlib) + pico_add_extra_outputs(pico_float_test) + #pico_set_float_implementation(pico_float_test compiler) + #pico_set_float_implementation(pico_float_test pico_vfp) + #pico_set_double_implementation(pico_float_test compiler) + + target_include_directories(pico_double_test PRIVATE ${CMAKE_CURRENT_LIST_DIR}/llvm) + target_link_libraries(pico_double_test pico_double pico_stdlib) + pico_add_extra_outputs(pico_double_test) + #pico_set_float_implementation(pico_double_test compiler) + #pico_set_double_implementation(pico_double_test compiler) + + if (PICO_RP2350 AND NOT PICO_RISCV) + add_executable(m33 + m33.c + ) + + target_compile_definitions(m33 PRIVATE + PICO_USE_CRT_PRINTF=1 # want full precision output PICO_FLOAT_PROPAGATE_NANS=1 - #PICO_DOUBLE_PROPAGATE_NANS=1 + PICO_DOUBLE_PROPAGATE_NANS=1 #PICO_DIVIDER_DISABLE_INTERRUPTS=1 - ) - -# handy for testing we aren't pulling in extra stuff -#target_link_options(pico_float_test PRIVATE -nodefaultlibs) - -target_include_directories(pico_float_test PRIVATE ${CMAKE_CURRENT_LIST_DIR}/llvm) -target_link_libraries(pico_float_test pico_float pico_stdlib) -pico_add_extra_outputs(pico_float_test) -#pico_set_float_implementation(pico_float_test compiler) -#pico_set_double_implementation(pico_float_test compiler) - -target_include_directories(pico_double_test PRIVATE ${CMAKE_CURRENT_LIST_DIR}/llvm) -target_link_libraries(pico_double_test pico_double pico_stdlib) -pico_add_extra_outputs(pico_double_test) -#pico_set_float_implementation(pico_double_test compiler) -#pico_set_double_implementation(pico_double_test compiler) \ No newline at end of file + ) + pico_set_printf_implementation(m33 compiler) # want full precision output + pico_set_float_implementation(m33 pico) + pico_set_double_implementation(m33 pico) + target_link_libraries(m33 pico_double pico_stdlib) + pico_add_extra_outputs(m33) + endif() +endif() \ No newline at end of file diff --git a/test/pico_float_test/m33.c b/test/pico_float_test/m33.c new file mode 100644 index 000000000..e42e797aa --- /dev/null +++ b/test/pico_float_test/m33.c @@ -0,0 +1,231 @@ +#include +#include "pico/stdlib.h" + +static int rc=0; + +typedef uint32_t ui32; +typedef uint64_t ui64; + +extern ui64 __aeabi_dadd(ui64, ui64); +extern ui64 __aeabi_dsub(ui64, ui64); +extern ui64 __aeabi_dmul(ui64, ui64); +extern ui64 ddiv_fast(ui64, ui64); +extern ui64 sqrt_fast(ui64); + +#define m33cf_dadd __aeabi_dadd +#define m33cf_dsub __aeabi_dsub +#define m33cf_dmul __aeabi_dmul +#define m33cf_ddiv_fast ddiv_fast +#define m33cf_dsqrt_fast sqrt_fast +static void checkf(ui32 r,ui32 t) { + static int n=0; + if(r!=t) { + printf("M33CF test F%d: expected %08x got %08x\n",n,t,r); + rc=-1; + } + n++; +} + +static void checkd(ui64 r,ui64 t) { + static int n=0; + if(r!=t) { + printf("M33CF test D%d: expected %08x%08x got %08x%08x\n", + n, + (ui32)(t>>32),(ui32)t, + (ui32)(r>>32),(ui32)r); + rc=-1; + } + n++; +} + +int main() { + stdio_init_all(); + puts("M33CF function test\n"); + +#if 0 + checkf(m33cf_fadd(0x4d3c3e6f,0x7617944a),0x7617944a); + checkf(m33cf_fadd(0x67819fdb,0xe6225dcc),0x675aa843); + checkf(m33cf_fadd(0x3c9a71a0,0x22d538f1),0x3c9a71a0); + checkf(m33cf_fadd(0xc37ab23a,0x825141a3),0xc37ab23a); + checkf(m33cf_fadd(0x98586bf0,0x17d915be),0x97d7c222); + checkf(m33cf_fadd(0x69572e49,0x4e650317),0x69572e49); + checkf(m33cf_fadd(0xa67b6fbc,0x266be0aa),0xa478f120); + checkf(m33cf_fadd(0x01d100ff,0xf3a2011c),0xf3a2011c); + checkf(m33cf_fadd(0x01f9ed0f,0x81130914),0x01b06885); + checkf(m33cf_fadd(0xb2ce6eb7,0x325aff32),0xb241de3c); + checkf(m33cf_fsub(0xc8c2cfa1,0xaca3309c),0xc8c2cfa1); + checkf(m33cf_fsub(0xe1e2656e,0x311fb841),0xe1e2656e); + checkf(m33cf_fsub(0xbb5b7ea5,0x2e393a3c),0xbb5b7ea5); + checkf(m33cf_fsub(0x04047b97,0x07c5cd1a),0x87c4c423); + checkf(m33cf_fsub(0xda4c2f9b,0xda13370e),0xd963e234); + checkf(m33cf_fsub(0x06325a1d,0xd9ccae75),0x59ccae75); + checkf(m33cf_fsub(0x001f6b55,0x71efb885),0xf1efb885); + checkf(m33cf_fsub(0x3eafa278,0x7d3bc3af),0xfd3bc3af); + checkf(m33cf_fsub(0xe8203c86,0x3d93556b),0xe8203c86); + checkf(m33cf_fsub(0xa5f8dbf1,0xc3f00090),0x43f00090); + checkf(m33cf_fmul(0x8009dc76,0x7cb46e28),0x80000000); + checkf(m33cf_fmul(0x2e3ba1b3,0x0fa7a191),0x00000000); + checkf(m33cf_fmul(0xf0c99917,0xf0c7ff9a),0x7f800000); + checkf(m33cf_fmul(0x41b2a69c,0xc14000be),0xc385fd7a); + checkf(m33cf_fmul(0x765c15f1,0x0aad9b08),0x4195401c); + checkf(m33cf_fmul(0xea3a2755,0xcc8ba580),0x774b1767); + checkf(m33cf_fmul(0xe0368e14,0xbdc000de),0x5e88eb2d); + checkf(m33cf_fmul(0x832fe859,0x8217ff9f),0x00000000); + checkf(m33cf_fmul(0x00f19200,0xe3752d1a),0xa4e75b49); + checkf(m33cf_fmul(0x42d1061e,0x63a8a510),0x6709b2ca); + checkf(m33cf_fdiv_fast(0xbe891ac7,0x779000b4),0x8673bca3); + checkf(m33cf_fdiv_fast(0x06cd4e3a,0x8075c830),0xff800000); + checkf(m33cf_fdiv_fast(0x1fca4821,0x9f084021),0xc03e0865); + checkf(m33cf_fdiv_fast(0x036f1348,0x715ba87b),0x00000000); + checkf(m33cf_fdiv_fast(0x403c6064,0xbe000057),0xc1bc5fe4); + checkf(m33cf_fdiv_fast(0x009bf1e5,0xbe5000a0),0x81bfee10); + checkf(m33cf_fdiv_fast(0x507bac6d,0x946acd7e),0xfb89326b); + checkf(m33cf_fdiv_fast(0x0810656a,0x880448ea),0xbf8bb812); + checkf(m33cf_fdiv_fast(0x16e368e6,0x965dc974),0xc0033ebf); + checkf(m33cf_fdiv_fast(0x72a7e095,0x6ba01097),0x46863f59); + checkf(m33cf_fadd(0x83e2ed1d,0x00d5c831),0x83df95fc); + checkf(m33cf_fadd(0xe4ddd608,0xb9587489),0xe4ddd608); + checkf(m33cf_fadd(0x6f337823,0xc0679a9f),0x6f337823); + checkf(m33cf_fadd(0x49a367e6,0x3f4679ba),0x49a367ec); + checkf(m33cf_fadd(0xd1307f4d,0xaf17b226),0xd1307f4d); + checkf(m33cf_fadd(0xbdf2106c,0x49a6a874),0x49a6a873); + checkf(m33cf_fadd(0xf3eacf1b,0x52634887),0xf3eacf1b); + checkf(m33cf_fadd(0x6f33647b,0x0442ab37),0x6f33647b); + checkf(m33cf_fadd(0x4cdb9e7a,0x7d301bff),0x7d301bff); + checkf(m33cf_fadd(0x4e1abca7,0x57441d4c),0x57441d73); + checkf(m33cf_fsub(0x8391af63,0xfee57d3d),0x7ee57d3d); + checkf(m33cf_fsub(0x2508aef8,0x1bd43e41),0x2508aedd); + checkf(m33cf_fsub(0x47fe76b7,0x9131d5b0),0x47fe76b7); + checkf(m33cf_fsub(0x5d3119e5,0xd16c2f47),0x5d3119e6); + checkf(m33cf_fsub(0xe39f668c,0x1f0dabef),0xe39f668c); + checkf(m33cf_fsub(0x1e6d2035,0x3bdab1d6),0xbbdab1d6); + checkf(m33cf_fsub(0xb5fde6fa,0x1a379480),0xb5fde6fa); + checkf(m33cf_fsub(0x225bb239,0xfeff8ff3),0x7eff8ff3); + checkf(m33cf_fsub(0x844054a3,0x2122b279),0xa122b279); + checkf(m33cf_fsub(0x5a04757e,0x56caed2b),0x5a02dfa4); + checkf(m33cf_fmul(0x4cb93c51,0xd3c0275f),0xe10b09ba); + checkf(m33cf_fmul(0x3f390c21,0x64abdb95),0x647873a6); + checkf(m33cf_fmul(0x56bd6b48,0x04a56d68),0x1bf4ce32); + checkf(m33cf_fmul(0xa3367c5f,0x59e18108),0xbda0bf4a); + checkf(m33cf_fmul(0x55939e8d,0x29b3443a),0x3fcebe68); + checkf(m33cf_fmul(0xd9fe416a,0x4e18e879),0xe897ddba); + checkf(m33cf_fmul(0x4c0712bd,0xfe8f0d4e),0xff800000); + checkf(m33cf_fmul(0xbdcb53f9,0x7b5292ea),0xf9a73f92); + checkf(m33cf_fmul(0x290fc5cc,0x8d7fcbed),0x80000000); + checkf(m33cf_fmul(0x98abd414,0x595cce6e),0xb29434d0); + checkf(m33cf_fdiv_fast(0x19fec05d,0x198926d6),0x3fedc0ae); + checkf(m33cf_fdiv_fast(0xd3f6c6ef,0xeb89ccae),0x27e53a49); + checkf(m33cf_fdiv_fast(0xe929f69d,0x5dd3860a),0xcacdb375); + checkf(m33cf_fdiv_fast(0xceef0386,0x3a2a3aa2),0xd433b89f); + checkf(m33cf_fdiv_fast(0xf3e76a98,0x859a5a67),0x7f800000); + checkf(m33cf_fdiv_fast(0x2ade013a,0x42dbe607),0x278139dc); + checkf(m33cf_fdiv_fast(0x7676da5e,0x48e1ff79),0x6d0bcfd4); + checkf(m33cf_fdiv_fast(0x42a137e4,0x5c054bdf),0x261ad000); + checkf(m33cf_fdiv_fast(0x358e8442,0x4a4c7e5a),0x2ab269aa); + checkf(m33cf_fdiv_fast(0xf72429ca,0xdc475d3a),0x5a52cc93); + checkf(m33cf_fsqrt_fast(0xc100dc14),0xffc00000); + checkf(m33cf_fsqrt_fast(0x2a2eaa04),0x34d374f7); + checkf(m33cf_fsqrt_fast(0x6e9ff12a),0x570f151a); + checkf(m33cf_fsqrt_fast(0xae37c4b7),0xffc00000); + checkf(m33cf_fsqrt_fast(0x47584a58),0x436b4f1d); + checkf(m33cf_fsqrt_fast(0xebca1f1e),0xffc00000); + checkf(m33cf_fsqrt_fast(0xba92914d),0xffc00000); + checkf(m33cf_fsqrt_fast(0xdb304a6d),0xffc00000); + checkf(m33cf_fsqrt_fast(0x92a72ec1),0xffc00000); + checkf(m33cf_fsqrt_fast(0x936f9320),0xffc00000); +#endif + + checkd(m33cf_dadd(0x000000fc75a5900aULL,0x5bc7667ff4f5aed4ULL),0x5bc7667ff4f5aed4ULL); + checkd(m33cf_dadd(0x3b795f9a7971afcaULL,0x3b795f7a89f1afcaULL),0x3b895f8a81b1afcaULL); + checkd(m33cf_dadd(0x800c3012be12e063ULL,0x0007ffffffffffb2ULL),0x0000000000000000ULL); + checkd(m33cf_dadd(0xf2ebeaef727ecb8cULL,0xe919ba322b0d6abeULL),0xf2ebeaef727ecb8cULL); + checkd(m33cf_dadd(0xf318c8542dbf290fULL,0x7318c84fdc68b825ULL),0xf1f14559c3a80000ULL); + checkd(m33cf_dadd(0xe9cafb8dc44950d0ULL,0x000081e7baa8971aULL),0xe9cafb8dc44950d0ULL); + checkd(m33cf_dadd(0xffb51396c4a74144ULL,0x0006ec693b58bedeULL),0xffb51396c4a74144ULL); + checkd(m33cf_dadd(0x8cb46a68a3f226a7ULL,0xb73c729a98a91e3cULL),0xb73c729a98a91e3cULL); + checkd(m33cf_dadd(0x16d2eaf7f2850dc1ULL,0x96d2cf06aaf78c08ULL),0x165bf1478d81b900ULL); + checkd(m33cf_dadd(0x7fecab31e7006bc2ULL,0xffec71829182845fULL),0x7f7cd7aabef3b180ULL); + checkd(m33cf_dsub(0x7fe80001bfc46633ULL,0xc01c0000dfe2337aULL),0x7fe80001bfc46633ULL); + checkd(m33cf_dsub(0x956bc258e14cf502ULL,0x956bc257257e217bULL),0x942bbced38700000ULL); + checkd(m33cf_dsub(0x1304f931164a0dc4ULL,0x1c3725edf809d211ULL),0x9c3725edf809d211ULL); + checkd(m33cf_dsub(0x8cb8000dd190a395ULL,0x4ae40006e8c85189ULL),0xcae40006e8c85189ULL); + checkd(m33cf_dsub(0x800000304a84d45aULL,0x0c32000000000026ULL),0x8c32000000000026ULL); + checkd(m33cf_dsub(0xf2b4699998abeef8ULL,0xeb07d9b004a574ddULL),0xf2b4699998abeef8ULL); + checkd(m33cf_dsub(0x3fdfe7b9d8d1dbffULL,0x800d7094d9d8d639ULL),0x3fdfe7b9d8d1dbffULL); + checkd(m33cf_dsub(0xb4e058de3e8b4acaULL,0x803f94b600000001ULL),0xb4e058de3e8b4acaULL); + checkd(m33cf_dsub(0x8ddfdbe97e292ab1ULL,0x4b9c6fda25efa7e6ULL),0xcb9c6fda25efa7e6ULL); + checkd(m33cf_dsub(0x9cfebf98a0150dc2ULL,0x1cceb5d8a0150dc3ULL),0x9d014b29da0bd7bdULL); + checkd(m33cf_dmul(0x7eee03dd737c3204ULL,0xc19afd2262fa8aa9ULL),0xfff0000000000000ULL); + checkd(m33cf_dmul(0x80760ca8a50d4410ULL,0x807512348901231bULL),0x0000000000000000ULL); + checkd(m33cf_dmul(0x7ca0d01a0450b53dULL,0x7ca0cf355c70652fULL),0x7ff0000000000000ULL); + checkd(m33cf_dmul(0x0ea698eb5b8a7c9eULL,0x0d0fffffffffff0fULL),0x0000000000000000ULL); + checkd(m33cf_dmul(0xba4565707f05766dULL,0x2c5e39f11066eb37ULL),0xa6b435d75666263eULL); + checkd(m33cf_dmul(0xf2cd3698d8928584ULL,0x8ba3e96d6434a1b9ULL),0x3e822d8426f335d6ULL); + checkd(m33cf_dmul(0x7b386a737bf6693dULL,0xfff70000000000ecULL),0xffff0000000000ecULL); + checkd(m33cf_dmul(0x407f0007866747d5ULL,0xe0408003c333a303ULL),0xe0cff80f0cd052ebULL); + checkd(m33cf_dmul(0x8142be0e6bff63ceULL,0x8135ac3ae2fe4078ULL),0x0000000000000000ULL); + checkd(m33cf_dmul(0x4d1f3420ca65f2baULL,0x8000282866063841ULL),0x8000000000000000ULL); + checkd(m33cf_ddiv_fast(0x94885bb8363252b5ULL,0x9484cbb8363252b6ULL),0x3ff2bdae4b39ea58ULL); + checkd(m33cf_ddiv_fast(0x7112caa0922ef96aULL,0x7112c703422ef96aULL),0x3ff0031472b5f708ULL); + checkd(m33cf_ddiv_fast(0x803795fc115579cfULL,0x00251828182845f3ULL),0xc001e3ca5352423eULL); + checkd(m33cf_ddiv_fast(0x9098cf9d1d63a8a6ULL,0x0000bce378acc9edULL),0xfff0000000000000ULL); + checkd(m33cf_ddiv_fast(0x76eb74d4755d9e90ULL,0x56da74d4755d9e40ULL),0x60009ad22a263295ULL); + checkd(m33cf_ddiv_fast(0xb7ac4ff81ab5acd6ULL,0x3770052042a6f0c2ULL),0xc02c46e8ee4dcde4ULL); + checkd(m33cf_ddiv_fast(0x9f7b7105213fc016ULL,0x9f7b7105206fc017ULL),0x3ff00000007946b7ULL); + checkd(m33cf_ddiv_fast(0x155302277af2c615ULL,0x0052a52fdf6ae145ULL),0x54f04fc7152639a7ULL); + checkd(m33cf_ddiv_fast(0x55544fdcabf6c324ULL,0x7f398c80174fa929ULL),0x160970d87e92ac22ULL); + checkd(m33cf_ddiv_fast(0x92a415a76b37d7d2ULL,0x0200640000000000ULL),0xd0939b1df01b2df3ULL); + checkd(m33cf_dadd(0x3dd4731301475eafULL,0xde02f10226d652e5ULL),0xde02f10226d652e5ULL); + checkd(m33cf_dadd(0x1a031fc739b5b31cULL,0xe23b24be4b0200bfULL),0xe23b24be4b0200bfULL); + checkd(m33cf_dadd(0x4baad04027dc41beULL,0xefe184a8db9b5e28ULL),0xefe184a8db9b5e28ULL); + checkd(m33cf_dadd(0xa97a312516d84984ULL,0xe87c4e53da594b0bULL),0xe87c4e53da594b0bULL); + checkd(m33cf_dadd(0x65f94cdbf4e1655bULL,0xeb08d78147a5fa0cULL),0xeb08d78147a5fa0cULL); + checkd(m33cf_dadd(0xd758e560b9f8515eULL,0x40167af8bfabbfc8ULL),0xd758e560b9f8515eULL); + checkd(m33cf_dadd(0x3177a00dd7f30cfaULL,0x14ce136ab4488ffbULL),0x3177a00dd7f30cfaULL); + checkd(m33cf_dadd(0xe2de834ef78df600ULL,0xe9709814970e2cb1ULL),0xe9709814970e2cb1ULL); + checkd(m33cf_dadd(0x88ad647a702f0bedULL,0x2c0af4057a3c4795ULL),0x2c0af4057a3c4795ULL); + checkd(m33cf_dadd(0xb7dd95bbcbfdd773ULL,0x531893debd8fbf97ULL),0x531893debd8fbf97ULL); + checkd(m33cf_dsub(0x7ba38f5e7b843460ULL,0xf0b3823de05b22b4ULL),0x7ba38f5e7b843460ULL); + checkd(m33cf_dsub(0xee5169f2e74a0f18ULL,0xd501efe1254788b3ULL),0xee5169f2e74a0f18ULL); + checkd(m33cf_dsub(0x69a4707a9a0e8faeULL,0xb2f0883420b659dbULL),0x69a4707a9a0e8faeULL); + checkd(m33cf_dsub(0x427f8d2ef8b19474ULL,0x3a5d0ad508f37fedULL),0x427f8d2ef8b19474ULL); + checkd(m33cf_dsub(0x32a9c51a3d565d85ULL,0x86600a23c10b178aULL),0x32a9c51a3d565d85ULL); + checkd(m33cf_dsub(0x07dac3387f06fa0cULL,0x5c733002a61b620dULL),0xdc733002a61b620dULL); + checkd(m33cf_dsub(0x43d6c9f6fdb3d1b3ULL,0xba69f6160840b2b1ULL),0x43d6c9f6fdb3d1b3ULL); + checkd(m33cf_dsub(0x4293bb41f9808440ULL,0x2482605096e85ffeULL),0x4293bb41f9808440ULL); + checkd(m33cf_dsub(0x83337a590422130bULL,0x7a45cb63b68f1999ULL),0xfa45cb63b68f1999ULL); + checkd(m33cf_dsub(0x122533912d6612c9ULL,0x1b08519e5f8f78b5ULL),0x9b08519e5f8f78b5ULL); + checkd(m33cf_dmul(0xd0bd40b470b385cdULL,0xabfa84fccb01cb46ULL),0x3cc83e249b03d547ULL); + checkd(m33cf_dmul(0x740cc7981c80fddaULL,0x90c53fcc12a6a097ULL),0xc4e31c5c4f5c9ba4ULL); + checkd(m33cf_dmul(0x43290fa64e05e998ULL,0xad4bb7fa2bb564b9ULL),0xb085b549bd618756ULL); + checkd(m33cf_dmul(0xf8fd9c8c9b0bd944ULL,0x4f4a1743e96370a8ULL),0xfff0000000000000ULL); + checkd(m33cf_dmul(0x0c3cdfc8888b644fULL,0x43223d92356f971eULL),0x0f70756f504cf5dcULL); + checkd(m33cf_dmul(0x640b87064cb6c260ULL,0x5d9aabe9efed6024ULL),0x7ff0000000000000ULL); + checkd(m33cf_dmul(0x8718f6339a5eb7d5ULL,0x5d05b556aad4f81aULL),0xa430ef060c1c1204ULL); + checkd(m33cf_dmul(0xd2325605b52e4bbaULL,0x21bef3dbb44cb312ULL),0xb401bc60793a2186ULL); + checkd(m33cf_dmul(0xa1e31fb000c8768eULL,0x6d10072a62a042f7ULL),0xcf03284086d8733fULL); + checkd(m33cf_dmul(0xc787a9a862f5b946ULL,0xcbdeeaeafe6b567dULL),0x5376dcc440db5e02ULL); + checkd(m33cf_ddiv_fast(0xd1ab78cc3a53310bULL,0x871b22cc627440ffULL),0x7ff0000000000000ULL); + checkd(m33cf_ddiv_fast(0x8c64d3beb627c82bULL,0x8ec3d33d99470d80ULL),0x3d90cf03611e44bcULL); + checkd(m33cf_ddiv_fast(0xf6bfb08f555b9642ULL,0x51560ce4365f67a5ULL),0xe556fe91c490804dULL); + checkd(m33cf_ddiv_fast(0xe2a556ddbf80d538ULL,0x48808e2d782a9962ULL),0xda149f9aa72e3465ULL); + checkd(m33cf_ddiv_fast(0x9646a0875dd00eb0ULL,0x579f2c0d32efbfc3ULL),0x8000000000000000ULL); + checkd(m33cf_ddiv_fast(0x4eb970540e932394ULL,0xc9bc823d173ca6deULL),0xc4ec8dd8577f1941ULL); + checkd(m33cf_ddiv_fast(0x26492979e5664695ULL,0x082cff680d6d2530ULL),0x5e0bc467714a1337ULL); + checkd(m33cf_ddiv_fast(0x12db696de9340939ULL,0xe5632c6e98de9cc0ULL),0x8000000000000000ULL); + checkd(m33cf_ddiv_fast(0x4af31aa7075beb9dULL,0x13f5ee839770ee58ULL),0x76ebdfd4cfc4635bULL); + checkd(m33cf_ddiv_fast(0x3e62ca75a07c1ac2ULL,0xb048d234e122da6dULL),0xce0839c35d7657d1ULL); + checkd(m33cf_dsqrt_fast(0x56d82e2279837d7bULL),0x4b63ab5aaabcb779ULL); + checkd(m33cf_dsqrt_fast(0xfc6998b66a2a51deULL),0xfff8000000000000ULL); + checkd(m33cf_dsqrt_fast(0x2c0cc3149408dcc9ULL),0x35fe567d3c418723ULL); + checkd(m33cf_dsqrt_fast(0x1f71e22e323600e6ULL),0x2fb0ea62598ef070ULL); + checkd(m33cf_dsqrt_fast(0x71a6cf9286fdea03ULL),0x58cb047c625fe761ULL); + checkd(m33cf_dsqrt_fast(0x307b55796f027243ULL),0x3834e9a8788bda68ULL); + checkd(m33cf_dsqrt_fast(0x10518d57b7b32094ULL),0x2820c212d75b45adULL); + checkd(m33cf_dsqrt_fast(0x85d55765699fc337ULL),0xfff8000000000000ULL); + checkd(m33cf_dsqrt_fast(0x030a70b7171e4c51ULL),0x217d166dff1d7836ULL); + checkd(m33cf_dsqrt_fast(0x5284145a8007521fULL),0x493959345ef6a420ULL); + + if(rc==0) puts("Pass"); + else puts("Fail"); +} diff --git a/test/pico_float_test/pico_double_test.c b/test/pico_float_test/pico_double_test.c index 6c095e7af..530b3ff93 100644 --- a/test/pico_float_test/pico_double_test.c +++ b/test/pico_float_test/pico_double_test.c @@ -19,6 +19,8 @@ #include "pico/stdlib.h" #include "inttypes.h" +#define test_assert(x) ({ if (!(x)) { printf("Assertion failed: ");puts(#x);printf(" at " __FILE__ ":%d\n", __LINE__); exit(-1); } }) + extern int __aeabi_dcmpun(double a, double b); #if __arm__ @@ -282,7 +284,7 @@ int test_dcmpun() { return 0; } -#define assert_nan(a) assert(isnan(a)) +#define assert_nan(a) test_assert(isnan(a)) #define check_nan(a) ({ assert_nan(a); a; }) double __aeabi_i2d(int32_t); @@ -314,10 +316,11 @@ double __real_trunc(double); double __real_ldexp(double, int); double __real_fmod(double, double); -#define EPSILON 1e-9 -#define assert_close(a, b) assert(((b - a) < EPSILON || (a - b) < EPSILON) || (isinf(a) && isinf(b) && (a < 0) == (b < 0))) -#define check1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); assert(r == r2); r; }) -#define check2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); assert(r == r2); r; }) +#define FRAC ((double)(1ull << 50)) +#define allowed_range(a) (fabs(a) / FRAC) +#define assert_close(a, b) test_assert((fabs(a - b) <= allowed_range(a) || ({ printf(" error: %f != %f\n", a, b); 0; })) || (isinf(a) && isinf(b) && (a < 0) == (b < 0))) +#define check1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); test_assert(r == r2); r; }) +#define check2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); test_assert(r == r2); r; }) #define check_close1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); if (isnan(p0)) assert_nan(r); else assert_close(r, r2); r; }) #define check_close2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); if (isnan(p0) || isnan(p1)) assert_nan(r); else assert_close(r, r2); r; }) #else @@ -361,7 +364,8 @@ int main() { printf("POW %10.18f\n", check_close2(pow, x, x)); printf("TRUNC %10.18f\n", check_close1(trunc, x)); printf("LDEXP %10.18f\n", check_close2(ldexp, x, x)); - printf("FMOD %10.18f\n", check_close2(fmod, x, 3.0f)); + // todo come pack + // printf("FMOD %10.18f\n", check_close2(fmod, x, 3.0f)); double s, c; sincos(x, &s, &c); printf("SINCOS %10.18f %10.18f\n", s, c); @@ -455,18 +459,18 @@ int main() { } for(double x = -4294967296.f * 4294967296.f * 2.f; x<=-0.5f; x/=2.f) { printf("d2i64 %f->%lld\n", x, (int64_t)x); - if (x < INT64_MIN) { + if (x <= (double) INT64_MIN) { // seems like there is a bug in the gcc version! - assert(__aeabi_d2lz(x) == INT64_MIN); + test_assert(__aeabi_d2lz(x) == INT64_MIN); } else { check1(__aeabi_d2lz, x); } } for(double x = 4294967296.f * 4294967296.f * 2.f; x>=0.5f; x/=2.f) { printf("d2i64 %f->%lld\n", x, (int64_t)x); - if (x >= INT64_MAX) { - // seems like there is a bug in the gcc version! - assert(__aeabi_d2lz(x) == INT64_MAX); + if (x >= (double)INT64_MAX) { + // seems like there is a bug in the clang and gcc versions! + test_assert(__aeabi_d2lz(x) == INT64_MAX); } else { check1(__aeabi_d2lz, x); } @@ -477,10 +481,14 @@ int main() { } for(double x = 4294967296.f * 4294967296.f; x>=0.5f; x/=2.f) { printf("d2i32 %f->%d\n", x, (int32_t)x); - check1(__aeabi_d2iz, x); + if (x >= (double) INT32_MAX - 1 && x <= (double) INT32_MAX + 1) { + // seems like there is a bug in the clang version! + test_assert(__aeabi_d2iz(x) == INT32_MAX); + } else { + check1(__aeabi_d2iz, x); + } } - - for (double x = 1; x < 11; x += 2) { + for (double x = 1; x < 11.0; x += 2.0) { double f = x * x; double g = 1.0 / x; printf("%g %10.18g %10.18g, %10.18g, %10.18g %10.18g\n", x, f, x + 0.37777777777777777777777777777, diff --git a/test/pico_float_test/pico_float_test.c b/test/pico_float_test/pico_float_test.c index 4d45a9abd..ca178474d 100644 --- a/test/pico_float_test/pico_float_test.c +++ b/test/pico_float_test/pico_float_test.c @@ -19,6 +19,7 @@ #include "pico/stdlib.h" #include "inttypes.h" +#define test_assert(x) ({ if (!(x)) { printf("Assertion failed: ");puts(#x);printf(" at " __FILE__ ":%d\n", __LINE__); exit(-1); } }) extern int __aeabi_fcmpun(float a, float b); #if __arm__ @@ -282,7 +283,7 @@ int test_fcmpun() { return 0; } -#define assert_nan(a) assert(isnan(a)) +#define assert_nan(a) test_assert(isnanf(a)) #define check_nan(a) ({ assert_nan(a); a; }) float __aeabi_i2f(int32_t); @@ -294,6 +295,7 @@ int64_t __aeabi_f2lz(float); float __aeabi_fmul(float, float); float __aeabi_fdiv(float, float); #if LIB_PICO_FLOAT_PICO +#if !LIB_PICO_FLOAT_PICO_VFP float __real___aeabi_i2f(int); float __real___aeabi_ui2f(int); float __real___aeabi_l2f(int64_t); @@ -303,6 +305,7 @@ float __real___aeabi_fdiv(float, float); int32_t __real___aeabi_f2iz(float); int64_t __real___aeabi_f2lz(float); float __real_sqrtf(float); +#endif float __real_cosf(float); float __real_sinf(float); float __real_tanf(float); @@ -313,12 +316,16 @@ float __real_powf(float, float); float __real_truncf(float); float __real_ldexpf(float, int); float __real_fmodf(float, float); -#define EPSILON 1e-9 -#define assert_close(a, b) assert(((b - a) < EPSILON || (a - b) < EPSILON) || (isinf(a) && isinf(b) && (a < 0) == (b < 0))) -#define check1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); assert(r == r2); r; }) -#define check2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); assert(r == r2); r; }) -#define check_close1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); if (isnan(p0)) assert_nan(r); else assert_close(r, r2); r; }) -#define check_close2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); if (isnan(p0) || isnan(p1)) assert_nan(r); else assert_close(r, r2); r; }) +#define FRAC ((float)(1u << 22)) +#define allowed_range(a) (fabsf(a) / FRAC) +#ifdef LLVM_LIBC_MATH_H +#define isinff isinf +#endif +#define assert_close(a, b) test_assert((fabsf(a - b) <= allowed_range(a) || ({ printf(" error: %f != %f\n", a, b); 0; })) || (isinff(a) && isinff(b) && (a < 0) == (b < 0))) +#define check1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); test_assert(r == r2); r; }) +#define check2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); test_assert(r == r2); r; }) +#define check_close1(func,p0) ({ typeof(p0) r = func(p0), r2 = __CONCAT(__real_, func)(p0); if (isnanf(p0)) assert_nan(r); else assert_close(r, r2); r; }) +#define check_close2(func,p0,p1) ({ typeof(p0) r = func(p0,p1), r2 = __CONCAT(__real_, func)(p0,p1); if (isnanf(p0) || isnanf(p1)) assert_nan(r); else assert_close(r, r2); r; }) #else #define check1(func,p0) func(p0) #define check2(func,p0,p1) func(p0,p1) @@ -386,7 +393,9 @@ int main() { #if 1 for (float x = 0; x < 3; x++) { printf("\n ----- %f\n", x); +#if !LIB_PICO_FLOAT_PICO_VFP printf("FSQRT %10.18f\n", check_close1(sqrtf, x)); +#endif printf("FCOS %10.18f\n", check_close1(cosf, x)); printf("FSIN %10.18f\n", check_close1(sinf, x)); float s, c; @@ -467,6 +476,7 @@ int main() { } #endif +#if !LIB_PICO_FLOAT_PICO_VFP { int32_t y; // for (int32_t x = 0; x>-512; x--) { @@ -509,21 +519,20 @@ int main() { } for(float x = -4294967296.f * 4294967296.f; x>=0.5f; x/=2.f) { printf("f %f->%lld\n", x, (int64_t)x); - if (x < INT64_MIN) { - // seems like there is a bug in the gcc version! - assert(__aeabi_f2lz(x) == INT64_MIN); - } else { - check1(__aeabi_f2lz, x); - } + check1(__aeabi_f2lz, x); } for(float x = 4294967296.f * 4294967296.f * 2.f; x>=0.5f; x/=2.f) { printf("f2i64 %f->%lld\n", x, (int64_t)x); +#if PICO_RP2040 if ((double)x >= (double)INT64_MAX) { - // seems like there is a bug in the gcc version! - assert(__aeabi_f2lz(x) == INT64_MAX); + // seems like there is a bug in the gcc version (which returns UINT64_MAX) + test_assert(__aeabi_f2lz(x) == INT64_MAX); } else { check1(__aeabi_f2lz, x); } +#else + check1(__aeabi_f2lz, x); +#endif } for(float x = -4294967296.f * 4294967296.f; x<=-0.5f; x/=2.f) { printf("d2i32 %f->%d\n", x, (int32_t)x); @@ -531,11 +540,16 @@ int main() { } for(float x = 4294967296.f * 4294967296.f; x>=0.5f; x/=2.f) { printf("d2i32 %f->%d\n", x, (int32_t)x); -#ifdef __clang__ - // seems to be a bug in clang wgere f2iz(2147483648.f) returns -2147483648 - if (x != 2147483648.f) -#endif +#if PICO_RP2040 + if ((double)x >= (double)INT32_MAX) { + // seems like there is a bug in the clang version (which returns INT32_MIN) + test_assert(__aeabi_f2iz(x) == INT32_MAX); + } else { + check1(__aeabi_f2iz, x); + } +#else check1(__aeabi_f2iz, x); +#endif } for (float x = 1; x < 11; x += 2) { @@ -546,6 +560,7 @@ int main() { check2(__aeabi_fmul, x, x); check2(__aeabi_fdiv, 1.0f, x); } +#endif if (fail || test_cfcmpeq() || @@ -627,4 +642,4 @@ int main() { printf("-2 op -1 %d\n", checkd(-2, -1)); #endif } -#endif \ No newline at end of file +#endif diff --git a/test/pico_sem_test/BUILD.bazel b/test/pico_sem_test/BUILD.bazel index c6b51c8c4..911056a62 100644 --- a/test/pico_sem_test/BUILD.bazel +++ b/test/pico_sem_test/BUILD.bazel @@ -5,8 +5,10 @@ cc_binary( testonly = True, srcs = ["pico_sem_test.c"], deps = [ - "//src/common/pico_stdlib", "//src/common/pico_sync", "//test/pico_test", - ], + ] + select({ + "//bazel/constraint:host": ["//src/host/pico_stdlib"], + "//conditions:default": ["//src/rp2_common/pico_stdlib"], + }), ) diff --git a/test/pico_sha256_test/BUILD.bazel b/test/pico_sha256_test/BUILD.bazel new file mode 100644 index 000000000..505f3de81 --- /dev/null +++ b/test/pico_sha256_test/BUILD.bazel @@ -0,0 +1,14 @@ +load("//bazel:defs.bzl", "compatible_with_rp2") + +package(default_visibility = ["//visibility:public"]) + +cc_binary( + name = "pico_sha256_test", + testonly = True, + srcs = ["pico_sha256_test.c"], + target_compatible_with = compatible_with_rp2(), + deps = [ + "//src/rp2_common/pico_sha256", + "//src/rp2_common/pico_stdlib", + ], +) diff --git a/test/pico_sha256_test/CMakeLists.txt b/test/pico_sha256_test/CMakeLists.txt new file mode 100644 index 000000000..8474f3edb --- /dev/null +++ b/test/pico_sha256_test/CMakeLists.txt @@ -0,0 +1,15 @@ +if (NOT TARGET hardware_sha256) + return() +endif() + +add_executable(pico_sha256_test + pico_sha256_test.c + ) +target_link_libraries(pico_sha256_test + pico_stdlib + pico_sha256 +) +target_include_directories(pico_sha256_test PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) +pico_add_extra_outputs(pico_sha256_test) diff --git a/test/pico_sha256_test/pico_sha256_test.c b/test/pico_sha256_test/pico_sha256_test.c new file mode 100644 index 000000000..21e748c2f --- /dev/null +++ b/test/pico_sha256_test/pico_sha256_test.c @@ -0,0 +1,173 @@ +/** + * Copyright (c) 2023 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include "pico/stdlib.h" +#include "pico/sha256.h" + +#define BUFFER_SIZE 10000 + +static void run_test(bool use_dma) { + pico_sha256_state_t state; + + // Test empty + const uint8_t empty_expected[] = { \ + 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 0x9a, 0xfb, \ + 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24, 0x27, 0xae, 0x41, 0xe4, \ + 0x64, 0x9b, 0x93, 0x4c, 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, \ + 0xb8, 0x55 }; + + sha256_result_t result; + + int rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + pico_sha256_update_blocking(&state, NULL, 0); + pico_sha256_finish(&state, &result); + hard_assert(memcmp(empty_expected, &result, SHA256_RESULT_BYTES) == 0); + + // nist 1 + const uint8_t nist_1[] = { 0x61, 0x62, 0x63 }; + const uint8_t nist_1_expected[] = { \ + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, \ + 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, \ + 0x96, 0x17, 0x7a, 0x9c, 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, \ + 0x15, 0xad }; + + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + pico_sha256_update_blocking(&state, nist_1, sizeof(nist_1)); + pico_sha256_finish(&state, &result); + hard_assert(memcmp(nist_1_expected, &result.bytes, SHA256_RESULT_BYTES) == 0); + + // RC4.16 + const uint8_t rc_4_16[] = { \ + 0xde, 0x18, 0x89, 0x41, 0xa3, 0x37, 0x5d, 0x3a, 0x8a, 0x06, \ + 0x1e, 0x67, 0x57, 0x6e, 0x92, 0x6d }; + const uint8_t rc_4_16_expected[] = { \ + 0x06, 0x7c, 0x53, 0x12, 0x69, 0x73, 0x5c, 0xa7, 0xf5, 0x41, \ + 0xfd, 0xac, 0xa8, 0xf0, 0xdc, 0x76, 0x30, 0x5d, 0x3c, 0xad, \ + 0xa1, 0x40, 0xf8, 0x93, 0x72, 0xa4, 0x10, 0xfe, 0x5e, 0xff, \ + 0x6e, 0x4d }; + + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + pico_sha256_update_blocking(&state, rc_4_16, sizeof(rc_4_16)); + pico_sha256_finish(&state, &result); + hard_assert(memcmp(rc_4_16_expected, &result.bytes, SHA256_RESULT_BYTES) == 0); + + // RC4.55 + const uint8_t rc_4_55[] = { \ + 0xde, 0x18, 0x89, 0x41, 0xa3, 0x37, 0x5d, 0x3a, 0x8a, 0x06, \ + 0x1e, 0x67, 0x57, 0x6e, 0x92, 0x6d, 0xc7, 0x1a, 0x7f, 0xa3, \ + 0xf0, 0xcc, 0xeb, 0x97, 0x45, 0x2b, 0x4d, 0x32, 0x27, 0x96, \ + 0x5f, 0x9e, 0xa8, 0xcc, 0x75, 0x07, 0x6d, 0x9f, 0xb9, 0xc5, \ + 0x41, 0x7a, 0xa5, 0xcb, 0x30, 0xfc, 0x22, 0x19, 0x8b, 0x34, \ + 0x98, 0x2d, 0xbb, 0x62, 0x9e }; + const uint8_t rc_4_55_expected[] = { \ + 0x03, 0x80, 0x51, 0xe9, 0xc3, 0x24, 0x39, 0x3b, 0xd1, 0xca, \ + 0x19, 0x78, 0xdd, 0x09, 0x52, 0xc2, 0xaa, 0x37, 0x42, 0xca, \ + 0x4f, 0x1b, 0xd5, 0xcd, 0x46, 0x11, 0xce, 0xa8, 0x38, 0x92, \ + 0xd3, 0x82 }; + + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + pico_sha256_update_blocking(&state, rc_4_55, sizeof(rc_4_55)); + pico_sha256_finish(&state, &result); + hard_assert(memcmp(rc_4_55_expected, result.bytes, SHA256_RESULT_BYTES) == 0); + + // nist 3 + uint8_t *buffer = malloc(10000); + memset(buffer, 0x61, BUFFER_SIZE); + const uint8_t nist_3_expected[] = { \ + 0xcd, 0xc7, 0x6e, 0x5c, 0x99, 0x14, 0xfb, 0x92, 0x81, 0xa1, \ + 0xc7, 0xe2, 0x84, 0xd7, 0x3e, 0x67, 0xf1, 0x80, 0x9a, 0x48, \ + 0xa4, 0x97, 0x20, 0x0e, 0x04, 0x6d, 0x39, 0xcc, 0xc7, 0x11, \ + 0x2c, 0xd0 }; + + uint64_t start = time_us_64(); + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + for(int i = 0; i < 1000000; i += BUFFER_SIZE) { + pico_sha256_update_blocking(&state, buffer, BUFFER_SIZE); + } + pico_sha256_finish(&state, &result); + uint64_t pico_time = time_us_64() - start; + printf("Pico hw time for sha256 of 1M bytes %s DMA %"PRIu64"ms\n", use_dma ? "with" : "without", pico_time / 1000); + hard_assert(memcmp(nist_3_expected, result.bytes, SHA256_RESULT_BYTES) == 0); + + // Cause an error + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + pico_sha256_update(&state, buffer, BUFFER_SIZE); // non-blocking! + if (use_dma) { + assert(dma_channel_is_busy(state.channel)); + dma_channel_wait_for_finish_blocking(state.channel); + dma_channel_configure( + state.channel, + &state.config, + sha256_get_write_addr(), + buffer, + BUFFER_SIZE, + true + ); + dma_channel_wait_for_finish_blocking(state.channel); + } else { + // If we're not using DMA, write a word at a time + for(int i = 0; i < BUFFER_SIZE; i += sizeof(uint32_t)) { + sha256_put_word(*((uint32_t*)(buffer + i))); + } + } + sha256_wait_ready_blocking(); + hard_assert(sha256_err_not_ready()); + pico_sha256_finish(&state, NULL); // passing null to just release the hardware + + // check we can restart + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + + // Check hardware is claimed + pico_sha256_state_t duff = {0}; + rc = pico_sha256_try_start(&duff, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_ERROR_RESOURCE_IN_USE); + rc = pico_sha256_start_blocking_until(&duff, SHA256_BIG_ENDIAN, use_dma, make_timeout_time_ms(100)); + hard_assert(rc == PICO_ERROR_TIMEOUT); + + pico_sha256_update_blocking(&state, nist_1, sizeof(nist_1)); + pico_sha256_finish(&state, &result); + hard_assert(memcmp(nist_1_expected, result.bytes, SHA256_RESULT_BYTES) == 0); + + // Repeat with multiple calls + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + pico_sha256_update_blocking(&state, nist_1+0, 1); + pico_sha256_update_blocking(&state, nist_1+1, 1); + pico_sha256_update_blocking(&state, nist_1+2, 1); + pico_sha256_finish(&state, &result); + hard_assert(memcmp(nist_1_expected, result.bytes, SHA256_RESULT_BYTES) == 0); + + // Test different size of buffer for hardware "not ready" errors + memset(buffer, 0, 1024); + for(int i=0; i <= 1024; i++) { + rc = pico_sha256_start_blocking(&state, SHA256_BIG_ENDIAN, use_dma); + hard_assert(rc == PICO_OK); + pico_sha256_update(&state, buffer, i); + pico_sha256_finish(&state, &result); + } + free(buffer); +} + +int main() { + stdio_init_all(); + + run_test(false); + run_test(true); + + printf("Test passed\n"); +} diff --git a/test/pico_stdio_test/BUILD.bazel b/test/pico_stdio_test/BUILD.bazel index eeffa06a7..420260192 100644 --- a/test/pico_stdio_test/BUILD.bazel +++ b/test/pico_stdio_test/BUILD.bazel @@ -9,8 +9,8 @@ cc_binary( # Host doesn't support PICO_TIME_NO_ALARM_SUPPORT without pico_host_sdl. target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_stdlib", "//src/rp2_common/pico_multicore", + "//src/rp2_common/pico_stdlib", "//test/pico_test", ], ) diff --git a/test/pico_stdio_test/CMakeLists.txt b/test/pico_stdio_test/CMakeLists.txt index 703103989..1a55bc0da 100644 --- a/test/pico_stdio_test/CMakeLists.txt +++ b/test/pico_stdio_test/CMakeLists.txt @@ -1,4 +1,4 @@ -if (NOT PICO_TIME_NO_ALARM_SUPPORT) +if (TARGET pico_multicore AND NOT PICO_TIME_NO_ALARM_SUPPORT) add_executable(pico_stdio_test_uart pico_stdio_test.c) target_link_libraries(pico_stdio_test_uart PRIVATE pico_stdlib pico_test pico_multicore) pico_add_extra_outputs(pico_stdio_test_uart) diff --git a/test/pico_stdlib_test/BUILD.bazel b/test/pico_stdlib_test/BUILD.bazel index edce64f18..7bfa2eab7 100644 --- a/test/pico_stdlib_test/BUILD.bazel +++ b/test/pico_stdlib_test/BUILD.bazel @@ -4,8 +4,16 @@ cc_binary( name = "pico_stdlib_test", testonly = True, srcs = ["pico_stdlib_test.c"], - deps = [ - "//src/common/pico_bit_ops", - "//src/common/pico_stdlib", + deps = select({ + "//bazel/constraint:host": [ + "//src/host/pico_bit_ops", + "//src/host/pico_stdlib", + ], + "//conditions:default": [ + "//src/rp2_common/pico_bit_ops", + "//src/rp2_common/pico_stdlib", + ], + }) + [ + "//src/common/pico_time", # TODO: This header should be #include'ed from source. ], ) diff --git a/test/pico_test/BUILD.bazel b/test/pico_test/BUILD.bazel index cbcd87462..f104b61e9 100644 --- a/test/pico_test/BUILD.bazel +++ b/test/pico_test/BUILD.bazel @@ -3,7 +3,12 @@ package(default_visibility = ["//visibility:public"]) cc_library( name = "pico_test", testonly = True, - hdrs = ["include/pico/test.h"], + hdrs = [ + "include/pico/test.h", + "include/pico/test/xrand.h", + ], includes = ["include"], - deps = ["//src/common/pico_base"], + deps = [ + "//src:pico_platform", + ], ) diff --git a/test/pico_test/include/pico/test.h b/test/pico_test/include/pico/test.h index 07ad53d3e..b444a95b1 100644 --- a/test/pico_test/include/pico/test.h +++ b/test/pico_test/include/pico/test.h @@ -58,4 +58,4 @@ but not sure that is implemented yet. {printf("%s: Success\n", picotest_description); return 0;} -#endif \ No newline at end of file +#endif diff --git a/test/pico_test/include/pico/test/xrand.h b/test/pico_test/include/pico/test/xrand.h new file mode 100644 index 000000000..1ff550f74 --- /dev/null +++ b/test/pico_test/include/pico/test/xrand.h @@ -0,0 +1,87 @@ +// This is a modified version of xoroshiro128++ from: +// +// https://prng.di.unimi.it/xoroshiro128plusplus.c +// +// The code is modified to accept a pointer to a state object rather than +// having a single global state. The algorithm itself is unmodified. Original +// licence header follows: + +/* Written in 2019 by David Blackman and Sebastiano Vigna (vigna@acm.org) + +To the extent possible under law, the author has dedicated all copyright +and related and neighboring rights to this software to the public domain +worldwide. + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR +IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ + +#include + +/* This is xoroshiro128++ 1.0, one of our all-purpose, rock-solid, + small-state generators. It is extremely (sub-ns) fast and it passes all + tests we are aware of, but its state space is large enough only for + mild parallelism. + + For generating just floating-point numbers, xoroshiro128+ is even + faster (but it has a very mild bias, see notes in the comments). + + The state must be seeded so that it is not everywhere zero. If you have + a 64-bit seed, we suggest to seed a splitmix64 generator and use its + output to fill s. */ + + +static inline uint64_t xrand_rotl(const uint64_t x, int k) { + return (x << k) | (x >> (64 - k)); +} + +typedef struct xrand_state { + uint64_t s0; + uint64_t s1; +} xrand_state_t; + +static inline uint64_t xrand_next(xrand_state_t *s) { + const uint64_t s0 = s->s0; + uint64_t s1 = s->s1; + const uint64_t result = xrand_rotl(s0 + s1, 17) + s0; + + s1 ^= s0; + s->s0 = xrand_rotl(s0, 49) ^ s1 ^ (s1 << 21); // a, b + s->s1 = xrand_rotl(s1, 28); // c + + return result; +} + + +/* This is the jump function for the generator. It is equivalent + to 2^64 calls to next(); it can be used to generate 2^64 + non-overlapping subsequences for parallel computations. */ + +static inline void xrand_jump(xrand_state_t *s) { + static const uint64_t JUMP[] = { 0x2bd7a6a6e99c2ddc, 0x0992ccaf6a6fca05 }; + + uint64_t s0 = 0; + uint64_t s1 = 0; + for(int i = 0; i < sizeof JUMP / sizeof *JUMP; i++) + for(int b = 0; b < 64; b++) { + if (JUMP[i] & UINT64_C(1) << b) { + s0 ^= s->s0; + s1 ^= s->s1; + } + xrand_next(s); + } + + s->s0 = s0; + s->s1 = s1; +} + +// Default seed for reproducible test runs: just 128 bits of /dev/urandom +#define XRAND_DEFAULT_INIT (xrand_state_t){0xfb11ab871044f128ull, 0x365396cb1df2665dull} + diff --git a/test/pico_time_test/BUILD.bazel b/test/pico_time_test/BUILD.bazel index 582e426aa..b7a437629 100644 --- a/test/pico_time_test/BUILD.bazel +++ b/test/pico_time_test/BUILD.bazel @@ -11,7 +11,7 @@ cc_binary( # Doesn't appear to work on host builds yet. target_compatible_with = compatible_with_rp2(), deps = [ - "//src/common/pico_stdlib", + "//src/rp2_common/pico_stdlib", "//test/pico_test", ], ) diff --git a/test/pico_time_test/pico_time_test.c b/test/pico_time_test/pico_time_test.c index bd419b67b..987b03f20 100644 --- a/test/pico_time_test/pico_time_test.c +++ b/test/pico_time_test/pico_time_test.c @@ -75,9 +75,9 @@ int main() { alarm_pool_init_default(); PICOTEST_START(); - struct alarm_pool *pools[NUM_TIMERS]; - for(uint i=0; i [MAJOR ] [MINOR ] [ROLLBACK ] [ROLLBACK_ROWS ]) +# Adds a version item to the metadata block, with the given major, minor and +# rollback version, along with the rollback rows. These are appended as arguments +# to PICOTOOL_EXTRA_PROCESS_ARGS if setting the rollback version, or set as compile +# definitions if only setting the major/minor versions. +function(pico_set_binary_version TARGET) + set(oneValueArgs MAJOR MINOR ROLLBACK) + set(multiValueArgs ROWS) + cmake_parse_arguments(PARSE_ARGV 1 SV "" "${oneValueArgs}" "${multiValueArgs}") + # get and set, to inherit list + get_target_property(extra_args ${TARGET} PICOTOOL_EXTRA_PROCESS_ARGS) + if (extra_args) + set_target_properties(${TARGET} PROPERTIES PICOTOOL_EXTRA_PROCESS_ARGS ${extra_args}) + endif() + if (SV_ROLLBACK) + if (SV_MAJOR) + # append major version + set_property(TARGET ${TARGET} APPEND PROPERTY + PICOTOOL_EXTRA_PROCESS_ARGS "--major" "${SV_MAJOR}" + ) + endif() + if (SV_MINOR) + # append minor version + set_property(TARGET ${TARGET} APPEND PROPERTY + PICOTOOL_EXTRA_PROCESS_ARGS "--minor" "${SV_MINOR}" + ) + endif() + # append rollback version + set_property(TARGET ${TARGET} APPEND PROPERTY + PICOTOOL_EXTRA_PROCESS_ARGS "--rollback" "${SV_ROLLBACK}" + ) + if (SV_ROWS) + # append rollback rows + foreach(row IN LISTS SV_ROWS) + set_property(TARGET ${TARGET} APPEND PROPERTY + PICOTOOL_EXTRA_PROCESS_ARGS "${row}" + ) + endforeach() + endif() + else() + if (SV_MAJOR) + # set major version + target_compile_definitions(${TARGET} PRIVATE PICO_CRT0_VERSION_MAJOR=${SV_MAJOR}) + endif() + if (SV_MINOR) + # append minor version + target_compile_definitions(${TARGET} PRIVATE PICO_CRT0_VERSION_MINOR=${SV_MINOR}) + endif() + endif() +endfunction() + +# pico_set_uf2_family(TARGET FAMILY) +# Set the UF2 family to use when creating the UF2. +# This sets PICOTOOL_UF2_FAMILY to FAMILY. +function(pico_set_uf2_family TARGET FAMILY) + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_UF2_FAMILY ${FAMILY} + ) +endfunction() + +# pico_sign_binary(TARGET [SIGFILE]) +# Sign the target binary with the given PEM signature. This sets +# PICOTOOL_SIGN_OUTPUT to true, PICOTOOL_SIGFILE to SIGFILE (if specified), +# and PICOTOOL_OTP_FILE to ${TARGET}.otp.json (if not already set). To +# specify a common SIGFILE for multiple targets, the SIGFILE property can be +# set for a given scope, and then the SIGFILE argument is optional. +function(pico_sign_binary TARGET) + # Enforce signing through target properties + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_SIGN_OUTPUT true + ) + if (ARGC EQUAL 2) + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_SIGFILE ${ARGV1} + ) + else() + get_target_property(sig_file ${TARGET} PICOTOOL_SIGFILE) + if (NOT sig_file) + message(FATAL_ERROR "Signature file not set for ${TARGET}") + endif() + endif() + get_target_property(otp_file ${TARGET} PICOTOOL_OTP_FILE) + if (NOT otp_file) + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_OTP_FILE "${TARGET}.otp.json" + ) + endif() +endfunction() + +# pico_hash_binary(TARGET) +# Hash the target binary. This sets PICOTOOL_HASH_OUTPUT to true. +function(pico_hash_binary TARGET) + # Enforce hashing through target properties + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_HASH_OUTPUT true + ) +endfunction() + +# pico_embed_pt_in_binary(TARGET PTFILE) +# Create the specified partition table from JSON, and embed it in the +# block loop. This sets PICOTOOL_EMBED_PT to PTFILE. +function(pico_embed_pt_in_binary TARGET PTFILE) + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_EMBED_PT ${PTFILE} + ) +endfunction() + +# pico_encrypt_binary(TARGET AESFILE [SIGFILE]) +# Encrypt the target binary with the given AES key (should be a binary +# file containing 32 bytes of a random key), and sign the encrypted binary. +# This sets PICOTOOL_AESFILE to AESFILE, and PICOTOOL_ENC_SIGFILE to SIGFILE +# if present, else PICOTOOL_SIGFILE. +function(pico_encrypt_binary TARGET AESFILE) + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_AESFILE ${AESFILE} + ) + if (ARGC EQUAL 3) + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_ENC_SIGFILE ${ARGV2} + ) + else() + get_target_property(enc_sig_file ${TARGET} PICOTOOL_ENC_SIGFILE) + if (NOT enc_sig_file) + get_target_property(sig_file ${TARGET} PICOTOOL_SIGFILE) + if (NOT sig_file) + message(FATAL_ERROR "Signature file not set for ${TARGET}") + else() + set_target_properties(${TARGET} PROPERTIES + PICOTOOL_ENC_SIGFILE ${sig_file} + ) + endif() + endif() + endif() +endfunction() + +# pico_add_uf2_output(TARGET) +# Add a UF2 output using picotool - must be called after +# all required properties have been set function(pico_add_uf2_output TARGET) + pico_init_picotool() get_target_property(${TARGET}_archive_directory ${TARGET} ARCHIVE_OUTPUT_DIRECTORY) if (${TARGET}_archive_directory) get_filename_component(output_path "${${TARGET}_archive_directory}" @@ -62,16 +377,118 @@ function(pico_add_uf2_output TARGET) else() set(output_path "") endif() - if (NOT ELF2UF2_FOUND) - find_package(pico-sdk-tools "${PICO_SDK_VERSION_MAJOR}.${PICO_SDK_VERSION_MINOR}.${PICO_SDK_VERSION_REVISION}" QUIET CONFIG CMAKE_FIND_ROOT_PATH_BOTH) - if (NOT ELF2UF2_FOUND) - set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${PICO_SDK_PATH}/tools) - find_package(ELF2UF2) + + get_target_property(${TARGET}_uf2_package_addr ${TARGET} PICOTOOL_UF2_PACKAGE_ADDR) + if (${TARGET}_uf2_package_addr) + set(uf2_package_args "-o;${${TARGET}_uf2_package_addr}") + endif() + + get_target_property(extra_uf2_args ${TARGET} PICOTOOL_EXTRA_UF2_ARGS) + if (1) # TODO: A2 only (Errata RP2350-E9) + if (NOT extra_uf2_args) + set(extra_uf2_args "--abs-block") + elseif(NOT "--abs-block" IN_LIST extra_uf2_args) + list(APPEND extra_uf2_args "--abs-block") + endif() + else() + if (NOT extra_uf2_args) + set(extra_uf2_args "") + endif() + endif() + + if (picotool_FOUND) + get_target_property(picotool_family ${TARGET} PICOTOOL_UF2_FAMILY) + if (NOT picotool_family) + if (PICOTOOL_DEFAULT_FAMILY) + set(picotool_family ${PICOTOOL_DEFAULT_FAMILY}) + else() + set(picotool_family ${PICO_PLATFORM}) + endif() endif() + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND picotool + ARGS uf2 convert + --quiet + ${uf2_package_args} + $ + ${output_path}$>,$,$>.uf2 + --family ${picotool_family} + ${extra_uf2_args} + COMMAND_EXPAND_LISTS + VERBATIM) + endif() +endfunction() + +# Run picotool post-processing on the binary - must be called after +# all required properties have been set +function(picotool_postprocess_binary TARGET) + # Read target properties + get_target_property(picotool_sign_output ${TARGET} PICOTOOL_SIGN_OUTPUT) + if (picotool_sign_output) + list(APPEND picotool_args "--sign") + get_target_property(picotool_sigfile ${TARGET} PICOTOOL_SIGFILE) endif() - if (ELF2UF2_FOUND) + + get_target_property(picotool_hash_output ${TARGET} PICOTOOL_HASH_OUTPUT) + if (picotool_hash_output) + list(APPEND picotool_args "--hash") + endif() + + get_target_property(otp_file ${TARGET} PICOTOOL_OTP_FILE) + if (NOT otp_file) + set(otp_file "") + endif() + get_target_property(uf2_package_addr ${TARGET} PICOTOOL_UF2_PACKAGE_ADDR) + + # Embed PT properties + get_target_property(picotool_embed_pt ${TARGET} PICOTOOL_EMBED_PT) + + # Encryption properties + get_target_property(picotool_aesfile ${TARGET} PICOTOOL_AESFILE) + get_target_property(picotool_enc_sigfile ${TARGET} PICOTOOL_ENC_SIGFILE) + + # Extra args + get_target_property(extra_process_args ${TARGET} PICOTOOL_EXTRA_PROCESS_ARGS) + if (extra_process_args) + list(APPEND picotool_args ${extra_process_args}) + endif() + + pico_init_picotool() + if (picotool_FOUND) + # Embed PT + if (picotool_embed_pt) + add_custom_command(TARGET ${TARGET} POST_BUILD + DEPENDS ${picotool_embed_pt} + COMMAND picotool partition create --quiet ${picotool_embed_pt} $ $ + VERBATIM) + endif() + # Signing/hashing/load maps for packaging + if ( + picotool_sign_output OR + picotool_hash_output OR + uf2_package_addr OR + extra_process_args + ) add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ELF2UF2 $ ${output_path}$>,$,$>.uf2 + DEPENDS ${picotool_sigfile} + COMMAND picotool + ARGS seal + --quiet + $ $ + ${picotool_sigfile} ${otp_file} + ${picotool_args} + COMMAND_EXPAND_LISTS VERBATIM) + endif() + # Encryption + if (picotool_aesfile) + add_custom_command(TARGET ${TARGET} POST_BUILD + DEPENDS ${picotool_enc_sigfile} ${picotool_aesfile} + COMMAND picotool encrypt --quiet --hash --sign $ $ ${picotool_aesfile} ${picotool_enc_sigfile} + VERBATIM) + if (ARGC EQUAL 2) + set(${ARGV1} TRUE PARENT_SCOPE) + endif() + endif() endif() endfunction() diff --git a/tools/FindELF2UF2.cmake b/tools/FindELF2UF2.cmake deleted file mode 100644 index e9ced6825..000000000 --- a/tools/FindELF2UF2.cmake +++ /dev/null @@ -1,45 +0,0 @@ -# Finds (or builds) the ELF2UF2 executable -# -# This will define the following variables -# -# ELF2UF2_FOUND -# -# and the following imported targets -# -# ELF2UF2 -# - -if (NOT ELF2UF2_FOUND) - # todo we would like to use pckgconfig to look for it first - # see https://pabloariasal.github.io/2018/02/19/its-time-to-do-cmake-right/ - - include(ExternalProject) - - set(ELF2UF2_SOURCE_DIR ${PICO_SDK_PATH}/tools/elf2uf2) - set(ELF2UF2_BINARY_DIR ${CMAKE_BINARY_DIR}/elf2uf2) - - set(ELF2UF2_BUILD_TARGET ELF2UF2Build) - set(ELF2UF2_TARGET ELF2UF2) - - if (NOT TARGET ${ELF2UF2_BUILD_TARGET}) - pico_message_debug("ELF2UF2 will need to be built") - ExternalProject_Add(${ELF2UF2_BUILD_TARGET} - PREFIX elf2uf2 - SOURCE_DIR ${ELF2UF2_SOURCE_DIR} - BINARY_DIR ${ELF2UF2_BINARY_DIR} - CMAKE_ARGS "-DCMAKE_MAKE_PROGRAM:FILEPATH=${CMAKE_MAKE_PROGRAM}" - BUILD_ALWAYS 1 # force dependency checking - INSTALL_COMMAND "" - ) - endif() - - set(ELF2UF2_EXECUTABLE ${ELF2UF2_BINARY_DIR}/elf2uf2) - if(NOT TARGET ${ELF2UF2_TARGET}) - add_executable(${ELF2UF2_TARGET} IMPORTED) - endif() - set_property(TARGET ${ELF2UF2_TARGET} PROPERTY IMPORTED_LOCATION - ${ELF2UF2_EXECUTABLE}) - - add_dependencies(${ELF2UF2_TARGET} ${ELF2UF2_BUILD_TARGET}) - set(ELF2UF2_FOUND 1) -endif() diff --git a/tools/FindPioasm.cmake b/tools/FindPioasm.cmake deleted file mode 100644 index d7bebdf10..000000000 --- a/tools/FindPioasm.cmake +++ /dev/null @@ -1,53 +0,0 @@ -# Finds (or builds) the Pioasm executable -# -# This will define the following variables -# -# Pioasm_FOUND -# -# and the following imported targets -# -# Pioasm -# - -if (NOT Pioasm_FOUND) - # todo we would like to use pckgconfig to look for it first - # see https://pabloariasal.github.io/2018/02/19/its-time-to-do-cmake-right/ - - include(ExternalProject) - - set(PIOASM_SOURCE_DIR ${PICO_SDK_PATH}/tools/pioasm) - set(PIOASM_BINARY_DIR ${CMAKE_BINARY_DIR}/pioasm) - - set(PioasmBuild_TARGET PioasmBuild) - set(Pioasm_TARGET Pioasm) - - if (NOT TARGET ${PioasmBuild_TARGET}) - pico_message_debug("PIOASM will need to be built") -# message("Adding external project ${PioasmBuild_Target} in ${CMAKE_CURRENT_LIST_DIR}}") - ExternalProject_Add(${PioasmBuild_TARGET} - PREFIX pioasm - SOURCE_DIR ${PIOASM_SOURCE_DIR} - BINARY_DIR ${PIOASM_BINARY_DIR} - CMAKE_ARGS "-DCMAKE_MAKE_PROGRAM:FILEPATH=${CMAKE_MAKE_PROGRAM}" - CMAKE_CACHE_ARGS "-DPIOASM_EXTRA_SOURCE_FILES:STRING=${PIOASM_EXTRA_SOURCE_FILES}" - BUILD_ALWAYS 1 # force dependency checking - INSTALL_COMMAND "" - ) - endif() - - if (CMAKE_HOST_WIN32) - set(Pioasm_EXECUTABLE ${PIOASM_BINARY_DIR}/pioasm.exe) - else() - set(Pioasm_EXECUTABLE ${PIOASM_BINARY_DIR}/pioasm) - endif() - if(NOT TARGET ${Pioasm_TARGET}) -# message("Adding executable ${Pioasm_Target} in ${CMAKE_CURRENT_LIST_DIR}") - add_executable(${Pioasm_TARGET} IMPORTED) - endif() - set_property(TARGET ${Pioasm_TARGET} PROPERTY IMPORTED_LOCATION - ${Pioasm_EXECUTABLE}) - -# message("EXE is ${Pioasm_EXECUTABLE}") - add_dependencies(${Pioasm_TARGET} ${PioasmBuild_TARGET}) - set(Pioasm_FOUND 1) -endif() diff --git a/tools/Findpicotool.cmake b/tools/Findpicotool.cmake new file mode 100644 index 000000000..0782bcd68 --- /dev/null +++ b/tools/Findpicotool.cmake @@ -0,0 +1,84 @@ +# Finds (or builds) the picotool executable +# +# This will define the following imported targets +# +# picotool +# +cmake_minimum_required(VERSION 3.17) + +if (NOT TARGET picotool) + include(ExternalProject) + + if (DEFINED ENV{PICOTOOL_FETCH_FROM_GIT_PATH} AND (NOT PICOTOOL_FETCH_FROM_GIT_PATH)) + set(PICOTOOL_FETCH_FROM_GIT_PATH $ENV{PICOTOOL_FETCH_FROM_GIT_PATH}) + message("Using PICOTOOL_FETCH_FROM_GIT_PATH from environment ('${PICOTOOL_FETCH_FROM_GIT_PATH}')") + endif () + + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICOTOOL_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICOTOOL_FETCH_FROM_GIT_PATH}" ABSOLUTE) + endif () + + set(picotool_BUILD_TARGET picotoolBuild) + set(picotool_TARGET picotool) + + if (NOT TARGET ${picotool_BUILD_TARGET}) + if (NOT PICOTOOL_FETCH_FROM_GIT_PATH) + message(WARNING + "No installed picotool with version ${picotool_VERSION_REQUIRED} found - building from source\n" + "It is recommended to build and install picotool separately, or to set PICOTOOL_FETCH_FROM_GIT_PATH " + "to a common directory for all your SDK projects" + ) + endif() + + FetchContent_Declare( + picotool + GIT_REPOSITORY https://github.com/raspberrypi/picotool.git + GIT_TAG 2.0.0 + GIT_PROGRESS true + ) + + FetchContent_GetProperties(picotool) + set(picotool_INSTALL_DIR ${FETCHCONTENT_BASE_DIR} CACHE PATH "Directory where picotool has been installed" FORCE) + if (NOT picotool_POPULATED) + message("Downloading Picotool") + FetchContent_Populate(picotool) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + + add_custom_target(picotoolForceReconfigure + ${CMAKE_COMMAND} -E touch_nocreate "${CMAKE_SOURCE_DIR}/CMakeLists.txt" + VERBATIM) + + ExternalProject_Add(${picotool_BUILD_TARGET} + PREFIX picotool + SOURCE_DIR ${picotool_SOURCE_DIR} + BINARY_DIR ${picotool_BINARY_DIR} + INSTALL_DIR ${picotool_INSTALL_DIR} + DEPENDS picotoolForceReconfigure + CMAKE_ARGS + "--no-warn-unused-cli" + "-DCMAKE_MAKE_PROGRAM:FILEPATH=${CMAKE_MAKE_PROGRAM}" + "-DPICO_SDK_PATH:FILEPATH=${PICO_SDK_PATH}" + "-DPICOTOOL_NO_LIBUSB=1" + "-DPICOTOOL_FLAT_INSTALL=1" + "-DCMAKE_INSTALL_PREFIX=${picotool_INSTALL_DIR}" + "-DCMAKE_RULE_MESSAGES=OFF" # quieten the build + "-DCMAKE_INSTALL_MESSAGE=NEVER" # quieten the install + BUILD_ALWAYS 1 # force dependency checking + EXCLUDE_FROM_ALL TRUE + TEST_COMMAND + ${picotool_INSTALL_DIR}/picotool/picotool + version ${picotool_VERSION_REQUIRED} + TEST_AFTER_INSTALL TRUE + ) + endif() + + set(picotool_EXECUTABLE ${picotool_INSTALL_DIR}/picotool/picotool) + add_executable(${picotool_TARGET} IMPORTED GLOBAL) + set_property(TARGET ${picotool_TARGET} PROPERTY IMPORTED_LOCATION + ${picotool_EXECUTABLE}) + + add_dependencies(${picotool_TARGET} ${picotool_BUILD_TARGET}) +endif() diff --git a/tools/Findpioasm.cmake b/tools/Findpioasm.cmake new file mode 100644 index 000000000..a5a547671 --- /dev/null +++ b/tools/Findpioasm.cmake @@ -0,0 +1,52 @@ +# Finds (or builds) the pioasm executable +# +# This will define the following imported targets +# +# pioasm +# + +if (NOT TARGET pioasm) + # todo we would like to use pckgconfig to look for it first + # see https://pabloariasal.github.io/2018/02/19/its-time-to-do-cmake-right/ + + include(ExternalProject) + + set(PIOASM_SOURCE_DIR ${PICO_SDK_PATH}/tools/pioasm) + set(PIOASM_BINARY_DIR ${CMAKE_BINARY_DIR}/pioasm) + set(PIOASM_INSTALL_DIR ${CMAKE_BINARY_DIR}/pioasm-install CACHE PATH "Directory where pioasm has been installed" FORCE) + + set(pioasmBuild_TARGET pioasmBuild) + set(pioasm_TARGET pioasm) + + if (NOT TARGET ${pioasmBuild_TARGET}) + pico_message_debug("PIOASM will need to be built") +# message("Adding external project ${pioasmBuild_Target} in ${CMAKE_CURRENT_LIST_DIR}}") + ExternalProject_Add(${pioasmBuild_TARGET} + PREFIX pioasm + SOURCE_DIR ${PIOASM_SOURCE_DIR} + BINARY_DIR ${PIOASM_BINARY_DIR} + INSTALL_DIR ${PIOASM_INSTALL_DIR} + CMAKE_ARGS + "--no-warn-unused-cli" + "-DCMAKE_MAKE_PROGRAM:FILEPATH=${CMAKE_MAKE_PROGRAM}" + "-DPIOASM_FLAT_INSTALL=1" + "-DCMAKE_INSTALL_PREFIX=${PIOASM_INSTALL_DIR}" + "-DCMAKE_RULE_MESSAGES=OFF" # quieten the build + "-DCMAKE_INSTALL_MESSAGE=NEVER" # quieten the install + CMAKE_CACHE_ARGS "-DPIOASM_EXTRA_SOURCE_FILES:STRING=${PIOASM_EXTRA_SOURCE_FILES}" + BUILD_ALWAYS 1 # force dependency checking + EXCLUDE_FROM_ALL TRUE + ) + endif() + + if (CMAKE_HOST_WIN32) + set(pioasm_EXECUTABLE ${PIOASM_INSTALL_DIR}/pioasm/pioasm.exe) + else() + set(pioasm_EXECUTABLE ${PIOASM_INSTALL_DIR}/pioasm/pioasm) + endif() + add_executable(${pioasm_TARGET} IMPORTED GLOBAL) + set_property(TARGET ${pioasm_TARGET} PROPERTY IMPORTED_LOCATION + ${pioasm_EXECUTABLE}) + + add_dependencies(${pioasm_TARGET} ${pioasmBuild_TARGET}) +endif() diff --git a/tools/bazel_build.py b/tools/bazel_build.py new file mode 100755 index 000000000..a25eaeccd --- /dev/null +++ b/tools/bazel_build.py @@ -0,0 +1,197 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2024 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# A script that verifies various Bazel build configurations succeed. + +import logging +import os +import sys + +from bazel_common import ( + SDK_ROOT, + override_picotool_arg, + parse_common_args, + print_framed_string, + run_bazel, + setup_logging, +) + + +BUILD_CONFIGURATIONS = ( + { + "name": "host", + "args": (), + "extra_targets": ( + "@picotool//:picotool", + "//tools/pioasm:pioasm", + ), + "exclusions": frozenset( + ( + "//test/cmsis_test:cmsis_test", + "//test/hardware_irq_test:hardware_irq_test", + "//test/hardware_pwm_test:hardware_pwm_test", + "//test/hardware_sync_spin_lock_test:hardware_sync_spin_lock_test", + "//test/kitchen_sink:kitchen_sink", + "//test/kitchen_sink:kitchen_sink_cpp", + "//test/kitchen_sink:kitchen_sink_lwip_poll", + "//test/kitchen_sink:kitchen_sink_lwip_background", + "//test/pico_divider_test:pico_divider_test", + "//test/pico_divider_test:pico_divider_nesting_test", + "//test/pico_float_test:pico_double_test", + "//test/pico_float_test:pico_float_test", + "//test/pico_sha256_test:pico_sha256_test", + "//test/pico_stdio_test:pico_stdio_test", + "//test/pico_time_test:pico_time_test", + + # Pretty much only Picotool and pioasm build on Windows. + "//..." if os.name == "nt" else "", + "//test/pico_sem_test:pico_sem_test" if os.name == "nt" else "", + "//test/pico_stdlib_test:pico_stdlib_test" if os.name == "nt" else "", + + ) + ), + "run_targets": (""), + }, + { + "name": "rp2040", + "args": ("--platforms=//bazel/platform:rp2040",), + "extra_targets": (), + "exclusions": frozenset( + ( + "//test/kitchen_sink:kitchen_sink_lwip_poll", + "//test/kitchen_sink:kitchen_sink_lwip_background", + # hardware_sha256 doesn't appear to work on RP2040. + "//test/pico_sha256_test:pico_sha256_test", + ) + ), + }, + { + "name": "rp2350", + "args": ("--platforms=//bazel/platform:rp2350",), + "extra_targets": (), + "exclusions": frozenset( + ( + "//test/kitchen_sink:kitchen_sink_lwip_poll", + "//test/kitchen_sink:kitchen_sink_lwip_background", + ) + ), + }, + { + "name": "rp2040 clang", + "args": ( + "--platforms=//bazel/platform:rp2040", + "--@pico-sdk//bazel/config:PICO_TOOLCHAIN=clang", + ), + "extra_targets": (), + "exclusions": frozenset( + ( + "//test/kitchen_sink:kitchen_sink_lwip_poll", + "//test/kitchen_sink:kitchen_sink_lwip_background", + # hardware_sha256 doesn't appear to work on RP2040. + "//test/pico_sha256_test:pico_sha256_test", + ) + ), + }, + { + "name": "rp2350 clang", + "args": ( + "--platforms=//bazel/platform:rp2350", + "--@pico-sdk//bazel/config:PICO_TOOLCHAIN=clang", + ), + "extra_targets": (), + "exclusions": frozenset( + ( + "//test/kitchen_sink:kitchen_sink_lwip_poll", + "//test/kitchen_sink:kitchen_sink_lwip_background", + ) + ), + }, + { + "name": "Pico W", + "args": ( + "--platforms=//bazel/platform:rp2040", + "--@pico-sdk//bazel/config:PICO_BOARD=pico_w", + ), + "extra_targets": (), + "exclusions": frozenset( + ( + # hardware_sha256 doesn't appear to work on RP2040. + "//test/pico_sha256_test:pico_sha256_test", + ) + ), + }, +) + + +def _find_tests(picotool_dir): + """Explicitly lists out every test binary in //tests.""" + all_tests = ( + run_bazel( + ( + "query", + "kind(cc_binary, //test/...)", + "--output=label", + override_picotool_arg(picotool_dir) if picotool_dir else "", + ), + text=True, + check=True, + capture_output=True, + ) + .stdout.strip() + .splitlines() + ) + # Some tests are behind a transition. + return [t.replace("_actual", "") for t in all_tests] + + +def build_all_configurations(picotool_dir): + default_build_targets = [ + "//...", + # Tests are explicitly built by name so we can catch compatibilty + # regressions that cause them to vanish from the wildcard build. + *_find_tests(picotool_dir), + ] + failed_builds = [] + for config in BUILD_CONFIGURATIONS: + print_framed_string(f"Building {config['name']} configuration...") + build_targets = [ + t for t in default_build_targets if t not in config["exclusions"] + ] + build_targets.extend(config["extra_targets"]) + + args = list(config["args"]) + if picotool_dir: + args.append(override_picotool_arg(picotool_dir)) + + result = run_bazel( + ( + "build", + *args, + *build_targets, + ), + ) + if result.returncode != 0: + failed_builds.append(config["name"]) + print() + + if failed_builds: + print_framed_string("ERROR: One or more builds failed.") + for build in failed_builds: + print(f" * FAILED: {build} build") + return 1 + + print_framed_string("All builds successfully passed!") + return 0 + + +def main(): + setup_logging() + args = parse_common_args() + return build_all_configurations(args.picotool_dir) + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/tools/bazel_common.py b/tools/bazel_common.py new file mode 100644 index 000000000..487044a46 --- /dev/null +++ b/tools/bazel_common.py @@ -0,0 +1,113 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2024 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Common helpers and variables shared across Bazel-related Python scripts. + +import argparse +import logging +import os +from pathlib import Path +import shlex +import shutil +import subprocess + + +_LOG = logging.getLogger(__file__) + +SCRIPT_DIR = os.path.dirname(os.path.realpath(__file__)) + +SDK_ROOT = subprocess.run( + ( + "git", + "rev-parse", + "--show-toplevel", + ), + cwd=SCRIPT_DIR, + text=True, + check=True, + capture_output=True, +).stdout.strip() + + +def parse_common_args(): + parser = argparse.ArgumentParser() + parser.add_argument( + "--picotool-dir", + help="Use a local copy of Picotool rather than the dynamically fetching it", + default=None, + type=Path, + ) + return parser.parse_args() + +def override_picotool_arg(picotool_dir): + return f"--override_module=picotool={picotool_dir.resolve()}" + + +def bazel_command() -> str: + """Return the path to bazelisk or bazel.""" + if shutil.which("bazelisk"): + return "bazelisk" + if shutil.which("bazel"): + return "bazel" + + raise FileNotFoundError( + "Cannot find 'bazel' or 'bazelisk' in the current system PATH" + ) + + +def run_bazel(args, check=False, **kwargs): + command = ( + bazel_command(), + *args, + ) + _LOG.info("Running Bazel command: %s", shlex.join(command)) + proc = subprocess.run( + command, + cwd=SDK_ROOT, + **kwargs, + ) + if proc.returncode != 0: + _LOG.error("Command invocation failed with return code %d!", proc.returncode) + _LOG.error( + "Failing command: %s", + " ".join(shlex.quote(str(arg)) for arg in args), + ) + if kwargs.get("capture_output", False): + output = ( + proc.stderr if isinstance(proc.stderr, str) else proc.stderr.decode() + ) + _LOG.error( + "Output:\n%s", + output, + ) + if check: + raise subprocess.CalledProcessError( + returncode=proc.returncode, + cmd=command, + output=proc.stdout, + stderr=proc.stderr, + ) + return proc + + +def print_framed_string(s): + """Frames a string of text and prints it to highlight script steps.""" + header_spacer = "#" * (len(s) + 12) + print(header_spacer) + print("### " + s + " ###") + print(header_spacer) + + +def setup_logging(): + log_levels = [ + (logging.ERROR, "\x1b[31m[ERROR]\x1b[0m"), + (logging.WARNING, "\x1b[33m[WARNING]\x1b[0m"), + (logging.INFO, "\x1b[35m[INFO]\x1b[0m"), + (logging.DEBUG, "\x1b[34m[DEBUG]\x1b[0m"), + ] + for level, level_text in log_levels: + logging.addLevelName(level, level_text) + logging.basicConfig(format="%(levelname)s %(message)s", level=logging.DEBUG) diff --git a/tools/check_source_files_in_bazel_build.py b/tools/check_source_files_in_bazel_build.py new file mode 100755 index 000000000..5717916d9 --- /dev/null +++ b/tools/check_source_files_in_bazel_build.py @@ -0,0 +1,210 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2024 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Check Bazel build file source coverage. Reports files that: +# - Are in the repo but not included in a BUILD.bazel file. +# - Are referenced in a BUILD.bazel file but are not present. +# +# Usage: +# python tools/check_source_files_in_bazel_build.py +# +# Run from anywhere in the pico-sdk repo. + +import logging +from pathlib import Path +import shlex +import subprocess +from typing import ( + Container, + Iterable, + List, + Optional, + Set, +) +import sys + +from bazel_common import ( + SDK_ROOT, + bazel_command, + override_picotool_arg, + parse_common_args, + setup_logging, +) + +_LOG = logging.getLogger(__file__) + +CPP_HEADER_EXTENSIONS = ( + ".h", + ".hpp", + ".hxx", + ".h++", + ".hh", + ".H", +) +CPP_SOURCE_EXTENSIONS = ( + ".c", + ".cpp", + ".cxx", + ".c++", + ".cc", + ".C", + ".S", + ".inc", + ".inl", +) + +IGNORED_FILE_PATTERNS = ( + # Doxygen only files. + "**/index.h", + "**/doc.h", +) + + +def get_paths_from_command(source_dir: Path, *args, **kwargs) -> Set[Path]: + """Runs a command and reads Bazel //-style paths from it.""" + process = subprocess.run( + args, check=False, capture_output=True, cwd=source_dir, **kwargs + ) + + if process.returncode: + _LOG.error("Command invocation failed with return code %d!", process.returncode) + _LOG.error( + "Command: %s", + " ".join(shlex.quote(str(arg)) for arg in args), + ) + _LOG.error( + "Output:\n%s", + process.stderr.decode(), + ) + sys.exit(1) + + files = set() + + for line in process.stdout.splitlines(): + path = line.strip().lstrip(b"/").replace(b":", b"/").decode() + files.add(Path(path)) + + return files + + +def check_bazel_build_for_files( + bazel_extensions_to_check: Container[str], + files: Iterable[Path], + bazel_dirs: Iterable[Path], + picotool_dir: Optional[Path], +) -> List[Path]: + """Checks that source files are in the Bazel builds. + + Args: + bazel_extensions_to_check: which file suffixes to look for in Bazel + files: the files that should be checked + bazel_dirs: directories in which to run bazel query + + Returns: + a list of missing files; will be empty if there were no missing files + """ + + # Collect all paths in the Bazel builds files. + bazel_build_source_files: Set[Path] = set() + pictool_override = override_picotool_arg(picotool_dir) if picotool_dir else "" + for directory in bazel_dirs: + bazel_build_source_files.update( + get_paths_from_command( + directory, bazel_command(), "query", pictool_override, 'kind("source file", //...:*)', + ) + ) + missing_from_bazel: List[Path] = [] + referenced_in_bazel_missing: List[Path] = [] + + if not bazel_dirs: + _LOG.error("No bazel directories to check.") + raise RuntimeError + + for path in (p for p in files if p.suffix in bazel_extensions_to_check): + if path not in bazel_build_source_files: + missing_from_bazel.append(path) + + for path in ( + p for p in bazel_build_source_files if p.suffix in bazel_extensions_to_check + ): + if path not in files: + referenced_in_bazel_missing.append(path) + + if missing_from_bazel: + _LOG.warning( + "Files not included in the Bazel build:\n\n%s\n", + "\n".join(" " + str(x) for x in sorted(missing_from_bazel)), + ) + + if referenced_in_bazel_missing: + _LOG.warning( + "Files referenced in the Bazel build that are missing:\n\n%s\n", + "\n".join(" " + str(x) for x in sorted(referenced_in_bazel_missing)), + ) + + return missing_from_bazel + referenced_in_bazel_missing + + +def git_ls_files_by_extension(file_suffixes: Iterable[str]) -> Iterable[Path]: + """List git source files. + + Returns: A list of files matching the provided extensions. + """ + git_command = ["git", "ls-files"] + for pattern in file_suffixes: + git_command.append("*" + pattern) + + bazel_file_list = subprocess.run( + git_command, + cwd=SDK_ROOT, + text=True, + check=True, + capture_output=True, + ).stdout + + bazel_files = [Path(f) for f in bazel_file_list.splitlines()] + return bazel_files + + +def check_sources_in_bazel_build(picotool_dir) -> int: + # List files using git ls-files + all_source_files = git_ls_files_by_extension( + CPP_HEADER_EXTENSIONS + CPP_SOURCE_EXTENSIONS + ) + + # Filter out any unwanted files. + ignored_files = [] + for source in all_source_files: + for pattern in IGNORED_FILE_PATTERNS: + if source.match(pattern): + ignored_files.append(source) + _LOG.debug( + "Ignoring files:\n\n%s\n", "\n".join(" " + str(f) for f in ignored_files) + ) + + source_files = list(set(all_source_files) - set(ignored_files)) + + # Check for missing files. + _LOG.info("Checking all source files are accounted for in Bazel.") + missing_files = check_bazel_build_for_files( + bazel_extensions_to_check=CPP_HEADER_EXTENSIONS + CPP_SOURCE_EXTENSIONS, + files=source_files, + bazel_dirs=[Path(SDK_ROOT)], + picotool_dir=picotool_dir, + ) + + if missing_files: + _LOG.error("Missing files found.") + return 1 + + _LOG.info("\x1b[32mSuccess!\x1b[0m All files accounted for in Bazel.") + return 0 + + +if __name__ == "__main__": + setup_logging() + args = parse_common_args() + sys.exit(check_sources_in_bazel_build(args.picotool_dir)) diff --git a/tools/compare_build_systems.py b/tools/compare_build_systems.py old mode 100644 new mode 100755 index d691e50ca..c5762817b --- a/tools/compare_build_systems.py +++ b/tools/compare_build_systems.py @@ -16,8 +16,10 @@ import glob import os import re -import subprocess import sys +from typing import Dict + +from bazel_common import SDK_ROOT CMAKE_FILE_TYPES = ( "**/CMakeLists.txt", @@ -30,21 +32,7 @@ "**/*.BUILD", ) -SCRIPT_DIR = os.path.dirname(os.path.realpath(__file__)) - -SDK_ROOT = subprocess.run( - ( - "git", - "rev-parse", - "--show-toplevel", - ), - cwd=SCRIPT_DIR, - text=True, - check=True, - capture_output=True, -).stdout.strip() - -ATTR_REGEX = re.compile(r',?\s*(?P[^=]+)=(?P[^,]+)') +ATTR_REGEX = re.compile(r",?\s*(?P[^=]+)=(?P[^,]+)") # Sometimes the build systems are supposed to be implemented differently. This # allowlist permits the descriptions to differ between CMake and Bazel. @@ -94,6 +82,16 @@ # TODO: Provide handy rules for PIOASM so users don't have to write out a # bespoke run_binary. "PICO_DEFAULT_PIOASM_OUTPUT_FORMAT", + # Bazel always has picotool. + "PICO_NO_PICOTOOL", + # TODO: Eventualy support. + "PICO_NO_COPRO_DIS", + "PICO_DEFAULT_RP2350_PLATFORM", + "PICO_GCC_TRIPLE", + "PICO_NO_FLASH", + "PICO_COPY_TO_RAM", + "PICO_RP2350_ARM_S_CONFIG_HEADER_FILES", + "PICO_RP2350_RISCV_CONFIG_HEADER_FILES", ) BAZEL_ONLY_ALLOWLIST = ( @@ -124,13 +122,28 @@ "PICO_BTSTACK_CONFIG", "PICO_LWIP_CONFIG", "PICO_FREERTOS_LIB", + "PICO_MBEDTLS_LIB", + # CMake has PICO_DEFAULT_CLIB, but it's not user-facing. + "PICO_CLIB", + # Selecting default library implementations. + "PICO_MULTICORE_ENABLED", + "PICO_DEFAULT_DOUBLE_IMPL", + "PICO_DEFAULT_FLOAT_IMPL", + "PICO_DEFAULT_DIVIDER_IMPL", + "PICO_DEFAULT_PRINTF_IMPL", + "PICO_DEFAULT_RAND_IMPL", + "PICO_BINARY_INFO_ENABLED", + # Allows selection of clang/gcc when using the dynamically fetched + # toolchains. + "PICO_TOOLCHAIN", ) + @dataclass class Option: name: str description: str - attrs: dict[str, str] + attrs: Dict[str, str] def matches(self, other): matches = (self.name == other.name) and (self.attrs == other.attrs) @@ -141,24 +154,25 @@ def matches(self, other): def FindKnownOptions(option_pattern_matcher, file_paths): pattern = re.compile( - option_pattern_matcher + - r':\s+(?P\w+),\s+(?P[^,]+)(?:,\s+(?P.*))?$') + option_pattern_matcher + + r":\s+(?P\w+),\s+(?P[^,]+)(?:,\s+(?P.*))?$" + ) options = {} for p in file_paths: - with open(p, 'r') as f: + with open(p, "r") as f: for line in f: match = re.search(pattern, line) if not match: continue attrs = { - m.group('key'): m.group('value') - for m in re.finditer(ATTR_REGEX, match.group('attrs')) + m.group("key"): m.group("value") + for m in re.finditer(ATTR_REGEX, match.group("attrs")) } - options[match.group('name')] = Option( - match.group('name'), - match.group('description'), + options[match.group("name")] = Option( + match.group("name"), + match.group("description"), attrs, ) return options @@ -193,31 +207,39 @@ def CompareOptions(bazel_pattern, bazel_files, cmake_pattern, cmake_files): both.update(bazel_options) both.update(cmake_options) for k in both.keys(): - if not OptionsAreEqual(bazel_options.get(k, None), - cmake_options.get(k, None)): + if not OptionsAreEqual(bazel_options.get(k, None), cmake_options.get(k, None)): are_equal = False return are_equal -cmake_files = [ - f for p in CMAKE_FILE_TYPES - for f in glob.glob(p, root_dir=SDK_ROOT, recursive=True) -] -bazel_files = [ - f for p in BAZEL_FILE_TYPES - for f in glob.glob(p, root_dir=SDK_ROOT, recursive=True) -] +def compare_build_systems(): + cmake_files = [ + f + for p in CMAKE_FILE_TYPES + for f in glob.glob(os.path.join(SDK_ROOT, p), recursive=True) + ] + bazel_files = [ + f + for p in BAZEL_FILE_TYPES + for f in glob.glob(os.path.join(SDK_ROOT, p), recursive=True) + ] + + print("[1/2] Checking build system configuration flags...") + build_options_ok = CompareOptions( + "PICO_BAZEL_CONFIG", bazel_files, "PICO_CMAKE_CONFIG", cmake_files + ) + + print("[2/2] Checking build system defines...") + build_defines_ok = CompareOptions( + "PICO_BUILD_DEFINE", bazel_files, "PICO_BUILD_DEFINE", cmake_files + ) -print('[1/2] Checking build system configuration flags...') -build_options_ok = CompareOptions("PICO_BAZEL_CONFIG", bazel_files, - "PICO_CMAKE_CONFIG", cmake_files) + if build_options_ok and build_defines_ok: + print("OK") + return 0 -print('[2/2] Checking build system defines...') -build_defines_ok = CompareOptions("PICO_BUILD_DEFINE", bazel_files, - "PICO_BUILD_DEFINE", cmake_files) + return 1 -if build_options_ok and build_defines_ok: - print("OK") - sys.exit(0) -sys.exit(1) +if __name__ == "__main__": + sys.exit(compare_build_systems()) diff --git a/tools/copro_dis.py b/tools/copro_dis.py new file mode 100644 index 000000000..285bc7be2 --- /dev/null +++ b/tools/copro_dis.py @@ -0,0 +1,318 @@ +#!/usr/bin/env python3 +import argparse, re + +parser = argparse.ArgumentParser(description="Disassemble RCP instructions in DIS file") + +parser.add_argument("input", help="Input DIS") +parser.add_argument("output", help="Output DIS") + +args = parser.parse_args() + +fin = open(args.input, mode="r") +contents = fin.read() +fin.close() + +def gpiodir(val): + val = int(val) + if val//4 == 0: + return "out" + elif val//4 == 1: + return "oe" + elif val//4 == 2: + return "in" + else: + return "unknown" + +def gpiohilo(val): + val = int(val) + if val % 4 == 0: + return "lo_" + gpiodir(val) + elif val % 4 == 1: + return "hi_" + gpiodir(val) + else: + return "unknown" + +def gpiopxsc(val): + val = int(val) + if val == 0: + return "put" + elif val == 1: + return "xor" + elif val == 2: + return "set" + elif val == 3: + return "clr" + else: + return "unknown" + +def gpioxsc2(val): + val = int(val) + return gpiopxsc(val - 4) + ("2" if val > 4 else "") + +def gpioxsc(val): + val = int(val) + return gpiopxsc(val - 4) + +replacements = [ + # ========================== RCP ========================== + (r'mrc\s*p?7, #?0, (.*), cr?(.*), cr?(.*), [\{#]1}?', lambda m: 'rcp_canary_get {0}, 0x{1:02x} ({1}), delay'.format(m.group(1), int(m.group(2)) * 16 + int(m.group(3)))), + (r'mrc2\s*p?7, #?0, (.*), cr?(.*), cr?(.*), [\{#]1}?', lambda m: 'rcp_canary_get {0}, 0x{1:02x} ({1}), nodelay'.format(m.group(1), int(m.group(2)) * 16 + int(m.group(3)))), + (r'mcr\s*p?7, #?0, (.*), cr?(.*), cr?(.*), [\{#]1}?', lambda m: 'rcp_canary_check {0}, 0x{1:02x} ({1}), delay'.format(m.group(1), int(m.group(2)) * 16 + int(m.group(3)))), + (r'mcr2\s*p?7, #?0, (.*), cr?(.*), cr?(.*), [\{#]1}?', lambda m: 'rcp_canary_check {0}, 0x{1:02x} ({1}), nodelay'.format(m.group(1), int(m.group(2)) * 16 + int(m.group(3)))), + + (r'mrc\s*p?7, #?1, (.*), cr?(.*), cr?(.*), [\{#]0}?', r'rcp_canary_status \1, delay'), + (r'mcr\s*p?7, #?1, (.*), cr?(.*), cr?(.*), [\{#]0}?', r'rcp_bvalid \1, delay'), + (r'mcr2\s*p?7, #?1, (.*), cr?(.*), cr?(.*), [\{#]0}?', r'rcp_bvalid \1, nodelay'), + + (r'mcr\s*p?7, #?2, (.*), cr?(.*), cr?(.*), [\{#]0}?', r'rcp_btrue \1, delay'), + (r'mcr2\s*p?7, #?2, (.*), cr?(.*), cr?(.*), [\{#]0}?', r'rcp_btrue \1, nodelay'), + + (r'mcr\s*p?7, #?3, (.*), cr?(.*), cr?(.*), [\{#]1}?', r'rcp_bfalse \1, delay'), + (r'mcr2\s*p?7, #?3, (.*), cr?(.*), cr?(.*), [\{#]1}?', r'rcp_bfalse \1, nodelay'), + + (r'mcr\s*p?7, #?4, (.*), cr?(.*), cr?(.*), [\{#]0}?', lambda m: 'rcp_count_set 0x{0:02x} ({0}), delay'.format(int(m.group(2)) * 16 + int(m.group(3)))), + (r'mcr2\s*p?7, #?4, (.*), cr?(.*), cr?(.*), [\{#]0}?', lambda m: 'rcp_count_set 0x{0:02x} ({0}), nodelay'.format(int(m.group(2)) * 16 + int(m.group(3)))), + (r'mcr\s*p?7, #?5, (.*), cr?(.*), cr?(.*), [\{#]1}?', lambda m: 'rcp_count_check 0x{0:02x} ({0}), delay'.format(int(m.group(2)) * 16 + int(m.group(3)))), + (r'mcr2\s*p?7, #?5, (.*), cr?(.*), cr?(.*), [\{#]1}?', lambda m: 'rcp_count_check 0x{0:02x} ({0}), nodelay'.format(int(m.group(2)) * 16 + int(m.group(3)))), + + (r'mcrr\s*p?7, #?0, (.*), (.*), cr?(.*)', r'rcp_b2valid \1, \2, delay'), + (r'mcrr2\s*p?7, #?0, (.*), (.*), cr?(.*)', r'rcp_b2valid \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?1, (.*), (.*), cr?(.*)', r'rcp_b2and \1, \2, delay'), + (r'mcrr2\s*p?7, #?1, (.*), (.*), cr?(.*)', r'rcp_b2and \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?2, (.*), (.*), cr?(.*)', r'rcp_b2or \1, \2, delay'), + (r'mcrr2\s*p?7, #?2, (.*), (.*), cr?(.*)', r'rcp_b2or \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?3, (.*), (.*), cr?(.*)', r'rcp_bxorvalid \1, \2, delay'), + (r'mcrr2\s*p?7, #?3, (.*), (.*), cr?(.*)', r'rcp_bxorvalid \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?4, (.*), (.*), cr?(.*)', r'rcp_bxortrue \1, \2, delay'), + (r'mcrr2\s*p?7, #?4, (.*), (.*), cr?(.*)', r'rcp_bxortrue \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?5, (.*), (.*), cr?(.*)', r'rcp_bxorfalse \1, \2, delay'), + (r'mcrr2\s*p?7, #?5, (.*), (.*), cr?(.*)', r'rcp_bxorfalse \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?6, (.*), (.*), cr?(.*)', r'rcp_ivalid \1, \2, delay'), + (r'mcrr2\s*p?7, #?6, (.*), (.*), cr?(.*)', r'rcp_ivalid \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?7, (.*), (.*), cr?(.*)', r'rcp_iequal \1, \2, delay'), + (r'mcrr2\s*p?7, #?7, (.*), (.*), cr?(.*)', r'rcp_iequal \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?8, (.*), (.*), cr?0', r'rcp_salt_core0 \1, \2, delay'), + (r'mcrr2\s*p?7, #?8, (.*), (.*), cr?0', r'rcp_salt_core0 \1, \2, nodelay'), + + (r'mcrr\s*p?7, #?8, (.*), (.*), cr?1', r'rcp_salt_core1 \1, \2, delay'), + (r'mcrr2\s*p?7, #?8, (.*), (.*), cr?1', r'rcp_salt_core1 \1, \2, nodelay'), + + (r'cdp\s*p?7, #?0, cr?0, cr?0, cr?0, [\{#]1}?', r'rcp_panic'), + + # ========================== DCP ========================== + + ('([0-9a-f]{8}:\tee00 0400 \t).*',r'\1dcp_init'), + ('([0-9a-f]{8}:\tee00 0500 \t).*',r'\1dcps_init'), + ('([0-9a-f]{8}:\tee00 0401 \t).*',r'\1dcp_add0'), + ('([0-9a-f]{8}:\tee00 0501 \t).*',r'\1dcps_add0'), + ('([0-9a-f]{8}:\tee10 0401 \t).*',r'\1dcp_add1'), + ('([0-9a-f]{8}:\tee10 0501 \t).*',r'\1dcps_add1'), + ('([0-9a-f]{8}:\tee10 0421 \t).*',r'\1dcp_sub1'), + ('([0-9a-f]{8}:\tee10 0521 \t).*',r'\1dcps_sub1'), + ('([0-9a-f]{8}:\tee20 0401 \t).*',r'\1dcp_sqr0'), + ('([0-9a-f]{8}:\tee20 0501 \t).*',r'\1dcps_sqr0'), + ('([0-9a-f]{8}:\tee80 0402 \t).*',r'\1dcp_norm'), + ('([0-9a-f]{8}:\tee80 0502 \t).*',r'\1dcps_norm'), + ('([0-9a-f]{8}:\tee80 0422 \t).*',r'\1dcp_nrdf'), + ('([0-9a-f]{8}:\tee80 0522 \t).*',r'\1dcps_nrdf'), + ('([0-9a-f]{8}:\tee80 0420 \t).*',r'\1dcp_nrdd'), + ('([0-9a-f]{8}:\tee80 0520 \t).*',r'\1dcps_nrdd'), + ('([0-9a-f]{8}:\tee80 0440 \t).*',r'\1dcp_ntdc'), + ('([0-9a-f]{8}:\tee80 0540 \t).*',r'\1dcps_ntdc'), + ('([0-9a-f]{8}:\tee80 0460 \t).*',r'\1dcp_nrdc'), + ('([0-9a-f]{8}:\tee80 0560 \t).*',r'\1dcps_nrdc'), + ('([0-9a-f]{8}:\tec4(.) (.)400 \t).*',r'\1dcp_wxmd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)500 \t).*',r'\1dcps_wxmd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)401 \t).*',r'\1dcp_wymd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)501 \t).*',r'\1dcps_wymd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)402 \t).*',r'\1dcp_wefd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)502 \t).*',r'\1dcps_wefd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)410 \t).*',r'\1dcp_wxup _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)510 \t).*',r'\1dcps_wxup _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)411 \t).*',r'\1dcp_wyup _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)511 \t).*',r'\1dcps_wyup _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)412 \t).*',r'\1dcp_wxyu _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)512 \t).*',r'\1dcps_wxyu _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)420 \t).*',r'\1dcp_wxms _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)520 \t).*',r'\1dcps_wxms _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)430 \t).*',r'\1dcp_wxmo _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)530 \t).*',r'\1dcps_wxmo _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)440 \t).*',r'\1dcp_wxdd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)540 \t).*',r'\1dcps_wxdd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)450 \t).*',r'\1dcp_wxdq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)550 \t).*',r'\1dcps_wxdq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)460 \t).*',r'\1dcp_wxuc _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)560 \t).*',r'\1dcps_wxuc _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)470 \t).*',r'\1dcp_wxic _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)570 \t).*',r'\1dcps_wxic _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)480 \t).*',r'\1dcp_wxdc _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)580 \t).*',r'\1dcps_wxdc _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)492 \t).*',r'\1dcp_wxfc _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)592 \t).*',r'\1dcps_wxfc _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)4a0 \t).*',r'\1dcp_wxfm _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)5a0 \t).*',r'\1dcps_wxfm _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)4b0 \t).*',r'\1dcp_wxfd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)5b0 \t).*',r'\1dcps_wxfd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)4c0 \t).*',r'\1dcp_wxfq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec4(.) (.)5c0 \t).*',r'\1dcps_wxfq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)410 \t).*',r'\1dcp_rxvd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)510 \t).*',r'\1dcps_rxvd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)430 \t).*',r'\1dcp_rcmp _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)530 \t).*',r'\1dcps_rcmp _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)412 \t).*',r'\1dcp_rdfa _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)512 \t).*',r'\1dcps_rdfa _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)432 \t).*',r'\1dcp_rdfs _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)532 \t).*',r'\1dcps_rdfs _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)452 \t).*',r'\1dcp_rdfm _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)552 \t).*',r'\1dcps_rdfm _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)472 \t).*',r'\1dcp_rdfd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)572 \t).*',r'\1dcps_rdfd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)492 \t).*',r'\1dcp_rdfq _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)592 \t).*',r'\1dcps_rdfq _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)4b2 \t).*',r'\1dcp_rdfg _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)5b2 \t).*',r'\1dcps_rdfg _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)413 \t).*',r'\1dcp_rdic _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)513 \t).*',r'\1dcps_rdic _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)433 \t).*',r'\1dcp_rduc _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tee10 (.)533 \t).*',r'\1dcps_rduc _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)408 \t).*',r'\1dcp_rxmd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)508 \t).*',r'\1dcps_rxmd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)409 \t).*',r'\1dcp_rymd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)509 \t).*',r'\1dcps_rymd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)40a \t).*',r'\1dcp_refd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)50a \t).*',r'\1dcps_refd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)4(.)4 \t).*',r'\1dcp_rxms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tec5(.) (.)5(.)4 \t).*',r'\1dcps_rxms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tec5(.) (.)4(.)5 \t).*',r'\1dcp_ryms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tec5(.) (.)5(.)5 \t).*',r'\1dcps_ryms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tec5(.) (.)411 \t).*',r'\1dcp_rxyh _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)511 \t).*',r'\1dcps_rxyh _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)421 \t).*',r'\1dcp_rymr _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)521 \t).*',r'\1dcps_rymr _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)441 \t).*',r'\1dcp_rxmq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)541 \t).*',r'\1dcps_rxmq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)410 \t).*',r'\1dcp_rdda _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)510 \t).*',r'\1dcps_rdda _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)430 \t).*',r'\1dcp_rdds _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)530 \t).*',r'\1dcps_rdds _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)450 \t).*',r'\1dcp_rddm _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)550 \t).*',r'\1dcps_rddm _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)470 \t).*',r'\1dcp_rddd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)570 \t).*',r'\1dcps_rddd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)490 \t).*',r'\1dcp_rddq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)590 \t).*',r'\1dcps_rddq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)4b0 \t).*',r'\1dcp_rddg _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tec5(.) (.)5b0 \t).*',r'\1dcps_rddg _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)410 \t).*',r'\1dcp_pxvd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)510 \t).*',r'\1dcps_pxvd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)430 \t).*',r'\1dcp_pcmp _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)530 \t).*',r'\1dcps_pcmp _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)412 \t).*',r'\1dcp_pdfa _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)512 \t).*',r'\1dcps_pdfa _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)432 \t).*',r'\1dcp_pdfs _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)532 \t).*',r'\1dcps_pdfs _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)452 \t).*',r'\1dcp_pdfm _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)552 \t).*',r'\1dcps_pdfm _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)472 \t).*',r'\1dcp_pdfd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)572 \t).*',r'\1dcps_pdfd _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)492 \t).*',r'\1dcp_pdfq _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)592 \t).*',r'\1dcps_pdfq _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)4b2 \t).*',r'\1dcp_pdfg _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)5b2 \t).*',r'\1dcps_pdfg _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)413 \t).*',r'\1dcp_pdic _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)513 \t).*',r'\1dcps_pdic _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)433 \t).*',r'\1dcp_pduc _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfe10 (.)533 \t).*',r'\1dcps_pduc _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)408 \t).*',r'\1dcp_pxmd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)508 \t).*',r'\1dcps_pxmd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)409 \t).*',r'\1dcp_pymd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)509 \t).*',r'\1dcps_pymd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)40a \t).*',r'\1dcp_pefd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)50a \t).*',r'\1dcps_pefd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)4(.)4 \t).*',r'\1dcp_pxms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tfc5(.) (.)5(.)4 \t).*',r'\1dcps_pxms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tfc5(.) (.)4(.)5 \t).*',r'\1dcp_pyms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tfc5(.) (.)5(.)5 \t).*',r'\1dcps_pyms _cpu_reg_\3_, _cpu_reg_\2_, #0x\4'), + ('([0-9a-f]{8}:\tfc5(.) (.)411 \t).*',r'\1dcp_pxyh _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)511 \t).*',r'\1dcps_pxyh _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)421 \t).*',r'\1dcp_pymr _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)521 \t).*',r'\1dcps_pymr _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)441 \t).*',r'\1dcp_pxmq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)541 \t).*',r'\1dcps_pxmq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)410 \t).*',r'\1dcp_pdda _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)510 \t).*',r'\1dcps_pdda _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)430 \t).*',r'\1dcp_pdds _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)530 \t).*',r'\1dcps_pdds _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)450 \t).*',r'\1dcp_pddm _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)550 \t).*',r'\1dcps_pddm _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)470 \t).*',r'\1dcp_pddd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)570 \t).*',r'\1dcps_pddd _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)490 \t).*',r'\1dcp_pddq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)590 \t).*',r'\1dcps_pddq _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)4b0 \t).*',r'\1dcp_pddg _cpu_reg_\3_, _cpu_reg_\2_'), + ('([0-9a-f]{8}:\tfc5(.) (.)5b0 \t).*',r'\1dcps_pddg _cpu_reg_\3_, _cpu_reg_\2_'), + ('_cpu_reg_([0-9])_', r'r\1'), + ('_cpu_reg_a_', r'sl'), + ('_cpu_reg_b_', r'fp'), + ('_cpu_reg_c_', r'ip'), + ('_cpu_reg_d_', r'sp'), + ('_cpu_reg_e_', r'lr'), + ('_cpu_reg_f_', r'pc'), + + # ========================== GPIO ========================== + + # OUT and OE mask write instructions + (r'mcr\s*p?0, #?([0-3]), (.*), cr?0, cr?([0145])', lambda m: 'gpioc_{0}_{1} {2}'.format( + gpiohilo(m.group(3)), gpiopxsc(m.group(1)), m.group(2) + )), + (r'mcrr\s*p?0, #?([0-3]), (.*), (.*), cr?([04])', lambda m: 'gpioc_hilo_{0}_{1} {2}, {3}'.format( + gpiodir(m.group(4)), gpiopxsc(m.group(1)), m.group(2), m.group(3) + )), + # Single-bit write instructions + (r'mcrr\s*p?0, #?([4-7]), (.*), (.*), cr?([04])', lambda m: 'gpioc_bit_{0}_{1} {2}, {3}'.format( + gpiodir(m.group(4)), gpioxsc2(m.group(1)), m.group(2), m.group(3) + )), + (r'mcr\s*p?0, #?([5-7]), (.*), cr?0, cr?([04])', lambda m: 'gpioc_bit_{0}_{1} {2}'.format( + gpiodir(m.group(3)), gpioxsc(m.group(1)), m.group(2) + )), + # Indexed mask write instructions -- write to a dynamically selected 32-bit + (r'mcrr\s*p?0, #?(8|9|10|11), (.*), (.*), cr?([04])', lambda m: 'gpioc_index_{0}_{1} {2}, {3}'.format( + gpiodir(m.group(4)), gpiopxsc(int(m.group(1)) - 8), m.group(2), m.group(3) + )), + # Read instructions + (r'mrc\s*p?0, #?0, (.*), cr?0, cr?([014589])', lambda m: 'gpioc_{0}_get {1}'.format( + gpiohilo(m.group(2)), m.group(1) + )), + (r'mrrc\s*p?0, #?0, (.*), (.*), cr?([048])', lambda m: 'gpioc_hilo_{0}_get {1}, {2}'.format( + gpiodir(m.group(3)), m.group(1), m.group(2) + )), +] + +# Add clang DCP replacements +for pat, rep in replacements: + if pat.startswith('([0-9a-f]{8}:\t'): + mid = pat.split('\t')[1] + left, right = mid.split(' ')[0:2] + if len(right) > 6: + new_pat = f"([0-9a-f]{{8}}:\s*{left[2:]} {left[0:2]} {right[4:]} {right[:4]} \s*).*" + new_rep = rep.replace('3', '7') + new_rep = new_rep.replace('4', '3') + new_rep = new_rep.replace('7', '4') + replacements.append((new_pat, new_rep)) + else: + replacements.append((f"([0-9a-f]{{8}}:\s*{left[2:]} {left[0:2]} {right[-2:]} {right[:-2]} \s*).*", rep)) + +for pat, rep in replacements: + contents = re.sub(pat, rep, contents) + +fout = open(args.output, mode="w") +fout.write(contents) +fout.close() diff --git a/tools/elf2uf2/BUILD.bazel b/tools/elf2uf2/BUILD.bazel deleted file mode 100644 index bb2e8edf7..000000000 --- a/tools/elf2uf2/BUILD.bazel +++ /dev/null @@ -1,19 +0,0 @@ -package(default_visibility = ["//visibility:public"]) - -cc_binary( - name = "elf2uf2", - srcs = [ - "elf.h", - "main.cpp", - ], - copts = select({ - "@platforms//os:windows": [], - "//conditions:default": [ - "-Wno-unused-function", - "-Wno-reorder-ctor", - "-Wno-unused-variable", - ], - }), - target_compatible_with = ["//bazel/constraint:host"], - deps = ["//src/common/boot_uf2"], -) diff --git a/tools/elf2uf2/CMakeLists.txt b/tools/elf2uf2/CMakeLists.txt deleted file mode 100644 index 9cd7d4a80..000000000 --- a/tools/elf2uf2/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -cmake_minimum_required(VERSION 3.13...3.27) -project(elf2uf2) - -set(CMAKE_CXX_STANDARD 14) - -add_subdirectory(../../src/common/boot_uf2 boot_uf2_headers) - -add_executable(elf2uf2 main.cpp) -if (WIN32 AND NOT MINGW AND (CMAKE_CXX_COMPILER_ID STREQUAL "Clang")) - target_compile_definitions(elf2uf2 PRIVATE _CRT_SECURE_NO_WARNINGS) -endif() -target_link_libraries(elf2uf2 boot_uf2_headers) diff --git a/tools/elf2uf2/elf.h b/tools/elf2uf2/elf.h deleted file mode 100644 index 32e3dbb40..000000000 --- a/tools/elf2uf2/elf.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _ELF_H -#define _ELF_H - -#include - -#define ELF_MAGIC 0x464c457fu - -#define EM_ARM 0x28u - -#define EF_ARM_ABI_FLOAT_HARD 0x00000400u - -#define PT_LOAD 0x00000001u - -#pragma pack(push, 1) -struct elf_header { - uint32_t magic; - uint8_t arch_class; - uint8_t endianness; - uint8_t version; - uint8_t abi; - uint8_t abi_version; - uint8_t _pad[7]; - uint16_t type; - uint16_t machine; - uint32_t version2; -}; - -struct elf32_header { - struct elf_header common; - uint32_t entry; - uint32_t ph_offset; - uint32_t sh_offset; - uint32_t flags; - uint16_t eh_size; - uint16_t ph_entry_size; - uint16_t ph_num; - uint16_t sh_entry_size; - uint16_t sh_num; - uint16_t sh_str_index; -}; - -struct elf32_ph_entry { - uint32_t type; - uint32_t offset; - uint32_t vaddr; - uint32_t paddr; - uint32_t filez; - uint32_t memsz; - uint32_t flags; - uint32_t align; -}; -#pragma pack(pop) - -#endif \ No newline at end of file diff --git a/tools/elf2uf2/main.cpp b/tools/elf2uf2/main.cpp deleted file mode 100644 index 5245fec36..000000000 --- a/tools/elf2uf2/main.cpp +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include "boot/uf2.h" -#include "elf.h" - -typedef unsigned int uint; - -#define ERROR_ARGS -1 -#define ERROR_FORMAT -2 -#define ERROR_INCOMPATIBLE -3 -#define ERROR_READ_FAILED -4 -#define ERROR_WRITE_FAILED -5 - -#define FLASH_SECTOR_ERASE_SIZE 4096u - -static char error_msg[512]; -static bool verbose; - -static int fail(int code, const char *format, ...) { - va_list args; - va_start(args, format); - vsnprintf(error_msg, sizeof(error_msg), format, args); - va_end(args); - return code; -} - -static int fail_read_error() { - return fail(ERROR_READ_FAILED, "Failed to read input file"); -} - -static int fail_write_error() { - return fail(ERROR_WRITE_FAILED, "Failed to write output file"); -} - -// we require 256 (as this is the page size supported by the device) -#define LOG2_PAGE_SIZE 8u -#define PAGE_SIZE (1u << LOG2_PAGE_SIZE) - -struct address_range { - enum type { - CONTENTS, // may have contents - NO_CONTENTS, // must be uninitialized - IGNORE // will be ignored - }; - address_range(uint32_t from, uint32_t to, type type) : from(from), to(to), type(type) {} - address_range() : address_range(0, 0, IGNORE) {} - type type; - uint32_t to; - uint32_t from; -}; - -typedef std::vector address_ranges; - -#define MAIN_RAM_START 0x20000000u // same as SRAM_BASE in addressmap.h -#define MAIN_RAM_END 0x20042000u // same as SRAM_END in addressmap.h -#define FLASH_START 0x10000000u // same as XIP_MAIN_BASE in addressmap.h -#define FLASH_END 0x15000000u -#define XIP_SRAM_START 0x15000000u // same as XIP_SRAM_BASE in addressmap.h -#define XIP_SRAM_END 0x15004000u // same as XIP_SRAM_END in addressmap.h -#define MAIN_RAM_BANKED_START 0x21000000u // same as SRAM0_BASE in addressmap.h -#define MAIN_RAM_BANKED_END 0x21040000u -#define ROM_START 0x00000000u // same as ROM_BASE in addressmap.h -#define ROM_END 0x00004000u - -const address_ranges rp2040_address_ranges_flash { - address_range(FLASH_START, FLASH_END, address_range::type::CONTENTS), - address_range(MAIN_RAM_START, MAIN_RAM_END, address_range::type::NO_CONTENTS), - address_range(MAIN_RAM_BANKED_START, MAIN_RAM_BANKED_END, address_range::type::NO_CONTENTS) -}; - -const address_ranges rp2040_address_ranges_ram { - address_range(MAIN_RAM_START, MAIN_RAM_END, address_range::type::CONTENTS), - address_range(XIP_SRAM_START, XIP_SRAM_END, address_range::type::CONTENTS), - address_range(ROM_START, ROM_END, address_range::type::IGNORE) // for now we ignore the bootrom if present -}; - -struct page_fragment { - page_fragment(uint32_t file_offset, uint32_t page_offset, uint32_t bytes) : file_offset(file_offset), page_offset(page_offset), bytes(bytes) {} - uint32_t file_offset; - uint32_t page_offset; - uint32_t bytes; -}; - -static int usage() { - fprintf(stderr, "Usage: elf2uf2 (-v) \n"); - return ERROR_ARGS; -} - -static int read_and_check_elf32_header(FILE *in, elf32_header& eh_out) { - if (1 != fread(&eh_out, sizeof(eh_out), 1, in)) { - return fail(ERROR_READ_FAILED, "Unable to read ELF header"); - } - if (eh_out.common.magic != ELF_MAGIC) { - return fail(ERROR_FORMAT, "Not an ELF file"); - } - if (eh_out.common.version != 1 || eh_out.common.version2 != 1) { - return fail(ERROR_FORMAT, "Unrecognized ELF version"); - } - if (eh_out.common.arch_class != 1 || eh_out.common.endianness != 1) { - return fail(ERROR_INCOMPATIBLE, "Require 32 bit little-endian ELF"); - } - if (eh_out.eh_size != sizeof(struct elf32_header)) { - return fail(ERROR_FORMAT, "Invalid ELF32 format"); - } - if (eh_out.common.machine != EM_ARM) { - return fail(ERROR_FORMAT, "Not an ARM executable"); - } - if (eh_out.common.abi != 0) { - return fail(ERROR_INCOMPATIBLE, "Unrecognized ABI"); - } - if (eh_out.flags & EF_ARM_ABI_FLOAT_HARD) { - return fail(ERROR_INCOMPATIBLE, "HARD-FLOAT not supported"); - } - return 0; -} - -int check_address_range(const address_ranges& valid_ranges, uint32_t addr, uint32_t vaddr, uint32_t size, bool uninitialized, address_range &ar) { - for(const auto& range : valid_ranges) { - if (range.from <= addr && range.to >= addr + size) { - if (range.type == address_range::type::NO_CONTENTS && !uninitialized) { - return fail(ERROR_INCOMPATIBLE, "ELF contains memory contents for uninitialized memory at %08x", addr); - } - ar = range; - if (verbose) { - printf("%s segment %08x->%08x (%08x->%08x)\n", uninitialized ? "Uninitialized" : "Mapped", addr, - addr + size, vaddr, vaddr+size); - } - return 0; - } - } - return fail(ERROR_INCOMPATIBLE, "Memory segment %08x->%08x is outside of valid address range for device", addr, addr+size); -} - -int read_elf32_ph_entries(FILE *in, const elf32_header &eh, std::vector& entries) { - if (eh.ph_entry_size != sizeof(elf32_ph_entry)) { - return fail(ERROR_FORMAT, "Invalid ELF32 program header"); - } - if (eh.ph_num) { - entries.resize(eh.ph_num); - if (fseek(in, eh.ph_offset, SEEK_SET)) { - return fail_read_error(); - } - if (eh.ph_num != fread(&entries[0], sizeof(struct elf32_ph_entry), eh.ph_num, in)) { - return fail_read_error(); - } - } - return 0; -} - -int check_elf32_ph_entries(const std::vector& entries, const address_ranges& valid_ranges, std::map>& pages) { - for(const auto & entry : entries) { - if (entry.type == PT_LOAD && entry.memsz) { - address_range ar; - int rc; - uint mapped_size = std::min(entry.filez, entry.memsz); - if (mapped_size) { - rc = check_address_range(valid_ranges, entry.paddr, entry.vaddr, mapped_size, false, ar); - if (rc) return rc; - // we don't download uninitialized, generally it is BSS and should be zero-ed by crt0.S, or it may be COPY areas which are undefined - if (ar.type != address_range::type::CONTENTS) { - if (verbose) printf(" ignored\n"); - continue; - } - uint addr = entry.paddr; - uint remaining = mapped_size; - uint file_offset = entry.offset; - while (remaining) { - uint off = addr & (PAGE_SIZE - 1); - uint len = std::min(remaining, PAGE_SIZE - off); - auto &fragments = pages[addr - off]; // list of fragments - // note if filesz is zero, we want zero init which is handled because the - // statement above creates an empty page fragment list - // check overlap with any existing fragments - for (const auto &fragment : fragments) { - if ((off < fragment.page_offset + fragment.bytes) != - ((off + len) <= fragment.page_offset)) { - fail(ERROR_FORMAT, "In memory segments overlap"); - } - } - fragments.push_back( - page_fragment{file_offset,off,len}); - addr += len; - file_offset += len; - remaining -= len; - } - } - if (entry.memsz > entry.filez) { - // we have some uninitialized data too - rc = check_address_range(valid_ranges, entry.paddr + entry.filez, entry.vaddr + entry.filez, entry.memsz - entry.filez, true, - ar); - if (rc) return rc; - } - } - } - return 0; -} - -int realize_page(FILE *in, const std::vector &fragments, uint8_t *buf, uint buf_len) { - assert(buf_len >= PAGE_SIZE); - for(auto& frag : fragments) { - assert(frag.page_offset >= 0 && frag.page_offset < PAGE_SIZE && frag.page_offset + frag.bytes <= PAGE_SIZE); - if (fseek(in, frag.file_offset, SEEK_SET)) { - return fail_read_error(); - } - if (1 != fread(buf + frag.page_offset, frag.bytes, 1, in)) { - return fail_read_error(); - } - } - return 0; -} - -static bool is_address_valid(const address_ranges& valid_ranges, uint32_t addr) { - for(const auto& range : valid_ranges) { - if (range.from <= addr && range.to > addr) { - return true; - } - } - return false; -} - -static bool is_address_initialized(const address_ranges& valid_ranges, uint32_t addr) { - for(const auto& range : valid_ranges) { - if (range.from <= addr && range.to > addr) { - return address_range::type::CONTENTS == range.type; - } - } - return false; -} - -static bool is_address_mapped(const std::map>& pages, uint32_t addr) { - uint32_t page = addr & ~(PAGE_SIZE - 1); - if (!pages.count(page)) return false; - // todo check actual address within page - return true; -} - -static int determine_binary_type(const elf32_header &eh, const std::vector& entries, bool *ram_style) { - for(const auto &entry : entries) { - if (entry.type == PT_LOAD && entry.memsz) { - uint mapped_size = std::min(entry.filez, entry.memsz); - if (mapped_size) { - // we back convert the entrypoint from a VADDR to a PADDR to see if it originates in flash, and if - // so call THAT a flash binary. - if (eh.entry >= entry.vaddr && eh.entry < entry.vaddr + mapped_size) { - uint32_t effective_entry = eh.entry + entry.paddr - entry.vaddr; - if (is_address_initialized(rp2040_address_ranges_ram, effective_entry)) { - *ram_style = true; - return 0; - } else if (is_address_initialized(rp2040_address_ranges_flash, effective_entry)) { - *ram_style = false; - return 0; - } - } - } - } - } - return fail(ERROR_INCOMPATIBLE, "entry point is not in mapped part of file"); -} - -int elf2uf2(FILE *in, FILE *out) { - elf32_header eh; - std::map> pages; - int rc = read_and_check_elf32_header(in, eh); - bool ram_style = false; - address_ranges valid_ranges = {}; - if (!rc) { - std::vector entries; - rc = read_elf32_ph_entries(in, eh, entries); - if (!rc) { - rc = determine_binary_type(eh, entries, &ram_style); - } - if (!rc) { - if (verbose) { - if (ram_style) { - printf("Detected RAM binary\n"); - } else { - printf("Detected FLASH binary\n"); - } - } - valid_ranges = ram_style ? rp2040_address_ranges_ram : rp2040_address_ranges_flash; - rc = check_elf32_ph_entries(entries, valid_ranges, pages); - } - } - if (rc) return rc; - if (pages.empty()) { - return fail(ERROR_INCOMPATIBLE, "The input file has no memory pages"); - } - uint page_num = 0; - if (ram_style) { - uint32_t expected_ep_main_ram = UINT32_MAX; - uint32_t expected_ep_xip_sram = UINT32_MAX; - for(auto& page_entry : pages) { - if ( ((page_entry.first >= MAIN_RAM_START) && (page_entry.first < MAIN_RAM_END)) && (page_entry.first < expected_ep_main_ram) ) { - expected_ep_main_ram = page_entry.first | 0x1; - } else if ( ((page_entry.first >= XIP_SRAM_START) && (page_entry.first < XIP_SRAM_END)) && (page_entry.first < expected_ep_xip_sram) ) { - expected_ep_xip_sram = page_entry.first | 0x1; - } - } - uint32_t expected_ep = (UINT32_MAX != expected_ep_main_ram) ? expected_ep_main_ram : expected_ep_xip_sram; - if (eh.entry == expected_ep_xip_sram) { - return fail(ERROR_INCOMPATIBLE, "B0/B1 Boot ROM does not support direct entry into XIP_SRAM\n"); - } else if (eh.entry != expected_ep) { - return fail(ERROR_INCOMPATIBLE, "A RAM binary should have an entry point at the beginning: %08x (not %08x)\n", expected_ep, eh.entry); - } - static_assert(0 == (MAIN_RAM_START & (PAGE_SIZE - 1)), ""); - // currently don't require this as entry point is now at the start, we don't know where reset vector is -#if 0 - uint8_t buf[PAGE_SIZE]; - rc = realize_page(in, pages[MAIN_RAM_START], buf, sizeof(buf)); - if (rc) return rc; - uint32_t sp = ((uint32_t *)buf)[0]; - uint32_t ip = ((uint32_t *)buf)[1]; - if (!is_address_mapped(pages, ip)) { - return fail(ERROR_INCOMPATIBLE, "Vector table at %08x is invalid: reset vector %08x is not in mapped memory", - MAIN_RAM_START, ip); - } - if (!is_address_valid(valid_ranges, sp - 4)) { - return fail(ERROR_INCOMPATIBLE, "Vector table at %08x is invalid: stack pointer %08x is not in RAM", - MAIN_RAM_START, sp); - } -#endif - } else { - // Fill in empty dummy uf2 pages to align the binary to flash sectors (except for the last sector which we don't - // need to pad, and choose not to to avoid making all SDK UF2s bigger) - // That workaround is required because the bootrom uses the block number for erase sector calculations: - // https://github.com/raspberrypi/pico-bootrom/blob/c09c7f08550e8a36fc38dc74f8873b9576de99eb/bootrom/virtual_disk.c#L205 - - std::set touched_sectors; - for (auto& page_entry : pages) { - uint32_t sector = page_entry.first / FLASH_SECTOR_ERASE_SIZE; - touched_sectors.insert(sector); - } - - uint32_t last_page = pages.rbegin()->first; - for (uint32_t sector : touched_sectors) { - for (uint32_t page = sector * FLASH_SECTOR_ERASE_SIZE; page < (sector + 1) * FLASH_SECTOR_ERASE_SIZE; page += PAGE_SIZE) { - if (page < last_page) { - // Create a dummy page, if it does not exist yet. note that all present pages are first - // zeroed before they are filled with any contents, so a dummy page will be all zeros. - auto &dummy = pages[page]; - } - } - } - } - uf2_block block; - block.magic_start0 = UF2_MAGIC_START0; - block.magic_start1 = UF2_MAGIC_START1; - block.flags = UF2_FLAG_FAMILY_ID_PRESENT; - block.payload_size = PAGE_SIZE; - block.num_blocks = (uint32_t)pages.size(); - block.file_size = RP2040_FAMILY_ID; - block.magic_end = UF2_MAGIC_END; - for(auto& page_entry : pages) { - block.target_addr = page_entry.first; - block.block_no = page_num++; - if (verbose) { - printf("Page %d / %d %08x%s\n", block.block_no, block.num_blocks, block.target_addr, - page_entry.second.empty() ? " (padding)": ""); - } - memset(block.data, 0, sizeof(block.data)); - rc = realize_page(in, page_entry.second, block.data, sizeof(block.data)); - if (rc) return rc; - if (1 != fwrite(&block, sizeof(uf2_block), 1, out)) { - return fail_write_error(); - } - } - return 0; -} - -int main(int argc, char **argv) { - int arg = 1; - if (arg < argc && !strcmp(argv[arg], "-v")) { - verbose = true; - arg++; - } - if (argc < arg + 2) { - return usage(); - } - const char *in_filename = argv[arg++]; - FILE *in = fopen(in_filename, "rb"); - if (!in) { - fprintf(stderr, "Can't open input file '%s'\n", in_filename); - return ERROR_ARGS; - } - const char *out_filename = argv[arg++]; - FILE *out = fopen(out_filename, "wb"); - if (!out) { - fprintf(stderr, "Can't open output file '%s'\n", out_filename); - return ERROR_ARGS; - } - - int rc = elf2uf2(in, out); - fclose(in); - fclose(out); - if (rc) { - remove(out_filename); - if (error_msg[0]) { - fprintf(stderr, "ERROR: %s\n", error_msg); - } - } - return rc; -} diff --git a/tools/extract_cmake_configs.py b/tools/extract_cmake_configs.py index 9c4f194fa..507429f46 100755 --- a/tools/extract_cmake_configs.py +++ b/tools/extract_cmake_configs.py @@ -123,9 +123,11 @@ def ValidateAttrs(config_attrs, file_path, linenum): if '=' in config_description: raise Exception("For {} at {}:{} the description was set to '{}' - has the description field been omitted?".format(config_name, file_path, linenum, config_description)) if config_description in all_descriptions: - raise Exception("Found description {} at {}:{} but it was already used at {}:{}".format(config_description, file_path, linenum, os.path.join(scandir, all_descriptions[config_description]['filename']), all_descriptions[config_description]['line_number'])) + # relax check for the same header/variable in a different tree + if config_name != all_descriptions[config_description]['config_name'] or filename != all_descriptions[config_description]['filename_only']: + raise Exception("Found description {} at {}:{} but it was already used at {}:{}".format(config_description, file_path, linenum, os.path.join(scandir, all_descriptions[config_description]['filename']), all_descriptions[config_description]['line_number'])) else: - all_descriptions[config_description] = {'config_name': config_name, 'filename': os.path.relpath(file_path, scandir), 'line_number': linenum} + all_descriptions[config_description] = {'config_name': config_name, 'filename': os.path.relpath(file_path, scandir), 'filename_only':filename, 'line_number': linenum} config_attrs = {} prev = None @@ -148,9 +150,11 @@ def ValidateAttrs(config_attrs, file_path, linenum): #print(file_path, config_name, config_attrs) if config_name in all_configs: - raise Exception("Found {} at {}:{} but it was already declared at {}:{}".format(config_name, file_path, linenum, os.path.join(scandir, all_configs[config_name]['filename']), all_configs[config_name]['line_number'])) + # relax check for the same header/variable in a different tree + if filename != all_configs[config_name]['filename_only']: + raise Exception("Found {} at {}:{} but it was already declared at {}:{}".format(config_name, file_path, linenum, os.path.join(scandir, all_configs[config_name]['filename']), all_configs[config_name]['line_number'])) else: - all_configs[config_name] = {'attrs': config_attrs, 'filename': os.path.relpath(file_path, scandir), 'line_number': linenum, 'description': config_description} + all_configs[config_name] = {'attrs': config_attrs, 'filename': os.path.relpath(file_path, scandir), 'filename_only' : filename, 'line_number': linenum, 'description': config_description} for config_name, config_obj in all_configs.items(): @@ -165,4 +169,9 @@ def ValidateAttrs(config_attrs, file_path, linenum): writer.writeheader() for config_name, config_obj in sorted(all_configs.items()): - writer.writerow({'name': config_name, 'location': '/{}:{}'.format(config_obj['filename'], config_obj['line_number']), 'description': config_obj['description'], **config_obj['attrs']}) + # kinda ugly, but good enough for now without messing with TSV + if 'docref' in config_obj['attrs']: + desc = "{} (see <<{}>>)".format(config_obj['description'], config_obj['attrs']['docref']) + else: + desc = config_obj['description'] + writer.writerow({'name': config_name, 'location': '/{}:{}'.format(config_obj['filename'], config_obj['line_number']), 'description': desc, **config_obj['attrs']}) diff --git a/tools/extract_configs.py b/tools/extract_configs.py index edb90994e..c95da4084 100755 --- a/tools/extract_configs.py +++ b/tools/extract_configs.py @@ -134,9 +134,11 @@ def ValidateAttrs(config_attrs, file_path, linenum): if '=' in config_description: raise Exception("For {} at {}:{} the description was set to '{}' - has the description field been omitted?".format(config_name, file_path, linenum, config_description)) if config_description in all_descriptions: - raise Exception("Found description {} at {}:{} but it was already used at {}:{}".format(config_description, file_path, linenum, os.path.join(scandir, all_descriptions[config_description]['filename']), all_descriptions[config_description]['line_number'])) + # relax check for the same header/variable in a different tree + if config_name != all_descriptions[config_description]['config_name'] or filename != all_descriptions[config_description]['filename_only']: + raise Exception("Found description {} at {}:{} but it was already used at {}:{}".format(config_description, file_path, linenum, os.path.join(scandir, all_descriptions[config_description]['filename']), all_descriptions[config_description]['line_number'])) else: - all_descriptions[config_description] = {'config_name': config_name, 'filename': os.path.relpath(file_path, scandir), 'line_number': linenum} + all_descriptions[config_description] = {'config_name': config_name, 'filename': os.path.relpath(file_path, scandir), 'filename_only':filename, 'line_number': linenum} config_attrs = {} prev = None @@ -159,9 +161,11 @@ def ValidateAttrs(config_attrs, file_path, linenum): #print(file_path, config_name, config_attrs) if config_name in all_configs: - raise Exception("Found {} at {}:{} but it was already declared at {}:{}".format(config_name, file_path, linenum, os.path.join(scandir, all_configs[config_name]['filename']), all_configs[config_name]['line_number'])) + # relax check for the same header/variable in a different tree + if filename != all_configs[config_name]['filename_only']: + raise Exception("Found {} at {}:{} but it was already declared at {}:{}".format(config_name, file_path, linenum, os.path.join(scandir, all_configs[config_name]['filename']), all_configs[config_name]['line_number'])) else: - all_configs[config_name] = {'attrs': config_attrs, 'filename': os.path.relpath(file_path, scandir), 'line_number': linenum, 'description': config_description} + all_configs[config_name] = {'attrs': config_attrs, 'filename': os.path.relpath(file_path, scandir), 'filename_only' : filename, 'line_number': linenum, 'description': config_description} else: m = DEFINE_RE.match(line) if m: diff --git a/tools/pioasm/BUILD.bazel b/tools/pioasm/BUILD.bazel index c9fd60150..266bce68a 100644 --- a/tools/pioasm/BUILD.bazel +++ b/tools/pioasm/BUILD.bazel @@ -17,8 +17,17 @@ cc_library( "pio_assembler.h", "pio_disassembler.cpp", "pio_disassembler.h", + "pio_enums.h", "pio_types.h", ], + copts = select({ + "@rules_cc//cc/compiler:msvc-cl": ["/std:c++20"], + "//conditions:default": ["-Wno-sign-compare"], + }), + defines = select({ + "@rules_cc//cc/compiler:msvc-cl": ["YY_NO_UNISTD_H=1"], + "//conditions:default": [], + }), includes = [ ".", "gen", diff --git a/tools/pioasm/CMakeLists.txt b/tools/pioasm/CMakeLists.txt index 1c451eeaf..0106da640 100644 --- a/tools/pioasm/CMakeLists.txt +++ b/tools/pioasm/CMakeLists.txt @@ -1,6 +1,10 @@ cmake_minimum_required(VERSION 3.13...3.27) project(pioasm CXX) +if (NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE Release) +endif() + set(CMAKE_CXX_STANDARD 11) if (PIOASM_GENERATE_PARSER) @@ -27,6 +31,7 @@ target_sources(pioasm PRIVATE json_output.cpp) target_sources(pioasm PRIVATE ada_output.cpp) target_sources(pioasm PRIVATE go_output.cpp) target_sources(pioasm PRIVATE ${PIOASM_EXTRA_SOURCE_FILES}) +target_sources(pioasm PRIVATE pio_types.h) if ((CMAKE_CXX_COMPILER_ID STREQUAL "GNU") AND (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL "7") AND @@ -46,3 +51,51 @@ if (MSVC) target_compile_options(pioasm PRIVATE "/std:c++latest") endif() + +# allow installing to flat dir +include(GNUInstallDirs) +if (PIOASM_FLAT_INSTALL) + set(INSTALL_CONFIGDIR pioasm) + set(INSTALL_BINDIR pioasm) +else() + set(INSTALL_CONFIGDIR ${CMAKE_INSTALL_LIBDIR}/cmake/pioasm) + set(INSTALL_BINDIR ${CMAKE_INSTALL_BINDIR}) +endif() + +# allow `make install` +install(TARGETS pioasm + EXPORT pioasm-targets + RUNTIME DESTINATION ${INSTALL_BINDIR} +) + +#Export the targets to a script +install(EXPORT pioasm-targets + FILE + pioasmTargets.cmake + DESTINATION + ${INSTALL_CONFIGDIR} +) + +include(../../pico_sdk_version.cmake) +set(PACKAGE_VERSION "${PICO_SDK_VERSION_MAJOR}.${PICO_SDK_VERSION_MINOR}.${PICO_SDK_VERSION_REVISION}") + +#Create a ConfigVersion.cmake file +include(CMakePackageConfigHelpers) +write_basic_package_version_file( + ${CMAKE_CURRENT_BINARY_DIR}/pioasmConfigVersion.cmake + VERSION ${PACKAGE_VERSION} + COMPATIBILITY ExactVersion + ARCH_INDEPENDENT +) + +configure_package_config_file(${CMAKE_CURRENT_LIST_DIR}/cmake/pioasmConfig.cmake + ${CMAKE_CURRENT_BINARY_DIR}/pioasmConfig.cmake + INSTALL_DESTINATION ${INSTALL_CONFIGDIR} +) + +#Install the config and configversion +install(FILES + ${CMAKE_CURRENT_BINARY_DIR}/pioasmConfig.cmake + ${CMAKE_CURRENT_BINARY_DIR}/pioasmConfigVersion.cmake + DESTINATION ${INSTALL_CONFIGDIR} +) diff --git a/tools/pioasm/ada_output.cpp b/tools/pioasm/ada_output.cpp index 8598f3345..c0f59a151 100644 --- a/tools/pioasm/ada_output.cpp +++ b/tools/pioasm/ada_output.cpp @@ -129,7 +129,7 @@ struct ada_output : public output_format { if (i == (int)program.instructions.size() - 1) { trailing_comma = ");"; } - fprintf(out, " 16#%04x#%s -- %2d: %s\n", inst, trailing_comma.c_str(), i, + fprintf(out, " 16#%04x#%s -- %2d: %s\n", (uint16_t)inst, trailing_comma.c_str(), i, disassemble(inst, program.sideset_bits_including_opt.get(), program.sideset_opt).c_str()); if (i == program.wrap) { fprintf(out, " -- .wrap\n"); diff --git a/tools/pioasm/c_sdk_output.cpp b/tools/pioasm/c_sdk_output.cpp index 9388c0d42..f54fabcd9 100644 --- a/tools/pioasm/c_sdk_output.cpp +++ b/tools/pioasm/c_sdk_output.cpp @@ -84,6 +84,7 @@ struct c_sdk_output : public output_format { fprintf(out, "#define %swrap_target %d\n", prefix.c_str(), program.wrap_target); fprintf(out, "#define %swrap %d\n", prefix.c_str(), program.wrap); + fprintf(out, "#define %spio_version %d\n", prefix.c_str(), program.pio_version); fprintf(out, "\n"); output_symbols(out, prefix, program.symbols); @@ -94,7 +95,7 @@ struct c_sdk_output : public output_format { if (i == program.wrap_target) { fprintf(out, " // .wrap_target\n"); } - fprintf(out, " 0x%04x, // %2d: %s\n", inst, i, + fprintf(out, " 0x%04x, // %2d: %s\n", (uint16_t)inst, i, disassemble(inst, program.sideset_bits_including_opt.get(), program.sideset_opt).c_str()); if (i == program.wrap) { fprintf(out, " // .wrap\n"); @@ -108,17 +109,58 @@ struct c_sdk_output : public output_format { fprintf(out, " .instructions = %sprogram_instructions,\n", prefix.c_str()); fprintf(out, " .length = %d,\n", (int) program.instructions.size()); fprintf(out, " .origin = %d,\n", program.origin.get()); + fprintf(out, " .pio_version = %d,\n", program.pio_version); + fprintf(out, "#if PICO_PIO_VERSION > 0\n"); + fprintf(out, " .used_gpio_ranges = 0x%x\n", program.used_gpio_ranges); + fprintf(out, "#endif\n"); fprintf(out, "};\n"); fprintf(out, "\n"); fprintf(out, "static inline pio_sm_config %sprogram_get_default_config(uint offset) {\n", prefix.c_str()); fprintf(out, " pio_sm_config c = pio_get_default_sm_config();\n"); fprintf(out, " sm_config_set_wrap(&c, offset + %swrap_target, offset + %swrap);\n", prefix.c_str(), prefix.c_str()); + if (program.in.pin_count >= 0) { + fprintf(out, " sm_config_set_in_pin_count(&c, %d);\n", program.in.pin_count); + fprintf(out, " sm_config_set_in_shift(&c, %d, %d, %d);\n", program.in.right, program.in.autop, program.in.threshold); + } + if (program.out.pin_count >= 0) { + fprintf(out, " sm_config_set_out_pin_count(&c, %d);\n", program.out.pin_count); + fprintf(out, " sm_config_set_out_shift(&c, %d, %d, %d);\n", program.out.right, program.out.autop, program.out.threshold); + } + if (program.set_count >= 0) { + fprintf(out, " sm_config_set_set_pin_count(&c, %d);\n", program.set_count); + } if (program.sideset_bits_including_opt.is_specified()) { fprintf(out, " sm_config_set_sideset(&c, %d, %s, %s);\n", program.sideset_bits_including_opt.get(), program.sideset_opt ? "true" : "false", program.sideset_pindirs ? "true" : "false"); } + if (program.mov_status_type != -1) { + const char *types[] = { + "STATUS_TX_LESSTHAN", + "STATUS_RX_LESSTHAN", + "STATUS_IRQ_INDEX", + }; + if (program.mov_status_type < 0 || program.mov_status_type >= 3) { + throw std::runtime_error("unknown mov_status type"); + } + fprintf(out, " sm_config_set_mov_status(&c, %s, %d);\n", types[program.mov_status_type], program.mov_status_n); + } + if (program.fifo != fifo_config::txrx) { + const char *type; + switch (program.fifo) { + case fifo_config::tx: type = "PIO_FIFO_JOIN_TX"; break; + case fifo_config::rx: type = "PIO_FIFO_JOIN_RX"; break; + case fifo_config::txput: type = "PIO_FIFO_JOIN_TXPUT"; break; + case fifo_config::txget: type = "PIO_FIFO_JOIN_TXGET"; break; + case fifo_config::putget: type = "PIO_FIFO_JOIN_PUTGET"; break; + default: throw std::runtime_error("unknown fifo_config type"); + } + fprintf(out, " sm_config_set_fifo_join(&c, %s);\n", type); + } + if (program.clock_div_int != 1 || program.clock_div_frac != 0) { + fprintf(out, " sm_config_set_clkdiv_int_frac(&c, %d, %d);\n", program.clock_div_int, program.clock_div_frac); + } fprintf(out, " return c;\n"); fprintf(out, "}\n"); diff --git a/tools/pioasm/cmake/pioasmConfig.cmake b/tools/pioasm/cmake/pioasmConfig.cmake new file mode 100644 index 000000000..54a92f47a --- /dev/null +++ b/tools/pioasm/cmake/pioasmConfig.cmake @@ -0,0 +1,3 @@ +if (NOT TARGET pioasm) + include("${CMAKE_CURRENT_LIST_DIR}/pioasmTargets.cmake") +endif() diff --git a/tools/pioasm/gen/lexer.cpp b/tools/pioasm/gen/lexer.cpp index 6277a7a4e..3bf860711 100644 --- a/tools/pioasm/gen/lexer.cpp +++ b/tools/pioasm/gen/lexer.cpp @@ -415,8 +415,8 @@ static void yynoreturn yy_fatal_error ( const char* msg ); /* %% [3.0] code to copy yytext_ptr to yytext[] goes here, if %array \ */\ (yy_c_buf_p) = yy_cp; /* %% [4.0] data tables for the DFA and the user's section 1 definitions go here */ -#define YY_NUM_RULES 95 -#define YY_END_OF_BUFFER 96 +#define YY_NUM_RULES 123 +#define YY_END_OF_BUFFER 124 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -424,37 +424,48 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[266] = +static const flex_int16_t yy_accept[368] = { 0, - 0, 0, 7, 7, 11, 11, 0, 0, 96, 94, - 1, 2, 40, 94, 37, 28, 29, 34, 30, 23, - 33, 94, 35, 89, 89, 25, 93, 92, 92, 92, - 92, 92, 92, 92, 92, 92, 92, 92, 92, 92, - 92, 73, 74, 92, 26, 27, 38, 36, 41, 94, - 7, 4, 5, 7, 11, 8, 12, 10, 19, 14, - 20, 14, 21, 16, 16, 15, 1, 2, 39, 0, - 0, 31, 50, 50, 50, 50, 50, 50, 50, 22, - 93, 89, 0, 0, 24, 93, 92, 92, 92, 92, - 92, 92, 53, 92, 92, 92, 92, 92, 92, 92, - - 92, 92, 92, 75, 92, 92, 92, 92, 92, 92, - 92, 92, 0, 7, 4, 5, 6, 11, 8, 12, - 9, 19, 14, 20, 14, 0, 13, 16, 19, 19, - 0, 3, 0, 50, 50, 50, 50, 50, 50, 50, - 50, 91, 90, 92, 92, 92, 92, 92, 92, 58, - 77, 51, 57, 92, 60, 92, 92, 87, 63, 78, - 54, 67, 92, 92, 92, 84, 59, 92, 92, 92, - 92, 0, 6, 18, 17, 50, 50, 50, 50, 50, - 50, 50, 92, 92, 76, 68, 92, 92, 92, 92, - 71, 92, 69, 92, 70, 92, 56, 55, 64, 92, - - 52, 88, 0, 50, 50, 50, 50, 50, 45, 44, - 80, 85, 92, 92, 92, 92, 92, 92, 92, 92, - 92, 92, 0, 50, 50, 50, 50, 50, 50, 92, - 82, 92, 86, 92, 92, 61, 92, 92, 79, 32, - 46, 50, 48, 50, 50, 50, 83, 81, 92, 72, - 65, 92, 50, 42, 50, 50, 62, 66, 49, 47, - 50, 50, 50, 43, 0 + 0, 0, 7, 7, 11, 11, 0, 0, 124, 122, + 1, 2, 42, 122, 37, 28, 29, 34, 30, 23, + 33, 122, 35, 116, 116, 25, 121, 44, 122, 120, + 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, + 120, 120, 120, 120, 120, 120, 83, 84, 120, 26, + 27, 40, 36, 43, 122, 7, 4, 5, 7, 11, + 8, 12, 10, 19, 14, 20, 14, 21, 16, 16, + 15, 1, 2, 41, 0, 0, 31, 117, 60, 60, + 60, 60, 60, 60, 60, 60, 60, 60, 60, 22, + 121, 0, 116, 0, 0, 24, 121, 39, 38, 120, + + 120, 120, 120, 120, 120, 120, 63, 120, 120, 120, + 120, 120, 120, 120, 120, 120, 120, 120, 120, 120, + 85, 120, 120, 120, 120, 120, 120, 102, 120, 120, + 120, 101, 120, 120, 0, 7, 4, 5, 6, 11, + 8, 12, 9, 19, 14, 20, 14, 0, 13, 16, + 19, 19, 0, 3, 0, 60, 60, 60, 60, 59, + 60, 60, 60, 60, 60, 60, 60, 60, 60, 60, + 119, 118, 120, 120, 120, 120, 120, 120, 120, 68, + 87, 61, 120, 120, 67, 120, 120, 70, 120, 120, + 106, 73, 88, 64, 77, 120, 120, 120, 120, 120, + + 94, 120, 120, 120, 69, 120, 120, 120, 120, 120, + 120, 120, 120, 0, 6, 18, 17, 60, 60, 60, + 60, 60, 60, 58, 60, 60, 57, 60, 60, 60, + 114, 120, 120, 86, 78, 120, 120, 120, 112, 120, + 98, 120, 120, 81, 120, 79, 120, 80, 99, 120, + 66, 65, 120, 120, 120, 120, 120, 74, 120, 120, + 120, 120, 100, 62, 107, 0, 60, 60, 55, 60, + 60, 60, 60, 60, 60, 48, 47, 90, 95, 120, + 120, 120, 120, 120, 120, 120, 120, 120, 120, 113, + 120, 120, 120, 120, 120, 120, 120, 104, 103, 0, + + 60, 60, 60, 60, 60, 60, 60, 60, 60, 120, + 92, 97, 115, 120, 96, 120, 120, 71, 105, 108, + 109, 110, 120, 120, 89, 111, 32, 60, 49, 60, + 60, 51, 60, 60, 60, 60, 93, 91, 120, 82, + 75, 120, 60, 60, 60, 60, 45, 60, 60, 72, + 76, 60, 52, 60, 60, 50, 60, 54, 60, 60, + 60, 56, 60, 60, 53, 46, 0 } ; static const YY_CHAR yy_ec[256] = @@ -464,17 +475,17 @@ static const YY_CHAR yy_ec[256] = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 5, 6, 1, 1, 7, 8, 1, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, - 19, 19, 19, 19, 19, 19, 19, 20, 21, 1, - 22, 1, 1, 1, 23, 24, 25, 26, 27, 28, - 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, - 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, - 49, 1, 50, 51, 52, 1, 53, 54, 55, 56, - - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, - 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, - 77, 78, 79, 80, 81, 82, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 83, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 84, 1, 1, 1, 1, + 20, 21, 22, 23, 23, 23, 23, 24, 25, 26, + 27, 28, 1, 1, 29, 30, 31, 32, 33, 34, + 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, + 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, + 55, 1, 56, 57, 58, 1, 59, 60, 61, 62, + + 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, + 83, 84, 85, 86, 87, 88, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 89, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -483,178 +494,227 @@ static const YY_CHAR yy_ec[256] = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 85, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 91, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const YY_CHAR yy_meta[86] = +static const YY_CHAR yy_meta[92] = { 0, 1, 2, 3, 1, 1, 2, 4, 1, 1, 1, - 5, 1, 1, 1, 1, 1, 6, 6, 6, 1, - 1, 2, 7, 7, 7, 7, 7, 7, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, - 1, 8, 7, 7, 7, 7, 7, 7, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, - 1, 1, 1, 1, 1 + 5, 1, 1, 1, 1, 1, 6, 6, 6, 6, + 6, 6, 6, 1, 1, 1, 2, 1, 6, 6, + 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 1, 1, 1, 7, 6, 6, + 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, + 1 + } ; -static const flex_int16_t yy_base[279] = +static const flex_int16_t yy_base[380] = { 0, - 0, 0, 84, 90, 96, 99, 102, 109, 540, 644, - 112, 536, 516, 121, 644, 644, 644, 644, 644, 644, - 523, 96, 79, 126, 121, 516, 0, 0, 83, 84, - 83, 94, 125, 111, 112, 114, 132, 161, 127, 151, - 132, 0, 0, 131, 644, 644, 644, 644, 644, 452, - 0, 195, 531, 452, 0, 205, 529, 391, 0, 209, - 401, 213, 393, 201, 209, 644, 227, 310, 644, 228, - 231, 644, 0, 167, 183, 170, 174, 190, 201, 644, - 0, 231, 118, 0, 644, 0, 0, 200, 212, 215, - 212, 218, 0, 213, 213, 216, 212, 236, 223, 231, - - 217, 221, 220, 0, 227, 261, 230, 224, 244, 255, - 248, 257, 214, 0, 297, 277, 301, 0, 310, 262, - 644, 0, 314, 198, 315, 171, 168, 303, 172, 316, - 322, 326, 327, 0, 278, 287, 306, 301, 319, 306, - 324, 331, 0, 325, 328, 327, 317, 320, 313, 0, - 0, 0, 0, 323, 0, 335, 325, 0, 329, 334, - 0, 337, 328, 330, 335, 0, 0, 339, 337, 341, - 360, 84, 396, 385, 411, 379, 382, 383, 385, 388, - 390, 379, 385, 379, 0, 0, 382, 387, 385, 392, - 0, 387, 0, 394, 0, 395, 0, 0, 391, 388, - - 0, 0, 73, 397, 90, 426, 418, 57, 0, 44, - 0, 0, 417, 426, 445, 429, 436, 433, 449, 448, - 435, 436, 5, 451, 442, 444, 458, 441, 441, 437, - 0, 452, 0, 463, 450, 0, 450, 466, 0, 644, - 0, 456, 0, 460, 469, 474, 0, 0, 464, 0, - 0, 457, 475, 0, 476, 479, 0, 0, 0, 0, - 491, 503, 489, 0, 644, 561, 569, 577, 585, 587, - 595, 598, 606, 614, 622, 630, 633, 636 + 0, 0, 90, 96, 102, 105, 108, 130, 867, 868, + 113, 863, 832, 116, 868, 868, 868, 868, 868, 868, + 838, 141, 85, 211, 122, 827, 0, 821, 817, 75, + 98, 126, 0, 115, 183, 201, 195, 204, 209, 206, + 209, 213, 254, 227, 188, 213, 0, 0, 213, 868, + 868, 868, 868, 868, 749, 0, 117, 826, 736, 0, + 293, 819, 771, 0, 297, 783, 298, 774, 290, 312, + 868, 312, 776, 868, 320, 321, 868, 326, 0, 214, + 263, 290, 295, 309, 296, 305, 315, 322, 310, 868, + 0, 356, 375, 105, 0, 868, 0, 868, 868, 0, + + 292, 298, 325, 347, 350, 366, 0, 356, 356, 359, + 370, 365, 358, 357, 384, 371, 379, 365, 369, 368, + 0, 376, 386, 420, 381, 387, 759, 389, 376, 393, + 397, 427, 390, 390, 685, 0, 358, 770, 361, 0, + 362, 768, 868, 0, 468, 766, 472, 522, 482, 464, + 138, 487, 473, 491, 492, 0, 416, 435, 466, 0, + 460, 461, 475, 465, 471, 472, 474, 491, 478, 496, + 286, 0, 483, 496, 500, 500, 490, 493, 486, 0, + 0, 492, 489, 489, 0, 491, 500, 0, 531, 522, + 0, 534, 539, 0, 541, 524, 535, 538, 543, 545, + + 0, 545, 298, 545, 0, 550, 536, 548, 553, 538, + 537, 543, 550, 388, 592, 446, 0, 564, 560, 555, + 564, 420, 565, 0, 389, 571, 0, 574, 588, 578, + 0, 585, 580, 0, 0, 587, 592, 596, 0, 605, + 0, 592, 601, 0, 596, 0, 603, 0, 0, 604, + 0, 0, 609, 595, 419, 398, 610, 599, 596, 613, + 600, 601, 0, 0, 0, 230, 612, 611, 0, 203, + 608, 621, 609, 614, 187, 0, 140, 0, 0, 618, + 627, 638, 642, 653, 638, 645, 645, 661, 645, 0, + 152, 148, 651, 662, 651, 652, 657, 0, 0, 56, + + 44, 668, 659, 655, 662, 672, 677, 660, 660, 656, + 0, 0, 0, 672, 0, 684, 668, 0, 0, 0, + 0, 0, 670, 686, 0, 0, 868, 688, 0, 682, + 698, 0, 694, 701, 711, 717, 0, 0, 707, 0, + 0, 703, 715, 705, 706, 708, 0, 710, 713, 0, + 0, 710, 0, 712, 725, 0, 728, 0, 717, 722, + 733, 0, 725, 720, 0, 0, 868, 798, 805, 812, + 819, 826, 828, 835, 842, 849, 856, 858, 89 } ; -static const flex_int16_t yy_def[279] = +static const flex_int16_t yy_def[380] = { 0, - 265, 1, 266, 266, 267, 267, 268, 268, 265, 265, - 265, 265, 265, 269, 265, 265, 265, 265, 265, 265, - 265, 270, 265, 265, 265, 265, 271, 272, 272, 272, - 272, 272, 272, 272, 272, 272, 272, 272, 272, 272, - 272, 272, 272, 272, 265, 265, 265, 265, 265, 265, - 273, 273, 265, 273, 274, 274, 265, 265, 275, 265, - 265, 275, 276, 275, 275, 265, 265, 265, 265, 269, - 269, 265, 277, 277, 277, 277, 277, 277, 277, 265, - 271, 265, 265, 278, 265, 271, 272, 272, 272, 272, - 272, 272, 272, 272, 272, 272, 272, 272, 272, 272, - - 272, 272, 272, 272, 272, 272, 272, 272, 272, 272, - 272, 272, 265, 273, 273, 265, 273, 274, 274, 265, - 265, 275, 265, 265, 275, 276, 276, 275, 275, 275, - 269, 269, 269, 277, 277, 277, 277, 277, 277, 277, - 277, 265, 278, 272, 272, 272, 272, 272, 272, 272, - 272, 272, 272, 272, 272, 272, 272, 272, 272, 272, - 272, 272, 272, 272, 272, 272, 272, 272, 272, 272, - 272, 265, 273, 275, 275, 277, 277, 277, 277, 277, - 277, 277, 272, 272, 272, 272, 272, 272, 272, 272, - 272, 272, 272, 272, 272, 272, 272, 272, 272, 272, - - 272, 272, 265, 277, 277, 277, 277, 277, 277, 277, - 272, 272, 272, 272, 272, 272, 272, 272, 272, 272, - 272, 272, 265, 277, 277, 277, 277, 277, 277, 272, - 272, 272, 272, 272, 272, 272, 272, 272, 272, 265, - 277, 277, 277, 277, 277, 277, 272, 272, 272, 272, - 272, 272, 277, 277, 277, 277, 272, 272, 277, 277, - 277, 277, 277, 277, 0, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265 + 367, 1, 368, 368, 369, 369, 370, 370, 367, 367, + 367, 367, 367, 371, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 372, 367, 367, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 367, + 367, 367, 367, 367, 367, 374, 374, 367, 374, 375, + 375, 367, 367, 376, 367, 367, 376, 377, 376, 376, + 367, 367, 367, 367, 371, 371, 367, 367, 378, 378, + 378, 378, 378, 378, 378, 378, 378, 378, 378, 367, + 372, 367, 367, 367, 379, 367, 372, 367, 367, 373, + + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 367, 374, 374, 367, 374, 375, + 375, 367, 367, 376, 367, 367, 376, 377, 377, 376, + 376, 376, 371, 371, 371, 378, 378, 378, 378, 378, + 378, 378, 378, 378, 378, 378, 378, 378, 378, 378, + 367, 379, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 367, 374, 376, 152, 378, 378, 378, + 378, 378, 378, 378, 378, 378, 378, 378, 378, 378, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 367, 378, 378, 378, 378, + 378, 378, 378, 378, 378, 378, 378, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 367, + + 378, 378, 378, 378, 378, 378, 378, 378, 378, 373, + 373, 373, 373, 373, 373, 373, 373, 373, 373, 373, + 373, 373, 373, 373, 373, 373, 367, 378, 378, 378, + 378, 378, 378, 378, 378, 378, 373, 373, 373, 373, + 373, 373, 378, 378, 378, 378, 378, 378, 378, 373, + 373, 378, 378, 378, 378, 378, 378, 378, 378, 378, + 378, 378, 378, 378, 378, 378, 0, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367 } ; -static const flex_int16_t yy_nxt[730] = +static const flex_int16_t yy_nxt[960] = { 0, 10, 11, 12, 11, 13, 10, 14, 15, 16, 17, - 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, - 27, 10, 28, 29, 30, 28, 31, 28, 32, 28, - 33, 34, 28, 28, 35, 36, 37, 38, 28, 39, - 40, 28, 28, 28, 41, 42, 43, 44, 45, 46, - 47, 28, 28, 29, 30, 28, 31, 28, 32, 28, - 33, 34, 28, 28, 35, 36, 37, 38, 28, 39, - 40, 28, 28, 28, 41, 42, 43, 44, 10, 48, - 10, 49, 10, 10, 50, 52, 53, 52, 240, 80, - 54, 52, 53, 52, 81, 229, 54, 56, 57, 56, - - 56, 57, 56, 60, 61, 62, 58, 63, 228, 58, - 60, 61, 62, 67, 63, 67, 88, 89, 64, 65, - 65, 74, 71, 66, 71, 64, 65, 65, 90, 75, - 66, 91, 76, 77, 142, 142, 78, 82, 82, 82, - 79, 225, 82, 82, 82, 96, 88, 89, 97, 83, - 98, 74, 92, 107, 111, 223, 99, 112, 90, 75, - 93, 91, 76, 77, 94, 95, 78, 100, 203, 101, - 79, 84, 102, 127, 103, 96, 127, 108, 97, 83, - 98, 109, 92, 107, 111, 104, 99, 112, 174, 174, - 93, 105, 110, 135, 94, 95, 115, 100, 115, 101, - - 124, 84, 102, 106, 103, 136, 119, 108, 119, 137, - 123, 109, 123, 138, 123, 104, 125, 128, 128, 128, - 139, 105, 110, 135, 129, 128, 128, 128, 67, 131, - 67, 131, 133, 106, 133, 136, 144, 140, 145, 137, - 141, 146, 147, 138, 148, 149, 130, 82, 82, 82, - 139, 150, 151, 152, 129, 153, 157, 158, 159, 154, - 160, 161, 162, 166, 120, 167, 144, 140, 145, 168, - 141, 146, 147, 155, 148, 149, 130, 169, 170, 116, - 156, 150, 151, 152, 163, 153, 157, 158, 159, 154, - 160, 161, 162, 166, 164, 167, 171, 172, 115, 168, - - 115, 165, 173, 155, 173, 176, 132, 169, 170, 132, - 156, 119, 68, 119, 163, 123, 123, 123, 125, 128, - 128, 128, 177, 131, 164, 131, 171, 131, 133, 131, - 133, 165, 175, 175, 175, 176, 178, 179, 175, 175, - 175, 175, 175, 175, 180, 181, 182, 142, 142, 183, - 184, 185, 177, 186, 187, 188, 189, 190, 191, 192, - 193, 196, 194, 197, 198, 199, 178, 179, 175, 175, - 175, 175, 175, 175, 180, 181, 182, 195, 200, 183, - 184, 185, 201, 186, 187, 188, 189, 190, 191, 192, - 193, 196, 194, 197, 198, 199, 202, 173, 127, 173, - - 132, 174, 174, 124, 132, 132, 121, 195, 200, 204, - 205, 206, 201, 207, 208, 209, 210, 211, 212, 213, - 214, 215, 216, 217, 218, 219, 202, 175, 175, 175, - 222, 220, 224, 175, 175, 175, 175, 175, 175, 204, - 205, 206, 221, 207, 208, 209, 210, 211, 212, 213, - 214, 215, 216, 217, 218, 219, 226, 227, 230, 231, - 222, 220, 224, 175, 175, 175, 175, 175, 175, 232, - 233, 234, 235, 236, 237, 238, 239, 241, 242, 243, - 244, 245, 246, 247, 248, 249, 226, 227, 230, 231, - 250, 251, 252, 253, 254, 255, 256, 257, 258, 232, - - 233, 234, 235, 236, 237, 238, 239, 241, 242, 243, - 244, 245, 246, 247, 248, 249, 259, 260, 261, 262, - 250, 251, 252, 253, 254, 255, 256, 257, 258, 263, - 264, 120, 117, 116, 113, 85, 72, 69, 68, 265, - 265, 265, 265, 265, 265, 265, 259, 260, 261, 262, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 263, - 264, 51, 51, 51, 51, 51, 51, 51, 51, 55, - 55, 55, 55, 55, 55, 55, 55, 59, 59, 59, - 59, 59, 59, 59, 59, 70, 70, 265, 265, 70, - 70, 70, 70, 73, 73, 86, 86, 265, 86, 86, - - 86, 86, 86, 87, 87, 87, 114, 114, 265, 114, - 114, 114, 114, 114, 118, 118, 265, 118, 265, 118, - 118, 118, 122, 265, 265, 122, 122, 122, 122, 122, - 126, 126, 265, 126, 126, 126, 126, 126, 134, 134, - 134, 143, 143, 9, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265 + 18, 19, 20, 21, 22, 23, 24, 25, 25, 25, + 25, 25, 25, 26, 27, 28, 10, 29, 30, 31, + 32, 33, 34, 33, 35, 33, 36, 37, 33, 38, + 39, 40, 41, 42, 33, 43, 44, 45, 33, 33, + 46, 47, 48, 49, 50, 51, 52, 33, 30, 31, + 32, 33, 34, 33, 35, 33, 36, 37, 33, 38, + 39, 40, 41, 42, 33, 43, 44, 45, 33, 33, + 46, 47, 48, 49, 10, 53, 10, 54, 10, 10, + 55, 57, 58, 57, 172, 90, 59, 57, 58, 57, + + 91, 328, 59, 61, 62, 61, 61, 62, 61, 65, + 66, 67, 63, 68, 72, 63, 72, 76, 137, 76, + 137, 171, 171, 101, 69, 70, 70, 70, 70, 70, + 70, 65, 66, 67, 71, 68, 92, 102, 93, 93, + 93, 93, 93, 93, 93, 327, 69, 70, 70, 70, + 70, 70, 70, 101, 216, 216, 71, 78, 78, 78, + 78, 78, 78, 78, 321, 103, 104, 102, 320, 79, + 79, 80, 81, 79, 82, 79, 79, 83, 79, 79, + 84, 85, 79, 86, 87, 79, 79, 88, 79, 79, + 79, 89, 79, 79, 79, 103, 104, 309, 79, 79, + + 79, 80, 81, 79, 82, 79, 79, 83, 79, 79, + 84, 85, 79, 86, 87, 79, 79, 88, 79, 79, + 79, 89, 79, 79, 79, 92, 105, 93, 93, 93, + 93, 93, 93, 93, 106, 110, 111, 112, 114, 132, + 94, 133, 107, 121, 308, 134, 108, 109, 115, 122, + 117, 113, 118, 157, 116, 119, 105, 120, 123, 129, + 303, 124, 95, 130, 106, 110, 111, 112, 114, 132, + 94, 133, 107, 121, 131, 134, 108, 109, 115, 122, + 117, 113, 118, 157, 116, 119, 125, 120, 123, 129, + 126, 124, 95, 130, 141, 158, 141, 127, 145, 145, + + 145, 147, 171, 171, 131, 128, 150, 150, 150, 150, + 150, 150, 150, 72, 255, 72, 125, 256, 300, 151, + 126, 153, 155, 153, 155, 158, 159, 127, 150, 150, + 150, 150, 150, 150, 150, 128, 160, 161, 162, 173, + 174, 152, 78, 78, 78, 78, 78, 78, 78, 151, + 163, 165, 169, 164, 167, 170, 159, 175, 168, 137, + 166, 137, 215, 141, 215, 141, 160, 161, 162, 173, + 174, 152, 78, 78, 78, 78, 78, 78, 78, 176, + 163, 165, 169, 164, 167, 170, 177, 175, 168, 92, + 166, 93, 93, 93, 93, 93, 93, 93, 178, 179, + + 180, 181, 182, 183, 154, 154, 184, 185, 186, 176, + 190, 191, 192, 187, 193, 194, 177, 195, 196, 292, + 201, 202, 204, 205, 206, 207, 212, 188, 178, 179, + 180, 181, 182, 183, 189, 213, 184, 185, 186, 291, + 190, 191, 192, 187, 193, 194, 273, 195, 196, 197, + 201, 202, 204, 205, 206, 207, 212, 188, 218, 198, + 208, 209, 216, 216, 189, 213, 199, 200, 219, 145, + 210, 145, 211, 145, 153, 147, 153, 271, 266, 197, + 150, 150, 150, 150, 150, 150, 150, 149, 218, 198, + 208, 209, 153, 155, 153, 155, 199, 200, 219, 220, + + 210, 221, 211, 217, 217, 217, 217, 217, 217, 217, + 222, 223, 224, 225, 226, 217, 217, 217, 217, 217, + 217, 227, 228, 229, 230, 231, 232, 149, 233, 220, + 234, 221, 235, 236, 237, 238, 239, 240, 241, 242, + 222, 223, 224, 225, 226, 217, 217, 217, 217, 217, + 217, 227, 228, 229, 230, 231, 232, 154, 233, 243, + 234, 244, 235, 236, 237, 238, 239, 240, 241, 242, + 245, 246, 247, 249, 250, 154, 154, 251, 252, 253, + 254, 257, 258, 259, 260, 261, 262, 248, 263, 243, + 264, 244, 265, 215, 267, 215, 268, 269, 270, 272, + + 245, 246, 247, 249, 250, 274, 275, 251, 252, 253, + 254, 257, 258, 259, 260, 261, 262, 248, 263, 276, + 264, 277, 265, 278, 267, 279, 268, 269, 270, 272, + 280, 281, 282, 283, 284, 274, 275, 285, 286, 287, + 288, 289, 290, 293, 296, 294, 297, 298, 299, 276, + 301, 277, 302, 278, 304, 279, 295, 305, 306, 307, + 280, 281, 282, 283, 284, 310, 311, 285, 286, 287, + 288, 289, 290, 293, 296, 294, 297, 298, 299, 312, + 301, 313, 302, 314, 304, 315, 316, 305, 306, 307, + 317, 318, 319, 322, 323, 310, 311, 324, 325, 326, + + 329, 330, 331, 332, 333, 334, 335, 336, 337, 312, + 338, 313, 339, 314, 340, 315, 316, 341, 342, 343, + 317, 318, 319, 322, 323, 344, 345, 324, 325, 326, + 329, 330, 331, 332, 333, 334, 335, 336, 337, 346, + 338, 347, 339, 348, 340, 349, 350, 341, 342, 343, + 351, 352, 353, 354, 355, 344, 345, 356, 357, 358, + 359, 360, 361, 362, 363, 364, 365, 366, 146, 346, + 142, 347, 138, 348, 214, 349, 350, 203, 73, 149, + 351, 352, 353, 354, 355, 146, 143, 356, 357, 358, + 359, 360, 361, 362, 363, 364, 365, 366, 56, 56, + + 56, 56, 56, 56, 56, 60, 60, 60, 60, 60, + 60, 60, 64, 64, 64, 64, 64, 64, 64, 75, + 75, 142, 139, 75, 75, 75, 97, 97, 138, 97, + 97, 97, 97, 100, 100, 136, 136, 135, 136, 136, + 136, 136, 140, 140, 99, 140, 98, 140, 140, 144, + 96, 77, 144, 144, 144, 144, 148, 148, 74, 148, + 148, 148, 148, 156, 156, 73, 367, 9, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367 } ; -static const flex_int16_t yy_chk[730] = +static const flex_int16_t yy_chk[960] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -664,78 +724,103 @@ static const flex_int16_t yy_chk[730] = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 3, 3, 3, 223, 23, - 3, 4, 4, 4, 23, 210, 4, 5, 5, 5, - - 6, 6, 6, 7, 7, 7, 5, 7, 208, 6, - 8, 8, 8, 11, 8, 11, 29, 30, 7, 7, - 7, 22, 14, 7, 14, 8, 8, 8, 31, 22, - 8, 32, 22, 22, 83, 83, 22, 25, 25, 25, - 22, 205, 24, 24, 24, 34, 29, 30, 35, 24, - 36, 22, 33, 39, 41, 203, 36, 44, 31, 22, - 33, 32, 22, 22, 33, 33, 22, 37, 172, 37, - 22, 24, 37, 127, 37, 34, 126, 40, 35, 24, - 36, 40, 33, 39, 41, 38, 36, 44, 129, 129, - 33, 38, 40, 74, 33, 33, 52, 37, 52, 37, - - 124, 24, 37, 38, 37, 75, 56, 40, 56, 76, - 60, 40, 60, 77, 62, 38, 62, 64, 64, 64, - 78, 38, 40, 74, 64, 65, 65, 65, 67, 70, - 67, 70, 71, 38, 71, 75, 88, 79, 89, 76, - 79, 90, 91, 77, 92, 92, 64, 82, 82, 82, - 78, 94, 95, 96, 64, 97, 99, 100, 101, 98, - 102, 103, 105, 107, 120, 108, 88, 79, 89, 109, - 79, 90, 91, 98, 92, 92, 64, 110, 111, 116, - 98, 94, 95, 96, 106, 97, 99, 100, 101, 98, - 102, 103, 105, 107, 106, 108, 112, 113, 115, 109, - - 115, 106, 117, 98, 117, 135, 70, 110, 111, 71, - 98, 119, 68, 119, 106, 123, 125, 123, 125, 128, - 128, 128, 136, 131, 106, 131, 112, 132, 133, 132, - 133, 106, 130, 130, 130, 135, 137, 138, 130, 130, - 130, 130, 130, 130, 139, 140, 141, 142, 142, 144, - 145, 146, 136, 147, 148, 149, 154, 156, 157, 159, - 160, 163, 162, 164, 165, 168, 137, 138, 130, 130, - 130, 130, 130, 130, 139, 140, 141, 162, 169, 144, - 145, 146, 170, 147, 148, 149, 154, 156, 157, 159, - 160, 163, 162, 164, 165, 168, 171, 173, 63, 173, - - 131, 174, 174, 61, 132, 133, 58, 162, 169, 176, - 177, 178, 170, 179, 180, 181, 182, 183, 184, 187, - 188, 189, 190, 192, 194, 196, 171, 175, 175, 175, - 200, 199, 204, 175, 175, 175, 175, 175, 175, 176, - 177, 178, 199, 179, 180, 181, 182, 183, 184, 187, - 188, 189, 190, 192, 194, 196, 206, 207, 213, 214, - 200, 199, 204, 175, 175, 175, 175, 175, 175, 215, - 216, 217, 218, 219, 220, 221, 222, 224, 225, 226, - 227, 228, 229, 230, 232, 234, 206, 207, 213, 214, - 235, 237, 238, 242, 244, 245, 246, 249, 252, 215, - - 216, 217, 218, 219, 220, 221, 222, 224, 225, 226, - 227, 228, 229, 230, 232, 234, 253, 255, 256, 261, - 235, 237, 238, 242, 244, 245, 246, 249, 252, 262, - 263, 57, 54, 53, 50, 26, 21, 13, 12, 9, - 0, 0, 0, 0, 0, 0, 253, 255, 256, 261, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 262, - 263, 266, 266, 266, 266, 266, 266, 266, 266, 267, - 267, 267, 267, 267, 267, 267, 267, 268, 268, 268, - 268, 268, 268, 268, 268, 269, 269, 0, 0, 269, - 269, 269, 269, 270, 270, 271, 271, 0, 271, 271, - - 271, 271, 271, 272, 272, 272, 273, 273, 0, 273, - 273, 273, 273, 273, 274, 274, 0, 274, 0, 274, - 274, 274, 275, 0, 0, 275, 275, 275, 275, 275, - 276, 276, 0, 276, 276, 276, 276, 276, 277, 277, - 277, 278, 278, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265, 265, - 265, 265, 265, 265, 265, 265, 265, 265, 265 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 3, 3, 3, 379, 23, 3, 4, 4, 4, + + 23, 301, 4, 5, 5, 5, 6, 6, 6, 7, + 7, 7, 5, 7, 11, 6, 11, 14, 57, 14, + 57, 94, 94, 30, 7, 7, 7, 7, 7, 7, + 7, 8, 8, 8, 7, 8, 25, 31, 25, 25, + 25, 25, 25, 25, 25, 300, 8, 8, 8, 8, + 8, 8, 8, 30, 151, 151, 8, 22, 22, 22, + 22, 22, 22, 22, 292, 32, 34, 31, 291, 22, + 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, + 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, + 22, 22, 22, 22, 22, 32, 34, 277, 22, 22, + + 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, + 22, 22, 22, 22, 22, 22, 22, 22, 22, 22, + 22, 22, 22, 22, 22, 24, 35, 24, 24, 24, + 24, 24, 24, 24, 36, 37, 38, 39, 40, 45, + 24, 46, 36, 42, 275, 49, 36, 36, 40, 42, + 41, 39, 41, 80, 40, 41, 35, 41, 42, 44, + 270, 42, 24, 44, 36, 37, 38, 39, 40, 45, + 24, 46, 36, 42, 44, 49, 36, 36, 40, 42, + 41, 39, 41, 80, 40, 41, 43, 41, 42, 44, + 43, 42, 24, 44, 61, 81, 61, 43, 65, 67, + + 65, 67, 171, 171, 44, 43, 69, 69, 69, 69, + 69, 69, 69, 72, 203, 72, 43, 203, 266, 69, + 43, 75, 76, 75, 76, 81, 82, 43, 70, 70, + 70, 70, 70, 70, 70, 43, 83, 84, 85, 101, + 102, 69, 78, 78, 78, 78, 78, 78, 78, 69, + 86, 87, 89, 86, 88, 89, 82, 103, 88, 137, + 87, 137, 139, 141, 139, 141, 83, 84, 85, 101, + 102, 69, 92, 92, 92, 92, 92, 92, 92, 104, + 86, 87, 89, 86, 88, 89, 105, 103, 88, 93, + 87, 93, 93, 93, 93, 93, 93, 93, 106, 106, + + 108, 109, 110, 111, 75, 76, 112, 113, 114, 104, + 116, 117, 118, 115, 119, 120, 105, 122, 123, 256, + 125, 126, 128, 129, 130, 131, 133, 115, 106, 106, + 108, 109, 110, 111, 115, 134, 112, 113, 114, 255, + 116, 117, 118, 115, 119, 120, 225, 122, 123, 124, + 125, 126, 128, 129, 130, 131, 133, 115, 157, 124, + 132, 132, 216, 216, 115, 134, 124, 124, 158, 145, + 132, 145, 132, 147, 153, 147, 153, 222, 214, 124, + 150, 150, 150, 150, 150, 150, 150, 149, 157, 124, + 132, 132, 154, 155, 154, 155, 124, 124, 158, 159, + + 132, 161, 132, 152, 152, 152, 152, 152, 152, 152, + 162, 163, 164, 165, 166, 152, 152, 152, 152, 152, + 152, 167, 168, 169, 170, 173, 174, 148, 175, 159, + 176, 161, 177, 178, 179, 182, 183, 184, 186, 187, + 162, 163, 164, 165, 166, 152, 152, 152, 152, 152, + 152, 167, 168, 169, 170, 173, 174, 153, 175, 189, + 176, 190, 177, 178, 179, 182, 183, 184, 186, 187, + 192, 193, 195, 196, 197, 154, 155, 198, 199, 200, + 202, 204, 206, 207, 208, 209, 210, 195, 211, 189, + 212, 190, 213, 215, 218, 215, 219, 220, 221, 223, + + 192, 193, 195, 196, 197, 226, 228, 198, 199, 200, + 202, 204, 206, 207, 208, 209, 210, 195, 211, 229, + 212, 230, 213, 232, 218, 233, 219, 220, 221, 223, + 236, 237, 238, 240, 242, 226, 228, 243, 245, 247, + 250, 253, 254, 257, 259, 258, 260, 261, 262, 229, + 267, 230, 268, 232, 271, 233, 258, 272, 273, 274, + 236, 237, 238, 240, 242, 280, 281, 243, 245, 247, + 250, 253, 254, 257, 259, 258, 260, 261, 262, 282, + 267, 283, 268, 284, 271, 285, 286, 272, 273, 274, + 287, 288, 289, 293, 294, 280, 281, 295, 296, 297, + + 302, 303, 304, 305, 306, 307, 308, 309, 310, 282, + 314, 283, 316, 284, 317, 285, 286, 323, 324, 328, + 287, 288, 289, 293, 294, 330, 331, 295, 296, 297, + 302, 303, 304, 305, 306, 307, 308, 309, 310, 333, + 314, 334, 316, 335, 317, 336, 339, 323, 324, 328, + 342, 343, 344, 345, 346, 330, 331, 348, 349, 352, + 354, 355, 357, 359, 360, 361, 363, 364, 146, 333, + 142, 334, 138, 335, 135, 336, 339, 127, 73, 68, + 342, 343, 344, 345, 346, 66, 63, 348, 349, 352, + 354, 355, 357, 359, 360, 361, 363, 364, 368, 368, + + 368, 368, 368, 368, 368, 369, 369, 369, 369, 369, + 369, 369, 370, 370, 370, 370, 370, 370, 370, 371, + 371, 62, 59, 371, 371, 371, 372, 372, 58, 372, + 372, 372, 372, 373, 373, 374, 374, 55, 374, 374, + 374, 374, 375, 375, 29, 375, 28, 375, 375, 376, + 26, 21, 376, 376, 376, 376, 377, 377, 13, 377, + 377, 377, 377, 378, 378, 12, 9, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367, 367, + 367, 367, 367, 367, 367, 367, 367, 367, 367 } ; static yy_state_type yy_last_accepting_state; @@ -744,19 +829,22 @@ static char *yy_last_accepting_cpos; extern int yy_flex_debug; int yy_flex_debug = 1; -static const flex_int16_t yy_rule_linenum[95] = +static const flex_int16_t yy_rule_linenum[123] = { 0, - 65, 66, 68, 79, 80, 81, 82, 86, 87, 88, - 89, 90, 94, 95, 96, 97, 98, 99, 100, 101, - 102, 105, 106, 107, 108, 109, 110, 111, 112, 113, - 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, - 124, 126, 127, 128, 129, 130, 131, 132, 133, 134, - 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, - 147, 149, 150, 151, 152, 153, 154, 155, 156, 158, - 159, 160, 161, 162, 163, 164, 165, 166, 167, 169, - 170, 171, 172, 173, 175, 176, 178, 179, 183, 184, - 185, 187, 189, 191 - + 67, 68, 70, 81, 82, 83, 84, 88, 89, 90, + 91, 92, 96, 97, 98, 99, 100, 101, 102, 103, + 104, 107, 108, 109, 110, 111, 112, 113, 114, 115, + 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, + 126, 127, 128, 129, 131, 132, 133, 134, 135, 136, + 137, 138, 139, 140, 141, 142, 143, 144, 145, 147, + 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, + 160, 162, 163, 164, 165, 166, 167, 168, 169, 171, + 172, 173, 174, 175, 176, 177, 178, 179, 180, 182, + 183, 184, 185, 186, 188, 189, 190, 191, 192, 194, + + 195, 196, 197, 198, 199, 201, 202, 204, 205, 206, + 207, 209, 210, 211, 212, 215, 216, 217, 218, 220, + 222, 224 } ; /* The intent behind this definition is that it'll catch @@ -767,13 +855,13 @@ static const flex_int16_t yy_rule_linenum[95] = #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; -#line 1 "lexer.ll" +#line 1 "tools/pioasm/lexer.ll" /* * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#line 8 "lexer.ll" +#line 8 "tools/pioasm/lexer.ll" # include # include # include @@ -786,8 +874,10 @@ char *yytext; #pragma warning(disable : 4996) // fopen #endif +#line 878 "tools/pioasm/gen/lexer.cpp" #define YY_NO_INPUT 1 yy::parser::symbol_type make_INT(const std::string &s, const yy::parser::location_type& loc); + yy::parser::symbol_type make_FLOAT(const std::string &s, const yy::parser::location_type& loc); yy::parser::symbol_type make_HEX(const std::string &s, const yy::parser::location_type& loc); yy::parser::symbol_type make_BINARY(const std::string &s, const yy::parser::location_type& loc); // Code run each time a pattern is matched. @@ -1108,13 +1198,13 @@ YY_DECL while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 266 ) + if ( yy_current_state >= 368 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_current_state != 265 ); + while ( yy_current_state != 367 ); yy_cp = (yy_last_accepting_cpos); yy_current_state = (yy_last_accepting_state); @@ -1133,13 +1223,13 @@ YY_DECL { if ( yy_act == 0 ) fprintf( stderr, "--scanner backing up\n" ); - else if ( yy_act < 95 ) + else if ( yy_act < 123 ) fprintf( stderr, "--accepting rule at line %ld (\"%s\")\n", (long)yy_rule_linenum[yy_act], yytext ); - else if ( yy_act == 95 ) + else if ( yy_act == 123 ) fprintf( stderr, "--accepting default rule (\"%s\")\n", yytext ); - else if ( yy_act == 96 ) + else if ( yy_act == 124 ) fprintf( stderr, "--(end of buffer or a NUL)\n" ); else fprintf( stderr, "--EOF (start condition %d)\n", YY_START ); @@ -1228,7 +1318,7 @@ loc.step(); YY_BREAK case 15: YY_RULE_SETUP -return yy::parser::make_EQUAL(loc); +return yy::parser::make_ASSIGN(loc); YY_BREAK case 16: YY_RULE_SETUP @@ -1322,239 +1412,351 @@ return yy::parser::make_AND(loc); YY_BREAK case 38: YY_RULE_SETUP -return yy::parser::make_XOR(loc); +return yy::parser::make_SHR(loc); YY_BREAK case 39: YY_RULE_SETUP -return yy::parser::make_NOT_EQUAL(loc); +return yy::parser::make_SHL(loc); YY_BREAK case 40: YY_RULE_SETUP -return yy::parser::make_NOT(loc); +return yy::parser::make_XOR(loc); YY_BREAK case 41: YY_RULE_SETUP -return yy::parser::make_NOT(loc); +return yy::parser::make_NOT_EQUAL(loc); YY_BREAK case 42: YY_RULE_SETUP -return yy::parser::make_PROGRAM(loc); +return yy::parser::make_NOT(loc); YY_BREAK case 43: YY_RULE_SETUP -return yy::parser::make_WRAP_TARGET(loc); +return yy::parser::make_NOT(loc); YY_BREAK case 44: YY_RULE_SETUP -return yy::parser::make_WRAP(loc); +return yy::parser::make_LESSTHAN(loc); YY_BREAK case 45: YY_RULE_SETUP -return yy::parser::make_WORD(loc); +return yy::parser::make_PROGRAM(loc); YY_BREAK case 46: YY_RULE_SETUP -return yy::parser::make_DEFINE(loc); +return yy::parser::make_WRAP_TARGET(loc); YY_BREAK case 47: YY_RULE_SETUP -return yy::parser::make_SIDE_SET(loc); +return yy::parser::make_WRAP(loc); YY_BREAK case 48: YY_RULE_SETUP -return yy::parser::make_ORIGIN(loc); +return yy::parser::make_WORD(loc); YY_BREAK case 49: YY_RULE_SETUP -{ BEGIN(lang_opt); return yy::parser::make_LANG_OPT(loc); } +return yy::parser::make_DEFINE(loc); YY_BREAK case 50: YY_RULE_SETUP -return yy::parser::make_UNKNOWN_DIRECTIVE(yytext, loc); +return yy::parser::make_SIDE_SET(loc); YY_BREAK case 51: YY_RULE_SETUP -return yy::parser::make_JMP(loc); +return yy::parser::make_ORIGIN(loc); YY_BREAK case 52: YY_RULE_SETUP -return yy::parser::make_WAIT(loc); +{ BEGIN(lang_opt); return yy::parser::make_LANG_OPT(loc); } YY_BREAK case 53: YY_RULE_SETUP -return yy::parser::make_IN(loc); +return yy::parser::make_PIO_VERSION(loc); YY_BREAK case 54: YY_RULE_SETUP -return yy::parser::make_OUT(loc); +return yy::parser::make_CLOCK_DIV(loc); YY_BREAK case 55: YY_RULE_SETUP -return yy::parser::make_PUSH(loc); +return yy::parser::make_FIFO(loc); YY_BREAK case 56: YY_RULE_SETUP -return yy::parser::make_PULL(loc); +return yy::parser::make_MOV_STATUS(loc); YY_BREAK case 57: YY_RULE_SETUP -return yy::parser::make_MOV(loc); +return yy::parser::make_DOT_SET(loc); YY_BREAK case 58: YY_RULE_SETUP -return yy::parser::make_IRQ(loc); +return yy::parser::make_DOT_OUT(loc); YY_BREAK case 59: YY_RULE_SETUP -return yy::parser::make_SET(loc); +return yy::parser::make_DOT_IN(loc); YY_BREAK case 60: YY_RULE_SETUP -return yy::parser::make_NOP(loc); +return yy::parser::make_UNKNOWN_DIRECTIVE(yytext, loc); YY_BREAK case 61: YY_RULE_SETUP -return yy::parser::make_PUBLIC(loc); +return yy::parser::make_JMP(loc); YY_BREAK case 62: YY_RULE_SETUP -return yy::parser::make_OPTIONAL(loc); +return yy::parser::make_WAIT(loc); YY_BREAK case 63: YY_RULE_SETUP -return yy::parser::make_OPTIONAL(loc); +return yy::parser::make_IN(loc); YY_BREAK case 64: YY_RULE_SETUP -return yy::parser::make_SIDE(loc); +return yy::parser::make_OUT(loc); YY_BREAK case 65: YY_RULE_SETUP -return yy::parser::make_SIDE(loc); +return yy::parser::make_PUSH(loc); YY_BREAK case 66: YY_RULE_SETUP -return yy::parser::make_SIDE(loc); +return yy::parser::make_PULL(loc); YY_BREAK case 67: YY_RULE_SETUP -return yy::parser::make_PIN(loc); +return yy::parser::make_MOV(loc); YY_BREAK case 68: YY_RULE_SETUP -return yy::parser::make_GPIO(loc); +return yy::parser::make_IRQ(loc); YY_BREAK case 69: YY_RULE_SETUP -return yy::parser::make_OSRE(loc); +return yy::parser::make_SET(loc); YY_BREAK case 70: YY_RULE_SETUP -return yy::parser::make_PINS(loc); +return yy::parser::make_NOP(loc); YY_BREAK case 71: YY_RULE_SETUP -return yy::parser::make_NULL(loc); +return yy::parser::make_PUBLIC(loc); YY_BREAK case 72: YY_RULE_SETUP -return yy::parser::make_PINDIRS(loc); +return yy::parser::make_OPTIONAL(loc); YY_BREAK case 73: YY_RULE_SETUP -return yy::parser::make_X(loc); +return yy::parser::make_OPTIONAL(loc); YY_BREAK case 74: YY_RULE_SETUP -return yy::parser::make_Y(loc); +return yy::parser::make_SIDE(loc); YY_BREAK case 75: YY_RULE_SETUP -return yy::parser::make_PC(loc); +return yy::parser::make_SIDE(loc); YY_BREAK case 76: YY_RULE_SETUP -return yy::parser::make_EXEC(loc); +return yy::parser::make_SIDE(loc); YY_BREAK case 77: YY_RULE_SETUP -return yy::parser::make_ISR(loc); +return yy::parser::make_PIN(loc); YY_BREAK case 78: YY_RULE_SETUP -return yy::parser::make_OSR(loc); +return yy::parser::make_GPIO(loc); YY_BREAK case 79: YY_RULE_SETUP -return yy::parser::make_STATUS(loc); +return yy::parser::make_OSRE(loc); YY_BREAK case 80: YY_RULE_SETUP -return yy::parser::make_BLOCK(loc); +return yy::parser::make_PINS(loc); YY_BREAK case 81: YY_RULE_SETUP -return yy::parser::make_NOBLOCK(loc); +return yy::parser::make_NULL(loc); YY_BREAK case 82: YY_RULE_SETUP -return yy::parser::make_IFFULL(loc); +return yy::parser::make_PINDIRS(loc); YY_BREAK case 83: YY_RULE_SETUP -return yy::parser::make_IFEMPTY(loc); +return yy::parser::make_X(loc); YY_BREAK case 84: YY_RULE_SETUP -return yy::parser::make_REL(loc); +return yy::parser::make_Y(loc); YY_BREAK case 85: YY_RULE_SETUP -return yy::parser::make_CLEAR(loc); +return yy::parser::make_PC(loc); YY_BREAK case 86: YY_RULE_SETUP -return yy::parser::make_NOWAIT(loc); +return yy::parser::make_EXEC(loc); YY_BREAK case 87: YY_RULE_SETUP -return yy::parser::make_INT(1, loc); +return yy::parser::make_ISR(loc); YY_BREAK case 88: YY_RULE_SETUP +return yy::parser::make_OSR(loc); + YY_BREAK +case 89: +YY_RULE_SETUP +return yy::parser::make_STATUS(loc); + YY_BREAK +case 90: +YY_RULE_SETUP +return yy::parser::make_BLOCK(loc); + YY_BREAK +case 91: +YY_RULE_SETUP +return yy::parser::make_NOBLOCK(loc); + YY_BREAK +case 92: +YY_RULE_SETUP +return yy::parser::make_IFFULL(loc); + YY_BREAK +case 93: +YY_RULE_SETUP +return yy::parser::make_IFEMPTY(loc); + YY_BREAK +case 94: +YY_RULE_SETUP +return yy::parser::make_REL(loc); + YY_BREAK +case 95: +YY_RULE_SETUP +return yy::parser::make_CLEAR(loc); + YY_BREAK +case 96: +YY_RULE_SETUP +return yy::parser::make_NOWAIT(loc); + YY_BREAK +case 97: +YY_RULE_SETUP +return yy::parser::make_JMPPIN(loc); + YY_BREAK +case 98: +YY_RULE_SETUP +return yy::parser::make_NEXT(loc); + YY_BREAK +case 99: +YY_RULE_SETUP +return yy::parser::make_PREV(loc); + YY_BREAK +case 100: +YY_RULE_SETUP +return yy::parser::make_TXRX(loc); + YY_BREAK +case 101: +YY_RULE_SETUP +return yy::parser::make_TX(loc); + YY_BREAK +case 102: +YY_RULE_SETUP +return yy::parser::make_RX(loc); + YY_BREAK +case 103: +YY_RULE_SETUP +return yy::parser::make_TXPUT(loc); + YY_BREAK +case 104: +YY_RULE_SETUP +return yy::parser::make_TXGET(loc); + YY_BREAK +case 105: +YY_RULE_SETUP +return yy::parser::make_PUTGET(loc); + YY_BREAK +case 106: +YY_RULE_SETUP +return yy::parser::make_INT(1, loc); + YY_BREAK +case 107: +YY_RULE_SETUP return yy::parser::make_INT(0, loc); YY_BREAK +case 108: +YY_RULE_SETUP +return yy::parser::make_RP2040(loc); + YY_BREAK +case 109: +YY_RULE_SETUP +return yy::parser::make_RP2350(loc); + YY_BREAK +case 110: +YY_RULE_SETUP +return yy::parser::make_RXFIFO(loc); + YY_BREAK +case 111: +YY_RULE_SETUP +return yy::parser::make_TXFIFO(loc); + YY_BREAK +case 112: +YY_RULE_SETUP +return yy::parser::make_LEFT(loc); + YY_BREAK +case 113: +YY_RULE_SETUP +return yy::parser::make_RIGHT(loc); + YY_BREAK +case 114: +YY_RULE_SETUP +return yy::parser::make_AUTO(loc); + YY_BREAK +case 115: +YY_RULE_SETUP +return yy::parser::make_MANUAL(loc); + YY_BREAK case YY_STATE_EOF(INITIAL): case YY_STATE_EOF(code_block): case YY_STATE_EOF(c_comment): case YY_STATE_EOF(lang_opt): return yy::parser::make_END(loc); YY_BREAK -case 89: +case 116: YY_RULE_SETUP return make_INT(yytext, loc); YY_BREAK -case 90: +case 117: +YY_RULE_SETUP +return make_FLOAT(yytext, loc); + YY_BREAK +case 118: YY_RULE_SETUP return make_HEX(yytext, loc); YY_BREAK -case 91: +case 119: YY_RULE_SETUP return make_BINARY(yytext, loc); YY_BREAK -case 92: +case 120: YY_RULE_SETUP return yy::parser::make_ID(yytext, loc); YY_BREAK -case 93: +case 121: YY_RULE_SETUP { } YY_BREAK -case 94: +case 122: YY_RULE_SETUP { throw yy::parser::syntax_error(loc, "invalid character: " + std::string(yytext)); } YY_BREAK -case 95: +case 123: YY_RULE_SETUP ECHO; YY_BREAK @@ -1876,7 +2078,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 266 ) + if ( yy_current_state >= 368 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1909,11 +2111,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 266 ) + if ( yy_current_state >= 368 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 265); + yy_is_jam = (yy_current_state == 367); return yy_is_jam ? 0 : yy_current_state; } @@ -2670,6 +2872,13 @@ yy::parser::symbol_type make_INT(const std::string &s, const yy::parser::locatio return yy::parser::make_INT((int) n, loc); } +yy::parser::symbol_type make_FLOAT(const std::string &s, const yy::parser::location_type& loc) +{ + errno = 0; + float n = strtof (s.c_str(), NULL); + return yy::parser::make_FLOAT(n, loc); +} + yy::parser::symbol_type make_HEX(const std::string &s, const yy::parser::location_type& loc) { errno = 0; diff --git a/tools/pioasm/gen/location.h b/tools/pioasm/gen/location.h index 4965682b0..0bfbfc18f 100644 --- a/tools/pioasm/gen/location.h +++ b/tools/pioasm/gen/location.h @@ -31,12 +31,12 @@ // version 2.2 of Bison. /** - ** \file pico_sdk/tools/pioasm/gen/location.h + ** \file tools/pioasm/gen/location.h ** Define the yy::location class. */ -#ifndef YY_YY_HOME_GRAHAM_DEV_MU_PICO_SDK_TOOLS_PIOASM_GEN_LOCATION_H_INCLUDED -# define YY_YY_HOME_GRAHAM_DEV_MU_PICO_SDK_TOOLS_PIOASM_GEN_LOCATION_H_INCLUDED +#ifndef YY_YY_HOME_GRAHAM_DEV_AMY_AMY_SDK_TOOLS_PIOASM_GEN_LOCATION_H_INCLUDED +# define YY_YY_HOME_GRAHAM_DEV_AMY_AMY_SDK_TOOLS_PIOASM_GEN_LOCATION_H_INCLUDED # include # include @@ -299,4 +299,4 @@ namespace yy { } // yy -#endif // !YY_YY_HOME_GRAHAM_DEV_MU_PICO_SDK_TOOLS_PIOASM_GEN_LOCATION_H_INCLUDED +#endif // !YY_YY_HOME_GRAHAM_DEV_AMY_AMY_SDK_TOOLS_PIOASM_GEN_LOCATION_H_INCLUDED diff --git a/tools/pioasm/gen/parser.cpp b/tools/pioasm/gen/parser.cpp index c9bd036ee..7027d2165 100644 --- a/tools/pioasm/gen/parser.cpp +++ b/tools/pioasm/gen/parser.cpp @@ -207,6 +207,8 @@ namespace yy { { switch (that.kind ()) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -217,6 +219,10 @@ namespace yy { value.YY_MOVE_OR_COPY< enum condition > (YY_MOVE (that.value)); break; + case symbol_kind::S_fifo_config: // fifo_config + value.YY_MOVE_OR_COPY< enum fifo_config > (YY_MOVE (that.value)); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -227,13 +233,17 @@ namespace yy { value.YY_MOVE_OR_COPY< enum irq > (YY_MOVE (that.value)); break; + case symbol_kind::S_mov_op: // mov_op + value.YY_MOVE_OR_COPY< enum mov_op > (YY_MOVE (that.value)); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.YY_MOVE_OR_COPY< enum mov > (YY_MOVE (that.value)); + value.YY_MOVE_OR_COPY< extended_mov > (YY_MOVE (that.value)); break; - case symbol_kind::S_mov_op: // mov_op - value.YY_MOVE_OR_COPY< enum mov_op > (YY_MOVE (that.value)); + case symbol_kind::S_FLOAT: // "float" + value.YY_MOVE_OR_COPY< float > (YY_MOVE (that.value)); break; case symbol_kind::S_INT: // "integer" @@ -249,6 +259,7 @@ namespace yy { case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.YY_MOVE_OR_COPY< std::shared_ptr > (YY_MOVE (that.value)); break; @@ -270,6 +281,10 @@ namespace yy { value.YY_MOVE_OR_COPY< std::string > (YY_MOVE (that.value)); break; + case symbol_kind::S_pio_version: // pio_version + value.YY_MOVE_OR_COPY< uint > (YY_MOVE (that.value)); + break; + default: break; } @@ -285,6 +300,8 @@ namespace yy { { switch (that.kind ()) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -295,6 +312,10 @@ namespace yy { value.move< enum condition > (YY_MOVE (that.value)); break; + case symbol_kind::S_fifo_config: // fifo_config + value.move< enum fifo_config > (YY_MOVE (that.value)); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -305,13 +326,17 @@ namespace yy { value.move< enum irq > (YY_MOVE (that.value)); break; + case symbol_kind::S_mov_op: // mov_op + value.move< enum mov_op > (YY_MOVE (that.value)); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.move< enum mov > (YY_MOVE (that.value)); + value.move< extended_mov > (YY_MOVE (that.value)); break; - case symbol_kind::S_mov_op: // mov_op - value.move< enum mov_op > (YY_MOVE (that.value)); + case symbol_kind::S_FLOAT: // "float" + value.move< float > (YY_MOVE (that.value)); break; case symbol_kind::S_INT: // "integer" @@ -327,6 +352,7 @@ namespace yy { case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.move< std::shared_ptr > (YY_MOVE (that.value)); break; @@ -348,6 +374,10 @@ namespace yy { value.move< std::string > (YY_MOVE (that.value)); break; + case symbol_kind::S_pio_version: // pio_version + value.move< uint > (YY_MOVE (that.value)); + break; + default: break; } @@ -363,6 +393,8 @@ namespace yy { state = that.state; switch (that.kind ()) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -373,6 +405,10 @@ namespace yy { value.copy< enum condition > (that.value); break; + case symbol_kind::S_fifo_config: // fifo_config + value.copy< enum fifo_config > (that.value); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -383,13 +419,17 @@ namespace yy { value.copy< enum irq > (that.value); break; + case symbol_kind::S_mov_op: // mov_op + value.copy< enum mov_op > (that.value); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.copy< enum mov > (that.value); + value.copy< extended_mov > (that.value); break; - case symbol_kind::S_mov_op: // mov_op - value.copy< enum mov_op > (that.value); + case symbol_kind::S_FLOAT: // "float" + value.copy< float > (that.value); break; case symbol_kind::S_INT: // "integer" @@ -405,6 +445,7 @@ namespace yy { case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.copy< std::shared_ptr > (that.value); break; @@ -426,6 +467,10 @@ namespace yy { value.copy< std::string > (that.value); break; + case symbol_kind::S_pio_version: // pio_version + value.copy< uint > (that.value); + break; + default: break; } @@ -440,6 +485,8 @@ namespace yy { state = that.state; switch (that.kind ()) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -450,6 +497,10 @@ namespace yy { value.move< enum condition > (that.value); break; + case symbol_kind::S_fifo_config: // fifo_config + value.move< enum fifo_config > (that.value); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -460,13 +511,17 @@ namespace yy { value.move< enum irq > (that.value); break; + case symbol_kind::S_mov_op: // mov_op + value.move< enum mov_op > (that.value); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.move< enum mov > (that.value); + value.move< extended_mov > (that.value); break; - case symbol_kind::S_mov_op: // mov_op - value.move< enum mov_op > (that.value); + case symbol_kind::S_FLOAT: // "float" + value.move< float > (that.value); break; case symbol_kind::S_INT: // "integer" @@ -482,6 +537,7 @@ namespace yy { case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.move< std::shared_ptr > (that.value); break; @@ -503,6 +559,10 @@ namespace yy { value.move< std::string > (that.value); break; + case symbol_kind::S_pio_version: // pio_version + value.move< uint > (that.value); + break; + default: break; } @@ -567,6 +627,10 @@ namespace yy { { yyo << "..."; } break; + case symbol_kind::S_FLOAT: // "float" + { yyo << "..."; } + break; + case symbol_kind::S_label_decl: // label_decl { yyo << "..."; } break; @@ -579,6 +643,10 @@ namespace yy { { yyo << "..."; } break; + case symbol_kind::S_pio_version: // pio_version + { yyo << "..."; } + break; + case symbol_kind::S_instruction: // instruction { yyo << "..."; } break; @@ -603,6 +671,10 @@ namespace yy { { yyo << "..."; } break; + case symbol_kind::S_fifo_config: // fifo_config + { yyo << "..."; } + break; + case symbol_kind::S_in_source: // in_source { yyo << "..."; } break; @@ -627,6 +699,18 @@ namespace yy { { yyo << "..."; } break; + case symbol_kind::S_direction: // direction + { yyo << "..."; } + break; + + case symbol_kind::S_autop: // autop + { yyo << "..."; } + break; + + case symbol_kind::S_threshold: // threshold + { yyo << "..."; } + break; + case symbol_kind::S_if_full: // if_full { yyo << "..."; } break; @@ -884,6 +968,8 @@ namespace yy { when using variants. */ switch (yyr1_[yyn]) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -894,6 +980,10 @@ namespace yy { yylhs.value.emplace< enum condition > (); break; + case symbol_kind::S_fifo_config: // fifo_config + yylhs.value.emplace< enum fifo_config > (); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -904,13 +994,17 @@ namespace yy { yylhs.value.emplace< enum irq > (); break; + case symbol_kind::S_mov_op: // mov_op + yylhs.value.emplace< enum mov_op > (); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - yylhs.value.emplace< enum mov > (); + yylhs.value.emplace< extended_mov > (); break; - case symbol_kind::S_mov_op: // mov_op - yylhs.value.emplace< enum mov_op > (); + case symbol_kind::S_FLOAT: // "float" + yylhs.value.emplace< float > (); break; case symbol_kind::S_INT: // "integer" @@ -926,6 +1020,7 @@ namespace yy { case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold yylhs.value.emplace< std::shared_ptr > (); break; @@ -947,6 +1042,10 @@ namespace yy { yylhs.value.emplace< std::string > (); break; + case symbol_kind::S_pio_version: // pio_version + yylhs.value.emplace< uint > (); + break; + default: break; } @@ -1007,435 +1106,627 @@ namespace yy { { pioasm.get_current_program(yystack_[1].location, ".origin", true).set_origin(yylhs.location, yystack_[0].value.as < std::shared_ptr > ()); } break; - case 17: // directive: ".side_set" value "opt" "pindirs" + case 17: // directive: ".pio_version" pio_version + { pioasm.get_current_program(yystack_[1].location, ".pio_version", true, false).set_pio_version(yylhs.location, yystack_[0].value.as < uint > ()); } + break; + + case 18: // directive: ".side_set" value "opt" "pindirs" { pioasm.get_current_program(yystack_[3].location, ".side_set", true).set_sideset(yylhs.location, yystack_[2].value.as < std::shared_ptr > (), true, true); } break; - case 18: // directive: ".side_set" value "opt" + case 19: // directive: ".side_set" value "opt" { pioasm.get_current_program(yystack_[2].location, ".side_set", true).set_sideset(yylhs.location, yystack_[1].value.as < std::shared_ptr > (), true, false); } break; - case 19: // directive: ".side_set" value "pindirs" + case 20: // directive: ".side_set" value "pindirs" { pioasm.get_current_program(yystack_[2].location, ".side_set", true).set_sideset(yylhs.location, yystack_[1].value.as < std::shared_ptr > (), false, true); } break; - case 20: // directive: ".side_set" value + case 21: // directive: ".side_set" value { pioasm.get_current_program(yystack_[1].location, ".side_set", true).set_sideset(yylhs.location, yystack_[0].value.as < std::shared_ptr > (), false, false); } break; - case 21: // directive: ".wrap_target" + case 22: // directive: ".in" value direction autop threshold + { pioasm.get_current_program(yystack_[4].location, ".out", true).set_in(yylhs.location, yystack_[3].value.as < std::shared_ptr > (), yystack_[2].value.as < bool > (), yystack_[1].value.as < bool > (), yystack_[0].value.as < std::shared_ptr > ()); } + break; + + case 23: // directive: ".out" value direction autop threshold + { pioasm.get_current_program(yystack_[4].location, ".out", true).set_out(yylhs.location, yystack_[3].value.as < std::shared_ptr > (), yystack_[2].value.as < bool > (), yystack_[1].value.as < bool > (), yystack_[0].value.as < std::shared_ptr > ()); } + break; + + case 24: // directive: ".set" value + { pioasm.check_version(1, yylhs.location, ".in"); pioasm.get_current_program(yystack_[1].location, ".out", true).set_set_count(yylhs.location, yystack_[0].value.as < std::shared_ptr > ()); } + break; + + case 25: // directive: ".wrap_target" { pioasm.get_current_program(yystack_[0].location, ".wrap_target").set_wrap_target(yylhs.location); } break; - case 22: // directive: ".wrap" + case 26: // directive: ".wrap" { pioasm.get_current_program(yystack_[0].location, ".wrap").set_wrap(yylhs.location); } break; - case 23: // directive: ".word" value + case 27: // directive: ".word" value { pioasm.get_current_program(yystack_[1].location, "instruction").add_instruction(std::shared_ptr(new instr_word(yylhs.location, yystack_[0].value.as < std::shared_ptr > ()))); } break; - case 24: // directive: ".lang_opt" "text" "text" "=" "integer" - { pioasm.get_current_program(yystack_[4].location, ".lang_opt").add_lang_opt(yystack_[3].value.as < std::string > (), yystack_[2].value.as < std::string > (), std::to_string(yystack_[0].value.as < int > ())); } + case 28: // directive: ".lang_opt" "text" "text" "=" "integer" + { pioasm.get_current_program(yystack_[4].location, ".lang_opt").add_lang_opt(yystack_[3].value.as < std::string > (), yystack_[2].value.as < std::string > (), std::to_string(yystack_[0].value.as < int > ())); } break; - case 25: // directive: ".lang_opt" "text" "text" "=" "string" - { pioasm.get_current_program(yystack_[4].location, ".lang_opt").add_lang_opt(yystack_[3].value.as < std::string > (), yystack_[2].value.as < std::string > (), yystack_[0].value.as < std::string > ()); } + case 29: // directive: ".lang_opt" "text" "text" "=" "string" + { pioasm.get_current_program(yystack_[4].location, ".lang_opt").add_lang_opt(yystack_[3].value.as < std::string > (), yystack_[2].value.as < std::string > (), yystack_[0].value.as < std::string > ()); } break; - case 26: // directive: ".lang_opt" "text" "text" "=" "text" - { pioasm.get_current_program(yystack_[4].location, ".lang_opt").add_lang_opt(yystack_[3].value.as < std::string > (), yystack_[2].value.as < std::string > (), yystack_[0].value.as < std::string > ()); } + case 30: // directive: ".lang_opt" "text" "text" "=" "text" + { pioasm.get_current_program(yystack_[4].location, ".lang_opt").add_lang_opt(yystack_[3].value.as < std::string > (), yystack_[2].value.as < std::string > (), yystack_[0].value.as < std::string > ()); } break; - case 27: // directive: ".lang_opt" error + case 31: // directive: ".lang_opt" error { error(yylhs.location, "expected format is .lang_opt language option_name = option_value"); } break; - case 28: // directive: UNKNOWN_DIRECTIVE + case 32: // directive: ".clock_div" "integer" + { pioasm.get_current_program(yystack_[1].location, ".clock_div").set_clock_div(yylhs.location, yystack_[0].value.as < int > ()); } + break; + + case 33: // directive: ".clock_div" "float" + { pioasm.get_current_program(yystack_[1].location, ".clock_div").set_clock_div(yylhs.location, yystack_[0].value.as < float > ()); } + break; + + case 34: // directive: ".fifo" fifo_config + { pioasm.get_current_program(yystack_[1].location, ".fifo", true).set_fifo_config(yylhs.location, yystack_[0].value.as < enum fifo_config > ()); } + break; + + case 35: // directive: ".mov_status" "txfifo" "<" value + { pioasm.get_current_program(yystack_[3].location, ".mov_status", true).set_mov_status(mov_status_type::tx_lessthan, yystack_[0].value.as < std::shared_ptr > ()); } + break; + + case 36: // directive: ".mov_status" "rxfifo" "<" value + { pioasm.get_current_program(yystack_[3].location, ".mov_status", true).set_mov_status(mov_status_type::rx_lessthan, yystack_[0].value.as < std::shared_ptr > ()); } + break; + + case 37: // directive: ".mov_status" "irq" "next" "set" value + { pioasm.get_current_program(yystack_[4].location, ".mov_status", true).set_mov_status(mov_status_type::irq_set, yystack_[0].value.as < std::shared_ptr > (), 2); } + break; + + case 38: // directive: ".mov_status" "irq" "prev" "set" value + { pioasm.get_current_program(yystack_[4].location, ".mov_status", true).set_mov_status(mov_status_type::irq_set, yystack_[0].value.as < std::shared_ptr > (), 1); } + break; + + case 39: // directive: ".mov_status" "irq" "set" value + { pioasm.get_current_program(yystack_[3].location, ".mov_status", true).set_mov_status(mov_status_type::irq_set, yystack_[0].value.as < std::shared_ptr > ()); } + break; + + case 40: // directive: ".mov_status" + { error(yystack_[1].location, "expected 'txfifo < N', 'rxfifo < N' or 'irq set N'"); } + break; + + case 41: // directive: UNKNOWN_DIRECTIVE { std::stringstream msg; msg << "unknown directive " << yystack_[0].value.as < std::string > (); throw syntax_error(yylhs.location, msg.str()); } break; - case 29: // value: "integer" + case 42: // value: "integer" { yylhs.value.as < std::shared_ptr > () = resolvable_int(yylhs.location, yystack_[0].value.as < int > ()); } break; - case 30: // value: "identifier" + case 43: // value: "identifier" { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new name_ref(yylhs.location, yystack_[0].value.as < std::string > ())); } break; - case 31: // value: "(" expression ")" + case 44: // value: "(" expression ")" { yylhs.value.as < std::shared_ptr > () = yystack_[1].value.as < std::shared_ptr > (); } break; - case 32: // expression: value + case 45: // expression: value { yylhs.value.as < std::shared_ptr > () = yystack_[0].value.as < std::shared_ptr > (); } break; - case 33: // expression: expression "+" expression + case 46: // expression: expression "+" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::add, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 34: // expression: expression "-" expression + case 47: // expression: expression "-" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::subtract, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 35: // expression: expression "*" expression + case 48: // expression: expression "*" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::multiply, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 36: // expression: expression "/" expression + case 49: // expression: expression "/" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::divide, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 37: // expression: expression "|" expression + case 50: // expression: expression "|" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::or_, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 38: // expression: expression "&" expression + case 51: // expression: expression "&" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::and_, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 39: // expression: expression "^" expression + case 52: // expression: expression "^" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::xor_, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 40: // expression: "-" expression + case 53: // expression: expression "<<" expression + { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::shl_, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } + break; + + case 54: // expression: expression ">>" expression + { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new binary_operation(yylhs.location, binary_operation::shr_, yystack_[2].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } + break; + + case 55: // expression: "-" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new unary_operation(yylhs.location, unary_operation::negate, yystack_[0].value.as < std::shared_ptr > ())); } break; - case 41: // expression: "::" expression + case 56: // expression: "::" expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new unary_operation(yylhs.location, unary_operation::reverse, yystack_[0].value.as < std::shared_ptr > ())); } break; - case 42: // instruction: base_instruction sideset delay + case 57: // pio_version: "integer" + { yylhs.value.as < uint > () = yystack_[0].value.as < int > (); } + break; + + case 58: // pio_version: "rp2040" + { yylhs.value.as < uint > () = 0; } + break; + + case 59: // pio_version: "rp2350" + { yylhs.value.as < uint > () = 1; } + break; + + case 60: // instruction: base_instruction sideset delay { yylhs.value.as < std::shared_ptr > () = yystack_[2].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->sideset = yystack_[1].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->delay = yystack_[0].value.as < std::shared_ptr > (); } break; - case 43: // instruction: base_instruction delay sideset + case 61: // instruction: base_instruction delay sideset { yylhs.value.as < std::shared_ptr > () = yystack_[2].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->delay = yystack_[1].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->sideset = yystack_[0].value.as < std::shared_ptr > (); } break; - case 44: // instruction: base_instruction sideset + case 62: // instruction: base_instruction sideset { yylhs.value.as < std::shared_ptr > () = yystack_[1].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->sideset = yystack_[0].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->delay = resolvable_int(yylhs.location, 0); } break; - case 45: // instruction: base_instruction delay + case 63: // instruction: base_instruction delay { yylhs.value.as < std::shared_ptr > () = yystack_[1].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->delay = yystack_[0].value.as < std::shared_ptr > (); } break; - case 46: // instruction: base_instruction + case 64: // instruction: base_instruction { yylhs.value.as < std::shared_ptr > () = yystack_[0].value.as < std::shared_ptr > (); yylhs.value.as < std::shared_ptr > ()->delay = resolvable_int(yylhs.location, 0); } break; - case 47: // base_instruction: "nop" + case 65: // base_instruction: "nop" { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_nop(yylhs.location)); } break; - case 48: // base_instruction: "jmp" condition comma expression + case 66: // base_instruction: "jmp" condition comma expression { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_jmp(yylhs.location, yystack_[2].value.as < enum condition > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 49: // base_instruction: "wait" value wait_source + case 67: // base_instruction: "wait" value wait_source { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_wait(yylhs.location, yystack_[1].value.as < std::shared_ptr > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 50: // base_instruction: "wait" value "," value - { std::stringstream msg; location l; l.begin = yystack_[2].location.end; l.end = yystack_[1].location.end; msg << "expected irq, gpio or pin after the polarity value and before the \",\""; throw yy::parser::syntax_error(l, msg.str()); } - break; - - case 51: // base_instruction: "wait" wait_source + case 68: // base_instruction: "wait" wait_source { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_wait(yylhs.location, resolvable_int(yylhs.location, 1), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 52: // base_instruction: "in" in_source comma value + case 69: // base_instruction: "in" in_source comma value { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_in(yylhs.location, yystack_[2].value.as < enum in_out_set > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 53: // base_instruction: "out" out_target comma value + case 70: // base_instruction: "out" out_target comma value { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_out(yylhs.location, yystack_[2].value.as < enum in_out_set > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 54: // base_instruction: "push" if_full blocking + case 71: // base_instruction: "push" if_full blocking { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_push(yylhs.location, yystack_[1].value.as < bool > (), yystack_[0].value.as < bool > ())); } break; - case 55: // base_instruction: "pull" if_empty blocking + case 72: // base_instruction: "pull" if_empty blocking { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_pull(yylhs.location, yystack_[1].value.as < bool > (), yystack_[0].value.as < bool > ())); } break; - case 56: // base_instruction: "mov" mov_target comma mov_op mov_source - { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_mov(yylhs.location, yystack_[3].value.as < enum mov > (), yystack_[0].value.as < enum mov > (), yystack_[1].value.as < enum mov_op > ())); } + case 73: // base_instruction: "mov" mov_target comma mov_op mov_source + { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_mov(yylhs.location, yystack_[3].value.as < extended_mov > (), yystack_[0].value.as < extended_mov > (), yystack_[1].value.as < enum mov_op > ())); } + break; + + case 74: // base_instruction: "irq" irq_modifiers value "rel" + { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_irq(yylhs.location, yystack_[2].value.as < enum irq > (), yystack_[1].value.as < std::shared_ptr > (), 2)); } + break; + + case 75: // base_instruction: "irq" "prev" irq_modifiers value + { pioasm.check_version(1, yylhs.location, "irq prev"); yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_irq(yylhs.location, yystack_[1].value.as < enum irq > (), yystack_[0].value.as < std::shared_ptr > (), 1)); } + break; + + case 76: // base_instruction: "irq" "next" irq_modifiers value + { pioasm.check_version(1, yylhs.location, "irq next"); yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_irq(yylhs.location, yystack_[1].value.as < enum irq > (), yystack_[0].value.as < std::shared_ptr > (), 3)); } + break; + + case 77: // base_instruction: "irq" "prev" irq_modifiers value "rel" + { pioasm.check_version(1, yylhs.location, "irq prev"); error(yystack_[0].location, "'rel' is not supported for 'irq prev'"); } break; - case 57: // base_instruction: "irq" irq_modifiers value "rel" - { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_irq(yylhs.location, yystack_[2].value.as < enum irq > (), yystack_[1].value.as < std::shared_ptr > (), true)); } + case 78: // base_instruction: "irq" "next" irq_modifiers value "rel" + { pioasm.check_version(1, yylhs.location, "irq next"); error(yystack_[0].location, "'rel' is not supported for 'irq next'"); } break; - case 58: // base_instruction: "irq" irq_modifiers value + case 79: // base_instruction: "irq" irq_modifiers value { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_irq(yylhs.location, yystack_[1].value.as < enum irq > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 59: // base_instruction: "set" set_target comma value + case 80: // base_instruction: "set" set_target comma value { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new instr_set(yylhs.location, yystack_[2].value.as < enum in_out_set > (), yystack_[0].value.as < std::shared_ptr > ())); } break; - case 60: // delay: "[" expression "]" + case 81: // delay: "[" expression "]" { yylhs.value.as < std::shared_ptr > () = yystack_[1].value.as < std::shared_ptr > (); } break; - case 61: // sideset: "side" value + case 82: // sideset: "side" value { yylhs.value.as < std::shared_ptr > () = yystack_[0].value.as < std::shared_ptr > (); } break; - case 62: // condition: "!" "x" + case 83: // condition: "!" "x" { yylhs.value.as < enum condition > () = condition::xz; } break; - case 63: // condition: "x" "--" + case 84: // condition: "x" "--" { yylhs.value.as < enum condition > () = condition::xnz__; } break; - case 64: // condition: "!" "y" + case 85: // condition: "!" "y" { yylhs.value.as < enum condition > () = condition::yz; } break; - case 65: // condition: "y" "--" + case 86: // condition: "y" "--" { yylhs.value.as < enum condition > () = condition::ynz__; } break; - case 66: // condition: "x" "!=" "y" + case 87: // condition: "x" "!=" "y" { yylhs.value.as < enum condition > () = condition::xney; } break; - case 67: // condition: "pin" + case 88: // condition: "pin" { yylhs.value.as < enum condition > () = condition::pin; } break; - case 68: // condition: "!" "osre" + case 89: // condition: "!" "osre" { yylhs.value.as < enum condition > () = condition::osrez; } break; - case 69: // condition: %empty + case 90: // condition: %empty { yylhs.value.as < enum condition > () = condition::al; } break; - case 70: // wait_source: "irq" comma value "rel" - { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::irq, yystack_[1].value.as < std::shared_ptr > (), true)); } + case 91: // wait_source: "irq" comma value "rel" + { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::irq, yystack_[1].value.as < std::shared_ptr > (), 2)); } break; - case 71: // wait_source: "irq" comma value - { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::irq, yystack_[0].value.as < std::shared_ptr > (), false)); } + case 92: // wait_source: "irq" "prev" comma value + { pioasm.check_version(1, yylhs.location, "irq prev"); yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::irq, yystack_[0].value.as < std::shared_ptr > (), 1)); } break; - case 72: // wait_source: "gpio" comma value + case 93: // wait_source: "irq" "next" comma value + { pioasm.check_version(1, yylhs.location, "irq next"); yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::irq, yystack_[0].value.as < std::shared_ptr > (), 3)); } + break; + + case 94: // wait_source: "irq" "prev" comma value "rel" + { pioasm.check_version(1, yylhs.location, "irq prev"); error(yystack_[0].location, "'rel' is not supported for 'irq prev'"); } + break; + + case 95: // wait_source: "irq" "next" comma value "rel" + { pioasm.check_version(1, yylhs.location, "irq next"); error(yystack_[0].location, "'rel' is not supported for 'irq next'"); } + break; + + case 96: // wait_source: "irq" comma value + { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::irq, yystack_[0].value.as < std::shared_ptr > (), 0)); } + break; + + case 97: // wait_source: "gpio" comma value { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::gpio, yystack_[0].value.as < std::shared_ptr > ())); } break; - case 73: // wait_source: "pin" comma value + case 98: // wait_source: "pin" comma value { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::pin, yystack_[0].value.as < std::shared_ptr > ())); } break; - case 76: // in_source: "pins" + case 99: // wait_source: "jmppin" + { pioasm.check_version(1, yylhs.location, "wait jmppin"); yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::jmppin, std::make_shared(yylhs.location, 0))); } + break; + + case 100: // wait_source: "jmppin" "+" value + { pioasm.check_version(1, yylhs.location, "wait jmppin"); yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new wait_source(wait_source::jmppin, yystack_[0].value.as < std::shared_ptr > ())); } + break; + + case 101: // wait_source: %empty + { error(yystack_[0].location, pioasm.version_string(1, "expected irq, gpio, pin or jmp_pin", "expected irq, gpio or pin")); } + break; + + case 102: // fifo_config: "txrx" + { yylhs.value.as < enum fifo_config > () = fifo_config::txrx; } + break; + + case 103: // fifo_config: "tx" + { yylhs.value.as < enum fifo_config > () = fifo_config::tx; } + break; + + case 104: // fifo_config: "rx" + { yylhs.value.as < enum fifo_config > () = fifo_config::rx; } + break; + + case 105: // fifo_config: "txput" + { pioasm.check_version(1, yylhs.location, "txput"); yylhs.value.as < enum fifo_config > () = fifo_config::txput; } + break; + + case 106: // fifo_config: "txget" + { pioasm.check_version(1, yylhs.location, "rxput"); yylhs.value.as < enum fifo_config > () = fifo_config::txget; } + break; + + case 107: // fifo_config: "putget" + { pioasm.check_version(1, yylhs.location, "putget"); yylhs.value.as < enum fifo_config > () = fifo_config::putget; } + break; + + case 108: // fifo_config: %empty + { error(yystack_[0].location, pioasm.version_string(1, "expected txrx, tx, rx, txput, rxget or putget", "expected txrx, tx or rx")); } + break; + + case 111: // in_source: "pins" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_pins; } break; - case 77: // in_source: "x" + case 112: // in_source: "x" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_x; } break; - case 78: // in_source: "y" + case 113: // in_source: "y" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_y; } break; - case 79: // in_source: "null" + case 114: // in_source: "null" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_null; } break; - case 80: // in_source: "isr" + case 115: // in_source: "isr" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_isr; } break; - case 81: // in_source: "osr" + case 116: // in_source: "osr" { yylhs.value.as < enum in_out_set > () = in_out_set::in_osr; } break; - case 82: // in_source: "status" + case 117: // in_source: "status" { yylhs.value.as < enum in_out_set > () = in_out_set::in_status; } break; - case 83: // out_target: "pins" + case 118: // out_target: "pins" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_pins; } break; - case 84: // out_target: "x" + case 119: // out_target: "x" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_x; } break; - case 85: // out_target: "y" + case 120: // out_target: "y" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_y; } break; - case 86: // out_target: "null" + case 121: // out_target: "null" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_null; } break; - case 87: // out_target: "pindirs" + case 122: // out_target: "pindirs" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_pindirs; } break; - case 88: // out_target: "isr" + case 123: // out_target: "isr" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_isr; } break; - case 89: // out_target: "pc" + case 124: // out_target: "pc" { yylhs.value.as < enum in_out_set > () = in_out_set::out_set_pc; } break; - case 90: // out_target: "exec" + case 125: // out_target: "exec" { yylhs.value.as < enum in_out_set > () = in_out_set::out_exec; } break; - case 91: // mov_target: "pins" - { yylhs.value.as < enum mov > () = mov::pins; } + case 126: // mov_target: "pins" + { yylhs.value.as < extended_mov > () = mov::pins; } + break; + + case 127: // mov_target: "x" + { yylhs.value.as < extended_mov > () = mov::x; } + break; + + case 128: // mov_target: "y" + { yylhs.value.as < extended_mov > () = mov::y; } + break; + + case 129: // mov_target: "exec" + { yylhs.value.as < extended_mov > () = mov::exec; } break; - case 92: // mov_target: "x" - { yylhs.value.as < enum mov > () = mov::x; } + case 130: // mov_target: "pc" + { yylhs.value.as < extended_mov > () = mov::pc; } break; - case 93: // mov_target: "y" - { yylhs.value.as < enum mov > () = mov::y; } + case 131: // mov_target: "isr" + { yylhs.value.as < extended_mov > () = mov::isr; } break; - case 94: // mov_target: "exec" - { yylhs.value.as < enum mov > () = mov::exec; } + case 132: // mov_target: "osr" + { yylhs.value.as < extended_mov > () = mov::osr; } break; - case 95: // mov_target: "pc" - { yylhs.value.as < enum mov > () = mov::pc; } + case 133: // mov_target: "pindirs" + { pioasm.check_version(1, yylhs.location, "mov pindirs"); yylhs.value.as < extended_mov > () = mov::pindirs; } break; - case 96: // mov_target: "isr" - { yylhs.value.as < enum mov > () = mov::isr; } + case 134: // mov_target: "rxfifo" "[" "y" "]" + { pioasm.check_version(1, yylhs.location, "mov rxfifo[], "); yylhs.value.as < extended_mov > () = mov::fifo_y; } break; - case 97: // mov_target: "osr" - { yylhs.value.as < enum mov > () = mov::osr; } + case 135: // mov_target: "rxfifo" "[" value "]" + { pioasm.check_version(1, yylhs.location, "mov rxfifo[], "); yylhs.value.as < extended_mov > () = extended_mov(yystack_[1].value.as < std::shared_ptr > ()); } break; - case 98: // mov_source: "pins" - { yylhs.value.as < enum mov > () = mov::pins; } + case 136: // mov_source: "pins" + { yylhs.value.as < extended_mov > () = mov::pins; } break; - case 99: // mov_source: "x" - { yylhs.value.as < enum mov > () = mov::x; } + case 137: // mov_source: "x" + { yylhs.value.as < extended_mov > () = mov::x; } break; - case 100: // mov_source: "y" - { yylhs.value.as < enum mov > () = mov::y; } + case 138: // mov_source: "y" + { yylhs.value.as < extended_mov > () = mov::y; } break; - case 101: // mov_source: "null" - { yylhs.value.as < enum mov > () = mov::null; } + case 139: // mov_source: "null" + { yylhs.value.as < extended_mov > () = mov::null; } break; - case 102: // mov_source: "status" - { yylhs.value.as < enum mov > () = mov::status; } + case 140: // mov_source: "status" + { yylhs.value.as < extended_mov > () = mov::status; } break; - case 103: // mov_source: "isr" - { yylhs.value.as < enum mov > () = mov::isr; } + case 141: // mov_source: "isr" + { yylhs.value.as < extended_mov > () = mov::isr; } break; - case 104: // mov_source: "osr" - { yylhs.value.as < enum mov > () = mov::osr; } + case 142: // mov_source: "osr" + { yylhs.value.as < extended_mov > () = mov::osr; } break; - case 105: // mov_op: "!" + case 143: // mov_source: "rxfifo" "[" "y" "]" + { pioasm.check_version(1, yylhs.location, "mov rxfifo[], "); yylhs.value.as < extended_mov > () = mov::fifo_y; } + break; + + case 144: // mov_source: "rxfifo" "[" value "]" + { pioasm.check_version(1, yylhs.location, "mov rxfifo[], "); yylhs.value.as < extended_mov > () = extended_mov(yystack_[1].value.as < std::shared_ptr > ()); } + break; + + case 145: // mov_op: "!" { yylhs.value.as < enum mov_op > () = mov_op::invert; } break; - case 106: // mov_op: "::" + case 146: // mov_op: "::" { yylhs.value.as < enum mov_op > () = mov_op::bit_reverse; } break; - case 107: // mov_op: %empty + case 147: // mov_op: %empty { yylhs.value.as < enum mov_op > () = mov_op::none; } break; - case 108: // set_target: "pins" + case 148: // set_target: "pins" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_pins; } break; - case 109: // set_target: "x" + case 149: // set_target: "x" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_x; } break; - case 110: // set_target: "y" + case 150: // set_target: "y" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_y; } break; - case 111: // set_target: "pindirs" + case 151: // set_target: "pindirs" { yylhs.value.as < enum in_out_set > () = in_out_set::in_out_set_pindirs; } break; - case 112: // if_full: "iffull" + case 152: // direction: "left" + { yylhs.value.as < bool > () = false; } + break; + + case 153: // direction: "right" + { yylhs.value.as < bool > () = true; } + break; + + case 154: // direction: %empty { yylhs.value.as < bool > () = true; } break; - case 113: // if_full: %empty + case 155: // autop: "auto" + { yylhs.value.as < bool > () = true; } + break; + + case 156: // autop: "manual" { yylhs.value.as < bool > () = false; } break; - case 114: // if_empty: "ifempty" + case 157: // autop: %empty + { yylhs.value.as < bool > () = false; } + break; + + case 158: // threshold: value + { yylhs.value.as < std::shared_ptr > () = yystack_[0].value.as < std::shared_ptr > (); } + break; + + case 159: // threshold: %empty + { yylhs.value.as < std::shared_ptr > () = resolvable_int(yylhs.location, 32); } + break; + + case 160: // if_full: "iffull" + { yylhs.value.as < bool > () = true; } + break; + + case 161: // if_full: %empty + { yylhs.value.as < bool > () = false; } + break; + + case 162: // if_empty: "ifempty" { yylhs.value.as < bool > () = true; } break; - case 115: // if_empty: %empty + case 163: // if_empty: %empty { yylhs.value.as < bool > () = false; } break; - case 116: // blocking: "block" + case 164: // blocking: "block" { yylhs.value.as < bool > () = true; } break; - case 117: // blocking: "noblock" + case 165: // blocking: "noblock" { yylhs.value.as < bool > () = false; } break; - case 118: // blocking: %empty + case 166: // blocking: %empty { yylhs.value.as < bool > () = true; } break; - case 119: // irq_modifiers: "clear" + case 167: // irq_modifiers: "clear" { yylhs.value.as < enum irq > () = irq::clear; } break; - case 120: // irq_modifiers: "wait" + case 168: // irq_modifiers: "wait" { yylhs.value.as < enum irq > () = irq::set_wait; } break; - case 121: // irq_modifiers: "nowait" + case 169: // irq_modifiers: "nowait" { yylhs.value.as < enum irq > () = irq::set; } break; - case 122: // irq_modifiers: "set" + case 170: // irq_modifiers: "set" { yylhs.value.as < enum irq > () = irq::set; } break; - case 123: // irq_modifiers: %empty + case 171: // irq_modifiers: %empty { yylhs.value.as < enum irq > () = irq::set; } break; - case 124: // symbol_def: "identifier" + case 172: // symbol_def: "identifier" { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new symbol(yylhs.location, yystack_[0].value.as < std::string > ())); } break; - case 125: // symbol_def: "public" "identifier" + case 173: // symbol_def: "public" "identifier" { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new symbol(yylhs.location, yystack_[0].value.as < std::string > (), true)); } break; - case 126: // symbol_def: "*" "identifier" + case 174: // symbol_def: "*" "identifier" { yylhs.value.as < std::shared_ptr > () = std::shared_ptr(new symbol(yylhs.location, yystack_[0].value.as < std::string > (), true)); } break; @@ -1924,184 +2215,240 @@ namespace yy { } - const signed char parser::yypact_ninf_ = -52; + const signed char parser::yypact_ninf_ = -76; const signed char parser::yytable_ninf_ = -12; const short parser::yypact_[] = { - 3, -52, -41, -39, -52, -52, -3, 5, 5, 5, - 7, 44, 10, 0, 101, 18, 30, 94, 51, 50, - -52, 20, -52, 13, -52, 88, 17, -52, -52, 129, - -52, -52, 2, 85, -52, -52, 1, 1, -52, -52, - 40, -52, -52, -52, 42, 58, -52, 28, 96, 120, - 120, 120, 120, 15, -52, -52, -52, -52, -52, -52, - -52, -52, 120, -52, -52, -52, -52, -52, -52, -52, - -52, 120, -52, 63, -52, 63, -52, -52, -52, -52, - -52, -52, -52, 120, -52, -52, -52, -52, 5, -52, - -52, -52, -52, 120, -52, -52, -52, -52, 3, -52, - 1, 5, 45, 130, -52, 1, 1, -52, 177, 162, - -52, 97, 132, -52, -52, -52, -52, 87, -52, -52, - 1, 5, 5, 5, 5, -52, 5, 5, -52, -52, - -52, -52, 29, 118, 5, -52, 170, -52, -52, -52, - 182, 177, 1, 1, 1, 1, 1, 1, 1, -52, - -52, -51, -52, 177, 119, -52, -52, -52, -52, -52, - -52, -52, 82, -52, -52, -52, 182, 182, 107, 107, - -52, -52, -52, -52, -52, -52, -52, -52, -52, -52, - -52, -52, -52, -52, -52 + 4, -76, -75, -68, -76, -76, -6, 15, 15, 15, + 10, -10, 27, 203, 35, 15, 15, 15, 6, 8, + 141, 163, -34, -1, 117, 67, 60, -76, -33, -76, + -32, -76, 65, 23, -76, -76, 206, -76, -76, 12, + 72, -76, -76, 70, 70, -76, -76, -4, -76, -76, + -76, -9, -76, -76, -76, -76, -76, -76, -76, -76, + -76, -76, -76, -76, -76, -30, 63, 76, -76, 42, + 42, 22, -76, 119, 74, 87, 9, 87, 87, 96, + 129, -76, -76, -76, -76, -76, -76, -76, -76, 87, + -76, -76, -76, -76, -76, -76, -76, -76, 87, -76, + 157, -76, 157, -76, -76, -76, -76, -76, -76, -76, + -76, 112, 87, -76, -76, 69, 69, -76, -76, 15, + -76, -76, -76, -76, 87, -76, -76, -76, -76, 4, + -76, 70, 15, 90, 137, -76, 70, 70, -76, 257, + 227, -76, 107, 145, 15, 123, 126, 15, 15, -76, + -76, 147, 147, -76, -76, -76, -76, 110, -76, -76, + 70, 87, 87, 15, 15, 15, 15, -76, 15, 15, + -76, -76, -76, -76, 11, 268, 15, 15, 116, 15, + -76, 248, -76, -76, -76, 210, 257, 70, 70, 70, + 70, 70, 70, 70, 70, 70, -76, -76, -21, -76, + 15, 15, -76, -76, -76, -76, 15, 15, -76, 257, + 15, 15, 124, -76, -76, -76, -76, -76, 187, 201, + -76, -76, 135, 149, 153, -76, -76, -76, 210, 210, + 120, 120, -76, -76, -76, 266, 266, -76, -76, -76, + -76, -76, -76, -76, -76, 228, 229, -76, -76, -76, + -76, -76, -76, -76, -76, -76, -76, 287, -76, -76, + -76, -76, -76, 13, 288, 289, -76, -76 }; - const signed char + const unsigned char parser::yydefact_[] = { - 0, 12, 0, 0, 21, 22, 0, 0, 0, 0, - 0, 69, 0, 0, 0, 113, 115, 0, 123, 0, - 47, 0, 124, 0, 28, 0, 0, 3, 10, 9, - 6, 7, 46, 0, 126, 5, 0, 0, 30, 29, - 20, 23, 16, 27, 0, 0, 67, 0, 0, 75, - 75, 75, 75, 0, 51, 76, 79, 77, 78, 80, - 81, 82, 75, 83, 86, 87, 84, 85, 90, 89, - 88, 75, 112, 118, 114, 118, 91, 92, 93, 94, - 95, 96, 97, 75, 120, 122, 121, 119, 0, 108, - 111, 109, 110, 75, 125, 13, 1, 2, 0, 8, - 0, 0, 45, 44, 14, 0, 0, 32, 15, 0, - 19, 18, 0, 68, 62, 64, 63, 0, 65, 74, - 0, 0, 0, 0, 0, 49, 0, 0, 116, 117, - 54, 55, 107, 58, 0, 4, 0, 61, 43, 42, - 40, 41, 0, 0, 0, 0, 0, 0, 0, 31, - 17, 0, 66, 48, 71, 73, 72, 50, 52, 53, - 105, 106, 0, 57, 59, 60, 33, 34, 35, 36, - 37, 38, 39, 25, 26, 24, 70, 98, 101, 99, - 100, 103, 104, 102, 56 + 0, 12, 0, 0, 25, 26, 0, 0, 0, 0, + 0, 0, 0, 108, 40, 0, 0, 0, 90, 101, + 0, 0, 161, 163, 0, 171, 0, 65, 0, 172, + 0, 41, 0, 0, 3, 10, 9, 6, 7, 64, + 0, 174, 5, 0, 0, 43, 42, 21, 27, 16, + 31, 0, 58, 59, 57, 17, 32, 33, 102, 103, + 104, 105, 106, 107, 34, 0, 0, 0, 24, 154, + 154, 0, 88, 0, 0, 110, 110, 110, 110, 99, + 101, 68, 111, 114, 112, 113, 115, 116, 117, 110, + 118, 121, 122, 119, 120, 125, 124, 123, 110, 160, + 166, 162, 166, 126, 133, 127, 128, 129, 130, 131, + 132, 0, 110, 168, 170, 171, 171, 169, 167, 0, + 148, 151, 149, 150, 110, 173, 13, 1, 2, 0, + 8, 0, 0, 63, 62, 14, 0, 0, 45, 15, + 0, 20, 19, 0, 0, 0, 0, 0, 0, 152, + 153, 157, 157, 89, 83, 85, 84, 0, 86, 109, + 0, 110, 110, 0, 0, 0, 0, 67, 0, 0, + 164, 165, 71, 72, 0, 147, 0, 0, 79, 0, + 4, 0, 82, 61, 60, 55, 56, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 44, 18, 0, 39, + 0, 0, 36, 35, 155, 156, 159, 159, 87, 66, + 0, 0, 96, 98, 97, 100, 69, 70, 0, 0, + 145, 146, 0, 75, 76, 74, 80, 81, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 29, 30, 28, + 38, 37, 158, 23, 22, 92, 93, 91, 134, 135, + 136, 139, 137, 138, 141, 142, 140, 0, 73, 77, + 78, 94, 95, 0, 0, 0, 143, 144 }; const short parser::yypgoto_[] = { - -52, -52, -52, 102, -52, -52, -52, -7, -14, 172, - -52, 99, 103, -52, 146, 25, -52, -52, -52, -52, - -52, -52, -52, -52, 128, -52, 198 + -76, -76, -76, 167, -76, -76, -76, -7, -41, -76, + 263, -76, 166, 168, -76, 222, -76, 66, -76, -76, + -76, -76, -76, -76, 233, 152, 98, -76, -76, 204, + 176, 301 }; const short parser::yydefgoto_[] = { - -1, 25, 26, 27, 28, 29, 30, 107, 108, 31, - 32, 102, 103, 49, 54, 120, 62, 71, 83, 184, - 162, 93, 73, 75, 130, 88, 33 + -1, 32, 33, 34, 35, 36, 37, 138, 139, 55, + 38, 39, 133, 134, 75, 81, 64, 160, 89, 98, + 112, 258, 222, 124, 151, 206, 243, 100, 102, 172, + 119, 40 }; const short parser::yytable_[] = { - 40, 41, 42, -11, 1, 53, -11, 37, 43, 2, - 100, 37, 105, 173, 174, 2, 37, 97, 175, 124, - 98, 106, 34, 109, 35, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, - 18, 19, 20, 55, 56, 116, 117, 50, 160, 161, - 51, 52, 50, 57, 58, 51, 52, 59, 60, 21, - 22, 61, 101, 45, 38, 21, 22, 72, 38, 23, - 39, 24, 44, 38, 39, 121, 122, 123, 74, 39, - 95, 133, 84, 94, 46, 110, 136, 126, 96, 85, - 104, 140, 141, 89, 137, 90, 127, 47, 48, 111, - 113, 86, 87, 91, 92, 101, 153, 112, 132, 128, - 129, 114, 115, 118, 154, 155, 156, 157, 134, 158, - 159, 146, 147, 148, 119, 177, 178, 164, 166, 167, - 168, 169, 170, 171, 172, 179, 180, 76, 100, 181, - 182, 152, 150, 183, 63, 64, 65, 77, 78, 79, - 80, 81, 82, 151, 66, 67, 68, 69, 70, 11, - 12, 13, 14, 15, 16, 17, 18, 19, 20, 149, - 163, 176, 142, 143, 144, 145, 146, 147, 148, 165, - 142, 143, 144, 145, 146, 147, 148, 142, 143, 144, - 145, 146, 147, 148, 144, 145, 146, 147, 148, 125, - 135, 99, 139, 131, 36, 138 + 47, 48, 49, 140, -11, 1, 2, -11, 68, 69, + 70, 50, 80, 159, 44, 41, 2, 44, 144, 44, + 131, 44, 42, 128, 145, 146, 129, 71, 99, 3, + 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 141, 76, 72, 125, 77, 78, + 101, 79, 126, 161, 162, 127, 52, 53, 142, 28, + 237, 238, 73, 74, 153, 239, 44, 135, 218, 28, + 264, 136, 65, 143, 29, 132, 54, 147, 154, 155, + 181, 159, 137, 158, 29, 185, 186, 30, 45, 31, + 148, 45, 51, 45, 46, 45, 166, 46, 113, 46, + 113, 46, 178, 66, 67, 114, 120, 114, 121, 209, + 174, 115, 116, 56, 57, 182, 122, 123, 149, 150, + 117, 118, 117, 118, 191, 192, 193, 199, 156, 157, + 202, 203, 163, 164, 165, 131, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 168, 212, 213, 214, 215, + 45, 216, 217, 132, 169, 197, 46, 219, 198, 223, + 224, 200, 226, 103, 201, 104, 76, 208, 175, 77, + 78, 225, 79, 105, 106, 107, 108, 109, 110, 247, + 179, 250, 251, 240, 241, 111, 248, 82, 83, 242, + 242, 252, 253, 245, 246, 254, 255, 84, 85, 256, + 249, 86, 87, 257, 259, 88, 170, 171, 260, 90, + 91, 92, 189, 190, 191, 192, 193, 210, 211, 93, + 94, 95, 96, 97, 196, 204, 205, 187, 188, 189, + 190, 191, 192, 193, 194, 195, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27, 265, 227, 187, 188, + 189, 190, 191, 192, 193, 194, 195, 187, 188, 189, + 190, 191, 192, 193, 194, 195, 187, 188, 189, 190, + 191, 192, 193, 58, 59, 60, 61, 62, 63, 220, + 221, 176, 177, 261, 262, 263, 180, 266, 267, 130, + 184, 183, 167, 152, 207, 244, 173, 43 }; - const unsigned char + const short parser::yycheck_[] = { - 7, 8, 9, 0, 1, 12, 3, 6, 1, 12, - 8, 6, 11, 64, 65, 12, 6, 0, 69, 4, - 3, 20, 63, 37, 63, 22, 23, 24, 25, 26, - 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, - 37, 38, 39, 43, 44, 17, 18, 37, 19, 20, - 40, 41, 37, 53, 54, 40, 41, 57, 58, 62, - 63, 61, 60, 19, 63, 62, 63, 49, 63, 66, - 69, 68, 65, 63, 69, 50, 51, 52, 48, 69, - 67, 88, 31, 63, 40, 45, 100, 62, 0, 38, - 5, 105, 106, 43, 101, 45, 71, 53, 54, 59, - 42, 50, 51, 53, 54, 60, 120, 65, 83, 46, - 47, 53, 54, 17, 121, 122, 123, 124, 93, 126, - 127, 14, 15, 16, 4, 43, 44, 134, 142, 143, - 144, 145, 146, 147, 148, 53, 54, 43, 8, 57, - 58, 54, 45, 61, 43, 44, 45, 53, 54, 55, - 56, 57, 58, 21, 53, 54, 55, 56, 57, 30, - 31, 32, 33, 34, 35, 36, 37, 38, 39, 7, - 52, 52, 10, 11, 12, 13, 14, 15, 16, 9, - 10, 11, 12, 13, 14, 15, 16, 10, 11, 12, - 13, 14, 15, 16, 12, 13, 14, 15, 16, 53, - 98, 29, 103, 75, 6, 102 + 7, 8, 9, 44, 0, 1, 12, 3, 15, 16, + 17, 1, 19, 4, 6, 90, 12, 6, 48, 6, + 8, 6, 90, 0, 54, 55, 3, 21, 62, 25, + 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, + 46, 47, 48, 49, 58, 47, 50, 90, 50, 51, + 61, 53, 94, 54, 55, 0, 76, 77, 72, 75, + 91, 92, 66, 67, 52, 96, 6, 5, 67, 75, + 67, 11, 47, 92, 90, 73, 96, 24, 66, 67, + 131, 4, 22, 19, 90, 136, 137, 93, 90, 95, + 24, 90, 92, 90, 96, 90, 10, 96, 41, 96, + 41, 96, 119, 78, 79, 48, 56, 48, 58, 160, + 8, 54, 55, 96, 97, 132, 66, 67, 86, 87, + 63, 64, 63, 64, 14, 15, 16, 144, 19, 20, + 147, 148, 76, 77, 78, 8, 187, 188, 189, 190, + 191, 192, 193, 194, 195, 89, 163, 164, 165, 166, + 90, 168, 169, 73, 98, 58, 96, 174, 23, 176, + 177, 48, 179, 56, 48, 58, 47, 67, 112, 50, + 51, 65, 53, 66, 67, 68, 69, 70, 71, 65, + 124, 56, 57, 200, 201, 78, 9, 56, 57, 206, + 207, 66, 67, 210, 211, 70, 71, 66, 67, 74, + 9, 70, 71, 78, 65, 74, 59, 60, 65, 56, + 57, 58, 12, 13, 14, 15, 16, 161, 162, 66, + 67, 68, 69, 70, 7, 88, 89, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 263, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 10, 11, 12, 13, + 14, 15, 16, 80, 81, 82, 83, 84, 85, 21, + 22, 115, 116, 65, 65, 8, 129, 9, 9, 36, + 134, 133, 80, 70, 152, 207, 102, 6 }; - const signed char + const unsigned char parser::yystos_[] = { - 0, 1, 12, 22, 23, 24, 25, 26, 27, 28, - 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, - 39, 62, 63, 66, 68, 71, 72, 73, 74, 75, - 76, 79, 80, 96, 63, 63, 96, 6, 63, 69, - 77, 77, 77, 1, 65, 19, 40, 53, 54, 83, - 37, 40, 41, 77, 84, 43, 44, 53, 54, 57, - 58, 61, 86, 43, 44, 45, 53, 54, 55, 56, - 57, 87, 49, 92, 48, 93, 43, 53, 54, 55, - 56, 57, 58, 88, 31, 38, 50, 51, 95, 43, - 45, 53, 54, 91, 63, 67, 0, 0, 3, 79, - 8, 60, 81, 82, 5, 11, 20, 77, 78, 78, - 45, 59, 65, 42, 53, 54, 17, 18, 17, 4, - 85, 85, 85, 85, 4, 84, 85, 85, 46, 47, - 94, 94, 85, 77, 85, 73, 78, 77, 82, 81, - 78, 78, 10, 11, 12, 13, 14, 15, 16, 7, - 45, 21, 54, 78, 77, 77, 77, 77, 77, 77, - 19, 20, 90, 52, 77, 9, 78, 78, 78, 78, - 78, 78, 78, 64, 65, 69, 52, 43, 44, 53, - 54, 57, 58, 61, 89 + 0, 1, 12, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, 49, 75, 90, + 93, 95, 99, 100, 101, 102, 103, 104, 108, 109, + 129, 90, 90, 129, 6, 90, 96, 105, 105, 105, + 1, 92, 76, 77, 96, 107, 96, 97, 80, 81, + 82, 83, 84, 85, 114, 47, 78, 79, 105, 105, + 105, 21, 50, 66, 67, 112, 47, 50, 51, 53, + 105, 113, 56, 57, 66, 67, 70, 71, 74, 116, + 56, 57, 58, 66, 67, 68, 69, 70, 117, 62, + 125, 61, 126, 56, 58, 66, 67, 68, 69, 70, + 71, 78, 118, 41, 48, 54, 55, 63, 64, 128, + 56, 58, 66, 67, 121, 90, 94, 0, 0, 3, + 108, 8, 73, 110, 111, 5, 11, 22, 105, 106, + 106, 58, 72, 92, 48, 54, 55, 24, 24, 86, + 87, 122, 122, 52, 66, 67, 19, 20, 19, 4, + 115, 54, 55, 115, 115, 115, 10, 113, 115, 115, + 59, 60, 127, 127, 8, 115, 128, 128, 105, 115, + 101, 106, 105, 111, 110, 106, 106, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 7, 58, 23, 105, + 48, 48, 105, 105, 88, 89, 123, 123, 67, 106, + 115, 115, 105, 105, 105, 105, 105, 105, 67, 105, + 21, 22, 120, 105, 105, 65, 105, 9, 106, 106, + 106, 106, 106, 106, 106, 106, 106, 91, 92, 96, + 105, 105, 105, 124, 124, 105, 105, 65, 9, 9, + 56, 57, 66, 67, 70, 71, 74, 78, 119, 65, + 65, 65, 65, 8, 67, 105, 9, 9 }; - const signed char + const unsigned char parser::yyr1_[] = { - 0, 70, 71, 72, 72, 73, 73, 73, 73, 73, - 73, 73, 73, 74, 75, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, 76, 77, - 77, 77, 78, 78, 78, 78, 78, 78, 78, 78, - 78, 78, 79, 79, 79, 79, 79, 80, 80, 80, - 80, 80, 80, 80, 80, 80, 80, 80, 80, 80, - 81, 82, 83, 83, 83, 83, 83, 83, 83, 83, - 84, 84, 84, 84, 85, 85, 86, 86, 86, 86, - 86, 86, 86, 87, 87, 87, 87, 87, 87, 87, - 87, 88, 88, 88, 88, 88, 88, 88, 89, 89, - 89, 89, 89, 89, 89, 90, 90, 90, 91, 91, - 91, 91, 92, 92, 93, 93, 94, 94, 94, 95, - 95, 95, 95, 95, 96, 96, 96 + 0, 98, 99, 100, 100, 101, 101, 101, 101, 101, + 101, 101, 101, 102, 103, 104, 104, 104, 104, 104, + 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, + 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, + 104, 104, 105, 105, 105, 106, 106, 106, 106, 106, + 106, 106, 106, 106, 106, 106, 106, 107, 107, 107, + 108, 108, 108, 108, 108, 109, 109, 109, 109, 109, + 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, + 109, 110, 111, 112, 112, 112, 112, 112, 112, 112, + 112, 113, 113, 113, 113, 113, 113, 113, 113, 113, + 113, 113, 114, 114, 114, 114, 114, 114, 114, 115, + 115, 116, 116, 116, 116, 116, 116, 116, 117, 117, + 117, 117, 117, 117, 117, 117, 118, 118, 118, 118, + 118, 118, 118, 118, 118, 118, 119, 119, 119, 119, + 119, 119, 119, 119, 119, 120, 120, 120, 121, 121, + 121, 121, 122, 122, 122, 123, 123, 123, 124, 124, + 125, 125, 126, 126, 127, 127, 127, 128, 128, 128, + 128, 128, 129, 129, 129 }; const signed char parser::yyr2_[] = { 0, 2, 2, 1, 3, 2, 1, 1, 2, 1, - 1, 0, 1, 2, 2, 3, 2, 4, 3, 3, - 2, 1, 1, 2, 5, 5, 5, 2, 1, 1, - 1, 3, 1, 3, 3, 3, 3, 3, 3, 3, - 2, 2, 3, 3, 2, 2, 1, 1, 4, 3, - 4, 2, 4, 4, 3, 3, 5, 4, 3, 4, - 3, 2, 2, 2, 2, 2, 3, 1, 2, 0, - 4, 3, 3, 3, 1, 0, 1, 1, 1, 1, + 1, 0, 1, 2, 2, 3, 2, 2, 4, 3, + 3, 2, 5, 5, 2, 1, 1, 2, 5, 5, + 5, 2, 2, 2, 2, 4, 4, 5, 5, 4, + 1, 1, 1, 1, 3, 1, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, + 3, 3, 2, 2, 1, 1, 4, 3, 2, 4, + 4, 3, 3, 5, 4, 4, 4, 5, 5, 3, + 4, 3, 2, 2, 2, 2, 2, 3, 1, 2, + 0, 4, 4, 4, 5, 5, 3, 3, 3, 1, + 3, 0, 1, 1, 1, 1, 1, 1, 0, 1, + 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, - 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, - 1, 1, 1, 0, 1, 2, 2 + 1, 1, 1, 1, 4, 4, 1, 1, 1, 1, + 1, 1, 1, 4, 4, 1, 1, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 1, 0, 1, 0, + 1, 0, 1, 0, 1, 1, 0, 1, 1, 1, + 1, 0, 1, 2, 2 }; @@ -2113,22 +2460,28 @@ namespace yy { { "\"end of file\"", "error", "\"invalid token\"", "\"end of line\"", "\",\"", "\":\"", "\"(\"", "\")\"", "\"[\"", "\"]\"", "\"+\"", "\"-\"", - "\"*\"", "\"/\"", "\"|\"", "\"&\"", "\"^\"", "\"--\"", "\"!=\"", "\"!\"", - "\"::\"", "\"=\"", "\".program\"", "\".wrap_target\"", "\".wrap\"", - "\".define\"", "\".side_set\"", "\".word\"", "\".origin\"", - "\".lang_opt\"", "\"jmp\"", "\"wait\"", "\"in\"", "\"out\"", "\"push\"", + "\"*\"", "\"/\"", "\"|\"", "\"&\"", "\"^\"", "\"<<\"", "\">>\"", + "\"--\"", "\"!=\"", "\"!\"", "\"::\"", "\"=\"", "\"<\"", "\".program\"", + "\".wrap_target\"", "\".wrap\"", "\".define\"", "\".side_set\"", + "\".word\"", "\".origin\"", "\".lang_opt\"", "\".pio_version\"", + "\".clock_div\"", "\".fifo\"", "\".mov_status\"", "\".set\"", "\".out\"", + "\".in\"", "\"jmp\"", "\"wait\"", "\"in\"", "\"out\"", "\"push\"", "\"pull\"", "\"mov\"", "\"irq\"", "\"set\"", "\"nop\"", "\"pin\"", - "\"gpio\"", "\"osre\"", "\"pins\"", "\"null\"", "\"pindirs\"", - "\"block\"", "\"noblock\"", "\"ifempty\"", "\"iffull\"", "\"nowait\"", - "\"clear\"", "\"rel\"", "\"x\"", "\"y\"", "\"exec\"", "\"pc\"", - "\"isr\"", "\"osr\"", "\"opt\"", "\"side\"", "\"status\"", "\"public\"", + "\"gpio\"", "\"osre\"", "\"jmppin\"", "\"prev\"", "\"next\"", "\"pins\"", + "\"null\"", "\"pindirs\"", "\"block\"", "\"noblock\"", "\"ifempty\"", + "\"iffull\"", "\"nowait\"", "\"clear\"", "\"rel\"", "\"x\"", "\"y\"", + "\"exec\"", "\"pc\"", "\"isr\"", "\"osr\"", "\"opt\"", "\"side\"", + "\"status\"", "\"public\"", "\"rp2040\"", "\"rp2350\"", "\"rxfifo\"", + "\"txfifo\"", "\"txrx\"", "\"tx\"", "\"rx\"", "\"txput\"", "\"txget\"", + "\"putget\"", "\"left\"", "\"right\"", "\"auto\"", "\"manual\"", "\"identifier\"", "\"string\"", "\"text\"", "\"code block\"", "\"%}\"", - "UNKNOWN_DIRECTIVE", "\"integer\"", "$accept", "file", "lines", "line", - "code_block", "label_decl", "directive", "value", "expression", - "instruction", "base_instruction", "delay", "sideset", "condition", - "wait_source", "comma", "in_source", "out_target", "mov_target", - "mov_source", "mov_op", "set_target", "if_full", "if_empty", "blocking", - "irq_modifiers", "symbol_def", YY_NULLPTR + "UNKNOWN_DIRECTIVE", "\"integer\"", "\"float\"", "$accept", "file", + "lines", "line", "code_block", "label_decl", "directive", "value", + "expression", "pio_version", "instruction", "base_instruction", "delay", + "sideset", "condition", "wait_source", "fifo_config", "comma", + "in_source", "out_target", "mov_target", "mov_source", "mov_op", + "set_target", "direction", "autop", "threshold", "if_full", "if_empty", + "blocking", "irq_modifiers", "symbol_def", YY_NULLPTR }; #endif @@ -2137,19 +2490,24 @@ namespace yy { const short parser::yyrline_[] = { - 0, 136, 136, 140, 141, 144, 145, 146, 147, 148, - 149, 150, 151, 155, 159, 162, 163, 164, 165, 166, - 167, 168, 169, 170, 171, 172, 173, 174, 175, 180, - 181, 182, 186, 187, 188, 189, 190, 191, 192, 193, - 194, 195, 199, 200, 201, 202, 203, 207, 208, 209, + 0, 169, 169, 173, 174, 177, 178, 179, 180, 181, + 182, 183, 184, 188, 192, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, - 224, 228, 232, 233, 234, 235, 236, 237, 238, 239, - 243, 244, 245, 246, 248, 248, 251, 252, 253, 254, - 255, 256, 257, 260, 261, 262, 263, 264, 265, 266, - 267, 270, 271, 272, 273, 274, 275, 276, 279, 280, - 281, 282, 283, 284, 285, 289, 290, 291, 295, 296, - 297, 298, 302, 303, 307, 308, 312, 313, 314, 318, - 319, 320, 321, 322, 326, 327, 328 + 220, 221, 226, 227, 228, 232, 233, 234, 235, 236, + 237, 238, 239, 240, 241, 242, 243, 246, 247, 248, + 252, 253, 254, 255, 256, 260, 261, 262, 263, 264, + 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, + 275, 280, 284, 288, 289, 290, 291, 292, 293, 294, + 295, 299, 300, 301, 302, 303, 304, 305, 306, 307, + 308, 309, 312, 313, 314, 315, 316, 317, 318, 321, + 321, 324, 325, 326, 327, 328, 329, 330, 333, 334, + 335, 336, 337, 338, 339, 340, 343, 344, 345, 346, + 347, 348, 349, 350, 351, 352, 355, 356, 357, 358, + 359, 360, 361, 362, 363, 367, 368, 369, 373, 374, + 375, 376, 380, 381, 382, 386, 387, 388, 391, 392, + 396, 397, 401, 402, 406, 407, 408, 412, 413, 414, + 415, 416, 420, 421, 422 }; void @@ -2205,4 +2563,3 @@ void yy::parser::error(const location_type& l, const std::string& m) std::cerr << m << '\n'; } } - diff --git a/tools/pioasm/gen/parser.hpp b/tools/pioasm/gen/parser.hpp index 11d83931a..65a7285f6 100644 --- a/tools/pioasm/gen/parser.hpp +++ b/tools/pioasm/gen/parser.hpp @@ -32,7 +32,7 @@ /** - ** \file pico_sdk/tools/pioasm/gen/parser.hpp + ** \file tools/pioasm/gen/parser.hpp ** Define the yy::parser class. */ @@ -42,8 +42,8 @@ // especially those whose name start with YY_ or yy_. They are // private implementation details that can be changed or removed. -#ifndef YY_YY_HOME_GRAHAM_DEV_MU_PICO_SDK_TOOLS_PIOASM_GEN_PARSER_HPP_INCLUDED -# define YY_YY_HOME_GRAHAM_DEV_MU_PICO_SDK_TOOLS_PIOASM_GEN_PARSER_HPP_INCLUDED +#ifndef YY_YY_HOME_GRAHAM_DEV_AMY_AMY_SDK_TOOLS_PIOASM_GEN_PARSER_HPP_INCLUDED +# define YY_YY_HOME_GRAHAM_DEV_AMY_AMY_SDK_TOOLS_PIOASM_GEN_PARSER_HPP_INCLUDED // "%code requires" blocks. #include @@ -380,6 +380,8 @@ namespace yy { /// An auxiliary type to compute the largest semantic type. union union_type { + // direction + // autop // if_full // if_empty // blocking @@ -388,40 +390,47 @@ namespace yy { // condition char dummy2[sizeof (enum condition)]; + // fifo_config + char dummy3[sizeof (enum fifo_config)]; + // in_source // out_target // set_target - char dummy3[sizeof (enum in_out_set)]; + char dummy4[sizeof (enum in_out_set)]; // irq_modifiers - char dummy4[sizeof (enum irq)]; + char dummy5[sizeof (enum irq)]; + + // mov_op + char dummy6[sizeof (enum mov_op)]; // mov_target // mov_source - char dummy5[sizeof (enum mov)]; + char dummy7[sizeof (extended_mov)]; - // mov_op - char dummy6[sizeof (enum mov_op)]; + // "float" + char dummy8[sizeof (float)]; // "integer" - char dummy7[sizeof (int)]; + char dummy9[sizeof (int)]; // instruction // base_instruction - char dummy8[sizeof (std::shared_ptr)]; + char dummy10[sizeof (std::shared_ptr)]; // value // expression // delay // sideset - char dummy9[sizeof (std::shared_ptr)]; + // threshold + char dummy11[sizeof (std::shared_ptr)]; // label_decl // symbol_def - char dummy10[sizeof (std::shared_ptr)]; + char dummy12[sizeof (std::shared_ptr)]; // wait_source - char dummy11[sizeof (std::shared_ptr)]; + char dummy13[sizeof (std::shared_ptr)]; // "identifier" // "string" @@ -429,7 +438,10 @@ namespace yy { // "code block" // "%}" // UNKNOWN_DIRECTIVE - char dummy12[sizeof (std::string)]; + char dummy14[sizeof (std::string)]; + + // pio_version + char dummy15[sizeof (uint)]; }; /// The size of the largest semantic type. @@ -492,59 +504,87 @@ namespace yy { TOK_OR = 269, // "|" TOK_AND = 270, // "&" TOK_XOR = 271, // "^" - TOK_POST_DECREMENT = 272, // "--" - TOK_NOT_EQUAL = 273, // "!=" - TOK_NOT = 274, // "!" - TOK_REVERSE = 275, // "::" - TOK_EQUAL = 276, // "=" - TOK_PROGRAM = 277, // ".program" - TOK_WRAP_TARGET = 278, // ".wrap_target" - TOK_WRAP = 279, // ".wrap" - TOK_DEFINE = 280, // ".define" - TOK_SIDE_SET = 281, // ".side_set" - TOK_WORD = 282, // ".word" - TOK_ORIGIN = 283, // ".origin" - TOK_LANG_OPT = 284, // ".lang_opt" - TOK_JMP = 285, // "jmp" - TOK_WAIT = 286, // "wait" - TOK_IN = 287, // "in" - TOK_OUT = 288, // "out" - TOK_PUSH = 289, // "push" - TOK_PULL = 290, // "pull" - TOK_MOV = 291, // "mov" - TOK_IRQ = 292, // "irq" - TOK_SET = 293, // "set" - TOK_NOP = 294, // "nop" - TOK_PIN = 295, // "pin" - TOK_GPIO = 296, // "gpio" - TOK_OSRE = 297, // "osre" - TOK_PINS = 298, // "pins" - TOK_NULL = 299, // "null" - TOK_PINDIRS = 300, // "pindirs" - TOK_BLOCK = 301, // "block" - TOK_NOBLOCK = 302, // "noblock" - TOK_IFEMPTY = 303, // "ifempty" - TOK_IFFULL = 304, // "iffull" - TOK_NOWAIT = 305, // "nowait" - TOK_CLEAR = 306, // "clear" - TOK_REL = 307, // "rel" - TOK_X = 308, // "x" - TOK_Y = 309, // "y" - TOK_EXEC = 310, // "exec" - TOK_PC = 311, // "pc" - TOK_ISR = 312, // "isr" - TOK_OSR = 313, // "osr" - TOK_OPTIONAL = 314, // "opt" - TOK_SIDE = 315, // "side" - TOK_STATUS = 316, // "status" - TOK_PUBLIC = 317, // "public" - TOK_ID = 318, // "identifier" - TOK_STRING = 319, // "string" - TOK_NON_WS = 320, // "text" - TOK_CODE_BLOCK_START = 321, // "code block" - TOK_CODE_BLOCK_CONTENTS = 322, // "%}" - TOK_UNKNOWN_DIRECTIVE = 323, // UNKNOWN_DIRECTIVE - TOK_INT = 324 // "integer" + TOK_SHL = 272, // "<<" + TOK_SHR = 273, // ">>" + TOK_POST_DECREMENT = 274, // "--" + TOK_NOT_EQUAL = 275, // "!=" + TOK_NOT = 276, // "!" + TOK_REVERSE = 277, // "::" + TOK_ASSIGN = 278, // "=" + TOK_LESSTHAN = 279, // "<" + TOK_PROGRAM = 280, // ".program" + TOK_WRAP_TARGET = 281, // ".wrap_target" + TOK_WRAP = 282, // ".wrap" + TOK_DEFINE = 283, // ".define" + TOK_SIDE_SET = 284, // ".side_set" + TOK_WORD = 285, // ".word" + TOK_ORIGIN = 286, // ".origin" + TOK_LANG_OPT = 287, // ".lang_opt" + TOK_PIO_VERSION = 288, // ".pio_version" + TOK_CLOCK_DIV = 289, // ".clock_div" + TOK_FIFO = 290, // ".fifo" + TOK_MOV_STATUS = 291, // ".mov_status" + TOK_DOT_SET = 292, // ".set" + TOK_DOT_OUT = 293, // ".out" + TOK_DOT_IN = 294, // ".in" + TOK_JMP = 295, // "jmp" + TOK_WAIT = 296, // "wait" + TOK_IN = 297, // "in" + TOK_OUT = 298, // "out" + TOK_PUSH = 299, // "push" + TOK_PULL = 300, // "pull" + TOK_MOV = 301, // "mov" + TOK_IRQ = 302, // "irq" + TOK_SET = 303, // "set" + TOK_NOP = 304, // "nop" + TOK_PIN = 305, // "pin" + TOK_GPIO = 306, // "gpio" + TOK_OSRE = 307, // "osre" + TOK_JMPPIN = 308, // "jmppin" + TOK_PREV = 309, // "prev" + TOK_NEXT = 310, // "next" + TOK_PINS = 311, // "pins" + TOK_NULL = 312, // "null" + TOK_PINDIRS = 313, // "pindirs" + TOK_BLOCK = 314, // "block" + TOK_NOBLOCK = 315, // "noblock" + TOK_IFEMPTY = 316, // "ifempty" + TOK_IFFULL = 317, // "iffull" + TOK_NOWAIT = 318, // "nowait" + TOK_CLEAR = 319, // "clear" + TOK_REL = 320, // "rel" + TOK_X = 321, // "x" + TOK_Y = 322, // "y" + TOK_EXEC = 323, // "exec" + TOK_PC = 324, // "pc" + TOK_ISR = 325, // "isr" + TOK_OSR = 326, // "osr" + TOK_OPTIONAL = 327, // "opt" + TOK_SIDE = 328, // "side" + TOK_STATUS = 329, // "status" + TOK_PUBLIC = 330, // "public" + TOK_RP2040 = 331, // "rp2040" + TOK_RP2350 = 332, // "rp2350" + TOK_RXFIFO = 333, // "rxfifo" + TOK_TXFIFO = 334, // "txfifo" + TOK_TXRX = 335, // "txrx" + TOK_TX = 336, // "tx" + TOK_RX = 337, // "rx" + TOK_TXPUT = 338, // "txput" + TOK_TXGET = 339, // "txget" + TOK_PUTGET = 340, // "putget" + TOK_LEFT = 341, // "left" + TOK_RIGHT = 342, // "right" + TOK_AUTO = 343, // "auto" + TOK_MANUAL = 344, // "manual" + TOK_ID = 345, // "identifier" + TOK_STRING = 346, // "string" + TOK_NON_WS = 347, // "text" + TOK_CODE_BLOCK_START = 348, // "code block" + TOK_CODE_BLOCK_CONTENTS = 349, // "%}" + TOK_UNKNOWN_DIRECTIVE = 350, // UNKNOWN_DIRECTIVE + TOK_INT = 351, // "integer" + TOK_FLOAT = 352 // "float" }; /// Backward compatibility alias (Bison 3.6). typedef token_kind_type yytokentype; @@ -561,7 +601,7 @@ namespace yy { { enum symbol_kind_type { - YYNTOKENS = 70, ///< Number of tokens. + YYNTOKENS = 98, ///< Number of tokens. S_YYEMPTY = -2, S_YYEOF = 0, // "end of file" S_YYerror = 1, // error @@ -580,86 +620,119 @@ namespace yy { S_OR = 14, // "|" S_AND = 15, // "&" S_XOR = 16, // "^" - S_POST_DECREMENT = 17, // "--" - S_NOT_EQUAL = 18, // "!=" - S_NOT = 19, // "!" - S_REVERSE = 20, // "::" - S_EQUAL = 21, // "=" - S_PROGRAM = 22, // ".program" - S_WRAP_TARGET = 23, // ".wrap_target" - S_WRAP = 24, // ".wrap" - S_DEFINE = 25, // ".define" - S_SIDE_SET = 26, // ".side_set" - S_WORD = 27, // ".word" - S_ORIGIN = 28, // ".origin" - S_LANG_OPT = 29, // ".lang_opt" - S_JMP = 30, // "jmp" - S_WAIT = 31, // "wait" - S_IN = 32, // "in" - S_OUT = 33, // "out" - S_PUSH = 34, // "push" - S_PULL = 35, // "pull" - S_MOV = 36, // "mov" - S_IRQ = 37, // "irq" - S_SET = 38, // "set" - S_NOP = 39, // "nop" - S_PIN = 40, // "pin" - S_GPIO = 41, // "gpio" - S_OSRE = 42, // "osre" - S_PINS = 43, // "pins" - S_NULL = 44, // "null" - S_PINDIRS = 45, // "pindirs" - S_BLOCK = 46, // "block" - S_NOBLOCK = 47, // "noblock" - S_IFEMPTY = 48, // "ifempty" - S_IFFULL = 49, // "iffull" - S_NOWAIT = 50, // "nowait" - S_CLEAR = 51, // "clear" - S_REL = 52, // "rel" - S_X = 53, // "x" - S_Y = 54, // "y" - S_EXEC = 55, // "exec" - S_PC = 56, // "pc" - S_ISR = 57, // "isr" - S_OSR = 58, // "osr" - S_OPTIONAL = 59, // "opt" - S_SIDE = 60, // "side" - S_STATUS = 61, // "status" - S_PUBLIC = 62, // "public" - S_ID = 63, // "identifier" - S_STRING = 64, // "string" - S_NON_WS = 65, // "text" - S_CODE_BLOCK_START = 66, // "code block" - S_CODE_BLOCK_CONTENTS = 67, // "%}" - S_UNKNOWN_DIRECTIVE = 68, // UNKNOWN_DIRECTIVE - S_INT = 69, // "integer" - S_YYACCEPT = 70, // $accept - S_file = 71, // file - S_lines = 72, // lines - S_line = 73, // line - S_code_block = 74, // code_block - S_label_decl = 75, // label_decl - S_directive = 76, // directive - S_value = 77, // value - S_expression = 78, // expression - S_instruction = 79, // instruction - S_base_instruction = 80, // base_instruction - S_delay = 81, // delay - S_sideset = 82, // sideset - S_condition = 83, // condition - S_wait_source = 84, // wait_source - S_comma = 85, // comma - S_in_source = 86, // in_source - S_out_target = 87, // out_target - S_mov_target = 88, // mov_target - S_mov_source = 89, // mov_source - S_mov_op = 90, // mov_op - S_set_target = 91, // set_target - S_if_full = 92, // if_full - S_if_empty = 93, // if_empty - S_blocking = 94, // blocking - S_irq_modifiers = 95, // irq_modifiers - S_symbol_def = 96 // symbol_def + S_SHL = 17, // "<<" + S_SHR = 18, // ">>" + S_POST_DECREMENT = 19, // "--" + S_NOT_EQUAL = 20, // "!=" + S_NOT = 21, // "!" + S_REVERSE = 22, // "::" + S_ASSIGN = 23, // "=" + S_LESSTHAN = 24, // "<" + S_PROGRAM = 25, // ".program" + S_WRAP_TARGET = 26, // ".wrap_target" + S_WRAP = 27, // ".wrap" + S_DEFINE = 28, // ".define" + S_SIDE_SET = 29, // ".side_set" + S_WORD = 30, // ".word" + S_ORIGIN = 31, // ".origin" + S_LANG_OPT = 32, // ".lang_opt" + S_PIO_VERSION = 33, // ".pio_version" + S_CLOCK_DIV = 34, // ".clock_div" + S_FIFO = 35, // ".fifo" + S_MOV_STATUS = 36, // ".mov_status" + S_DOT_SET = 37, // ".set" + S_DOT_OUT = 38, // ".out" + S_DOT_IN = 39, // ".in" + S_JMP = 40, // "jmp" + S_WAIT = 41, // "wait" + S_IN = 42, // "in" + S_OUT = 43, // "out" + S_PUSH = 44, // "push" + S_PULL = 45, // "pull" + S_MOV = 46, // "mov" + S_IRQ = 47, // "irq" + S_SET = 48, // "set" + S_NOP = 49, // "nop" + S_PIN = 50, // "pin" + S_GPIO = 51, // "gpio" + S_OSRE = 52, // "osre" + S_JMPPIN = 53, // "jmppin" + S_PREV = 54, // "prev" + S_NEXT = 55, // "next" + S_PINS = 56, // "pins" + S_NULL = 57, // "null" + S_PINDIRS = 58, // "pindirs" + S_BLOCK = 59, // "block" + S_NOBLOCK = 60, // "noblock" + S_IFEMPTY = 61, // "ifempty" + S_IFFULL = 62, // "iffull" + S_NOWAIT = 63, // "nowait" + S_CLEAR = 64, // "clear" + S_REL = 65, // "rel" + S_X = 66, // "x" + S_Y = 67, // "y" + S_EXEC = 68, // "exec" + S_PC = 69, // "pc" + S_ISR = 70, // "isr" + S_OSR = 71, // "osr" + S_OPTIONAL = 72, // "opt" + S_SIDE = 73, // "side" + S_STATUS = 74, // "status" + S_PUBLIC = 75, // "public" + S_RP2040 = 76, // "rp2040" + S_RP2350 = 77, // "rp2350" + S_RXFIFO = 78, // "rxfifo" + S_TXFIFO = 79, // "txfifo" + S_TXRX = 80, // "txrx" + S_TX = 81, // "tx" + S_RX = 82, // "rx" + S_TXPUT = 83, // "txput" + S_TXGET = 84, // "txget" + S_PUTGET = 85, // "putget" + S_LEFT = 86, // "left" + S_RIGHT = 87, // "right" + S_AUTO = 88, // "auto" + S_MANUAL = 89, // "manual" + S_ID = 90, // "identifier" + S_STRING = 91, // "string" + S_NON_WS = 92, // "text" + S_CODE_BLOCK_START = 93, // "code block" + S_CODE_BLOCK_CONTENTS = 94, // "%}" + S_UNKNOWN_DIRECTIVE = 95, // UNKNOWN_DIRECTIVE + S_INT = 96, // "integer" + S_FLOAT = 97, // "float" + S_YYACCEPT = 98, // $accept + S_file = 99, // file + S_lines = 100, // lines + S_line = 101, // line + S_code_block = 102, // code_block + S_label_decl = 103, // label_decl + S_directive = 104, // directive + S_value = 105, // value + S_expression = 106, // expression + S_pio_version = 107, // pio_version + S_instruction = 108, // instruction + S_base_instruction = 109, // base_instruction + S_delay = 110, // delay + S_sideset = 111, // sideset + S_condition = 112, // condition + S_wait_source = 113, // wait_source + S_fifo_config = 114, // fifo_config + S_comma = 115, // comma + S_in_source = 116, // in_source + S_out_target = 117, // out_target + S_mov_target = 118, // mov_target + S_mov_source = 119, // mov_source + S_mov_op = 120, // mov_op + S_set_target = 121, // set_target + S_direction = 122, // direction + S_autop = 123, // autop + S_threshold = 124, // threshold + S_if_full = 125, // if_full + S_if_empty = 126, // if_empty + S_blocking = 127, // blocking + S_irq_modifiers = 128, // irq_modifiers + S_symbol_def = 129 // symbol_def }; }; @@ -696,6 +769,8 @@ namespace yy { { switch (this->kind ()) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -706,6 +781,10 @@ namespace yy { value.move< enum condition > (std::move (that.value)); break; + case symbol_kind::S_fifo_config: // fifo_config + value.move< enum fifo_config > (std::move (that.value)); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -716,13 +795,17 @@ namespace yy { value.move< enum irq > (std::move (that.value)); break; + case symbol_kind::S_mov_op: // mov_op + value.move< enum mov_op > (std::move (that.value)); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.move< enum mov > (std::move (that.value)); + value.move< extended_mov > (std::move (that.value)); break; - case symbol_kind::S_mov_op: // mov_op - value.move< enum mov_op > (std::move (that.value)); + case symbol_kind::S_FLOAT: // "float" + value.move< float > (std::move (that.value)); break; case symbol_kind::S_INT: // "integer" @@ -738,6 +821,7 @@ namespace yy { case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.move< std::shared_ptr > (std::move (that.value)); break; @@ -759,6 +843,10 @@ namespace yy { value.move< std::string > (std::move (that.value)); break; + case symbol_kind::S_pio_version: // pio_version + value.move< uint > (std::move (that.value)); + break; + default: break; } @@ -807,6 +895,19 @@ namespace yy { , location (l) {} #endif +#if 201103L <= YY_CPLUSPLUS + basic_symbol (typename Base::kind_type t, enum fifo_config&& v, location_type&& l) + : Base (t) + , value (std::move (v)) + , location (std::move (l)) + {} +#else + basic_symbol (typename Base::kind_type t, const enum fifo_config& v, const location_type& l) + : Base (t) + , value (v) + , location (l) + {} +#endif #if 201103L <= YY_CPLUSPLUS basic_symbol (typename Base::kind_type t, enum in_out_set&& v, location_type&& l) : Base (t) @@ -834,26 +935,39 @@ namespace yy { {} #endif #if 201103L <= YY_CPLUSPLUS - basic_symbol (typename Base::kind_type t, enum mov&& v, location_type&& l) + basic_symbol (typename Base::kind_type t, enum mov_op&& v, location_type&& l) : Base (t) , value (std::move (v)) , location (std::move (l)) {} #else - basic_symbol (typename Base::kind_type t, const enum mov& v, const location_type& l) + basic_symbol (typename Base::kind_type t, const enum mov_op& v, const location_type& l) : Base (t) , value (v) , location (l) {} #endif #if 201103L <= YY_CPLUSPLUS - basic_symbol (typename Base::kind_type t, enum mov_op&& v, location_type&& l) + basic_symbol (typename Base::kind_type t, extended_mov&& v, location_type&& l) : Base (t) , value (std::move (v)) , location (std::move (l)) {} #else - basic_symbol (typename Base::kind_type t, const enum mov_op& v, const location_type& l) + basic_symbol (typename Base::kind_type t, const extended_mov& v, const location_type& l) + : Base (t) + , value (v) + , location (l) + {} +#endif +#if 201103L <= YY_CPLUSPLUS + basic_symbol (typename Base::kind_type t, float&& v, location_type&& l) + : Base (t) + , value (std::move (v)) + , location (std::move (l)) + {} +#else + basic_symbol (typename Base::kind_type t, const float& v, const location_type& l) : Base (t) , value (v) , location (l) @@ -937,6 +1051,19 @@ namespace yy { , location (l) {} #endif +#if 201103L <= YY_CPLUSPLUS + basic_symbol (typename Base::kind_type t, uint&& v, location_type&& l) + : Base (t) + , value (std::move (v)) + , location (std::move (l)) + {} +#else + basic_symbol (typename Base::kind_type t, const uint& v, const location_type& l) + : Base (t) + , value (v) + , location (l) + {} +#endif /// Destroy the symbol. ~basic_symbol () @@ -960,6 +1087,8 @@ namespace yy { // Value type destructor. switch (yykind) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -970,6 +1099,10 @@ switch (yykind) value.template destroy< enum condition > (); break; + case symbol_kind::S_fifo_config: // fifo_config + value.template destroy< enum fifo_config > (); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -980,13 +1113,17 @@ switch (yykind) value.template destroy< enum irq > (); break; + case symbol_kind::S_mov_op: // mov_op + value.template destroy< enum mov_op > (); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.template destroy< enum mov > (); + value.template destroy< extended_mov > (); break; - case symbol_kind::S_mov_op: // mov_op - value.template destroy< enum mov_op > (); + case symbol_kind::S_FLOAT: // "float" + value.template destroy< float > (); break; case symbol_kind::S_INT: // "integer" @@ -1002,6 +1139,7 @@ switch (yykind) case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.template destroy< std::shared_ptr > (); break; @@ -1023,6 +1161,10 @@ switch (yykind) value.template destroy< std::string > (); break; + case symbol_kind::S_pio_version: // pio_version + value.template destroy< uint > (); + break; + default: break; } @@ -1113,13 +1255,26 @@ switch (yykind) symbol_type (int tok, location_type l) : super_type(token_type (tok), std::move (l)) { - YY_ASSERT (tok == token::TOK_END || tok == token::TOK_YYerror || tok == token::TOK_YYUNDEF || tok == token::TOK_NEWLINE || tok == token::TOK_COMMA || tok == token::TOK_COLON || tok == token::TOK_LPAREN || tok == token::TOK_RPAREN || tok == token::TOK_LBRACKET || tok == token::TOK_RBRACKET || tok == token::TOK_PLUS || tok == token::TOK_MINUS || tok == token::TOK_MULTIPLY || tok == token::TOK_DIVIDE || tok == token::TOK_OR || tok == token::TOK_AND || tok == token::TOK_XOR || tok == token::TOK_POST_DECREMENT || tok == token::TOK_NOT_EQUAL || tok == token::TOK_NOT || tok == token::TOK_REVERSE || tok == token::TOK_EQUAL || tok == token::TOK_PROGRAM || tok == token::TOK_WRAP_TARGET || tok == token::TOK_WRAP || tok == token::TOK_DEFINE || tok == token::TOK_SIDE_SET || tok == token::TOK_WORD || tok == token::TOK_ORIGIN || tok == token::TOK_LANG_OPT || tok == token::TOK_JMP || tok == token::TOK_WAIT || tok == token::TOK_IN || tok == token::TOK_OUT || tok == token::TOK_PUSH || tok == token::TOK_PULL || tok == token::TOK_MOV || tok == token::TOK_IRQ || tok == token::TOK_SET || tok == token::TOK_NOP || tok == token::TOK_PIN || tok == token::TOK_GPIO || tok == token::TOK_OSRE || tok == token::TOK_PINS || tok == token::TOK_NULL || tok == token::TOK_PINDIRS || tok == token::TOK_BLOCK || tok == token::TOK_NOBLOCK || tok == token::TOK_IFEMPTY || tok == token::TOK_IFFULL || tok == token::TOK_NOWAIT || tok == token::TOK_CLEAR || tok == token::TOK_REL || tok == token::TOK_X || tok == token::TOK_Y || tok == token::TOK_EXEC || tok == token::TOK_PC || tok == token::TOK_ISR || tok == token::TOK_OSR || tok == token::TOK_OPTIONAL || tok == token::TOK_SIDE || tok == token::TOK_STATUS || tok == token::TOK_PUBLIC); + YY_ASSERT (tok == token::TOK_END || tok == token::TOK_YYerror || tok == token::TOK_YYUNDEF || tok == token::TOK_NEWLINE || tok == token::TOK_COMMA || tok == token::TOK_COLON || tok == token::TOK_LPAREN || tok == token::TOK_RPAREN || tok == token::TOK_LBRACKET || tok == token::TOK_RBRACKET || tok == token::TOK_PLUS || tok == token::TOK_MINUS || tok == token::TOK_MULTIPLY || tok == token::TOK_DIVIDE || tok == token::TOK_OR || tok == token::TOK_AND || tok == token::TOK_XOR || tok == token::TOK_SHL || tok == token::TOK_SHR || tok == token::TOK_POST_DECREMENT || tok == token::TOK_NOT_EQUAL || tok == token::TOK_NOT || tok == token::TOK_REVERSE || tok == token::TOK_ASSIGN || tok == token::TOK_LESSTHAN || tok == token::TOK_PROGRAM || tok == token::TOK_WRAP_TARGET || tok == token::TOK_WRAP || tok == token::TOK_DEFINE || tok == token::TOK_SIDE_SET || tok == token::TOK_WORD || tok == token::TOK_ORIGIN || tok == token::TOK_LANG_OPT || tok == token::TOK_PIO_VERSION || tok == token::TOK_CLOCK_DIV || tok == token::TOK_FIFO || tok == token::TOK_MOV_STATUS || tok == token::TOK_DOT_SET || tok == token::TOK_DOT_OUT || tok == token::TOK_DOT_IN || tok == token::TOK_JMP || tok == token::TOK_WAIT || tok == token::TOK_IN || tok == token::TOK_OUT || tok == token::TOK_PUSH || tok == token::TOK_PULL || tok == token::TOK_MOV || tok == token::TOK_IRQ || tok == token::TOK_SET || tok == token::TOK_NOP || tok == token::TOK_PIN || tok == token::TOK_GPIO || tok == token::TOK_OSRE || tok == token::TOK_JMPPIN || tok == token::TOK_PREV || tok == token::TOK_NEXT || tok == token::TOK_PINS || tok == token::TOK_NULL || tok == token::TOK_PINDIRS || tok == token::TOK_BLOCK || tok == token::TOK_NOBLOCK || tok == token::TOK_IFEMPTY || tok == token::TOK_IFFULL || tok == token::TOK_NOWAIT || tok == token::TOK_CLEAR || tok == token::TOK_REL || tok == token::TOK_X || tok == token::TOK_Y || tok == token::TOK_EXEC || tok == token::TOK_PC || tok == token::TOK_ISR || tok == token::TOK_OSR || tok == token::TOK_OPTIONAL || tok == token::TOK_SIDE || tok == token::TOK_STATUS || tok == token::TOK_PUBLIC || tok == token::TOK_RP2040 || tok == token::TOK_RP2350 || tok == token::TOK_RXFIFO || tok == token::TOK_TXFIFO || tok == token::TOK_TXRX || tok == token::TOK_TX || tok == token::TOK_RX || tok == token::TOK_TXPUT || tok == token::TOK_TXGET || tok == token::TOK_PUTGET || tok == token::TOK_LEFT || tok == token::TOK_RIGHT || tok == token::TOK_AUTO || tok == token::TOK_MANUAL); } #else symbol_type (int tok, const location_type& l) : super_type(token_type (tok), l) { - YY_ASSERT (tok == token::TOK_END || tok == token::TOK_YYerror || tok == token::TOK_YYUNDEF || tok == token::TOK_NEWLINE || tok == token::TOK_COMMA || tok == token::TOK_COLON || tok == token::TOK_LPAREN || tok == token::TOK_RPAREN || tok == token::TOK_LBRACKET || tok == token::TOK_RBRACKET || tok == token::TOK_PLUS || tok == token::TOK_MINUS || tok == token::TOK_MULTIPLY || tok == token::TOK_DIVIDE || tok == token::TOK_OR || tok == token::TOK_AND || tok == token::TOK_XOR || tok == token::TOK_POST_DECREMENT || tok == token::TOK_NOT_EQUAL || tok == token::TOK_NOT || tok == token::TOK_REVERSE || tok == token::TOK_EQUAL || tok == token::TOK_PROGRAM || tok == token::TOK_WRAP_TARGET || tok == token::TOK_WRAP || tok == token::TOK_DEFINE || tok == token::TOK_SIDE_SET || tok == token::TOK_WORD || tok == token::TOK_ORIGIN || tok == token::TOK_LANG_OPT || tok == token::TOK_JMP || tok == token::TOK_WAIT || tok == token::TOK_IN || tok == token::TOK_OUT || tok == token::TOK_PUSH || tok == token::TOK_PULL || tok == token::TOK_MOV || tok == token::TOK_IRQ || tok == token::TOK_SET || tok == token::TOK_NOP || tok == token::TOK_PIN || tok == token::TOK_GPIO || tok == token::TOK_OSRE || tok == token::TOK_PINS || tok == token::TOK_NULL || tok == token::TOK_PINDIRS || tok == token::TOK_BLOCK || tok == token::TOK_NOBLOCK || tok == token::TOK_IFEMPTY || tok == token::TOK_IFFULL || tok == token::TOK_NOWAIT || tok == token::TOK_CLEAR || tok == token::TOK_REL || tok == token::TOK_X || tok == token::TOK_Y || tok == token::TOK_EXEC || tok == token::TOK_PC || tok == token::TOK_ISR || tok == token::TOK_OSR || tok == token::TOK_OPTIONAL || tok == token::TOK_SIDE || tok == token::TOK_STATUS || tok == token::TOK_PUBLIC); + YY_ASSERT (tok == token::TOK_END || tok == token::TOK_YYerror || tok == token::TOK_YYUNDEF || tok == token::TOK_NEWLINE || tok == token::TOK_COMMA || tok == token::TOK_COLON || tok == token::TOK_LPAREN || tok == token::TOK_RPAREN || tok == token::TOK_LBRACKET || tok == token::TOK_RBRACKET || tok == token::TOK_PLUS || tok == token::TOK_MINUS || tok == token::TOK_MULTIPLY || tok == token::TOK_DIVIDE || tok == token::TOK_OR || tok == token::TOK_AND || tok == token::TOK_XOR || tok == token::TOK_SHL || tok == token::TOK_SHR || tok == token::TOK_POST_DECREMENT || tok == token::TOK_NOT_EQUAL || tok == token::TOK_NOT || tok == token::TOK_REVERSE || tok == token::TOK_ASSIGN || tok == token::TOK_LESSTHAN || tok == token::TOK_PROGRAM || tok == token::TOK_WRAP_TARGET || tok == token::TOK_WRAP || tok == token::TOK_DEFINE || tok == token::TOK_SIDE_SET || tok == token::TOK_WORD || tok == token::TOK_ORIGIN || tok == token::TOK_LANG_OPT || tok == token::TOK_PIO_VERSION || tok == token::TOK_CLOCK_DIV || tok == token::TOK_FIFO || tok == token::TOK_MOV_STATUS || tok == token::TOK_DOT_SET || tok == token::TOK_DOT_OUT || tok == token::TOK_DOT_IN || tok == token::TOK_JMP || tok == token::TOK_WAIT || tok == token::TOK_IN || tok == token::TOK_OUT || tok == token::TOK_PUSH || tok == token::TOK_PULL || tok == token::TOK_MOV || tok == token::TOK_IRQ || tok == token::TOK_SET || tok == token::TOK_NOP || tok == token::TOK_PIN || tok == token::TOK_GPIO || tok == token::TOK_OSRE || tok == token::TOK_JMPPIN || tok == token::TOK_PREV || tok == token::TOK_NEXT || tok == token::TOK_PINS || tok == token::TOK_NULL || tok == token::TOK_PINDIRS || tok == token::TOK_BLOCK || tok == token::TOK_NOBLOCK || tok == token::TOK_IFEMPTY || tok == token::TOK_IFFULL || tok == token::TOK_NOWAIT || tok == token::TOK_CLEAR || tok == token::TOK_REL || tok == token::TOK_X || tok == token::TOK_Y || tok == token::TOK_EXEC || tok == token::TOK_PC || tok == token::TOK_ISR || tok == token::TOK_OSR || tok == token::TOK_OPTIONAL || tok == token::TOK_SIDE || tok == token::TOK_STATUS || tok == token::TOK_PUBLIC || tok == token::TOK_RP2040 || tok == token::TOK_RP2350 || tok == token::TOK_RXFIFO || tok == token::TOK_TXFIFO || tok == token::TOK_TXRX || tok == token::TOK_TX || tok == token::TOK_RX || tok == token::TOK_TXPUT || tok == token::TOK_TXGET || tok == token::TOK_PUTGET || tok == token::TOK_LEFT || tok == token::TOK_RIGHT || tok == token::TOK_AUTO || tok == token::TOK_MANUAL); + } +#endif +#if 201103L <= YY_CPLUSPLUS + symbol_type (int tok, float v, location_type l) + : super_type(token_type (tok), std::move (v), std::move (l)) + { + YY_ASSERT (tok == token::TOK_FLOAT); + } +#else + symbol_type (int tok, const float& v, const location_type& l) + : super_type(token_type (tok), v, l) + { + YY_ASSERT (tok == token::TOK_FLOAT); } #endif #if 201103L <= YY_CPLUSPLUS @@ -1451,6 +1606,36 @@ switch (yykind) return symbol_type (token::TOK_XOR, l); } #endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_SHL (location_type l) + { + return symbol_type (token::TOK_SHL, std::move (l)); + } +#else + static + symbol_type + make_SHL (const location_type& l) + { + return symbol_type (token::TOK_SHL, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_SHR (location_type l) + { + return symbol_type (token::TOK_SHR, std::move (l)); + } +#else + static + symbol_type + make_SHR (const location_type& l) + { + return symbol_type (token::TOK_SHR, l); + } +#endif #if 201103L <= YY_CPLUSPLUS static symbol_type @@ -1514,16 +1699,31 @@ switch (yykind) #if 201103L <= YY_CPLUSPLUS static symbol_type - make_EQUAL (location_type l) + make_ASSIGN (location_type l) { - return symbol_type (token::TOK_EQUAL, std::move (l)); + return symbol_type (token::TOK_ASSIGN, std::move (l)); } #else static symbol_type - make_EQUAL (const location_type& l) + make_ASSIGN (const location_type& l) { - return symbol_type (token::TOK_EQUAL, l); + return symbol_type (token::TOK_ASSIGN, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_LESSTHAN (location_type l) + { + return symbol_type (token::TOK_LESSTHAN, std::move (l)); + } +#else + static + symbol_type + make_LESSTHAN (const location_type& l) + { + return symbol_type (token::TOK_LESSTHAN, l); } #endif #if 201103L <= YY_CPLUSPLUS @@ -1646,6 +1846,111 @@ switch (yykind) return symbol_type (token::TOK_LANG_OPT, l); } #endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_PIO_VERSION (location_type l) + { + return symbol_type (token::TOK_PIO_VERSION, std::move (l)); + } +#else + static + symbol_type + make_PIO_VERSION (const location_type& l) + { + return symbol_type (token::TOK_PIO_VERSION, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_CLOCK_DIV (location_type l) + { + return symbol_type (token::TOK_CLOCK_DIV, std::move (l)); + } +#else + static + symbol_type + make_CLOCK_DIV (const location_type& l) + { + return symbol_type (token::TOK_CLOCK_DIV, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_FIFO (location_type l) + { + return symbol_type (token::TOK_FIFO, std::move (l)); + } +#else + static + symbol_type + make_FIFO (const location_type& l) + { + return symbol_type (token::TOK_FIFO, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_MOV_STATUS (location_type l) + { + return symbol_type (token::TOK_MOV_STATUS, std::move (l)); + } +#else + static + symbol_type + make_MOV_STATUS (const location_type& l) + { + return symbol_type (token::TOK_MOV_STATUS, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_DOT_SET (location_type l) + { + return symbol_type (token::TOK_DOT_SET, std::move (l)); + } +#else + static + symbol_type + make_DOT_SET (const location_type& l) + { + return symbol_type (token::TOK_DOT_SET, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_DOT_OUT (location_type l) + { + return symbol_type (token::TOK_DOT_OUT, std::move (l)); + } +#else + static + symbol_type + make_DOT_OUT (const location_type& l) + { + return symbol_type (token::TOK_DOT_OUT, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_DOT_IN (location_type l) + { + return symbol_type (token::TOK_DOT_IN, std::move (l)); + } +#else + static + symbol_type + make_DOT_IN (const location_type& l) + { + return symbol_type (token::TOK_DOT_IN, l); + } +#endif #if 201103L <= YY_CPLUSPLUS static symbol_type @@ -1841,6 +2146,51 @@ switch (yykind) return symbol_type (token::TOK_OSRE, l); } #endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_JMPPIN (location_type l) + { + return symbol_type (token::TOK_JMPPIN, std::move (l)); + } +#else + static + symbol_type + make_JMPPIN (const location_type& l) + { + return symbol_type (token::TOK_JMPPIN, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_PREV (location_type l) + { + return symbol_type (token::TOK_PREV, std::move (l)); + } +#else + static + symbol_type + make_PREV (const location_type& l) + { + return symbol_type (token::TOK_PREV, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_NEXT (location_type l) + { + return symbol_type (token::TOK_NEXT, std::move (l)); + } +#else + static + symbol_type + make_NEXT (const location_type& l) + { + return symbol_type (token::TOK_NEXT, l); + } +#endif #if 201103L <= YY_CPLUSPLUS static symbol_type @@ -2141,6 +2491,216 @@ switch (yykind) return symbol_type (token::TOK_PUBLIC, l); } #endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_RP2040 (location_type l) + { + return symbol_type (token::TOK_RP2040, std::move (l)); + } +#else + static + symbol_type + make_RP2040 (const location_type& l) + { + return symbol_type (token::TOK_RP2040, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_RP2350 (location_type l) + { + return symbol_type (token::TOK_RP2350, std::move (l)); + } +#else + static + symbol_type + make_RP2350 (const location_type& l) + { + return symbol_type (token::TOK_RP2350, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_RXFIFO (location_type l) + { + return symbol_type (token::TOK_RXFIFO, std::move (l)); + } +#else + static + symbol_type + make_RXFIFO (const location_type& l) + { + return symbol_type (token::TOK_RXFIFO, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_TXFIFO (location_type l) + { + return symbol_type (token::TOK_TXFIFO, std::move (l)); + } +#else + static + symbol_type + make_TXFIFO (const location_type& l) + { + return symbol_type (token::TOK_TXFIFO, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_TXRX (location_type l) + { + return symbol_type (token::TOK_TXRX, std::move (l)); + } +#else + static + symbol_type + make_TXRX (const location_type& l) + { + return symbol_type (token::TOK_TXRX, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_TX (location_type l) + { + return symbol_type (token::TOK_TX, std::move (l)); + } +#else + static + symbol_type + make_TX (const location_type& l) + { + return symbol_type (token::TOK_TX, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_RX (location_type l) + { + return symbol_type (token::TOK_RX, std::move (l)); + } +#else + static + symbol_type + make_RX (const location_type& l) + { + return symbol_type (token::TOK_RX, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_TXPUT (location_type l) + { + return symbol_type (token::TOK_TXPUT, std::move (l)); + } +#else + static + symbol_type + make_TXPUT (const location_type& l) + { + return symbol_type (token::TOK_TXPUT, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_TXGET (location_type l) + { + return symbol_type (token::TOK_TXGET, std::move (l)); + } +#else + static + symbol_type + make_TXGET (const location_type& l) + { + return symbol_type (token::TOK_TXGET, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_PUTGET (location_type l) + { + return symbol_type (token::TOK_PUTGET, std::move (l)); + } +#else + static + symbol_type + make_PUTGET (const location_type& l) + { + return symbol_type (token::TOK_PUTGET, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_LEFT (location_type l) + { + return symbol_type (token::TOK_LEFT, std::move (l)); + } +#else + static + symbol_type + make_LEFT (const location_type& l) + { + return symbol_type (token::TOK_LEFT, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_RIGHT (location_type l) + { + return symbol_type (token::TOK_RIGHT, std::move (l)); + } +#else + static + symbol_type + make_RIGHT (const location_type& l) + { + return symbol_type (token::TOK_RIGHT, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_AUTO (location_type l) + { + return symbol_type (token::TOK_AUTO, std::move (l)); + } +#else + static + symbol_type + make_AUTO (const location_type& l) + { + return symbol_type (token::TOK_AUTO, l); + } +#endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_MANUAL (location_type l) + { + return symbol_type (token::TOK_MANUAL, std::move (l)); + } +#else + static + symbol_type + make_MANUAL (const location_type& l) + { + return symbol_type (token::TOK_MANUAL, l); + } +#endif #if 201103L <= YY_CPLUSPLUS static symbol_type @@ -2246,6 +2806,21 @@ switch (yykind) return symbol_type (token::TOK_INT, v, l); } #endif +#if 201103L <= YY_CPLUSPLUS + static + symbol_type + make_FLOAT (float v, location_type l) + { + return symbol_type (token::TOK_FLOAT, std::move (v), std::move (l)); + } +#else + static + symbol_type + make_FLOAT (const float& v, const location_type& l) + { + return symbol_type (token::TOK_FLOAT, v, l); + } +#endif class context @@ -2286,7 +2861,7 @@ switch (yykind) void yy_lac_discard_ (const char* event); /// Stored state numbers (used for stacks). - typedef unsigned char state_type; + typedef short state_type; /// The arguments of the error message. int yy_syntax_error_arguments_ (const context& yyctx, @@ -2331,7 +2906,7 @@ switch (yykind) // YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. // Performed when YYTABLE does not specify something else to do. Zero // means the default is an error. - static const signed char yydefact_[]; + static const unsigned char yydefact_[]; // YYPGOTO[NTERM-NUM]. static const short yypgoto_[]; @@ -2344,14 +2919,14 @@ switch (yykind) // number is the opposite. If YYTABLE_NINF, syntax error. static const short yytable_[]; - static const unsigned char yycheck_[]; + static const short yycheck_[]; // YYSTOS[STATE-NUM] -- The (internal number of the) accessing // symbol of state STATE-NUM. - static const signed char yystos_[]; + static const unsigned char yystos_[]; // YYR1[YYN] -- Symbol number of symbol that rule YYN derives. - static const signed char yyr1_[]; + static const unsigned char yyr1_[]; // YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. static const signed char yyr2_[]; @@ -2595,9 +3170,9 @@ switch (yykind) /// Constants. enum { - yylast_ = 205, ///< Last index in yytable_. - yynnts_ = 27, ///< Number of nonterminal symbols. - yyfinal_ = 96 ///< Termination state number. + yylast_ = 307, ///< Last index in yytable_. + yynnts_ = 32, ///< Number of nonterminal symbols. + yyfinal_ = 127 ///< Termination state number. }; @@ -2648,10 +3223,13 @@ switch (yykind) 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, - 65, 66, 67, 68, 69 + 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, + 95, 96, 97 }; // Last valid token kind. - const int code_max = 324; + const int code_max = 352; if (t <= 0) return symbol_kind::S_YYEOF; @@ -2670,6 +3248,8 @@ switch (yykind) { switch (this->kind ()) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -2680,6 +3260,10 @@ switch (yykind) value.copy< enum condition > (YY_MOVE (that.value)); break; + case symbol_kind::S_fifo_config: // fifo_config + value.copy< enum fifo_config > (YY_MOVE (that.value)); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -2690,13 +3274,17 @@ switch (yykind) value.copy< enum irq > (YY_MOVE (that.value)); break; + case symbol_kind::S_mov_op: // mov_op + value.copy< enum mov_op > (YY_MOVE (that.value)); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.copy< enum mov > (YY_MOVE (that.value)); + value.copy< extended_mov > (YY_MOVE (that.value)); break; - case symbol_kind::S_mov_op: // mov_op - value.copy< enum mov_op > (YY_MOVE (that.value)); + case symbol_kind::S_FLOAT: // "float" + value.copy< float > (YY_MOVE (that.value)); break; case symbol_kind::S_INT: // "integer" @@ -2712,6 +3300,7 @@ switch (yykind) case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.copy< std::shared_ptr > (YY_MOVE (that.value)); break; @@ -2733,6 +3322,10 @@ switch (yykind) value.copy< std::string > (YY_MOVE (that.value)); break; + case symbol_kind::S_pio_version: // pio_version + value.copy< uint > (YY_MOVE (that.value)); + break; + default: break; } @@ -2762,6 +3355,8 @@ switch (yykind) super_type::move (s); switch (this->kind ()) { + case symbol_kind::S_direction: // direction + case symbol_kind::S_autop: // autop case symbol_kind::S_if_full: // if_full case symbol_kind::S_if_empty: // if_empty case symbol_kind::S_blocking: // blocking @@ -2772,6 +3367,10 @@ switch (yykind) value.move< enum condition > (YY_MOVE (s.value)); break; + case symbol_kind::S_fifo_config: // fifo_config + value.move< enum fifo_config > (YY_MOVE (s.value)); + break; + case symbol_kind::S_in_source: // in_source case symbol_kind::S_out_target: // out_target case symbol_kind::S_set_target: // set_target @@ -2782,13 +3381,17 @@ switch (yykind) value.move< enum irq > (YY_MOVE (s.value)); break; + case symbol_kind::S_mov_op: // mov_op + value.move< enum mov_op > (YY_MOVE (s.value)); + break; + case symbol_kind::S_mov_target: // mov_target case symbol_kind::S_mov_source: // mov_source - value.move< enum mov > (YY_MOVE (s.value)); + value.move< extended_mov > (YY_MOVE (s.value)); break; - case symbol_kind::S_mov_op: // mov_op - value.move< enum mov_op > (YY_MOVE (s.value)); + case symbol_kind::S_FLOAT: // "float" + value.move< float > (YY_MOVE (s.value)); break; case symbol_kind::S_INT: // "integer" @@ -2804,6 +3407,7 @@ switch (yykind) case symbol_kind::S_expression: // expression case symbol_kind::S_delay: // delay case symbol_kind::S_sideset: // sideset + case symbol_kind::S_threshold: // threshold value.move< std::shared_ptr > (YY_MOVE (s.value)); break; @@ -2825,6 +3429,10 @@ switch (yykind) value.move< std::string > (YY_MOVE (s.value)); break; + case symbol_kind::S_pio_version: // pio_version + value.move< uint > (YY_MOVE (s.value)); + break; + default: break; } @@ -2891,4 +3499,4 @@ switch (yykind) -#endif // !YY_YY_HOME_GRAHAM_DEV_MU_PICO_SDK_TOOLS_PIOASM_GEN_PARSER_HPP_INCLUDED +#endif // !YY_YY_HOME_GRAHAM_DEV_AMY_AMY_SDK_TOOLS_PIOASM_GEN_PARSER_HPP_INCLUDED diff --git a/tools/pioasm/lexer.ll b/tools/pioasm/lexer.ll index 5604b7019..fdf8c7220 100644 --- a/tools/pioasm/lexer.ll +++ b/tools/pioasm/lexer.ll @@ -23,6 +23,7 @@ %{ yy::parser::symbol_type make_INT(const std::string &s, const yy::parser::location_type& loc); + yy::parser::symbol_type make_FLOAT(const std::string &s, const yy::parser::location_type& loc); yy::parser::symbol_type make_HEX(const std::string &s, const yy::parser::location_type& loc); yy::parser::symbol_type make_BINARY(const std::string &s, const yy::parser::location_type& loc); %} @@ -37,6 +38,7 @@ id [a-zA-Z_][a-zA-Z0-9_]* binary "0b"[01]+ int {digit}+ +float {digit}*\.{digit}+ hex "0x"[0-9a-fA-F]+ directive \.{id} @@ -92,7 +94,7 @@ output_fmt [^%\n]+ { \"[^\n]*\" return yy::parser::make_STRING(yytext, loc); {blank}+ loc.step(); -"=" return yy::parser::make_EQUAL(loc); +"=" return yy::parser::make_ASSIGN(loc); {int} return make_INT(yytext, loc); {hex} return make_HEX(yytext, loc); {binary} return make_BINARY(yytext, loc); @@ -117,10 +119,13 @@ output_fmt [^%\n]+ "/" return yy::parser::make_DIVIDE(loc); "|" return yy::parser::make_OR(loc); "&" return yy::parser::make_AND(loc); +">>" return yy::parser::make_SHR(loc); +"<<" return yy::parser::make_SHL(loc); "^" return yy::parser::make_XOR(loc); "!=" return yy::parser::make_NOT_EQUAL(loc); "!" return yy::parser::make_NOT(loc); "~" return yy::parser::make_NOT(loc); +"<" return yy::parser::make_LESSTHAN(loc); ".program" return yy::parser::make_PROGRAM(loc); ".wrap_target" return yy::parser::make_WRAP_TARGET(loc); @@ -130,6 +135,14 @@ output_fmt [^%\n]+ ".side_set" return yy::parser::make_SIDE_SET(loc); ".origin" return yy::parser::make_ORIGIN(loc); ".lang_opt" { BEGIN(lang_opt); return yy::parser::make_LANG_OPT(loc); } +".pio_version" return yy::parser::make_PIO_VERSION(loc); +".clock_div" return yy::parser::make_CLOCK_DIV(loc); +".fifo" return yy::parser::make_FIFO(loc); +".mov_status" return yy::parser::make_MOV_STATUS(loc); +".set" return yy::parser::make_DOT_SET(loc); +".out" return yy::parser::make_DOT_OUT(loc); +".in" return yy::parser::make_DOT_IN(loc); + {directive} return yy::parser::make_UNKNOWN_DIRECTIVE(yytext, loc); "JMP" return yy::parser::make_JMP(loc); @@ -173,13 +186,33 @@ output_fmt [^%\n]+ "CLEAR" return yy::parser::make_CLEAR(loc); "NOWAIT" return yy::parser::make_NOWAIT(loc); +"JMPPIN" return yy::parser::make_JMPPIN(loc); +"NEXT" return yy::parser::make_NEXT(loc); +"PREV" return yy::parser::make_PREV(loc); + +"TXRX" return yy::parser::make_TXRX(loc); +"TX" return yy::parser::make_TX(loc); +"RX" return yy::parser::make_RX(loc); +"TXPUT" return yy::parser::make_TXPUT(loc); +"TXGET" return yy::parser::make_TXGET(loc); +"PUTGET" return yy::parser::make_PUTGET(loc); "ONE" return yy::parser::make_INT(1, loc); "ZERO" return yy::parser::make_INT(0, loc); +"RP2040" return yy::parser::make_RP2040(loc); +"RP2350" return yy::parser::make_RP2350(loc); +"RXFIFO" return yy::parser::make_RXFIFO(loc); +"TXFIFO" return yy::parser::make_TXFIFO(loc); + +"LEFT" return yy::parser::make_LEFT(loc); +"RIGHT" return yy::parser::make_RIGHT(loc); +"AUTO" return yy::parser::make_AUTO(loc); +"MANUAL" return yy::parser::make_MANUAL(loc); <> return yy::parser::make_END(loc); {int} return make_INT(yytext, loc); +{float} return make_FLOAT(yytext, loc); {hex} return make_HEX(yytext, loc); {binary} return make_BINARY(yytext, loc); @@ -200,6 +233,13 @@ yy::parser::symbol_type make_INT(const std::string &s, const yy::parser::locatio return yy::parser::make_INT((int) n, loc); } +yy::parser::symbol_type make_FLOAT(const std::string &s, const yy::parser::location_type& loc) +{ + errno = 0; + float n = strtof (s.c_str(), NULL); + return yy::parser::make_FLOAT(n, loc); +} + yy::parser::symbol_type make_HEX(const std::string &s, const yy::parser::location_type& loc) { errno = 0; diff --git a/tools/pioasm/main.cpp b/tools/pioasm/main.cpp index e7ff6866b..f5d678535 100644 --- a/tools/pioasm/main.cpp +++ b/tools/pioasm/main.cpp @@ -23,6 +23,7 @@ void usage() { std::cerr << " " << f->get_description() << std::endl; } std::cerr << " -p add a parameter to be passed to the output format generator" << std::endl; + std::cerr << " -v specify the default PIO version (0 or 1)" << std::endl; std::cerr << " -?, --help print this help and exit\n"; } @@ -50,6 +51,18 @@ int main(int argc, char *argv[]) { std::cerr << "error: -p requires parameter value" << std::endl; res = 1; } + } else if (argv[i] == std::string("-v")) { + if (++i < argc) { + if (argv[i] == std::string("0")) pioasm.default_pio_version = 0; + else if (argv[i] == std::string("1")) pioasm.default_pio_version = 1; + else { + std::cerr << "error: unsupported PIO version '" << argv[i] << "'" << std::endl; + res = 1; + } + } else { + std::cerr << "error: -v requires version number" << std::endl; + res = 1; + } } else if (argv[i] == std::string("-?") || argv[i] == std::string("--help")) { usage(); return 1; diff --git a/tools/pioasm/output_format.h b/tools/pioasm/output_format.h index 2ba899db1..405a5ae75 100644 --- a/tools/pioasm/output_format.h +++ b/tools/pioasm/output_format.h @@ -12,6 +12,8 @@ #include #include +#include "pio_enums.h" + typedef unsigned int uint; // can't use optional because we want to support older compilers @@ -55,6 +57,13 @@ struct compiled_source { symbol(std::string name, int value, bool is_label) : name(std::move(name)), value(value), is_label(is_label) {} }; + struct in_out { + int pin_count; + bool right; + bool autop; + int threshold; + }; + struct program { std::string name; optional_int origin = optional_int::with_default(-1); @@ -63,6 +72,16 @@ struct compiled_source { bool sideset_pindirs = false; int wrap; int wrap_target; + int pio_version; + int mov_status_type; + int mov_status_n; + in_out in; + in_out out; + int set_count; + uint clock_div_int; + uint clock_div_frac; + uint8_t used_gpio_ranges; + fifo_config fifo; std::vector instructions; std::vector symbols; // public only std::map> code_blocks; diff --git a/tools/pioasm/parser.yy b/tools/pioasm/parser.yy index 467ca890f..df05f5f7d 100644 --- a/tools/pioasm/parser.yy +++ b/tools/pioasm/parser.yy @@ -60,11 +60,15 @@ OR "|" AND "&" XOR "^" + SHL "<<" + SHR ">>" POST_DECREMENT "--" NOT_EQUAL "!=" NOT "!" REVERSE "::" - EQUAL "=" + + ASSIGN "=" + LESSTHAN "<" PROGRAM ".program" WRAP_TARGET ".wrap_target" @@ -74,6 +78,13 @@ WORD ".word" ORIGIN ".origin" LANG_OPT ".lang_opt" + PIO_VERSION ".pio_version" + CLOCK_DIV ".clock_div" + FIFO ".fifo" + MOV_STATUS ".mov_status" + DOT_SET ".set" + DOT_OUT ".out" + DOT_IN ".in" JMP "jmp" WAIT "wait" @@ -89,6 +100,9 @@ PIN "pin" GPIO "gpio" OSRE "osre" + JMPPIN "jmppin" + PREV "prev" + NEXT "next" PINS "pins" NULL "null" @@ -110,6 +124,23 @@ SIDE "side" STATUS "status" PUBLIC "public" + + RP2040 "rp2040" + RP2350 "rp2350" + RXFIFO "rxfifo" + TXFIFO "txfifo" + + TXRX "txrx" + TX "tx" + RX "rx" + TXPUT "txput" + TXGET "txget" + PUTGET "putget" + + LEFT "left" + RIGHT "right" + AUTO "auto" + MANUAL "manual" ; %token @@ -120,10 +151,12 @@ CODE_BLOCK_CONTENTS "%}" // bit ugly but if there is no end this is what we will be missing UNKNOWN_DIRECTIVE INT "integer" + FLOAT "float" ; %left REVERSE +%left SHL SHR %left PLUS MINUS %left MULTIPLY DIVIDE %left AND OR XOR @@ -161,17 +194,30 @@ label_decl: directive: DEFINE symbol_def expression { $2->is_label = false; $2->value = $3; pioasm.get_current_program(@1, ".define", false, false).add_symbol($2); } | ORIGIN value { pioasm.get_current_program(@1, ".origin", true).set_origin(@$, $2); } + | PIO_VERSION pio_version { pioasm.get_current_program(@1, ".pio_version", true, false).set_pio_version(@$, $2); } | SIDE_SET value OPTIONAL PINDIRS { pioasm.get_current_program(@1, ".side_set", true).set_sideset(@$, $2, true, true); } | SIDE_SET value OPTIONAL { pioasm.get_current_program(@1, ".side_set", true).set_sideset(@$, $2, true, false); } | SIDE_SET value PINDIRS { pioasm.get_current_program(@1, ".side_set", true).set_sideset(@$, $2, false, true); } | SIDE_SET value { pioasm.get_current_program(@1, ".side_set", true).set_sideset(@$, $2, false, false); } + | DOT_IN value direction autop threshold { pioasm.get_current_program(@1, ".out", true).set_in(@$, $2, $3, $4, $5); } + | DOT_OUT value direction autop threshold { pioasm.get_current_program(@1, ".out", true).set_out(@$, $2, $3, $4, $5); } + | DOT_SET value { pioasm.check_version(1, @$, ".in"); pioasm.get_current_program(@1, ".out", true).set_set_count(@$, $2); } | WRAP_TARGET { pioasm.get_current_program(@1, ".wrap_target").set_wrap_target(@$); } | WRAP { pioasm.get_current_program(@1, ".wrap").set_wrap(@$); } | WORD value { pioasm.get_current_program(@1, "instruction").add_instruction(std::shared_ptr(new instr_word(@$, $2))); } - | LANG_OPT NON_WS NON_WS EQUAL INT { pioasm.get_current_program(@1, ".lang_opt").add_lang_opt($2, $3, std::to_string($5)); } - | LANG_OPT NON_WS NON_WS EQUAL STRING { pioasm.get_current_program(@1, ".lang_opt").add_lang_opt($2, $3, $5); } - | LANG_OPT NON_WS NON_WS EQUAL NON_WS { pioasm.get_current_program(@1, ".lang_opt").add_lang_opt($2, $3, $5); } + | LANG_OPT NON_WS NON_WS ASSIGN INT { pioasm.get_current_program(@1, ".lang_opt").add_lang_opt($2, $3, std::to_string($5)); } + | LANG_OPT NON_WS NON_WS ASSIGN STRING { pioasm.get_current_program(@1, ".lang_opt").add_lang_opt($2, $3, $5); } + | LANG_OPT NON_WS NON_WS ASSIGN NON_WS { pioasm.get_current_program(@1, ".lang_opt").add_lang_opt($2, $3, $5); } | LANG_OPT error { error(@$, "expected format is .lang_opt language option_name = option_value"); } + | CLOCK_DIV INT { pioasm.get_current_program(@1, ".clock_div").set_clock_div(@$, $2); } + | CLOCK_DIV FLOAT { pioasm.get_current_program(@1, ".clock_div").set_clock_div(@$, $2); } + | FIFO fifo_config { pioasm.get_current_program(@1, ".fifo", true).set_fifo_config(@$, $2); } + | MOV_STATUS TXFIFO LESSTHAN value { pioasm.get_current_program(@1, ".mov_status", true).set_mov_status(mov_status_type::tx_lessthan, $4); } + | MOV_STATUS RXFIFO LESSTHAN value { pioasm.get_current_program(@1, ".mov_status", true).set_mov_status(mov_status_type::rx_lessthan, $4); } + | MOV_STATUS IRQ NEXT SET value { pioasm.get_current_program(@1, ".mov_status", true).set_mov_status(mov_status_type::irq_set, $5, 2); } + | MOV_STATUS IRQ PREV SET value { pioasm.get_current_program(@1, ".mov_status", true).set_mov_status(mov_status_type::irq_set, $5, 1); } + | MOV_STATUS IRQ SET value { pioasm.get_current_program(@1, ".mov_status", true).set_mov_status(mov_status_type::irq_set, $4); } + | MOV_STATUS { error(@0, "expected 'txfifo < N', 'rxfifo < N' or 'irq set N'"); } | UNKNOWN_DIRECTIVE { std::stringstream msg; msg << "unknown directive " << $1; throw syntax_error(@$, msg.str()); } ; @@ -191,9 +237,16 @@ expression: | expression OR expression { $$ = std::shared_ptr(new binary_operation(@$, binary_operation::or_, $1, $3)); } | expression AND expression { $$ = std::shared_ptr(new binary_operation(@$, binary_operation::and_, $1, $3)); } | expression XOR expression { $$ = std::shared_ptr(new binary_operation(@$, binary_operation::xor_, $1, $3)); } + | expression SHL expression { $$ = std::shared_ptr(new binary_operation(@$, binary_operation::shl_, $1, $3)); } + | expression SHR expression { $$ = std::shared_ptr(new binary_operation(@$, binary_operation::shr_, $1, $3)); } | MINUS expression { $$ = std::shared_ptr(new unary_operation(@$, unary_operation::negate, $2)); } | REVERSE expression { $$ = std::shared_ptr(new unary_operation(@$, unary_operation::reverse, $2)); } +%type pio_version; +pio_version: INT { $$ = $1; } + | RP2040 { $$ = 0; } + | RP2350 { $$ = 1; } + %type > instruction; instruction: base_instruction sideset delay { $$ = $1; $$->sideset = $2; $$->delay = $3; } @@ -207,14 +260,17 @@ base_instruction: NOP { $$ = std::shared_ptr(new instr_nop(@$)); } | JMP condition comma expression { $$ = std::shared_ptr(new instr_jmp(@$, $2, $4)); } | WAIT value wait_source { $$ = std::shared_ptr(new instr_wait(@$, $2, $3)); } - | WAIT value COMMA value { std::stringstream msg; location l; l.begin = @2.end; l.end = @3.end; msg << "expected irq, gpio or pin after the polarity value and before the \",\""; throw yy::parser::syntax_error(l, msg.str()); } | WAIT wait_source { $$ = std::shared_ptr(new instr_wait(@$, resolvable_int(@$, 1), $2)); } | IN in_source comma value { $$ = std::shared_ptr(new instr_in(@$, $2, $4)); } | OUT out_target comma value { $$ = std::shared_ptr(new instr_out(@$, $2, $4)); } | PUSH if_full blocking { $$ = std::shared_ptr(new instr_push(@$, $2, $3)); } | PULL if_empty blocking { $$ = std::shared_ptr(new instr_pull(@$, $2, $3)); } | MOV mov_target comma mov_op mov_source { $$ = std::shared_ptr(new instr_mov(@$, $2, $5, $4)); } - | IRQ irq_modifiers value REL { $$ = std::shared_ptr(new instr_irq(@$, $2, $3, true)); } + | IRQ irq_modifiers value REL { $$ = std::shared_ptr(new instr_irq(@$, $2, $3, 2)); } + | IRQ PREV irq_modifiers value { pioasm.check_version(1, @$, "irq prev"); $$ = std::shared_ptr(new instr_irq(@$, $3, $4, 1)); } + | IRQ NEXT irq_modifiers value { pioasm.check_version(1, @$, "irq next"); $$ = std::shared_ptr(new instr_irq(@$, $3, $4, 3)); } + | IRQ PREV irq_modifiers value REL { pioasm.check_version(1, @$, "irq prev"); error(@5, "'rel' is not supported for 'irq prev'"); } + | IRQ NEXT irq_modifiers value REL { pioasm.check_version(1, @$, "irq next"); error(@5, "'rel' is not supported for 'irq next'"); } | IRQ irq_modifiers value { $$ = std::shared_ptr(new instr_irq(@$, $2, $3)); } | SET set_target comma value { $$ = std::shared_ptr(new instr_set(@$, $2, $4)); } ; @@ -240,10 +296,27 @@ condition: %type > wait_source; wait_source: - IRQ comma value REL { $$ = std::shared_ptr(new wait_source(wait_source::irq, $3, true)); } - | IRQ comma value { $$ = std::shared_ptr(new wait_source(wait_source::irq, $3, false)); } + IRQ comma value REL { $$ = std::shared_ptr(new wait_source(wait_source::irq, $3, 2)); } + | IRQ PREV comma value { pioasm.check_version(1, @$, "irq prev"); $$ = std::shared_ptr(new wait_source(wait_source::irq, $4, 1)); } + | IRQ NEXT comma value { pioasm.check_version(1, @$, "irq next"); $$ = std::shared_ptr(new wait_source(wait_source::irq, $4, 3)); } + | IRQ PREV comma value REL { pioasm.check_version(1, @$, "irq prev"); error(@5, "'rel' is not supported for 'irq prev'"); } + | IRQ NEXT comma value REL { pioasm.check_version(1, @$, "irq next"); error(@5, "'rel' is not supported for 'irq next'"); } + | IRQ comma value { $$ = std::shared_ptr(new wait_source(wait_source::irq, $3, 0)); } | GPIO comma value { $$ = std::shared_ptr(new wait_source(wait_source::gpio, $3)); } | PIN comma value { $$ = std::shared_ptr(new wait_source(wait_source::pin, $3)); } + | JMPPIN { pioasm.check_version(1, @$, "wait jmppin"); $$ = std::shared_ptr(new wait_source(wait_source::jmppin, std::make_shared(@$, 0))); } + | JMPPIN PLUS value { pioasm.check_version(1, @$, "wait jmppin"); $$ = std::shared_ptr(new wait_source(wait_source::jmppin, $3)); } + | %empty { error(@0, pioasm.version_string(1, "expected irq, gpio, pin or jmp_pin", "expected irq, gpio or pin")); } + +%type fifo_config; +fifo_config: TXRX { $$ = fifo_config::txrx; } + | TX { $$ = fifo_config::tx; } + | RX { $$ = fifo_config::rx; } + | TXPUT { pioasm.check_version(1, @$, "txput"); $$ = fifo_config::txput; } + | TXGET { pioasm.check_version(1, @$, "rxput"); $$ = fifo_config::txget; } + | PUTGET { pioasm.check_version(1, @$, "putget"); $$ = fifo_config::putget; } + | %empty { error(@0, pioasm.version_string(1, "expected txrx, tx, rx, txput, rxget or putget", "expected txrx, tx or rx")); } + comma: COMMA | %empty /* not a huge fan of forcing commas */ @@ -266,7 +339,7 @@ out_target: PINS { $$ = in_out_set::in_out_set_pins; } | PC { $$ = in_out_set::out_set_pc; } | EXEC { $$ = in_out_set::out_exec; } -%type mov_target; +%type mov_target; mov_target: PINS { $$ = mov::pins; } | X { $$ = mov::x; } | Y { $$ = mov::y; } @@ -274,8 +347,11 @@ mov_target: PINS { $$ = mov::pins; } | PC { $$ = mov::pc; } | ISR { $$ = mov::isr; } | OSR { $$ = mov::osr; } + | PINDIRS { pioasm.check_version(1, @$, "mov pindirs"); $$ = mov::pindirs; } + | RXFIFO LBRACKET Y RBRACKET { pioasm.check_version(1, @$, "mov rxfifo[], "); $$ = mov::fifo_y; } + | RXFIFO LBRACKET value RBRACKET { pioasm.check_version(1, @$, "mov rxfifo[], "); $$ = extended_mov($3); } -%type mov_source; +%type mov_source; mov_source: PINS { $$ = mov::pins; } | X { $$ = mov::x; } | Y { $$ = mov::y; } @@ -283,6 +359,8 @@ mov_source: PINS { $$ = mov::pins; } | STATUS { $$ = mov::status; } | ISR { $$ = mov::isr; } | OSR { $$ = mov::osr; } + | RXFIFO LBRACKET Y RBRACKET { pioasm.check_version(1, @$, "mov rxfifo[], "); $$ = mov::fifo_y; } + | RXFIFO LBRACKET value RBRACKET { pioasm.check_version(1, @$, "mov rxfifo[], "); $$ = extended_mov($3); } %type mov_op; mov_op: @@ -297,6 +375,22 @@ set_target: | Y { $$ = in_out_set::in_out_set_y; } | PINDIRS { $$ = in_out_set::in_out_set_pindirs; } +%type direction; +direction: + LEFT { $$ = false; } + | RIGHT { $$ = true; } + | %empty { $$ = true; } + +%type autop; +autop: + AUTO { $$ = true; } + | MANUAL { $$ = false; } + | %empty { $$ = false; } + +%type > threshold; +threshold: value { $$ = $1; } + | %empty { $$ = resolvable_int(@$, 32); } + %type if_full; if_full: IFFULL { $$ = true; } @@ -350,4 +444,3 @@ void yy::parser::error(const location_type& l, const std::string& m) std::cerr << m << '\n'; } } - diff --git a/tools/pioasm/pio_assembler.cpp b/tools/pioasm/pio_assembler.cpp index 469d733a8..a427c22e4 100644 --- a/tools/pioasm/pio_assembler.cpp +++ b/tools/pioasm/pio_assembler.cpp @@ -48,10 +48,35 @@ void program::add_instruction(std::shared_ptr inst) { msg << "instruction requires 'side' to specify side set value for the instruction because non optional sideset was specified for the program at " << sideset.location; throw syntax_error(inst->location, msg.str()); } + inst->pre_validate(*this); instructions.push_back(inst); } -using syntax_error = yy::parser::syntax_error; +using syntax_error = syntax_error; + +void program::set_pio_version(const yy::location &l, int version) { + if (version < 0 || version > 1) { + throw syntax_error(l, "only PIO versions 0 (rp2040) and 1 (rp2350) are supported"); + } + pio_version = version; +} + +void program::set_clock_div(const yy::location &l, float clock_div) { + if (clock_div < 1.0f || clock_div >= 65536.0f) { + throw syntax_error(l, "clock divider must be between 1 and 65546"); + } + clock_div_int = (uint16_t)clock_div; + if (clock_div_int == 0) { + clock_div_frac = 0; + } else { + clock_div_frac = (uint8_t)((clock_div - (float)clock_div_frac) * (1u << 8u)); + } +} + +void program::set_fifo_config(const yy::location &l, fifo_config config) { + fifo_loc = l; + fifo = config; +} void program::add_symbol(std::shared_ptr symbol) { const auto &existing = pioasm->get_symbol(symbol->name, this); @@ -115,6 +140,10 @@ int binary_operation::resolve(pio_assembler *pioasm, const program *program, con return lvalue | rvalue; case xor_: return lvalue ^ rvalue; + case shl_: + return lvalue << rvalue; + case shr_: + return lvalue >> rvalue; default: throw syntax_error(location, "internal error"); } @@ -150,6 +179,33 @@ void program::add_lang_opt(std::string lang, std::string name, std::string value } void program::finalize() { + if (mov_status.type != mov_status_type::unspecified) { + uint n = mov_status.n->resolve(*this); + if (mov_status.type == mov_status_type::irq_set) { + if (n > 7) throw syntax_error(mov_status.n->location, "irq number should be >= 0 and <= 7"); + mov_status.final_n = mov_status.param * 8 + n; + } else { + if (n > 31) throw syntax_error(mov_status.n->location, "fido depth should be >= 0 and <= 31"); + mov_status.final_n = n; + } + } + if (in.pin_count) { + in.final_pin_count = in.pin_count->resolve(*this); + if (!pio_version && in.final_pin_count != 32) throw syntax_error(in.pin_count->location, "in pin count must be 32 for PIO version 0"); + if (in.final_pin_count < 1 || in.final_pin_count > 32) throw syntax_error(in.pin_count->location, "in pin count should be >= 1 and <= 32"); + in.final_threshold = in.threshold->resolve(*this); + if (in.final_threshold < 1 || in.final_threshold > 32) throw syntax_error(in.threshold->location, "threshold should be >= 1 and <= 32"); + } + if (out.pin_count) { + out.final_pin_count = out.pin_count->resolve(*this); + if (out.final_pin_count < 0 || out.final_pin_count > 32) throw syntax_error(out.pin_count->location, "out pin count should be >= 0 and <= 32"); + out.final_threshold = out.threshold->resolve(*this); + if (out.final_threshold < 1 || out.final_threshold > 32) throw syntax_error(out.threshold->location, "threshold should be >= 1 and <= 32"); + } + if (set_count.value) { + final_set_count = set_count.value->resolve(*this); + if (final_set_count < 0 || final_set_count > 5) throw syntax_error(set_count.location, "set pin count should be >= 0 and <= 5"); + } if (sideset.value) { int bits = sideset.value->resolve(*this); if (bits < 0) { @@ -169,6 +225,13 @@ void program::finalize() { sideset_max = 0; delay_max = 31; } + if (fifo != fifo_config::rx && fifo != fifo_config::tx && fifo != fifo_config::txrx) { + std::stringstream msg; + if (in.pin_count && in.autop) { + msg << "autopush is incompatible with your selected FIFO configuration specified at " << fifo_loc; + throw syntax_error(in.location, msg.str()); + } + } } int name_ref::resolve(pio_assembler *pioasm, const program *program, const resolvable &scope) { @@ -195,7 +258,7 @@ int name_ref::resolve(pio_assembler *pioasm, const program *program, const resol } } -uint instruction::encode(const program &program) { +uint instruction::encode(program &program) { raw_encoding raw = raw_encode(program); int _delay = delay->resolve(program); if (_delay < 0) { @@ -228,14 +291,15 @@ uint instruction::encode(const program &program) { _sideset |= 0x10u; } } - return (((uint) raw.type) << 13u) | (((uint) _delay | (uint) _sideset) << 8u) | (raw.arg1 << 5u) | raw.arg2; + // note we store the 6th bit of arg2 above the 16 bits of instruction + return (((uint) raw.type) << 13u) | (((uint) _delay | (uint) _sideset) << 8u) | (raw.arg1 << 5u) | raw.arg2 | ((raw.arg2 >> 5) << 16); } -raw_encoding instruction::raw_encode(const program &program) { +raw_encoding instruction::raw_encode(program& program) { throw syntax_error(location, "internal error"); } -uint instr_word::encode(const program &program) { +uint instr_word::encode(program &program) { uint value = encoding->resolve(program); if (value > 0xffffu) { throw syntax_error(location, ".word value must be a positive 16 bit value"); @@ -243,7 +307,55 @@ uint instr_word::encode(const program &program) { return value; } -raw_encoding instr_jmp::raw_encode(const program &program) { +uint instr_mov::get_push_get_index(const program &program, extended_mov index) { + if (index.loc == mov::fifo_y) { + return 0; + } else { + uint v = index.fifo_index->resolve(program); + if (v > 7) { + throw syntax_error(index.fifo_index->location, "FIFO index myst be between 0 and 7"); + } + return v | 8; + } +} + +void instr_push::pre_validate(program& program) { + if (program.fifo != fifo_config::rx && program.fifo != fifo_config::txrx) { + throw syntax_error(location, "FIFO must be configured for 'txrx' or 'rx' to use this instruction"); + } +} + +void instr_mov::pre_validate(program &program) { + if (dest.uses_fifo()) { + if (src.loc != mov::isr) { + throw syntax_error(location, "mov rxfifo[] source must be isr"); + } + if (program.fifo != fifo_config::txput && program.fifo != fifo_config::putget) { + throw syntax_error(location, "FIFO must be configured for 'txput' or 'putget' to use this instruction"); + } + } else if (src.uses_fifo()) { + if (dest.loc != mov::osr) { + throw syntax_error(location, "mov ,txfifo[] target must be osr"); + } + if (program.fifo != fifo_config::txget && program.fifo != fifo_config::putget) { + throw syntax_error(location, "FIFO must be configured for 'txget' or 'putget' to use this instruction"); + } + } +} + +raw_encoding instr_mov::raw_encode(program& program) { + if (!dest.uses_fifo() && !src.uses_fifo()) { + // regular mov + return {inst_type::mov, (uint) dest.loc, (uint) src.loc | ((uint) op << 3u)}; + } + if (dest.uses_fifo()) { + return {inst_type::push_pull, 0, 0x10 | get_push_get_index(program, dest) }; + } else { + return {inst_type::push_pull, 0x4, 0x10 | get_push_get_index(program, src) }; + } +} + +raw_encoding instr_jmp::raw_encode(program& program) { int dest = target->resolve(program); if (dest < 0) { throw syntax_error(target->location, "jmp target address must be positive"); @@ -255,7 +367,7 @@ raw_encoding instr_jmp::raw_encode(const program &program) { return {inst_type::jmp, (uint) cond, (uint) dest}; } -raw_encoding instr_in::raw_encode(const program &program) { +raw_encoding instr_in::raw_encode(program& program) { int v = value->resolve(program); if (v < 1 || v > 32) { throw syntax_error(value->location, "'in' bit count must be >= 1 and <= 32"); @@ -263,7 +375,7 @@ raw_encoding instr_in::raw_encode(const program &program) { return {inst_type::in, (uint) src, (uint) v & 0x1fu}; } -raw_encoding instr_out::raw_encode(const program &program) { +raw_encoding instr_out::raw_encode(program& program) { int v = value->resolve(program); if (v < 1 || v > 32) { throw syntax_error(value->location, "'out' bit count must be >= 1 and <= 32"); @@ -271,7 +383,7 @@ raw_encoding instr_out::raw_encode(const program &program) { return {inst_type::out, (uint) dest, (uint) v & 0x1fu}; } -raw_encoding instr_set::raw_encode(const program &program) { +raw_encoding instr_set::raw_encode(program& program) { int v = value->resolve(program); if (v < 0 || v > 31) { throw syntax_error(value->location, "'set' bit count must be >= 0 and <= 31"); @@ -279,7 +391,7 @@ raw_encoding instr_set::raw_encode(const program &program) { return {inst_type::set, (uint) dest, (uint) v}; } -raw_encoding instr_wait::raw_encode(const program &program) { +raw_encoding instr_wait::raw_encode(program& program) { uint pol = polarity->resolve(program); if (pol > 1) { throw syntax_error(polarity->location, "'wait' polarity must be 0 or 1"); @@ -289,21 +401,38 @@ raw_encoding instr_wait::raw_encode(const program &program) { case wait_source::irq: if (arg2 > 7) throw syntax_error(source->param->location, "irq number must be must be >= 0 and <= 7"); break; - case wait_source::gpio: - if (arg2 > 31) - throw syntax_error(source->param->location, "absolute GPIO number must be must be >= 0 and <= 31"); + case wait_source::gpio: { + if (!program.pio_version) { + if (arg2 > 31) + throw syntax_error(source->param->location, "absolute GPIO number must be must be >= 0 and <= 31"); + } else { + if (arg2 > 47) + throw syntax_error(source->param->location, "absolute GPIO number must be must be >= 0 and <= 47"); + } + int bitmap = 1u << (arg2 >> 4); + if (bitmap == 4 && program.used_gpio_ranges & 1) { + throw syntax_error(source->param->location, "absolute GPIO number must be must be >= 0 and <= 31 as a GPIO number <16 has already been used"); + } + if (bitmap == 1 && program.used_gpio_ranges & 4) { + throw syntax_error(source->param->location, "absolute GPIO number must be must be >= 16 and <= 47 as a GPIO number >32 has already been used"); + } + program.used_gpio_ranges |= bitmap; break; + } case wait_source::pin: - if (arg2 > 31) throw syntax_error(polarity->location, "pin number must be must be >= 0 and <= 31"); + if (arg2 > 31) throw syntax_error(source->param->location, "pin number must be must be >= 0 and <= 31"); + break; + case wait_source::jmppin: + if (arg2 > 3) throw syntax_error(source->param->location, "jmppin offset must be must be >= 0 and <= 3"); break; } - return {inst_type::wait, (pol << 2u) | (uint) source->target, arg2 | (source->flag ? 0x10u : 0u)}; + return {inst_type::wait, (pol << 2u) | (uint) source->target, arg2 | (source->irq_type << 3)}; } -raw_encoding instr_irq::raw_encode(const program &program) { +raw_encoding instr_irq::raw_encode(program& program) { uint arg2 = num->resolve(program); if (arg2 > 7) throw syntax_error(num->location, "irq number must be must be >= 0 and <= 7"); - if (relative) arg2 |= 0x10u; + arg2 |= irq_type << 3; return {inst_type::irq, (uint)modifiers, arg2}; } @@ -333,9 +462,9 @@ int pio_assembler::write_output() { source.global_symbols = public_symbols(get_dummy_global_program()); for (auto &program : programs) { program.finalize(); - source.programs.emplace_back(compiled_source::program(program.name)); + source.programs.emplace_back(program.name); auto &cprogram = source.programs[source.programs.size() - 1]; - cprogram = compiled_source::program(program.name); + cprogram.pio_version = program.pio_version; // encode the instructions std::transform(program.instructions.begin(), program.instructions.end(), @@ -358,8 +487,32 @@ int pio_assembler::write_output() { } if (program.wrap) cprogram.wrap = program.wrap->resolve(program); else cprogram.wrap = std::max((int)program.instructions.size() - 1, 0); - if (program.wrap_target) cprogram.wrap_target = program.wrap_target->resolve(program); else cprogram.wrap_target = 0; + cprogram.clock_div_int = program.clock_div_int; + cprogram.clock_div_frac = program.clock_div_frac; + if (program.wrap_target) { + cprogram.wrap_target = program.wrap_target->resolve(program); + if (cprogram.wrap_target >= program.instructions.size()) { + throw syntax_error(program.wrap_target->location, ".wrap_target cannot be placed after the last program instruction"); + } + } else { + cprogram.wrap_target = 0; + } if (program.origin.value) cprogram.origin = program.origin.value->resolve(program); + cprogram.mov_status_type = program.mov_status.type == mov_status_type::unspecified ? -1 : (int)program.mov_status.type; + cprogram.mov_status_n = program.mov_status.final_n; + cprogram.fifo = program.fifo; + cprogram.used_gpio_ranges = program.used_gpio_ranges; + auto in_out_convert = [](const in_out &io) { + return compiled_source::in_out{ + .pin_count = io.final_pin_count, + .right = io.right, + .autop = io.autop, + .threshold = io.final_threshold, + }; + }; + cprogram.in = in_out_convert(program.in); + cprogram.out = in_out_convert(program.out); + cprogram.set_count = program.final_set_count; if (program.sideset.value) { cprogram.sideset_bits_including_opt = program.sideset_bits_including_opt; cprogram.sideset_opt = program.sideset_opt; diff --git a/tools/pioasm/pio_assembler.h b/tools/pioasm/pio_assembler.h index 7183800d7..e537f8940 100644 --- a/tools/pioasm/pio_assembler.h +++ b/tools/pioasm/pio_assembler.h @@ -17,11 +17,11 @@ // ... and declare it for the parser's sake. YY_DECL; - struct pio_assembler { public: using syntax_error = yy::parser::syntax_error; using location_type = yy::parser::location_type; + using position = yy::position; std::shared_ptr dummy_global_program; std::vector programs; @@ -35,6 +35,7 @@ struct pio_assembler { // name of the output file or "-" for stdout std::string dest; std::vector options; + int default_pio_version = 0; int write_output(); @@ -42,6 +43,7 @@ struct pio_assembler { if (std::find_if(programs.begin(), programs.end(), [&](const program &p) { return p.name == name; }) == programs.end()) { programs.emplace_back(this, l, name); + programs[programs.size()-1].pio_version = get_default_pio_version(); return true; } else { return false; @@ -51,6 +53,7 @@ struct pio_assembler { program &get_dummy_global_program() { if (!dummy_global_program) { dummy_global_program = std::shared_ptr(new program(this, yy::location(&source), "")); + dummy_global_program->pio_version = default_pio_version; } return *dummy_global_program; } @@ -68,12 +71,24 @@ struct pio_assembler { auto &p = programs[programs.size() - 1]; if (before_any_instructions && !p.instructions.empty()) { std::stringstream msg; - msg << requiring_program << " must preceed any program instructions"; + msg << requiring_program << " must precede any program instructions"; throw syntax_error(l, msg.str()); } return p; } + int get_default_pio_version() { + return get_dummy_global_program().pio_version; + } + + int get_current_pio_version() { + if (!programs.empty()) { + auto &p = programs[programs.size() - 1]; + return p.pio_version; + } + return get_default_pio_version(); + } + // note p may be null for global symbols only std::shared_ptr get_symbol(const std::string &name, const program *p) { const auto &i = get_dummy_global_program().symbols.find(name); @@ -88,6 +103,18 @@ struct pio_assembler { return nullptr; } + void check_version(int min_version, const location_type &l, std::string feature) { + if (get_current_pio_version() < min_version) { + std::stringstream msg; + msg << "PIO version " << min_version << " is required for '" << feature << "'"; + throw syntax_error(l, msg.str()); + } + } + + std::string version_string(int min_version, std::string a, std::string b) { + return get_current_pio_version() >= min_version ? a : b; + } + std::vector public_symbols(program &program); int generate(std::shared_ptr _format, const std::string &_source, const std::string &_dest, const std::vector &_options = std::vector()); diff --git a/tools/pioasm/pio_disassembler.cpp b/tools/pioasm/pio_disassembler.cpp index c30fb0b66..eb1f4268c 100644 --- a/tools/pioasm/pio_disassembler.cpp +++ b/tools/pioasm/pio_disassembler.cpp @@ -9,15 +9,15 @@ #include #include "pio_disassembler.h" -extern "C" void disassemble(char *buf, int buf_len, uint16_t inst, uint sideset_bits, bool sideset_opt) { +extern "C" void disassemble(char *buf, int buf_len, uint inst, uint sideset_bits, bool sideset_opt) { if (buf_len) buf[disassemble(inst, sideset_bits, sideset_opt).copy(buf, buf_len - 1)] = 0; } -std::string disassemble(uint16_t inst, uint sideset_bits_including_opt, bool sideset_opt) { +std::string disassemble(uint inst, uint sideset_bits_including_opt, bool sideset_opt) { std::stringstream ss; - uint major = inst >> 13u; + uint major = (inst >> 13u) & 0x7; uint arg1 = ((uint) inst >> 5u) & 0x7u; - uint arg2 = inst & 0x1fu; + uint arg2 = (inst & 0x1fu) | ((inst & 0x10000) >> 11); auto op = [&](const std::string &s) { ss << std::left << std::setw(7) << s; }; @@ -45,13 +45,18 @@ std::string disassemble(uint16_t inst, uint sideset_bits_including_opt, bool sid guts = "pin, " + std::to_string(arg2); break; case 0b10: - if (arg2 & 0x8u) { + guts = "irq"; + if (arg2 & 0x08) { + guts += arg2 & 0x10 ? " next" : " prev"; + } + guts += ", " + std::to_string(arg2 & 7u); + if (0x10 == (arg2 & 0x18)) guts += " rel"; + break; + case 0b11: + if (arg2 & 0x1cu) { invalid = true; - } else { - guts = "irq, " + std::to_string(arg2 & 7u); - if (arg2 & 0x10u) { - guts += " rel"; - } + } else if (arg2) { + guts = "jmppin " + std::to_string(arg2 & 3u); } break; } @@ -81,7 +86,21 @@ std::string disassemble(uint16_t inst, uint sideset_bits_including_opt, bool sid } case 0b100: { if (arg2) { - invalid = true; + if ((arg1 & 3) || !(arg2 & 0x10)) { + invalid = true; + } else { + std::string index; + if (arg2 & 8) index = "y"; + else index = std::to_string(arg2 & 7); + std::string guts = ""; + op("mov"); + if (arg1 & 4) { + guts = "osr, rxfifo[" + index + "]"; + } else { + guts = "rxfifo[" + index + "], isr"; + } + op_guts(guts); + } } else { std::string guts = ""; if (arg1 & 4u) { @@ -97,7 +116,7 @@ std::string disassemble(uint16_t inst, uint sideset_bits_including_opt, bool sid break; } case 0b101: { - static std::array dests { "pins", "x", "y", "", "exec", "pc", "isr", "osr"}; + static std::array dests { "pins", "x", "y", "pindirs", "exec", "pc", "isr", "osr"}; static std::array sources { "pins", "x", "y", "null", "", "status", "isr", "osr"}; std::string dest = dests[arg1]; std::string source = sources[arg2 & 7u]; @@ -122,7 +141,7 @@ std::string disassemble(uint16_t inst, uint sideset_bits_including_opt, bool sid break; } case 0b110: { - if ((arg1 & 0x4u) || (arg2 & 0x8u)) { + if ((arg1 & 0x4u)) { invalid = true; } else { op("irq"); @@ -135,8 +154,16 @@ std::string disassemble(uint16_t inst, uint sideset_bits_including_opt, bool sid guts += "nowait "; } guts += std::to_string(arg2 & 7u); - if (arg2 & 0x10u) { - guts += " rel"; + switch(arg2 & 0x18) { + case 0x10: + guts += " rel"; + break; + case 0x08: + guts = "prev "+guts; + break; + case 0x18: + guts = "next "+guts; + break; } op_guts(guts); } diff --git a/tools/pioasm/pio_disassembler.h b/tools/pioasm/pio_disassembler.h index 652e89465..e1b77ca34 100644 --- a/tools/pioasm/pio_disassembler.h +++ b/tools/pioasm/pio_disassembler.h @@ -11,11 +11,12 @@ #include #include +#include "pio_types.h" typedef unsigned int uint; -std::string disassemble(uint16_t inst, uint sideset_bits, bool sideset_opt); -extern "C" void disassemble(char *buf, int buf_len, uint16_t inst, uint sideset_bits, bool sideset_opt); +std::string disassemble(uint inst, uint sideset_bits, bool sideset_opt); +extern "C" void disassemble(char *buf, int buf_len, uint inst, uint sideset_bits, bool sideset_opt); #else void disassemble(char *buf, int buf_len, uint inst, uint sideset_bits, bool sideset_opt); #endif diff --git a/tools/pioasm/pio_enums.h b/tools/pioasm/pio_enums.h new file mode 100644 index 000000000..ef5a4737e --- /dev/null +++ b/tools/pioasm/pio_enums.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIO_ENUMS_H +#define _PIO_ENUMS_H + +typedef unsigned int uint; + +enum struct fifo_config { + txrx = 0, + tx = 1, + rx = 2, + txget = 3, + txput = 4, + putget = 5, +}; + +#endif \ No newline at end of file diff --git a/tools/pioasm/pio_types.h b/tools/pioasm/pio_types.h index d26284964..9f9fb0e3e 100644 --- a/tools/pioasm/pio_types.h +++ b/tools/pioasm/pio_types.h @@ -15,8 +15,34 @@ #include #include "location.h" +#include "pio_enums.h" -typedef unsigned int uint; +struct src_item { + yy::location location; + + src_item() = default; + + explicit src_item(const yy::location &location) : location(location) {} +}; + +struct program; +struct pio_assembler; + +struct resolvable : public src_item { + resolvable(const yy::location &l) : src_item(l) {} + + int resolve(const program &program); + + int resolve(pio_assembler *pioasm, const program *program) { + return resolve(pioasm, program, *this); + } + + virtual int resolve(pio_assembler *pioasm, const program *program, const resolvable &scope) = 0; + + virtual ~resolvable() = default; +}; + +using rvalue = std::shared_ptr; enum struct inst_type { jmp = 0x0, @@ -67,54 +93,51 @@ enum struct mov { x = 0x1, y = 0x2, null = 0x3, + pindirs = 0x3, exec = 0x4, pc = 0x5, status = 0x5, isr = 0x6, osr = 0x7, + fifo_y = 0x8, + fifo_index = 0x9, }; -enum struct mov_op { - none = 0x0, - invert = 0x1, - bit_reverse = 0x2, +enum struct mov_status_type { + unspecified = -1, + tx_lessthan = 0, + rx_lessthan = 1, + irq_set = 2, }; -struct src_item { - yy::location location; +struct extended_mov { + mov loc; + rvalue fifo_index; - src_item() = default; + extended_mov() : loc(mov::pindirs), fifo_index(nullptr) {} + extended_mov(mov _type) : loc(_type), fifo_index(nullptr) {} + extended_mov(rvalue _fifo_index) : loc(mov::fifo_index), fifo_index(_fifo_index) {} - explicit src_item(const yy::location &location) : location(location) {} + bool uses_fifo(void) const { return loc == mov::fifo_index || loc == mov::fifo_y; } }; -struct program; -struct pio_assembler; - -struct resolvable : public src_item { - resolvable(const yy::location &l) : src_item(l) {} - - int resolve(const program &program); - - int resolve(pio_assembler *pioasm, const program *program) { - return resolve(pioasm, program, *this); - } - - virtual int resolve(pio_assembler *pioasm, const program *program, const resolvable &scope) = 0; +enum struct mov_op { + none = 0x0, + invert = 0x1, + bit_reverse = 0x2, }; -using rvalue = std::shared_ptr; - struct wait_source { enum type { gpio = 0x0, pin = 0x1, - irq = 0x2 + irq = 0x2, + jmppin = 0x3, } target; rvalue param; - bool flag; + int irq_type; - wait_source(type target, rvalue param, bool flag = false) : target(target), param(std::move(param)), flag(flag) {} + wait_source(type target, rvalue param = 0, int irq_type = 0) : target(target), param(std::move(param)), irq_type(irq_type) {} }; struct name_ref : public resolvable { @@ -159,7 +182,9 @@ struct binary_operation : public resolvable { divide, and_, // pesky C++ or_, - xor_ + xor_, + shl_, + shr_ }; op_type op; @@ -210,9 +235,12 @@ struct instruction : public src_item { instruction(const yy::location &l) : src_item(l) {} - virtual uint encode(const program &program); + // validate while adding instruciton + virtual void pre_validate(program &program) {} - virtual raw_encoding raw_encode(const program &program); + virtual uint encode(program &program); + + virtual raw_encoding raw_encode(program &program); }; struct pio_assembler; @@ -227,6 +255,16 @@ struct rvalue_loc { rvalue_loc(const rvalue &v, const yy::location &l) : value(v), location(l) {} }; +struct in_out { + yy::location location; + rvalue pin_count; + bool right; + bool autop; + rvalue threshold; + int final_pin_count = -1; // not specified + int final_threshold; +}; + struct program : public src_item { static const int MAX_INSTRUCTIONS = 32; @@ -234,22 +272,42 @@ struct program : public src_item { std::string name; rvalue_loc origin; rvalue_loc sideset; + rvalue_loc set_count; + in_out in; + in_out out; bool sideset_opt; bool sideset_pindirs; rvalue wrap_target; rvalue wrap; + int pio_version = 0; + uint clock_div_int = 1; + uint clock_div_frac = 0; + yy::location fifo_loc; + fifo_config fifo = fifo_config::txrx; + // 1 bit of bitmap per 16 pins used + uint8_t used_gpio_ranges = 0; + std::map> symbols; std::vector> ordered_symbols; std::vector> instructions; std::map> code_blocks; std::map>> lang_opts; + struct { + mov_status_type type = mov_status_type::unspecified; + rvalue n; + int param; + int final_n; // post finalization + } mov_status; // post finalization int delay_max; int sideset_bits_including_opt; // specified side set bits + 1 if we need presence flag int sideset_max; + int final_set_count = -1; + int final_out_count = -1; + int final_in_count = -1; program(pio_assembler *pioasm, const yy::location &l, std::string name) : src_item(l), pioasm(pioasm), name(std::move(name)), sideset_opt(true), sideset_pindirs(false) {} @@ -268,6 +326,26 @@ struct program : public src_item { sideset_pindirs = pindirs; } + void set_out(const yy::location &l, rvalue v, bool right, bool autop, rvalue threshold) { + out.location = l; + out.pin_count = std::move(v); + out.right = right; + out.autop = autop; + out.threshold = threshold; + } + + void set_in(const yy::location &l, rvalue v, bool right, bool autop, rvalue threshold) { + in.location = l; + in.pin_count = std::move(v); + in.right = right; + in.autop = autop; + in.threshold = threshold; + } + + void set_set_count(const yy::location &l, rvalue v) { + set_count = rvalue_loc(v, l); + } + void add_label(std::shared_ptr label) { label->value = resolvable_int(label->location, instructions.size()); add_symbol(label); @@ -280,7 +358,22 @@ struct program : public src_item { void add_code_block(const code_block &block); void add_lang_opt(std::string lang, std::string name, std::string value); + + void set_pio_version(const yy::location &l, int version); + + void set_clock_div(const yy::location &l, float clock_div); + + void set_fifo_config(const yy::location &l, fifo_config config); + + void set_mov_status(mov_status_type type, rvalue n, int param = 0) { + mov_status.type = type; + mov_status.n = n; + mov_status.param = param; + } + void finalize(); +protected: + void init_pio_version(); }; struct instr_jmp : public instruction { @@ -289,7 +382,7 @@ struct instr_jmp : public instruction { instr_jmp(const yy::location &l, condition c, rvalue target) : instruction(l), cond(c), target(std::move(target)) { } - raw_encoding raw_encode(const program &program) override; + raw_encoding raw_encode(program &program) override; }; struct instr_wait : public instruction { @@ -299,7 +392,7 @@ struct instr_wait : public instruction { instr_wait(const yy::location &l, rvalue polarity, std::shared_ptr source) : instruction(l), polarity( std::move(polarity)), source(std::move(source)) {} - raw_encoding raw_encode(const program &program) override; + raw_encoding raw_encode(program &program) override; }; struct instr_in : public instruction { @@ -309,7 +402,7 @@ struct instr_in : public instruction { instr_in(const yy::location &l, const enum in_out_set &src, rvalue value) : instruction(l), src(src), value(std::move(value)) {} - raw_encoding raw_encode(const program &program) override; + raw_encoding raw_encode(program &program) override; }; struct instr_out : public instruction { @@ -319,7 +412,7 @@ struct instr_out : public instruction { instr_out(const yy::location &l, const enum in_out_set &dest, rvalue value) : instruction(l), dest(dest), value(std::move(value)) {} - raw_encoding raw_encode(const program &program) override; + raw_encoding raw_encode(program &program) override; }; struct instr_set : public instruction { @@ -329,7 +422,7 @@ struct instr_set : public instruction { instr_set(const yy::location &l, const enum in_out_set &dest, rvalue value) : instruction(l), dest(dest), value(std::move(value)) {} - raw_encoding raw_encode(const program &program) override; + raw_encoding raw_encode(program &program) override; }; @@ -339,7 +432,9 @@ struct instr_push : public instruction { instr_push(const yy::location &l, bool if_full, bool blocking) : instruction(l), if_full(if_full), blocking(blocking) {} - raw_encoding raw_encode(const program &program) override { + + void pre_validate(program& program) override; + raw_encoding raw_encode(program &program) override { uint arg1 = (blocking ? 1u : 0u) | (if_full ? 0x2u : 0); return {inst_type::push_pull, arg1, 0}; } @@ -351,33 +446,33 @@ struct instr_pull : public instruction { instr_pull(const yy::location &l, bool if_empty, bool blocking) : instruction(l), if_empty(if_empty), blocking(blocking) {} - raw_encoding raw_encode(const program &program) override { + raw_encoding raw_encode(program &program) override { uint arg1 = (blocking ? 1u : 0u) | (if_empty ? 0x2u : 0) | 0x4u; return {inst_type::push_pull, arg1, 0}; } }; struct instr_mov : public instruction { - enum mov dest, src; + extended_mov dest, src; mov_op op; - instr_mov(const yy::location &l, const enum mov &dest, const enum mov &src, const mov_op& op = mov_op::none) : + instr_mov(const yy::location &l, const extended_mov &dest, const extended_mov &src, const mov_op& op = mov_op::none) : instruction(l), dest(dest), src(src), op(op) {} - raw_encoding raw_encode(const program &program) override { - return {inst_type::mov, (uint) dest, (uint)src | ((uint)op << 3u)}; - } + uint get_push_get_index(const program &program, extended_mov index); + void pre_validate(program& program) override; + raw_encoding raw_encode(program &program) override; }; struct instr_irq : public instruction { enum irq modifiers; rvalue num; - bool relative; + int irq_type; - instr_irq(const yy::location &l, const enum irq &modifiers, rvalue num, bool relative = false) : - instruction(l), modifiers(modifiers), num(std::move(num)), relative(relative) {} + instr_irq(const yy::location &l, const enum irq &modifiers, rvalue num, int irq_type = 0) : + instruction(l), modifiers(modifiers), num(std::move(num)), irq_type(irq_type) {} - raw_encoding raw_encode(const program &program) override; + raw_encoding raw_encode(program &program) override; }; @@ -390,7 +485,7 @@ struct instr_word : public instruction { instr_word(const yy::location &l, rvalue encoding) : instruction(l), encoding(std::move(encoding)) {} - uint encode(const program &program) override; + uint encode(program &program) override; }; -#endif \ No newline at end of file +#endif diff --git a/tools/pioasm/python_output.cpp b/tools/pioasm/python_output.cpp index 32a50bb28..bcaa8d610 100644 --- a/tools/pioasm/python_output.cpp +++ b/tools/pioasm/python_output.cpp @@ -97,7 +97,7 @@ struct python_output : public output_format { std::map jmp_labels; // for now just use numeric labels for (int i = 0; i < (int)program.instructions.size(); i++) { - const auto &inst = program.instructions[i]; + const auto &inst = (uint16_t)program.instructions[i]; if (!(inst >> 13u)) { // a jump uint target = inst &0x1fu; @@ -105,9 +105,9 @@ struct python_output : public output_format { } } - for (uint i = 0; i < (int)program.instructions.size(); i++) { + for (uint i = 0; i < (uint)program.instructions.size(); i++) { const auto &inst = program.instructions[i]; - if (i == program.wrap_target) { + if (i == (uint)program.wrap_target) { fprintf(out, " wrap_target()\n"); } auto it = jmp_labels.find(i); @@ -115,7 +115,7 @@ struct python_output : public output_format { fprintf(out, " label(\"%s\")\n", it->second.c_str()); } fprintf(out, " %s # %d\n", disassemble(jmp_labels, inst, program.sideset_bits_including_opt.get(), program.sideset_opt).c_str(), i); - if (i == program.wrap) { + if (i == (uint)program.wrap) { fprintf(out, " wrap()\n"); } } @@ -151,11 +151,11 @@ struct python_output : public output_format { return 0; } - static std::string disassemble(const std::map& jmp_labels, uint16_t inst, uint sideset_bits_including_opt, bool sideset_opt) { + static std::string disassemble(const std::map& jmp_labels, uint inst, uint sideset_bits_including_opt, bool sideset_opt) { std::stringstream ss; - uint major = inst >> 13u; + uint major = (inst >> 13u) & 0x7; uint arg1 = ((uint) inst >> 5u) & 0x7u; - uint arg2 = inst & 0x1fu; + uint arg2 = (inst & 0x1fu) | ((inst & 0x10000) >> 11); std::string op_string; auto op = [&](const std::string &s) { op_string = s; diff --git a/tools/pioasm/test/amethyst.pio b/tools/pioasm/test/amethyst.pio new file mode 100644 index 000000000..97422a22b --- /dev/null +++ b/tools/pioasm/test/amethyst.pio @@ -0,0 +1,46 @@ +.pio_version rp2350 +.pio_version ONE + +.pio_version 0 + +.program bar +.fifo tx + +.program foo +.pio_version 1 +.clock_div 3.6 +//wait fling +.fifo putget +.out 3 auto +wait jmppin +wait 0 jmppin + 3 +mov pindirs, null +set pins, 3 +irq 3 rel +irq next 3 +irq prev 3 +set pins, (1 << 3) +//irq prev 3 rel +wait 1 irq 2 rel +wait 1 irq next 2 +wait 1 irq prev 4 +.define flan 1 +mov osr, rxfifo[flan] +mov rxfifo[y], isr + +//wait 0 jmppin + 4 + +.program wibble +.pio_version 0 +wait gpio 23 +wait gpio 7 + +.program wibble2 +.pio_version 1 +wait gpio 23 +wait gpio 40 + +.program wibble3 +.pio_version 1 +.mov_status txfifo < 12 +.mov_status irq next set 3 diff --git a/tools/run_all_bazel_checks.py b/tools/run_all_bazel_checks.py new file mode 100755 index 000000000..dfdc24633 --- /dev/null +++ b/tools/run_all_bazel_checks.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python3 +# +# Copyright (c) 2024 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# Runs all Bazel checks. + +import sys + +from bazel_build import build_all_configurations +from bazel_common import setup_logging, print_framed_string, parse_common_args +from compare_build_systems import compare_build_systems +from check_source_files_in_bazel_build import check_sources_in_bazel_build + + +def main(): + setup_logging() + failed_steps = [] + + args = parse_common_args() + + steps = ( + { + "description": "Bazel build", + "action": lambda : build_all_configurations(args.picotool_dir), + }, + { + "description": "Ensure build system configurations options match", + "action": compare_build_systems, + }, + { + "description": "Ensure source files are present in Bazel build", + "action": lambda : check_sources_in_bazel_build(args.picotool_dir), + }, + ) + + for step in steps: + print_framed_string(f"{step['description']}...") + returncode = step["action"]() + if returncode != 0: + failed_steps.append(step["description"]) + print() + + if failed_steps: + print_framed_string("ERROR: One or more steps failed.") + for build in failed_steps: + print(f" * FAILED: {build}") + return 1 + + print_framed_string("All checks successfully passed!") + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/tools/uf2_aspect.bzl b/tools/uf2_aspect.bzl index 961fcbce7..a1df382f4 100644 --- a/tools/uf2_aspect.bzl +++ b/tools/uf2_aspect.bzl @@ -17,9 +17,14 @@ def _pico_uf2_aspect_impl(target, ctx): ctx.actions.run( outputs = [uf2_output], inputs = [binary_to_convert], - tools = [ctx.executable._elf2uf2_tool], - executable = ctx.executable._elf2uf2_tool, + tools = [ctx.executable._picotool], + executable = ctx.executable._picotool, arguments = [ + "uf2", + "convert", + "--quiet", + "-t", + "elf", binary_to_convert.path, uf2_output.path, ], @@ -29,7 +34,6 @@ def _pico_uf2_aspect_impl(target, ctx): pico_uf2_files = depset([uf2_output]), ), ] - return [] pico_uf2_aspect = aspect( implementation = _pico_uf2_aspect_impl, @@ -58,6 +62,6 @@ will only be produced when you explicitly use your custom macro. default = _SUPPORTED_BINARY_TYPES, doc = "A comma-separated list of rule kinds to apply the UF2 aspect to", ), - "_elf2uf2_tool": attr.label(default = "//tools/elf2uf2:elf2uf2", executable = True, cfg = "exec"), + "_picotool": attr.label(default = "@picotool//:picotool", executable = True, cfg = "exec"), }, )